| FULL RUN LOG: |
| Executing Step 0 of 9: Extracting GDS Files |
| Step 0 done without fatal errors. |
| Executing Step 1 of 9: Project License Check |
| {{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root |
| SPDX COMPLIANCE Found 69 non-compliant files with the SPDX Standard. Check full log for more information |
| SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/phardytx/Work/mpw2/README.md', '/home/phardytx/Work/mpw2/verilog/rtl/sky130_hilas_TopLevelProtectStructure.v', '/home/phardytx/Work/mpw2/xschem/example_por.sch', '/home/phardytx/Work/mpw2/xschem/test.data', '/home/phardytx/Work/mpw2/xschem/example_por.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_Trans4small.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_TopProtection.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_WTA4Stage01.sch', '/home/phardytx/Work/mpw2/xschem/user_analog_project_wrapper.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_Trans2med.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_DAC5bit01.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_Tgate4Single01.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_pFETLarge.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_drainSelect01.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_TopLevelTestStructure.sch', '/home/phardytx/Work/mpw2/xschem/analog_wrapper_tb.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_nFETLarge.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_pFETLarge.sch'] |
| Executing Step 2 of 9: YAML File Check |
| YAML file valid! |
| Step 2 done without fatal errors. |
| Detected Project Type is "analog" |
| Executing Step 3 of 9: Project Compliance Checks |
| b'Going into /home/phardytx/Work/mpw2/caravel' |
| b'Removing manifest' |
| b'Fetching manifest' |
| b'Running sha1sum checks' |
| Manifest Checks Failed. Please rebase your Repository to the latest Caravel master. |
| verilog/rtl/DFFRAM.v: FAILED open or read |
| verilog/rtl/DFFRAMBB.v: FAILED open or read |
| verilog/rtl/__uprj_analog_netlists.v: FAILED open or read |
| verilog/rtl/__uprj_netlists.v: FAILED open or read |
| verilog/rtl/__user_analog_project_wrapper.v: FAILED open or read |
| verilog/rtl/__user_project_wrapper.v: FAILED open or read |
| verilog/rtl/caravan.v: FAILED open or read |
| verilog/rtl/caravan_netlists.v: FAILED open or read |
| verilog/rtl/caravel.v: FAILED open or read |
| verilog/rtl/caravel_clocking.v: FAILED open or read |
| verilog/rtl/chip_io.v: FAILED open or read |
| verilog/rtl/chip_io_alt.v: FAILED open or read |
| verilog/rtl/clock_div.v: FAILED open or read |
| verilog/rtl/convert_gpio_sigs.v: FAILED open or read |
| verilog/rtl/counter_timer_high.v: FAILED open or read |
| verilog/rtl/counter_timer_low.v: FAILED open or read |
| verilog/rtl/digital_pll.v: FAILED open or read |
| verilog/rtl/digital_pll_controller.v: FAILED open or read |
| verilog/rtl/gpio_control_block.v: FAILED open or read |
| verilog/rtl/gpio_wb.v: FAILED open or read |
| verilog/rtl/housekeeping_spi.v: FAILED open or read |
| verilog/rtl/la_wb.v: FAILED open or read |
| verilog/rtl/mem_wb.v: FAILED open or read |
| verilog/rtl/mgmt_core.v: FAILED open or read |
| verilog/rtl/mgmt_protect.v: FAILED open or read |
| verilog/rtl/mgmt_protect_hv.v: FAILED open or read |
| verilog/rtl/mgmt_soc.v: FAILED open or read |
| verilog/rtl/mprj2_logic_high.v: FAILED open or read |
| verilog/rtl/mprj_ctrl.v: FAILED open or read |
| verilog/rtl/mprj_io.v: FAILED open or read |
| verilog/rtl/mprj_logic_high.v: FAILED open or read |
| verilog/rtl/pads.v: FAILED open or read |
| verilog/rtl/picorv32.v: FAILED open or read |
| verilog/rtl/ring_osc2x13.v: FAILED open or read |
| verilog/rtl/simple_por.v: FAILED open or read |
| verilog/rtl/simple_spi_master.v: FAILED open or read |
| verilog/rtl/simpleuart.v: FAILED open or read |
| verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v: FAILED open or read |
| verilog/rtl/spimemio.v: FAILED open or read |
| verilog/rtl/sram_1rw1r_32_256_8_sky130.v: FAILED open or read |
| verilog/rtl/storage.v: FAILED open or read |
| verilog/rtl/storage_bridge_wb.v: FAILED open or read |
| verilog/rtl/sysctrl.v: FAILED open or read |
| verilog/rtl/wb_intercon.v: FAILED open or read |
| scripts/set_user_id.py: FAILED open or read |
| scripts/generate_fill.py: FAILED open or read |
| scripts/compositor.py: FAILED open or read |
| Makefile Checks Passed. |
| Default config checks failed because: |
| The parameter organization_url in info.yaml is default |
| The parameter owner in info.yaml is default |
| Default Content checks failed because: |
| user_analog_project_wrapper.gds file is identical to default caravel_user_project file user_analog_project_wrapper.gds |
| Documentation Checks Passed. |
| Executing Step 4 of 9: Fuzzy Consistency Checks |
| Consistency Checks Failed+ Reason: Verilog file /home/phardytx/Work/mpw2/caravel/verilog/gl/caravan.v not found |
| Executing Step 5 of 9: XOR Consistency Checks |
| Running XOR Checks... |
| XOR Checks on GDS Failed, Reason: Either you didn't mount the docker, or you ran out of RAM. Otherwise, magic is broken and it segfaulted. Please check: /home/phardytx/Work/mpw2/checks/magic_xor.log |
| TEST FAILED AT STEP 5 |
| Executing Step 6 of 9: DRC Violations Checks |
| Running Magic DRC Checks... |
| DRC Checks on User Project GDS Passed! |
| Step 6 done without fatal errors. |
| Executing Step 7 of 9: KLayout DRC Violations Check |
| Running Klayout DRC Checks... |
| Klayout DRC Checks on User Project GDS Passed! |
| Step 7 done without fatal errors. |
| Executing Klayout offgrid check. |
| Klayout offgrid Checks on User Project GDS Passed! |
| Step 8 done without fatal errors. |
| Klayout metal minimum clear area density Checks on User Project GDS Passed! |
| Step 8 done without fatal errors. |
| SOME Checks FAILED !!! |