copying entire /mag/ /gds/ and /verilog/ from PDK
diff --git a/gds/m12m3.gds b/gds/m12m3.gds
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Binary files differ
diff --git a/gds/sky130_hilas_nMirror03.gds b/gds/sky130_hilas_nMirror03.gds
new file mode 100644
index 0000000..7d59adb
--- /dev/null
+++ b/gds/sky130_hilas_nMirror03.gds
Binary files differ
diff --git a/gds/sky130_hilas_nOverlapCap01.gds b/gds/sky130_hilas_nOverlapCap01.gds
new file mode 100644
index 0000000..fe6a00d
--- /dev/null
+++ b/gds/sky130_hilas_nOverlapCap01.gds
Binary files differ
diff --git a/gds/sky130_hilas_overlapCap01.gds b/gds/sky130_hilas_overlapCap01.gds
new file mode 100644
index 0000000..f108198
--- /dev/null
+++ b/gds/sky130_hilas_overlapCap01.gds
Binary files differ
diff --git a/gds/sky130_hilas_overlapCap02.gds b/gds/sky130_hilas_overlapCap02.gds
new file mode 100644
index 0000000..d4e634a
--- /dev/null
+++ b/gds/sky130_hilas_overlapCap02.gds
Binary files differ
diff --git a/gds/sky130_hilas_overlapCap02a.gds b/gds/sky130_hilas_overlapCap02a.gds
new file mode 100644
index 0000000..89a7471
--- /dev/null
+++ b/gds/sky130_hilas_overlapCap02a.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETLarge.gds b/gds/sky130_hilas_pFETLarge.gds
new file mode 100644
index 0000000..bd7c73d
--- /dev/null
+++ b/gds/sky130_hilas_pFETLarge.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETLargePart1.gds b/gds/sky130_hilas_pFETLargePart1.gds
new file mode 100644
index 0000000..ce9d523
--- /dev/null
+++ b/gds/sky130_hilas_pFETLargePart1.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETdevice01.gds b/gds/sky130_hilas_pFETdevice01.gds
new file mode 100644
index 0000000..b1a89bc
--- /dev/null
+++ b/gds/sky130_hilas_pFETdevice01.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETdevice01a.gds b/gds/sky130_hilas_pFETdevice01a.gds
new file mode 100644
index 0000000..d5474f4
--- /dev/null
+++ b/gds/sky130_hilas_pFETdevice01a.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETdevice01aa.gds b/gds/sky130_hilas_pFETdevice01aa.gds
new file mode 100644
index 0000000..ecf4b13
--- /dev/null
+++ b/gds/sky130_hilas_pFETdevice01aa.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETdevice01b.gds b/gds/sky130_hilas_pFETdevice01b.gds
new file mode 100644
index 0000000..fa178f9
--- /dev/null
+++ b/gds/sky130_hilas_pFETdevice01b.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETdevice01ba.gds b/gds/sky130_hilas_pFETdevice01ba.gds
new file mode 100644
index 0000000..c6b9d2e
--- /dev/null
+++ b/gds/sky130_hilas_pFETdevice01ba.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETdevice01c.gds b/gds/sky130_hilas_pFETdevice01c.gds
new file mode 100644
index 0000000..119c7fe
--- /dev/null
+++ b/gds/sky130_hilas_pFETdevice01c.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETdevice01d.gds b/gds/sky130_hilas_pFETdevice01d.gds
new file mode 100644
index 0000000..4f198b0
--- /dev/null
+++ b/gds/sky130_hilas_pFETdevice01d.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETdevice01e.gds b/gds/sky130_hilas_pFETdevice01e.gds
new file mode 100644
index 0000000..5cd6008
--- /dev/null
+++ b/gds/sky130_hilas_pFETdevice01e.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETmed.gds b/gds/sky130_hilas_pFETmed.gds
new file mode 100644
index 0000000..fa80bd9
--- /dev/null
+++ b/gds/sky130_hilas_pFETmed.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETmirror.gds b/gds/sky130_hilas_pFETmirror.gds
new file mode 100644
index 0000000..bb91a8e
--- /dev/null
+++ b/gds/sky130_hilas_pFETmirror.gds
Binary files differ
diff --git a/gds/sky130_hilas_pFETmirror02.gds b/gds/sky130_hilas_pFETmirror02.gds
new file mode 100644
index 0000000..50df45d
--- /dev/null
+++ b/gds/sky130_hilas_pFETmirror02.gds
Binary files differ
diff --git a/gds/sky130_hilas_pTransistorPair.gds b/gds/sky130_hilas_pTransistorPair.gds
new file mode 100644
index 0000000..bf3ff99
--- /dev/null
+++ b/gds/sky130_hilas_pTransistorPair.gds
Binary files differ
diff --git a/gds/sky130_hilas_pTransistorVert01.gds b/gds/sky130_hilas_pTransistorVert01.gds
new file mode 100644
index 0000000..268aa6a
--- /dev/null
+++ b/gds/sky130_hilas_pTransistorVert01.gds
Binary files differ
diff --git a/gds/sky130_hilas_poly2li.gds b/gds/sky130_hilas_poly2li.gds
new file mode 100644
index 0000000..5876630
--- /dev/null
+++ b/gds/sky130_hilas_poly2li.gds
Binary files differ
diff --git a/gds/sky130_hilas_poly2m1.gds b/gds/sky130_hilas_poly2m1.gds
new file mode 100644
index 0000000..ec64ca5
--- /dev/null
+++ b/gds/sky130_hilas_poly2m1.gds
Binary files differ
diff --git a/gds/sky130_hilas_poly2m2.gds b/gds/sky130_hilas_poly2m2.gds
new file mode 100644
index 0000000..57bbcbc
--- /dev/null
+++ b/gds/sky130_hilas_poly2m2.gds
Binary files differ
diff --git a/gds/sky130_hilas_polyresistorGND.gds b/gds/sky130_hilas_polyresistorGND.gds
new file mode 100644
index 0000000..d9d4979
--- /dev/null
+++ b/gds/sky130_hilas_polyresistorGND.gds
Binary files differ
diff --git a/gds/sky130_hilas_resistor01.gds b/gds/sky130_hilas_resistor01.gds
new file mode 100644
index 0000000..ac1cdcc
--- /dev/null
+++ b/gds/sky130_hilas_resistor01.gds
Binary files differ
diff --git a/gds/sky130_hilas_swc2x2varactor.gds b/gds/sky130_hilas_swc2x2varactor.gds
new file mode 100644
index 0000000..8fc02d6
--- /dev/null
+++ b/gds/sky130_hilas_swc2x2varactor.gds
Binary files differ
diff --git a/gds/sky130_hilas_swc4x1BiasCell.gds b/gds/sky130_hilas_swc4x1BiasCell.gds
new file mode 100644
index 0000000..035b7ad
--- /dev/null
+++ b/gds/sky130_hilas_swc4x1BiasCell.gds
Binary files differ
diff --git a/gds/sky130_hilas_swc4x1cellOverlap.gds b/gds/sky130_hilas_swc4x1cellOverlap.gds
new file mode 100644
index 0000000..35aeac9
--- /dev/null
+++ b/gds/sky130_hilas_swc4x1cellOverlap.gds
Binary files differ
diff --git a/gds/sky130_hilas_swc4x1cellOverlap2.gds b/gds/sky130_hilas_swc4x1cellOverlap2.gds
new file mode 100644
index 0000000..e561f68
--- /dev/null
+++ b/gds/sky130_hilas_swc4x1cellOverlap2.gds
Binary files differ
diff --git a/gds/sky130_hilas_swc4x2cell.gds b/gds/sky130_hilas_swc4x2cell.gds
new file mode 100644
index 0000000..b0a9781
--- /dev/null
+++ b/gds/sky130_hilas_swc4x2cell.gds
Binary files differ
diff --git a/gds/sky130_hilas_swc4x2cellOverlap.gds b/gds/sky130_hilas_swc4x2cellOverlap.gds
new file mode 100644
index 0000000..5e69d60
--- /dev/null
+++ b/gds/sky130_hilas_swc4x2cellOverlap.gds
Binary files differ
diff --git a/gds/sky130_hilas_wellContact.gds b/gds/sky130_hilas_wellContact.gds
new file mode 100644
index 0000000..4c4d9da
--- /dev/null
+++ b/gds/sky130_hilas_wellContact.gds
Binary files differ
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 252229f..2bfb670 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/m12m3.mag b/mag/m12m3.mag
new file mode 100644
index 0000000..0e61ca6
--- /dev/null
+++ b/mag/m12m3.mag
@@ -0,0 +1,31 @@
+magic
+tech sky130A
+timestamp 1626781805
+<< metal1 >>
+rect 14 1024 1179 1044
+rect 14 471 30 1024
+rect 11 455 30 471
+rect 11 20 27 455
+rect 1156 21 1179 1024
+rect 513 20 1179 21
+rect 11 7 1179 20
+rect 11 6 528 7
+<< via1 >>
+rect 30 455 1156 1024
+rect 27 21 1156 455
+rect 27 20 513 21
+<< metal2 >>
+rect -6 1024 1212 1064
+rect -6 455 30 1024
+rect -6 20 27 455
+rect 1156 21 1212 1024
+rect 513 20 1212 21
+rect -6 -9 1212 20
+<< via2 >>
+rect 37 30 1133 1004
+<< metal3 >>
+rect -25 1004 1232 1087
+rect -25 30 37 1004
+rect 1133 30 1232 1004
+rect -25 -21 1232 30
+<< end >>
diff --git a/mag/sky130_hilas_CapModule01.mag b/mag/sky130_hilas_CapModule01.mag
new file mode 100644
index 0000000..2ab9f89
--- /dev/null
+++ b/mag/sky130_hilas_CapModule01.mag
@@ -0,0 +1,19 @@
+magic
+tech sky130A
+timestamp 1607800460
+<< metal3 >>
+rect -443 -245 -159 41
+<< mimcap >>
+rect -401 -105 -201 -2
+rect -401 -118 -316 -105
+rect -302 -118 -201 -105
+rect -401 -202 -201 -118
+<< mimcapcontact >>
+rect -316 -118 -302 -105
+<< metal4 >>
+rect -331 -93 -286 -92
+rect -333 -105 -281 -93
+rect -333 -118 -316 -105
+rect -302 -118 -281 -105
+rect -333 -142 -281 -118
+<< end >>
diff --git a/mag/sky130_hilas_CapModule01a.mag b/mag/sky130_hilas_CapModule01a.mag
new file mode 100644
index 0000000..d37c85b
--- /dev/null
+++ b/mag/sky130_hilas_CapModule01a.mag
@@ -0,0 +1,19 @@
+magic
+tech sky130A
+timestamp 1607818356
+<< metal3 >>
+rect -416 -216 -186 12
+<< mimcap >>
+rect -401 -105 -201 -2
+rect -401 -118 -316 -105
+rect -302 -118 -201 -105
+rect -401 -202 -201 -118
+<< mimcapcontact >>
+rect -316 -118 -302 -105
+<< metal4 >>
+rect -331 -93 -286 -92
+rect -333 -105 -281 -93
+rect -333 -118 -316 -105
+rect -302 -118 -281 -105
+rect -333 -142 -281 -118
+<< end >>
diff --git a/mag/sky130_hilas_CapModule02.mag b/mag/sky130_hilas_CapModule02.mag
new file mode 100644
index 0000000..84e1841
--- /dev/null
+++ b/mag/sky130_hilas_CapModule02.mag
@@ -0,0 +1,46 @@
+magic
+tech sky130A
+timestamp 1607802006
+<< metal3 >>
+rect -443 333 -161 336
+rect -443 -245 277 333
+rect -164 -247 277 -245
+<< mimcap >>
+rect -404 -104 234 295
+rect -404 -105 -288 -104
+rect -404 -118 -316 -105
+rect -302 -118 -288 -105
+rect -274 -118 -260 -104
+rect -246 -118 -232 -104
+rect -218 -118 -204 -104
+rect -190 -118 -176 -104
+rect -162 -118 -149 -104
+rect -135 -118 -121 -104
+rect -107 -118 -93 -104
+rect -79 -118 234 -104
+rect -404 -205 234 -118
+<< mimcapcontact >>
+rect -316 -118 -302 -105
+rect -288 -118 -274 -104
+rect -260 -118 -246 -104
+rect -232 -118 -218 -104
+rect -204 -118 -190 -104
+rect -176 -118 -162 -104
+rect -149 -118 -135 -104
+rect -121 -118 -107 -104
+rect -93 -118 -79 -104
+<< metal4 >>
+rect -354 -104 -50 -90
+rect -354 -105 -288 -104
+rect -354 -118 -316 -105
+rect -302 -118 -288 -105
+rect -274 -118 -260 -104
+rect -246 -118 -232 -104
+rect -218 -118 -204 -104
+rect -190 -118 -176 -104
+rect -162 -118 -149 -104
+rect -135 -118 -121 -104
+rect -107 -118 -93 -104
+rect -79 -118 -50 -104
+rect -354 -137 -50 -118
+<< end >>
diff --git a/mag/sky130_hilas_CapModule03.mag b/mag/sky130_hilas_CapModule03.mag
new file mode 100644
index 0000000..fea8c7a
--- /dev/null
+++ b/mag/sky130_hilas_CapModule03.mag
@@ -0,0 +1,41 @@
+magic
+tech sky130A
+timestamp 1607813757
+<< metal3 >>
+rect -392 333 -161 336
+rect -392 -245 31 333
+rect -164 -247 31 -245
+<< mimcap >>
+rect -332 -104 -10 295
+rect -332 -118 -288 -104
+rect -274 -118 -260 -104
+rect -246 -118 -232 -104
+rect -218 -118 -204 -104
+rect -190 -118 -176 -104
+rect -162 -118 -149 -104
+rect -135 -118 -121 -104
+rect -107 -118 -93 -104
+rect -79 -118 -10 -104
+rect -332 -205 -10 -118
+<< mimcapcontact >>
+rect -288 -118 -274 -104
+rect -260 -118 -246 -104
+rect -232 -118 -218 -104
+rect -204 -118 -190 -104
+rect -176 -118 -162 -104
+rect -149 -118 -135 -104
+rect -121 -118 -107 -104
+rect -93 -118 -79 -104
+<< metal4 >>
+rect -354 -104 -53 -90
+rect -354 -118 -288 -104
+rect -274 -118 -260 -104
+rect -246 -118 -232 -104
+rect -218 -118 -204 -104
+rect -190 -118 -176 -104
+rect -162 -118 -149 -104
+rect -135 -118 -121 -104
+rect -107 -118 -93 -104
+rect -79 -118 -53 -104
+rect -354 -137 -53 -118
+<< end >>
diff --git a/mag/sky130_hilas_DAC5bit01.mag b/mag/sky130_hilas_DAC5bit01.mag
new file mode 100644
index 0000000..92da476
--- /dev/null
+++ b/mag/sky130_hilas_DAC5bit01.mag
@@ -0,0 +1,181 @@
+magic
+tech sky130A
+timestamp 1625056879
+<< error_s >>
+rect 1063 889 1065 890
+<< nwell >>
+rect 619 1020 1762 1027
+<< locali >>
+rect 780 1027 797 1028
+rect 1677 1027 1698 1105
+rect 1744 1027 1761 1095
+rect 619 1004 1762 1027
+rect 619 648 636 1004
+rect 685 525 702 971
+rect 780 648 797 1004
+rect 848 525 865 967
+rect 939 648 956 1004
+rect 1008 525 1025 975
+rect 1101 648 1118 1004
+rect 1170 525 1187 970
+rect 1263 650 1280 1004
+rect 1330 525 1347 975
+rect 1423 651 1440 1004
+rect 1492 525 1509 975
+rect 1584 650 1601 1004
+rect 1652 525 1669 973
+rect 1745 647 1762 1004
+rect 1813 525 1830 991
+<< metal1 >>
+rect 1056 880 1401 897
+rect 1211 627 1229 781
+rect 1381 696 1401 880
+rect 686 525 2040 548
+<< metal2 >>
+rect 382 1102 1087 1121
+rect 382 1100 397 1102
+rect 382 1020 588 1026
+rect 730 1020 752 1066
+rect 1222 1021 1247 1097
+rect 1222 1020 1250 1021
+rect 382 1005 1250 1020
+rect 408 981 428 1005
+rect 572 990 1250 1005
+rect 1393 833 1413 1089
+rect 382 812 1413 833
+rect 1553 735 1568 1109
+rect 1653 1093 1769 1121
+rect 1728 1092 1769 1093
+rect 382 715 1569 735
+rect 382 714 396 715
+rect 382 603 1236 623
+use sky130_hilas_DAC6TransistorStack01a sky130_hilas_DAC6TransistorStack01a_0
+timestamp 1607478455
+transform 1 0 391 0 1 701
+box 28 -174 200 391
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_12
+timestamp 1607270276
+transform 1 0 417 0 1 769
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_11
+timestamp 1607270276
+transform 1 0 417 0 1 863
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_10
+timestamp 1607270276
+transform 1 0 411 0 1 958
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_9
+timestamp 1607270276
+transform 1 0 425 0 1 1089
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_8
+timestamp 1607270276
+transform 1 0 584 0 1 1090
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_7
+timestamp 1607270276
+transform 0 1 739 -1 0 1073
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_6
+timestamp 1607270276
+transform 1 0 904 0 1 1089
+box -9 -26 24 29
+use sky130_hilas_li2m1 sky130_hilas_li2m1_6
+timestamp 1607179295
+transform 1 0 855 0 1 532
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 693 0 1 532
+box -10 -8 13 21
+use sky130_hilas_DAC6TransistorStack01 sky130_hilas_DAC6TransistorStack01_0
+array 0 2 161 0 0 566
+timestamp 1607480432
+transform 1 0 552 0 1 701
+box 28 -174 200 391
+use sky130_hilas_DAC6TransistorStack01b sky130_hilas_DAC6TransistorStack01b_0
+timestamp 1607480432
+transform 1 0 1035 0 1 701
+box 15 -174 200 391
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_5
+timestamp 1607270276
+transform 1 0 1065 0 1 1089
+box -9 -26 24 29
+use sky130_hilas_li2m1 sky130_hilas_li2m1_7
+timestamp 1607179295
+transform 1 0 1015 0 1 532
+box -10 -8 13 21
+use sky130_hilas_DAC6TransistorStack01c sky130_hilas_DAC6TransistorStack01c_0
+timestamp 1607478930
+transform 1 0 1196 0 1 701
+box 28 -174 215 391
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_3
+timestamp 1607270276
+transform 1 0 1388 0 1 1090
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_4
+timestamp 1607270276
+transform 1 0 1227 0 1 1089
+box -9 -26 24 29
+use sky130_hilas_li2m1 sky130_hilas_li2m1_1
+timestamp 1607179295
+transform 1 0 1177 0 1 532
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_5
+timestamp 1607179295
+transform 1 0 1337 0 1 532
+box -10 -8 13 21
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607949437
+transform 1 0 1217 0 1 607
+box -9 -10 23 22
+use sky130_hilas_DAC6TransistorStack01 sky130_hilas_DAC6TransistorStack01_2
+array 0 2 161 0 0 566
+timestamp 1607480432
+transform 1 0 1357 0 1 701
+box 28 -174 200 391
+use sky130_hilas_DAC6TransistorStack01a sky130_hilas_DAC6TransistorStack01a_1
+timestamp 1607478455
+transform 1 0 1840 0 1 701
+box 28 -174 200 391
+use sky130_hilas_li2m1 sky130_hilas_li2m1_2
+timestamp 1607179295
+transform 1 0 1499 0 1 532
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_4
+timestamp 1607179295
+transform 1 0 1820 0 1 532
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_3
+timestamp 1607179295
+transform 1 0 1659 0 1 532
+box -10 -8 13 21
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 1746 0 1 1090
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 1679 0 1 1090
+box -14 -15 20 18
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_2
+timestamp 1607270276
+transform 1 0 1549 0 1 1090
+box -9 -26 24 29
+<< labels >>
+rlabel metal2 383 1100 393 1121 0 A4
+port 5 nsew analog default
+rlabel metal2 382 1005 392 1026 0 A3
+port 4 nsew analog default
+rlabel metal2 383 812 393 833 0 A2
+port 3 nsew analog default
+rlabel metal2 383 714 393 735 0 A1
+port 2 nsew analog default
+rlabel metal2 382 603 390 623 0 A0
+port 1 nsew analog default
+rlabel metal2 1653 1107 1728 1121 0 VPWR
+port 6 nsew analog default
+rlabel metal1 2028 525 2040 548 0 OUT
+port 7 nsew analog default
+<< end >>
diff --git a/mag/sky130_hilas_DAC6TransistorStack01.mag b/mag/sky130_hilas_DAC6TransistorStack01.mag
new file mode 100644
index 0000000..22db13d
--- /dev/null
+++ b/mag/sky130_hilas_DAC6TransistorStack01.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+timestamp 1607480432
+use sky130_hilas_pFETdevice01a sky130_hilas_pFETdevice01a_0
+timestamp 1607477942
+transform 1 0 108 0 1 -132
+box -80 -42 81 43
+use sky130_hilas_pFETdevice01 sky130_hilas_pFETdevice01_0
+timestamp 1607471549
+transform 1 0 107 0 1 -36
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01 sky130_hilas_pFETdevice01_4
+timestamp 1607471549
+transform 1 0 107 0 1 60
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01 sky130_hilas_pFETdevice01_3
+timestamp 1607471549
+transform 1 0 107 0 1 156
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01 sky130_hilas_pFETdevice01_6
+timestamp 1607471549
+transform 1 0 107 0 1 252
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01aa sky130_hilas_pFETdevice01aa_0
+timestamp 1607478455
+transform 1 0 108 0 1 348
+box -80 -78 92 43
+<< end >>
diff --git a/mag/sky130_hilas_DAC6TransistorStack01a.mag b/mag/sky130_hilas_DAC6TransistorStack01a.mag
new file mode 100644
index 0000000..3df8063
--- /dev/null
+++ b/mag/sky130_hilas_DAC6TransistorStack01a.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+timestamp 1607478455
+use sky130_hilas_pFETdevice01aa sky130_hilas_pFETdevice01aa_3
+timestamp 1607478455
+transform 1 0 108 0 1 348
+box -80 -78 92 43
+use sky130_hilas_pFETdevice01aa sky130_hilas_pFETdevice01aa_2
+timestamp 1607478455
+transform 1 0 108 0 1 252
+box -80 -78 92 43
+use sky130_hilas_pFETdevice01aa sky130_hilas_pFETdevice01aa_4
+timestamp 1607478455
+transform 1 0 108 0 1 156
+box -80 -78 92 43
+use sky130_hilas_pFETdevice01a sky130_hilas_pFETdevice01a_0
+timestamp 1607477942
+transform 1 0 108 0 1 -132
+box -80 -42 81 43
+use sky130_hilas_pFETdevice01aa sky130_hilas_pFETdevice01aa_1
+timestamp 1607478455
+transform 1 0 108 0 1 60
+box -80 -78 92 43
+use sky130_hilas_pFETdevice01aa sky130_hilas_pFETdevice01aa_0
+timestamp 1607478455
+transform 1 0 108 0 1 -36
+box -80 -78 92 43
+<< end >>
diff --git a/mag/sky130_hilas_DAC6TransistorStack01b.mag b/mag/sky130_hilas_DAC6TransistorStack01b.mag
new file mode 100644
index 0000000..3b7ae8a
--- /dev/null
+++ b/mag/sky130_hilas_DAC6TransistorStack01b.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+timestamp 1607480432
+use sky130_hilas_pFETdevice01d sky130_hilas_pFETdevice01d_0
+timestamp 1607475773
+transform 1 0 107 0 1 156
+box -92 -102 92 43
+use sky130_hilas_pFETdevice01 sky130_hilas_pFETdevice01_6
+timestamp 1607471549
+transform 1 0 107 0 1 252
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01 sky130_hilas_pFETdevice01_4
+timestamp 1607471549
+transform 1 0 107 0 1 60
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01 sky130_hilas_pFETdevice01_0
+timestamp 1607471549
+transform 1 0 107 0 1 -36
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01a sky130_hilas_pFETdevice01a_0
+timestamp 1607477942
+transform 1 0 108 0 1 -132
+box -80 -42 81 43
+use sky130_hilas_pFETdevice01aa sky130_hilas_pFETdevice01aa_0
+timestamp 1607478455
+transform 1 0 108 0 1 348
+box -80 -78 92 43
+<< end >>
diff --git a/mag/sky130_hilas_DAC6TransistorStack01c.mag b/mag/sky130_hilas_DAC6TransistorStack01c.mag
new file mode 100644
index 0000000..2554057
--- /dev/null
+++ b/mag/sky130_hilas_DAC6TransistorStack01c.mag
@@ -0,0 +1,28 @@
+magic
+tech sky130A
+timestamp 1607478930
+use sky130_hilas_pFETdevice01b sky130_hilas_pFETdevice01b_1
+timestamp 1607475333
+transform 1 0 107 0 1 60
+box -79 -114 108 43
+use sky130_hilas_pFETdevice01 sky130_hilas_pFETdevice01_6
+timestamp 1607471549
+transform 1 0 107 0 1 252
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01 sky130_hilas_pFETdevice01_3
+timestamp 1607471549
+transform 1 0 107 0 1 156
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01 sky130_hilas_pFETdevice01_0
+timestamp 1607471549
+transform 1 0 107 0 1 -36
+box -79 -78 82 43
+use sky130_hilas_pFETdevice01a sky130_hilas_pFETdevice01a_0
+timestamp 1607477942
+transform 1 0 108 0 1 -132
+box -80 -42 81 43
+use sky130_hilas_pFETdevice01aa sky130_hilas_pFETdevice01aa_0
+timestamp 1607478455
+transform 1 0 108 0 1 348
+box -80 -78 92 43
+<< end >>
diff --git a/mag/sky130_hilas_DAC6bit01.mag b/mag/sky130_hilas_DAC6bit01.mag
new file mode 100644
index 0000000..a9cc377
--- /dev/null
+++ b/mag/sky130_hilas_DAC6bit01.mag
@@ -0,0 +1,159 @@
+magic
+tech sky130A
+timestamp 1607481960
+<< error_s >>
+rect 752 1027 1762 1104
+rect 1868 1020 1889 1092
+rect 414 1005 418 1019
+rect 428 987 432 1005
+<< nwell >>
+rect 752 1020 1762 1027
+<< locali >>
+rect 780 1027 797 1028
+rect 1677 1027 1698 1105
+rect 1744 1027 1761 1095
+rect 619 1004 1762 1027
+rect 619 648 636 1004
+rect 685 525 702 971
+rect 780 648 797 1004
+rect 848 525 865 967
+rect 939 648 956 1004
+rect 1008 525 1025 975
+rect 1101 648 1118 1004
+rect 1170 525 1187 970
+rect 1263 650 1280 1004
+rect 1330 525 1347 975
+rect 1423 651 1440 1004
+rect 1492 525 1509 975
+rect 1584 650 1601 1004
+rect 1652 525 1669 973
+rect 1745 647 1762 1004
+rect 1813 525 1830 991
+<< metal1 >>
+rect 1056 880 1401 897
+rect 1211 627 1229 781
+rect 1381 696 1401 880
+rect 686 525 2030 548
+<< metal2 >>
+rect 418 1102 1087 1121
+rect 418 1020 588 1026
+rect 730 1020 752 1066
+rect 1222 1021 1247 1097
+rect 1222 1020 1250 1021
+rect 418 1005 1250 1020
+rect 418 981 428 1005
+rect 572 990 1250 1005
+rect 1393 833 1413 1089
+rect 418 812 1413 833
+rect 1553 735 1568 1109
+rect 1653 1093 1769 1121
+rect 1728 1092 1769 1093
+rect 418 715 1569 735
+rect 418 603 1236 623
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_8
+timestamp 1607270276
+transform 1 0 584 0 1 1090
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_9
+timestamp 1607270276
+transform 1 0 425 0 1 1089
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_10
+timestamp 1607270276
+transform 1 0 411 0 1 958
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_11
+timestamp 1607270276
+transform 1 0 417 0 1 863
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_12
+timestamp 1607270276
+transform 1 0 417 0 1 769
+box -9 -26 24 29
+use sky130_hilas_DAC6TransistorStack01a sky130_hilas_DAC6TransistorStack01a_0
+timestamp 1607478455
+transform 1 0 391 0 1 701
+box 28 -174 200 391
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 693 0 1 532
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_6
+timestamp 1607179295
+transform 1 0 855 0 1 532
+box -10 -8 13 21
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_6
+timestamp 1607270276
+transform 1 0 904 0 1 1089
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_7
+timestamp 1607270276
+transform 0 1 739 -1 0 1073
+box -9 -26 24 29
+use sky130_hilas_li2m1 sky130_hilas_li2m1_7
+timestamp 1607179295
+transform 1 0 1015 0 1 532
+box -10 -8 13 21
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_5
+timestamp 1607270276
+transform 1 0 1065 0 1 1089
+box -9 -26 24 29
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607179755
+transform 1 0 1217 0 1 607
+box -9 -10 23 22
+use sky130_hilas_li2m1 sky130_hilas_li2m1_5
+timestamp 1607179295
+transform 1 0 1337 0 1 532
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_1
+timestamp 1607179295
+transform 1 0 1177 0 1 532
+box -10 -8 13 21
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_4
+timestamp 1607270276
+transform 1 0 1227 0 1 1089
+box -9 -26 24 29
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_3
+timestamp 1607270276
+transform 1 0 1388 0 1 1090
+box -9 -26 24 29
+use sky130_hilas_DAC6TransistorStack01a sky130_hilas_DAC6TransistorStack01a_1
+timestamp 1607478455
+transform 1 0 1840 0 1 701
+box 28 -174 200 391
+use sky130_hilas_li2m1 sky130_hilas_li2m1_2
+timestamp 1607179295
+transform 1 0 1499 0 1 532
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_4
+timestamp 1607179295
+transform 1 0 1820 0 1 532
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_3
+timestamp 1607179295
+transform 1 0 1659 0 1 532
+box -10 -8 13 21
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 1746 0 1 1090
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 1679 0 1 1090
+box -14 -15 20 18
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_2
+timestamp 1607270276
+transform 1 0 1549 0 1 1090
+box -9 -26 24 29
+use sky130_hilas_DAC6TransistorStack01 sky130_hilas_DAC6TransistorStack01_0
+timestamp 1607480432
+transform 1 0 548 0 1 1501
+box 28 -174 200 391
+use sky130_hilas_DAC6TransistorStack01 sky130_hilas_DAC6TransistorStack01_0
+timestamp 0
+transform 1 0 535 0 1 1475
+box 0 0 1 1
+<< labels >>
+rlabel metal2 1653 1107 1728 1121 0 Vdd
+<< end >>
diff --git a/mag/sky130_hilas_DecoupVinj00.mag b/mag/sky130_hilas_DecoupVinj00.mag
new file mode 100644
index 0000000..eac1cad
--- /dev/null
+++ b/mag/sky130_hilas_DecoupVinj00.mag
@@ -0,0 +1,236 @@
+magic
+tech sky130A
+timestamp 1625358249
+<< nwell >>
+rect 68 52 472 189
+<< mvnmos >>
+rect 130 -56 341 5
+<< mvpmos >>
+rect 130 86 340 148
+<< mvndiff >>
+rect 101 1 130 5
+rect 101 -16 107 1
+rect 124 -16 130 1
+rect 101 -33 130 -16
+rect 101 -50 107 -33
+rect 124 -50 130 -33
+rect 101 -56 130 -50
+rect 341 1 370 5
+rect 341 -16 347 1
+rect 364 -16 370 1
+rect 341 -33 370 -16
+rect 341 -50 347 -33
+rect 364 -50 370 -33
+rect 341 -56 370 -50
+<< mvpdiff >>
+rect 101 143 130 148
+rect 101 126 107 143
+rect 124 126 130 143
+rect 101 109 130 126
+rect 101 92 107 109
+rect 124 92 130 109
+rect 101 86 130 92
+rect 340 143 370 148
+rect 340 126 346 143
+rect 363 126 370 143
+rect 340 109 370 126
+rect 340 92 346 109
+rect 363 92 370 109
+rect 340 86 370 92
+<< mvndiffc >>
+rect 107 -16 124 1
+rect 107 -50 124 -33
+rect 347 -16 364 1
+rect 347 -50 364 -33
+<< mvpdiffc >>
+rect 107 126 124 143
+rect 107 92 124 109
+rect 346 126 363 143
+rect 346 92 363 109
+<< psubdiff >>
+rect 389 -2 458 10
+rect 389 -19 399 -2
+rect 416 -19 433 -2
+rect 450 -19 458 -2
+rect 389 -36 458 -19
+rect 389 -53 399 -36
+rect 416 -53 433 -36
+rect 450 -53 458 -36
+rect 389 -70 458 -53
+rect 382 -87 399 -70
+rect 416 -87 433 -70
+rect 450 -87 458 -70
+rect 389 -99 458 -87
+<< mvnsubdiff >>
+rect 397 144 439 156
+rect 397 127 409 144
+rect 426 127 439 144
+rect 397 110 439 127
+rect 397 93 409 110
+rect 426 93 439 110
+rect 397 86 439 93
+<< psubdiffcont >>
+rect 399 -19 416 -2
+rect 433 -19 450 -2
+rect 399 -53 416 -36
+rect 433 -53 450 -36
+rect 399 -87 416 -70
+rect 433 -87 450 -70
+<< mvnsubdiffcont >>
+rect 409 127 426 144
+rect 409 93 426 110
+<< poly >>
+rect 130 148 341 163
+rect 130 85 340 86
+rect 130 68 341 85
+rect 130 67 231 68
+rect 163 40 164 67
+rect 197 40 198 67
+rect 304 20 305 46
+rect 338 20 339 46
+rect 271 19 341 20
+rect 130 5 341 19
+rect 130 -69 341 -56
+<< locali >>
+rect 99 183 429 189
+rect 99 182 158 183
+rect 166 182 265 183
+rect 275 182 429 183
+rect 99 179 429 182
+rect 99 162 377 179
+rect 394 162 412 179
+rect 99 144 429 162
+rect 99 143 409 144
+rect 99 126 107 143
+rect 124 126 346 143
+rect 363 127 409 143
+rect 426 127 429 144
+rect 363 126 429 127
+rect 99 110 428 126
+rect 99 109 409 110
+rect 99 92 107 109
+rect 124 92 346 109
+rect 363 93 409 109
+rect 426 93 428 110
+rect 363 92 428 93
+rect 99 85 428 92
+rect 99 1 231 67
+rect 271 24 428 85
+rect 367 4 450 6
+rect 361 1 450 4
+rect 99 -16 107 1
+rect 124 -16 347 1
+rect 364 -2 450 1
+rect 364 -16 399 -2
+rect 99 -19 399 -16
+rect 416 -19 433 -2
+rect 99 -33 450 -19
+rect 99 -50 107 -33
+rect 124 -50 347 -33
+rect 364 -36 450 -33
+rect 364 -50 399 -36
+rect 99 -53 399 -50
+rect 416 -53 433 -36
+rect 99 -70 450 -53
+rect 99 -87 382 -70
+rect 99 -88 450 -87
+rect 375 -95 450 -88
+<< viali >>
+rect 377 162 394 179
+rect 412 162 429 179
+rect 382 -87 399 -70
+rect 416 -87 433 -70
+<< metal1 >>
+rect 68 179 473 189
+rect 68 162 377 179
+rect 394 162 412 179
+rect 429 162 473 179
+rect 68 142 473 162
+rect 99 141 473 142
+rect 68 -64 373 -50
+rect 68 -70 473 -64
+rect 68 -87 382 -70
+rect 399 -87 416 -70
+rect 433 -87 473 -70
+rect 68 -113 473 -87
+use sky130_hilas_li2m1 sky130_hilas_li2m1_1
+timestamp 1607179295
+transform 1 0 174 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 138 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_3
+timestamp 1607179295
+transform 1 0 210 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_2
+timestamp 1607179295
+transform 1 0 282 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_5
+timestamp 1607179295
+transform 1 0 246 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_7
+timestamp 1607179295
+transform 1 0 354 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_4
+timestamp 1607179295
+transform 1 0 318 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_poly2li sky130_hilas_poly2li_4
+timestamp 1607178257
+transform 0 1 285 -1 0 37
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_3
+timestamp 1607178257
+transform 0 1 353 -1 0 37
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_0
+timestamp 1607178257
+transform 0 1 319 -1 0 37
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_1
+timestamp 1607178257
+transform 0 1 144 -1 0 58
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_2
+timestamp 1607178257
+transform 0 1 178 -1 0 58
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_5
+timestamp 1607178257
+transform 0 1 212 -1 0 58
+box -9 -14 18 19
+use sky130_hilas_li2m1 sky130_hilas_li2m1_10
+timestamp 1607179295
+transform 1 0 159 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_9
+timestamp 1607179295
+transform 1 0 123 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_12
+timestamp 1607179295
+transform 1 0 231 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_11
+timestamp 1607179295
+transform 1 0 195 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_13
+timestamp 1607179295
+transform 1 0 267 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_15
+timestamp 1607179295
+transform 1 0 347 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_14
+timestamp 1607179295
+transform 1 0 303 0 1 165
+box -10 -8 13 21
+<< end >>
diff --git a/mag/sky130_hilas_DecoupVinj01.mag b/mag/sky130_hilas_DecoupVinj01.mag
new file mode 100644
index 0000000..320a2ad
--- /dev/null
+++ b/mag/sky130_hilas_DecoupVinj01.mag
@@ -0,0 +1,152 @@
+magic
+tech sky130A
+timestamp 1625359887
+<< psubdiff >>
+rect 671 88 672 171
+<< locali >>
+rect 646 547 665 636
+rect 646 82 672 171
+<< metal1 >>
+rect 341 598 376 661
+rect 341 582 603 598
+rect 637 607 744 661
+rect 637 598 656 607
+rect 629 582 656 598
+rect 341 581 656 582
+rect 682 581 744 607
+rect 341 567 744 581
+rect 341 566 656 567
+rect 341 540 601 566
+rect 627 541 656 566
+rect 682 541 744 567
+rect 627 540 744 541
+rect 341 530 744 540
+rect 341 476 744 499
+rect 341 449 392 476
+rect 419 449 447 476
+rect 474 449 744 476
+rect 341 419 744 449
+rect 341 418 447 419
+rect 341 391 391 418
+rect 418 392 447 418
+rect 474 392 744 419
+rect 418 391 744 392
+rect 341 335 744 391
+rect 341 334 447 335
+rect 341 307 392 334
+rect 419 308 447 334
+rect 474 308 744 335
+rect 419 307 744 308
+rect 341 284 744 307
+rect 341 257 392 284
+rect 419 282 744 284
+rect 419 257 445 282
+rect 341 255 445 257
+rect 472 255 744 282
+rect 341 220 744 255
+rect 341 157 744 184
+rect 341 131 617 157
+rect 643 131 665 157
+rect 691 131 744 157
+rect 341 116 744 131
+rect 341 90 615 116
+rect 641 90 664 116
+rect 690 90 744 116
+rect 341 60 744 90
+rect 341 57 377 60
+rect 646 58 744 60
+rect 645 57 744 58
+<< via1 >>
+rect 603 582 629 608
+rect 656 581 682 607
+rect 601 540 627 566
+rect 656 541 682 567
+rect 392 449 419 476
+rect 447 449 474 476
+rect 391 391 418 418
+rect 447 392 474 419
+rect 392 307 419 334
+rect 447 308 474 335
+rect 392 257 419 284
+rect 445 255 472 282
+rect 617 131 643 157
+rect 665 131 691 157
+rect 615 90 641 116
+rect 664 90 690 116
+<< metal2 >>
+rect 377 476 507 661
+rect 377 449 392 476
+rect 419 449 447 476
+rect 474 449 507 476
+rect 377 419 507 449
+rect 377 418 447 419
+rect 377 391 391 418
+rect 418 392 447 418
+rect 474 392 507 419
+rect 418 391 507 392
+rect 377 335 507 391
+rect 377 334 447 335
+rect 377 307 392 334
+rect 419 308 447 334
+rect 474 308 507 335
+rect 419 307 507 308
+rect 377 284 507 307
+rect 377 257 392 284
+rect 419 282 507 284
+rect 419 257 445 282
+rect 377 255 445 257
+rect 472 255 507 282
+rect 377 57 507 255
+rect 585 608 715 661
+rect 585 582 603 608
+rect 629 607 715 608
+rect 629 582 656 607
+rect 585 581 656 582
+rect 682 581 715 607
+rect 585 567 715 581
+rect 585 566 656 567
+rect 585 540 601 566
+rect 627 541 656 566
+rect 682 541 715 567
+rect 627 540 715 541
+rect 585 519 715 540
+rect 585 189 714 519
+rect 585 157 715 189
+rect 585 131 617 157
+rect 643 131 665 157
+rect 691 131 715 157
+rect 585 116 715 131
+rect 585 90 615 116
+rect 641 90 664 116
+rect 690 90 715 116
+rect 585 57 715 90
+use sky130_hilas_DecoupVinj00 CapDeco_1
+timestamp 1625358249
+transform 1 0 273 0 1 170
+box 68 -113 473 189
+use sky130_hilas_DecoupVinj00 CapDeco_0
+timestamp 1625358249
+transform 1 0 273 0 -1 548
+box 68 -113 473 189
+<< labels >>
+rlabel metal1 355 57 364 120 0 VGND
+port 1 nsew
+rlabel metal1 729 57 744 120 0 VGND
+port 1 nsew
+rlabel metal2 377 651 507 661 0 VINJ
+port 1 nsew
+rlabel metal2 585 653 715 661 0 VGND
+port 2 nsew
+rlabel metal2 377 57 507 69 0 VINJ
+port 1 nsew
+rlabel metal2 585 57 715 69 0 VGND
+port 2 nsew
+rlabel metal1 727 313 744 407 0 VINJ
+port 1 nsew
+rlabel metal1 341 311 358 407 0 VINJ
+port 1 nsew
+rlabel metal1 355 598 363 661 0 VGND
+port 3 nsew
+rlabel metal1 734 598 744 661 0 VGND
+port 2 nsew
+<< end >>
diff --git a/mag/sky130_hilas_DoubleTGate01.mag b/mag/sky130_hilas_DoubleTGate01.mag
new file mode 100644
index 0000000..ed26cae
--- /dev/null
+++ b/mag/sky130_hilas_DoubleTGate01.mag
@@ -0,0 +1,34 @@
+magic
+tech sky130A
+timestamp 1607908253
+<< metal2 >>
+rect 1107 559 1180 560
+rect 1107 543 1249 559
+rect 1107 542 1180 543
+rect 1107 372 1174 374
+rect 1107 356 1246 372
+rect 1107 257 1177 258
+rect 1107 241 1250 257
+rect 1107 57 1253 74
+use sky130_hilas_TgateVinj01 sky130_hilas_TgateVinj01_0
+timestamp 1607907894
+transform 1 0 1282 0 1 338
+box -210 -40 332 119
+use sky130_hilas_TgateVinj01 sky130_hilas_TgateVinj01_3
+timestamp 1607907894
+transform 1 0 1282 0 -1 277
+box -210 -40 332 119
+use sky130_hilas_TgateVinj01 sky130_hilas_TgateVinj01_1
+timestamp 1607907894
+transform 1 0 1282 0 -1 570
+box -210 -40 332 119
+use sky130_hilas_TgateVinj01 sky130_hilas_TgateVinj01_2
+timestamp 1607907894
+transform 1 0 1282 0 1 45
+box -210 -40 332 119
+<< labels >>
+rlabel metal2 1107 542 1112 560 0 drain1
+rlabel metal2 1107 356 1112 374 0 drain2
+rlabel metal2 1107 241 1112 258 0 drain3
+rlabel metal2 1107 57 1112 74 0 drain4
+<< end >>
diff --git a/mag/sky130_hilas_DualTACore01.mag b/mag/sky130_hilas_DualTACore01.mag
new file mode 100644
index 0000000..f7f3412
--- /dev/null
+++ b/mag/sky130_hilas_DualTACore01.mag
@@ -0,0 +1,63 @@
+magic
+tech sky130A
+timestamp 1608069483
+<< metal1 >>
+rect -41 -22 -7 550
+rect 26 -21 53 549
+<< metal2 >>
+rect -136 507 118 530
+rect -110 293 155 316
+rect -136 211 155 233
+rect -137 -6 134 17
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 106 0 1 228
+box -14 -15 20 18
+use sky130_hilas_nMirror03 sky130_hilas_nMirror03_1
+timestamp 1607268356
+transform 1 0 -113 0 1 131
+box -59 -5 125 122
+use sky130_hilas_nMirror03 sky130_hilas_nMirror03_0
+timestamp 1607268356
+transform 1 0 -113 0 -1 100
+box -59 -5 125 122
+use sky130_hilas_li2m1 sky130_hilas_li2m1_1
+timestamp 1607179295
+transform 1 0 41 0 1 126
+box -10 -8 13 21
+use sky130_hilas_li2m2 sky130_hilas_li2m2_3
+timestamp 1607089160
+transform 1 0 98 0 1 3
+box -14 -15 20 18
+use sky130_hilas_pFETmirror02 sky130_hilas_pFETmirror02_0
+timestamp 1607207238
+transform 1 0 88 0 1 -111
+box -61 89 67 373
+use sky130_hilas_pFETmirror02 sky130_hilas_pFETmirror02_1
+timestamp 1607207238
+transform 1 0 88 0 -1 635
+box -61 89 67 373
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 107 0 1 300
+box -14 -15 20 18
+use sky130_hilas_nMirror03 sky130_hilas_nMirror03_2
+timestamp 1607268356
+transform 1 0 -113 0 1 427
+box -59 -5 125 122
+use sky130_hilas_nMirror03 sky130_hilas_nMirror03_3
+timestamp 1607268356
+transform 1 0 -113 0 -1 396
+box -59 -5 125 122
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 41 0 1 385
+box -10 -8 13 21
+use sky130_hilas_li2m2 sky130_hilas_li2m2_2
+timestamp 1607089160
+transform 1 0 102 0 1 522
+box -14 -15 20 18
+<< labels >>
+rlabel metal2 144 293 155 316 0 output1
+rlabel space 144 211 155 234 0 output2
+<< end >>
diff --git a/mag/sky130_hilas_FGBias2x1cell.mag b/mag/sky130_hilas_FGBias2x1cell.mag
new file mode 100644
index 0000000..9d8acdb
--- /dev/null
+++ b/mag/sky130_hilas_FGBias2x1cell.mag
@@ -0,0 +1,192 @@
+magic
+tech sky130A
+timestamp 1625491133
+<< error_s >>
+rect -338 150 -332 156
+rect -285 150 -279 156
+rect -344 100 -338 106
+rect -279 100 -273 106
+rect 85 91 91 97
+rect 190 91 196 97
+rect 79 41 85 47
+rect 196 41 202 47
+rect 85 -210 91 -204
+rect 190 -210 196 -204
+rect -338 -264 -332 -258
+rect -285 -264 -279 -258
+rect 79 -260 85 -254
+rect 196 -260 202 -254
+rect -344 -314 -338 -308
+rect -279 -314 -273 -308
+<< nwell >>
+rect 426 222 757 223
+rect 661 219 680 222
+rect -337 -242 -281 0
+<< psubdiff >>
+rect -95 -42 -70 121
+rect -95 -59 -92 -42
+rect -73 -59 -70 -42
+rect -95 -72 -70 -59
+rect -95 -75 267 -72
+rect -95 -76 146 -75
+rect -95 -93 -71 -76
+rect -52 -93 -28 -76
+rect -9 -93 16 -76
+rect 35 -93 56 -76
+rect 75 -93 100 -76
+rect 119 -92 146 -76
+rect 165 -76 267 -75
+rect 165 -92 190 -76
+rect 119 -93 190 -92
+rect 209 -93 236 -76
+rect 255 -93 267 -76
+rect -95 -97 267 -93
+rect -95 -110 -70 -97
+rect -95 -127 -92 -110
+rect -73 -127 -70 -110
+rect -95 -281 -70 -127
+<< mvnsubdiff >>
+rect -337 -242 -281 0
+<< psubdiffcont >>
+rect -92 -59 -73 -42
+rect -71 -93 -52 -76
+rect -28 -93 -9 -76
+rect 16 -93 35 -76
+rect 56 -93 75 -76
+rect 100 -93 119 -76
+rect 146 -92 165 -75
+rect 190 -93 209 -76
+rect 236 -93 255 -76
+rect -92 -127 -73 -110
+<< poly >>
+rect -237 134 332 151
+rect -237 126 -185 134
+rect 45 91 64 134
+rect 220 90 237 134
+rect 46 -293 63 -260
+rect 220 -293 237 -260
+rect -280 -310 331 -293
+<< locali >>
+rect 467 28 470 45
+rect -92 -42 -73 -34
+rect 467 -51 472 -34
+rect -92 -75 -73 -59
+rect -92 -76 146 -75
+rect -92 -93 -71 -76
+rect -52 -93 -28 -76
+rect -9 -93 16 -76
+rect 35 -93 56 -76
+rect 75 -93 100 -76
+rect 119 -92 146 -76
+rect 165 -76 263 -75
+rect 165 -92 190 -76
+rect 119 -93 190 -92
+rect 209 -93 236 -76
+rect 255 -93 263 -76
+rect -92 -110 -73 -93
+rect 474 -108 491 -51
+rect 467 -125 469 -108
+rect -92 -135 -73 -127
+rect 11 -197 34 -193
+rect 467 -204 470 -187
+<< metal1 >>
+rect -361 -382 -319 223
+rect -113 -382 -90 223
+rect 9 -382 32 223
+rect 661 219 680 223
+rect 661 -382 680 -377
+rect 705 -382 733 223
+<< metal2 >>
+rect -396 155 516 173
+rect 554 49 757 71
+rect 622 -98 740 -63
+rect 553 -226 757 -205
+rect 510 -315 526 -313
+rect -396 -320 526 -315
+rect -396 -330 514 -320
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_3
+timestamp 1608066871
+transform 1 0 1056 0 1 433
+box -1451 -400 -1278 -210
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_1
+timestamp 1608066871
+transform 1 0 1056 0 1 19
+box -1451 -400 -1278 -210
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 -103 0 1 -92
+box -10 -8 13 21
+use sky130_hilas_wellContact sky130_hilas_wellContact_1
+timestamp 1606753443
+transform 1 0 1054 0 1 404
+box -1449 -441 -1275 -255
+use sky130_hilas_wellContact sky130_hilas_wellContact_0
+timestamp 1606753443
+transform 1 0 1054 0 1 231
+box -1449 -441 -1275 -255
+use sky130_hilas_FGVaractorCapacitor02 sky130_hilas_FGVaractorCapacitor02_0
+timestamp 1606868103
+transform 1 0 986 0 1 62
+box -1005 -380 -733 -211
+use sky130_hilas_FGVaractorCapacitor02 sky130_hilas_FGVaractorCapacitor02_2
+timestamp 1606868103
+transform 1 0 986 0 -1 -231
+box -1005 -380 -733 -211
+use sky130_hilas_horizTransCell01 sky130_hilas_horizTransCell01_1
+timestamp 1625488390
+transform 1 0 790 0 -1 270
+box -476 48 -33 359
+use sky130_hilas_horizTransCell01 sky130_hilas_horizTransCell01_0
+timestamp 1625488390
+transform 1 0 790 0 1 -429
+box -476 48 -33 359
+use sky130_hilas_m12m2 sky130_hilas_m12m2_2
+timestamp 1607949437
+transform 1 0 721 0 1 -84
+box -9 -10 23 22
+use sky130_hilas_m12m2 sky130_hilas_m12m2_1
+timestamp 1607949437
+transform 1 0 627 0 1 -56
+box -9 -10 23 22
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607949437
+transform 1 0 627 0 1 -116
+box -9 -10 23 22
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 538 0 1 -216
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 538 0 1 60
+box -14 -15 20 18
+<< labels >>
+rlabel metal1 -361 216 -319 223 0 VTUN
+port 1 nsew analog default
+rlabel metal1 -113 216 -90 223 0 VGND
+port 2 nsew ground default
+rlabel metal1 9 215 32 223 0 GATE_CONTROL
+port 3 nsew analog default
+rlabel metal1 705 216 733 223 0 VINJ
+port 7 nsew power default
+rlabel metal2 749 49 757 71 0 OUTPUT1
+port 8 nsew analog default
+rlabel metal2 750 -226 757 -205 0 OUTPUT2
+port 9 nsew analog default
+rlabel metal1 -361 -382 -319 -370 0 VTUN
+port 1 nsew analog default
+rlabel metal1 9 -382 32 -376 0 GATE_CONTROL
+port 4 nsew analog default
+rlabel metal1 -113 -382 -90 -376 0 VGND
+port 2 nsew ground default
+rlabel metal2 -396 155 -389 173 0 DRAIN1
+port 5 nsew analog default
+rlabel metal2 -396 -330 -390 -315 0 DRAIN4
+port 6 nsew analog default
+rlabel metal1 661 219 680 223 0 GATECOL
+port 10 nsew
+rlabel metal1 661 -382 680 -377 0 GATECOL
+port 10 nsew
+rlabel metal1 705 -382 733 -377 0 VINJ
+port 11 nsew
+<< end >>
diff --git a/mag/sky130_hilas_FGBiasWeakGate2x1cell.mag b/mag/sky130_hilas_FGBiasWeakGate2x1cell.mag
new file mode 100644
index 0000000..7b283e8
--- /dev/null
+++ b/mag/sky130_hilas_FGBiasWeakGate2x1cell.mag
@@ -0,0 +1,216 @@
+magic
+tech sky130A
+timestamp 1625491133
+<< error_s >>
+rect -338 150 -332 156
+rect -285 150 -279 156
+rect -344 100 -338 106
+rect -279 100 -273 106
+rect 85 91 91 97
+rect 190 91 196 97
+rect 79 41 85 47
+rect 196 41 202 47
+rect 85 -210 91 -204
+rect 190 -210 196 -204
+rect -338 -264 -332 -258
+rect -285 -264 -279 -258
+rect 79 -260 85 -254
+rect 196 -260 202 -254
+rect -344 -314 -338 -308
+rect -279 -314 -273 -308
+<< nwell >>
+rect -337 -242 -281 0
+<< psubdiff >>
+rect -95 -42 -70 101
+rect -95 -59 -92 -42
+rect -73 -59 -70 -42
+rect -95 -72 -70 -59
+rect -95 -75 267 -72
+rect -95 -76 146 -75
+rect -95 -93 -71 -76
+rect -52 -93 -28 -76
+rect -9 -93 16 -76
+rect 35 -93 56 -76
+rect 75 -93 100 -76
+rect 119 -92 146 -76
+rect 165 -76 267 -75
+rect 165 -92 190 -76
+rect 119 -93 190 -92
+rect 209 -93 236 -76
+rect 255 -93 267 -76
+rect -95 -97 267 -93
+rect -95 -110 -70 -97
+rect -95 -127 -92 -110
+rect -73 -127 -70 -110
+rect -95 -281 -70 -127
+<< mvnsubdiff >>
+rect -337 -242 -281 0
+<< psubdiffcont >>
+rect -92 -59 -73 -42
+rect -71 -93 -52 -76
+rect -28 -93 -9 -76
+rect 16 -93 35 -76
+rect 56 -93 75 -76
+rect 100 -93 119 -76
+rect 146 -92 165 -75
+rect 190 -93 209 -76
+rect 236 -93 255 -76
+rect -92 -127 -73 -110
+<< poly >>
+rect -206 151 293 201
+rect -237 134 332 151
+rect -237 126 321 134
+rect 45 91 64 126
+rect 220 90 237 126
+rect 46 -293 63 -260
+rect 220 -293 237 -260
+rect -280 -310 331 -293
+rect -202 -367 298 -310
+<< locali >>
+rect -209 122 297 205
+rect -202 114 -154 122
+rect -169 89 -154 114
+rect 467 28 470 45
+rect -92 -42 -73 -34
+rect 467 -51 472 -34
+rect -92 -75 -73 -59
+rect -92 -76 146 -75
+rect -92 -93 -71 -76
+rect -52 -93 -28 -76
+rect -9 -93 16 -76
+rect 35 -93 56 -76
+rect 75 -93 100 -76
+rect 119 -92 146 -76
+rect 165 -76 263 -75
+rect 165 -92 190 -76
+rect 119 -93 190 -92
+rect 209 -93 236 -76
+rect 255 -93 263 -76
+rect -92 -110 -73 -93
+rect 474 -108 491 -51
+rect 467 -125 469 -108
+rect -92 -135 -73 -127
+rect 11 -197 34 -193
+rect 467 -204 470 -187
+rect -172 -279 -170 -254
+rect -205 -287 -170 -279
+rect -205 -372 300 -287
+<< metal1 >>
+rect -361 -381 -319 223
+rect -113 126 -90 223
+rect -113 101 -89 126
+rect -113 -382 -90 101
+rect 9 -382 32 223
+rect 661 217 680 223
+rect 661 -382 680 -376
+rect 705 -382 733 223
+<< metal2 >>
+rect -396 155 516 173
+rect -217 113 -171 114
+rect -396 97 -171 113
+rect -396 95 -202 97
+rect 554 70 757 71
+rect -396 49 757 70
+rect -396 48 626 49
+rect -396 -49 650 -27
+rect 622 -98 648 -63
+rect -396 -226 757 -205
+rect -396 -227 626 -226
+rect -396 -279 -201 -258
+rect 510 -315 526 -313
+rect -396 -320 526 -315
+rect -396 -330 514 -320
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_1
+timestamp 1608066871
+transform 1 0 1056 0 1 19
+box -1451 -400 -1278 -210
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_3
+timestamp 1608066871
+transform 1 0 1056 0 1 433
+box -1451 -400 -1278 -210
+use sky130_hilas_li2m2 sky130_hilas_li2m2_3
+timestamp 1607089160
+transform 1 0 -191 0 1 -268
+box -14 -15 20 18
+use sky130_hilas_FGVaractorCapacitor02 sky130_hilas_FGVaractorCapacitor02_0
+timestamp 1606868103
+transform 1 0 986 0 1 62
+box -1005 -380 -733 -211
+use sky130_hilas_wellContact sky130_hilas_wellContact_0
+timestamp 1606753443
+transform 1 0 1054 0 1 231
+box -1449 -441 -1275 -255
+use sky130_hilas_FGVaractorCapacitor02 sky130_hilas_FGVaractorCapacitor02_2
+timestamp 1606868103
+transform 1 0 986 0 -1 -231
+box -1005 -380 -733 -211
+use sky130_hilas_wellContact sky130_hilas_wellContact_1
+timestamp 1606753443
+transform 1 0 1054 0 1 404
+box -1449 -441 -1275 -255
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 -103 0 1 -92
+box -10 -8 13 21
+use sky130_hilas_li2m2 sky130_hilas_li2m2_2
+timestamp 1607089160
+transform 1 0 -188 0 1 101
+box -14 -15 20 18
+use sky130_hilas_horizTransCell01 sky130_hilas_horizTransCell01_1
+timestamp 1625488390
+transform 1 0 790 0 -1 270
+box -476 48 -33 359
+use sky130_hilas_horizTransCell01 sky130_hilas_horizTransCell01_0
+timestamp 1625488390
+transform 1 0 790 0 1 -429
+box -476 48 -33 359
+use sky130_hilas_m12m2 sky130_hilas_m12m2_1
+timestamp 1607949437
+transform 1 0 627 0 1 -56
+box -9 -10 23 22
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607949437
+transform 1 0 627 0 1 -116
+box -9 -10 23 22
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 538 0 1 -216
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 538 0 1 60
+box -14 -15 20 18
+<< labels >>
+rlabel metal1 -361 216 -319 223 0 VTUN
+port 9 nsew analog default
+rlabel metal1 -113 216 -90 223 0 VGND
+port 7 nsew ground default
+rlabel metal1 9 215 32 223 0 GATE1
+port 8 nsew analog default
+rlabel metal1 705 216 733 223 0 VINJ
+port 5 nsew power default
+rlabel metal2 749 49 757 71 0 ROW1
+port 3 nsew analog default
+rlabel metal2 750 -226 757 -205 0 ROW2
+port 4 nsew analog default
+rlabel metal2 -396 155 -389 173 0 DRAIN1
+port 1 nsew analog default
+rlabel metal2 -396 95 -391 113 0 VIN11
+port 2 nsew
+rlabel metal1 661 217 680 222 0 COLSEL1
+port 6 nsew analog default
+rlabel metal1 661 -382 680 -376 0 COLSEL1
+port 6 nsew analog default
+rlabel metal1 705 -382 733 -375 0 VINJ
+port 5 nsew power default
+rlabel metal1 -113 -382 -90 -372 0 VGND
+port 7 nsew ground default
+rlabel metal1 9 -382 32 -374 0 GATE1
+port 10 nsew analog default
+rlabel metal2 -396 -330 -391 -315 0 DRAIN2
+port 11 nsew analog default
+rlabel metal2 -396 -279 -390 -258 0 VIN12
+port 12 nsew analog default
+rlabel metal2 -396 -49 -390 -27 0 COMMONSOURCE
+port 13 nsew analog default
+<< end >>
diff --git a/mag/sky130_hilas_FGHugeVaractorCapacitor01.mag b/mag/sky130_hilas_FGHugeVaractorCapacitor01.mag
new file mode 100644
index 0000000..fcc9ad3
--- /dev/null
+++ b/mag/sky130_hilas_FGHugeVaractorCapacitor01.mag
@@ -0,0 +1,41 @@
+magic
+tech sky130A
+timestamp 1608043965
+<< error_p >>
+rect -500 -276 -494 -270
+rect 350 -276 357 -270
+rect -506 -742 -500 -736
+rect 356 -742 362 -736
+<< nwell >>
+rect -556 -677 413 -217
+rect -556 -816 473 -677
+<< mvvaractor >>
+rect -500 -742 356 -276
+<< mvnsubdiff >>
+rect -500 -276 357 -250
+rect 404 -727 440 -710
+rect -500 -766 356 -742
+rect 404 -744 410 -727
+rect 427 -744 440 -727
+rect 404 -761 440 -744
+rect 404 -766 410 -761
+rect -500 -778 410 -766
+rect 427 -778 440 -761
+rect -500 -783 440 -778
+<< mvnsubdiffcont >>
+rect 410 -744 427 -727
+rect 410 -778 427 -761
+<< poly >>
+rect -540 -742 -500 -276
+rect 356 -742 395 -276
+<< locali >>
+rect 410 -727 427 -719
+rect 410 -786 427 -778
+<< viali >>
+rect 410 -761 427 -744
+<< metal1 >>
+rect 407 -744 431 -734
+rect 407 -761 410 -744
+rect 427 -761 431 -744
+rect 407 -770 431 -761
+<< end >>
diff --git a/mag/sky130_hilas_FGVaractorCapacitor.mag b/mag/sky130_hilas_FGVaractorCapacitor.mag
new file mode 100644
index 0000000..e1373bc
--- /dev/null
+++ b/mag/sky130_hilas_FGVaractorCapacitor.mag
@@ -0,0 +1,21 @@
+magic
+tech sky130A
+timestamp 1606741561
+<< error_p >>
+rect -901 -272 -895 -266
+rect -796 -272 -790 -266
+rect -907 -336 -901 -330
+rect -790 -336 -784 -330
+<< nwell >>
+rect -957 -395 -734 -210
+<< mvvaractor >>
+rect -901 -336 -790 -272
+<< mvnsubdiff >>
+rect -901 -272 -790 -244
+rect -901 -361 -790 -336
+<< poly >>
+rect -941 -336 -901 -272
+rect -790 -336 -749 -272
+<< metal1 >>
+rect -892 -395 -854 -209
+<< end >>
diff --git a/mag/sky130_hilas_FGVaractorCapacitor02.mag b/mag/sky130_hilas_FGVaractorCapacitor02.mag
new file mode 100644
index 0000000..4ac6a16
--- /dev/null
+++ b/mag/sky130_hilas_FGVaractorCapacitor02.mag
@@ -0,0 +1,48 @@
+magic
+tech sky130A
+timestamp 1606868103
+<< error_p >>
+rect -901 -272 -895 -266
+rect -796 -272 -790 -266
+rect -907 -322 -901 -316
+rect -790 -322 -784 -316
+<< nwell >>
+rect -1005 -215 -734 -211
+rect -1005 -380 -733 -215
+<< mvvaractor >>
+rect -901 -322 -790 -272
+<< mvnsubdiff >>
+rect -972 -265 -790 -246
+rect -972 -287 -950 -265
+rect -901 -272 -790 -265
+rect -954 -304 -950 -287
+rect -972 -337 -950 -304
+rect -901 -347 -790 -322
+<< mvnsubdiffcont >>
+rect -972 -304 -954 -287
+<< poly >>
+rect -941 -322 -901 -272
+rect -790 -322 -749 -272
+<< locali >>
+rect -975 -263 -952 -259
+rect -975 -280 -972 -263
+rect -955 -280 -952 -263
+rect -975 -287 -952 -280
+rect -975 -304 -972 -287
+rect -954 -304 -952 -287
+rect -975 -308 -952 -304
+rect -975 -325 -972 -308
+rect -955 -325 -952 -308
+rect -975 -328 -952 -325
+<< viali >>
+rect -972 -280 -955 -263
+rect -972 -325 -955 -308
+<< metal1 >>
+rect -977 -263 -951 -254
+rect -977 -280 -972 -263
+rect -955 -280 -951 -263
+rect -977 -308 -951 -280
+rect -977 -325 -972 -308
+rect -955 -325 -951 -308
+rect -977 -333 -951 -325
+<< end >>
diff --git a/mag/sky130_hilas_FGVaractorTunnelCap01.mag b/mag/sky130_hilas_FGVaractorTunnelCap01.mag
new file mode 100644
index 0000000..e4555b0
--- /dev/null
+++ b/mag/sky130_hilas_FGVaractorTunnelCap01.mag
@@ -0,0 +1,47 @@
+magic
+tech sky130A
+timestamp 1608049473
+<< error_p >>
+rect -901 -272 -895 -266
+rect -846 -272 -840 -266
+rect -907 -322 -901 -316
+rect -840 -322 -834 -316
+<< nwell >>
+rect -1005 -380 -783 -211
+<< mvvaractor >>
+rect -901 -322 -840 -272
+<< mvnsubdiff >>
+rect -972 -265 -840 -246
+rect -972 -287 -950 -265
+rect -901 -272 -840 -265
+rect -954 -304 -950 -287
+rect -972 -337 -950 -304
+rect -901 -347 -840 -322
+<< mvnsubdiffcont >>
+rect -972 -304 -954 -287
+<< poly >>
+rect -941 -322 -901 -272
+rect -840 -322 -800 -272
+<< locali >>
+rect -975 -263 -952 -259
+rect -975 -280 -972 -263
+rect -955 -280 -952 -263
+rect -975 -287 -952 -280
+rect -975 -304 -972 -287
+rect -954 -304 -952 -287
+rect -975 -308 -952 -304
+rect -975 -325 -972 -308
+rect -955 -325 -952 -308
+rect -975 -328 -952 -325
+<< viali >>
+rect -972 -280 -955 -263
+rect -972 -325 -955 -308
+<< metal1 >>
+rect -977 -263 -951 -254
+rect -977 -280 -972 -263
+rect -955 -280 -951 -263
+rect -977 -308 -951 -280
+rect -977 -325 -972 -308
+rect -955 -325 -951 -308
+rect -977 -333 -951 -325
+<< end >>
diff --git a/mag/sky130_hilas_FGcharacterization01.mag b/mag/sky130_hilas_FGcharacterization01.mag
new file mode 100644
index 0000000..660f1a5
--- /dev/null
+++ b/mag/sky130_hilas_FGcharacterization01.mag
@@ -0,0 +1,905 @@
+magic
+tech sky130A
+timestamp 1625074044
+<< error_s >>
+rect 52 825 81 841
+rect 131 825 160 841
+rect 210 825 239 841
+rect 289 825 318 841
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+rect 4 559 119 578
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+rect 1799 509 2073 859
+rect -409 427 -387 438
+<< mvnmos >>
+rect 1688 764 1751 814
+rect 1688 542 1751 592
+rect 1688 375 1750 452
+rect 1833 375 1897 430
+rect 1975 375 2039 430
+<< mvpmos >>
+rect 1836 738 1896 793
+rect 1976 738 2036 793
+rect 1836 571 1896 626
+rect 1976 571 2036 626
+<< mvndiff >>
+rect 1688 837 1751 841
+rect 1688 820 1694 837
+rect 1711 820 1728 837
+rect 1745 820 1751 837
+rect 1688 814 1751 820
+rect 1688 751 1751 764
+rect 1688 592 1751 597
+rect 1688 536 1751 542
+rect 1688 519 1693 536
+rect 1710 519 1727 536
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+rect 1688 513 1751 519
+rect 1688 475 1750 483
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+rect 1891 352 1897 369
+rect 1833 345 1897 352
+rect 1975 369 2039 375
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+rect 1998 352 2015 369
+rect 2032 352 2039 369
+rect 1975 346 2039 352
+<< mvpdiff >>
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+rect 1836 799 1840 816
+rect 1857 799 1874 816
+rect 1891 799 1896 816
+rect 1976 816 2036 822
+rect 1836 793 1896 799
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+rect 1836 649 1896 667
+rect 1836 632 1840 649
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+rect 1836 626 1896 632
+rect 1976 731 2036 738
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+rect 1891 548 1896 565
+rect 1836 542 1896 548
+rect 1976 565 2036 571
+rect 1976 548 1981 565
+rect 1998 548 2015 565
+rect 2032 548 2036 565
+rect 1976 542 2036 548
+<< mvndiffc >>
+rect 1694 820 1711 837
+rect 1728 820 1745 837
+rect 1693 519 1710 536
+rect 1727 519 1744 536
+rect 1693 458 1710 475
+rect 1727 458 1744 475
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+rect 1692 352 1709 369
+rect 1726 352 1743 369
+rect 1840 352 1857 369
+rect 1874 352 1891 369
+rect 1981 352 1998 369
+rect 2015 352 2032 369
+<< mvpdiffc >>
+rect 1840 799 1857 816
+rect 1874 799 1891 816
+rect 1981 799 1998 816
+rect 2015 799 2032 816
+rect 1840 714 1857 731
+rect 1874 714 1891 731
+rect 1840 632 1857 649
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+rect 1981 632 1998 649
+rect 2015 632 2032 649
+rect 1840 548 1857 565
+rect 1874 548 1891 565
+rect 1981 548 1998 565
+rect 2015 548 2032 565
+<< psubdiff >>
+rect -533 637 -199 642
+rect -533 620 -493 637
+rect -476 620 -459 637
+rect -442 620 -425 637
+rect -408 620 -391 637
+rect -374 620 -357 637
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+rect 448 603 487 636
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+rect 448 540 460 557
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+rect 448 519 487 540
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+rect 448 459 460 476
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+rect -533 410 -527 427
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+rect -533 393 -504 410
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+rect -533 359 -504 376
+rect -533 342 -527 359
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+rect 448 421 487 459
+rect 448 404 460 421
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+rect -533 330 -504 342
+rect 448 345 487 364
+rect 448 328 460 345
+rect 477 328 487 345
+rect 448 307 487 328
+rect 448 290 459 307
+rect 476 290 487 307
+rect 448 274 487 290
+<< mvpsubdiff >>
+rect 1689 302 2043 308
+rect 1689 301 1769 302
+rect 1689 284 1701 301
+rect 1718 284 1735 301
+rect 1752 285 1769 301
+rect 1786 285 1805 302
+rect 1822 285 1841 302
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+rect 1892 285 1909 302
+rect 1926 285 1943 302
+rect 1960 285 1977 302
+rect 1994 285 2011 302
+rect 2028 285 2043 302
+rect 1752 284 2043 285
+rect 1689 278 2043 284
+<< mvnsubdiff >>
+rect 311 688 352 696
+rect 311 675 323 688
+rect 297 671 323 675
+rect 340 671 352 688
+rect 297 654 352 671
+rect 297 637 323 654
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+rect 311 603 323 620
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+rect 1836 667 1896 673
+rect 1976 690 2036 697
+rect 1976 673 1997 690
+rect 2014 673 2036 690
+rect 1976 667 2036 673
+rect -409 427 -387 438
+<< psubdiffcont >>
+rect -493 620 -476 637
+rect -459 620 -442 637
+rect -425 620 -408 637
+rect -391 620 -374 637
+rect -357 620 -340 637
+rect -323 620 -306 637
+rect -289 620 -272 637
+rect -255 620 -238 637
+rect -527 580 -510 597
+rect -629 538 -612 555
+rect -595 538 -578 555
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+rect -527 546 -510 563
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+rect -527 444 -510 461
+rect 460 586 477 603
+rect 460 540 477 557
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+rect 460 459 477 476
+rect -527 410 -510 427
+rect -527 376 -510 393
+rect -527 342 -510 359
+rect 460 404 477 421
+rect 460 364 477 381
+rect 460 328 477 345
+rect 459 290 476 307
+<< mvpsubdiffcont >>
+rect 1701 284 1718 301
+rect 1735 284 1752 301
+rect 1769 285 1786 302
+rect 1805 285 1822 302
+rect 1841 285 1858 302
+rect 1875 285 1892 302
+rect 1909 285 1926 302
+rect 1943 285 1960 302
+rect 1977 285 1994 302
+rect 2011 285 2028 302
+<< mvnsubdiffcont >>
+rect 323 671 340 688
+rect 323 637 340 654
+rect 323 603 340 620
+rect 1857 673 1874 690
+rect 1997 673 2014 690
+<< poly >>
+rect -708 746 -680 796
+rect -705 679 -680 746
+rect -186 716 -137 803
+rect -186 714 8 716
+rect 291 714 342 715
+rect 365 714 561 801
+rect 1476 764 1688 814
+rect 1751 764 1764 814
+rect 1912 793 1932 815
+rect 2050 793 2068 814
+rect 1476 750 1528 764
+rect 1822 738 1836 793
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+rect 1960 738 1976 793
+rect 2036 738 2068 793
+rect -186 679 160 714
+rect -817 655 160 679
+rect -817 476 -779 655
+rect -186 559 160 655
+rect 1734 658 1781 692
+rect 1765 592 1781 658
+rect 1912 626 1932 738
+rect 2051 626 2068 738
+rect 291 577 342 578
+rect 279 559 342 577
+rect -186 558 8 559
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+rect -186 433 -137 558
+rect 1673 542 1688 592
+rect 1751 543 1781 592
+rect 1822 571 1836 626
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+rect 2036 571 2068 626
+rect 1751 542 1759 543
+rect 1776 495 1814 496
+rect -186 404 103 433
+rect 1758 457 1814 495
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+rect -186 349 -137 404
+rect 1673 375 1688 452
+rect 1750 437 1779 452
+rect 1750 375 1764 437
+rect 1817 375 1833 430
+rect 1897 375 1975 430
+rect 2039 375 2051 430
+<< locali >>
+rect 1686 820 1694 837
+rect 1745 820 1753 837
+rect 1973 816 2073 817
+rect 1832 799 1840 816
+rect 1891 799 1933 816
+rect 1973 799 1981 816
+rect 2032 799 2073 816
+rect 1832 714 1840 731
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+rect 2032 714 2040 731
+rect 323 688 340 696
+rect 1840 673 1857 690
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+rect 2014 673 2022 690
+rect 323 661 340 671
+rect 323 654 383 661
+rect -527 637 -510 639
+rect 340 637 383 654
+rect -527 620 -493 637
+rect -476 620 -459 637
+rect -442 620 -425 637
+rect -408 620 -391 637
+rect -374 620 -357 637
+rect -340 620 -323 637
+rect -306 620 -289 637
+rect -272 620 -255 637
+rect -238 620 -221 637
+rect 323 635 383 637
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+rect 460 603 477 614
+rect -527 563 -510 580
+rect -637 538 -629 555
+rect -612 538 -595 555
+rect -578 538 -561 555
+rect -544 546 -527 555
+rect -544 538 -510 546
+rect -527 529 -510 538
+rect -527 495 -510 512
+rect -527 461 -510 478
+rect -527 427 -510 444
+rect -527 393 -510 410
+rect -527 359 -510 376
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+rect 1832 548 1840 565
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+rect 460 519 477 540
+rect 1685 519 1693 536
+rect 1710 519 1727 536
+rect 1744 519 1799 536
+rect 460 476 477 502
+rect 460 421 477 459
+rect 1685 458 1693 475
+rect 1744 458 1752 475
+rect 1832 436 1840 453
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+rect 2032 436 2040 453
+rect 460 381 477 404
+rect 460 349 477 364
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+rect 1709 352 1726 369
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+rect 1857 352 1874 369
+rect 1891 352 1981 369
+rect 1998 352 2015 369
+rect 2032 352 2041 369
+rect -527 297 -510 342
+rect 459 345 477 349
+rect 459 328 460 345
+rect 459 307 477 328
+rect 476 290 477 307
+rect 1710 302 1778 307
+rect 1710 301 1769 302
+rect 459 276 477 290
+rect 1693 284 1701 301
+rect 1718 284 1735 301
+rect 1752 285 1769 301
+rect 1786 285 1805 302
+rect 1822 285 1841 302
+rect 1858 285 1875 302
+rect 1892 285 1909 302
+rect 1926 285 1943 302
+rect 1960 285 1977 302
+rect 1994 285 2011 302
+rect 2028 285 2036 302
+rect 1752 284 1778 285
+<< viali >>
+rect 1711 820 1728 837
+rect 1857 799 1874 816
+rect 1998 799 2015 816
+rect 1857 714 1874 731
+rect 1998 714 2015 731
+rect 1874 673 1891 690
+rect 1980 673 1997 690
+rect 1857 632 1874 649
+rect 1998 632 2015 649
+rect 1857 548 1874 565
+rect 1998 548 2015 565
+rect 1710 458 1727 475
+rect 1857 436 1874 453
+rect 1998 436 2015 453
+<< metal1 >>
+rect -884 775 -858 864
+rect -414 739 -387 864
+rect 173 823 197 864
+rect 1705 837 1734 840
+rect 1705 820 1711 837
+rect 1728 820 1734 837
+rect 1705 817 1734 820
+rect 1781 816 1884 824
+rect 1781 799 1857 816
+rect 1874 799 1884 816
+rect 1781 793 1884 799
+rect 1987 816 2025 824
+rect 1987 799 1998 816
+rect 2015 799 2025 816
+rect 1987 793 2025 799
+rect 1706 748 1733 761
+rect 1697 739 1733 748
+rect 1697 719 1739 739
+rect 1697 625 1720 719
+rect 1697 607 1733 625
+rect -805 277 -780 464
+rect -806 259 -780 277
+rect -415 259 -384 518
+rect 1706 478 1733 607
+rect 1781 516 1805 793
+rect 1854 731 1877 737
+rect 1854 714 1857 731
+rect 1874 714 1877 731
+rect 1994 731 2018 737
+rect 1994 714 1998 731
+rect 2015 714 2018 731
+rect 1849 690 2024 714
+rect 1849 673 1874 690
+rect 1891 673 1980 690
+rect 1997 673 2024 690
+rect 1849 649 2024 673
+rect 1849 648 1857 649
+rect 1854 632 1857 648
+rect 1874 648 1998 649
+rect 1874 632 1877 648
+rect 1854 626 1877 632
+rect 1994 632 1998 648
+rect 2015 648 2024 649
+rect 2015 632 2018 648
+rect 1994 626 2018 632
+rect 1854 565 1877 571
+rect 1854 548 1857 565
+rect 1874 548 1877 565
+rect 1700 475 1733 478
+rect 1700 458 1710 475
+rect 1727 458 1733 475
+rect 1700 455 1733 458
+rect 1854 453 1877 548
+rect 174 259 198 447
+rect 1854 436 1857 453
+rect 1874 436 1877 453
+rect 1854 430 1877 436
+rect 1995 565 2018 571
+rect 1995 548 1998 565
+rect 2015 548 2018 565
+rect 1995 453 2018 548
+rect 1995 436 1998 453
+rect 2015 436 2018 453
+rect 1995 430 2018 436
+rect 1505 259 1534 365
+<< metal2 >>
+rect 1704 817 1993 841
+rect 351 718 1816 731
+rect 351 710 2083 718
+rect 174 640 204 686
+rect 247 641 277 687
+rect 385 643 409 710
+rect 1802 693 2083 710
+rect 1738 559 1765 687
+rect 1816 642 2083 693
+rect 1738 558 2017 559
+rect 1738 536 2083 558
+rect 1790 535 2083 536
+rect 2021 487 2083 519
+rect 1780 448 2083 471
+rect 1695 321 2083 354
+rect 1694 312 2083 321
+rect 1695 305 2083 312
+rect 1719 287 1763 305
+rect -531 266 1792 287
+use sky130_hilas_li2m2 sky130_hilas_li2m2_14
+timestamp 1607089160
+transform 1 0 -520 0 1 283
+box -14 -15 20 18
+use sky130_hilas_FGVaractorCapacitor02 sky130_hilas_FGVaractorCapacitor02_0
+timestamp 1606868103
+transform 1 0 563 0 1 673
+box -1005 -380 -733 -211
+use sky130_hilas_FGVaractorCapacitor02 sky130_hilas_FGVaractorCapacitor02_2
+timestamp 1606868103
+transform 1 0 563 0 1 774
+box -1005 -380 -733 -211
+use sky130_hilas_overlapCap02a sky130_hilas_overlapCap02a_1
+timestamp 1607261501
+transform 1 0 506 0 1 468
+box -521 -54 -121 110
+use sky130_hilas_overlapCap02a sky130_hilas_overlapCap02a_2
+timestamp 1607261501
+transform 1 0 506 0 1 313
+box -521 -54 -121 110
+use sky130_hilas_FGVaractorCapacitor02 sky130_hilas_FGVaractorCapacitor02_1
+timestamp 1606868103
+transform 1 0 563 0 1 1073
+box -1005 -380 -733 -211
+use sky130_hilas_overlapCap02a sky130_hilas_overlapCap02a_0
+timestamp 1607261501
+transform 1 0 506 0 1 748
+box -521 -54 -121 110
+use sky130_hilas_FGVaractorTunnelCap01 sky130_hilas_FGVaractorTunnelCap01_0
+timestamp 1608049473
+transform 1 0 93 0 1 1068
+box -1005 -380 -783 -211
+use sky130_hilas_nOverlapCap01 sky130_hilas_nOverlapCap01_0
+timestamp 1607262215
+transform 1 0 -795 0 1 395
+box -62 -43 67 86
+use sky130_hilas_pFETdevice01 sky130_hilas_pFETdevice01_0
+timestamp 1607471549
+transform 1 0 224 0 1 655
+box -79 -78 82 43
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 466 0 1 281
+box -14 -15 20 18
+use sky130_hilas_FGHugeVaractorCapacitor01 sky130_hilas_FGHugeVaractorCapacitor01_0
+timestamp 1608043965
+transform 1 0 1099 0 1 1077
+box -556 -816 473 -217
+use sky130_hilas_li2m2 sky130_hilas_li2m2_13
+timestamp 1607089160
+transform 1 0 189 0 1 654
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_12
+timestamp 1607089160
+transform 1 0 258 0 1 655
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_11
+timestamp 1607089160
+transform 1 0 394 0 1 647
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_9
+timestamp 1607089160
+transform 1 0 1706 0 1 298
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_4
+timestamp 1607089160
+transform 1 0 1792 0 1 359
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_5
+timestamp 1607089160
+transform 1 0 1777 0 1 299
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_6
+timestamp 1607089160
+transform 1 0 1851 0 1 299
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_3
+timestamp 1607089160
+transform 1 0 1935 0 1 357
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_7
+timestamp 1607089160
+transform 1 0 1921 0 1 299
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_8
+timestamp 1607089160
+transform 1 0 2014 0 1 299
+box -14 -15 20 18
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 1791 0 1 524
+box -10 -8 13 21
+use sky130_hilas_li2m2 sky130_hilas_li2m2_10
+timestamp 1607089160
+transform -1 0 1795 0 -1 479
+box -14 -15 20 18
+use sky130_hilas_poly2li sky130_hilas_poly2li_5
+timestamp 1607178257
+transform -1 0 1805 0 -1 480
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_3
+timestamp 1607178257
+transform 1 0 1921 0 1 440
+box -9 -14 18 19
+use sky130_hilas_m12m2 sky130_hilas_m12m2_9
+timestamp 1607949437
+transform 1 0 2000 0 1 497
+box -9 -10 23 22
+use sky130_hilas_nDiffThOxContact sky130_hilas_nDiffThOxContact_3
+timestamp 1608039004
+transform 1 0 1712 0 1 580
+box -26 13 41 42
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_0
+timestamp 1607270276
+transform 1 0 1743 0 1 666
+box -9 -26 24 29
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607949437
+transform 1 0 1859 0 1 676
+box -9 -10 23 22
+use sky130_hilas_m12m2 sky130_hilas_m12m2_4
+timestamp 1607949437
+transform 1 0 1857 0 1 634
+box -9 -10 23 22
+use sky130_hilas_m12m2 sky130_hilas_m12m2_6
+timestamp 1607949437
+transform 1 0 1859 0 1 720
+box -9 -10 23 22
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 1933 0 1 637
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_2
+timestamp 1607089160
+transform 1 0 1933 0 1 721
+box -14 -15 20 18
+use sky130_hilas_m12m2 sky130_hilas_m12m2_1
+timestamp 1607949437
+transform 1 0 2000 0 1 674
+box -9 -10 23 22
+use sky130_hilas_m12m2 sky130_hilas_m12m2_2
+timestamp 1607949437
+transform 1 0 2000 0 1 719
+box -9 -10 23 22
+use sky130_hilas_m12m2 sky130_hilas_m12m2_3
+timestamp 1607949437
+transform 1 0 2000 0 1 632
+box -9 -10 23 22
+use sky130_hilas_nDiffThOxContact sky130_hilas_nDiffThOxContact_0
+timestamp 1608039004
+transform 1 0 1712 0 1 723
+box -26 13 41 42
+use sky130_hilas_m12m2 sky130_hilas_m12m2_10
+timestamp 1607949437
+transform 1 0 1713 0 1 827
+box -9 -10 23 22
+use sky130_hilas_poly2li sky130_hilas_poly2li_1
+timestamp 1607178257
+transform 1 0 1920 0 1 828
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_4
+timestamp 1607178257
+transform 1 0 2060 0 1 828
+box -9 -14 18 19
+use sky130_hilas_m12m2 sky130_hilas_m12m2_7
+timestamp 1607949437
+transform 1 0 1999 0 1 822
+box -9 -10 23 22
+<< labels >>
+rlabel metal2 2077 305 2083 354 0 VGND
+port 8 nsew ground default
+rlabel metal2 2077 487 2083 519 0 OUTPUT
+port 10 nsew analog default
+rlabel metal2 2076 642 2083 718 0 VINJ
+port 9 nsew power default
+rlabel metal2 2077 448 2083 471 0 VBIAS
+port 12 nsew analog default
+rlabel metal2 2077 535 2083 558 0 VREF
+port 11 nsew analog default
+rlabel metal1 1505 261 1534 266 0 LARGECAPACITOR
+port 7 nsew analog default
+rlabel metal1 173 858 197 864 0 GATE3
+port 3 nsew analog default
+rlabel metal1 174 259 198 266 0 GATE4
+port 6 nsew analog default
+rlabel metal1 -415 259 -384 266 0 GATE2
+port 5 nsew analog default
+rlabel metal1 -414 855 -387 864 0 GATE1
+port 2 nsew analog default
+rlabel metal1 -806 259 -780 269 0 VTUNOVERLAP01
+port 4 nsew analog default
+rlabel metal1 -884 857 -858 864 0 VTUN
+port 1 nsew analog default
+rlabel metal2 174 675 204 686 0 DRAIN1
+port 13 nsew
+rlabel metal2 247 676 276 687 0 SOURCE1
+port 14 nsew
+<< end >>
diff --git a/mag/sky130_hilas_FGtrans2x1cell.mag b/mag/sky130_hilas_FGtrans2x1cell.mag
new file mode 100644
index 0000000..55ebc99
--- /dev/null
+++ b/mag/sky130_hilas_FGtrans2x1cell.mag
@@ -0,0 +1,286 @@
+magic
+tech sky130A
+timestamp 1625491133
+<< error_s >>
+rect -338 150 -332 156
+rect -285 150 -279 156
+rect -344 100 -338 106
+rect -279 100 -273 106
+rect 38 91 44 97
+rect 143 91 149 97
+rect 32 41 38 47
+rect 149 41 155 47
+rect 38 -210 44 -204
+rect 143 -210 149 -204
+rect -338 -264 -332 -258
+rect -285 -264 -279 -258
+rect 32 -260 38 -254
+rect 149 -260 155 -254
+rect -344 -314 -338 -308
+rect -279 -314 -273 -308
+<< nwell >>
+rect -337 -242 -281 0
+rect -361 -381 -319 -374
+<< psubdiff >>
+rect -95 -42 -70 121
+rect -95 -59 -92 -42
+rect -73 -59 -70 -42
+rect -95 -72 -70 -59
+rect -95 -75 268 -72
+rect -95 -76 146 -75
+rect -95 -93 -71 -76
+rect -52 -93 -28 -76
+rect -9 -93 16 -76
+rect 35 -93 56 -76
+rect 75 -93 100 -76
+rect 119 -92 146 -76
+rect 165 -76 268 -75
+rect 165 -92 190 -76
+rect 119 -93 190 -92
+rect 209 -93 236 -76
+rect 255 -93 268 -76
+rect -95 -97 268 -93
+rect -95 -110 -70 -97
+rect -95 -127 -92 -110
+rect -73 -127 -70 -110
+rect -95 -281 -70 -127
+<< mvnsubdiff >>
+rect -337 -242 -281 0
+<< psubdiffcont >>
+rect -92 -59 -73 -42
+rect -71 -93 -52 -76
+rect -28 -93 -9 -76
+rect 16 -93 35 -76
+rect 56 -93 75 -76
+rect 100 -93 119 -76
+rect 146 -92 165 -75
+rect 190 -93 209 -76
+rect 236 -93 255 -76
+rect -92 -127 -73 -110
+<< poly >>
+rect -237 134 331 151
+rect -237 126 -185 134
+rect -2 91 20 134
+rect 166 91 188 134
+rect 276 51 314 101
+rect 276 -210 291 51
+rect 384 -28 398 -27
+rect 384 -131 406 -28
+rect 276 -233 316 -210
+rect 272 -238 316 -233
+rect 272 -255 280 -238
+rect 297 -255 316 -238
+rect 272 -260 316 -255
+rect -3 -293 17 -260
+rect 169 -293 189 -260
+rect 272 -263 300 -260
+rect -280 -310 331 -293
+<< polycont >>
+rect 280 -255 297 -238
+<< locali >>
+rect 386 163 474 180
+rect 386 124 403 163
+rect 364 107 403 124
+rect 444 107 466 124
+rect 221 28 329 45
+rect 362 28 470 45
+rect -92 -42 -73 -34
+rect 464 -51 472 -34
+rect -92 -75 -73 -59
+rect -92 -76 146 -75
+rect -92 -93 -71 -76
+rect -52 -93 -28 -76
+rect -9 -93 16 -76
+rect 35 -93 56 -76
+rect 75 -93 100 -76
+rect 119 -92 146 -76
+rect 165 -76 263 -75
+rect 165 -92 190 -76
+rect 119 -93 190 -92
+rect 209 -93 236 -76
+rect 255 -93 263 -76
+rect -92 -110 -73 -93
+rect 338 -108 355 -51
+rect 356 -111 364 -110
+rect 422 -111 427 -110
+rect 356 -115 427 -111
+rect 354 -119 427 -115
+rect -92 -135 -73 -127
+rect 347 -131 431 -119
+rect 464 -125 469 -108
+rect 206 -204 330 -187
+rect 362 -204 470 -187
+rect 280 -236 297 -230
+rect 280 -264 297 -257
+rect 364 -267 410 -266
+rect 363 -282 410 -267
+rect 364 -283 410 -282
+rect 445 -283 466 -266
+rect 391 -317 410 -283
+rect 391 -335 487 -317
+<< viali >>
+rect 278 -238 299 -236
+rect 278 -255 280 -238
+rect 280 -255 297 -238
+rect 297 -255 299 -238
+rect 278 -257 299 -255
+<< metal1 >>
+rect -361 -382 -319 223
+rect -113 -382 -90 223
+rect 279 -230 297 223
+rect 274 -236 303 -230
+rect 274 -257 278 -236
+rect 299 -257 303 -236
+rect 274 -264 303 -257
+rect 279 -382 297 -264
+rect 384 -382 405 223
+rect 427 -382 446 223
+rect 472 -56 493 223
+rect 661 217 680 223
+rect 705 218 721 223
+rect 621 -101 645 -59
+rect 472 -332 491 -107
+rect 522 -332 523 -331
+rect 469 -382 492 -332
+rect 661 -382 680 -377
+rect 705 -382 721 -377
+<< metal2 >>
+rect 484 173 516 175
+rect -395 155 516 173
+rect 749 155 757 173
+rect -395 0 576 19
+rect -395 -73 621 -69
+rect -395 -92 622 -73
+rect -395 -186 577 -167
+rect 510 -315 526 -313
+rect -395 -320 526 -315
+rect -395 -330 514 -320
+rect 749 -332 757 -314
+use sky130_hilas_FGVaractorCapacitor02 sky130_hilas_FGVaractorCapacitor02_0
+timestamp 1606868103
+transform -1 0 -752 0 1 62
+box -1005 -380 -733 -211
+use sky130_hilas_FGVaractorCapacitor02 sky130_hilas_FGVaractorCapacitor02_2
+timestamp 1606868103
+transform -1 0 -752 0 -1 -231
+box -1005 -380 -733 -211
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 -103 0 1 -92
+box -10 -8 13 21
+use sky130_hilas_wellContact sky130_hilas_wellContact_1
+timestamp 1606753443
+transform 1 0 1054 0 1 404
+box -1449 -441 -1275 -255
+use sky130_hilas_wellContact sky130_hilas_wellContact_0
+timestamp 1606753443
+transform 1 0 1054 0 1 231
+box -1449 -441 -1275 -255
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_1
+timestamp 1608066871
+transform 1 0 1056 0 1 19
+box -1451 -400 -1278 -210
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_3
+timestamp 1608066871
+transform 1 0 1056 0 1 433
+box -1451 -400 -1278 -210
+use sky130_hilas_poly2m1 sky130_hilas_poly2m1_0
+timestamp 1607270135
+transform 1 0 389 0 1 -74
+box -9 -26 24 25
+use sky130_hilas_li2m1 sky130_hilas_li2m1_1
+timestamp 1607179295
+transform 1 0 434 0 1 -123
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_3
+timestamp 1607179295
+transform 1 0 480 0 1 -141
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_2
+timestamp 1607179295
+transform 1 0 435 0 1 -281
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_5
+timestamp 1607179295
+transform 1 0 478 0 1 -332
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_6
+timestamp 1607179295
+transform 1 0 481 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_4
+timestamp 1607179295
+transform 1 0 434 0 1 109
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_7
+timestamp 1607179295
+transform 1 0 481 0 1 -34
+box -10 -8 13 21
+use sky130_hilas_horizTransCell01 sky130_hilas_horizTransCell01_1
+timestamp 1625488390
+transform 1 0 790 0 -1 270
+box -476 48 -33 359
+use sky130_hilas_horizTransCell01 sky130_hilas_horizTransCell01_0
+timestamp 1625488390
+transform 1 0 790 0 1 -429
+box -476 48 -33 359
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607949437
+transform 1 0 628 0 1 -85
+box -9 -10 23 22
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 563 0 1 -166
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 562 0 1 3
+box -14 -15 20 18
+<< labels >>
+rlabel metal1 -361 216 -319 223 0 VTUN
+port 11 nsew analog default
+rlabel metal1 -113 216 -90 223 0 VGND
+port 10 nsew ground default
+rlabel space 705 217 721 222 0 VINJ
+port 2 nsew analog default
+rlabel metal2 -395 -330 -391 -315 3 DRAIN2
+port 12 e analog default
+rlabel metal2 -395 155 -389 173 0 DRAIN1
+port 15 nsew analog default
+rlabel metal1 427 217 446 223 0 GATE1
+port 9 nsew analog default
+rlabel metal1 469 -381 492 -357 0 VIN2
+port 7 nsew analog default
+rlabel metal1 279 -382 297 -375 0 RUN
+port 6 nsew analog default
+rlabel metal1 384 -382 405 -375 0 PROG
+port 5 nsew analog default
+rlabel metal1 279 216 297 223 0 RUN
+port 6 nsew analog default
+rlabel metal1 384 217 405 223 0 PROG
+port 5 nsew analog default
+rlabel metal1 472 191 493 222 0 VIN1
+port 8 nsew analog default
+rlabel metal1 661 217 680 223 0 COLSEL1
+port 1 nsew analog default
+rlabel metal1 661 -382 680 -377 0 COLSEL1
+port 1 nsew analog default
+rlabel metal1 705 -382 721 -377 0 VINJ
+port 2 nsew analog default
+rlabel metal2 749 155 757 173 0 DRAIN1
+port 3 nsew analog default
+rlabel metal2 749 -332 757 -314 0 DRAIN2
+port 4 nsew analog default
+rlabel metal1 427 -381 446 -376 0 GATE1
+port 9 nsew analog default
+rlabel metal1 -113 -382 -90 -375 0 VGND
+port 10 nsew ground default
+rlabel metal1 -361 -381 -319 -374 0 VTUN
+port 11 nsew analog default
+rlabel metal2 -395 -92 -389 -69 0 COL1
+port 16 nsew
+rlabel metal2 -395 0 -389 19 0 ROW1
+port 17 nsew
+rlabel metal2 -395 -186 -389 -167 0 ROW2
+port 18 nsew
+<< end >>
diff --git a/mag/sky130_hilas_LeftProtection.mag b/mag/sky130_hilas_LeftProtection.mag
new file mode 100644
index 0000000..e838b1e
--- /dev/null
+++ b/mag/sky130_hilas_LeftProtection.mag
@@ -0,0 +1,135 @@
+magic
+tech sky130A
+timestamp 1626559870
+<< metal1 >>
+rect -898 27122 -834 27516
+rect -2065 26640 -1984 27030
+rect -898 24264 -834 24658
+rect -2065 23781 -1984 24171
+rect -897 21403 -833 21797
+rect -2065 20922 -1984 21312
+rect -898 18545 -834 18939
+rect -2064 18063 -1983 18453
+rect -897 15687 -833 16081
+rect -2065 15204 -1984 15594
+rect -898 12828 -834 13222
+rect -2065 12345 -1984 12735
+rect -898 9969 -834 10363
+rect -2065 9487 -1984 9877
+rect -898 7109 -834 7503
+rect -2063 6628 -1982 7018
+rect -898 4250 -834 4644
+rect -2064 3768 -1983 4158
+rect -899 1393 -835 1787
+rect -2064 909 -1983 1299
+rect -899 -1467 -835 -1073
+rect -2064 -1950 -1983 -1560
+rect -897 -4327 -833 -3933
+rect -2063 -4809 -1982 -4419
+rect -897 -7184 -833 -6790
+rect -2065 -7668 -1984 -7278
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_0
+timestamp 1626558701
+transform 0 -1 -1126 1 0 -7694
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_1
+timestamp 1626558701
+transform 0 -1 -1126 1 0 -4835
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_2
+timestamp 1626558701
+transform 0 -1 -1126 1 0 -1976
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_3
+timestamp 1626558701
+transform 0 -1 -1126 1 0 883
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_4
+timestamp 1626558701
+transform 0 -1 -1126 1 0 3742
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_6
+timestamp 1626558701
+transform 0 -1 -1126 1 0 6601
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_9
+timestamp 1626558701
+transform 0 -1 -1126 1 0 9460
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_7
+timestamp 1626558701
+transform 0 -1 -1126 1 0 12319
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_8
+timestamp 1626558701
+transform 0 -1 -1126 1 0 15178
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_5
+timestamp 1626558701
+transform 0 -1 -1126 1 0 18037
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_10
+timestamp 1626558701
+transform 0 -1 -1126 1 0 20896
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_11
+timestamp 1626558701
+transform 0 -1 -1126 1 0 23755
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_12
+timestamp 1626558701
+transform 0 -1 -1126 1 0 26614
+box -745 -229 2114 858
+<< labels >>
+rlabel metal1 -2065 26640 -1984 27030 0 IO25
+port 1 nsew
+rlabel metal1 -2065 23781 -1984 24171 0 IO26
+port 2 nsew
+rlabel metal1 -2065 20922 -1984 21312 0 IO27
+port 3 nsew
+rlabel metal1 -2064 18063 -1983 18453 0 IO28
+port 4 nsew
+rlabel metal1 -2065 15204 -1984 15594 0 IO29
+port 5 nsew
+rlabel metal1 -2065 12345 -1984 12735 0 IO30
+port 6 nsew
+rlabel metal1 -2065 9487 -1984 9877 0 IO31
+port 7 nsew
+rlabel metal1 -2063 6628 -1982 7018 0 IO32
+port 8 nsew
+rlabel metal1 -2064 3768 -1983 4158 0 IO33
+port 9 nsew
+rlabel metal1 -2064 909 -1983 1299 0 IO34
+port 10 nsew
+rlabel metal1 -2064 -1950 -1983 -1560 0 IO35
+port 11 nsew
+rlabel metal1 -2063 -4809 -1982 -4419 0 IO36
+port 12 nsew
+rlabel metal1 -2065 -7668 -1984 -7278 0 IO37
+port 13 nsew
+rlabel metal1 -898 27122 -834 27516 0 PIN1
+port 14 nsew
+rlabel metal1 -898 24264 -834 24658 0 PIN2
+port 15 nsew
+rlabel metal1 -897 21403 -833 21797 0 PIN3
+rlabel metal1 -898 18545 -834 18939 0 PIN4
+port 16 nsew
+rlabel metal1 -897 15687 -833 16081 0 PIN5
+port 17 nsew
+rlabel metal1 -898 12828 -834 13222 0 PIN6
+port 18 nsew
+rlabel metal1 -898 9969 -834 10363 0 PIN7
+port 19 nsew
+rlabel metal1 -898 7109 -834 7503 0 PIN8
+port 20 nsew
+rlabel metal1 -898 4250 -834 4644 0 PIN9
+port 21 nsew
+rlabel metal1 -899 1393 -835 1787 0 PIN10
+port 22 nsew
+rlabel metal1 -899 -1467 -835 -1073 0 PIN11
+port 23 nsew
+rlabel metal1 -897 -4327 -833 -3933 0 PIN12
+port 24 nsew
+rlabel metal1 -897 -7184 -833 -6790 0 PIN13
+port 25 nsew
+<< end >>
diff --git a/mag/sky130_hilas_LevelShift4InputUp.mag b/mag/sky130_hilas_LevelShift4InputUp.mag
new file mode 100644
index 0000000..5eada27
--- /dev/null
+++ b/mag/sky130_hilas_LevelShift4InputUp.mag
@@ -0,0 +1,65 @@
+magic
+tech sky130A
+timestamp 1624113741
+<< metal1 >>
+rect 4 517 33 522
+rect 445 515 476 522
+rect 746 517 770 522
+rect 4 -102 33 -97
+rect 445 -102 476 -96
+rect 746 -102 770 -97
+<< metal2 >>
+rect -30 470 -19 490
+rect 841 372 850 404
+rect -30 315 -19 335
+rect 841 217 850 249
+rect -30 160 -19 180
+rect 841 62 850 94
+rect -30 5 -19 25
+rect 841 -93 850 -61
+use sky130_hilas_StepUpDigital StepUpDigital_2
+timestamp 1624113415
+transform 1 0 -49 0 1 403
+box 19 -40 899 119
+use sky130_hilas_StepUpDigital StepUpDigital_1
+timestamp 1624113415
+transform 1 0 -49 0 1 248
+box 19 -40 899 119
+use sky130_hilas_StepUpDigital StepUpDigital_0
+timestamp 1624113415
+transform 1 0 -49 0 1 93
+box 19 -40 899 119
+use sky130_hilas_StepUpDigital StepUpDigital_3
+timestamp 1624113415
+transform 1 0 -49 0 1 -62
+box 19 -40 899 119
+<< labels >>
+rlabel metal2 841 372 850 404 0 INPUT1
+port 1 nsew
+rlabel metal2 841 217 850 249 0 INPUT2
+port 2 nsew
+rlabel metal2 841 62 850 94 0 INPUT3
+port 3 nsew
+rlabel metal2 841 -93 850 -61 0 INPUT4
+port 4 nsew
+rlabel metal1 746 517 770 522 0 VPWR
+port 5 nsew
+rlabel metal1 746 -102 770 -97 0 VPWR
+port 5 nsew
+rlabel metal1 4 517 33 522 0 VINJ
+port 6 nsew
+rlabel metal1 4 -102 33 -97 0 VINJ
+port 6 nsew
+rlabel metal2 -30 470 -19 490 0 OUTPUT1
+port 7 nsew
+rlabel metal2 -30 315 -19 335 0 OUTPUT2
+port 8 nsew
+rlabel metal2 -30 160 -19 180 0 OUTPUT3
+port 9 nsew
+rlabel metal2 -30 5 -19 25 0 OUTPUT4
+port 10 nsew
+rlabel metal1 445 515 476 522 0 VGND
+port 11 nsew
+rlabel metal1 445 -102 476 -96 0 VGND
+port 11 nsew
+<< end >>
diff --git a/mag/sky130_hilas_RightProtection.mag b/mag/sky130_hilas_RightProtection.mag
new file mode 100644
index 0000000..af753b0
--- /dev/null
+++ b/mag/sky130_hilas_RightProtection.mag
@@ -0,0 +1,76 @@
+magic
+tech sky130A
+timestamp 1626559870
+<< metal1 >>
+rect -2053 27123 -1982 27519
+rect -898 26641 -826 27030
+rect -2054 24263 -1984 24659
+rect -898 23782 -826 24171
+rect -2052 21404 -1982 21800
+rect -898 20922 -826 21311
+rect -2054 18545 -1984 18941
+rect -898 18065 -826 18454
+rect -2054 15685 -1984 16081
+rect -899 15205 -827 15594
+rect -2053 12827 -1983 13223
+rect -898 12346 -826 12735
+rect -2053 9967 -1983 10363
+rect -898 9486 -826 9875
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_9
+timestamp 1626558701
+transform 0 1 -1755 1 0 9460
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_7
+timestamp 1626558701
+transform 0 1 -1755 1 0 12319
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_8
+timestamp 1626558701
+transform 0 1 -1755 1 0 15178
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_5
+timestamp 1626558701
+transform 0 1 -1755 1 0 18037
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_10
+timestamp 1626558701
+transform 0 1 -1755 1 0 20896
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_11
+timestamp 1626558701
+transform 0 1 -1755 1 0 23755
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_12
+timestamp 1626558701
+transform 0 1 -1755 1 0 26614
+box -745 -229 2114 858
+<< labels >>
+rlabel metal1 -898 9486 -826 9875 0 IO7
+port 1 nsew
+rlabel metal1 -898 12346 -826 12735 0 IO8
+port 2 nsew
+rlabel metal1 -899 15205 -827 15594 0 IO9
+port 3 nsew
+rlabel metal1 -898 18065 -826 18454 0 IO10
+port 4 nsew
+rlabel metal1 -898 20922 -826 21311 0 IO11
+port 5 nsew
+rlabel metal1 -898 23782 -826 24171 0 IO12
+port 7 nsew
+rlabel metal1 -898 26641 -826 27030 0 IO13
+port 6 nsew
+rlabel metal1 -2053 9967 -1983 10363 0 PIN1
+port 8 nsew
+rlabel metal1 -2053 12827 -1983 13223 0 PIN2
+port 9 nsew
+rlabel metal1 -2054 15685 -1984 16081 0 PIN3
+port 10 nsew
+rlabel metal1 -2054 18545 -1984 18941 0 PIN4
+port 11 nsew
+rlabel metal1 -2052 21404 -1982 21800 0 PIN5
+port 12 nsew
+rlabel metal1 -2054 24263 -1984 24659 0 PIN6
+port 13 nsew
+rlabel metal1 -2053 27123 -1983 27519 0 PIN7
+port 14 nsew
+<< end >>
diff --git a/mag/sky130_hilas_StepUpDigital.mag b/mag/sky130_hilas_StepUpDigital.mag
new file mode 100644
index 0000000..6b1892b
--- /dev/null
+++ b/mag/sky130_hilas_StepUpDigital.mag
@@ -0,0 +1,112 @@
+magic
+tech sky130A
+timestamp 1624113415
+<< nwell >>
+rect 19 -40 270 119
+<< mvpmos >>
+rect 84 55 134 86
+rect 155 -7 205 24
+<< mvpdiff >>
+rect 53 79 84 86
+rect 53 62 61 79
+rect 78 62 84 79
+rect 53 55 84 62
+rect 134 80 168 86
+rect 134 63 140 80
+rect 157 63 168 80
+rect 134 55 168 63
+rect 124 16 155 24
+rect 124 -1 130 16
+rect 148 -1 155 16
+rect 124 -7 155 -1
+rect 205 18 237 24
+rect 205 1 211 18
+rect 229 1 237 18
+rect 205 -7 237 1
+<< mvpdiffc >>
+rect 61 62 78 79
+rect 140 63 157 80
+rect 130 -1 148 16
+rect 211 1 229 18
+<< mvnsubdiff >>
+rect 54 16 124 24
+rect 54 -1 80 16
+rect 97 -1 124 16
+rect 54 -7 124 -1
+<< mvnsubdiffcont >>
+rect 80 -1 97 16
+<< poly >>
+rect 84 88 255 104
+rect 84 86 134 88
+rect 228 60 255 88
+rect 84 40 134 55
+rect 228 43 233 60
+rect 250 43 255 60
+rect 155 24 205 39
+rect 228 35 255 43
+rect 155 -10 205 -7
+rect 155 -25 285 -10
+<< polycont >>
+rect 233 43 250 60
+<< locali >>
+rect 147 87 370 95
+rect 147 80 164 87
+rect 53 62 61 79
+rect 78 62 86 79
+rect 132 63 140 80
+rect 157 70 164 80
+rect 181 78 370 87
+rect 181 70 192 78
+rect 157 63 192 70
+rect 60 52 78 62
+rect 77 35 78 52
+rect 60 17 78 35
+rect 225 43 233 60
+rect 250 43 258 60
+rect 225 18 250 43
+rect 77 16 78 17
+rect 77 0 80 16
+rect 60 -1 80 0
+rect 97 -1 130 16
+rect 148 -1 156 16
+rect 203 1 211 18
+rect 229 8 250 18
+rect 229 7 267 8
+rect 229 1 285 7
+rect 211 -10 285 1
+<< viali >>
+rect 164 70 181 87
+rect 60 35 77 52
+rect 60 0 77 17
+<< metal1 >>
+rect 53 52 82 119
+rect 157 92 189 95
+rect 157 66 160 92
+rect 186 66 189 92
+rect 157 65 189 66
+rect 53 35 60 52
+rect 77 35 82 52
+rect 53 17 82 35
+rect 53 0 60 17
+rect 77 0 82 17
+rect 53 -40 82 0
+<< via1 >>
+rect 160 87 186 92
+rect 160 70 164 87
+rect 164 70 181 87
+rect 181 70 186 87
+rect 160 66 186 70
+<< metal2 >>
+rect 157 87 160 92
+rect 26 67 160 87
+rect 157 66 160 67
+rect 186 66 189 92
+use sky130_hilas_StepUpDigitalPart1 StepUpDigitalPart1_0
+timestamp 1624113415
+transform 1 0 7 0 1 0
+box 278 -40 892 119
+<< labels >>
+rlabel metal2 26 67 33 87 0 Output
+rlabel metal1 53 111 82 119 0 Vinj
+rlabel metal1 53 -40 82 -32 0 Vinj
+<< end >>
diff --git a/mag/sky130_hilas_StepUpDigitalPart1.mag b/mag/sky130_hilas_StepUpDigitalPart1.mag
new file mode 100644
index 0000000..e629345
--- /dev/null
+++ b/mag/sky130_hilas_StepUpDigitalPart1.mag
@@ -0,0 +1,251 @@
+magic
+tech sky130A
+timestamp 1624113415
+<< nwell >>
+rect 659 -40 836 119
+<< nmos >>
+rect 567 51 595 77
+rect 518 -11 546 14
+<< pmos >>
+rect 709 51 737 77
+rect 758 -11 786 14
+<< mvnmos >>
+rect 410 50 460 83
+rect 338 -17 389 15
+<< ndiff >>
+rect 533 72 567 77
+rect 533 55 544 72
+rect 561 55 567 72
+rect 533 51 567 55
+rect 595 72 624 77
+rect 595 55 601 72
+rect 618 55 624 72
+rect 595 51 624 55
+rect 489 10 518 14
+rect 489 -7 495 10
+rect 512 -7 518 10
+rect 489 -11 518 -7
+rect 546 10 575 14
+rect 546 -7 552 10
+rect 569 -7 575 10
+rect 546 -11 575 -7
+<< pdiff >>
+rect 678 72 709 77
+rect 678 55 684 72
+rect 702 55 709 72
+rect 678 51 709 55
+rect 737 72 773 77
+rect 737 55 743 72
+rect 760 55 773 72
+rect 737 51 773 55
+rect 729 10 758 14
+rect 729 -7 735 10
+rect 752 -7 758 10
+rect 729 -11 758 -7
+rect 786 10 817 14
+rect 786 -7 793 10
+rect 810 -7 817 10
+rect 786 -11 817 -7
+<< mvndiff >>
+rect 382 75 410 83
+rect 382 58 386 75
+rect 404 58 410 75
+rect 382 50 410 58
+rect 460 75 491 83
+rect 460 58 466 75
+rect 484 58 491 75
+rect 460 50 491 58
+rect 306 7 338 15
+rect 306 -10 313 7
+rect 331 -10 338 7
+rect 306 -17 338 -10
+rect 389 5 420 15
+rect 389 -12 395 5
+rect 413 -12 420 5
+rect 389 -17 420 -12
+<< ndiffc >>
+rect 544 55 561 72
+rect 601 55 618 72
+rect 495 -7 512 10
+rect 552 -7 569 10
+<< pdiffc >>
+rect 684 55 702 72
+rect 743 55 760 72
+rect 735 -7 752 10
+rect 793 -7 810 10
+<< mvndiffc >>
+rect 386 58 404 75
+rect 466 58 484 75
+rect 313 -10 331 7
+rect 395 -12 413 5
+<< psubdiff >>
+rect 491 72 533 77
+rect 491 55 503 72
+rect 520 55 533 72
+rect 491 51 533 55
+<< nsubdiff >>
+rect 773 72 818 77
+rect 773 55 785 72
+rect 802 55 818 72
+rect 773 51 818 55
+<< psubdiffcont >>
+rect 503 55 520 72
+<< nsubdiffcont >>
+rect 785 55 802 72
+<< poly >>
+rect 410 85 595 100
+rect 340 77 368 85
+rect 410 83 460 85
+rect 340 65 345 77
+rect 302 60 345 65
+rect 363 60 368 77
+rect 302 50 368 60
+rect 567 77 595 85
+rect 709 77 737 93
+rect 302 33 317 50
+rect 410 37 460 50
+rect 567 42 595 51
+rect 709 42 737 51
+rect 287 18 317 33
+rect 287 -10 303 18
+rect 338 15 389 29
+rect 278 -25 303 -10
+rect 518 14 546 33
+rect 567 32 737 42
+rect 567 27 642 32
+rect 634 15 642 27
+rect 659 27 737 32
+rect 659 15 667 27
+rect 434 -1 461 14
+rect 338 -19 389 -17
+rect 434 -18 439 -1
+rect 456 -18 461 -1
+rect 634 9 667 15
+rect 758 14 786 31
+rect 843 -6 881 4
+rect 434 -19 461 -18
+rect 338 -34 461 -19
+rect 518 -19 546 -11
+rect 758 -19 786 -11
+rect 843 -19 853 -6
+rect 518 -23 853 -19
+rect 870 -23 881 -6
+rect 518 -34 881 -23
+<< polycont >>
+rect 345 60 363 77
+rect 642 15 659 32
+rect 439 -18 456 -1
+rect 853 -23 870 -6
+<< locali >>
+rect 345 77 363 85
+rect 635 80 670 82
+rect 363 75 409 77
+rect 363 60 386 75
+rect 345 58 386 60
+rect 404 58 413 75
+rect 458 58 466 75
+rect 484 72 504 75
+rect 635 72 641 80
+rect 484 58 503 72
+rect 345 52 363 58
+rect 487 55 503 58
+rect 520 55 544 72
+rect 561 55 569 72
+rect 593 55 601 72
+rect 618 59 641 72
+rect 662 72 670 80
+rect 662 59 684 72
+rect 618 55 684 59
+rect 702 55 710 72
+rect 735 55 743 72
+rect 760 55 785 72
+rect 802 55 811 72
+rect 487 41 513 55
+rect 395 24 513 41
+rect 788 54 811 55
+rect 788 39 815 54
+rect 278 -10 313 7
+rect 331 -10 340 7
+rect 395 5 413 24
+rect 487 10 513 24
+rect 634 32 667 36
+rect 634 15 642 32
+rect 659 15 667 32
+rect 634 10 667 15
+rect 788 22 792 39
+rect 809 22 815 39
+rect 788 10 815 22
+rect 395 -20 413 -12
+rect 437 -1 458 7
+rect 437 -18 439 -1
+rect 456 -18 458 -1
+rect 487 -7 495 10
+rect 512 -7 520 10
+rect 544 -7 552 10
+rect 569 -7 735 10
+rect 752 -7 760 10
+rect 785 -7 793 10
+rect 810 -7 818 10
+rect 853 -4 870 2
+rect 487 -12 504 -7
+rect 785 -8 818 -7
+rect 437 -26 458 -18
+rect 853 -31 870 -26
+<< viali >>
+rect 641 59 662 80
+rect 792 22 809 39
+rect 851 -6 873 -4
+rect 851 -23 853 -6
+rect 853 -23 870 -6
+rect 870 -23 873 -6
+rect 851 -26 873 -23
+<< metal1 >>
+rect 434 10 462 13
+rect 434 -16 435 10
+rect 461 -16 462 10
+rect 434 -20 462 -16
+rect 487 -40 518 119
+rect 635 82 670 84
+rect 635 56 639 82
+rect 665 56 670 82
+rect 635 55 670 56
+rect 650 53 670 55
+rect 788 39 812 119
+rect 788 22 792 39
+rect 809 22 812 39
+rect 788 -40 812 22
+rect 845 -2 886 2
+rect 845 -28 849 -2
+rect 875 -28 886 -2
+rect 845 -31 886 -28
+<< via1 >>
+rect 435 -16 461 10
+rect 639 80 665 82
+rect 639 59 641 80
+rect 641 59 662 80
+rect 662 59 665 80
+rect 639 56 665 59
+rect 849 -4 875 -2
+rect 849 -26 851 -4
+rect 851 -26 873 -4
+rect 873 -26 875 -4
+rect 849 -28 875 -26
+<< metal2 >>
+rect 639 82 665 85
+rect 431 10 465 11
+rect 431 -16 435 10
+rect 461 5 465 10
+rect 639 5 665 56
+rect 461 -16 675 5
+rect 431 -17 675 -16
+rect 846 -2 892 1
+rect 846 -28 849 -2
+rect 875 -28 892 -2
+rect 846 -31 892 -28
+<< labels >>
+rlabel metal2 885 -31 892 1 0 Input
+rlabel metal1 788 115 812 119 0 Vdd
+rlabel metal1 788 -40 812 -36 0 Vdd
+rlabel metal1 487 115 518 119 0 GND
+rlabel metal1 487 -40 518 -35 0 GND
+<< end >>
diff --git a/mag/sky130_hilas_TA2Cell_1FG.mag b/mag/sky130_hilas_TA2Cell_1FG.mag
new file mode 100644
index 0000000..8df5d95
--- /dev/null
+++ b/mag/sky130_hilas_TA2Cell_1FG.mag
@@ -0,0 +1,245 @@
+magic
+tech sky130A
+timestamp 1625491133
+<< error_s >>
+rect -1580 672 -1574 678
+rect -1527 672 -1521 678
+rect -1415 672 -1409 678
+rect -1362 672 -1356 678
+rect -1586 622 -1580 628
+rect -1521 622 -1515 628
+rect -1421 622 -1415 628
+rect -1356 622 -1350 628
+rect -2055 613 -2049 619
+rect -1950 613 -1944 619
+rect -992 613 -986 619
+rect -887 613 -881 619
+rect -2061 563 -2055 569
+rect -1944 563 -1938 569
+rect -998 563 -992 569
+rect -881 563 -875 569
+rect -1187 428 -1170 429
+rect -1187 411 -1170 412
+rect -1749 394 -1748 407
+rect -2055 312 -2049 318
+rect -1950 312 -1944 318
+rect -992 312 -986 318
+rect -887 312 -881 318
+rect -2061 262 -2055 268
+rect -1944 262 -1938 268
+rect -1580 258 -1574 264
+rect -1527 258 -1521 264
+rect -1415 258 -1409 264
+rect -1362 258 -1356 264
+rect -998 262 -992 268
+rect -881 262 -875 268
+rect -1586 208 -1580 214
+rect -1521 208 -1515 214
+rect -1421 208 -1415 214
+rect -1356 208 -1350 214
+<< nwell >>
+rect -2616 744 -2418 745
+rect -320 744 -173 745
+rect 65 727 193 745
+rect -2616 677 -2609 695
+rect -2616 190 -2608 208
+rect 65 140 193 159
+<< locali >>
+rect -1767 480 -1747 488
+rect -1767 463 -1766 480
+rect -1749 463 -1747 480
+rect -1767 411 -1747 463
+rect -1767 394 -1765 411
+rect -1748 394 -1747 411
+rect -1767 387 -1747 394
+rect -1192 480 -1163 488
+rect -1192 463 -1187 480
+rect -1170 463 -1163 480
+rect -1192 412 -1163 463
+rect -1192 395 -1187 412
+rect -1170 395 -1163 412
+rect -1192 387 -1163 395
+<< viali >>
+rect -1766 463 -1749 480
+rect -1765 394 -1748 411
+rect -1187 463 -1170 480
+rect -1187 395 -1170 412
+<< metal1 >>
+rect -2592 740 -2564 745
+rect -2592 739 -2560 740
+rect -2539 739 -2520 745
+rect -2592 713 -2589 739
+rect -2563 713 -2560 739
+rect -1891 736 -1868 744
+rect -1769 736 -1746 744
+rect -1540 729 -1396 745
+rect -1190 736 -1167 745
+rect -1068 737 -1045 745
+rect -416 737 -397 745
+rect -372 740 -344 745
+rect -372 738 -340 740
+rect -2592 712 -2560 713
+rect -372 712 -369 738
+rect -343 712 -340 738
+rect -3 731 31 745
+rect 63 730 91 745
+rect -372 710 -340 712
+rect -1768 432 -1736 434
+rect -1768 404 -1765 432
+rect -1739 406 -1736 432
+rect -1748 404 -1736 406
+rect -1198 426 -1166 429
+rect -1198 400 -1195 426
+rect -1169 400 -1166 426
+rect -1198 397 -1187 400
+rect -1170 397 -1166 400
+rect -154 187 -121 189
+rect -1198 174 -1166 176
+rect -1198 148 -1195 174
+rect -1169 148 -1166 174
+rect -154 161 -151 187
+rect -124 161 -121 187
+rect -154 160 -121 161
+rect -1198 146 -1166 148
+rect -155 159 -3 160
+rect -155 146 31 159
+rect -416 140 -397 145
+rect -372 140 -344 145
+rect -3 140 31 146
+rect 64 140 91 161
+<< via1 >>
+rect -2589 713 -2563 739
+rect -369 712 -343 738
+rect -1765 411 -1739 432
+rect -1765 406 -1748 411
+rect -1748 406 -1739 411
+rect -1195 412 -1169 426
+rect -1195 400 -1187 412
+rect -1187 400 -1170 412
+rect -1170 400 -1169 412
+rect -1195 148 -1169 174
+rect -151 161 -124 187
+<< metal2 >>
+rect -2592 739 -2560 740
+rect -2592 713 -2589 739
+rect -2563 728 -2560 739
+rect -372 738 -340 740
+rect -372 728 -369 738
+rect -2563 713 -369 728
+rect -2592 712 -369 713
+rect -343 712 -340 738
+rect -260 718 -229 742
+rect -2592 710 -340 712
+rect -2616 677 -2609 695
+rect -149 655 -127 657
+rect -1726 617 -1642 637
+rect -154 621 -127 655
+rect -1681 570 -667 592
+rect -328 571 -293 593
+rect -1686 473 -785 495
+rect -1768 432 -1736 434
+rect -1768 406 -1765 432
+rect -1739 429 -1736 432
+rect -1739 426 -1166 429
+rect -1739 406 -1195 426
+rect -1768 404 -1195 406
+rect -1198 400 -1195 404
+rect -1169 400 -1166 426
+rect -1198 397 -1166 400
+rect -1681 295 -1115 317
+rect -1731 265 -1683 266
+rect -1731 241 -1642 265
+rect -1137 262 -1115 295
+rect -807 312 -785 473
+rect -689 450 -667 570
+rect -147 564 -127 565
+rect -147 531 -125 564
+rect -145 530 -125 531
+rect -252 451 -220 475
+rect 182 474 193 497
+rect -692 446 -667 450
+rect -692 382 -666 446
+rect 182 392 193 414
+rect -692 361 -279 382
+rect -300 347 -279 361
+rect -300 326 -113 347
+rect -807 290 -522 312
+rect -700 262 -113 267
+rect -1137 246 -113 262
+rect -1137 240 -661 246
+rect -2616 190 -2608 208
+rect -154 187 -121 189
+rect -1198 175 -1166 176
+rect -154 175 -151 187
+rect -1198 174 -151 175
+rect -1198 148 -1195 174
+rect -1169 161 -151 174
+rect -124 161 -121 187
+rect -1169 159 -121 161
+rect -1169 158 -1129 159
+rect -1169 148 -1166 158
+rect -1198 146 -1166 148
+use sky130_hilas_FGBias2x1cell sky130_hilas_FGBias2x1cell_0
+timestamp 1625491133
+transform 1 0 -1077 0 1 522
+box -396 -382 757 223
+use sky130_hilas_FGBiasWeakGate2x1cell sky130_hilas_FGBiasWeakGate2x1cell_0
+timestamp 1625491133
+transform -1 0 -1859 0 1 522
+box -396 -382 757 223
+use sky130_hilas_pTransistorPair sky130_hilas_pTransistorPair_1
+timestamp 1608384750
+transform 1 0 -454 0 -1 305
+box 133 -440 320 165
+use sky130_hilas_DualTACore01 sky130_hilas_DualTACore01_0
+timestamp 1608069483
+transform 1 0 38 0 1 181
+box -172 -22 155 550
+<< labels >>
+rlabel metal2 -1726 617 -1690 636 0 VIN11
+port 2 nsew analog default
+rlabel metal2 -1731 241 -1695 266 0 VIN12
+port 1 nsew analog default
+rlabel metal1 -3 739 31 745 0 VGND
+port 7 nsew analog default
+rlabel metal1 63 739 91 745 0 VPWR
+port 6 nsew analog default
+rlabel metal1 64 140 91 146 0 VPWR
+port 6 nsew power default
+rlabel metal1 -3 140 31 146 0 VGND
+port 7 nsew ground default
+rlabel metal2 -252 451 -220 475 0 VIN21
+port 3 nsew analog default
+rlabel metal2 -260 718 -229 742 1 VIN22
+port 4 n analog default
+rlabel metal1 -372 737 -344 745 0 VINJ
+port 8 nsew power default
+rlabel metal1 -372 140 -344 145 0 VINJ
+port 8 nsew power default
+rlabel metal2 182 474 193 497 0 OUTPUT1
+port 9 nsew analog default
+rlabel metal2 182 392 193 414 0 OUTPUT2
+port 10 nsew analog default
+rlabel metal2 -2616 677 -2609 695 0 DRAIN1
+port 11 nsew
+rlabel metal2 -2616 190 -2608 208 0 DRAIN2
+port 12 nsew
+rlabel metal1 -2592 738 -2564 745 0 VINJ
+port 8 nsew
+rlabel metal1 -2539 739 -2520 745 0 COLSEL2
+port 13 nsew
+rlabel metal1 -1891 736 -1868 744 0 GATE2
+port 14 nsew
+rlabel metal1 -1769 736 -1746 744 0 VGND
+port 7 nsew
+rlabel metal1 -1068 737 -1045 745 0 GATE1
+port 15 nsew
+rlabel metal1 -1190 737 -1167 745 0 VGND
+port 7 nsew
+rlabel metal1 -416 737 -397 745 0 COLSEL1
+port 16 nsew
+rlabel metal1 -416 140 -397 145 0 COLSEL1
+port 16 nsew
+rlabel metal1 -1498 733 -1438 745 0 VTUN
+port 17 nsew
+<< end >>
diff --git a/mag/sky130_hilas_TA2Cell_1FG_Strong.mag b/mag/sky130_hilas_TA2Cell_1FG_Strong.mag
new file mode 100644
index 0000000..dd4b59c
--- /dev/null
+++ b/mag/sky130_hilas_TA2Cell_1FG_Strong.mag
@@ -0,0 +1,210 @@
+magic
+tech sky130A
+timestamp 1626460134
+<< error_s >>
+rect -1581 672 -1575 678
+rect -1528 672 -1522 678
+rect -1415 672 -1409 678
+rect -1362 672 -1356 678
+rect -1587 622 -1581 628
+rect -1522 622 -1516 628
+rect -1421 622 -1415 628
+rect -1356 622 -1350 628
+rect -2009 613 -2003 619
+rect -1904 613 -1898 619
+rect -992 613 -986 619
+rect -887 613 -881 619
+rect -2015 563 -2009 569
+rect -1898 563 -1892 569
+rect -998 563 -992 569
+rect -881 563 -875 569
+rect -2009 312 -2003 318
+rect -1904 312 -1898 318
+rect -992 312 -986 318
+rect -887 312 -881 318
+rect -2015 262 -2009 268
+rect -1898 262 -1892 268
+rect -1581 258 -1575 264
+rect -1528 258 -1522 264
+rect -1415 258 -1409 264
+rect -1362 258 -1356 264
+rect -998 262 -992 268
+rect -881 262 -875 268
+rect -1587 208 -1581 214
+rect -1522 208 -1516 214
+rect -1421 208 -1415 214
+rect -1356 208 -1350 214
+<< nwell >>
+rect -2617 744 -2286 745
+rect -320 744 -186 745
+rect -2597 713 -2565 743
+rect -370 713 -338 743
+rect 65 727 193 745
+rect 65 140 193 159
+<< metal1 >>
+rect -2581 743 -2565 745
+rect -2597 741 -2565 743
+rect -2597 715 -2594 741
+rect -2568 715 -2565 741
+rect -2540 739 -2521 745
+rect -2353 734 -2332 745
+rect -2306 737 -2287 745
+rect -2265 739 -2244 745
+rect -2157 738 -2139 745
+rect -1541 730 -1499 745
+rect -1438 730 -1396 745
+rect -1068 737 -1045 745
+rect -416 737 -397 745
+rect -372 743 -344 745
+rect -372 741 -338 743
+rect -372 737 -367 741
+rect -1541 716 -1396 730
+rect -2597 713 -2565 715
+rect -370 715 -367 737
+rect -341 715 -338 741
+rect -3 731 31 745
+rect 63 730 91 745
+rect -370 713 -338 715
+rect -156 188 -124 190
+rect -1775 173 -1743 175
+rect -2352 141 -2329 153
+rect -1775 147 -1772 173
+rect -1746 147 -1743 173
+rect -1775 145 -1743 147
+rect -1195 173 -1163 175
+rect -1195 147 -1192 173
+rect -1166 147 -1163 173
+rect -156 162 -153 188
+rect -127 162 -124 188
+rect -156 160 -124 162
+rect -156 159 -2 160
+rect -156 154 31 159
+rect -1195 145 -1163 147
+rect -151 146 31 154
+rect -416 140 -397 145
+rect -372 140 -344 145
+rect -3 140 31 146
+rect 64 140 91 161
+<< via1 >>
+rect -2594 715 -2568 741
+rect -367 715 -341 741
+rect -1772 147 -1746 173
+rect -1192 147 -1166 173
+rect -153 162 -127 188
+<< metal2 >>
+rect -2597 741 -2565 743
+rect -2597 715 -2594 741
+rect -2568 731 -2565 741
+rect -370 741 -338 743
+rect -370 731 -367 741
+rect -2568 715 -367 731
+rect -341 715 -338 741
+rect -260 718 -229 742
+rect -2597 713 -338 715
+rect -2617 677 -2609 695
+rect -149 655 -127 657
+rect -154 621 -127 655
+rect -328 571 -293 593
+rect -147 564 -127 565
+rect -1466 522 -667 542
+rect -147 531 -125 564
+rect -145 530 -125 531
+rect -807 454 -785 455
+rect -1465 429 -782 454
+rect -689 450 -667 522
+rect -252 451 -220 475
+rect 182 474 193 497
+rect -1465 337 -1114 356
+rect -1137 277 -1114 337
+rect -811 312 -782 429
+rect -692 446 -667 450
+rect -692 382 -666 446
+rect 182 392 193 414
+rect -692 361 -279 382
+rect -300 347 -279 361
+rect -300 326 -113 347
+rect -811 290 -522 312
+rect -811 289 -782 290
+rect -1137 262 -1115 277
+rect -700 262 -113 267
+rect -1137 246 -113 262
+rect -1137 240 -661 246
+rect -2617 190 -2609 208
+rect -156 188 -124 190
+rect -156 175 -153 188
+rect -1775 173 -153 175
+rect -1775 147 -1772 173
+rect -1746 160 -1192 173
+rect -1746 147 -1743 160
+rect -1775 145 -1743 147
+rect -1195 147 -1192 160
+rect -1166 162 -153 173
+rect -127 162 -124 188
+rect -1166 160 -124 162
+rect -1166 147 -1163 160
+rect -1195 145 -1163 147
+use sky130_hilas_DualTACore01 sky130_hilas_DualTACore01_0
+timestamp 1608069483
+transform 1 0 38 0 1 181
+box -172 -22 155 550
+use sky130_hilas_pTransistorPair sky130_hilas_pTransistorPair_1
+timestamp 1608384750
+transform 1 0 -454 0 -1 305
+box 133 -440 320 165
+use sky130_hilas_FGBias2x1cell sky130_hilas_FGBias2x1cell_0
+timestamp 1625491133
+transform 1 0 -1077 0 1 522
+box -396 -382 757 223
+use sky130_hilas_FGtrans2x1cell sky130_hilas_FGtrans2x1cell_0
+timestamp 1625491133
+transform -1 0 -1860 0 1 522
+box -395 -382 757 223
+<< labels >>
+rlabel metal1 -3 739 31 745 0 VGND
+port 11 nsew
+rlabel metal1 63 739 91 745 0 VPWR
+port 10 nsew
+rlabel metal1 64 140 91 146 0 VPWR
+port 10 nsew
+rlabel metal1 -3 140 31 146 0 VGND
+port 11 nsew
+rlabel metal2 -252 451 -220 475 0 VIN21
+port 9 nsew
+rlabel metal2 -260 718 -229 742 1 VIN22
+port 8 n
+rlabel metal1 -2352 141 -2329 153 0 VIN12
+port 18 nsew
+rlabel metal1 -2353 734 -2332 745 0 VIN11
+port 5 nsew
+rlabel metal1 -1438 738 -1396 745 0 VTUN
+port 1 nsew
+rlabel metal1 -1541 738 -1499 745 0 VTUN
+rlabel metal1 -2265 739 -2244 745 0 PROG
+port 3 nsew
+rlabel metal1 -2581 739 -2565 745 0 VINJ
+port 6 nsew
+rlabel metal1 -372 737 -344 745 0 VINJ
+port 6 nsew
+rlabel metal2 182 474 193 497 0 OUTPUT1
+port 13 nsew
+rlabel metal2 182 392 193 414 0 OUTPUT2
+port 12 nsew
+rlabel metal1 -2540 739 -2521 745 0 GATESEL1
+port 14 nsew
+rlabel metal1 -416 140 -397 145 0 GATESEL2
+port 15 nsew
+rlabel metal1 -372 140 -344 145 0 VINJ
+port 6 nsew
+rlabel metal1 -416 737 -397 745 0 GATESEL2
+port 15 nsew
+rlabel metal2 -2617 677 -2609 695 0 DRAIN1
+port 16 nsew
+rlabel metal2 -2617 190 -2609 208 0 DRAIN2
+port 17 nsew
+rlabel metal1 -1068 737 -1045 745 0 GATE1
+port 4 nsew
+rlabel metal1 -2306 737 -2287 745 0 GATE2
+port 19 nsew
+rlabel metal1 -2157 738 -2139 745 0 RUN
+port 20 nsew
+<< end >>
diff --git a/mag/sky130_hilas_TA2Cell_NoFG.mag b/mag/sky130_hilas_TA2Cell_NoFG.mag
new file mode 100644
index 0000000..2d27ac9
--- /dev/null
+++ b/mag/sky130_hilas_TA2Cell_NoFG.mag
@@ -0,0 +1,138 @@
+magic
+tech sky130A
+timestamp 1625491133
+<< error_s >>
+rect -1415 672 -1409 678
+rect -1362 672 -1356 678
+rect -1421 622 -1415 628
+rect -1356 622 -1350 628
+rect -992 613 -986 619
+rect -887 613 -881 619
+rect -998 563 -992 569
+rect -881 563 -875 569
+rect -992 312 -986 318
+rect -887 312 -881 318
+rect -1415 258 -1409 264
+rect -1362 258 -1356 264
+rect -998 262 -992 268
+rect -881 262 -875 268
+rect -1421 208 -1415 214
+rect -1356 208 -1350 214
+<< nwell >>
+rect 192 727 319 745
+rect -328 571 -162 593
+rect -282 410 -254 434
+rect 191 140 319 159
+<< locali >>
+rect -1190 479 -1144 488
+rect -1190 462 -1187 479
+rect -1170 462 -1144 479
+rect -1190 410 -1144 462
+rect -1190 393 -1187 410
+rect -1170 393 -1144 410
+rect -1190 387 -1144 393
+<< viali >>
+rect -1187 462 -1170 479
+rect -1187 393 -1170 410
+<< metal1 >>
+rect -1438 738 -1396 745
+rect -1068 737 -1045 745
+rect -416 737 -397 745
+rect -372 737 -344 745
+rect 123 731 157 745
+rect 190 730 217 745
+rect -1194 484 -1156 488
+rect -1194 391 -1190 484
+rect -1161 391 -1156 484
+rect -1194 387 -1156 391
+rect 123 140 157 159
+rect 190 140 217 161
+<< via1 >>
+rect 127 579 153 605
+rect -1190 479 -1161 484
+rect -1190 462 -1187 479
+rect -1187 462 -1170 479
+rect -1170 462 -1161 479
+rect -1190 410 -1161 462
+rect -1190 393 -1187 410
+rect -1187 393 -1170 410
+rect -1170 393 -1161 410
+rect -1190 391 -1161 393
+<< metal2 >>
+rect -130 718 -105 744
+rect -1473 677 -1466 695
+rect -24 620 1 657
+rect 123 605 157 609
+rect 123 600 127 605
+rect -328 571 -162 593
+rect -112 581 127 600
+rect -112 524 -93 581
+rect 123 579 127 581
+rect 153 579 157 605
+rect 123 576 157 579
+rect -21 535 0 564
+rect -1191 505 -93 524
+rect -1191 487 -1172 505
+rect -1193 484 -1158 487
+rect -1193 391 -1190 484
+rect -1161 391 -1158 484
+rect 304 474 319 496
+rect -126 451 -101 474
+rect -282 410 -254 434
+rect 304 392 319 414
+rect -1193 388 -1158 391
+rect -177 327 0 347
+rect -334 278 -318 318
+rect -206 246 0 267
+rect -1473 192 -1465 207
+rect -286 142 -260 167
+use sky130_hilas_FGBias2x1cell sky130_hilas_FGBias2x1cell_0
+timestamp 1625491133
+transform 1 0 -1077 0 1 522
+box -396 -382 757 223
+use sky130_hilas_pTransistorPair sky130_hilas_pTransistorPair_0
+timestamp 1608384750
+transform 1 0 -484 0 1 580
+box 133 -440 320 165
+use sky130_hilas_pTransistorPair sky130_hilas_pTransistorPair_1
+timestamp 1608384750
+transform 1 0 -328 0 -1 305
+box 133 -440 320 165
+use sky130_hilas_DualTACore01 sky130_hilas_DualTACore01_0
+timestamp 1608069483
+transform 1 0 164 0 1 181
+box -172 -22 155 550
+<< labels >>
+rlabel metal1 123 140 157 146 0 VGND
+port 7 nsew ground default
+rlabel metal1 190 140 217 146 0 VPWR
+port 8 nsew power default
+rlabel metal1 123 740 157 745 0 VGND
+port 7 nsew ground default
+rlabel metal1 190 740 217 745 0 VPWR
+port 8 nsew power default
+rlabel metal2 -126 451 -101 474 0 VIN21
+port 3 nsew
+rlabel metal2 -286 142 -263 167 0 VIN12
+port 2 nsew analog default
+rlabel metal2 -130 718 -105 744 0 VIN22
+port 4 nsew
+rlabel metal2 304 392 319 414 0 OUTPUT1
+port 5 nsew
+rlabel metal2 304 474 319 496 0 OUTPUT2
+port 6 nsew
+rlabel metal1 -416 737 -397 745 0 COLSEL1
+port 1 nsew
+rlabel metal2 -1473 677 -1466 695 0 DRAIN1
+port 9 nsew
+rlabel metal2 -1473 192 -1465 207 0 DRAIN2
+port 10 nsew
+rlabel metal1 -1438 738 -1396 745 0 VTUN
+port 11 nsew
+rlabel metal1 -1068 737 -1045 745 0 GATE1
+port 12 nsew
+rlabel metal1 -372 737 -344 745 0 VINJ
+port 13 nsew
+rlabel metal2 -282 410 -259 434 0 VIN11
+port 14 nsew
+<< end >>
diff --git a/mag/sky130_hilas_TA2SignalBiasCell.mag b/mag/sky130_hilas_TA2SignalBiasCell.mag
new file mode 100644
index 0000000..a9a4008
--- /dev/null
+++ b/mag/sky130_hilas_TA2SignalBiasCell.mag
@@ -0,0 +1,249 @@
+magic
+tech sky130A
+timestamp 1625486632
+<< error_s >>
+rect 214 528 215 529
+<< nwell >>
+rect -569 744 -378 745
+rect -569 184 -9 744
+rect 191 727 319 745
+rect -569 166 -526 184
+rect -569 143 -498 166
+rect -569 141 -526 143
+rect 191 140 319 159
+<< nsubdiff >>
+rect -550 661 -519 698
+rect -550 644 -544 661
+rect -527 644 -519 661
+rect -550 627 -519 644
+rect -550 610 -544 627
+rect -527 610 -519 627
+rect -550 593 -519 610
+rect -550 576 -544 593
+rect -527 576 -519 593
+rect -550 559 -519 576
+rect -550 542 -544 559
+rect -527 542 -519 559
+rect -550 525 -519 542
+rect -550 508 -544 525
+rect -527 508 -519 525
+rect -550 493 -519 508
+rect -551 358 -519 391
+rect -551 341 -543 358
+rect -526 341 -519 358
+rect -551 324 -519 341
+rect -551 307 -543 324
+rect -526 307 -519 324
+rect -551 290 -519 307
+rect -551 273 -543 290
+rect -526 273 -519 290
+rect -551 256 -519 273
+rect -551 239 -543 256
+rect -526 239 -519 256
+rect -551 222 -519 239
+rect -551 205 -543 222
+rect -526 205 -519 222
+rect -551 190 -519 205
+<< nsubdiffcont >>
+rect -544 644 -527 661
+rect -544 610 -527 627
+rect -544 576 -527 593
+rect -544 542 -527 559
+rect -544 508 -527 525
+rect -543 341 -526 358
+rect -543 307 -526 324
+rect -543 273 -526 290
+rect -543 239 -526 256
+rect -543 205 -526 222
+<< locali >>
+rect -502 697 -468 698
+rect -527 673 -468 697
+rect -527 624 -485 673
+rect 196 598 198 615
+rect 215 598 221 615
+rect 196 561 221 598
+rect 196 545 217 561
+rect 196 528 198 545
+rect 215 528 217 545
+rect 196 526 217 528
+rect -544 491 -527 508
+rect -543 197 -526 205
+<< viali >>
+rect -544 661 -527 678
+rect -544 627 -527 644
+rect -485 656 -468 673
+rect -485 622 -468 639
+rect -544 593 -527 610
+rect -544 559 -527 576
+rect -544 525 -527 542
+rect 198 598 215 615
+rect 198 528 215 545
+rect -543 358 -526 375
+rect -543 324 -526 341
+rect -543 290 -526 307
+rect -543 256 -526 273
+rect -543 222 -526 239
+<< metal1 >>
+rect 123 731 157 745
+rect 190 730 217 745
+rect -547 698 -494 699
+rect -547 697 -468 698
+rect -547 691 -465 697
+rect -547 678 -535 691
+rect -547 661 -544 678
+rect -476 673 -465 691
+rect -547 644 -535 661
+rect -468 667 -465 673
+rect -468 656 -462 667
+rect -547 627 -544 644
+rect -476 639 -462 656
+rect -547 619 -535 627
+rect -468 638 -462 639
+rect -468 622 -465 638
+rect -476 619 -465 622
+rect -547 613 -465 619
+rect 193 615 225 619
+rect -547 610 -483 613
+rect -547 593 -544 610
+rect -527 593 -483 610
+rect -547 576 -483 593
+rect -547 559 -544 576
+rect -527 559 -483 576
+rect -547 542 -483 559
+rect -547 525 -544 542
+rect -527 525 -483 542
+rect 193 529 194 615
+rect 220 529 225 615
+rect 193 528 198 529
+rect 215 528 225 529
+rect 193 527 225 528
+rect 196 526 225 527
+rect -547 375 -483 525
+rect -547 358 -543 375
+rect -526 358 -483 375
+rect -547 341 -483 358
+rect -547 324 -543 341
+rect -526 324 -483 341
+rect -547 307 -483 324
+rect -547 290 -543 307
+rect -526 290 -483 307
+rect -547 273 -483 290
+rect -547 256 -543 273
+rect -526 256 -483 273
+rect -547 239 -483 256
+rect -547 222 -543 239
+rect -526 222 -483 239
+rect -547 195 -483 222
+rect -525 194 -483 195
+rect 123 140 157 159
+rect 190 140 217 161
+<< via1 >>
+rect -535 678 -476 691
+rect -535 661 -527 678
+rect -527 673 -476 678
+rect -527 661 -485 673
+rect -535 656 -485 661
+rect -485 656 -476 673
+rect -535 644 -476 656
+rect -535 627 -527 644
+rect -527 639 -476 644
+rect -527 627 -485 639
+rect -535 622 -485 627
+rect -485 622 -476 639
+rect -535 619 -476 622
+rect 194 598 198 615
+rect 198 598 215 615
+rect 215 598 220 615
+rect 194 545 220 598
+rect 194 529 198 545
+rect 198 529 215 545
+rect 215 529 220 545
+<< metal2 >>
+rect -490 698 -466 745
+rect -130 718 -105 744
+rect -542 691 -466 698
+rect -542 619 -535 691
+rect -476 663 -466 691
+rect -476 640 -88 663
+rect -476 619 -466 640
+rect -542 616 -466 619
+rect -542 615 -497 616
+rect -111 604 -88 640
+rect -24 620 1 657
+rect 191 615 224 619
+rect 191 604 194 615
+rect -381 571 -162 593
+rect -111 584 194 604
+rect -85 583 194 584
+rect -21 535 0 564
+rect 191 529 194 583
+rect 220 529 224 615
+rect 191 526 224 529
+rect 304 474 319 496
+rect -126 451 -101 474
+rect -568 410 -422 434
+rect -282 410 -254 434
+rect -568 409 -504 410
+rect 304 392 319 414
+rect -177 327 0 347
+rect -334 292 -318 310
+rect -336 291 -318 292
+rect -358 278 -318 291
+rect -358 229 -322 278
+rect -206 246 0 267
+rect -564 143 -399 166
+rect -286 142 -260 167
+<< rmetal2 >>
+rect -497 615 -466 616
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 -480 0 1 709
+box -14 -15 20 18
+use sky130_hilas_DualTACore01 sky130_hilas_DualTACore01_0
+timestamp 1608069483
+transform 1 0 164 0 1 181
+box -172 -22 155 550
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 -396 0 1 581
+box -14 -15 20 18
+use sky130_hilas_pTransistorPair sky130_hilas_pTransistorPair_2
+timestamp 1608384750
+transform 1 0 -659 0 1 580
+box 133 -440 320 165
+use sky130_hilas_pTransistorPair sky130_hilas_pTransistorPair_1
+timestamp 1608384750
+transform 1 0 -328 0 -1 305
+box 133 -440 320 165
+use sky130_hilas_pTransistorPair sky130_hilas_pTransistorPair_0
+timestamp 1608384750
+transform 1 0 -484 0 1 580
+box 133 -440 320 165
+<< labels >>
+rlabel metal1 123 140 157 146 0 VGND
+port 3 nsew ground default
+rlabel metal1 190 140 217 146 0 VPWR
+port 4 nsew power default
+rlabel metal1 123 740 157 745 0 VGND
+port 3 nsew ground default
+rlabel metal1 190 740 217 745 0 VPWR
+port 4 nsew power default
+rlabel metal2 -282 410 -259 434 0 VIN11
+port 7 nsew analog default
+rlabel metal2 -126 451 -101 474 0 VIN21
+port 6 nsew analog default
+rlabel metal2 -286 142 -263 167 0 VIN12
+port 8 nsew analog default
+rlabel metal2 -130 718 -105 744 0 VIN22
+port 5 nsew analog default
+rlabel metal2 304 392 319 414 0 VOUT_AMP1
+port 2 nsew analog default
+rlabel metal2 304 474 319 496 0 VOUT_AMP2
+port 1 nsew analog default
+rlabel metal2 -490 737 -466 745 0 VPWR
+port 4 nsew power default
+rlabel metal2 -526 410 -519 434 0 VBIAS1
+port 10 nsew analog default
+rlabel metal2 -526 143 -519 166 0 VBIAS2
+port 9 nsew analog default
+<< end >>
diff --git a/mag/sky130_hilas_TACoreBlock.mag b/mag/sky130_hilas_TACoreBlock.mag
new file mode 100644
index 0000000..5ffc3e5
--- /dev/null
+++ b/mag/sky130_hilas_TACoreBlock.mag
@@ -0,0 +1,61 @@
+magic
+tech sky130A
+timestamp 1607993916
+<< error_s >>
+rect -401 342 -395 348
+rect -296 342 -290 348
+rect -407 278 -401 284
+rect -290 278 -284 284
+rect -457 219 -234 220
+rect -31 195 44 213
+rect -31 131 -13 195
+rect 26 131 44 195
+rect -31 113 44 131
+rect -36 64 59 82
+rect -374 20 -368 26
+rect -321 20 -315 26
+rect -8 -18 -7 64
+rect 25 47 59 64
+rect -3 39 25 47
+rect -3 28 38 39
+rect -3 -18 19 28
+rect 25 10 59 28
+rect 68 21 74 27
+rect 173 21 179 27
+rect 20 -18 59 10
+rect -8 -19 59 -18
+rect -380 -30 -374 -24
+rect -315 -30 -309 -24
+rect 62 -29 68 -23
+rect 179 -29 185 -23
+<< nmos >>
+rect -8 10 25 39
+<< ndiff >>
+rect -8 39 25 64
+rect -8 4 25 10
+rect -8 -13 0 4
+rect 17 -13 25 4
+rect -8 -19 25 -13
+<< pdiff >>
+rect -13 131 26 195
+<< ndiffc >>
+rect 0 -13 17 4
+<< poly >>
+rect -21 10 -8 39
+rect 25 10 38 39
+<< locali >>
+rect -8 -13 0 4
+rect 17 -13 25 4
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_0
+timestamp 1607993916
+transform 1 0 1020 0 1 303
+box -1451 -400 -784 -210
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_0
+timestamp 1607386385
+transform 1 0 530 0 1 165
+box -289 47 -33 232
+use sky130_hilas_FGVaractorCapacitor sky130_hilas_FGVaractorCapacitor_0
+timestamp 1606741561
+transform 1 0 500 0 1 614
+box -957 -395 -734 -209
+<< end >>
diff --git a/mag/sky130_hilas_TACoreBlock2.mag b/mag/sky130_hilas_TACoreBlock2.mag
new file mode 100644
index 0000000..dce844d
--- /dev/null
+++ b/mag/sky130_hilas_TACoreBlock2.mag
@@ -0,0 +1,216 @@
+magic
+tech sky130A
+timestamp 1607028117
+<< error_p >>
+rect 85 -19 102 -18
+rect 109 -30 110 11
+rect 73 -42 77 -30
+rect 109 -42 114 -30
+rect 109 -58 110 -42
+rect 109 -90 110 -59
+rect 109 -148 110 -119
+<< nwell >>
+rect -61 112 158 285
+<< nmos >>
+rect -8 11 25 40
+rect 77 11 110 40
+rect -8 -119 25 -90
+rect 77 -119 110 -90
+<< pmos >>
+rect -40 164 28 194
+rect 64 164 132 194
+<< ndiff >>
+rect -8 64 25 68
+rect -8 47 0 64
+rect 17 47 25 64
+rect -8 40 25 47
+rect 77 64 110 68
+rect 77 47 85 64
+rect 102 47 110 64
+rect 77 40 110 47
+rect -8 4 25 11
+rect -8 -13 0 4
+rect 17 -13 25 4
+rect -8 -19 25 -13
+rect -8 -67 25 -60
+rect -8 -84 0 -67
+rect 17 -84 25 -67
+rect -8 -90 25 -84
+rect 77 4 110 11
+rect 77 -13 85 4
+rect 102 -13 110 4
+rect 77 -19 110 -13
+rect 77 -66 110 -59
+rect 77 -83 85 -66
+rect 102 -83 110 -66
+rect 77 -90 110 -83
+rect -8 -126 25 -119
+rect -8 -143 -1 -126
+rect 17 -143 25 -126
+rect -8 -147 25 -143
+rect 77 -125 110 -119
+rect 77 -142 84 -125
+rect 103 -142 110 -125
+rect 77 -148 110 -142
+<< pdiff >>
+rect -40 218 28 224
+rect -40 201 -32 218
+rect -14 201 4 218
+rect 22 201 28 218
+rect -40 194 28 201
+rect 64 218 132 224
+rect 64 201 72 218
+rect 90 201 109 218
+rect 128 201 132 218
+rect 64 194 132 201
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+rect -14 140 4 157
+rect 22 140 28 157
+rect -40 131 28 140
+rect 64 157 132 164
+rect 64 140 70 157
+rect 88 140 106 157
+rect 124 140 132 157
+rect 64 136 132 140
+rect 71 131 132 136
+<< ndiffc >>
+rect 0 47 17 64
+rect 85 47 102 64
+rect 0 -13 17 4
+rect 0 -84 17 -67
+rect 85 -13 102 4
+rect 85 -83 102 -66
+rect -1 -143 17 -126
+rect 84 -142 103 -125
+<< pdiffc >>
+rect -32 201 -14 218
+rect 4 201 22 218
+rect 72 201 90 218
+rect 109 201 128 218
+rect -32 140 -14 157
+rect 4 140 22 157
+rect 70 140 88 157
+rect 106 140 124 157
+<< psubdiff >>
+rect -8 -31 25 -19
+rect -8 -48 0 -31
+rect 17 -48 25 -31
+rect -8 -60 25 -48
+rect 77 -30 110 -19
+rect 77 -47 85 -30
+rect 102 -47 110 -30
+rect 77 -58 110 -47
+rect 77 -59 109 -58
+<< nsubdiff >>
+rect -40 253 28 265
+rect -40 236 -32 253
+rect -14 236 4 253
+rect 22 236 28 253
+rect -40 224 28 236
+rect 64 253 132 265
+rect 64 236 72 253
+rect 90 236 109 253
+rect 128 236 132 253
+rect 64 224 132 236
+<< psubdiffcont >>
+rect 0 -48 17 -31
+rect 85 -47 102 -30
+<< nsubdiffcont >>
+rect -32 236 -14 253
+rect 4 236 22 253
+rect 72 236 90 253
+rect 109 236 128 253
+<< poly >>
+rect -53 164 -40 194
+rect 28 164 64 194
+rect 132 164 145 194
+rect 36 120 53 164
+rect 30 112 57 120
+rect 30 95 35 112
+rect 52 95 57 112
+rect 30 87 57 95
+rect -33 11 -8 40
+rect 25 11 38 40
+rect 63 11 77 40
+rect 110 11 133 40
+rect -33 -90 -17 11
+rect 117 -90 133 11
+rect -33 -119 -8 -90
+rect 25 -119 38 -90
+rect 62 -119 77 -90
+rect 110 -119 133 -90
+rect -33 -158 -17 -119
+rect -33 -166 26 -158
+rect 117 -159 133 -119
+rect -33 -183 -1 -166
+rect 17 -183 26 -166
+rect -33 -189 26 -183
+rect 77 -167 133 -159
+rect 77 -184 86 -167
+rect 103 -184 133 -167
+rect 77 -189 133 -184
+<< polycont >>
+rect 35 95 52 112
+rect -1 -183 17 -166
+rect 86 -184 103 -167
+<< locali >>
+rect -40 236 -32 253
+rect -14 236 4 253
+rect 22 236 72 253
+rect 90 236 109 253
+rect 128 236 136 253
+rect -40 218 136 236
+rect -40 201 -32 218
+rect -14 201 4 218
+rect 22 201 72 218
+rect 90 201 109 218
+rect 128 201 136 218
+rect -40 140 -32 157
+rect -14 140 4 157
+rect 22 140 31 157
+rect 62 140 70 157
+rect 88 140 106 157
+rect 124 140 132 157
+rect -5 123 31 140
+rect -5 112 60 123
+rect -5 95 35 112
+rect 52 95 60 112
+rect -5 87 60 95
+rect -5 64 22 87
+rect 85 65 110 140
+rect 77 64 110 65
+rect -8 47 0 64
+rect 17 47 25 64
+rect 77 47 85 64
+rect 102 47 110 64
+rect -12 -13 0 4
+rect 17 -13 29 4
+rect -12 -20 29 -13
+rect 73 -13 85 4
+rect 102 -13 114 4
+rect 73 -20 114 -13
+rect -12 -30 114 -20
+rect -12 -31 85 -30
+rect -12 -48 0 -31
+rect 17 -47 85 -31
+rect 102 -47 114 -30
+rect 17 -48 114 -47
+rect -12 -58 114 -48
+rect -12 -67 29 -58
+rect -12 -84 0 -67
+rect 17 -84 29 -67
+rect 73 -66 114 -58
+rect 73 -83 85 -66
+rect 102 -83 114 -66
+rect -9 -143 -1 -126
+rect 17 -143 25 -126
+rect 76 -142 84 -125
+rect 103 -142 112 -125
+rect 76 -143 112 -142
+rect -1 -166 17 -143
+rect -1 -192 17 -183
+rect 84 -167 103 -143
+rect 84 -184 86 -167
+rect 84 -192 103 -184
+<< end >>
diff --git a/mag/sky130_hilas_Tgate4Double01.mag b/mag/sky130_hilas_Tgate4Double01.mag
new file mode 100644
index 0000000..f645529
--- /dev/null
+++ b/mag/sky130_hilas_Tgate4Double01.mag
@@ -0,0 +1,83 @@
+magic
+tech sky130A
+timestamp 1624821938
+<< metal1 >>
+rect 38 460 58 464
+rect 621 460 640 464
+rect 38 -141 58 -137
+rect 621 -141 640 -137
+<< metal2 >>
+rect -36 433 -31 453
+rect -36 385 -31 405
+rect -36 335 -30 355
+rect 665 335 672 355
+rect -36 270 -30 290
+rect 666 270 672 290
+rect -36 220 -31 240
+rect -36 172 -31 192
+rect -36 131 -31 151
+rect -36 83 -31 103
+rect -36 33 -30 53
+rect 666 33 672 53
+rect -36 -32 -30 -12
+rect 666 -32 672 -12
+rect -36 -82 -31 -62
+rect -36 -130 -31 -110
+use sky130_hilas_TgateDouble01 sky130_hilas_TgateDouble01_1
+timestamp 1608225149
+transform 1 0 227 0 1 40
+box -263 -181 445 -29
+use sky130_hilas_TgateDouble01 sky130_hilas_TgateDouble01_0
+timestamp 1608225149
+transform 1 0 227 0 -1 283
+box -263 -181 445 -29
+use sky130_hilas_TgateDouble01 sky130_hilas_TgateDouble01_3
+timestamp 1608225149
+transform 1 0 227 0 1 342
+box -263 -181 445 -29
+use sky130_hilas_TgateDouble01 sky130_hilas_TgateDouble01_2
+timestamp 1608225149
+transform 1 0 227 0 -1 -19
+box -263 -181 445 -29
+<< labels >>
+rlabel metal1 621 460 640 464 0 VPWR
+port 13 nsew
+rlabel metal1 38 460 58 464 0 VGND
+port 1 nsew ground default
+rlabel metal2 665 335 672 355 0 OUTPUT1
+port 17 nsew
+rlabel metal2 666 33 672 53 0 OUTPUT3
+port 15 nsew
+rlabel metal2 666 270 672 290 0 OUTPUT2
+port 16 nsew
+rlabel metal2 666 -32 672 -12 0 OUTPUT4
+port 14 nsew
+rlabel metal2 -36 335 -30 355 0 SELECT1
+port 4 nsew
+rlabel metal2 -36 270 -30 290 0 SELECT2
+port 5 nsew
+rlabel metal2 -36 33 -30 53 0 SELECT3
+port 8 nsew
+rlabel metal2 -36 -32 -30 -12 0 SELECT4
+port 10 nsew
+rlabel metal1 621 -141 640 -137 0 VGND
+port 1 nsew
+rlabel metal1 38 -141 58 -137 0 VPWR
+port 13 nsew
+rlabel metal2 -36 433 -31 453 0 INPUT1_1
+port 2 nsew
+rlabel metal2 -36 172 -31 192 0 INPUT1_2
+port 7 nsew
+rlabel metal2 -36 220 -31 240 0 INPUT2_2
+port 6 nsew
+rlabel metal2 -36 131 -31 151 0 INPUT1_3
+port 19 nsew
+rlabel metal2 -36 83 -31 103 0 INPUT2_3
+port 9 nsew
+rlabel metal2 -36 -82 -31 -62 0 INPUT2_4
+port 11 nsew
+rlabel metal2 -36 -130 -31 -110 0 INPUT1_4
+port 12 nsew
+rlabel metal2 -36 385 -31 405 0 INPUT2_1
+port 18 nsew
+<< end >>
diff --git a/mag/sky130_hilas_Tgate4Single01.mag b/mag/sky130_hilas_Tgate4Single01.mag
new file mode 100644
index 0000000..943a797
--- /dev/null
+++ b/mag/sky130_hilas_Tgate4Single01.mag
@@ -0,0 +1,71 @@
+magic
+tech sky130A
+timestamp 1608226321
+<< metal1 >>
+rect 38 460 58 464
+rect 389 458 408 464
+rect 38 -141 58 -137
+rect 389 -141 408 -135
+<< metal2 >>
+rect -36 433 -31 453
+rect -36 335 -30 355
+rect 433 335 440 355
+rect -36 270 -30 290
+rect 433 270 440 290
+rect -36 172 -31 192
+rect -36 131 -31 151
+rect -36 33 -30 53
+rect 433 33 440 53
+rect -36 -32 -30 -12
+rect 433 -32 440 -12
+rect -36 -130 -31 -110
+use sky130_hilas_TgateSingle01 sky130_hilas_TgateSingle01_2
+timestamp 1608225149
+transform 1 0 227 0 -1 -19
+box -263 -181 213 -29
+use sky130_hilas_TgateSingle01 sky130_hilas_TgateSingle01_3
+timestamp 1608225149
+transform 1 0 227 0 1 342
+box -263 -181 213 -29
+use sky130_hilas_TgateSingle01 sky130_hilas_TgateSingle01_0
+timestamp 1608225149
+transform 1 0 227 0 -1 283
+box -263 -181 213 -29
+use sky130_hilas_TgateSingle01 sky130_hilas_TgateSingle01_1
+timestamp 1608225149
+transform 1 0 227 0 1 40
+box -263 -181 213 -29
+<< labels >>
+rlabel metal2 -36 335 -30 355 0 SELECT1
+port 8 nsew analog default
+rlabel metal2 -36 270 -30 290 0 SELECT2
+port 7 nsew analog default
+rlabel metal2 -36 33 -30 53 0 SELECT3
+port 4 nsew analog default
+rlabel metal2 -36 -32 -30 -12 0 SELECT4
+port 3 nsew analog default
+rlabel metal1 38 -141 58 -137 0 VPWR
+port 2 nsew analog default
+rlabel metal2 -36 433 -31 453 0 INPUT1_1
+port 9 nsew analog default
+rlabel metal2 -36 172 -31 192 0 INPUT1_2
+port 6 nsew analog default
+rlabel metal2 -36 131 -31 151 0 INPUT1_3
+port 5 nsew analog default
+rlabel metal2 -36 -130 -31 -110 0 INPUT1_4
+port 1 nsew analog default
+rlabel metal1 389 458 408 464 0 VGND
+port 10 nsew ground default
+rlabel metal1 389 -141 408 -135 0 VGND
+port 10 nsew ground default
+rlabel metal2 433 335 440 355 0 OUTPUT1
+port 11 nsew analog default
+rlabel metal2 433 270 440 290 0 OUTPUT2
+port 12 nsew analog default
+rlabel metal2 433 33 440 53 0 OUTPUT3
+port 13 nsew analog default
+rlabel metal2 433 -32 440 -12 0 OUTPUT4
+port 14 nsew analog default
+rlabel metal1 38 460 58 464 0 VPWR
+port 2 nsew power default
+<< end >>
diff --git a/mag/sky130_hilas_TgateDouble01.mag b/mag/sky130_hilas_TgateDouble01.mag
new file mode 100644
index 0000000..14233c7
--- /dev/null
+++ b/mag/sky130_hilas_TgateDouble01.mag
@@ -0,0 +1,237 @@
+magic
+tech sky130A
+timestamp 1608225149
+<< nwell >>
+rect -251 -181 96 -29
+<< nmos >>
+rect 320 -94 360 -64
+rect 177 -157 217 -126
+rect 320 -157 360 -126
+<< pmos >>
+rect -138 -96 -98 -64
+rect -138 -157 -98 -126
+rect 9 -157 49 -126
+<< ndiff >>
+rect 291 -70 320 -64
+rect 291 -87 296 -70
+rect 313 -87 320 -70
+rect 291 -94 320 -87
+rect 360 -70 391 -64
+rect 360 -87 367 -70
+rect 384 -87 391 -70
+rect 360 -94 391 -87
+rect 145 -134 177 -126
+rect 145 -151 151 -134
+rect 168 -151 177 -134
+rect 145 -157 177 -151
+rect 217 -134 249 -126
+rect 217 -151 225 -134
+rect 242 -151 249 -134
+rect 217 -157 249 -151
+rect 291 -133 320 -126
+rect 291 -150 297 -133
+rect 314 -150 320 -133
+rect 291 -157 320 -150
+rect 360 -133 390 -126
+rect 360 -150 366 -133
+rect 383 -150 390 -133
+rect 360 -157 390 -150
+<< pdiff >>
+rect -167 -71 -138 -64
+rect -167 -88 -161 -71
+rect -144 -88 -138 -71
+rect -167 -96 -138 -88
+rect -98 -71 -70 -64
+rect -98 -88 -92 -71
+rect -75 -88 -70 -71
+rect -98 -96 -70 -88
+rect -168 -134 -138 -126
+rect -168 -151 -161 -134
+rect -144 -151 -138 -134
+rect -168 -157 -138 -151
+rect -98 -134 -71 -126
+rect -98 -151 -92 -134
+rect -75 -151 -71 -134
+rect -98 -157 -71 -151
+rect -20 -133 9 -126
+rect -20 -150 -14 -133
+rect 3 -150 9 -133
+rect -20 -157 9 -150
+rect 49 -133 78 -126
+rect 49 -150 55 -133
+rect 72 -150 78 -133
+rect 49 -157 78 -150
+<< ndiffc >>
+rect 296 -87 313 -70
+rect 367 -87 384 -70
+rect 151 -151 168 -134
+rect 225 -151 242 -134
+rect 297 -150 314 -133
+rect 366 -150 383 -133
+<< pdiffc >>
+rect -161 -88 -144 -71
+rect -92 -88 -75 -71
+rect -161 -151 -144 -134
+rect -92 -151 -75 -134
+rect -14 -150 3 -133
+rect 55 -150 72 -133
+<< psubdiff >>
+rect 417 -134 440 -122
+rect 417 -151 420 -134
+rect 437 -151 440 -134
+rect 417 -163 440 -151
+<< nsubdiff >>
+rect -227 -130 -195 -117
+rect -227 -147 -220 -130
+rect -203 -147 -195 -130
+rect -227 -159 -195 -147
+<< psubdiffcont >>
+rect 420 -151 437 -134
+<< nsubdiffcont >>
+rect -220 -147 -203 -130
+<< poly >>
+rect -234 -56 360 -40
+rect -138 -64 -98 -56
+rect 320 -64 360 -56
+rect -52 -83 -19 -77
+rect -138 -126 -98 -96
+rect -52 -100 -44 -83
+rect -27 -100 -19 -83
+rect -52 -103 -19 -100
+rect -52 -118 217 -103
+rect 9 -126 49 -118
+rect 177 -126 217 -118
+rect 320 -126 360 -94
+rect -138 -170 -98 -157
+rect 9 -170 49 -157
+rect 177 -170 217 -157
+rect 320 -170 360 -157
+<< polycont >>
+rect -44 -100 -27 -83
+<< locali >>
+rect -101 -71 296 -70
+rect -171 -83 -161 -71
+rect -188 -88 -161 -83
+rect -144 -88 -136 -71
+rect -101 -88 -92 -71
+rect -75 -83 296 -71
+rect -75 -88 -44 -83
+rect -188 -96 -169 -88
+rect -190 -99 -169 -96
+rect -191 -100 -169 -99
+rect -52 -100 -44 -88
+rect -27 -87 296 -83
+rect 313 -87 321 -70
+rect 359 -87 367 -70
+rect 384 -87 394 -70
+rect -27 -88 321 -87
+rect -27 -100 -19 -88
+rect 412 -91 437 -71
+rect -203 -105 -169 -100
+rect -216 -108 -169 -105
+rect -220 -111 -169 -108
+rect -220 -117 -171 -111
+rect -220 -122 -186 -117
+rect -220 -124 -194 -122
+rect -92 -124 -76 -110
+rect -220 -126 -197 -124
+rect -220 -130 -199 -126
+rect -152 -134 -134 -130
+rect -220 -158 -203 -147
+rect -169 -151 -161 -134
+rect -144 -151 -134 -134
+rect -92 -134 -75 -124
+rect -92 -159 -75 -151
+rect -14 -133 3 -125
+rect -14 -155 3 -150
+rect 55 -133 72 -124
+rect 55 -159 72 -150
+rect 151 -134 168 -129
+rect 151 -159 168 -151
+rect 225 -134 242 -122
+rect 225 -160 242 -151
+rect 297 -133 314 -125
+rect 363 -150 366 -133
+rect 383 -150 392 -133
+rect 420 -134 437 -91
+rect 297 -155 314 -150
+rect 420 -159 437 -151
+<< metal1 >>
+rect -189 -181 -169 -29
+rect -91 -107 -74 -80
+rect 54 -105 71 -78
+rect 226 -108 243 -74
+rect 346 -128 365 -53
+rect 394 -181 413 -29
+<< metal2 >>
+rect -263 -72 -202 -52
+rect -93 -72 445 -52
+rect -263 -122 174 -102
+rect -263 -170 314 -150
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607949437
+transform 1 0 -225 0 1 -62
+box -9 -10 23 22
+use sky130_hilas_poly2m1 sky130_hilas_poly2m1_0
+timestamp 1607270135
+transform 1 0 -236 0 1 -65
+box -9 -26 24 25
+use sky130_hilas_li2m1 sky130_hilas_li2m1_2
+timestamp 1607179295
+transform 1 0 -180 0 1 -86
+box -10 -8 13 21
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 -139 0 1 -119
+box -14 -15 20 18
+use sky130_hilas_m12m2 sky130_hilas_m12m2_1
+timestamp 1607949437
+transform 1 0 -86 0 1 -70
+box -9 -10 23 22
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 -83 0 1 -127
+box -10 -8 13 21
+use sky130_hilas_li2m2 sky130_hilas_li2m2_2
+timestamp 1607089160
+transform 1 0 -4 0 1 -156
+box -14 -15 20 18
+use sky130_hilas_m12m2 sky130_hilas_m12m2_2
+timestamp 1607949437
+transform 1 0 56 0 1 -69
+box -9 -10 23 22
+use sky130_hilas_li2m1 sky130_hilas_li2m1_3
+timestamp 1607179295
+transform 1 0 62 0 1 -125
+box -10 -8 13 21
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 153 0 1 -119
+box -14 -15 20 18
+use sky130_hilas_m12m2 sky130_hilas_m12m2_4
+timestamp 1607949437
+transform 1 0 231 0 1 -67
+box -9 -10 23 22
+use sky130_hilas_li2m1 sky130_hilas_li2m1_4
+timestamp 1607179295
+transform 1 0 233 0 1 -126
+box -10 -8 13 21
+use sky130_hilas_m12m2 sky130_hilas_m12m2_3
+timestamp 1607949437
+transform 1 0 335 0 1 -68
+box -9 -10 23 22
+use sky130_hilas_li2m2 sky130_hilas_li2m2_3
+timestamp 1607089160
+transform 1 0 304 0 1 -155
+box -14 -15 20 18
+use sky130_hilas_li2m1 sky130_hilas_li2m1_5
+timestamp 1607179295
+transform 1 0 356 0 1 -148
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_1
+timestamp 1607179295
+transform 1 0 402 0 1 -86
+box -10 -8 13 21
+<< labels >>
+rlabel metal2 439 -72 445 -52 0 output
+<< end >>
diff --git a/mag/sky130_hilas_TgateSingle01.mag b/mag/sky130_hilas_TgateSingle01.mag
new file mode 100644
index 0000000..b8d9802
--- /dev/null
+++ b/mag/sky130_hilas_TgateSingle01.mag
@@ -0,0 +1,89 @@
+magic
+tech sky130A
+timestamp 1608225149
+<< nwell >>
+rect -251 -102 25 -29
+rect -251 -119 -52 -102
+rect -251 -181 -53 -119
+<< pmos >>
+rect -138 -96 -98 -64
+<< pdiff >>
+rect -167 -71 -138 -64
+rect -167 -88 -161 -71
+rect -144 -88 -138 -71
+rect -167 -96 -138 -88
+rect -98 -71 -70 -64
+rect -98 -88 -92 -71
+rect -75 -88 -70 -71
+rect -98 -96 -70 -88
+<< pdiffc >>
+rect -161 -88 -144 -71
+rect -92 -88 -75 -71
+<< nsubdiff >>
+rect -227 -130 -195 -117
+rect -227 -147 -220 -130
+rect -203 -147 -195 -130
+rect -227 -159 -195 -147
+<< nsubdiffcont >>
+rect -220 -147 -203 -130
+<< poly >>
+rect -234 -56 25 -40
+rect -138 -64 -98 -56
+rect -52 -83 -19 -77
+rect -138 -118 -98 -96
+rect -52 -100 -44 -83
+rect -27 -100 -19 -83
+rect -52 -112 -19 -100
+<< polycont >>
+rect -44 -100 -27 -83
+<< locali >>
+rect -101 -71 25 -70
+rect -171 -83 -161 -71
+rect -188 -88 -161 -83
+rect -144 -88 -136 -71
+rect -101 -88 -92 -71
+rect -75 -83 25 -71
+rect -75 -88 -44 -83
+rect -188 -96 -169 -88
+rect -190 -99 -169 -96
+rect -191 -100 -169 -99
+rect -52 -100 -44 -88
+rect -27 -88 25 -83
+rect -27 -100 -19 -88
+rect -203 -105 -169 -100
+rect -216 -108 -169 -105
+rect -220 -111 -169 -108
+rect -220 -117 -171 -111
+rect -220 -122 -186 -117
+rect -220 -124 -194 -122
+rect -220 -126 -197 -124
+rect -220 -130 -199 -126
+rect -220 -158 -203 -147
+<< metal1 >>
+rect -189 -181 -169 -29
+<< metal2 >>
+rect -263 -72 -202 -52
+rect -176 -150 -64 -149
+rect -263 -170 -64 -150
+rect -176 -171 -64 -170
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607949437
+transform 1 0 -225 0 1 -62
+box -9 -10 23 22
+use sky130_hilas_TgateSingle01Part2 sky130_hilas_TgateSingle01Part2_0
+timestamp 1608225149
+transform 1 0 -71 0 1 0
+box -67 -181 96 -38
+use sky130_hilas_TgateSingle01Part1 sky130_hilas_TgateSingle01Part1_0
+timestamp 1608225149
+transform 1 0 -232 0 1 0
+box 257 -181 445 -29
+use sky130_hilas_li2m1 sky130_hilas_li2m1_2
+timestamp 1607179295
+transform 1 0 -180 0 1 -86
+box -10 -8 13 21
+use sky130_hilas_poly2m1 sky130_hilas_poly2m1_0
+timestamp 1607270135
+transform 1 0 -236 0 1 -65
+box -9 -26 24 25
+<< end >>
diff --git a/mag/sky130_hilas_TgateSingle01Part1.mag b/mag/sky130_hilas_TgateSingle01Part1.mag
new file mode 100644
index 0000000..134c1d0
--- /dev/null
+++ b/mag/sky130_hilas_TgateSingle01Part1.mag
@@ -0,0 +1,78 @@
+magic
+tech sky130A
+timestamp 1608225149
+<< nmos >>
+rect 320 -94 360 -64
+rect 320 -157 360 -126
+<< ndiff >>
+rect 291 -70 320 -64
+rect 291 -87 296 -70
+rect 313 -87 320 -70
+rect 291 -94 320 -87
+rect 360 -70 391 -64
+rect 360 -87 367 -70
+rect 384 -87 391 -70
+rect 360 -94 391 -87
+rect 291 -133 320 -126
+rect 291 -150 297 -133
+rect 314 -150 320 -133
+rect 291 -157 320 -150
+rect 360 -133 390 -126
+rect 360 -150 366 -133
+rect 383 -150 390 -133
+rect 360 -157 390 -150
+<< ndiffc >>
+rect 296 -87 313 -70
+rect 367 -87 384 -70
+rect 297 -150 314 -133
+rect 366 -150 383 -133
+<< psubdiff >>
+rect 417 -134 440 -122
+rect 417 -151 420 -134
+rect 437 -151 440 -134
+rect 417 -163 440 -151
+<< psubdiffcont >>
+rect 420 -151 437 -134
+<< poly >>
+rect 257 -56 360 -40
+rect 320 -64 360 -56
+rect 320 -126 360 -94
+rect 320 -170 360 -157
+<< locali >>
+rect 257 -87 296 -70
+rect 313 -87 321 -70
+rect 359 -87 367 -70
+rect 384 -87 394 -70
+rect 257 -88 321 -87
+rect 412 -91 437 -71
+rect 297 -133 314 -125
+rect 363 -150 366 -133
+rect 383 -150 392 -133
+rect 420 -134 437 -91
+rect 297 -155 314 -150
+rect 420 -159 437 -151
+<< metal1 >>
+rect 346 -128 365 -53
+rect 394 -181 413 -29
+<< metal2 >>
+rect 257 -72 445 -52
+rect 257 -170 314 -150
+use sky130_hilas_m12m2 sky130_hilas_m12m2_3
+timestamp 1607949437
+transform 1 0 335 0 1 -68
+box -9 -10 23 22
+use sky130_hilas_li2m1 sky130_hilas_li2m1_1
+timestamp 1607179295
+transform 1 0 402 0 1 -86
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+use sky130_hilas_li2m1 sky130_hilas_li2m1_5
+timestamp 1607179295
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+box -10 -8 13 21
+use sky130_hilas_li2m2 sky130_hilas_li2m2_3
+timestamp 1607089160
+transform 1 0 304 0 1 -155
+box -14 -15 20 18
+<< labels >>
+rlabel metal2 439 -72 445 -52 0 output
+<< end >>
diff --git a/mag/sky130_hilas_TgateSingle01Part2.mag b/mag/sky130_hilas_TgateSingle01Part2.mag
new file mode 100644
index 0000000..1a0d127
--- /dev/null
+++ b/mag/sky130_hilas_TgateSingle01Part2.mag
@@ -0,0 +1,51 @@
+magic
+tech sky130A
+timestamp 1608225149
+<< nwell >>
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+rect -67 -181 96 -97
+<< pmos >>
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+<< pdiff >>
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+rect 3 -150 9 -133
+rect -20 -157 9 -150
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+rect 49 -150 55 -133
+rect 72 -150 78 -133
+rect 49 -157 78 -150
+<< pdiffc >>
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+<< poly >>
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+rect 9 -170 49 -157
+<< locali >>
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+<< metal2 >>
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+use sky130_hilas_m12m2 sky130_hilas_m12m2_2
+timestamp 1607949437
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+box -9 -10 23 22
+use sky130_hilas_li2m2 sky130_hilas_li2m2_2
+timestamp 1607089160
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+box -14 -15 20 18
+use sky130_hilas_li2m1 sky130_hilas_li2m1_3
+timestamp 1607179295
+transform 1 0 82 0 1 -147
+box -10 -8 13 21
+<< end >>
diff --git a/mag/sky130_hilas_TgateVinj01.mag b/mag/sky130_hilas_TgateVinj01.mag
new file mode 100644
index 0000000..8449cdc
--- /dev/null
+++ b/mag/sky130_hilas_TgateVinj01.mag
@@ -0,0 +1,225 @@
+magic
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+timestamp 1625970418
+<< nwell >>
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+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
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+<< end >>
diff --git a/mag/sky130_hilas_TopLevelProtectStructure.mag b/mag/sky130_hilas_TopLevelProtectStructure.mag
new file mode 100644
index 0000000..b859aa7
--- /dev/null
+++ b/mag/sky130_hilas_TopLevelProtectStructure.mag
@@ -0,0 +1,1066 @@
+magic
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+rect -8162 -22788 -8149 -22465
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+<< via1 >>
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+rect -5617 12608 -5565 12645
+rect -9695 12287 -9372 12512
+rect -12737 11860 -12512 12183
+rect -13890 11520 -13704 11843
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+rect -9244 -17070 -9036 -16747
+rect -8800 -19929 -8592 -19606
+rect -8370 -22788 -8162 -22465
+<< metal2 >>
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+rect 20638 -7218 20779 -7128
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+rect -15053 -24304 -14913 -24107
+rect -14423 -24337 -14283 -23971
+use sky130_hilas_RightProtection sky130_hilas_RightProtection_0
+timestamp 1626559870
+transform 1 0 22518 0 1 -15744
+box -2054 8715 -826 28728
+use sky130_hilas_LeftProtection sky130_hilas_LeftProtection_0
+timestamp 1626559870
+transform 1 0 -13278 0 1 -15672
+box -2065 -8439 -833 28728
+use sky130_hilas_TopProtection sky130_hilas_TopProtection_0
+timestamp 1626559870
+transform 1 0 -13875 0 1 13286
+box -2 -76 34131 1170
+use sky130_hilas_TopLevelTextStructure sky130_hilas_TopLevelTextStructure_0
+timestamp 1626570174
+transform 1 0 -2990 0 1 6624
+box 218 -793 13243 6785
+<< labels >>
+rlabel metal1 21692 -6258 21817 -5869 0 IO07
+port 1 nsew
+rlabel metal1 21692 -3397 21817 -3008 0 IO08
+port 2 nsew
+rlabel metal1 21690 -539 21815 -150 0 IO09
+port 3 nsew
+rlabel metal1 21692 2322 21817 2711 0 IO10
+port 4 nsew
+rlabel metal1 21691 5178 21816 5567 0 IO11
+port 5 nsew
+rlabel metal1 21691 8038 21816 8427 0 IO12
+port 6 nsew
+rlabel metal1 21692 10898 21817 11287 0 IO13
+port 7 nsew
+rlabel metal1 -15468 10968 -15343 11357 0 IO25
+port 8 nsew
+rlabel metal1 -15467 8110 -15342 8499 0 IO26
+port 9 nsew
+rlabel metal1 -15468 5250 -15343 5639 0 IO27
+port 10 nsew
+rlabel metal1 -15466 2391 -15341 2780 0 IO28
+port 11 nsew
+rlabel metal1 -15467 -467 -15342 -78 0 IO29
+port 12 nsew
+rlabel metal1 -15468 -3327 -15343 -2938 0 IO30
+port 13 nsew
+rlabel metal1 -15467 -6185 -15342 -5796 0 IO31
+port 14 nsew
+rlabel metal1 -15464 -9043 -15339 -8654 0 IO32
+port 15 nsew
+rlabel metal1 -15466 -11904 -15341 -11515 0 IO33
+port 16 nsew
+rlabel metal1 -15467 -14763 -15342 -14374 0 IO34
+port 17 nsew
+rlabel metal1 -15467 -17622 -15342 -17233 0 IO35
+port 18 nsew
+rlabel metal1 -15466 -20481 -15341 -20092 0 IO36
+port 19 nsew
+rlabel metal1 -15466 -23339 -15341 -22950 0 IO37
+port 20 nsew
+rlabel metal2 -15139 13873 -14971 14164 0 VSSA1
+port 21 nsew
+rlabel metal1 -13106 14454 -12717 14571 0 ANALOG10
+port 22 nsew
+rlabel metal1 -10247 14453 -9858 14570 0 ANALOG09
+port 23 nsew
+rlabel metal1 -7388 14453 -6999 14570 0 ANALOG08
+port 24 nsew
+rlabel metal1 -3198 14456 -2809 14573 0 ANALOG07
+port 25 nsew
+rlabel metal1 1014 14454 1403 14571 0 ANALOG06
+port 26 nsew
+rlabel metal1 3873 14454 4262 14571 0 ANALOG05
+port 27 nsew
+rlabel metal1 6733 14454 7122 14571 0 ANALOG04
+port 28 nsew
+rlabel metal1 9592 14454 9981 14571 0 ANALOG03
+port 29 nsew
+rlabel metal1 12451 14454 12840 14571 0 ANALOG02
+port 30 nsew
+rlabel metal1 15310 14453 15699 14570 0 ANALOG01
+port 31 nsew
+rlabel metal1 18169 14453 18558 14570 0 ANALOG00
+port 32 nsew
+rlabel metal2 21381 13908 21500 14166 0 VSSA1
+port 33 nsew
+rlabel metal2 -14423 -24337 -14283 -24197 0 VDDA1
+port 34 nsew
+rlabel metal2 -15053 -24304 -14913 -24164 0 VSSA1
+port 33 nsew
+rlabel metal2 20639 -7218 20779 -7101 0 VDDA1
+port 34 nsew
+rlabel metal2 21273 -7224 21413 -7107 0 VSSA1
+port 33 nsew
+rlabel metal2 -1269 -23816 -1067 -23660 0 LADATAOUT00
+port 36 nsew
+rlabel metal2 -862 -23815 -660 -23659 0 LADATAOUT01
+port 35 nsew
+rlabel metal2 -467 -23816 -265 -23660 0 LADATAOUT02
+port 37 nsew
+rlabel metal2 -67 -23816 135 -23660 0 LADATAOUT03
+port 38 nsew
+rlabel metal2 339 -23816 541 -23660 0 LADATAOUT04
+port 39 nsew
+rlabel metal2 739 -23815 941 -23659 0 LADATAOUT05
+port 40 nsew
+rlabel metal2 1140 -23816 1342 -23660 0 LADATAOUT06
+port 41 nsew
+rlabel metal2 1549 -23816 1751 -23660 0 LADATAOUT07
+port 42 nsew
+rlabel metal2 1961 -23816 2163 -23660 0 LADATAOUT08
+port 43 nsew
+rlabel metal2 2361 -23816 2563 -23660 0 LADATAOUT09
+port 44 nsew
+rlabel metal2 2757 -23816 2959 -23660 0 LADATAOUT10
+port 45 nsew
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+port 46 nsew
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+port 47 nsew
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+port 48 nsew
+rlabel metal2 4378 -23816 4580 -23660 0 LADATAOUT14
+port 49 nsew
+rlabel metal2 4787 -23818 4989 -23662 0 LADATAOUT15
+port 50 nsew
+rlabel metal2 5191 -23816 5393 -23660 0 LADATA16
+port 51 nsew
+rlabel metal2 5588 -23816 5790 -23660 0 LADATAOUT17
+port 52 nsew
+rlabel metal2 6000 -23815 6202 -23659 0 LADATAOUT18
+port 53 nsew
+rlabel metal2 6413 -23817 6615 -23661 0 LADATAOUT19
+port 54 nsew
+rlabel metal2 6814 -23816 7016 -23660 0 LADATAOUT20
+port 55 nsew
+rlabel metal2 7215 -23814 7419 -23648 0 LADATAOUT21
+port 56 nsew
+rlabel metal2 7624 -23816 7827 -23650 0 LADATAOUT22
+port 57 nsew
+rlabel metal2 8039 -23816 8242 -23650 0 LADATAOUT23
+port 58 nsew
+rlabel metal2 8441 -23816 8644 -23650 0 LADATAOUT24
+port 59 nsew
+rlabel metal2 8839 -23816 9042 -23650 0 LADATAIN00
+port 60 nsew
+rlabel metal2 9237 -23816 9440 -23650 0 LADATAIN01
+port 61 nsew
+rlabel metal2 9644 -23816 9847 -23650 0 LADATAIN02
+port 62 nsew
+rlabel metal2 10050 -23816 10253 -23650 0 LADATAIN03
+port 63 nsew
+rlabel metal2 20683 -8211 20799 -8085 0 VCCA
+port 64 nsew
+<< end >>
diff --git a/mag/sky130_hilas_TopLevelTextStructure.mag b/mag/sky130_hilas_TopLevelTextStructure.mag
new file mode 100644
index 0000000..6cde771
--- /dev/null
+++ b/mag/sky130_hilas_TopLevelTextStructure.mag
@@ -0,0 +1,3325 @@
+magic
+tech sky130A
+timestamp 1626570174
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+rect 10204 -782 10407 -747
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+rect 11014 -647 11033 -630
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+rect 11030 -726 11233 -717
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+rect 11579 -719 11598 -712
+rect 11839 -717 12040 1013
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+rect 11030 -782 11233 -747
+rect 11428 -784 11631 -719
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+rect 12225 -717 12426 1103
+rect 11833 -782 12036 -769
+rect 12225 -782 12432 -717
+rect 12633 -719 12834 1193
+rect 13042 -717 13243 1283
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+rect 12633 -784 12837 -719
+rect 13039 -775 13243 -717
+rect 13039 -782 13242 -775
+rect 12633 -792 12834 -784
+<< via2 >>
+rect 7948 4760 7980 4763
+rect 7948 4734 7971 4760
+rect 7971 4734 7980 4760
+rect 8051 4761 8083 4762
+rect 8051 4735 8073 4761
+rect 8073 4735 8083 4761
+rect 7948 4731 7980 4734
+rect 8051 4730 8083 4735
+rect 8059 4382 8093 4416
+rect 7952 4034 7985 4069
+rect 8061 3777 8095 3813
+<< metal3 >>
+rect 7941 4763 7986 4769
+rect 7941 4731 7948 4763
+rect 7980 4731 7986 4763
+rect 7941 4694 7986 4731
+rect 8045 4762 8090 4768
+rect 8045 4730 8051 4762
+rect 8083 4730 8090 4762
+rect 7941 4078 7978 4694
+rect 8045 4693 8090 4730
+rect 8053 4429 8090 4693
+rect 8053 4416 8097 4429
+rect 8053 4382 8059 4416
+rect 8093 4382 8097 4416
+rect 8053 4369 8097 4382
+rect 7941 4069 7990 4078
+rect 7941 4045 7952 4069
+rect 7946 4034 7952 4045
+rect 7985 4034 7990 4069
+rect 7946 4029 7990 4034
+rect 8053 3858 8090 4369
+rect 8052 3813 8099 3858
+rect 8052 3777 8061 3813
+rect 8095 3777 8099 3813
+rect 8052 3771 8099 3777
+use sky130_hilas_pFETLarge sky130_hilas_pFETLarge_0
+timestamp 1608245216
+transform -1 0 2012 0 -1 1081
+box 64 419 528 1018
+use sky130_hilas_nFETLarge sky130_hilas_nFETLarge_0
+timestamp 1625426387
+transform -1 0 2008 0 -1 1836
+box 64 420 501 1003
+use sky130_hilas_DAC5bit01 sky130_hilas_DAC5bit01_0
+timestamp 1625056879
+transform 0 1 9912 1 0 -1031
+box 382 524 2040 1121
+use sky130_hilas_Trans2med sky130_hilas_Trans2med_0
+timestamp 1626027626
+transform 1 0 2073 0 -1 2311
+box -380 -143 -27 452
+use sky130_hilas_LevelShift4InputUp sky130_hilas_LevelShift4InputUp_3
+timestamp 1624113741
+transform -1 0 4927 0 -1 2263
+box -30 -102 850 522
+use sky130_hilas_drainSelect01 sky130_hilas_drainSelect01_3
+timestamp 1625970648
+transform -1 0 6601 0 -1 2362
+box 1050 5 1622 610
+use sky130_hilas_pFETLarge sky130_hilas_pFETLarge_1
+timestamp 1608245216
+transform 1 0 4824 0 1 606
+box 64 419 528 1018
+use sky130_hilas_pFETLarge sky130_hilas_pFETLarge_2
+timestamp 1608245216
+transform -1 0 5880 0 1 606
+box 64 419 528 1018
+use sky130_hilas_pFETLarge sky130_hilas_pFETLarge_3
+timestamp 1608245216
+transform 1 0 5805 0 1 609
+box 64 419 528 1018
+use sky130_hilas_pFETLarge sky130_hilas_pFETLarge_4
+timestamp 1608245216
+transform -1 0 6861 0 1 609
+box 64 419 528 1018
+use sky130_hilas_WTA4Stage01 sky130_hilas_WTA4Stage01_0
+timestamp 1625404155
+transform 1 0 6825 0 1 1803
+box -1121 -43 296 562
+use sky130_hilas_nFETLarge sky130_hilas_nFETLarge_1
+timestamp 1625426387
+transform -1 0 7435 0 1 608
+box 64 420 501 1003
+use sky130_hilas_Trans4small sky130_hilas_Trans4small_0
+timestamp 1608234847
+transform 1 0 1738 0 1 4259
+box 191 -150 471 438
+use sky130_hilas_LevelShift4InputUp sky130_hilas_LevelShift4InputUp_2
+timestamp 1624113741
+transform -1 0 4927 0 -1 3240
+box -30 -102 850 522
+use sky130_hilas_LevelShift4InputUp sky130_hilas_LevelShift4InputUp_1
+timestamp 1624113741
+transform -1 0 4927 0 -1 4253
+box -30 -102 850 522
+use sky130_hilas_drainSelect01 sky130_hilas_drainSelect01_2
+timestamp 1625970648
+transform -1 0 6601 0 -1 3338
+box 1050 5 1622 610
+use sky130_hilas_swc4x2cell sky130_hilas_swc4x2cell_0
+timestamp 1625491916
+transform 1 0 6768 0 1 2742
+box -1004 -4 1009 601
+use sky130_hilas_drainSelect01 sky130_hilas_drainSelect01_1
+timestamp 1625970648
+transform -1 0 6601 0 -1 4345
+box 1050 5 1622 610
+use sky130_hilas_TA2Cell_1FG_Strong sky130_hilas_TA2Cell_1FG_Strong_0
+timestamp 1626460134
+transform 1 0 8236 0 1 3936
+box -2617 140 193 745
+use sky130_hilas_TA2Cell_1FG sky130_hilas_TA2Cell_1FG_0
+timestamp 1625491133
+transform 1 0 8236 0 1 3333
+box -2616 140 193 745
+use sky130_hilas_Tgate4Single01 sky130_hilas_Tgate4Single01_0
+timestamp 1608226321
+transform 1 0 10780 0 1 3947
+box -36 -141 440 464
+use sky130_hilas_FGcharacterization01 sky130_hilas_FGcharacterization01_0
+timestamp 1625074044
+transform -1 0 2682 0 1 5308
+box -912 259 2083 864
+use sky130_hilas_LevelShift4InputUp sky130_hilas_LevelShift4InputUp_0
+timestamp 1624113741
+transform -1 0 4927 0 1 4465
+box -30 -102 850 522
+<< labels >>
+rlabel metal2 13039 -782 13242 -717 1 DIG24
+port 1 n
+rlabel metal2 12634 -784 12837 -719 0 DIG23
+port 2 nsew
+rlabel metal2 12229 -782 12432 -717 0 DIG22
+port 3 nsew
+rlabel metal2 11833 -782 12036 -717 0 DIG21
+port 4 nsew
+rlabel metal2 11428 -784 11631 -719 0 DIG29
+port 5 nsew
+rlabel metal2 11030 -782 11233 -717 0 DIG28
+port 6 nsew
+rlabel metal2 10612 -782 10815 -717 0 DIG27
+port 7 nsew
+rlabel metal2 10204 -782 10407 -717 0 DIG26
+port 8 nsew
+rlabel metal2 9802 -782 10005 -717 0 DIG25
+port 9 nsew
+rlabel metal2 9403 -785 9606 -720 0 DIG20
+port 10 nsew
+rlabel metal2 8989 -782 9192 -717 0 DIG19
+port 11 nsew
+rlabel metal2 8577 -784 8780 -719 0 DIG18
+port 12 nsew
+rlabel metal2 8182 -782 8385 -717 0 DIG17
+port 13 nsew
+rlabel metal2 7774 -780 7977 -715 0 DIG16
+port 14 nsew
+rlabel metal2 7367 -782 7570 -717 0 DIG15
+port 15 nsew
+rlabel metal2 6962 -782 7165 -717 0 DIG14
+port 16 nsew
+rlabel metal2 6559 -782 6762 -717 0 DIG13
+port 17 nsew
+rlabel metal2 6152 -784 6355 -719 0 DIG12
+port 18 nsew
+rlabel metal2 5747 -778 5950 -712 0 DIG11
+port 19 nsew
+rlabel metal2 5351 -776 5554 -710 0 DIG10
+port 20 nsew
+rlabel metal2 4953 -782 5156 -716 0 DIG09
+port 21 nsew
+rlabel metal2 4536 -784 4739 -718 0 DIG08
+port 22 nsew
+rlabel metal2 4127 -782 4330 -716 0 DIG07
+port 23 nsew
+rlabel metal2 3731 -785 3934 -719 0 DIG06
+port 24 nsew
+rlabel metal2 3328 -784 3531 -718 0 DIG05
+port 25 nsew
+rlabel metal2 2923 -782 3126 -716 0 DIG04
+port 26 nsew
+rlabel metal2 2523 -782 2726 -716 0 DIG03
+port 27 nsew
+rlabel metal2 2127 -782 2330 -716 0 DIG02
+port 28 nsew
+rlabel metal2 1720 -785 1923 -719 0 DIG01
+port 29 nsew
+rlabel metal2 11805 1367 11882 1576 0 CAP2
+port 30 nsew
+rlabel metal2 11760 1918 11850 2127 0 GENERALGATE01
+port 31 nsew
+rlabel metal2 11763 2426 11853 2635 0 GATEANDCAP1
+port 32 nsew
+rlabel metal2 11760 2944 11850 3153 0 GENERALGATE02
+port 33 nsew
+rlabel metal2 11760 3432 11850 3641 0 OUTPUTTA1
+port 34 nsew
+rlabel metal2 11760 3970 11850 4179 0 GATENFET1
+port 35 nsew
+rlabel metal2 11763 4415 11853 4624 0 DACOUTPUT
+port 36 nsew
+rlabel metal2 11764 4853 11850 5063 0 DRAINOUT
+port 37 nsew
+rlabel metal2 11764 5292 11850 5502 0 ROWTERM2
+port 38 nsew
+rlabel metal2 11767 5701 11853 5911 0 COLUMN2
+port 39 nsew
+rlabel metal2 11767 6114 11853 6324 0 COLUMN1
+port 40 nsew
+rlabel metal1 10273 6287 10592 6399 0 GATE2
+port 41 nsew
+rlabel metal1 7416 6284 7735 6396 0 GATE1
+port 61 nsew
+rlabel metal1 4557 6285 4876 6397 0 DRAININJECT
+port 42 nsew
+rlabel metal1 3026 6238 3160 6339 0 VTUN
+port 43 nsew
+rlabel metal2 295 6136 363 6368 0 VREFCHAR
+port 44 nsew
+rlabel metal2 295 5683 363 5915 0 CHAROUTPUT
+port 45 nsew
+rlabel metal2 250 5236 318 5468 0 LARGECAPACITOR
+port 46 nsew
+rlabel metal2 1379 920 1416 961 0 DRAIN6N
+port 47 nsew
+rlabel metal2 1379 192 1416 233 0 DRAIN6P
+port 48 nsew
+rlabel metal2 1383 1884 1420 1925 0 DRAIN5P
+port 49 nsew
+rlabel metal2 1383 1980 1420 2021 0 DARIN4P
+port 50 nsew
+rlabel metal2 1383 2350 1420 2391 0 DRAIN5N
+port 51 nsew
+rlabel metal2 1383 2414 1420 2455 0 DRAIN4N
+port 52 nsew
+rlabel metal2 1383 4157 1420 4198 0 DRAIN3P
+port 53 nsew
+rlabel metal2 1383 4253 1420 4294 0 DRAIN2P
+port 54 nsew
+rlabel metal2 1383 4349 1420 4390 0 DRAIN1P
+port 55 nsew
+rlabel metal2 1383 4461 1420 4502 0 DRAIN3N
+port 56 nsew
+rlabel metal2 1383 4554 1420 4595 0 DRAIN2N
+port 57 nsew
+rlabel metal2 1383 4657 1420 4698 0 DRAIN1N
+port 58 nsew
+rlabel metal2 1353 4765 1383 4805 0 SOURCEN
+port 59 nsew
+rlabel metal2 1353 4847 1383 4887 0 SOURCEP
+port 60 nsew
+rlabel metal2 279 5546 324 5586 0 VGND
+port 63 nsew
+rlabel metal2 283 5987 328 6027 0 VINJ
+port 62 nsew
+rlabel metal2 250 5157 301 5198 0 VINJ
+port 62 nsew
+rlabel metal2 246 5067 297 5108 0 VGND
+port 63 nsew
+rlabel metal2 298 1555 361 1597 0 VINJ
+port 62 nsew
+rlabel metal2 296 1458 359 1500 0 VGND
+port 63 nsew
+rlabel metal2 11863 4720 11908 4765 0 VPWR
+port 64 nsew
+rlabel metal1 5638 6371 5711 6401 0 VINJ
+port 62 nsew
+rlabel metal1 6154 6380 6251 6401 0 VGND
+port 63 nsew
+rlabel metal2 11811 1680 11877 1795 0 VPWR
+port 64 nsew
+rlabel metal1 5200 -785 5292 -712 0 VPWR
+port 64 nsew
+rlabel metal1 6393 -785 6485 -712 0 VPWR
+port 64 nsew
+<< end >>
diff --git a/mag/sky130_hilas_TopProtectStructure.mag b/mag/sky130_hilas_TopProtectStructure.mag
new file mode 100644
index 0000000..4df1e73
--- /dev/null
+++ b/mag/sky130_hilas_TopProtectStructure.mag
@@ -0,0 +1,1059 @@
+magic
+tech sky130A
+timestamp 1626780777
+<< error_s >>
+rect -626 12757 -597 12773
+rect -547 12757 -518 12773
+rect -468 12757 -439 12773
+rect -389 12757 -360 12773
+rect -1764 12733 -1757 12739
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+rect -468 12723 -467 12724
+rect -440 12723 -439 12724
+rect -389 12723 -388 12724
+rect -361 12723 -360 12724
+rect -676 12694 -659 12723
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+rect -548 12722 -517 12723
+rect -469 12722 -438 12723
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+rect -626 12715 -597 12722
+rect -547 12715 -518 12722
+rect -468 12715 -439 12722
+rect -389 12715 -360 12722
+rect -626 12701 -617 12715
+rect -370 12701 -360 12715
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+rect 9643 -23816 9847 -23650
+rect 10049 -23816 10253 -23650
+rect -15053 -24304 -14913 -24107
+rect -14423 -24337 -14283 -23971
+use sky130_hilas_TopProtection sky130_hilas_TopProtection_0
+timestamp 1626559870
+transform 1 0 -13875 0 1 13286
+box -2 -76 34131 1170
+use sky130_hilas_LeftProtection sky130_hilas_LeftProtection_0
+timestamp 1626559870
+transform 1 0 -13278 0 1 -15672
+box -2065 -8439 -833 28728
+use sky130_hilas_RightProtection sky130_hilas_RightProtection_0
+timestamp 1626559870
+transform 1 0 22518 0 1 -15744
+box -2054 8715 -826 28728
+use sky130_hilas_TopLevelTextStructure sky130_hilas_TopLevelTextStructure_0
+timestamp 1626570174
+transform 1 0 -2990 0 1 6624
+box 218 -793 13243 6785
+<< labels >>
+rlabel metal1 21692 -6258 21817 -5869 0 IO07
+port 1 nsew
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+port 2 nsew
+rlabel metal1 21690 -539 21815 -150 0 IO09
+port 3 nsew
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+port 4 nsew
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+port 63 nsew
+rlabel metal2 20683 -8211 20799 -8085 0 VCCA
+port 64 nsew
+<< end >>
diff --git a/mag/sky130_hilas_TopProtection.mag b/mag/sky130_hilas_TopProtection.mag
new file mode 100644
index 0000000..5632330
--- /dev/null
+++ b/mag/sky130_hilas_TopProtection.mag
@@ -0,0 +1,116 @@
+magic
+tech sky130A
+timestamp 1626559870
+<< metal1 >>
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+rect 3628 1088 4017 1168
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+rect 29666 -76 30061 1
+rect 32525 -76 32920 1
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_1
+timestamp 1626558701
+transform 1 0 3602 0 1 230
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_0
+timestamp 1626558701
+transform 1 0 743 0 1 230
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_2
+timestamp 1626558701
+transform 1 0 6461 0 1 230
+box -745 -229 2114 858
+use sky130_hilas_polyresistorGND sky130_hilas_polyresistorGND_0
+timestamp 1626558701
+transform 1 0 11320 0 1 58
+box -2749 -57 2798 1032
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_3
+timestamp 1626558701
+transform 1 0 14863 0 1 230
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_4
+timestamp 1626558701
+transform 1 0 17722 0 1 230
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_5
+timestamp 1626558701
+transform 1 0 20581 0 1 230
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_6
+timestamp 1626558701
+transform 1 0 23440 0 1 230
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_9
+timestamp 1626558701
+transform 1 0 26299 0 1 230
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_7
+timestamp 1626558701
+transform 1 0 29158 0 1 230
+box -745 -229 2114 858
+use sky130_hilas_VinjDiodeProtect01 sky130_hilas_VinjDiodeProtect01_8
+timestamp 1626558701
+transform 1 0 32017 0 1 230
+box -745 -229 2114 858
+<< labels >>
+rlabel metal1 32044 1088 32433 1168 0 ANALOG00
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+port 2 nsew
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+rlabel metal1 11246 -76 11494 1 0 VTUN
+port 22 nsew
+<< end >>
diff --git a/mag/sky130_hilas_Trans2med.mag b/mag/sky130_hilas_Trans2med.mag
new file mode 100644
index 0000000..39ea31f
--- /dev/null
+++ b/mag/sky130_hilas_Trans2med.mag
@@ -0,0 +1,197 @@
+magic
+tech sky130A
+timestamp 1626027626
+<< nwell >>
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+<< psubdiff >>
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+rect -52 247 -45 264
+rect -73 218 -45 247
+<< psubdiffcont >>
+rect -68 17 -51 34
+rect -68 -17 -51 0
+<< nsubdiffcont >>
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+rect -69 247 -52 264
+<< poly >>
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+rect -155 160 -76 175
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+rect -155 124 -76 139
+<< locali >>
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+rect -69 239 -52 247
+<< viali >>
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+rect -96 -116 -27 -95
+use sky130_hilas_m12m2 sky130_hilas_m12m2_1
+timestamp 1607949437
+transform 1 0 -349 0 1 66
+box -9 -10 23 22
+use sky130_hilas_poly2m1 sky130_hilas_poly2m1_1
+timestamp 1607270135
+transform -1 0 -335 0 1 114
+box -9 -26 24 25
+use sky130_hilas_li2m2 sky130_hilas_li2m2_4
+timestamp 1607089160
+transform 1 0 -299 0 1 -64
+box -14 -15 20 18
+use sky130_hilas_nFETmed sky130_hilas_nFETmed_1
+timestamp 1607963611
+transform 1 0 -290 0 1 -99
+box -12 -44 70 228
+use sky130_hilas_li2m2 sky130_hilas_li2m2_5
+timestamp 1607089160
+transform 1 0 -229 0 1 -64
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_7
+timestamp 1607089160
+transform 1 0 -177 0 1 -108
+box -14 -15 20 18
+use sky130_hilas_nFETmed sky130_hilas_nFETmed_0
+timestamp 1607963611
+transform 1 0 -171 0 1 -99
+box -12 -44 70 228
+use sky130_hilas_li2m2 sky130_hilas_li2m2_6
+timestamp 1607089160
+transform 1 0 -112 0 1 -108
+box -14 -15 20 18
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_0
+timestamp 1607270276
+transform 0 -1 -54 1 0 115
+box -9 -26 24 29
+use sky130_hilas_pFETmed sky130_hilas_pFETmed_0
+timestamp 1607969308
+transform 1 0 -467 0 1 187
+box 147 -22 266 265
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607949437
+transform 1 0 -349 0 1 221
+box -9 -10 23 22
+use sky130_hilas_poly2m1 sky130_hilas_poly2m1_0
+timestamp 1607270135
+transform 1 0 -349 0 -1 185
+box -9 -26 24 25
+use sky130_hilas_li2m2 sky130_hilas_li2m2_3
+timestamp 1607089160
+transform 1 0 -296 0 1 324
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 -227 0 1 325
+box -14 -15 20 18
+use sky130_hilas_pFETmed sky130_hilas_pFETmed_1
+timestamp 1607969308
+transform 1 0 -349 0 1 187
+box 147 -22 266 265
+use sky130_hilas_li2m2 sky130_hilas_li2m2_2
+timestamp 1607089160
+transform 1 0 -179 0 1 402
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 -108 0 1 408
+box -14 -15 20 18
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_1
+timestamp 1607270276
+transform 0 -1 -53 1 0 169
+box -9 -26 24 29
+<< labels >>
+rlabel metal2 -380 215 -371 237 0 GATE1P
+port 3 nsew analog default
+rlabel metal2 -380 159 -372 180 0 GATE2P
+port 2 nsew analog default
+rlabel metal2 -380 119 -372 140 0 GATE2N
+port 4 nsew analog default
+rlabel metal2 -380 62 -372 83 0 GATE1N
+port 1 nsew analog default
+rlabel metal2 -37 400 -27 421 0 DRAIN2P
+port 12 nsew analog default
+rlabel metal2 -37 317 -27 338 0 DRAIN1P
+port 11 nsew analog default
+rlabel metal2 -380 314 -372 336 0 SOURCE1P
+port 5 nsew analog default
+rlabel metal2 -380 392 -372 414 0 SOURCE2P
+port 6 nsew analog default
+rlabel metal2 -380 -74 -373 -53 0 SOURCE1N
+port 8 nsew analog default
+rlabel metal2 -380 -119 -373 -97 0 SOURCE2N
+port 7 nsew analog default
+rlabel metal2 -34 -72 -27 -50 0 DRAIN1N
+port 9 nsew analog default
+rlabel metal2 -34 -116 -27 -95 0 DRAIN2N
+port 10 nsew analog default
+rlabel metal2 -38 0 -27 21 0 VGND
+port 14 nsew
+rlabel metal2 -36 261 -27 282 0 WELL
+port 15 nsew
+<< end >>
diff --git a/mag/sky130_hilas_Trans4small.mag b/mag/sky130_hilas_Trans4small.mag
new file mode 100644
index 0000000..54e3fe3
--- /dev/null
+++ b/mag/sky130_hilas_Trans4small.mag
@@ -0,0 +1,130 @@
+magic
+tech sky130A
+timestamp 1608234847
+<< nwell >>
+rect 401 -87 455 159
+rect 383 -132 455 -87
+rect 198 -150 455 -132
+<< psubdiff >>
+rect 397 368 439 375
+rect 397 351 410 368
+rect 427 351 439 368
+rect 397 344 439 351
+<< nsubdiff >>
+rect 396 -110 437 -105
+rect 396 -127 408 -110
+rect 425 -127 437 -110
+rect 396 -132 437 -127
+<< psubdiffcont >>
+rect 410 351 427 368
+<< nsubdiffcont >>
+rect 408 -127 425 -110
+<< locali >>
+rect 411 376 428 381
+rect 410 373 428 376
+rect 410 368 453 373
+rect 427 351 453 368
+rect 410 348 453 351
+rect 410 342 427 348
+rect 396 -127 408 -110
+rect 425 -127 438 -110
+<< metal1 >>
+rect 409 -150 431 438
+rect 449 -150 471 438
+<< metal2 >>
+rect 191 398 198 415
+rect 389 399 471 416
+rect 191 357 198 374
+rect 191 306 198 323
+rect 389 307 471 324
+rect 191 265 198 282
+rect 191 214 198 231
+rect 389 215 471 232
+rect 191 173 198 190
+rect 191 112 198 131
+rect 391 105 471 125
+rect 191 70 198 89
+rect 191 16 198 35
+rect 391 9 471 29
+rect 191 -26 198 -7
+rect 191 -80 198 -61
+rect 390 -87 471 -67
+rect 191 -122 198 -103
+use sky130_hilas_nFET03a sky130_hilas_nFET03a_3
+timestamp 1608056777
+transform 1 0 309 0 1 396
+box -111 -47 97 42
+use sky130_hilas_nFET03a sky130_hilas_nFET03a_1
+timestamp 1608056777
+transform 1 0 309 0 1 304
+box -111 -47 97 42
+use sky130_hilas_nFET03a sky130_hilas_nFET03a_0
+timestamp 1608056777
+transform 1 0 309 0 1 212
+box -111 -47 97 42
+use sky130_hilas_pFETdevice01e sky130_hilas_pFETdevice01e_2
+timestamp 1608055794
+transform 1 0 319 0 1 -77
+box -121 -55 82 44
+use sky130_hilas_pFETdevice01e sky130_hilas_pFETdevice01e_1
+timestamp 1608055794
+transform 1 0 319 0 1 19
+box -121 -55 82 44
+use sky130_hilas_pFETdevice01e sky130_hilas_pFETdevice01e_0
+timestamp 1608055794
+transform 1 0 319 0 1 115
+box -121 -55 82 44
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 0 1 411 -1 0 -120
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_1
+timestamp 1607179295
+transform 1 0 458 0 1 354
+box -10 -8 13 21
+<< labels >>
+rlabel metal1 409 -150 431 -141 0 WELL
+port 13 nsew power default
+rlabel metal1 449 -150 471 -141 0 VGND
+port 14 nsew ground default
+rlabel metal1 409 429 431 438 0 WELL
+port 13 nsew ground default
+rlabel metal1 449 429 471 438 0 VGND
+port 14 nsew power default
+rlabel metal2 191 398 198 415 0 NFET_SOURCE1
+port 1 nsew analog default
+rlabel metal2 191 357 198 374 0 NFET_GATE1
+port 2 nsew analog default
+rlabel metal2 191 306 198 323 0 NFET_SOURCE2
+port 3 nsew analog default
+rlabel metal2 191 265 198 282 0 NFET_GATE2
+port 4 nsew analog default
+rlabel metal2 191 214 198 231 0 NFET_SOURCE3
+port 5 nsew analog default
+rlabel metal2 191 173 198 190 0 NFET_GATE3
+port 6 nsew analog default
+rlabel metal2 191 70 198 89 0 PFET_GATE1
+port 8 nsew analog default
+rlabel metal2 191 112 198 131 0 PFET_SOURCE1
+port 7 nsew analog default
+rlabel metal2 191 16 198 35 0 PFET_SOURCE2
+port 9 nsew analog default
+rlabel metal2 191 -26 198 -7 0 PFET_GATE2
+port 10 nsew analog default
+rlabel metal2 191 -80 198 -61 0 PFET_SOURCE3
+port 11 nsew analog default
+rlabel metal2 191 -122 198 -103 0 PFET_GATE3
+port 12 nsew analog default
+rlabel metal2 465 105 471 125 0 PFET_DRAIN1
+port 17 nsew analog default
+rlabel metal2 465 9 471 29 0 PFET_DRAIN2
+port 16 nsew analog default
+rlabel metal2 465 -87 471 -67 0 PFET_DRAIN3
+port 15 nsew analog default
+rlabel metal2 466 399 471 416 0 NFET_DRAIN1
+port 20 nsew analog default
+rlabel metal2 466 307 471 324 0 NFET_DRAIN2
+port 19 nsew analog default
+rlabel metal2 466 215 471 232 0 NFET_DRAIN3
+port 18 nsew analog default
+<< end >>
diff --git a/mag/sky130_hilas_TunCap01.mag b/mag/sky130_hilas_TunCap01.mag
new file mode 100644
index 0000000..25c608c
--- /dev/null
+++ b/mag/sky130_hilas_TunCap01.mag
@@ -0,0 +1,19 @@
+magic
+tech sky130A
+timestamp 1608066871
+<< error_p >>
+rect -1394 -283 -1388 -277
+rect -1341 -283 -1335 -277
+rect -1400 -333 -1394 -327
+rect -1335 -333 -1329 -327
+<< nwell >>
+rect -1451 -400 -1278 -210
+<< mvvaractor >>
+rect -1394 -333 -1335 -283
+<< mvnsubdiff >>
+rect -1394 -283 -1335 -247
+rect -1394 -367 -1335 -333
+<< poly >>
+rect -1436 -333 -1394 -283
+rect -1335 -333 -1293 -283
+<< end >>
diff --git a/mag/sky130_hilas_TunVaractorCapcitor.mag b/mag/sky130_hilas_TunVaractorCapcitor.mag
new file mode 100644
index 0000000..9e4fbac
--- /dev/null
+++ b/mag/sky130_hilas_TunVaractorCapcitor.mag
@@ -0,0 +1,202 @@
+magic
+tech sky130A
+timestamp 1606589603
+<< error_p >>
+rect -1466 226 -1381 259
+rect -869 161 -863 167
+rect -820 161 -814 167
+rect -1393 135 -1387 141
+rect -1341 135 -1335 141
+rect -1399 77 -1393 83
+rect -1335 77 -1329 83
+rect -1393 25 -1387 31
+rect -1341 25 -1335 31
+rect -875 -23 -869 -17
+rect -814 -23 -808 -17
+rect -805 -23 -769 -22
+rect -1399 -32 -1393 -26
+rect -1335 -32 -1329 -26
+rect -873 -51 -872 -47
+rect -873 -72 -867 -66
+rect -820 -72 -814 -66
+rect -1393 -83 -1387 -77
+rect -1341 -83 -1335 -77
+rect -1400 -133 -1393 -127
+rect -1335 -133 -1329 -127
+rect -879 -147 -873 -141
+rect -814 -147 -808 -141
+rect -534 -175 -513 -174
+rect -1394 -183 -1388 -177
+rect -1341 -183 -1335 -177
+rect -1400 -233 -1394 -227
+rect -1335 -233 -1329 -227
+rect -900 -244 -875 -223
+rect -900 -248 -869 -244
+rect -806 -248 -800 -242
+rect -900 -275 -875 -248
+rect -1394 -283 -1388 -277
+rect -1341 -283 -1335 -277
+rect -1400 -333 -1394 -327
+rect -1335 -333 -1329 -327
+rect -884 -362 -875 -344
+rect -866 -362 -865 -361
+rect -800 -362 -794 -356
+rect -778 -362 -775 -250
+rect -916 -364 -875 -362
+rect -867 -363 -775 -362
+rect -866 -364 -775 -363
+rect -891 -387 -875 -364
+rect -521 -408 -491 -407
+rect -554 -441 -507 -440
+rect -425 -442 -423 -356
+<< nwell >>
+rect -1466 175 -1275 226
+rect -1465 -440 -1275 175
+rect -992 26 -713 224
+rect -994 -253 -712 26
+rect -990 -440 -712 -253
+rect -572 -440 -425 226
+rect -507 -442 -425 -440
+<< mvpmos >>
+rect -521 116 -491 166
+rect -521 -21 -491 30
+rect -521 -94 -491 -42
+rect -521 -175 -491 -123
+rect -521 -246 -491 -196
+rect -521 -381 -491 -331
+<< mvvaractor >>
+rect -1393 77 -1335 135
+rect -1393 -32 -1335 25
+rect -869 -23 -814 161
+rect -1393 -133 -1335 -83
+rect -873 -147 -814 -72
+rect -1394 -233 -1335 -183
+rect -1394 -333 -1335 -283
+rect -875 -362 -800 -248
+rect -875 -364 -866 -362
+<< mvpdiff >>
+rect -521 189 -491 193
+rect -521 172 -515 189
+rect -497 172 -491 189
+rect -521 166 -491 172
+rect -521 110 -491 116
+rect -521 93 -515 110
+rect -497 93 -491 110
+rect -521 88 -491 93
+rect -521 53 -491 58
+rect -521 36 -515 53
+rect -497 36 -491 53
+rect -521 30 -491 36
+rect -521 -42 -491 -21
+rect -521 -100 -491 -94
+rect -521 -117 -515 -100
+rect -497 -117 -491 -100
+rect -521 -123 -491 -117
+rect -521 -196 -491 -175
+rect -521 -252 -491 -246
+rect -521 -269 -515 -252
+rect -497 -269 -491 -252
+rect -521 -273 -491 -269
+rect -521 -308 -491 -304
+rect -521 -325 -515 -308
+rect -497 -325 -491 -308
+rect -521 -331 -491 -325
+rect -521 -387 -491 -381
+rect -521 -404 -515 -387
+rect -497 -404 -491 -387
+rect -521 -408 -491 -404
+<< mvpdiffc >>
+rect -515 172 -497 189
+rect -515 93 -497 110
+rect -515 36 -497 53
+rect -515 -117 -497 -100
+rect -515 -269 -497 -252
+rect -515 -325 -497 -308
+rect -515 -404 -497 -387
+<< psubdiff >>
+rect -656 -361 -630 -349
+rect -656 -378 -652 -361
+rect -634 -378 -630 -361
+rect -656 -390 -630 -378
+<< mvnsubdiff >>
+rect -1393 135 -1335 182
+rect -869 161 -814 191
+rect -1393 25 -1335 77
+rect -1393 -83 -1335 -32
+rect -869 -43 -814 -23
+rect -872 -51 -814 -43
+rect -873 -72 -814 -51
+rect -1394 -183 -1335 -133
+rect -873 -190 -814 -147
+rect -1394 -283 -1335 -233
+rect -875 -248 -800 -190
+rect -1394 -360 -1335 -333
+rect -1394 -387 -1379 -360
+rect -1351 -387 -1335 -360
+rect -866 -364 -800 -362
+rect -1394 -397 -1335 -387
+rect -875 -403 -800 -364
+<< psubdiffcont >>
+rect -652 -378 -634 -361
+<< mvnsubdiffcont >>
+rect -1379 -387 -1351 -360
+<< poly >>
+rect -915 160 -869 161
+rect -1436 77 -1393 135
+rect -1335 77 -1292 135
+rect -917 54 -869 160
+rect -951 27 -869 54
+rect -1435 -32 -1393 25
+rect -1335 -32 -1292 25
+rect -917 -23 -869 27
+rect -814 54 -769 161
+rect -555 116 -521 166
+rect -491 116 -478 166
+rect -814 27 -743 54
+rect -555 30 -534 116
+rect -814 -22 -769 27
+rect -555 -21 -521 30
+rect -491 -21 -476 30
+rect -814 -23 -805 -22
+rect -1435 -133 -1393 -83
+rect -1335 -133 -1291 -83
+rect -915 -147 -873 -72
+rect -814 -147 -771 -72
+rect -535 -94 -521 -42
+rect -491 -94 -465 -42
+rect -488 -123 -465 -94
+rect -1436 -233 -1394 -183
+rect -1335 -233 -1292 -183
+rect -534 -175 -521 -123
+rect -491 -175 -465 -123
+rect -550 -196 -534 -195
+rect -550 -246 -521 -196
+rect -491 -246 -472 -196
+rect -1436 -333 -1394 -283
+rect -1335 -333 -1292 -283
+rect -927 -364 -875 -250
+rect -800 -362 -778 -248
+rect -550 -331 -534 -246
+rect -550 -381 -521 -331
+rect -491 -381 -475 -331
+rect -550 -382 -534 -381
+<< locali >>
+rect -523 172 -515 189
+rect -497 172 -489 189
+rect -523 93 -515 110
+rect -497 93 -489 110
+rect -523 36 -515 53
+rect -497 36 -489 53
+rect -524 -117 -515 -100
+rect -497 -117 -489 -100
+rect -523 -269 -515 -252
+rect -497 -269 -489 -252
+rect -523 -325 -515 -308
+rect -497 -325 -489 -308
+rect -1379 -360 -1351 -352
+rect -660 -378 -652 -361
+rect -634 -378 -626 -361
+rect -1379 -395 -1351 -387
+rect -523 -404 -515 -387
+rect -497 -404 -489 -387
+<< end >>
diff --git a/mag/sky130_hilas_VinjDecode2to4.mag b/mag/sky130_hilas_VinjDecode2to4.mag
new file mode 100644
index 0000000..e5367c9
--- /dev/null
+++ b/mag/sky130_hilas_VinjDecode2to4.mag
@@ -0,0 +1,217 @@
+magic
+tech sky130A
+timestamp 1624147000
+<< error_s >>
+rect -330 594 -329 597
+rect -330 443 -329 446
+rect -330 292 -329 295
+rect 202 225 254 226
+rect 412 225 462 226
+<< nwell >>
+rect 32 659 54 665
+rect 32 64 54 69
+<< metal1 >>
+rect -576 658 -554 666
+rect -319 657 -296 666
+rect -270 631 -243 660
+rect 32 659 54 665
+rect 529 661 556 666
+rect -274 604 -271 631
+rect -244 604 -241 631
+rect -178 612 -151 617
+rect -270 526 -243 604
+rect -271 523 -243 526
+rect -244 496 -243 523
+rect -271 493 -243 496
+rect -270 490 -243 493
+rect -224 563 -197 570
+rect -224 358 -197 536
+rect -178 471 -151 585
+rect -83 567 -54 572
+rect -85 564 -54 567
+rect -56 535 -54 564
+rect -85 532 -54 535
+rect -183 444 -180 471
+rect -153 444 -150 471
+rect -225 355 -197 358
+rect -198 328 -197 355
+rect -225 325 -197 328
+rect -224 208 -197 325
+rect -178 313 -151 444
+rect -180 310 -151 313
+rect -153 283 -151 310
+rect -180 280 -151 283
+rect -178 278 -151 280
+rect -131 417 -104 423
+rect -131 414 -103 417
+rect -131 387 -130 414
+rect -131 384 -103 387
+rect -83 410 -54 532
+rect -83 384 -81 410
+rect -55 384 -54 410
+rect -224 205 -194 208
+rect -224 178 -221 205
+rect -224 175 -194 178
+rect -224 170 -197 175
+rect -131 163 -104 384
+rect -133 160 -104 163
+rect -106 133 -104 160
+rect -133 130 -104 133
+rect -131 127 -104 130
+rect -83 267 -54 384
+rect -83 264 -53 267
+rect -83 235 -82 264
+rect -83 232 -53 235
+rect -83 110 -54 232
+rect -83 78 -54 81
+rect 32 64 54 69
+rect 529 64 556 69
+<< via1 >>
+rect -271 604 -244 631
+rect -178 585 -151 612
+rect -271 496 -244 523
+rect -224 536 -197 563
+rect -85 535 -56 564
+rect -180 444 -153 471
+rect -225 328 -198 355
+rect -180 283 -153 310
+rect -130 387 -103 414
+rect -81 384 -55 410
+rect -221 178 -194 205
+rect -133 133 -106 160
+rect -82 235 -53 264
+rect -83 81 -54 110
+<< metal2 >>
+rect -266 650 -29 651
+rect -268 635 -29 650
+rect -268 634 -241 635
+rect -271 631 -241 634
+rect -637 609 -626 627
+rect -294 609 -271 627
+rect -244 609 -241 631
+rect -271 601 -244 604
+rect -181 585 -178 612
+rect -151 606 -148 612
+rect -151 590 -29 606
+rect -151 585 -148 590
+rect -227 560 -224 563
+rect -294 542 -224 560
+rect -227 536 -224 542
+rect -197 560 -194 563
+rect -197 541 -192 560
+rect -197 536 -194 541
+rect -88 535 -85 564
+rect -56 557 -53 564
+rect -56 541 -29 557
+rect -56 535 -53 541
+rect 645 537 658 554
+rect -274 496 -271 523
+rect -244 517 -241 523
+rect -244 501 -110 517
+rect -244 496 -241 501
+rect -126 500 -110 501
+rect -126 484 -30 500
+rect -637 458 -626 476
+rect -294 474 -158 476
+rect -294 471 -153 474
+rect -294 458 -180 471
+rect -153 444 -152 455
+rect -180 441 -152 444
+rect -175 439 -152 441
+rect -125 439 -29 455
+rect -125 414 -109 439
+rect -133 409 -130 414
+rect -294 391 -130 409
+rect -133 387 -130 391
+rect -103 387 -100 414
+rect -84 384 -81 410
+rect -55 406 -52 410
+rect -55 390 -29 406
+rect -55 384 -52 390
+rect 645 386 658 403
+rect -228 328 -225 355
+rect -198 349 -195 355
+rect -198 333 -29 349
+rect -198 328 -195 333
+rect -637 307 -626 325
+rect -183 283 -180 310
+rect -153 304 -150 310
+rect -153 288 -29 304
+rect -153 283 -150 288
+rect -85 258 -82 264
+rect -294 240 -82 258
+rect -85 235 -82 240
+rect -53 258 -50 264
+rect -53 255 -36 258
+rect -53 239 -29 255
+rect -53 235 -50 239
+rect 645 235 658 252
+rect -224 178 -221 205
+rect -194 199 -191 205
+rect -194 183 -29 199
+rect -194 178 -191 183
+rect -136 133 -133 160
+rect -106 154 -103 160
+rect -106 138 -29 154
+rect -106 133 -103 138
+rect -86 81 -83 110
+rect -54 105 -51 110
+rect -54 89 -29 105
+rect -54 81 -51 89
+rect 645 85 658 102
+use sky130_hilas_VinjInv2 VinjInv2_2
+timestamp 1624141468
+transform 1 0 -301 0 1 60
+box -336 144 25 308
+use sky130_hilas_VinjInv2 VinjInv2_1
+timestamp 1624141468
+transform 1 0 -301 0 1 211
+box -336 144 25 308
+use sky130_hilas_VinjInv2 VinjInv2_0
+timestamp 1624141468
+transform 1 0 -301 0 1 362
+box -336 144 25 308
+use sky130_hilas_VinjNOR3 VinjNOR3_0
+timestamp 1624138502
+transform 1 0 307 0 1 -90
+box -337 144 351 308
+use sky130_hilas_VinjNOR3 VinjNOR3_3
+timestamp 1624138502
+transform 1 0 307 0 1 362
+box -337 144 351 308
+use sky130_hilas_VinjNOR3 VinjNOR3_1
+timestamp 1624138502
+transform 1 0 307 0 1 60
+box -337 144 351 308
+use sky130_hilas_VinjNOR3 VinjNOR3_2
+timestamp 1624138502
+transform 1 0 307 0 1 211
+box -337 144 351 308
+<< labels >>
+rlabel metal2 645 537 658 554 0 OUTPUT00
+port 1 nsew
+rlabel metal2 645 386 658 403 0 OUTPUT01
+port 2 nsew
+rlabel metal2 645 235 658 252 0 OUTPUT10
+port 3 nsew
+rlabel metal2 645 85 658 102 0 OUTPUT11
+port 4 nsew
+rlabel metal1 529 661 556 666 0 VGND
+port 5 nsew
+rlabel metal1 529 64 556 69 0 VGND
+port 5 nsew
+rlabel metal1 32 64 54 69 0 VINJ
+port 6 nsew
+rlabel metal1 32 659 54 665 0 VINJ
+port 6 nsew
+rlabel metal2 -637 609 -626 627 0 IN1
+port 8 nsew
+rlabel metal2 -637 458 -626 476 0 IN2
+port 7 nsew
+rlabel metal2 -637 307 -626 325 0 ENABLE
+port 9 nsew
+rlabel metal1 -576 658 -554 666 0 VINJ
+port 6 nsew
+rlabel metal1 -319 657 -296 666 0 VGND
+port 5 nsew
+<< end >>
diff --git a/mag/sky130_hilas_VinjDiodeProtect01.mag b/mag/sky130_hilas_VinjDiodeProtect01.mag
new file mode 100644
index 0000000..68bedab
--- /dev/null
+++ b/mag/sky130_hilas_VinjDiodeProtect01.mag
@@ -0,0 +1,629 @@
+magic
+tech sky130A
+timestamp 1626558701
+<< nwell >>
+rect 742 -38 1947 556
+<< mvndiff >>
+rect -558 543 599 548
+rect -558 526 -552 543
+rect 593 526 599 543
+rect -558 517 599 526
+rect -558 486 -527 517
+rect -558 479 599 486
+rect -558 462 -552 479
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+rect -558 400 -552 417
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+rect -558 34 599 40
+rect -558 4 -527 34
+rect -559 -4 599 4
+rect -559 -21 -552 -4
+rect 592 -21 599 -4
+rect -559 -26 599 -21
+<< mvpdiff >>
+rect 832 463 1850 472
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+rect 1819 446 1850 463
+rect 832 441 1850 446
+rect 1819 404 1850 441
+rect 836 396 1850 404
+rect 836 379 844 396
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+rect 837 99 1850 107
+rect 1819 69 1850 99
+rect 837 62 1850 69
+rect 837 45 845 62
+rect 1816 45 1850 62
+rect 837 38 1850 45
+<< mvndiffc >>
+rect -552 526 593 543
+rect -552 462 593 479
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+rect -552 340 593 357
+rect -552 281 593 298
+rect -552 222 593 239
+rect -552 163 592 180
+rect -552 102 593 119
+rect -551 40 593 57
+rect -552 -21 592 -4
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+rect 849 306 1824 323
+rect 848 238 1816 255
+rect 844 171 1818 188
+rect 843 107 1816 124
+rect 845 45 1816 62
+<< psubdiff >>
+rect -698 648 -664 649
+rect -698 646 -646 648
+rect 646 646 2054 648
+rect -698 640 2054 646
+rect -698 623 -621 640
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+rect -673 -39 -656 570
+rect -639 -39 -631 570
+rect 646 579 2056 583
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+rect -673 -55 -631 -39
+rect -698 -56 -631 -55
+rect 646 -44 651 570
+rect 668 568 709 570
+rect 668 -44 685 568
+rect 646 -45 685 -44
+rect 702 -45 709 568
+rect 1988 577 2056 579
+rect 646 -52 709 -45
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+rect 2010 573 2056 577
+rect 2010 -45 2031 573
+rect 1988 -46 2031 -45
+rect 2048 -46 2056 573
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+rect -698 -62 2056 -56
+rect -698 -79 -624 -62
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+rect -698 -96 2056 -79
+rect -698 -107 -624 -96
+rect -697 -113 -624 -107
+rect 1977 -113 2056 -96
+rect -697 -119 2056 -113
+rect -697 -123 -631 -119
+rect 535 -121 2056 -119
+rect -697 -124 -646 -123
+<< nsubdiff >>
+rect 773 517 1909 523
+rect 773 500 802 517
+rect 1869 500 1909 517
+rect 773 495 1909 500
+rect 773 482 801 495
+rect 773 23 778 482
+rect 795 23 801 482
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+rect 773 11 801 23
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+rect 1903 23 1909 492
+rect 1881 11 1909 23
+rect 767 6 1909 11
+rect 767 -11 808 6
+rect 1875 -11 1909 6
+rect 767 -17 1909 -11
+<< psubdiffcont >>
+rect -621 623 1966 640
+rect -621 589 1966 606
+rect -690 -55 -673 583
+rect -656 -39 -639 570
+rect 651 -44 668 570
+rect 685 -45 702 568
+rect 1993 -45 2010 577
+rect 2031 -46 2048 573
+rect -624 -79 1977 -62
+rect -624 -113 1977 -96
+<< nsubdiffcont >>
+rect 802 500 1869 517
+rect 778 23 795 482
+rect 1886 23 1903 492
+rect 808 -11 1875 6
+<< poly >>
+rect 32 796 49 807
+rect 700 796 717 805
+rect 23 790 73 796
+rect 23 773 32 790
+rect 49 773 73 790
+rect 23 756 73 773
+rect 23 739 32 756
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+rect 717 703 726 720
+rect 654 686 726 703
+rect 654 669 700 686
+rect 717 669 726 686
+rect 654 664 726 669
+<< polycont >>
+rect 32 773 49 790
+rect 32 739 49 756
+rect 32 705 49 722
+rect 32 671 49 688
+rect 700 771 717 788
+rect 700 737 717 754
+rect 700 703 717 720
+rect 700 669 717 686
+<< npolyres >>
+rect 73 664 654 796
+<< locali >>
+rect 28 807 53 810
+rect 28 671 32 807
+rect 49 671 53 807
+rect 28 664 53 671
+rect 696 805 721 808
+rect 696 669 700 805
+rect 717 669 721 805
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+rect 696 661 721 669
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+rect -690 589 -621 606
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+rect -690 583 -674 589
+rect -656 588 -610 589
+rect -656 570 -638 588
+rect -673 -39 -656 397
+rect -639 396 -638 570
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+rect 834 139 856 156
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+rect 834 75 857 92
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+rect 834 62 1847 75
+rect 834 45 845 62
+rect 1816 45 1847 62
+rect 834 44 1847 45
+rect 834 36 1845 44
+rect 778 13 795 23
+rect 777 6 795 13
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+rect -690 -62 -639 -55
+rect -565 -62 -385 -61
+rect 651 -62 702 -45
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+rect 2031 573 2048 600
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+rect -690 -79 -624 -62
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+rect -690 -96 2048 -79
+rect -687 -113 -624 -96
+rect 1977 -113 2048 -96
+rect -687 -115 -618 -113
+rect -567 -114 -387 -113
+<< viali >>
+rect 32 790 49 807
+rect 32 756 49 773
+rect 32 722 49 739
+rect 32 688 49 705
+rect 700 788 717 805
+rect 700 754 717 771
+rect 700 720 717 737
+rect 700 686 717 703
+rect -682 623 -621 624
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+rect -682 606 -495 623
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+rect -674 583 -656 589
+rect -674 510 -673 583
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+rect -638 396 -620 588
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+rect -519 431 579 448
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+rect 856 270 1796 287
+rect 857 204 1794 221
+rect 856 139 1801 156
+rect 857 75 1796 92
+rect 1904 -17 1939 313
+rect 2011 507 2031 600
+<< metal1 >>
+rect 26 807 416 858
+rect 26 790 32 807
+rect 49 799 416 807
+rect 690 805 725 811
+rect 49 790 55 799
+rect 690 796 700 805
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+rect 717 788 726 796
+rect 689 771 726 788
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+rect 689 737 726 754
+rect 689 720 700 737
+rect 717 720 726 737
+rect 689 703 726 720
+rect 689 701 700 703
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+rect 717 686 901 701
+rect 511 664 901 686
+rect -701 632 -464 647
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+rect -701 599 -679 606
+rect -476 599 -464 632
+rect -701 589 -464 599
+rect -701 584 -674 589
+rect -698 575 -674 584
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+rect -656 575 -638 588
+rect -620 584 -464 588
+rect -620 575 -603 584
+rect -528 582 -470 584
+rect -698 513 -685 575
+rect -615 513 -603 575
+rect 510 518 901 664
+rect 1633 634 2046 639
+rect 1633 623 1660 634
+rect 1959 623 2046 634
+rect 1633 605 1654 623
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+rect 1633 599 1660 605
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+rect 2031 599 2046 600
+rect 2031 595 2047 599
+rect 1633 590 2003 595
+rect -461 517 901 518
+rect -698 510 -674 513
+rect -698 397 -673 510
+rect -656 397 -638 513
+rect -698 396 -638 397
+rect -620 396 -603 513
+rect -698 388 -603 396
+rect -675 -179 -603 388
+rect -528 510 901 517
+rect -528 493 -519 510
+rect 579 493 901 510
+rect 1994 519 2003 590
+rect 2038 519 2047 595
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+rect 2031 507 2047 519
+rect 1994 500 2047 507
+rect -528 461 901 493
+rect -528 448 1807 461
+rect -528 431 -519 448
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+rect 579 431 854 434
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+rect -528 386 1807 417
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+rect -528 342 853 359
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+rect -528 328 1807 342
+rect -528 311 -516 328
+rect 582 311 1807 328
+rect -528 287 1807 311
+rect -528 270 856 287
+rect 1796 270 1807 287
+rect -528 269 1807 270
+rect -528 252 -515 269
+rect 583 252 1807 269
+rect -528 221 1807 252
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+rect -528 192 -515 209
+rect 583 204 857 209
+rect 1794 204 1807 221
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+rect 578 132 1807 139
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+rect -528 88 857 92
+rect -528 71 -519 88
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+rect 1796 75 1807 92
+rect 579 71 1807 75
+rect -528 31 1807 71
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+rect -528 28 901 31
+rect -528 11 -520 28
+rect 578 11 901 28
+rect -528 3 901 11
+rect 510 -152 901 3
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+rect 1942 -10 1946 307
+rect 1884 -17 1904 -10
+rect 1939 -17 1946 -10
+rect 1884 -23 1946 -17
+rect 1884 -24 1941 -23
+rect 1801 -140 1857 -137
+rect 508 -229 903 -152
+rect 1801 -187 1803 -140
+rect 1802 -192 1803 -187
+rect 1855 -192 1857 -140
+rect 1802 -209 1857 -192
+<< via1 >>
+rect -679 624 -476 632
+rect -679 623 -496 624
+rect -496 623 -476 624
+rect -679 606 -495 623
+rect -495 606 -476 623
+rect -679 599 -476 606
+rect -685 513 -674 575
+rect -674 513 -656 575
+rect -656 513 -638 575
+rect -638 513 -620 575
+rect -620 513 -615 575
+rect 1660 623 1959 634
+rect 1660 605 1959 623
+rect 1660 599 1959 605
+rect 2003 519 2011 595
+rect 2011 519 2031 595
+rect 2031 519 2038 595
+rect 1900 -10 1904 307
+rect 1904 -10 1939 307
+rect 1939 -10 1942 307
+rect 1803 -192 1855 -140
+<< metal2 >>
+rect -745 634 2114 649
+rect -745 632 1660 634
+rect -745 599 -679 632
+rect -476 599 1660 632
+rect 1959 599 2114 634
+rect -745 595 2114 599
+rect -745 575 2003 595
+rect -745 513 -685 575
+rect -615 519 2003 575
+rect 2038 519 2114 595
+rect -615 513 2114 519
+rect -745 509 2114 513
+rect -698 508 -605 509
+rect -673 397 -656 508
+rect 1889 307 1953 320
+rect 1889 19 1900 307
+rect -745 -10 1900 19
+rect 1942 19 1953 307
+rect 1942 -10 2114 19
+rect -745 -121 2114 -10
+rect 1799 -134 2062 -121
+rect 1799 -140 2054 -134
+rect 1799 -192 1803 -140
+rect 1855 -185 2054 -140
+rect 1855 -192 1861 -185
+<< labels >>
+rlabel metal1 508 -229 903 -152 0 OUTPUT
+port 2 nsew
+rlabel space -744 508 -721 649 0 VGND
+port 3 nsew
+rlabel metal2 2078 509 2114 649 0 VGND
+port 3 nsew
+rlabel metal2 -744 -121 -723 19 0 VINJ
+port 4 nsew
+rlabel metal2 2084 -121 2114 19 0 VINJ
+port 4 nsew
+rlabel metal1 26 811 415 858 0 INPUT
+port 5 nsew
+rlabel metal2 1875 -185 2054 -160 0 VINJ
+port 4 nsew
+rlabel metal1 -675 -179 -603 -145 0 VGND
+port 3 nsew
+<< end >>
diff --git a/mag/sky130_hilas_VinjInv2.mag b/mag/sky130_hilas_VinjInv2.mag
new file mode 100644
index 0000000..934930e
--- /dev/null
+++ b/mag/sky130_hilas_VinjInv2.mag
@@ -0,0 +1,149 @@
+magic
+tech sky130A
+timestamp 1624141468
+<< error_p >>
+rect -29 232 -28 235
+<< nwell >>
+rect -336 144 -138 308
+<< mvnmos >>
+rect -73 177 -21 209
+<< mvpmos >>
+rect -252 177 -199 210
+<< mvndiff >>
+rect -101 202 -73 209
+rect -101 185 -96 202
+rect -79 185 -73 202
+rect -101 177 -73 185
+rect -21 201 7 209
+rect -21 184 -15 201
+rect 2 184 7 201
+rect -21 177 7 184
+<< mvpdiff >>
+rect -279 202 -252 210
+rect -279 185 -275 202
+rect -258 185 -252 202
+rect -279 177 -252 185
+rect -199 202 -171 210
+rect -199 185 -193 202
+rect -176 185 -171 202
+rect -199 177 -171 185
+<< mvndiffc >>
+rect -96 185 -79 202
+rect -15 184 2 201
+<< mvpdiffc >>
+rect -275 185 -258 202
+rect -193 185 -176 202
+<< psubdiff >>
+rect -29 256 15 264
+rect -29 239 -15 256
+rect 2 239 15 256
+rect -29 232 15 239
+<< mvnsubdiff >>
+rect -286 267 -245 275
+rect -286 250 -274 267
+rect -257 250 -245 267
+rect -286 241 -245 250
+<< psubdiffcont >>
+rect -15 239 2 256
+<< mvnsubdiffcont >>
+rect -274 250 -257 267
+<< poly >>
+rect -322 224 -36 227
+rect -322 212 -21 224
+rect -322 202 -295 212
+rect -252 210 -199 212
+rect -322 185 -317 202
+rect -300 185 -295 202
+rect -322 177 -295 185
+rect -73 209 -21 212
+rect -252 164 -199 177
+rect -73 164 -21 177
+<< polycont >>
+rect -317 185 -300 202
+<< locali >>
+rect -274 267 -257 279
+rect -274 248 -272 250
+rect -15 256 2 264
+rect -274 238 -257 248
+rect -15 229 2 239
+rect -317 202 -300 210
+rect -302 183 -300 185
+rect -317 177 -300 183
+rect -275 204 -258 210
+rect -275 202 -250 204
+rect -258 197 -250 202
+rect -275 180 -271 185
+rect -254 180 -250 197
+rect -201 202 -176 210
+rect -201 185 -193 202
+rect -176 185 -137 202
+rect -120 185 -96 202
+rect -79 185 -71 202
+rect -15 201 2 212
+rect -275 177 -250 180
+rect -274 175 -250 177
+rect -193 176 -176 185
+rect -23 184 -15 201
+rect 2 184 10 201
+<< viali >>
+rect -272 250 -257 265
+rect -257 250 -255 265
+rect -272 248 -255 250
+rect -15 212 2 229
+rect -319 185 -317 200
+rect -317 185 -302 200
+rect -319 183 -302 185
+rect -271 185 -258 197
+rect -258 185 -254 197
+rect -271 180 -254 185
+rect -137 185 -120 202
+<< metal1 >>
+rect -275 270 -253 304
+rect -275 265 -252 270
+rect -275 248 -272 265
+rect -255 248 -252 265
+rect -275 244 -252 248
+rect -328 205 -297 211
+rect -328 179 -325 205
+rect -299 179 -297 205
+rect -328 176 -297 179
+rect -275 204 -253 244
+rect -18 229 5 304
+rect -18 212 -15 229
+rect 2 212 5 229
+rect -275 197 -250 204
+rect -275 180 -271 197
+rect -254 180 -250 197
+rect -145 180 -142 206
+rect -116 180 -113 206
+rect -275 173 -250 180
+rect -275 153 -253 173
+rect -18 153 5 212
+<< via1 >>
+rect -325 200 -299 205
+rect -325 183 -319 200
+rect -319 183 -302 200
+rect -302 183 -299 200
+rect -325 179 -299 183
+rect -142 202 -116 206
+rect -142 185 -137 202
+rect -137 185 -120 202
+rect -120 185 -116 202
+rect -142 180 -116 185
+<< metal2 >>
+rect -336 247 25 265
+rect -328 195 -325 205
+rect -329 179 -325 195
+rect -299 179 -296 205
+rect -145 180 -142 206
+rect -116 198 -113 206
+rect -116 180 25 198
+<< labels >>
+rlabel metal1 -275 153 -253 159 0 Vinj
+rlabel metal1 -275 297 -253 304 0 Vinj
+rlabel metal1 -18 295 5 304 0 GND
+rlabel metal1 -18 153 5 159 0 GND
+rlabel metal2 -336 247 -326 265 0 Input
+rlabel metal2 16 247 25 265 0 Input
+rlabel metal2 16 180 25 198 0 Output
+<< end >>
diff --git a/mag/sky130_hilas_VinjNOR3.mag b/mag/sky130_hilas_VinjNOR3.mag
new file mode 100644
index 0000000..8d94b18
--- /dev/null
+++ b/mag/sky130_hilas_VinjNOR3.mag
@@ -0,0 +1,288 @@
+magic
+tech sky130A
+timestamp 1624138502
+<< nwell >>
+rect -336 144 8 308
+<< mvnmos >>
+rect 176 239 226 271
+rect 105 178 155 209
+rect 247 178 297 209
+<< mvpmos >>
+rect -178 241 -126 275
+rect -252 177 -199 210
+rect -105 178 -53 210
+<< mvndiff >>
+rect 145 263 176 271
+rect 145 246 152 263
+rect 169 246 176 263
+rect 145 239 176 246
+rect 226 263 253 271
+rect 226 246 232 263
+rect 249 246 253 263
+rect 226 239 253 246
+rect 76 202 105 209
+rect 76 185 81 202
+rect 98 185 105 202
+rect 76 178 105 185
+rect 155 202 183 209
+rect 155 185 161 202
+rect 178 185 183 202
+rect 155 178 183 185
+rect 219 202 247 209
+rect 219 185 224 202
+rect 241 185 247 202
+rect 219 178 247 185
+rect 297 202 326 209
+rect 297 185 303 202
+rect 320 185 326 202
+rect 297 178 326 185
+<< mvpdiff >>
+rect -206 267 -178 275
+rect -206 250 -201 267
+rect -184 250 -178 267
+rect -206 241 -178 250
+rect -126 267 -98 275
+rect -126 250 -120 267
+rect -103 250 -98 267
+rect -126 241 -98 250
+rect -279 202 -252 210
+rect -279 185 -275 202
+rect -258 185 -252 202
+rect -279 177 -252 185
+rect -199 202 -171 210
+rect -199 185 -193 202
+rect -176 185 -171 202
+rect -199 177 -171 185
+rect -132 202 -105 210
+rect -132 185 -128 202
+rect -111 185 -105 202
+rect -132 178 -105 185
+rect -53 202 -26 210
+rect -53 185 -47 202
+rect -30 185 -26 202
+rect -53 178 -26 185
+<< mvndiffc >>
+rect 152 246 169 263
+rect 232 246 249 263
+rect 81 185 98 202
+rect 161 185 178 202
+rect 224 185 241 202
+rect 303 185 320 202
+<< mvpdiffc >>
+rect -201 250 -184 267
+rect -120 250 -103 267
+rect -275 185 -258 202
+rect -193 185 -176 202
+rect -128 185 -111 202
+rect -47 185 -30 202
+<< psubdiff >>
+rect 292 264 333 271
+rect 292 247 304 264
+rect 321 247 333 264
+rect 292 239 333 247
+<< mvnsubdiff >>
+rect -286 267 -245 275
+rect -286 250 -274 267
+rect -257 250 -245 267
+rect -286 241 -245 250
+<< psubdiffcont >>
+rect 304 247 321 264
+<< mvnsubdiffcont >>
+rect -274 250 -257 267
+<< poly >>
+rect -143 289 194 295
+rect -178 284 194 289
+rect -178 278 226 284
+rect -178 275 -126 278
+rect 25 275 60 278
+rect 25 258 34 275
+rect 51 258 60 275
+rect 176 271 226 278
+rect -74 251 -39 257
+rect 25 251 60 258
+rect -322 226 -236 227
+rect -322 212 -199 226
+rect -178 225 -126 241
+rect -74 234 -64 251
+rect -47 234 -39 251
+rect -74 230 -39 234
+rect -74 225 123 230
+rect 176 225 226 239
+rect -322 202 -295 212
+rect -252 210 -199 212
+rect -105 223 123 225
+rect -105 213 155 223
+rect -105 210 -53 213
+rect -322 185 -317 202
+rect -300 185 -295 202
+rect -322 177 -295 185
+rect 105 209 155 213
+rect 247 209 297 223
+rect -252 164 -199 177
+rect -105 165 -53 178
+rect 105 165 155 178
+rect 247 165 297 178
+<< polycont >>
+rect 34 258 51 275
+rect -64 234 -47 251
+rect -317 185 -300 202
+<< locali >>
+rect -274 267 -257 279
+rect 34 275 51 283
+rect -201 267 -184 275
+rect -120 267 -103 275
+rect -274 248 -272 250
+rect -184 250 -180 267
+rect -274 238 -257 248
+rect -201 210 -180 250
+rect -124 250 -120 267
+rect -124 242 -103 250
+rect -64 251 -47 259
+rect 223 264 249 271
+rect 303 264 321 277
+rect 223 263 304 264
+rect 47 254 51 258
+rect 34 250 51 254
+rect -124 210 -107 242
+rect -50 232 -47 234
+rect -64 222 -47 232
+rect 90 246 152 263
+rect 169 246 177 263
+rect 223 246 232 263
+rect 249 247 304 263
+rect 249 246 321 247
+rect -317 202 -300 210
+rect -302 183 -300 185
+rect -317 177 -300 183
+rect -275 204 -258 210
+rect -275 202 -250 204
+rect -258 197 -250 202
+rect -275 180 -271 185
+rect -254 180 -250 197
+rect -201 202 -176 210
+rect -201 185 -193 202
+rect -275 177 -250 180
+rect -274 175 -250 177
+rect -193 176 -176 185
+rect -128 202 -107 210
+rect 90 202 107 246
+rect 223 232 249 246
+rect 303 235 321 246
+rect 223 214 226 232
+rect 244 214 249 232
+rect 223 202 249 214
+rect -111 185 -107 202
+rect -56 185 -47 202
+rect -30 198 81 202
+rect -30 185 21 198
+rect -128 177 -111 185
+rect 38 185 81 198
+rect 98 185 107 202
+rect 152 185 161 202
+rect 178 185 224 202
+rect 241 185 249 202
+rect 294 185 303 202
+rect 320 185 328 202
+<< viali >>
+rect -272 250 -257 265
+rect -257 250 -255 265
+rect -272 248 -255 250
+rect 30 258 34 271
+rect 34 258 47 271
+rect 30 254 47 258
+rect -67 234 -64 249
+rect -64 234 -50 249
+rect -67 232 -50 234
+rect -319 185 -317 200
+rect -317 185 -302 200
+rect -319 183 -302 185
+rect -271 185 -258 197
+rect -258 185 -254 197
+rect -271 180 -254 185
+rect 226 214 244 232
+rect 21 181 38 198
+<< metal1 >>
+rect -275 270 -253 304
+rect -275 265 -252 270
+rect -275 248 -272 265
+rect -255 248 -252 265
+rect -275 244 -252 248
+rect -328 205 -297 211
+rect -328 179 -325 205
+rect -299 179 -297 205
+rect -328 176 -297 179
+rect -275 204 -253 244
+rect -73 228 -69 254
+rect -43 228 -40 254
+rect 24 253 30 279
+rect 56 253 67 279
+rect 24 250 67 253
+rect 222 232 249 305
+rect 222 214 226 232
+rect 244 214 249 232
+rect -275 197 -250 204
+rect -275 180 -271 197
+rect -254 180 -250 197
+rect -275 173 -250 180
+rect 11 201 50 202
+rect 11 175 17 201
+rect 43 175 50 201
+rect -275 153 -253 173
+rect 222 153 249 214
+rect 304 205 335 208
+rect 304 179 307 205
+rect 333 179 335 205
+rect 304 176 335 179
+<< via1 >>
+rect -325 200 -299 205
+rect -325 183 -319 200
+rect -319 183 -302 200
+rect -302 183 -299 200
+rect -325 179 -299 183
+rect -69 249 -43 254
+rect -69 232 -67 249
+rect -67 232 -50 249
+rect -50 232 -43 249
+rect -69 228 -43 232
+rect 30 271 56 279
+rect 30 254 47 271
+rect 47 254 56 271
+rect 30 253 56 254
+rect 17 198 43 201
+rect 17 181 21 198
+rect 21 181 38 198
+rect 38 181 43 198
+rect 17 175 43 181
+rect 307 179 333 205
+<< metal2 >>
+rect -337 279 67 289
+rect -337 273 30 279
+rect -73 246 -69 254
+rect -100 244 -69 246
+rect -336 228 -69 244
+rect -43 228 -40 254
+rect 25 253 30 273
+rect 56 253 67 279
+rect 25 250 67 253
+rect 304 205 335 208
+rect -328 195 -325 205
+rect -336 179 -325 195
+rect -299 179 -296 205
+rect 13 175 17 201
+rect 43 193 50 201
+rect 43 192 116 193
+rect 304 192 307 205
+rect 43 179 307 192
+rect 333 192 335 205
+rect 333 179 351 192
+rect 43 175 351 179
+<< labels >>
+rlabel metal2 345 175 351 192 0 Output
+rlabel metal2 -337 273 -331 289 0 Input1
+rlabel space -337 228 -331 244 0 Input2
+rlabel space -337 179 -331 195 0 Input3
+rlabel metal1 222 299 249 305 0 GND
+rlabel metal1 222 153 249 158 0 GND
+rlabel metal1 -275 153 -253 159 0 Vinj
+rlabel metal1 -275 297 -253 304 0 Vinj
+<< end >>
diff --git a/mag/sky130_hilas_WTA4Stage01.mag b/mag/sky130_hilas_WTA4Stage01.mag
new file mode 100644
index 0000000..f140284
--- /dev/null
+++ b/mag/sky130_hilas_WTA4Stage01.mag
@@ -0,0 +1,207 @@
+magic
+tech sky130A
+timestamp 1625404155
+<< error_s >>
+rect -596 499 -590 505
+rect -491 499 -485 505
+rect -170 489 -164 495
+rect -117 489 -111 495
+rect -602 435 -596 441
+rect -485 435 -479 441
+rect -176 439 -170 445
+rect -111 439 -105 445
+rect -596 382 -590 388
+rect -491 382 -485 388
+rect -170 380 -164 386
+rect -117 380 -111 386
+rect -176 330 -170 336
+rect -111 330 -105 336
+rect -602 318 -596 324
+rect -485 318 -479 324
+rect -596 197 -590 203
+rect -491 197 -485 203
+rect -333 192 -316 196
+rect -170 191 -164 197
+rect -117 191 -111 197
+rect -176 141 -170 147
+rect -111 141 -105 147
+rect -602 133 -596 139
+rect -485 133 -479 139
+rect -596 81 -590 87
+rect -491 81 -485 87
+rect -170 74 -164 80
+rect -117 74 -111 80
+rect -176 24 -170 30
+rect -111 24 -105 30
+rect -602 17 -596 23
+rect -485 17 -479 23
+<< nwell >>
+rect -1101 561 -805 562
+rect -1101 546 -1060 561
+rect -532 552 -494 562
+rect -129 548 -89 562
+rect -1101 545 -1042 546
+rect -1101 369 -1060 545
+rect -1112 254 -1060 369
+rect -1101 -42 -1060 254
+<< poly >>
+rect 209 516 229 562
+rect 209 -43 229 -18
+<< locali >>
+rect -1115 -22 -1097 67
+<< metal1 >>
+rect -1025 555 -1009 562
+rect -984 555 -965 562
+rect -944 555 -928 562
+rect -532 552 -494 562
+rect -129 548 -89 562
+rect 131 516 154 562
+rect 257 516 280 562
+rect -782 430 -761 504
+rect -1112 254 -1091 369
+rect -784 93 -768 243
+rect 257 127 280 132
+rect 253 126 281 127
+rect 253 124 283 126
+rect 253 97 254 124
+rect 281 97 283 124
+rect 253 94 283 97
+rect -532 -43 -494 -33
+rect 131 -43 154 -18
+rect 257 -43 280 -18
+<< via1 >>
+rect 254 97 281 124
+<< metal2 >>
+rect -758 512 7 531
+rect -1116 494 -1061 512
+rect -758 510 24 512
+rect -14 491 24 510
+rect -1112 418 -1097 469
+rect -54 457 -50 466
+rect -65 437 56 457
+rect 170 426 296 442
+rect -1112 402 -769 418
+rect -1112 352 -1086 378
+rect -1107 351 -1090 352
+rect -55 351 66 371
+rect 170 333 296 349
+rect -1118 308 -1061 326
+rect -791 304 -768 305
+rect -791 301 -34 304
+rect -791 284 -28 301
+rect -791 274 -767 284
+rect -1112 256 -767 274
+rect -47 264 24 284
+rect -1112 254 -775 256
+rect -777 234 -32 236
+rect -777 214 24 234
+rect -777 213 -745 214
+rect -1116 193 -1061 211
+rect -1116 192 -1100 193
+rect -1118 118 -1098 168
+rect -56 152 44 168
+rect 170 149 296 165
+rect 251 124 284 125
+rect -1118 98 -763 118
+rect 251 116 254 124
+rect -384 99 254 116
+rect 251 97 254 99
+rect 281 97 284 124
+rect 251 96 284 97
+rect -1119 47 -1091 74
+rect -55 54 45 71
+rect 172 56 296 72
+rect -55 53 39 54
+rect -1114 26 -1098 27
+rect -1114 8 -1061 26
+rect -32 8 23 9
+rect -790 -14 23 8
+rect -790 -15 -31 -14
+rect -790 -16 -713 -15
+rect -790 -20 -766 -16
+rect -1114 -40 -766 -20
+rect -1114 -41 -847 -40
+use sky130_hilas_m12m2 sky130_hilas_m12m2_4
+timestamp 1607949437
+transform 1 0 -778 0 1 221
+box -9 -10 23 22
+use sky130_hilas_m12m2 sky130_hilas_m12m2_5
+timestamp 1607949437
+transform 1 0 -794 0 1 103
+box -9 -10 23 22
+use sky130_hilas_m12m2 sky130_hilas_m12m2_2
+timestamp 1607949437
+transform 1 0 -778 0 1 409
+box -9 -10 23 22
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607949437
+transform 1 0 -776 0 1 514
+box -9 -10 23 22
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 -1102 0 1 -26
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 -1107 0 1 59
+box -14 -15 20 18
+use sky130_hilas_m12m2 sky130_hilas_m12m2_3
+timestamp 1607949437
+transform 1 0 -1105 0 1 359
+box -9 -10 23 22
+use sky130_hilas_m12m2 sky130_hilas_m12m2_1
+timestamp 1607949437
+transform 1 0 -1107 0 1 258
+box -9 -10 23 22
+use sky130_hilas_WTA4stage01 sky130_hilas_WTA4stage01_0
+timestamp 1607370486
+transform 1 0 67 0 1 -19
+box -54 1 229 535
+use sky130_hilas_swc4x1BiasCell sky130_hilas_swc4x1BiasCell_0
+timestamp 1625403878
+transform -1 0 -317 0 1 339
+box -266 -382 745 223
+<< labels >>
+rlabel metal2 289 426 296 442 0 OUTPUT1
+port 4 nsew analog default
+rlabel metal2 291 333 296 349 0 OUTPUT2
+port 5 nsew analog default
+rlabel metal2 291 149 296 165 0 OUTPUT3
+port 6 nsew analog default
+rlabel metal2 291 56 296 72 0 OUTPUT4
+port 7 nsew analog default
+rlabel metal1 257 556 280 562 0 VGND
+port 1 nsew ground default
+rlabel metal1 257 -43 280 -37 0 VGND
+port 1 nsew ground default
+rlabel metal2 -1112 449 -1097 469 0 INPUT1
+port 8 nsew analog default
+rlabel metal2 -1112 352 -1086 378 0 INPUT2
+port 9 nsew analog default
+rlabel metal2 -1118 151 -1098 168 0 INPUT3
+port 10 nsew analog default
+rlabel metal2 -1119 47 -1091 74 0 INPUT4
+port 11 nsew analog default
+rlabel metal2 -1100 494 -1088 512 0 DRAIN1
+port 12 nsew
+rlabel metal2 -1100 308 -1088 326 0 DRAIN2
+port 13 nsew
+rlabel metal2 -1100 193 -1088 211 0 DRAIN3
+port 14 nsew
+rlabel metal2 -1100 8 -1088 26 0 DRAIN4
+port 15 nsew
+rlabel metal1 -531 552 -495 562 0 GATE1
+port 16 nsew
+rlabel metal1 -129 548 -89 562 0 VTUN
+port 17 nsew
+rlabel metal1 131 -43 154 -37 0 WTAMIDDLENODE
+port 18 nsew
+rlabel metal1 131 556 154 562 0 WTAMIDDLENODE
+port 18 nsew
+rlabel metal1 -984 555 -965 562 0 COLSEL1
+port 19 nsew
+rlabel metal1 -1025 555 -1009 562 0 VINJ
+port 21 nsew
+rlabel metal1 -944 555 -928 562 0 VPWR
+port 20 nsew
+<< end >>
diff --git a/mag/sky130_hilas_WTA4stage01.mag b/mag/sky130_hilas_WTA4stage01.mag
new file mode 100644
index 0000000..d43df5f
--- /dev/null
+++ b/mag/sky130_hilas_WTA4stage01.mag
@@ -0,0 +1,27 @@
+magic
+tech sky130A
+timestamp 1607370486
+<< poly >>
+rect 142 506 162 535
+rect 141 229 162 308
+rect 142 1 162 30
+<< metal1 >>
+rect 64 258 87 278
+rect 190 258 213 279
+use sky130_hilas_WTAsinglestage01 sky130_hilas_WTAsinglestage01_3
+timestamp 1607090551
+transform 1 0 54 0 1 354
+box -108 -76 175 67
+use sky130_hilas_WTAsinglestage01 sky130_hilas_WTAsinglestage01_2
+timestamp 1607090551
+transform 1 0 54 0 -1 459
+box -108 -76 175 67
+use sky130_hilas_WTAsinglestage01 sky130_hilas_WTAsinglestage01_1
+timestamp 1607090551
+transform 1 0 54 0 -1 182
+box -108 -76 175 67
+use sky130_hilas_WTAsinglestage01 sky130_hilas_WTAsinglestage01_0
+timestamp 1607090551
+transform 1 0 54 0 1 77
+box -108 -76 175 67
+<< end >>
diff --git a/mag/sky130_hilas_WTAblockSample01.mag b/mag/sky130_hilas_WTAblockSample01.mag
new file mode 100644
index 0000000..edbd0f8
--- /dev/null
+++ b/mag/sky130_hilas_WTAblockSample01.mag
@@ -0,0 +1,238 @@
+magic
+tech sky130A
+timestamp 1607392100
+<< error_s >>
+rect -1540 1135 -1534 1141
+rect -1435 1135 -1429 1141
+rect -569 1135 -563 1141
+rect -464 1135 -458 1141
+rect 510 1135 516 1141
+rect 615 1135 621 1141
+rect -1114 1125 -1108 1131
+rect -1061 1125 -1055 1131
+rect -943 1125 -937 1131
+rect -890 1125 -884 1131
+rect 936 1125 942 1131
+rect 989 1125 995 1131
+rect -1546 1071 -1540 1077
+rect -1429 1071 -1423 1077
+rect -1120 1075 -1114 1081
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+rect -949 1075 -943 1081
+rect -884 1075 -878 1081
+rect -575 1071 -569 1077
+rect -458 1071 -452 1077
+rect 504 1071 510 1077
+rect 621 1071 627 1077
+rect 930 1075 936 1081
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+rect -1540 1018 -1534 1024
+rect -1435 1018 -1429 1024
+rect -1114 1016 -1108 1022
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+rect -943 1016 -937 1022
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+rect -569 1018 -563 1024
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+rect -240 958 -227 963
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+rect 621 954 627 960
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+rect -943 827 -937 833
+rect -890 827 -884 833
+rect 936 827 942 833
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+rect -1120 777 -1114 783
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+rect -949 777 -943 783
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+rect -1546 769 -1540 775
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+rect -575 769 -569 775
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+rect 504 769 510 775
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+rect -1114 710 -1108 716
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+rect -943 710 -937 716
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+rect -29 714 -28 726
+rect 510 717 516 723
+rect 615 717 621 723
+rect -15 700 -14 712
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+rect 989 710 995 716
+rect -1120 660 -1114 666
+rect -1055 660 -1049 666
+rect -949 660 -943 666
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+rect -1546 653 -1540 659
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+rect 621 653 627 659
+rect -1866 613 -1864 621
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+rect -1953 600 -1952 608
+rect -1872 600 -1871 608
+rect -110 602 -109 608
+rect -110 594 -108 602
+rect -29 600 -28 608
+rect -1537 537 -1531 543
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+rect -566 537 -560 543
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+rect 512 537 518 543
+rect 617 537 623 543
+rect -1111 527 -1105 533
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+rect -887 527 -881 533
+rect 938 527 944 533
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+rect -1052 477 -1046 483
+rect -946 477 -940 483
+rect -881 477 -875 483
+rect -572 473 -566 479
+rect -455 473 -449 479
+rect 506 473 512 479
+rect 623 473 629 479
+rect 932 477 938 483
+rect 997 477 1003 483
+rect -1537 420 -1531 426
+rect -1432 420 -1426 426
+rect -1111 418 -1105 424
+rect -1058 418 -1052 424
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+rect -887 418 -881 424
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+rect -1117 368 -1111 374
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+rect -1768 360 -1755 365
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+rect -1543 356 -1537 362
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+rect -251 360 -238 364
+rect -237 360 -224 365
+rect -251 357 -224 360
+rect 506 356 512 362
+rect 623 356 629 362
+rect -1537 235 -1531 241
+rect -1432 235 -1426 241
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+rect 512 235 518 241
+rect 617 235 623 241
+rect -1111 229 -1105 235
+rect -1058 229 -1052 235
+rect -940 229 -934 235
+rect -887 229 -881 235
+rect 938 229 944 235
+rect 991 229 997 235
+rect -1117 179 -1111 185
+rect -1052 179 -1046 185
+rect -946 179 -940 185
+rect -881 179 -875 185
+rect 932 179 938 185
+rect 997 179 1003 185
+rect -1543 171 -1537 177
+rect -1426 171 -1420 177
+rect -572 171 -566 177
+rect -455 171 -449 177
+rect 506 171 512 177
+rect 623 171 629 177
+rect -1537 119 -1531 125
+rect -1432 119 -1426 125
+rect -566 119 -560 125
+rect -461 119 -455 125
+rect -1111 112 -1105 118
+rect -1058 112 -1052 118
+rect -940 112 -934 118
+rect -887 112 -881 118
+rect -27 116 -25 128
+rect 512 119 518 125
+rect 617 119 623 125
+rect -27 68 -26 116
+rect -13 102 -11 114
+rect 938 112 944 118
+rect 991 112 997 118
+rect -13 82 -12 102
+rect -1117 62 -1111 68
+rect -1052 62 -1046 68
+rect -946 62 -940 68
+rect -881 62 -875 68
+rect 932 62 938 68
+rect 997 62 1003 68
+rect -1543 55 -1537 61
+rect -1426 55 -1420 61
+rect -572 55 -566 61
+rect -455 55 -449 61
+rect 506 55 512 61
+rect 623 55 629 61
+use sky130_hilas_WTA4Stage01 sky130_hilas_WTA4Stage01_1
+timestamp 1607392100
+transform 1 0 1106 0 1 636
+box -1121 -43 296 562
+use sky130_hilas_WTA4Stage01 sky130_hilas_WTA4Stage01_0
+timestamp 1607392100
+transform 1 0 1108 0 1 38
+box -1121 -43 296 562
+use sky130_hilas_swc4x2cell sky130_hilas_swc4x2cell_1
+timestamp 1607392100
+transform 1 0 -1001 0 1 597
+box -1004 -4 1008 601
+use sky130_hilas_swc4x2cell sky130_hilas_swc4x2cell_0
+timestamp 1607392100
+transform 1 0 -998 0 1 -1
+box -1004 -4 1008 601
+<< end >>
diff --git a/mag/sky130_hilas_WTAsinglestage01.mag b/mag/sky130_hilas_WTAsinglestage01.mag
new file mode 100644
index 0000000..bc2d29d
--- /dev/null
+++ b/mag/sky130_hilas_WTAsinglestage01.mag
@@ -0,0 +1,127 @@
+magic
+tech sky130A
+timestamp 1607090551
+<< nmos >>
+rect -18 -34 2 25
+rect 88 -34 108 25
+<< ndiff >>
+rect 116 25 146 33
+rect -47 21 -18 25
+rect -47 4 -41 21
+rect -24 4 -18 21
+rect -47 -13 -18 4
+rect -47 -30 -41 -13
+rect -24 -30 -18 -13
+rect -47 -34 -18 -30
+rect 2 21 32 25
+rect 2 4 9 21
+rect 26 4 32 21
+rect 2 -13 32 4
+rect 2 -30 9 -13
+rect 26 -30 32 -13
+rect 2 -34 32 -30
+rect 59 21 88 25
+rect 59 4 65 21
+rect 82 4 88 21
+rect 59 -13 88 4
+rect 59 -30 65 -13
+rect 82 -30 88 -13
+rect 59 -34 88 -30
+rect 108 21 146 25
+rect 108 4 122 21
+rect 139 4 146 21
+rect 108 -13 146 4
+rect 108 -30 122 -13
+rect 139 -30 146 -13
+rect 108 -34 146 -30
+rect 116 -42 146 -34
+<< ndiffc >>
+rect -41 4 -24 21
+rect -41 -30 -24 -13
+rect 9 4 26 21
+rect 9 -30 26 -13
+rect 65 4 82 21
+rect 65 -30 82 -13
+rect 122 4 139 21
+rect 122 -30 139 -13
+<< psubdiff >>
+rect 146 21 175 33
+rect 146 4 156 21
+rect 173 4 175 21
+rect 146 -13 175 4
+rect 146 -30 156 -13
+rect 173 -30 175 -13
+rect 146 -42 175 -30
+<< psubdiffcont >>
+rect 156 4 173 21
+rect 156 -30 173 -13
+<< poly >>
+rect 43 61 108 66
+rect 43 44 51 61
+rect 68 44 108 61
+rect 43 38 108 44
+rect -18 25 2 38
+rect 88 25 108 38
+rect -18 -43 2 -34
+rect -63 -53 2 -43
+rect 88 -47 108 -34
+rect -63 -70 -55 -53
+rect -38 -70 2 -53
+rect -63 -75 2 -70
+<< polycont >>
+rect 51 44 68 61
+rect -55 -70 -38 -53
+<< locali >>
+rect 11 61 32 63
+rect 9 44 13 61
+rect 30 44 51 61
+rect 68 44 76 61
+rect 9 21 34 44
+rect 122 21 173 29
+rect -50 4 -41 21
+rect -24 4 -16 21
+rect 1 4 9 21
+rect 26 4 34 21
+rect 56 4 65 21
+rect 82 4 90 21
+rect 139 4 156 21
+rect -50 -13 -16 4
+rect 9 -13 26 4
+rect 65 -13 82 4
+rect 122 -13 139 4
+rect 156 -13 173 4
+rect -50 -30 -41 -13
+rect -24 -30 -16 -13
+rect 1 -30 9 -13
+rect 26 -30 34 -13
+rect 56 -30 65 -13
+rect 82 -30 90 -13
+rect 139 -30 156 -13
+rect 65 -53 82 -30
+rect 122 -38 173 -30
+rect -64 -70 -55 -53
+rect -38 -70 82 -53
+<< viali >>
+rect 13 44 30 61
+rect 139 -13 156 4
+<< metal1 >>
+rect 10 61 33 67
+rect 10 44 13 61
+rect 30 44 33 61
+rect 10 -76 33 44
+rect 136 4 159 53
+rect 136 -13 139 4
+rect 156 -13 159 4
+rect 136 -76 159 -13
+<< metal2 >>
+rect -54 -2 175 14
+rect -108 -72 -96 -51
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 -84 0 1 -61
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 -69 0 1 7
+box -14 -15 20 18
+<< end >>
diff --git a/mag/sky130_hilas_all.mag b/mag/sky130_hilas_all.mag
new file mode 100644
index 0000000..6ada49c
--- /dev/null
+++ b/mag/sky130_hilas_all.mag
@@ -0,0 +1,147 @@
+magic
+tech sky130A
+timestamp 1606594671
+<< error_p >>
+rect -540 172 -533 173
+rect -601 -66 -516 -60
+rect -602 -94 -516 -66
+rect -573 -97 -572 -94
+rect -560 -97 -554 -94
+rect -573 -100 -551 -97
+rect -550 -100 -516 -94
+rect -498 -95 -495 -92
+rect -575 -103 -516 -100
+rect -575 -106 -566 -103
+rect -573 -122 -572 -106
+rect -569 -114 -566 -106
+rect -560 -106 -516 -103
+rect -560 -114 -551 -106
+rect -569 -117 -551 -114
+rect -560 -120 -551 -117
+rect -560 -122 -554 -120
+rect -550 -122 -516 -106
+rect -495 -96 -492 -95
+rect -495 -121 -494 -96
+rect -573 -123 -516 -122
+<< nwell >>
+rect -572 -43 -425 226
+rect -601 -67 -425 -43
+rect -602 -150 -425 -67
+rect -572 -441 -425 -150
+<< mvpmos >>
+rect -521 116 -491 166
+rect -521 -21 -491 30
+rect -521 -94 -491 -42
+rect -521 -175 -491 -123
+rect -521 -246 -491 -196
+rect -521 -381 -491 -331
+<< mvndiff >>
+rect -573 -123 -550 -94
+<< mvpdiff >>
+rect -521 189 -491 193
+rect -521 172 -515 189
+rect -498 172 -491 189
+rect -521 166 -491 172
+rect -521 110 -491 116
+rect -521 93 -515 110
+rect -497 93 -491 110
+rect -521 88 -491 93
+rect -521 53 -491 58
+rect -521 36 -515 53
+rect -497 36 -491 53
+rect -521 30 -491 36
+rect -521 -42 -491 -21
+rect -521 -100 -491 -94
+rect -521 -117 -515 -100
+rect -497 -117 -491 -100
+rect -521 -123 -491 -117
+rect -521 -196 -491 -175
+rect -521 -252 -491 -246
+rect -521 -269 -515 -252
+rect -497 -269 -491 -252
+rect -521 -273 -491 -269
+rect -521 -308 -491 -304
+rect -521 -325 -515 -308
+rect -497 -325 -491 -308
+rect -521 -331 -491 -325
+rect -521 -387 -491 -381
+rect -521 -404 -515 -387
+rect -497 -404 -491 -387
+rect -521 -408 -491 -404
+<< mvpdiffc >>
+rect -515 172 -498 189
+rect -515 93 -497 110
+rect -515 36 -497 53
+rect -515 -117 -497 -100
+rect -515 -269 -497 -252
+rect -515 -325 -497 -308
+rect -515 -404 -497 -387
+<< poly >>
+rect -555 116 -521 166
+rect -491 116 -478 166
+rect -555 30 -534 116
+rect -555 -21 -521 30
+rect -491 -21 -476 30
+rect -534 -94 -521 -42
+rect -491 -94 -465 -42
+rect -488 -123 -465 -94
+rect -534 -175 -521 -123
+rect -491 -175 -465 -123
+rect -550 -246 -521 -196
+rect -491 -246 -478 -196
+rect -550 -331 -534 -246
+rect -550 -381 -521 -331
+rect -491 -381 -478 -331
+rect -550 -382 -534 -381
+<< locali >>
+rect -522 172 -515 189
+rect -498 172 -490 189
+rect -523 93 -515 110
+rect -497 93 -489 110
+rect -523 36 -515 53
+rect -497 36 -489 53
+rect -554 -117 -540 -100
+rect -522 -117 -515 -100
+rect -497 -117 -489 -100
+rect -523 -269 -515 -252
+rect -497 -269 -489 -252
+rect -523 -325 -515 -308
+rect -497 -325 -489 -308
+rect -523 -404 -515 -387
+rect -497 -404 -489 -387
+<< viali >>
+rect -540 172 -522 189
+rect -569 -117 -554 -100
+rect -540 -117 -522 -100
+<< metal1 >>
+rect -536 196 -502 200
+rect -536 195 -532 196
+rect -546 189 -532 195
+rect -506 195 -502 196
+rect -546 172 -540 189
+rect -546 170 -532 172
+rect -506 170 -490 195
+rect -536 167 -502 170
+rect -546 -100 -520 -96
+rect -546 -117 -540 -100
+rect -522 -117 -520 -100
+rect -546 -121 -520 -117
+rect -495 -121 -492 -96
+<< via1 >>
+rect -532 189 -506 196
+rect -532 172 -522 189
+rect -522 172 -506 189
+rect -532 170 -506 172
+rect -520 -121 -495 -95
+<< metal2 >>
+rect -536 196 -502 200
+rect -572 170 -532 196
+rect -506 170 -453 196
+rect -536 167 -502 170
+rect -522 -94 -492 -93
+rect -522 -95 -491 -94
+rect -542 -121 -520 -95
+rect -495 -121 -489 -95
+rect -542 -122 -489 -121
+rect -522 -124 -492 -122
+<< end >>
diff --git a/mag/sky130_hilas_capacitorArray01.mag b/mag/sky130_hilas_capacitorArray01.mag
new file mode 100644
index 0000000..35d47ed
--- /dev/null
+++ b/mag/sky130_hilas_capacitorArray01.mag
@@ -0,0 +1,210 @@
+magic
+tech sky130A
+timestamp 1625405899
+<< error_s >>
+rect -872 485 -866 491
+rect -767 485 -761 491
+rect -1246 475 -1240 481
+rect -1193 475 -1187 481
+rect -1252 425 -1246 431
+rect -1187 425 -1181 431
+rect -878 421 -872 427
+rect -761 421 -755 427
+rect -1246 366 -1240 372
+rect -1193 366 -1187 372
+rect -872 368 -866 374
+rect -767 368 -761 374
+rect -1252 316 -1246 322
+rect -1187 316 -1181 322
+rect -878 304 -872 310
+rect -761 304 -755 310
+rect 2331 228 2333 256
+rect -872 183 -866 189
+rect -767 183 -761 189
+rect -1246 177 -1240 183
+rect -1193 177 -1187 183
+rect -1252 127 -1246 133
+rect -1187 127 -1181 133
+rect -878 119 -872 125
+rect -761 119 -755 125
+rect -872 67 -866 73
+rect -767 67 -761 73
+rect -1246 60 -1240 66
+rect -1193 60 -1187 66
+rect -1252 10 -1246 16
+rect -1187 10 -1181 16
+rect -878 3 -872 9
+rect -761 3 -755 9
+<< nwell >>
+rect -297 547 2238 548
+rect -296 540 2238 547
+rect -1303 480 -1292 498
+rect -1304 294 -1292 312
+rect -1302 -5 -1292 12
+rect -298 -51 2238 540
+rect -297 -56 2238 -51
+rect -104 -57 2238 -56
+<< metal1 >>
+rect -1268 534 -1228 548
+rect -1024 542 -1000 548
+rect -862 540 -825 548
+rect -631 541 -607 548
+rect -392 543 -373 548
+rect -348 543 -332 548
+rect -863 535 -825 540
+rect -864 -44 -863 -42
+rect -1268 -57 -1229 -45
+rect -1024 -57 -1000 -50
+rect -864 -56 -825 -44
+rect -864 -57 -863 -56
+rect -631 -57 -607 -50
+rect -429 -56 -413 -50
+rect -392 -56 -373 -50
+rect -348 -56 -332 -50
+<< metal2 >>
+rect -230 545 -179 548
+rect -230 543 -137 545
+rect -230 536 -174 543
+rect -416 517 -174 536
+rect -187 515 -174 517
+rect -146 515 -137 543
+rect -1303 480 -1292 498
+rect -406 480 2366 498
+rect -412 437 2366 455
+rect -406 337 2366 355
+rect 2265 312 2366 313
+rect -1304 294 -1292 312
+rect -410 294 2366 312
+rect 2297 256 2366 263
+rect 2297 228 2304 256
+rect 2333 228 2366 256
+rect 2297 222 2366 228
+rect -1302 179 -1292 196
+rect -427 179 2366 196
+rect -417 137 2366 154
+rect -419 39 2366 56
+rect -1302 -5 -1292 12
+rect -423 -5 2366 12
+<< via2 >>
+rect -174 515 -146 543
+rect 2304 228 2333 256
+<< metal3 >>
+rect -179 543 -141 546
+rect -179 517 -174 543
+rect -187 515 -174 517
+rect -146 517 -141 543
+rect -146 515 -133 517
+rect -187 392 -133 515
+rect 2219 256 2334 327
+rect 2219 228 2304 256
+rect 2333 228 2334 256
+rect -267 143 -249 173
+rect 2219 163 2334 228
+rect 2264 162 2334 163
+rect -158 22 -140 52
+<< metal4 >>
+rect -25 481 385 511
+rect -194 420 76 431
+rect -194 390 97 420
+rect 46 356 97 390
+rect 347 361 385 481
+rect 631 364 959 394
+rect -263 318 -127 348
+rect -157 262 -127 318
+rect 631 262 661 364
+rect 929 262 959 364
+rect -157 232 959 262
+rect 1199 362 2088 392
+rect 67 173 386 176
+rect 631 173 661 176
+rect -267 143 953 173
+rect 67 106 97 143
+rect 356 109 386 143
+rect 631 109 661 143
+rect 356 106 661 109
+rect 923 106 953 143
+rect 67 76 953 106
+rect 1199 110 1229 362
+rect 1482 359 1793 362
+rect 1482 110 1512 359
+rect 1763 110 1793 359
+rect 2058 110 2088 362
+rect 1199 80 2094 110
+rect 1763 79 2094 80
+rect -170 22 -119 52
+rect -149 -2 -119 22
+rect 2064 -2 2094 79
+rect -149 -32 2094 -2
+use sky130_hilas_cellAttempt01 sky130_hilas_cellAttempt01_1
+timestamp 1625402619
+transform 1 0 -1040 0 1 325
+box -264 -382 744 223
+use sky130_hilas_cellAttempt01 sky130_hilas_cellAttempt01_0
+timestamp 1625402619
+transform 1 0 -1040 0 1 325
+box -264 -382 744 223
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607949437
+transform 1 0 -428 0 1 524
+box -9 -10 23 22
+use sky130_hilas_m22m4 sky130_hilas_m22m4_1
+timestamp 1607701799
+transform 1 0 -302 0 1 348
+box -36 -36 43 39
+use sky130_hilas_m22m4 sky130_hilas_m22m4_2
+timestamp 1607701799
+transform 1 0 -306 0 1 139
+box -36 -36 43 39
+use sky130_hilas_m22m4 sky130_hilas_m22m4_3
+timestamp 1607701799
+transform 1 0 -197 0 1 52
+box -36 -36 43 39
+use sky130_hilas_m12m2 sky130_hilas_m12m2_1
+timestamp 1607949437
+transform 1 0 -428 0 1 524
+box -9 -10 23 22
+<< labels >>
+rlabel metal2 2354 222 2366 263 0 CAPTERM2
+port 1 nsew analog default
+rlabel metal2 -230 535 -179 548 0 CAPTERM1
+port 2 nsew analog default
+rlabel metal1 -392 543 -373 548 0 GATESELECT
+port 4 nsew
+rlabel metal1 -348 543 -332 548 0 VINJ
+port 3 nsew power default
+rlabel metal1 -862 535 -825 548 0 GATE
+port 6 nsew analog default
+rlabel metal1 -1268 534 -1228 548 0 VTUN
+port 5 nsew
+rlabel metal1 -1268 -57 -1229 -45 0 VTUN
+port 5 nsew
+rlabel metal1 -864 -56 -825 -44 0 GATE
+port 6 nsew
+rlabel metal1 -348 -56 -332 -50 0 VINJ
+rlabel metal1 -429 -56 -413 -50 0 CAPTERM1
+rlabel metal1 -392 -56 -373 -50 0 GATESELECT
+rlabel metal2 -1303 480 -1292 498 0 DRAIN1
+port 8 nsew
+rlabel metal2 -1304 294 -1292 312 0 DRAIN2
+port 7 nsew
+rlabel metal2 2356 -5 2366 12 0 DRAIN4
+port 10 nsew
+rlabel metal2 2356 480 2366 498 0 DRAIN1
+port 8 nsew
+rlabel metal2 2355 294 2366 313 0 DRAIN2
+port 7 nsew
+rlabel metal2 2355 179 2366 196 0 DRAIN3
+port 11 nsew
+rlabel metal2 -1302 179 -1292 196 0 DRAIN3
+port 11 nsew
+rlabel metal2 -1302 -5 -1292 12 0 DRAIN4
+port 10 nsew
+rlabel metal1 -1024 542 -1000 548 0 VGND
+port 12 nsew
+rlabel metal1 -631 541 -607 548 0 VGND
+port 12 nsew
+rlabel metal1 -1024 -57 -1000 -50 0 VGND
+port 12 nsew
+rlabel metal1 -631 -57 -607 -50 0 VGND
+port 12 nsew
+<< end >>
diff --git a/mag/sky130_hilas_capacitorSize01.mag b/mag/sky130_hilas_capacitorSize01.mag
new file mode 100644
index 0000000..1e089d3
--- /dev/null
+++ b/mag/sky130_hilas_capacitorSize01.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+timestamp 1608072649
+<< metal2 >>
+rect 1414 480 2456 498
+rect 1414 437 2456 455
+rect 1417 337 2456 355
+rect 2265 312 2456 313
+rect 1417 294 2456 312
+rect 1416 232 1443 260
+rect 2420 233 2456 261
+rect 1417 179 2456 196
+rect 1417 137 2456 154
+rect 1417 39 2456 56
+rect 1417 -5 2456 12
+<< metal3 >>
+rect 2237 207 2433 282
+<< metal4 >>
+rect 1530 272 1631 273
+rect 1459 222 1794 272
+rect 1459 221 1566 222
+rect 1730 110 1793 222
+rect 1730 80 1945 110
+rect 1763 79 1945 80
+use sky130_hilas_CapModule02 sky130_hilas_CapModule02_0
+timestamp 1607802006
+transform 1 0 2003 0 1 199
+box -443 -247 277 336
+use sky130_hilas_m22m4 sky130_hilas_m22m4_0
+timestamp 1607701799
+transform 1 0 1452 0 1 242
+box -36 -36 43 39
+use sky130_hilas_m22m4 sky130_hilas_m22m4_1
+timestamp 1607701799
+transform 1 0 2401 0 1 243
+box -36 -36 43 39
+<< labels >>
+rlabel metal2 1416 232 1423 260 0 CAPTERM01
+port 2 nsew analog default
+rlabel metal2 2444 233 2456 261 0 CAPTERM02
+port 1 nsew analog default
+<< end >>
diff --git a/mag/sky130_hilas_capacitorSize02.mag b/mag/sky130_hilas_capacitorSize02.mag
new file mode 100644
index 0000000..98cd56e
--- /dev/null
+++ b/mag/sky130_hilas_capacitorSize02.mag
@@ -0,0 +1,44 @@
+magic
+tech sky130A
+timestamp 1608072448
+<< metal2 >>
+rect 1414 480 2211 498
+rect 1414 437 2211 455
+rect 1417 337 2211 355
+rect 1417 294 2211 312
+rect 1416 232 1443 260
+rect 2180 234 2211 262
+rect 1417 179 2211 196
+rect 1417 137 2211 154
+rect 1417 39 2211 56
+rect 1417 -5 2211 12
+<< metal3 >>
+rect 1982 222 2180 283
+rect 1982 221 2178 222
+rect 2179 221 2180 222
+rect 1982 208 2180 221
+<< metal4 >>
+rect 1530 272 1631 273
+rect 1459 222 1794 272
+rect 1459 221 1566 222
+rect 1730 110 1793 222
+rect 1730 80 1945 110
+rect 1763 79 1945 80
+use sky130_hilas_m22m4 sky130_hilas_m22m4_1
+timestamp 1607701799
+transform 1 0 2164 0 1 244
+box -36 -36 43 39
+use sky130_hilas_CapModule03 sky130_hilas_CapModule03_0
+timestamp 1607813757
+transform 1 0 1952 0 1 199
+box -392 -247 31 336
+use sky130_hilas_m22m4 sky130_hilas_m22m4_0
+timestamp 1607701799
+transform 1 0 1452 0 1 242
+box -36 -36 43 39
+<< labels >>
+rlabel metal2 1416 232 1423 260 0 CAPTERM01
+port 2 nsew analog default
+rlabel metal2 2196 234 2211 262 0 CAPTERM02
+port 1 nsew analog default
+<< end >>
diff --git a/mag/sky130_hilas_capacitorSize03.mag b/mag/sky130_hilas_capacitorSize03.mag
new file mode 100644
index 0000000..8a19e26
--- /dev/null
+++ b/mag/sky130_hilas_capacitorSize03.mag
@@ -0,0 +1,48 @@
+magic
+tech sky130A
+timestamp 1608249223
+<< metal2 >>
+rect 1414 480 1992 498
+rect 1414 437 1992 455
+rect 1417 337 1992 355
+rect 1417 294 1992 312
+rect 1416 232 1443 260
+rect 1956 236 1993 264
+rect 1417 179 1992 196
+rect 1417 137 1992 154
+rect 1417 39 1992 56
+rect 1417 -5 1992 12
+<< metal3 >>
+rect 1559 285 1586 286
+rect 1559 210 1973 285
+<< metal4 >>
+rect 1672 273 1716 357
+rect 1530 272 1631 273
+rect 1671 272 1717 273
+rect 1459 222 1717 272
+rect 1459 221 1566 222
+rect 1671 156 1717 222
+rect 1671 106 1719 156
+rect 1716 76 1719 106
+use sky130_hilas_CapModule01 sky130_hilas_CapModule01_0
+timestamp 1607800460
+transform 1 0 2002 0 1 198
+box -443 -245 -159 41
+use sky130_hilas_CapModule01 sky130_hilas_CapModule01_1
+timestamp 1607800460
+transform 1 0 2002 0 1 499
+box -443 -245 -159 41
+use sky130_hilas_m22m4 sky130_hilas_m22m4_1
+timestamp 1607701799
+transform 1 0 1937 0 1 246
+box -36 -36 43 39
+use sky130_hilas_m22m4 sky130_hilas_m22m4_0
+timestamp 1607701799
+transform 1 0 1452 0 1 242
+box -36 -36 43 39
+<< labels >>
+rlabel metal2 1416 232 1423 260 0 CAPTERM01
+port 2 nsew analog default
+rlabel metal2 1985 236 1993 264 0 CAPTERM02
+port 1 nsew analog default
+<< end >>
diff --git a/mag/sky130_hilas_capacitorSize04.mag b/mag/sky130_hilas_capacitorSize04.mag
new file mode 100644
index 0000000..75ef863
--- /dev/null
+++ b/mag/sky130_hilas_capacitorSize04.mag
@@ -0,0 +1,56 @@
+magic
+tech sky130A
+timestamp 1608072649
+<< metal2 >>
+rect 1417 480 1992 498
+rect 1417 437 1992 455
+rect 1417 385 1444 413
+rect 1957 385 1992 413
+rect 1417 337 1992 355
+rect 1417 294 1992 312
+rect 1417 179 1992 196
+rect 1417 137 1992 154
+rect 1417 85 1445 113
+rect 1957 85 1993 113
+rect 1417 39 1992 56
+rect 1417 -5 1992 12
+<< metal3 >>
+rect 1801 359 1904 434
+rect 1800 60 1906 133
+<< metal4 >>
+rect 1441 365 1720 406
+rect 1472 64 1684 105
+use sky130_hilas_m22m4 sky130_hilas_m22m4_4
+timestamp 1607701799
+transform 1 0 1938 0 1 95
+box -36 -36 43 39
+use sky130_hilas_m22m4 sky130_hilas_m22m4_3
+timestamp 1607701799
+transform 1 0 1938 0 1 395
+box -36 -36 43 39
+use sky130_hilas_m22m4 sky130_hilas_m22m4_5
+timestamp 1607701799
+transform 1 0 1454 0 1 95
+box -36 -36 43 39
+use sky130_hilas_m22m4 sky130_hilas_m22m4_2
+timestamp 1607701799
+transform 1 0 1451 0 1 395
+box -36 -36 43 39
+use sky130_hilas_CapModule01a sky130_hilas_CapModule01a_0
+timestamp 1607818356
+transform 1 0 2002 0 1 198
+box -416 -216 -186 12
+use sky130_hilas_CapModule01a sky130_hilas_CapModule01a_1
+timestamp 1607818356
+transform 1 0 2002 0 1 499
+box -416 -216 -186 12
+<< labels >>
+rlabel metal2 1982 385 1992 413 0 CAP1TERM02
+port 1 nsew analog default
+rlabel metal2 1417 385 1424 413 0 CAP1TERM01
+port 4 nsew analog default
+rlabel metal2 1417 85 1423 113 0 CAP2TERM01
+port 3 nsew analog default
+rlabel metal2 1986 85 1993 113 0 CAP2TERM02
+port 2 nsew analog default
+<< end >>
diff --git a/mag/sky130_hilas_cellAttempt01.mag b/mag/sky130_hilas_cellAttempt01.mag
new file mode 100644
index 0000000..a360f6f
--- /dev/null
+++ b/mag/sky130_hilas_cellAttempt01.mag
@@ -0,0 +1,283 @@
+magic
+tech sky130A
+timestamp 1625402619
+<< error_s >>
+rect 168 160 174 166
+rect 273 160 279 166
+rect -206 150 -200 156
+rect -153 150 -147 156
+rect -212 100 -206 106
+rect -147 100 -141 106
+rect 162 96 168 102
+rect 279 96 285 102
+rect -206 41 -200 47
+rect -153 41 -147 47
+rect 168 43 174 49
+rect 273 43 279 49
+rect -212 -9 -206 -3
+rect -147 -9 -141 -3
+rect 162 -21 168 -15
+rect 279 -21 285 -15
+rect 168 -142 174 -136
+rect 273 -142 279 -136
+rect -206 -148 -200 -142
+rect -153 -148 -147 -142
+rect -212 -198 -206 -192
+rect -147 -198 -141 -192
+rect 162 -206 168 -200
+rect 279 -206 285 -200
+rect 168 -258 174 -252
+rect 273 -258 279 -252
+rect -206 -265 -200 -259
+rect -153 -265 -147 -259
+rect -212 -315 -206 -309
+rect -147 -315 -141 -309
+rect 162 -322 168 -316
+rect 279 -322 285 -316
+<< nwell >>
+rect 112 222 335 223
+rect -263 112 -256 130
+rect 632 -72 667 -71
+rect 632 -88 649 -72
+rect 666 -88 667 -72
+rect 177 -381 215 -373
+rect 112 -382 335 -381
+<< psubdiff >>
+rect 15 82 41 105
+rect 15 65 19 82
+rect 36 65 41 82
+rect 15 39 41 65
+rect 407 81 434 107
+rect 407 64 413 81
+rect 430 64 434 81
+rect 407 41 434 64
+rect 16 -30 41 -3
+rect 16 -47 20 -30
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+rect 16 -64 41 -47
+rect 16 -81 20 -64
+rect 37 -81 41 -64
+rect 16 -98 41 -81
+rect 16 -115 20 -98
+rect 37 -115 41 -98
+rect 16 -143 41 -115
+rect 409 -44 434 -17
+rect 409 -61 413 -44
+rect 430 -61 434 -44
+rect 409 -78 434 -61
+rect 409 -95 413 -78
+rect 430 -95 434 -78
+rect 409 -112 434 -95
+rect 409 -129 413 -112
+rect 430 -129 434 -112
+rect 409 -142 434 -129
+<< psubdiffcont >>
+rect 19 65 36 82
+rect 413 64 430 81
+rect 20 -47 37 -30
+rect 20 -81 37 -64
+rect 20 -115 37 -98
+rect 413 -61 430 -44
+rect 413 -95 430 -78
+rect 413 -129 430 -112
+<< poly >>
+rect 319 147 489 151
+rect -107 114 130 138
+rect 319 135 488 147
+rect -107 5 128 29
+rect 319 -9 488 8
+rect 649 -72 667 -71
+rect 665 -88 667 -72
+rect -107 -175 130 -151
+rect 320 -167 488 -150
+rect -105 -295 132 -271
+rect 320 -309 488 -292
+<< polycont >>
+rect 632 -88 649 -71
+<< locali >>
+rect 20 -30 37 -22
+rect 20 -123 37 -115
+rect 413 -44 430 -36
+rect 623 -88 632 -71
+rect 413 -137 430 -129
+<< viali >>
+rect 19 82 36 99
+rect 19 48 36 65
+rect 413 81 430 98
+rect 413 47 430 64
+rect 20 -64 37 -47
+rect 20 -98 37 -81
+rect 413 -78 430 -61
+rect 649 -88 667 -71
+rect 413 -112 430 -95
+<< metal1 >>
+rect -228 -382 -188 223
+rect 16 105 40 223
+rect 177 213 215 223
+rect 409 107 433 223
+rect 611 219 627 223
+rect 648 218 667 223
+rect 692 218 708 223
+rect 15 99 41 105
+rect 15 82 19 99
+rect 36 82 41 99
+rect 15 65 41 82
+rect 15 48 19 65
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+rect 15 39 41 48
+rect 407 98 434 107
+rect 407 81 413 98
+rect 430 81 434 98
+rect 407 64 434 81
+rect 407 47 413 64
+rect 430 47 434 64
+rect 407 41 434 47
+rect 16 -47 40 39
+rect 16 -64 20 -47
+rect 37 -64 40 -47
+rect 16 -81 40 -64
+rect 16 -98 20 -81
+rect 37 -98 40 -81
+rect 16 -222 40 -98
+rect 409 -61 433 41
+rect 409 -78 413 -61
+rect 430 -78 433 -61
+rect 654 -68 667 -66
+rect 409 -95 433 -78
+rect 646 -71 670 -68
+rect 646 -88 649 -71
+rect 667 -88 670 -71
+rect 646 -91 670 -88
+rect 656 -95 667 -91
+rect 409 -112 413 -95
+rect 430 -112 433 -95
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+rect 408 -221 434 -218
+rect 15 -225 41 -222
+rect 408 -250 434 -247
+rect 15 -254 41 -251
+rect 16 -382 40 -254
+rect 177 -382 215 -373
+rect 409 -382 433 -250
+<< via1 >>
+rect 15 -251 41 -225
+rect 408 -247 434 -221
+<< metal2 >>
+rect -263 166 497 173
+rect -263 155 500 166
+rect -263 112 710 130
+rect -264 24 497 30
+rect -264 12 500 24
+rect -264 -31 500 -13
+rect -262 -146 500 -129
+rect -262 -188 500 -171
+rect 405 -221 437 -218
+rect 12 -251 15 -225
+rect 41 -226 44 -225
+rect 405 -226 408 -221
+rect 41 -244 408 -226
+rect 41 -251 44 -244
+rect 405 -247 408 -244
+rect 434 -247 437 -221
+rect 405 -250 437 -247
+rect -262 -286 500 -269
+rect -184 -295 -30 -286
+rect -262 -330 500 -313
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_0
+timestamp 1608066871
+transform 1 0 1188 0 1 135
+box -1451 -400 -1278 -210
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_1
+timestamp 1608066871
+transform 1 0 1188 0 1 18
+box -1451 -400 -1278 -210
+use sky130_hilas_FGVaractorCapacitor sky130_hilas_FGVaractorCapacitor_0
+timestamp 1606741561
+transform 1 0 1069 0 1 14
+box -957 -395 -734 -209
+use sky130_hilas_FGVaractorCapacitor sky130_hilas_FGVaractorCapacitor_1
+timestamp 1606741561
+transform 1 0 1069 0 1 130
+box -957 -395 -734 -209
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_1
+timestamp 1607386385
+transform 1 0 777 0 1 -428
+box -289 47 -33 232
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_2
+timestamp 1607386385
+transform 1 0 777 0 -1 -31
+box -289 47 -33 232
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_2
+timestamp 1608066871
+transform 1 0 1188 0 1 324
+box -1451 -400 -1278 -210
+use sky130_hilas_wellContact sky130_hilas_wellContact_1
+timestamp 1606753443
+transform 1 0 1185 0 1 293
+box -1449 -441 -1275 -255
+use sky130_hilas_FGVaractorCapacitor sky130_hilas_FGVaractorCapacitor_2
+timestamp 1606741561
+transform 1 0 1069 0 1 315
+box -957 -395 -734 -209
+use sky130_hilas_wellContact sky130_hilas_wellContact_0
+timestamp 1606753443
+transform 1 0 1588 0 1 286
+box -1449 -441 -1275 -255
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_0
+timestamp 1607386385
+transform 1 0 777 0 1 -128
+box -289 47 -33 232
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_3
+timestamp 1608066871
+transform 1 0 1188 0 1 433
+box -1451 -400 -1278 -210
+use sky130_hilas_FGVaractorCapacitor sky130_hilas_FGVaractorCapacitor_3
+timestamp 1606741561
+transform 1 0 1069 0 1 432
+box -957 -395 -734 -209
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_3
+timestamp 1607386385
+transform 1 0 777 0 -1 270
+box -289 47 -33 232
+<< labels >>
+rlabel metal1 -228 211 -188 223 0 VTUN
+port 1 nsew
+rlabel metal1 692 218 708 223 0 VINJ
+port 2 nsew
+rlabel metal1 648 218 667 223 0 COLSEL1
+port 3 nsew
+rlabel metal1 611 219 627 223 0 COL1
+port 4 nsew
+rlabel metal1 177 213 215 223 0 GATE1
+port 5 nsew
+rlabel poly 383 136 394 149 0 FG1
+rlabel poly 372 -9 389 6 0 FG2
+rlabel poly 379 -166 396 -151 0 FG3
+rlabel poly 389 -307 406 -292 0 FG4
+rlabel metal2 -263 155 -256 173 0 DRAIN1
+port 6 nsew
+rlabel metal2 -264 12 -257 30 0 ROW2
+port 9 nsew
+rlabel metal2 -264 -31 -257 -13 0 DRAIN2
+port 8 nsew
+rlabel metal2 -262 -146 -256 -129 0 DRAIN3
+port 10 nsew
+rlabel metal2 -262 -188 -256 -171 0 ROW3
+port 7 nsew
+rlabel metal2 -262 -286 -256 -269 0 ROW4
+port 11 nsew
+rlabel metal2 -262 -330 -256 -313 0 DRAIN4
+port 12 nsew
+rlabel metal2 -263 112 -256 130 0 ROW1
+port 13 nsew
+rlabel metal1 16 218 40 223 0 VGND
+port 14 nsew
+rlabel metal1 409 218 433 223 0 VGND
+port 14 nsew
+rlabel metal1 409 -382 433 -376 0 VGND
+port 14 nsew
+rlabel metal1 16 -382 40 -376 0 VGND
+port 14 nsew
+rlabel metal1 177 -382 215 -373 0 GATE1
+port 5 nsew
+<< end >>
diff --git a/mag/sky130_hilas_decoup_cap_00.mag b/mag/sky130_hilas_decoup_cap_00.mag
new file mode 100644
index 0000000..a47eb3c
--- /dev/null
+++ b/mag/sky130_hilas_decoup_cap_00.mag
@@ -0,0 +1,172 @@
+magic
+tech sky130A
+timestamp 1623107852
+<< nwell >>
+rect 82 43 390 189
+<< nmos >>
+rect 130 -55 341 5
+<< pmos >>
+rect 130 86 341 147
+<< ndiff >>
+rect 101 1 130 5
+rect 101 -16 107 1
+rect 124 -16 130 1
+rect 101 -33 130 -16
+rect 101 -50 107 -33
+rect 124 -50 130 -33
+rect 101 -55 130 -50
+rect 341 1 370 5
+rect 341 -16 347 1
+rect 364 -16 370 1
+rect 341 -33 370 -16
+rect 341 -50 347 -33
+rect 364 -50 370 -33
+rect 341 -55 370 -50
+<< pdiff >>
+rect 101 141 130 147
+rect 101 124 107 141
+rect 124 124 130 141
+rect 101 107 130 124
+rect 101 90 107 107
+rect 124 90 130 107
+rect 101 86 130 90
+rect 341 142 371 147
+rect 341 125 347 142
+rect 365 125 371 142
+rect 341 108 371 125
+rect 341 90 347 108
+rect 365 90 371 108
+rect 341 86 371 90
+<< ndiffc >>
+rect 107 -16 124 1
+rect 107 -50 124 -33
+rect 347 -16 364 1
+rect 347 -50 364 -33
+<< pdiffc >>
+rect 107 124 124 141
+rect 107 90 124 107
+rect 347 125 365 142
+rect 347 90 365 108
+<< poly >>
+rect 130 147 341 160
+rect 130 68 341 86
+rect 130 67 231 68
+rect 163 40 164 67
+rect 197 40 198 67
+rect 304 20 305 46
+rect 338 20 339 46
+rect 271 19 341 20
+rect 130 5 341 19
+rect 130 -68 341 -55
+<< locali >>
+rect 99 183 373 189
+rect 99 182 158 183
+rect 166 182 265 183
+rect 275 182 373 183
+rect 99 142 373 182
+rect 99 141 347 142
+rect 99 124 107 141
+rect 124 125 347 141
+rect 365 125 373 142
+rect 124 124 373 125
+rect 99 108 373 124
+rect 99 107 347 108
+rect 99 90 107 107
+rect 124 90 347 107
+rect 365 90 373 108
+rect 99 86 373 90
+rect 99 1 231 67
+rect 271 24 373 86
+rect 99 -16 107 1
+rect 124 -16 347 1
+rect 364 -16 373 1
+rect 99 -33 373 -16
+rect 99 -50 107 -33
+rect 124 -50 347 -33
+rect 364 -50 373 -33
+rect 99 -88 373 -50
+<< metal1 >>
+rect 99 141 373 189
+rect 99 -112 373 -50
+rect 99 -113 372 -112
+use sky130_hilas_li2m1 sky130_hilas_li2m1_1
+timestamp 1607179295
+transform 1 0 174 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 138 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_3
+timestamp 1607179295
+transform 1 0 210 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_2
+timestamp 1607179295
+transform 1 0 282 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_5
+timestamp 1607179295
+transform 1 0 246 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_7
+timestamp 1607179295
+transform 1 0 354 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_4
+timestamp 1607179295
+transform 1 0 318 0 1 -83
+box -10 -8 13 21
+use sky130_hilas_poly2li sky130_hilas_poly2li_4
+timestamp 1607178257
+transform 0 1 285 -1 0 37
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_3
+timestamp 1607178257
+transform 0 1 353 -1 0 37
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_0
+timestamp 1607178257
+transform 0 1 319 -1 0 37
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_1
+timestamp 1607178257
+transform 0 1 144 -1 0 58
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_2
+timestamp 1607178257
+transform 0 1 178 -1 0 58
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_5
+timestamp 1607178257
+transform 0 1 212 -1 0 58
+box -9 -14 18 19
+use sky130_hilas_li2m1 sky130_hilas_li2m1_15
+timestamp 1607179295
+transform 1 0 347 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_14
+timestamp 1607179295
+transform 1 0 303 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_13
+timestamp 1607179295
+transform 1 0 267 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_12
+timestamp 1607179295
+transform 1 0 231 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_11
+timestamp 1607179295
+transform 1 0 195 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_10
+timestamp 1607179295
+transform 1 0 159 0 1 165
+box -10 -8 13 21
+use sky130_hilas_li2m1 sky130_hilas_li2m1_9
+timestamp 1607179295
+transform 1 0 123 0 1 165
+box -10 -8 13 21
+<< end >>
diff --git a/mag/sky130_hilas_decoup_cap_01.mag b/mag/sky130_hilas_decoup_cap_01.mag
new file mode 100644
index 0000000..8ef3dbf
--- /dev/null
+++ b/mag/sky130_hilas_decoup_cap_01.mag
@@ -0,0 +1,270 @@
+magic
+tech sky130A
+timestamp 1625360156
+<< nwell >>
+rect 663 213 744 505
+<< psubdiff >>
+rect 670 619 714 643
+rect 670 602 683 619
+rect 700 602 714 619
+rect 670 585 714 602
+rect 670 568 683 585
+rect 700 568 714 585
+rect 670 551 714 568
+rect 670 534 683 551
+rect 700 534 714 551
+rect 670 525 714 534
+rect 671 161 714 187
+rect 671 144 684 161
+rect 701 144 714 161
+rect 671 127 714 144
+rect 671 110 684 127
+rect 701 110 714 127
+rect 671 93 714 110
+rect 671 76 684 93
+rect 701 76 714 93
+rect 671 71 714 76
+<< nsubdiff >>
+rect 671 462 713 474
+rect 671 444 682 462
+rect 700 444 713 462
+rect 671 425 713 444
+rect 671 407 682 425
+rect 700 407 713 425
+rect 671 389 713 407
+rect 671 371 682 389
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+rect 671 318 713 335
+rect 671 300 683 318
+rect 701 300 713 318
+rect 671 282 713 300
+rect 671 264 683 282
+rect 701 264 713 282
+rect 671 255 713 264
+<< psubdiffcont >>
+rect 683 602 700 619
+rect 683 568 700 585
+rect 683 534 700 551
+rect 684 144 701 161
+rect 684 110 701 127
+rect 684 76 701 93
+<< nsubdiffcont >>
+rect 682 444 700 462
+rect 682 407 700 425
+rect 682 371 700 389
+rect 682 335 700 353
+rect 683 300 701 318
+rect 683 264 701 282
+<< locali >>
+rect 646 619 708 636
+rect 646 602 683 619
+rect 700 602 708 619
+rect 646 585 708 602
+rect 646 568 683 585
+rect 700 568 708 585
+rect 646 551 708 568
+rect 646 547 683 551
+rect 672 534 683 547
+rect 700 534 708 551
+rect 672 532 708 534
+rect 644 462 702 470
+rect 644 444 682 462
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+rect 644 431 702 444
+rect 644 425 707 431
+rect 644 407 682 425
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+rect 644 389 707 407
+rect 644 385 682 389
+rect 644 368 647 385
+rect 664 368 681 385
+rect 700 371 707 389
+rect 698 368 707 371
+rect 644 353 707 368
+rect 644 350 682 353
+rect 644 333 647 350
+rect 664 333 681 350
+rect 700 335 707 353
+rect 698 333 707 335
+rect 644 318 707 333
+rect 644 300 683 318
+rect 701 300 707 318
+rect 644 293 707 300
+rect 644 282 702 293
+rect 644 264 683 282
+rect 701 264 702 282
+rect 644 256 702 264
+rect 646 161 701 171
+rect 646 144 684 161
+rect 646 127 701 144
+rect 646 110 684 127
+rect 646 93 701 110
+rect 646 82 684 93
+rect 684 68 701 76
+<< viali >>
+rect 647 368 664 385
+rect 681 371 682 385
+rect 682 371 698 385
+rect 681 368 698 371
+rect 647 333 664 350
+rect 681 335 682 350
+rect 682 335 698 350
+rect 681 333 698 335
+<< metal1 >>
+rect 355 598 376 661
+rect 355 582 603 598
+rect 637 607 744 661
+rect 637 598 656 607
+rect 629 582 656 598
+rect 355 581 656 582
+rect 682 581 744 607
+rect 355 567 744 581
+rect 355 566 656 567
+rect 355 540 601 566
+rect 627 541 656 566
+rect 682 541 744 567
+rect 627 540 744 541
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+rect 355 476 744 499
+rect 355 449 392 476
+rect 419 449 447 476
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+rect 355 419 744 449
+rect 355 418 447 419
+rect 355 391 391 418
+rect 418 392 447 418
+rect 474 392 744 419
+rect 418 391 744 392
+rect 355 385 744 391
+rect 355 368 647 385
+rect 664 368 681 385
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+rect 355 350 744 368
+rect 355 335 647 350
+rect 355 334 447 335
+rect 355 315 392 334
+rect 355 314 372 315
+rect 355 307 392 314
+rect 419 315 447 334
+rect 419 308 447 314
+rect 474 333 647 335
+rect 664 333 681 350
+rect 698 333 744 350
+rect 474 315 744 333
+rect 607 314 744 315
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+rect 419 307 744 308
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+rect 355 257 392 284
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+rect 355 255 445 257
+rect 472 255 744 282
+rect 355 220 744 255
+rect 355 157 744 184
+rect 355 131 617 157
+rect 643 131 665 157
+rect 691 131 744 157
+rect 355 116 744 131
+rect 355 90 615 116
+rect 641 90 664 116
+rect 690 90 744 116
+rect 355 60 744 90
+rect 355 57 372 60
+rect 646 58 744 60
+rect 645 57 744 58
+<< via1 >>
+rect 603 582 629 608
+rect 656 581 682 607
+rect 601 540 627 566
+rect 656 541 682 567
+rect 392 449 419 476
+rect 447 449 474 476
+rect 391 391 418 418
+rect 447 392 474 419
+rect 392 307 419 334
+rect 447 308 474 335
+rect 392 257 419 284
+rect 445 255 472 282
+rect 617 131 643 157
+rect 665 131 691 157
+rect 615 90 641 116
+rect 664 90 690 116
+<< metal2 >>
+rect 377 476 507 661
+rect 377 449 392 476
+rect 419 449 447 476
+rect 474 449 507 476
+rect 377 419 507 449
+rect 377 418 447 419
+rect 377 391 391 418
+rect 418 392 447 418
+rect 474 392 507 419
+rect 418 391 507 392
+rect 377 335 507 391
+rect 377 334 447 335
+rect 377 307 392 334
+rect 419 308 447 334
+rect 474 308 507 335
+rect 419 307 507 308
+rect 377 284 507 307
+rect 377 257 392 284
+rect 419 282 507 284
+rect 419 257 445 282
+rect 377 255 445 257
+rect 472 255 507 282
+rect 377 57 507 255
+rect 585 608 715 661
+rect 585 582 603 608
+rect 629 607 715 608
+rect 629 582 656 607
+rect 585 581 656 582
+rect 682 581 715 607
+rect 585 567 715 581
+rect 585 566 656 567
+rect 585 540 601 566
+rect 627 541 656 566
+rect 682 541 715 567
+rect 627 540 715 541
+rect 585 157 715 540
+rect 585 131 617 157
+rect 643 131 665 157
+rect 691 131 715 157
+rect 585 116 715 131
+rect 585 90 615 116
+rect 641 90 664 116
+rect 690 90 715 116
+rect 585 57 715 90
+use sky130_hilas_decoup_cap_00 CapDeco_1
+timestamp 1623107852
+transform 1 0 273 0 1 170
+box 82 -113 390 189
+use sky130_hilas_decoup_cap_00 CapDeco_0
+timestamp 1623107852
+transform 1 0 273 0 -1 548
+box 82 -113 390 189
+<< labels >>
+rlabel metal1 355 311 372 407 0 VPWR
+port 1 nsew
+rlabel metal1 727 313 744 407 0 VPWR
+port 1 nsew
+rlabel metal1 734 598 744 661 0 VGND
+port 1 nsew
+rlabel metal1 355 598 363 661 0 VGND
+port 1 nsew
+rlabel metal1 355 57 364 120 0 VGND
+port 1 nsew
+rlabel metal1 729 57 744 120 0 VGND
+port 1 nsew
+rlabel metal2 377 651 507 661 0 VPWR
+port 1 nsew
+rlabel metal2 585 653 715 661 0 VGND
+port 2 nsew
+rlabel metal2 377 57 507 69 0 VPWR
+port 1 nsew
+rlabel metal2 585 57 715 69 0 VGND
+port 2 nsew
+<< end >>
diff --git a/mag/sky130_hilas_drainSelect01.mag b/mag/sky130_hilas_drainSelect01.mag
new file mode 100644
index 0000000..0bc24d2
--- /dev/null
+++ b/mag/sky130_hilas_drainSelect01.mag
@@ -0,0 +1,68 @@
+magic
+tech sky130A
+timestamp 1625970648
+<< metal1 >>
+rect 1108 603 1133 610
+rect 1407 603 1430 610
+rect 1542 605 1561 610
+rect 1407 5 1430 13
+rect 1542 5 1561 12
+<< metal2 >>
+rect 1055 559 1180 560
+rect 1055 543 1249 559
+rect 1055 542 1180 543
+rect 1614 501 1622 524
+rect 1611 384 1622 407
+rect 1055 372 1174 374
+rect 1055 356 1246 372
+rect 1055 258 1107 259
+rect 1055 257 1177 258
+rect 1055 241 1250 257
+rect 1614 208 1622 231
+rect 1613 91 1622 114
+rect 1055 74 1107 75
+rect 1055 57 1253 74
+use sky130_hilas_TgateVinj01 sky130_hilas_TgateVinj01_2
+timestamp 1625970418
+transform 1 0 1282 0 1 45
+box -232 -40 336 119
+use sky130_hilas_TgateVinj01 sky130_hilas_TgateVinj01_1
+timestamp 1625970418
+transform 1 0 1282 0 -1 570
+box -232 -40 336 119
+use sky130_hilas_TgateVinj01 sky130_hilas_TgateVinj01_3
+timestamp 1625970418
+transform 1 0 1282 0 -1 277
+box -232 -40 336 119
+use sky130_hilas_TgateVinj01 sky130_hilas_TgateVinj01_0
+timestamp 1625970418
+transform 1 0 1282 0 1 338
+box -232 -40 336 119
+<< labels >>
+rlabel metal2 1107 542 1112 560 0 DRAIN1
+port 4 nsew analog default
+rlabel metal2 1107 356 1112 374 0 DRAIN2
+port 3 nsew analog default
+rlabel metal2 1107 241 1112 258 0 DRAIN3
+port 2 nsew
+rlabel metal2 1107 57 1112 74 0 DRAIN4
+port 1 nsew
+rlabel metal1 1108 603 1133 610 0 VINJ
+port 9 nsew power default
+rlabel metal1 1407 603 1430 610 0 DRAIN_MUX
+port 10 nsew analog default
+rlabel metal1 1407 5 1430 13 0 DRAIN_MUX
+port 10 nsew analog default
+rlabel metal1 1542 5 1561 12 0 VGND
+port 11 nsew ground default
+rlabel metal1 1542 605 1561 610 0 VGND
+port 11 nsew ground default
+rlabel metal2 1613 91 1618 114 0 SELECT4
+port 12 nsew
+rlabel metal2 1614 208 1622 231 0 SELECT3
+port 13 nsew
+rlabel metal2 1611 384 1622 407 0 SELECT2
+port 14 nsew
+rlabel metal2 1614 501 1622 524 0 SELECT1
+port 15 nsew
+<< end >>
diff --git a/mag/sky130_hilas_horizPcell01.mag b/mag/sky130_hilas_horizPcell01.mag
new file mode 100644
index 0000000..08c7d40
--- /dev/null
+++ b/mag/sky130_hilas_horizPcell01.mag
@@ -0,0 +1,106 @@
+magic
+tech sky130A
+timestamp 1607386385
+<< nwell >>
+rect -289 48 -33 232
+rect -289 47 -34 48
+<< mvpmos >>
+rect -222 143 -172 173
+rect -222 81 -172 112
+rect -150 81 -100 112
+<< mvpdiff >>
+rect -251 167 -222 173
+rect -251 150 -247 167
+rect -229 150 -222 167
+rect -251 143 -222 150
+rect -172 166 -141 173
+rect -172 149 -165 166
+rect -146 149 -141 166
+rect -172 143 -141 149
+rect -254 105 -222 112
+rect -254 88 -247 105
+rect -229 88 -222 105
+rect -254 81 -222 88
+rect -172 81 -150 112
+rect -100 105 -66 112
+rect -100 88 -93 105
+rect -73 88 -66 105
+rect -100 81 -66 88
+<< mvpdiffc >>
+rect -247 150 -229 167
+rect -165 149 -146 166
+rect -247 88 -229 105
+rect -93 88 -73 105
+<< mvnsubdiff >>
+rect -100 169 -66 183
+rect -100 151 -93 169
+rect -73 151 -66 169
+rect -100 139 -66 151
+<< mvnsubdiffcont >>
+rect -93 151 -73 169
+<< poly >>
+rect -222 173 -172 188
+rect -137 158 -117 199
+rect -222 136 -172 143
+rect -289 119 -172 136
+rect -137 127 -116 158
+rect -222 112 -172 119
+rect -150 112 -100 127
+rect -222 66 -172 81
+rect -150 47 -100 81
+<< locali >>
+rect -255 150 -247 167
+rect -229 150 -221 167
+rect -166 166 -146 174
+rect -166 149 -165 166
+rect -166 138 -146 149
+rect -166 121 -165 138
+rect -148 121 -146 138
+rect -166 117 -146 121
+rect -94 169 -72 177
+rect -94 151 -93 169
+rect -73 151 -72 169
+rect -94 135 -72 151
+rect -94 118 -92 135
+rect -75 118 -72 135
+rect -93 115 -72 118
+rect -93 105 -73 115
+rect -255 88 -247 105
+rect -229 88 -221 105
+rect -93 80 -73 88
+<< viali >>
+rect -165 121 -148 138
+rect -92 118 -75 135
+<< metal1 >>
+rect -166 163 -150 232
+rect -166 141 -146 163
+rect -126 158 -110 232
+rect -85 181 -69 232
+rect -85 172 -68 181
+rect -127 146 -110 158
+rect -168 138 -145 141
+rect -168 121 -165 138
+rect -148 121 -145 138
+rect -168 117 -145 121
+rect -166 115 -146 117
+rect -166 47 -150 115
+rect -129 47 -110 146
+rect -96 167 -68 172
+rect -96 135 -69 167
+rect -96 118 -92 135
+rect -75 118 -69 135
+rect -96 112 -69 118
+rect -85 47 -69 112
+<< metal2 >>
+rect -289 140 -280 158
+rect -250 140 -33 158
+rect -251 97 -33 115
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 -266 0 -1 156
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 -266 0 -1 101
+box -14 -15 20 18
+<< end >>
diff --git a/mag/sky130_hilas_horizTransCell01.mag b/mag/sky130_hilas_horizTransCell01.mag
new file mode 100644
index 0000000..73b5624
--- /dev/null
+++ b/mag/sky130_hilas_horizTransCell01.mag
@@ -0,0 +1,222 @@
+magic
+tech sky130A
+timestamp 1625488390
+<< nwell >>
+rect -364 48 -33 359
+<< mvnmos >>
+rect -463 248 -423 298
+rect -463 169 -423 219
+<< mvpmos >>
+rect -327 248 -288 298
+rect -327 169 -288 219
+rect -224 142 -173 326
+rect -222 81 -172 112
+rect -150 81 -100 112
+<< mvndiff >>
+rect -463 321 -423 326
+rect -463 304 -452 321
+rect -434 304 -423 321
+rect -463 298 -423 304
+rect -463 242 -423 248
+rect -463 225 -453 242
+rect -434 225 -423 242
+rect -463 219 -423 225
+rect -463 163 -423 169
+rect -463 146 -452 163
+rect -434 146 -423 163
+rect -463 142 -423 146
+<< mvpdiff >>
+rect -327 321 -288 326
+rect -327 304 -316 321
+rect -299 304 -288 321
+rect -327 298 -288 304
+rect -256 305 -224 326
+rect -256 288 -249 305
+rect -232 288 -224 305
+rect -256 271 -224 288
+rect -256 254 -249 271
+rect -232 254 -224 271
+rect -327 242 -288 248
+rect -327 225 -316 242
+rect -299 225 -288 242
+rect -327 219 -288 225
+rect -256 237 -224 254
+rect -256 220 -249 237
+rect -232 220 -224 237
+rect -256 203 -224 220
+rect -256 186 -249 203
+rect -232 186 -224 203
+rect -256 169 -224 186
+rect -327 163 -288 169
+rect -327 146 -316 163
+rect -299 146 -288 163
+rect -327 142 -288 146
+rect -256 152 -249 169
+rect -232 152 -224 169
+rect -256 142 -224 152
+rect -173 304 -145 326
+rect -173 287 -166 304
+rect -149 287 -145 304
+rect -173 270 -145 287
+rect -173 253 -166 270
+rect -149 253 -145 270
+rect -173 236 -145 253
+rect -173 219 -166 236
+rect -149 219 -145 236
+rect -173 202 -145 219
+rect -173 185 -166 202
+rect -149 185 -145 202
+rect -173 168 -145 185
+rect -173 151 -166 168
+rect -149 151 -145 168
+rect -173 142 -145 151
+rect -256 105 -222 112
+rect -256 88 -247 105
+rect -229 88 -222 105
+rect -256 81 -222 88
+rect -172 81 -150 112
+rect -100 105 -66 112
+rect -100 88 -93 105
+rect -73 88 -66 105
+rect -100 81 -66 88
+<< mvndiffc >>
+rect -452 304 -434 321
+rect -453 225 -434 242
+rect -452 146 -434 163
+<< mvpdiffc >>
+rect -316 304 -299 321
+rect -249 288 -232 305
+rect -249 254 -232 271
+rect -316 225 -299 242
+rect -249 220 -232 237
+rect -249 186 -232 203
+rect -316 146 -299 163
+rect -249 152 -232 169
+rect -166 287 -149 304
+rect -166 253 -149 270
+rect -166 219 -149 236
+rect -166 185 -149 202
+rect -166 151 -149 168
+rect -247 88 -229 105
+rect -93 88 -73 105
+<< mvnsubdiff >>
+rect -100 169 -66 183
+rect -100 151 -93 169
+rect -73 151 -66 169
+rect -100 139 -66 151
+<< mvnsubdiffcont >>
+rect -93 151 -73 169
+<< poly >>
+rect -224 326 -173 339
+rect -476 248 -463 298
+rect -423 248 -327 298
+rect -288 248 -275 298
+rect -476 169 -463 219
+rect -423 169 -327 219
+rect -288 169 -275 219
+rect -133 248 -104 256
+rect -133 231 -126 248
+rect -109 231 -104 248
+rect -133 222 -104 231
+rect -133 193 -106 222
+rect -224 136 -173 142
+rect -476 119 -172 136
+rect -129 127 -106 193
+rect -129 125 -100 127
+rect -222 112 -172 119
+rect -150 112 -100 125
+rect -222 66 -172 81
+rect -150 65 -100 81
+<< polycont >>
+rect -126 231 -109 248
+<< locali >>
+rect -460 304 -452 321
+rect -434 304 -426 321
+rect -324 304 -316 321
+rect -299 304 -291 321
+rect -249 305 -232 313
+rect -249 271 -232 288
+rect -461 225 -453 242
+rect -434 225 -426 242
+rect -324 225 -316 242
+rect -299 225 -291 242
+rect -249 237 -232 254
+rect -249 203 -232 220
+rect -249 169 -232 186
+rect -461 146 -452 163
+rect -434 146 -426 163
+rect -324 146 -316 163
+rect -299 146 -291 163
+rect -249 144 -232 152
+rect -166 270 -149 287
+rect -166 236 -149 253
+rect -130 248 -106 256
+rect -130 231 -126 248
+rect -109 231 -106 248
+rect -130 223 -106 231
+rect -166 202 -149 219
+rect -129 219 -109 223
+rect -129 200 -128 219
+rect -110 200 -109 219
+rect -129 194 -109 200
+rect -129 193 -110 194
+rect -166 168 -149 185
+rect -93 176 -72 177
+rect -166 143 -149 151
+rect -94 169 -72 176
+rect -94 151 -93 169
+rect -73 151 -72 169
+rect -94 135 -72 151
+rect -94 118 -92 135
+rect -75 118 -72 135
+rect -93 115 -72 118
+rect -93 105 -73 115
+rect -256 88 -247 105
+rect -229 88 -221 105
+rect -93 80 -73 88
+<< viali >>
+rect -166 304 -148 323
+rect -128 200 -110 219
+rect -92 118 -75 135
+rect -274 88 -256 105
+<< metal1 >>
+rect -169 323 -145 329
+rect -169 304 -166 323
+rect -148 304 -145 323
+rect -169 291 -145 304
+rect -126 248 -110 350
+rect -130 224 -107 248
+rect -130 223 -106 224
+rect -131 219 -106 223
+rect -131 200 -128 219
+rect -110 200 -106 219
+rect -131 196 -106 200
+rect -129 193 -107 196
+rect -281 126 -250 129
+rect -281 100 -278 126
+rect -252 100 -250 126
+rect -281 88 -274 100
+rect -256 88 -250 100
+rect -281 85 -250 88
+rect -129 48 -110 193
+rect -85 181 -69 350
+rect -85 172 -68 181
+rect -96 167 -68 172
+rect -96 135 -69 167
+rect -96 118 -92 135
+rect -75 118 -69 135
+rect -96 112 -69 118
+rect -85 48 -69 112
+<< via1 >>
+rect -278 105 -252 126
+rect -278 100 -274 105
+rect -274 100 -256 105
+rect -256 100 -252 105
+<< metal2 >>
+rect -281 126 -250 129
+rect -281 100 -278 126
+rect -252 115 -250 126
+rect -252 100 -33 115
+rect -281 97 -33 100
+rect -281 96 -250 97
+<< end >>
diff --git a/mag/sky130_hilas_invert01.mag b/mag/sky130_hilas_invert01.mag
new file mode 100644
index 0000000..24c825a
--- /dev/null
+++ b/mag/sky130_hilas_invert01.mag
@@ -0,0 +1,62 @@
+magic
+tech scmos
+timestamp 1602540516
+<< polysilicon >>
+rect -8 0 -5 3
+rect 1 0 26 3
+rect 32 0 34 3
+rect 11 -3 14 0
+rect 9 -4 15 -3
+rect 9 -8 10 -4
+rect 14 -8 15 -4
+rect 9 -9 15 -8
+<< ndiffusion >>
+rect -5 9 1 10
+rect -5 5 -4 9
+rect 0 5 1 9
+rect -5 3 1 5
+rect -5 -2 1 0
+rect -5 -6 -4 -2
+rect 0 -6 1 -2
+rect -5 -7 1 -6
+<< pdiffusion >>
+rect 26 10 32 11
+rect 26 6 27 10
+rect 31 6 32 10
+rect 26 3 32 6
+rect 26 -3 32 0
+rect 26 -7 27 -3
+rect 31 -7 32 -3
+rect 26 -8 32 -7
+<< metal1 >>
+rect 10 9 14 16
+rect 0 6 27 9
+rect 0 5 31 6
+rect -8 -6 -4 -2
+rect 31 -7 34 -3
+rect 10 -15 14 -8
+<< metal2 >>
+rect -13 -2 -7 15
+rect -13 -6 -12 -2
+rect -8 -6 -7 -2
+rect -13 -12 -7 -6
+rect 33 -3 39 15
+rect 33 -7 34 -3
+rect 38 -7 39 -3
+rect 33 -12 39 -7
+<< ntransistor >>
+rect -5 0 1 3
+<< ptransistor >>
+rect 26 0 32 3
+<< polycontact >>
+rect 10 -8 14 -4
+<< ndcontact >>
+rect -4 5 0 9
+rect -4 -6 0 -2
+<< pdcontact >>
+rect 27 6 31 10
+rect 27 -7 31 -3
+<< m2contact >>
+rect -12 -6 -8 -2
+rect 34 -7 38 -3
+<< end >>
diff --git a/mag/sky130_hilas_li2m1.mag b/mag/sky130_hilas_li2m1.mag
new file mode 100644
index 0000000..5dca2c5
--- /dev/null
+++ b/mag/sky130_hilas_li2m1.mag
@@ -0,0 +1,20 @@
+magic
+tech sky130A
+timestamp 1607179295
+<< error_p >>
+rect -10 15 13 21
+rect -10 -2 -7 15
+rect -10 -8 13 -2
+<< locali >>
+rect -8 15 11 18
+rect -8 -2 -7 15
+rect 10 -2 11 15
+rect -8 -5 11 -2
+<< viali >>
+rect -7 -2 10 15
+<< metal1 >>
+rect -10 15 13 21
+rect -10 -2 -7 15
+rect 10 -2 13 15
+rect -10 -8 13 -2
+<< end >>
diff --git a/mag/sky130_hilas_li2m2.mag b/mag/sky130_hilas_li2m2.mag
new file mode 100644
index 0000000..34af6e6
--- /dev/null
+++ b/mag/sky130_hilas_li2m2.mag
@@ -0,0 +1,29 @@
+magic
+tech sky130A
+timestamp 1607089160
+<< locali >>
+rect -13 10 19 14
+rect -13 9 20 10
+rect -13 -8 -7 9
+rect 10 -8 20 9
+rect -13 -9 20 -8
+rect -13 -12 19 -9
+<< viali >>
+rect -7 -8 10 9
+<< metal1 >>
+rect -14 14 18 17
+rect -14 -12 -11 14
+rect 15 -12 18 14
+rect -14 -15 18 -12
+<< via1 >>
+rect -11 9 15 14
+rect -11 -8 -7 9
+rect -7 -8 10 9
+rect 10 -8 15 9
+rect -11 -12 15 -8
+<< metal2 >>
+rect -14 14 17 18
+rect -14 -12 -11 14
+rect 15 -12 17 14
+rect -14 -15 17 -12
+<< end >>
diff --git a/mag/sky130_hilas_m12m2.mag b/mag/sky130_hilas_m12m2.mag
new file mode 100644
index 0000000..5adc050
--- /dev/null
+++ b/mag/sky130_hilas_m12m2.mag
@@ -0,0 +1,12 @@
+magic
+tech sky130A
+timestamp 1607949437
+<< metal1 >>
+rect -6 19 20 22
+rect -6 -10 20 -7
+<< via1 >>
+rect -6 -7 20 19
+<< metal2 >>
+rect -9 -7 -6 19
+rect 20 -7 23 19
+<< end >>
diff --git a/mag/sky130_hilas_m22m4.mag b/mag/sky130_hilas_m22m4.mag
new file mode 100644
index 0000000..8430aca
--- /dev/null
+++ b/mag/sky130_hilas_m22m4.mag
@@ -0,0 +1,27 @@
+magic
+tech sky130A
+timestamp 1607701799
+<< metal2 >>
+rect -14 18 23 24
+rect -14 -10 -9 18
+rect 19 -10 23 18
+rect -14 -16 23 -10
+<< via2 >>
+rect -9 -10 19 18
+<< metal3 >>
+rect -36 27 43 39
+rect -36 -21 -17 27
+rect 26 -21 43 27
+rect -36 -36 43 -21
+<< via3 >>
+rect -17 18 26 27
+rect -17 -10 -9 18
+rect -9 -10 19 18
+rect 19 -10 26 18
+rect -17 -21 26 -10
+<< metal4 >>
+rect -27 27 39 36
+rect -27 -21 -17 27
+rect 26 -21 39 27
+rect -27 -30 39 -21
+<< end >>
diff --git a/mag/sky130_hilas_mcap2m4.mag b/mag/sky130_hilas_mcap2m4.mag
new file mode 100644
index 0000000..8430aca
--- /dev/null
+++ b/mag/sky130_hilas_mcap2m4.mag
@@ -0,0 +1,27 @@
+magic
+tech sky130A
+timestamp 1607701799
+<< metal2 >>
+rect -14 18 23 24
+rect -14 -10 -9 18
+rect 19 -10 23 18
+rect -14 -16 23 -10
+<< via2 >>
+rect -9 -10 19 18
+<< metal3 >>
+rect -36 27 43 39
+rect -36 -21 -17 27
+rect 26 -21 43 27
+rect -36 -36 43 -21
+<< via3 >>
+rect -17 18 26 27
+rect -17 -10 -9 18
+rect -9 -10 19 18
+rect 19 -10 26 18
+rect -17 -21 26 -10
+<< metal4 >>
+rect -27 27 39 36
+rect -27 -21 -17 27
+rect 26 -21 39 27
+rect -27 -30 39 -21
+<< end >>
diff --git a/mag/sky130_hilas_nDiffThOxContact.mag b/mag/sky130_hilas_nDiffThOxContact.mag
new file mode 100644
index 0000000..ca3c4b5
--- /dev/null
+++ b/mag/sky130_hilas_nDiffThOxContact.mag
@@ -0,0 +1,25 @@
+magic
+tech sky130A
+timestamp 1608039004
+<< error_p >>
+rect -24 41 39 42
+<< mvndiff >>
+rect -24 35 39 41
+rect -24 18 -18 35
+rect -1 18 16 35
+rect 33 18 39 35
+rect -24 13 39 18
+<< mvndiffc >>
+rect -18 18 -1 35
+rect 16 18 33 35
+<< locali >>
+rect -26 18 -18 35
+rect 33 18 41 35
+<< viali >>
+rect -1 18 16 35
+<< metal1 >>
+rect -12 35 27 38
+rect -12 18 -1 35
+rect 16 18 27 35
+rect -12 15 27 18
+<< end >>
diff --git a/mag/sky130_hilas_nFET03.mag b/mag/sky130_hilas_nFET03.mag
new file mode 100644
index 0000000..a5681a9
--- /dev/null
+++ b/mag/sky130_hilas_nFET03.mag
@@ -0,0 +1,26 @@
+magic
+tech sky130A
+timestamp 1607185713
+<< nmos >>
+rect 0 -6 27 29
+<< ndiff >>
+rect -31 20 0 29
+rect -31 3 -26 20
+rect -6 3 0 20
+rect -31 -6 0 3
+rect 27 20 58 29
+rect 27 3 33 20
+rect 53 3 58 20
+rect 27 -6 58 3
+<< ndiffc >>
+rect -26 3 -6 20
+rect 33 3 53 20
+<< poly >>
+rect 0 29 27 42
+rect 0 -19 27 -6
+<< locali >>
+rect -26 20 -6 28
+rect -26 -5 -6 3
+rect 33 20 53 28
+rect 33 -5 53 3
+<< end >>
diff --git a/mag/sky130_hilas_nFET03a.mag b/mag/sky130_hilas_nFET03a.mag
new file mode 100644
index 0000000..2a67a68
--- /dev/null
+++ b/mag/sky130_hilas_nFET03a.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+timestamp 1608056777
+<< nmos >>
+rect 0 -6 27 29
+<< ndiff >>
+rect -31 20 0 29
+rect -31 3 -26 20
+rect -6 3 0 20
+rect -31 -6 0 3
+rect 27 20 58 29
+rect 27 3 33 20
+rect 53 3 58 20
+rect 27 -6 58 3
+<< ndiffc >>
+rect -26 3 -6 20
+rect 33 3 53 20
+<< poly >>
+rect 0 29 27 42
+rect 0 -14 27 -6
+rect -92 -29 27 -14
+<< locali >>
+rect -26 20 -6 28
+rect -26 -5 -6 3
+rect 33 20 53 28
+rect 33 -5 53 3
+<< metal2 >>
+rect -111 2 -51 19
+rect 75 3 97 20
+rect -111 -39 -94 -22
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_0
+timestamp 1607270276
+transform 0 -1 -76 1 0 -38
+box -9 -26 24 29
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 -44 0 1 10
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 65 0 1 11
+box -14 -15 20 18
+<< end >>
diff --git a/mag/sky130_hilas_nFETLarge.mag b/mag/sky130_hilas_nFETLarge.mag
new file mode 100644
index 0000000..def38ed
--- /dev/null
+++ b/mag/sky130_hilas_nFETLarge.mag
@@ -0,0 +1,198 @@
+magic
+tech sky130A
+timestamp 1625426387
+<< psubdiff >>
+rect 77 642 117 896
+rect 77 625 88 642
+rect 105 625 117 642
+rect 77 608 117 625
+rect 77 591 88 608
+rect 105 591 117 608
+rect 77 574 117 591
+rect 77 557 88 574
+rect 105 557 117 574
+rect 77 535 117 557
+<< psubdiffcont >>
+rect 88 625 105 642
+rect 88 591 105 608
+rect 88 557 105 574
+<< poly >>
+rect 126 988 428 1003
+rect 126 725 145 988
+rect 126 710 429 725
+rect 126 523 146 710
+rect 78 513 146 523
+rect 78 496 83 513
+rect 100 496 117 513
+rect 134 496 146 513
+rect 78 479 146 496
+rect 78 462 84 479
+rect 101 462 118 479
+rect 135 462 146 479
+rect 78 447 146 462
+rect 78 445 428 447
+rect 78 428 84 445
+rect 101 428 118 445
+rect 135 430 428 445
+rect 135 428 161 430
+rect 78 423 161 428
+rect 78 420 147 423
+<< polycont >>
+rect 83 496 100 513
+rect 117 496 134 513
+rect 84 462 101 479
+rect 118 462 135 479
+rect 84 428 101 445
+rect 118 428 135 445
+<< locali >>
+rect 159 700 176 738
+rect 214 700 231 738
+rect 269 700 286 738
+rect 324 700 341 738
+rect 379 700 396 738
+rect 434 700 451 738
+rect 83 513 134 521
+rect 100 496 117 513
+rect 83 495 134 496
+rect 83 488 135 495
+rect 84 479 135 488
+rect 101 462 118 479
+rect 84 445 135 462
+rect 101 428 118 445
+rect 84 420 135 428
+<< viali >>
+rect 88 642 105 659
+rect 88 608 105 625
+rect 88 574 105 591
+rect 88 540 105 557
+<< metal1 >>
+rect 82 659 110 665
+rect 82 642 88 659
+rect 105 642 110 659
+rect 82 625 110 642
+rect 82 612 88 625
+rect 64 608 88 612
+rect 105 608 110 625
+rect 64 591 110 608
+rect 64 580 88 591
+rect 82 574 88 580
+rect 105 582 110 591
+rect 105 574 111 582
+rect 82 557 111 574
+rect 82 540 88 557
+rect 105 540 111 557
+rect 82 537 111 540
+<< metal2 >>
+rect 97 979 403 980
+rect 88 946 403 979
+rect 88 701 120 946
+rect 207 878 501 908
+rect 426 874 501 878
+rect 463 861 501 874
+rect 466 774 501 861
+rect 206 741 501 774
+rect 88 668 404 701
+rect 88 564 120 668
+rect 88 532 404 564
+rect 64 420 124 502
+rect 466 497 501 741
+rect 207 465 501 497
+rect 207 464 478 465
+use sky130_hilas_li2m2 sky130_hilas_li2m2_8
+timestamp 1607089160
+transform 1 0 107 0 1 482
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_7
+timestamp 1607089160
+transform 1 0 108 0 1 435
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_9
+timestamp 1607089160
+transform 1 0 164 0 1 546
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_19
+timestamp 1607089160
+transform 1 0 439 0 1 479
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_17
+timestamp 1607089160
+transform 1 0 329 0 1 478
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_15
+timestamp 1607089160
+transform 1 0 220 0 1 478
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_6
+timestamp 1607089160
+transform 1 0 384 0 1 546
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_10
+timestamp 1607089160
+transform 1 0 274 0 1 546
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 164 0 1 683
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_2
+timestamp 1607089160
+transform 1 0 384 0 1 683
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 274 0 1 683
+box -14 -15 20 18
+use sky130_hilas_nFETLargePart1 sky130_hilas_nFETLargePart1_1
+timestamp 1607983547
+transform 1 0 319 0 1 473
+box -165 -31 137 241
+use sky130_hilas_li2m2 sky130_hilas_li2m2_5
+timestamp 1607089160
+transform 1 0 439 0 1 756
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_4
+timestamp 1607089160
+transform 1 0 220 0 1 756
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_3
+timestamp 1607089160
+transform 1 0 329 0 1 756
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_13
+timestamp 1607089160
+transform 1 0 440 0 1 890
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_12
+timestamp 1607089160
+transform 1 0 329 0 1 891
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_16
+timestamp 1607089160
+transform 1 0 220 0 1 893
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_11
+timestamp 1607089160
+transform 1 0 165 0 1 961
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_18
+timestamp 1607089160
+transform 1 0 384 0 1 960
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_14
+timestamp 1607089160
+transform 1 0 274 0 1 961
+box -14 -15 20 18
+use sky130_hilas_nFETLargePart1 sky130_hilas_nFETLargePart1_0
+timestamp 1607983547
+transform 1 0 319 0 1 751
+box -165 -31 137 241
+<< labels >>
+rlabel metal2 486 834 500 908 0 DRAIN
+port 3 nsew analog default
+rlabel metal2 88 905 102 979 0 SOURCE
+port 2 nsew analog default
+rlabel metal2 64 420 74 502 0 GATE
+port 1 nsew analog default
+rlabel metal1 64 580 71 612 0 VGND
+port 4 nsew
+<< end >>
diff --git a/mag/sky130_hilas_nFETLargePart1.mag b/mag/sky130_hilas_nFETLargePart1.mag
new file mode 100644
index 0000000..1d42c22
--- /dev/null
+++ b/mag/sky130_hilas_nFETLargePart1.mag
@@ -0,0 +1,24 @@
+magic
+tech sky130A
+timestamp 1607983547
+use sky130_hilas_nFETmed sky130_hilas_nFETmed_2
+timestamp 1607963611
+transform 1 0 12 0 1 13
+box -12 -44 70 228
+use sky130_hilas_nFETmed sky130_hilas_nFETmed_1
+timestamp 1607963611
+transform 1 0 -43 0 1 13
+box -12 -44 70 228
+use sky130_hilas_nFETmed sky130_hilas_nFETmed_0
+timestamp 1607963611
+transform 1 0 -98 0 1 13
+box -12 -44 70 228
+use sky130_hilas_nFETmed sky130_hilas_nFETmed_4
+timestamp 1607963611
+transform 1 0 -153 0 1 13
+box -12 -44 70 228
+use sky130_hilas_nFETmed sky130_hilas_nFETmed_3
+timestamp 1607963611
+transform 1 0 67 0 1 13
+box -12 -44 70 228
+<< end >>
diff --git a/mag/sky130_hilas_nFETmed.mag b/mag/sky130_hilas_nFETmed.mag
new file mode 100644
index 0000000..c088151
--- /dev/null
+++ b/mag/sky130_hilas_nFETmed.mag
@@ -0,0 +1,86 @@
+magic
+tech sky130A
+timestamp 1607963611
+<< nmos >>
+rect 16 -31 42 215
+<< ndiff >>
+rect -12 206 16 215
+rect -12 189 -7 206
+rect 10 189 16 206
+rect -12 172 16 189
+rect -12 155 -7 172
+rect 10 155 16 172
+rect -12 138 16 155
+rect -12 121 -7 138
+rect 10 121 16 138
+rect -12 104 16 121
+rect -12 87 -7 104
+rect 10 87 16 104
+rect -12 70 16 87
+rect -12 53 -7 70
+rect 10 53 16 70
+rect -12 36 16 53
+rect -12 19 -7 36
+rect 10 19 16 36
+rect -12 2 16 19
+rect -12 -15 -7 2
+rect 10 -15 16 2
+rect -12 -31 16 -15
+rect 42 206 70 215
+rect 42 189 48 206
+rect 65 189 70 206
+rect 42 172 70 189
+rect 42 155 48 172
+rect 65 155 70 172
+rect 42 138 70 155
+rect 42 121 48 138
+rect 65 121 70 138
+rect 42 104 70 121
+rect 42 87 48 104
+rect 65 87 70 104
+rect 42 70 70 87
+rect 42 53 48 70
+rect 65 53 70 70
+rect 42 36 70 53
+rect 42 19 48 36
+rect 65 19 70 36
+rect 42 2 70 19
+rect 42 -15 48 2
+rect 65 -15 70 2
+rect 42 -31 70 -15
+<< ndiffc >>
+rect -7 189 10 206
+rect -7 155 10 172
+rect -7 121 10 138
+rect -7 87 10 104
+rect -7 53 10 70
+rect -7 19 10 36
+rect -7 -15 10 2
+rect 48 189 65 206
+rect 48 155 65 172
+rect 48 121 65 138
+rect 48 87 65 104
+rect 48 53 65 70
+rect 48 19 65 36
+rect 48 -15 65 2
+<< poly >>
+rect 16 215 42 228
+rect 16 -44 42 -31
+<< locali >>
+rect -7 206 10 214
+rect -7 172 10 189
+rect -7 138 10 155
+rect -7 104 10 121
+rect -7 70 10 87
+rect -7 36 10 53
+rect -7 2 10 19
+rect -7 -26 10 -15
+rect 48 206 65 214
+rect 48 172 65 189
+rect 48 138 65 155
+rect 48 104 65 121
+rect 48 70 65 87
+rect 48 36 65 53
+rect 48 2 65 19
+rect 48 -26 65 -15
+<< end >>
diff --git a/mag/sky130_hilas_nFETmirrorPairs.mag b/mag/sky130_hilas_nFETmirrorPairs.mag
new file mode 100644
index 0000000..254a2aa
--- /dev/null
+++ b/mag/sky130_hilas_nFETmirrorPairs.mag
@@ -0,0 +1,133 @@
+magic
+tech sky130A
+timestamp 1607184666
+<< error_p >>
+rect 85 -19 102 -18
+rect 109 -30 110 11
+rect 73 -42 77 -30
+rect 109 -42 114 -30
+rect 109 -58 110 -42
+rect 109 -90 110 -59
+rect 109 -148 110 -119
+<< nmos >>
+rect -8 11 25 40
+rect 77 11 110 40
+rect -8 -119 25 -90
+rect 77 -119 110 -90
+<< ndiff >>
+rect -8 64 25 68
+rect -8 47 0 64
+rect 17 47 25 64
+rect -8 40 25 47
+rect 77 64 110 68
+rect 77 47 85 64
+rect 102 47 110 64
+rect 77 40 110 47
+rect -8 4 25 11
+rect -8 -13 0 4
+rect 17 -13 25 4
+rect -8 -19 25 -13
+rect -8 -67 25 -60
+rect -8 -84 0 -67
+rect 17 -84 25 -67
+rect -8 -90 25 -84
+rect 77 4 110 11
+rect 77 -13 85 4
+rect 102 -13 110 4
+rect 77 -19 110 -13
+rect 77 -66 110 -59
+rect 77 -83 85 -66
+rect 102 -83 110 -66
+rect 77 -90 110 -83
+rect -8 -126 25 -119
+rect -8 -143 -1 -126
+rect 17 -143 25 -126
+rect -8 -147 25 -143
+rect 77 -125 110 -119
+rect 77 -142 84 -125
+rect 103 -142 110 -125
+rect 77 -148 110 -142
+<< ndiffc >>
+rect 0 47 17 64
+rect 85 47 102 64
+rect 0 -13 17 4
+rect 0 -84 17 -67
+rect 85 -13 102 4
+rect 85 -83 102 -66
+rect -1 -143 17 -126
+rect 84 -142 103 -125
+<< psubdiff >>
+rect -8 -31 25 -19
+rect -8 -48 0 -31
+rect 17 -48 25 -31
+rect -8 -60 25 -48
+rect 77 -30 110 -19
+rect 77 -47 85 -30
+rect 102 -47 110 -30
+rect 77 -58 110 -47
+rect 77 -59 109 -58
+<< psubdiffcont >>
+rect 0 -48 17 -31
+rect 85 -47 102 -30
+<< poly >>
+rect -33 11 -8 40
+rect 25 11 38 40
+rect 63 11 77 40
+rect 110 11 133 40
+rect -33 -90 -17 11
+rect 117 -90 133 11
+rect -33 -119 -8 -90
+rect 25 -119 38 -90
+rect 62 -119 77 -90
+rect 110 -119 133 -90
+rect -33 -158 -17 -119
+rect -33 -166 26 -158
+rect 117 -159 133 -119
+rect -33 -183 -1 -166
+rect 17 -183 26 -166
+rect -33 -189 26 -183
+rect 77 -167 133 -159
+rect 77 -184 86 -167
+rect 103 -184 133 -167
+rect 77 -189 133 -184
+<< polycont >>
+rect -1 -183 17 -166
+rect 86 -184 103 -167
+<< locali >>
+rect -5 64 22 83
+rect 85 65 110 83
+rect 77 64 110 65
+rect -8 47 0 64
+rect 17 47 25 64
+rect 77 47 85 64
+rect 102 47 110 64
+rect -12 -13 0 4
+rect 17 -13 29 4
+rect -12 -20 29 -13
+rect 73 -13 85 4
+rect 102 -13 114 4
+rect 73 -20 114 -13
+rect -12 -30 114 -20
+rect -12 -31 85 -30
+rect -12 -48 0 -31
+rect 17 -47 85 -31
+rect 102 -47 114 -30
+rect 17 -48 114 -47
+rect -12 -58 114 -48
+rect -12 -67 29 -58
+rect -12 -84 0 -67
+rect 17 -84 29 -67
+rect 73 -66 114 -58
+rect 73 -83 85 -66
+rect 102 -83 114 -66
+rect -9 -143 -1 -126
+rect 17 -143 25 -126
+rect 76 -142 84 -125
+rect 103 -142 112 -125
+rect 76 -143 112 -142
+rect -1 -166 17 -143
+rect -1 -192 17 -183
+rect 84 -167 103 -143
+rect 84 -184 86 -167
+rect 84 -192 103 -184
+<< end >>
diff --git a/mag/sky130_hilas_nFETmirrorPairs2.mag b/mag/sky130_hilas_nFETmirrorPairs2.mag
new file mode 100644
index 0000000..3e15bbb
--- /dev/null
+++ b/mag/sky130_hilas_nFETmirrorPairs2.mag
@@ -0,0 +1,234 @@
+magic
+tech sky130A
+timestamp 1607186163
+<< error_s >>
+rect 85 -19 102 -18
+rect 109 -30 110 11
+rect 73 -42 77 -30
+rect 109 -42 114 -30
+rect 109 -58 110 -42
+rect 109 -90 110 -59
+rect 109 -148 110 -119
+<< nwell >>
+rect -61 112 158 285
+<< nmos >>
+rect -8 11 25 40
+rect 77 11 110 40
+rect -8 -119 25 -90
+rect 77 -119 110 -90
+<< pmos >>
+rect -40 164 28 194
+rect 64 164 132 194
+<< ndiff >>
+rect -8 64 25 68
+rect -8 47 0 64
+rect 17 47 25 64
+rect -8 40 25 47
+rect 77 64 110 68
+rect 77 47 85 64
+rect 102 47 110 64
+rect 77 40 110 47
+rect -8 4 25 11
+rect -8 -13 0 4
+rect 17 -13 25 4
+rect -8 -19 25 -13
+rect -8 -67 25 -60
+rect -8 -84 0 -67
+rect 17 -84 25 -67
+rect -8 -90 25 -84
+rect 77 4 110 11
+rect 77 -13 85 4
+rect 102 -13 110 4
+rect 77 -19 110 -13
+rect 77 -66 110 -59
+rect 77 -83 85 -66
+rect 102 -83 110 -66
+rect 77 -90 110 -83
+rect -8 -126 25 -119
+rect -8 -143 -1 -126
+rect 17 -143 25 -126
+rect -8 -147 25 -143
+rect 77 -125 110 -119
+rect 77 -142 84 -125
+rect 103 -142 110 -125
+rect 77 -148 110 -142
+<< pdiff >>
+rect -40 218 28 224
+rect -40 201 -32 218
+rect -14 201 4 218
+rect 22 201 28 218
+rect -40 194 28 201
+rect 64 218 132 224
+rect 64 201 72 218
+rect 90 201 109 218
+rect 128 201 132 218
+rect 64 194 132 201
+rect -40 157 28 164
+rect -40 140 -32 157
+rect -14 140 4 157
+rect 22 140 28 157
+rect -40 131 28 140
+rect 64 157 132 164
+rect 64 140 70 157
+rect 88 140 106 157
+rect 124 140 132 157
+rect 64 136 132 140
+rect 71 131 132 136
+<< ndiffc >>
+rect 0 47 17 64
+rect 85 47 102 64
+rect 0 -13 17 4
+rect 0 -84 17 -67
+rect 85 -13 102 4
+rect 85 -83 102 -66
+rect -1 -143 17 -126
+rect 84 -142 103 -125
+<< pdiffc >>
+rect -32 201 -14 218
+rect 4 201 22 218
+rect 72 201 90 218
+rect 109 201 128 218
+rect -32 140 -14 157
+rect 4 140 22 157
+rect 70 140 88 157
+rect 106 140 124 157
+<< psubdiff >>
+rect -8 -31 25 -19
+rect -8 -48 0 -31
+rect 17 -48 25 -31
+rect -8 -60 25 -48
+rect 77 -30 110 -19
+rect 77 -47 85 -30
+rect 102 -47 110 -30
+rect 77 -58 110 -47
+rect 77 -59 109 -58
+<< nsubdiff >>
+rect -40 253 28 265
+rect -40 236 -32 253
+rect -14 236 4 253
+rect 22 236 28 253
+rect -40 224 28 236
+rect 64 253 132 265
+rect 64 236 72 253
+rect 90 236 109 253
+rect 128 236 132 253
+rect 64 224 132 236
+<< psubdiffcont >>
+rect 0 -48 17 -31
+rect 85 -47 102 -30
+<< nsubdiffcont >>
+rect -32 236 -14 253
+rect 4 236 22 253
+rect 72 236 90 253
+rect 109 236 128 253
+<< poly >>
+rect -53 164 -40 194
+rect 28 164 64 194
+rect 132 164 145 194
+rect 36 120 53 164
+rect 30 112 57 120
+rect 30 95 35 112
+rect 52 95 57 112
+rect 30 87 57 95
+rect -278 23 -251 27
+rect -33 11 -8 40
+rect 25 11 38 40
+rect 63 11 77 40
+rect 110 11 133 40
+rect -33 -90 -17 11
+rect 117 -90 133 11
+rect -33 -119 -8 -90
+rect 25 -119 38 -90
+rect 62 -119 77 -90
+rect 110 -119 133 -90
+rect -278 -123 -251 -120
+rect -33 -158 -17 -119
+rect -33 -166 26 -158
+rect 117 -159 133 -119
+rect -33 -183 -1 -166
+rect 17 -183 26 -166
+rect -33 -189 26 -183
+rect 77 -167 133 -159
+rect 77 -184 86 -167
+rect 103 -184 133 -167
+rect 77 -189 133 -184
+<< polycont >>
+rect 35 95 52 112
+rect -1 -183 17 -166
+rect 86 -184 103 -167
+<< locali >>
+rect -40 236 -32 253
+rect -14 236 4 253
+rect 22 236 72 253
+rect 90 236 109 253
+rect 128 236 136 253
+rect -40 218 136 236
+rect -40 201 -32 218
+rect -14 201 4 218
+rect 22 201 72 218
+rect 90 201 109 218
+rect 128 201 136 218
+rect -40 140 -32 157
+rect -14 140 4 157
+rect 22 140 31 157
+rect 62 140 70 157
+rect 88 140 106 157
+rect 124 140 132 157
+rect -5 123 31 140
+rect -5 112 60 123
+rect -5 95 35 112
+rect 52 95 60 112
+rect -5 87 60 95
+rect -5 64 22 87
+rect 85 65 110 140
+rect 77 64 110 65
+rect -8 47 0 64
+rect 17 47 25 64
+rect 77 47 85 64
+rect 102 47 110 64
+rect -12 -13 0 4
+rect 17 -13 29 4
+rect -12 -20 29 -13
+rect 73 -13 85 4
+rect 102 -13 114 4
+rect 73 -20 114 -13
+rect -12 -30 114 -20
+rect -12 -31 85 -30
+rect -12 -48 0 -31
+rect 17 -47 85 -31
+rect 102 -47 114 -30
+rect 17 -48 114 -47
+rect -12 -58 114 -48
+rect -12 -67 29 -58
+rect -12 -84 0 -67
+rect 17 -84 29 -67
+rect 73 -66 114 -58
+rect 73 -83 85 -66
+rect 102 -83 114 -66
+rect -9 -143 -1 -126
+rect 17 -143 25 -126
+rect 76 -142 84 -125
+rect 103 -142 112 -125
+rect 76 -143 112 -142
+rect -1 -166 17 -143
+rect -1 -192 17 -183
+rect 84 -167 103 -143
+rect 84 -184 86 -167
+rect 84 -192 103 -184
+use sky130_hilas_nFET03 sky130_hilas_nFET03_3
+timestamp 1607185713
+transform 1 0 -278 0 1 46
+box -31 -19 58 42
+use sky130_hilas_nFET03 sky130_hilas_nFET03_2
+timestamp 1607185713
+transform 1 0 -278 0 1 -19
+box -31 -19 58 42
+use sky130_hilas_nFET03 sky130_hilas_nFET03_1
+timestamp 1607185713
+transform 1 0 -278 0 1 -101
+box -31 -19 58 42
+use sky130_hilas_nFET03 sky130_hilas_nFET03_0
+timestamp 1607185713
+transform 1 0 -278 0 1 -165
+box -31 -19 58 42
+<< end >>
diff --git a/mag/sky130_hilas_nMirror03.mag b/mag/sky130_hilas_nMirror03.mag
new file mode 100644
index 0000000..7e484f8
--- /dev/null
+++ b/mag/sky130_hilas_nMirror03.mag
@@ -0,0 +1,61 @@
+magic
+tech sky130A
+timestamp 1607268356
+<< error_s >>
+rect 78 67 101 73
+rect 78 50 81 67
+rect 78 44 101 50
+<< psubdiff >>
+rect 84 100 125 109
+rect 84 83 96 100
+rect 113 83 125 100
+rect 84 74 125 83
+rect 84 34 125 43
+rect 84 17 96 34
+rect 113 17 125 34
+rect 84 8 125 17
+<< psubdiffcont >>
+rect 96 83 113 100
+rect 96 17 113 34
+<< poly >>
+rect -46 56 53 66
+rect -46 51 26 56
+rect -46 43 -19 51
+<< locali >>
+rect 79 100 114 108
+rect 79 83 96 100
+rect 113 83 114 100
+rect 59 75 78 76
+rect 79 75 114 83
+rect 59 42 114 75
+rect 79 34 114 42
+rect 79 17 96 34
+rect 113 17 114 34
+rect 79 9 114 17
+<< metal2 >>
+rect -59 14 -26 35
+use sky130_hilas_nFET03 sky130_hilas_nFET03_1
+timestamp 1607185713
+transform 1 0 26 0 1 80
+box -31 -19 58 42
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 -10 0 1 90
+box -14 -15 20 18
+use sky130_hilas_poly2li sky130_hilas_poly2li_0
+timestamp 1607178257
+transform 1 0 -37 0 1 24
+box -9 -14 18 19
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 -15 0 1 25
+box -14 -15 20 18
+use sky130_hilas_nFET03 sky130_hilas_nFET03_0
+timestamp 1607185713
+transform 1 0 26 0 1 14
+box -31 -19 58 42
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 88 0 1 52
+box -10 -8 13 21
+<< end >>
diff --git a/mag/sky130_hilas_nOverlapCap01.mag b/mag/sky130_hilas_nOverlapCap01.mag
new file mode 100644
index 0000000..f1353bb
--- /dev/null
+++ b/mag/sky130_hilas_nOverlapCap01.mag
@@ -0,0 +1,51 @@
+magic
+tech sky130A
+timestamp 1607262215
+<< error_p >>
+rect -12 68 17 86
+rect -12 36 -11 37
+rect 16 36 17 37
+rect -62 7 -44 36
+rect -13 35 18 36
+rect -12 26 17 35
+rect -12 17 -2 26
+rect 7 17 17 26
+rect -12 8 17 17
+rect -13 7 18 8
+rect 49 7 67 36
+rect -12 6 -11 7
+rect 16 6 17 7
+rect -12 -43 17 -25
+<< mvnmos >>
+rect -44 36 49 68
+rect -44 7 -12 36
+rect 17 7 49 36
+rect -44 -25 49 7
+<< mvndiff >>
+rect -12 30 17 36
+rect -12 13 -6 30
+rect 11 13 17 30
+rect -12 7 17 13
+<< mvndiffc >>
+rect -6 13 11 30
+<< poly >>
+rect -57 68 62 81
+rect -57 -25 -44 68
+rect 49 -25 62 68
+rect -57 -38 62 -25
+<< locali >>
+rect -6 64 11 67
+rect -6 30 11 47
+rect -6 -5 11 13
+<< viali >>
+rect -6 47 11 64
+rect -6 -22 11 -5
+<< metal1 >>
+rect -9 64 14 86
+rect -9 47 -6 64
+rect 11 47 14 64
+rect -9 -5 14 47
+rect -9 -22 -6 -5
+rect 11 -22 14 -5
+rect -9 -43 14 -22
+<< end >>
diff --git a/mag/sky130_hilas_overlapCap01.mag b/mag/sky130_hilas_overlapCap01.mag
new file mode 100644
index 0000000..b3b63df
--- /dev/null
+++ b/mag/sky130_hilas_overlapCap01.mag
@@ -0,0 +1,163 @@
+magic
+tech sky130A
+timestamp 1607257541
+<< error_p >>
+rect -237 109 -208 137
+rect -158 109 -129 137
+rect -79 109 -50 137
+rect -259 102 -29 109
+rect -259 87 -252 102
+rect -237 96 -208 102
+rect -158 96 -129 102
+rect -79 96 -50 102
+rect -237 87 -236 88
+rect -209 87 -208 88
+rect -158 87 -157 88
+rect -130 87 -129 88
+rect -79 87 -78 88
+rect -51 87 -50 88
+rect -36 87 -29 102
+rect -287 58 -246 87
+rect -238 86 -207 87
+rect -159 86 -128 87
+rect -80 86 -49 87
+rect -237 59 -208 86
+rect -158 59 -129 86
+rect -79 59 -50 86
+rect -238 58 -207 59
+rect -159 58 -128 59
+rect -80 58 -49 59
+rect -42 58 0 87
+rect -259 8 -252 58
+rect -237 57 -236 58
+rect -209 57 -208 58
+rect -158 57 -157 58
+rect -130 57 -129 58
+rect -79 57 -78 58
+rect -51 57 -50 58
+rect -237 8 -236 9
+rect -209 8 -208 9
+rect -158 8 -157 9
+rect -130 8 -129 9
+rect -79 8 -78 9
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+<< nwell >>
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+<< mvpmos >>
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+rect -246 -30 -42 -21
+<< mvpdiff >>
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+rect -79 2 -50 8
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+rect -56 -15 -50 2
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+<< mvpdiffc >>
+rect -231 64 -214 81
+rect -152 64 -135 81
+rect -73 64 -56 81
+rect -231 -15 -214 1
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+rect -73 -15 -56 2
+<< poly >>
+rect -252 96 -36 102
+rect -252 -30 -246 96
+rect -42 -30 -36 96
+rect -252 -36 -36 -30
+<< locali >>
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+rect -241 64 -231 81
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+rect -176 64 -152 74
+rect -135 64 -73 81
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+rect -241 23 -193 40
+rect -176 23 -46 40
+rect -241 6 -46 23
+rect -241 1 -193 6
+rect -241 -15 -231 1
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+rect -176 2 -46 6
+rect -176 1 -73 2
+rect -176 -11 -152 1
+rect -214 -15 -152 -11
+rect -135 -15 -73 1
+rect -56 -15 -46 2
+rect -241 -26 -46 -15
+<< viali >>
+rect -193 57 -176 74
+rect -193 23 -176 40
+rect -193 -11 -176 6
+<< metal1 >>
+rect -197 74 -171 80
+rect -197 57 -193 74
+rect -176 57 -171 74
+rect -197 40 -171 57
+rect -197 32 -193 40
+rect -198 23 -193 32
+rect -176 23 -171 40
+rect -198 6 -171 23
+rect -198 -11 -193 6
+rect -176 -11 -171 6
+rect -198 -20 -171 -11
+rect -198 -65 -172 -20
+<< end >>
diff --git a/mag/sky130_hilas_overlapCap02.mag b/mag/sky130_hilas_overlapCap02.mag
new file mode 100644
index 0000000..f06026d
--- /dev/null
+++ b/mag/sky130_hilas_overlapCap02.mag
@@ -0,0 +1,108 @@
+magic
+tech sky130A
+timestamp 1607260043
+<< error_p >>
+rect -454 43 -453 44
+rect -426 43 -425 44
+rect -375 43 -374 44
+rect -347 43 -346 44
+rect -296 43 -295 44
+rect -268 43 -267 44
+rect -217 43 -216 44
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+rect -425 42 -424 43
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+rect -297 42 -296 43
+rect -267 42 -266 43
+rect -218 42 -217 43
+rect -188 42 -187 43
+rect -455 14 -454 15
+rect -425 14 -424 15
+rect -376 14 -375 15
+rect -346 14 -345 15
+rect -297 14 -296 15
+rect -267 14 -266 15
+rect -218 14 -217 15
+rect -188 14 -187 15
+rect -454 13 -453 14
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+rect -375 13 -374 14
+rect -347 13 -346 14
+rect -296 13 -295 14
+rect -268 13 -267 14
+rect -217 13 -216 14
+rect -189 13 -188 14
+<< nwell >>
+rect -537 -69 -105 126
+<< mvpmos >>
+rect -504 43 -138 93
+rect -504 14 -454 43
+rect -425 14 -375 43
+rect -346 14 -296 43
+rect -267 14 -217 43
+rect -188 14 -138 43
+rect -504 -36 -138 14
+<< mvpdiff >>
+rect -454 37 -425 43
+rect -454 20 -448 37
+rect -431 20 -425 37
+rect -454 14 -425 20
+rect -375 37 -346 43
+rect -375 20 -369 37
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+rect -296 14 -267 20
+rect -217 37 -188 43
+rect -217 20 -211 37
+rect -194 20 -188 37
+rect -217 14 -188 20
+<< mvpdiffc >>
+rect -448 20 -431 37
+rect -369 20 -352 37
+rect -290 20 -273 37
+rect -211 20 -194 37
+<< poly >>
+rect -518 93 -124 106
+rect -518 -36 -504 93
+rect -138 -36 -124 93
+rect -518 -50 -124 -36
+<< locali >>
+rect -512 71 -132 98
+rect -512 54 -329 71
+rect -312 54 -132 71
+rect -512 37 -132 54
+rect -512 20 -448 37
+rect -431 20 -369 37
+rect -352 36 -290 37
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+rect -512 19 -329 20
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+rect -312 19 -132 20
+rect -512 2 -132 19
+rect -512 -15 -329 2
+rect -312 -15 -132 2
+rect -512 -43 -132 -15
+<< viali >>
+rect -329 54 -312 71
+rect -329 19 -312 36
+rect -329 -15 -312 2
+<< metal1 >>
+rect -333 71 -309 77
+rect -333 54 -329 71
+rect -312 54 -309 71
+rect -333 36 -309 54
+rect -333 19 -329 36
+rect -312 19 -309 36
+rect -333 13 -309 19
+rect -332 2 -309 13
+rect -332 -15 -329 2
+rect -312 -15 -309 2
+rect -332 -52 -309 -15
+<< end >>
diff --git a/mag/sky130_hilas_overlapCap02a.mag b/mag/sky130_hilas_overlapCap02a.mag
new file mode 100644
index 0000000..e0a455d
--- /dev/null
+++ b/mag/sky130_hilas_overlapCap02a.mag
@@ -0,0 +1,121 @@
+magic
+tech sky130A
+timestamp 1607261501
+<< error_p >>
+rect -454 77 -425 93
+rect -375 77 -346 93
+rect -296 77 -267 93
+rect -217 77 -188 93
+rect -454 43 -453 44
+rect -426 43 -425 44
+rect -375 43 -374 44
+rect -347 43 -346 44
+rect -296 43 -295 44
+rect -268 43 -267 44
+rect -217 43 -216 44
+rect -189 43 -188 44
+rect -504 14 -486 43
+rect -455 42 -424 43
+rect -376 42 -345 43
+rect -297 42 -266 43
+rect -218 42 -187 43
+rect -454 35 -425 42
+rect -375 35 -346 42
+rect -296 35 -267 42
+rect -217 35 -188 42
+rect -454 21 -444 35
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+rect -454 15 -425 21
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+rect -296 15 -267 21
+rect -217 15 -188 21
+rect -455 14 -424 15
+rect -376 14 -345 15
+rect -297 14 -266 15
+rect -218 14 -187 15
+rect -155 14 -138 43
+rect -454 13 -453 14
+rect -426 13 -425 14
+rect -375 13 -374 14
+rect -347 13 -346 14
+rect -296 13 -295 14
+rect -268 13 -267 14
+rect -217 13 -216 14
+rect -189 13 -188 14
+rect -454 -36 -425 -21
+rect -375 -36 -346 -21
+rect -296 -36 -267 -21
+rect -217 -36 -188 -21
+<< nwell >>
+rect -521 -54 -121 110
+<< mvpmos >>
+rect -486 43 -155 77
+rect -486 14 -454 43
+rect -425 14 -375 43
+rect -346 14 -296 43
+rect -267 14 -217 43
+rect -188 14 -155 43
+rect -486 -21 -155 14
+<< mvpdiff >>
+rect -454 37 -425 43
+rect -454 20 -448 37
+rect -431 20 -425 37
+rect -454 14 -425 20
+rect -375 37 -346 43
+rect -375 20 -369 37
+rect -352 20 -346 37
+rect -375 14 -346 20
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+rect -273 20 -267 37
+rect -296 14 -267 20
+rect -217 37 -188 43
+rect -217 20 -211 37
+rect -194 20 -188 37
+rect -217 14 -188 20
+<< mvpdiffc >>
+rect -448 20 -431 37
+rect -369 20 -352 37
+rect -290 20 -273 37
+rect -211 20 -194 37
+<< poly >>
+rect -502 77 -140 91
+rect -502 -21 -486 77
+rect -155 -21 -140 77
+rect -502 -35 -140 -21
+<< locali >>
+rect -486 71 -155 77
+rect -486 54 -329 71
+rect -312 54 -155 71
+rect -486 37 -155 54
+rect -486 20 -448 37
+rect -431 20 -369 37
+rect -352 36 -290 37
+rect -352 20 -329 36
+rect -486 19 -329 20
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+rect -273 20 -211 37
+rect -194 20 -155 37
+rect -312 19 -155 20
+rect -486 2 -155 19
+rect -486 -15 -329 2
+rect -312 -15 -155 2
+rect -486 -21 -155 -15
+<< viali >>
+rect -329 54 -312 71
+rect -329 19 -312 36
+rect -329 -15 -312 2
+<< metal1 >>
+rect -333 71 -309 77
+rect -333 54 -329 71
+rect -312 54 -309 71
+rect -333 36 -309 54
+rect -333 19 -329 36
+rect -312 19 -309 36
+rect -333 13 -309 19
+rect -332 2 -309 13
+rect -332 -15 -329 2
+rect -312 -13 -309 2
+rect -312 -15 -308 -13
+rect -332 -35 -308 -15
+<< end >>
diff --git a/mag/sky130_hilas_pFETLarge.mag b/mag/sky130_hilas_pFETLarge.mag
new file mode 100644
index 0000000..eb71678
--- /dev/null
+++ b/mag/sky130_hilas_pFETLarge.mag
@@ -0,0 +1,204 @@
+magic
+tech sky130A
+timestamp 1608245216
+<< nwell >>
+rect 145 728 213 729
+rect 145 725 221 728
+rect 428 725 429 729
+rect 466 437 528 1007
+<< nsubdiff >>
+rect 484 970 510 989
+rect 484 953 489 970
+rect 506 953 510 970
+rect 484 936 510 953
+rect 484 919 489 936
+rect 506 919 510 936
+rect 484 907 510 919
+<< nsubdiffcont >>
+rect 489 953 506 970
+rect 489 919 506 936
+<< poly >>
+rect 126 1001 429 1018
+rect 126 729 145 1001
+rect 126 714 429 729
+rect 126 523 146 714
+rect 78 513 146 523
+rect 78 496 83 513
+rect 100 496 117 513
+rect 134 496 146 513
+rect 78 479 146 496
+rect 78 462 84 479
+rect 101 462 118 479
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+rect 78 447 146 462
+rect 78 445 428 447
+rect 78 428 84 445
+rect 101 428 118 445
+rect 135 430 428 445
+rect 135 428 161 430
+rect 78 423 161 428
+rect 78 420 147 423
+<< polycont >>
+rect 83 496 100 513
+rect 117 496 134 513
+rect 84 462 101 479
+rect 118 462 135 479
+rect 84 428 101 445
+rect 118 428 135 445
+<< locali >>
+rect 489 911 506 919
+rect 160 735 176 738
+rect 160 701 177 735
+rect 215 734 231 738
+rect 215 701 232 734
+rect 270 701 287 741
+rect 325 734 341 738
+rect 380 734 396 738
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+rect 83 495 134 496
+rect 83 488 135 495
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+rect 101 462 118 479
+rect 84 445 135 462
+rect 101 428 118 445
+rect 84 420 135 428
+<< viali >>
+rect 489 970 506 987
+rect 489 936 506 953
+<< metal1 >>
+rect 478 998 504 1018
+rect 478 987 509 998
+rect 478 970 489 987
+rect 506 970 509 987
+rect 478 953 509 970
+rect 478 936 489 953
+rect 506 936 509 953
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+rect 478 419 504 917
+<< metal2 >>
+rect 97 979 403 980
+rect 88 946 403 979
+rect 88 701 120 946
+rect 207 878 501 908
+rect 426 874 501 878
+rect 463 861 501 874
+rect 466 774 501 861
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+rect 88 668 404 701
+rect 88 564 120 668
+rect 88 532 404 564
+rect 64 420 124 502
+rect 466 497 501 741
+rect 207 465 501 497
+rect 207 464 478 465
+use sky130_hilas_li2m2 sky130_hilas_li2m2_8
+timestamp 1607089160
+transform 1 0 107 0 1 482
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_7
+timestamp 1607089160
+transform 1 0 108 0 1 435
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_9
+timestamp 1607089160
+transform 1 0 164 0 1 546
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_19
+timestamp 1607089160
+transform 1 0 439 0 1 479
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_17
+timestamp 1607089160
+transform 1 0 329 0 1 478
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_15
+timestamp 1607089160
+transform 1 0 220 0 1 478
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_6
+timestamp 1607089160
+transform 1 0 384 0 1 546
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_10
+timestamp 1607089160
+transform 1 0 274 0 1 546
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 164 0 1 683
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_2
+timestamp 1607089160
+transform 1 0 384 0 1 683
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 274 0 1 683
+box -14 -15 20 18
+use sky130_hilas_pFETLargePart1 sky130_hilas_pFETLargePart1_1
+timestamp 1607986851
+transform 1 0 142 0 1 446
+box -6 -9 333 278
+use sky130_hilas_li2m2 sky130_hilas_li2m2_5
+timestamp 1607089160
+transform 1 0 439 0 1 756
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_4
+timestamp 1607089160
+transform 1 0 220 0 1 756
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_3
+timestamp 1607089160
+transform 1 0 329 0 1 756
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_13
+timestamp 1607089160
+transform 1 0 440 0 1 890
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_12
+timestamp 1607089160
+transform 1 0 329 0 1 891
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_16
+timestamp 1607089160
+transform 1 0 220 0 1 893
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_11
+timestamp 1607089160
+transform 1 0 165 0 1 961
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_18
+timestamp 1607089160
+transform 1 0 384 0 1 960
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_14
+timestamp 1607089160
+transform 1 0 274 0 1 961
+box -14 -15 20 18
+use sky130_hilas_pFETLargePart1 sky130_hilas_pFETLargePart1_0
+timestamp 1607986851
+transform 1 0 142 0 1 729
+box -6 -9 333 278
+<< labels >>
+rlabel metal2 486 834 500 908 0 DRAIN
+port 3 nsew analog default
+rlabel metal2 88 905 102 979 0 SOURCE
+port 2 nsew analog default
+rlabel metal2 64 420 74 502 0 GATE
+port 1 nsew
+rlabel metal1 478 1010 504 1018 0 WELL
+port 4 nsew analog default
+rlabel metal1 478 419 504 427 0 WELL
+port 4 nsew analog default
+<< end >>
diff --git a/mag/sky130_hilas_pFETLargePart1.mag b/mag/sky130_hilas_pFETLargePart1.mag
new file mode 100644
index 0000000..3fefd41
--- /dev/null
+++ b/mag/sky130_hilas_pFETLargePart1.mag
@@ -0,0 +1,24 @@
+magic
+tech sky130A
+timestamp 1607986851
+use sky130_hilas_pFETmed sky130_hilas_pFETmed_2
+timestamp 1607969308
+transform 1 0 12 0 1 13
+box 147 -22 266 265
+use sky130_hilas_pFETmed sky130_hilas_pFETmed_1
+timestamp 1607969308
+transform 1 0 -43 0 1 13
+box 147 -22 266 265
+use sky130_hilas_pFETmed sky130_hilas_pFETmed_0
+timestamp 1607969308
+transform 1 0 -98 0 1 13
+box 147 -22 266 265
+use sky130_hilas_pFETmed sky130_hilas_pFETmed_4
+timestamp 1607969308
+transform 1 0 -153 0 1 13
+box 147 -22 266 265
+use sky130_hilas_pFETmed sky130_hilas_pFETmed_3
+timestamp 1607969308
+transform 1 0 67 0 1 13
+box 147 -22 266 265
+<< end >>
diff --git a/mag/sky130_hilas_pFETdevice01.mag b/mag/sky130_hilas_pFETdevice01.mag
new file mode 100644
index 0000000..e7088f2
--- /dev/null
+++ b/mag/sky130_hilas_pFETdevice01.mag
@@ -0,0 +1,33 @@
+magic
+tech sky130A
+timestamp 1607471549
+<< nwell >>
+rect -79 -78 82 43
+<< pmos >>
+rect -18 -19 21 20
+<< pdiff >>
+rect -45 9 -18 20
+rect -45 -8 -41 9
+rect -24 -8 -18 9
+rect -45 -19 -18 -8
+rect 21 9 48 20
+rect 21 -8 27 9
+rect 44 -8 48 9
+rect 21 -19 48 -8
+<< pdiffc >>
+rect -41 -8 -24 9
+rect 27 -8 44 9
+<< poly >>
+rect -79 18 -53 33
+rect -18 20 21 33
+rect -68 -27 -53 18
+rect -18 -27 21 -19
+rect -68 -42 71 -27
+rect 56 -63 71 -42
+rect 56 -78 82 -63
+<< locali >>
+rect -41 9 -24 17
+rect -41 -16 -24 -8
+rect 27 9 44 17
+rect 27 -16 44 -8
+<< end >>
diff --git a/mag/sky130_hilas_pFETdevice01a.mag b/mag/sky130_hilas_pFETdevice01a.mag
new file mode 100644
index 0000000..7efe26d
--- /dev/null
+++ b/mag/sky130_hilas_pFETdevice01a.mag
@@ -0,0 +1,17 @@
+magic
+tech sky130A
+timestamp 1607477942
+<< nwell >>
+rect -80 -42 81 43
+<< pmos >>
+rect -18 -19 21 20
+<< pdiff >>
+rect -46 -19 -18 20
+rect 21 -19 47 20
+<< poly >>
+rect -80 18 -54 33
+rect -18 20 21 33
+rect -69 -27 -54 18
+rect -18 -27 21 -19
+rect -69 -42 71 -27
+<< end >>
diff --git a/mag/sky130_hilas_pFETdevice01aa.mag b/mag/sky130_hilas_pFETdevice01aa.mag
new file mode 100644
index 0000000..8f0f1d1
--- /dev/null
+++ b/mag/sky130_hilas_pFETdevice01aa.mag
@@ -0,0 +1,19 @@
+magic
+tech sky130A
+timestamp 1607478455
+<< nwell >>
+rect -80 -78 81 43
+<< pmos >>
+rect -18 -19 21 20
+<< pdiff >>
+rect -46 -19 -18 20
+rect 21 -19 47 20
+<< poly >>
+rect -80 18 -54 33
+rect -18 20 21 33
+rect -69 -27 -54 18
+rect -18 -27 21 -19
+rect -69 -42 71 -27
+rect 56 -63 71 -42
+rect 56 -78 92 -63
+<< end >>
diff --git a/mag/sky130_hilas_pFETdevice01b.mag b/mag/sky130_hilas_pFETdevice01b.mag
new file mode 100644
index 0000000..34eb406
--- /dev/null
+++ b/mag/sky130_hilas_pFETdevice01b.mag
@@ -0,0 +1,23 @@
+magic
+tech sky130A
+timestamp 1607475333
+<< nwell >>
+rect -79 -78 82 43
+<< pmos >>
+rect -18 -19 21 20
+<< pdiff >>
+rect -45 -19 -18 20
+rect 21 -19 48 20
+<< poly >>
+rect -18 20 21 33
+rect -18 -27 21 -19
+rect -18 -42 71 -27
+rect 56 -63 71 -42
+rect 56 -78 108 -63
+rect 80 -79 85 -78
+rect 93 -90 108 -78
+use sky130_hilas_poly2m1 sky130_hilas_poly2m1_0
+timestamp 1607270135
+transform 1 0 81 0 1 -88
+box -9 -26 24 25
+<< end >>
diff --git a/mag/sky130_hilas_pFETdevice01ba.mag b/mag/sky130_hilas_pFETdevice01ba.mag
new file mode 100644
index 0000000..34eb406
--- /dev/null
+++ b/mag/sky130_hilas_pFETdevice01ba.mag
@@ -0,0 +1,23 @@
+magic
+tech sky130A
+timestamp 1607475333
+<< nwell >>
+rect -79 -78 82 43
+<< pmos >>
+rect -18 -19 21 20
+<< pdiff >>
+rect -45 -19 -18 20
+rect 21 -19 48 20
+<< poly >>
+rect -18 20 21 33
+rect -18 -27 21 -19
+rect -18 -42 71 -27
+rect 56 -63 71 -42
+rect 56 -78 108 -63
+rect 80 -79 85 -78
+rect 93 -90 108 -78
+use sky130_hilas_poly2m1 sky130_hilas_poly2m1_0
+timestamp 1607270135
+transform 1 0 81 0 1 -88
+box -9 -26 24 25
+<< end >>
diff --git a/mag/sky130_hilas_pFETdevice01c.mag b/mag/sky130_hilas_pFETdevice01c.mag
new file mode 100644
index 0000000..34eb406
--- /dev/null
+++ b/mag/sky130_hilas_pFETdevice01c.mag
@@ -0,0 +1,23 @@
+magic
+tech sky130A
+timestamp 1607475333
+<< nwell >>
+rect -79 -78 82 43
+<< pmos >>
+rect -18 -19 21 20
+<< pdiff >>
+rect -45 -19 -18 20
+rect 21 -19 48 20
+<< poly >>
+rect -18 20 21 33
+rect -18 -27 21 -19
+rect -18 -42 71 -27
+rect 56 -63 71 -42
+rect 56 -78 108 -63
+rect 80 -79 85 -78
+rect 93 -90 108 -78
+use sky130_hilas_poly2m1 sky130_hilas_poly2m1_0
+timestamp 1607270135
+transform 1 0 81 0 1 -88
+box -9 -26 24 25
+<< end >>
diff --git a/mag/sky130_hilas_pFETdevice01d.mag b/mag/sky130_hilas_pFETdevice01d.mag
new file mode 100644
index 0000000..8ae205d
--- /dev/null
+++ b/mag/sky130_hilas_pFETdevice01d.mag
@@ -0,0 +1,39 @@
+magic
+tech sky130A
+timestamp 1607475773
+<< nwell >>
+rect -79 -78 82 43
+<< pmos >>
+rect -18 -19 21 20
+<< pdiff >>
+rect -45 9 -18 20
+rect -45 -8 -41 9
+rect -24 -8 -18 9
+rect -45 -19 -18 -8
+rect 21 9 48 20
+rect 21 -8 27 9
+rect 44 -8 48 9
+rect 21 -19 48 -8
+<< pdiffc >>
+rect -41 -8 -24 9
+rect 27 -8 44 9
+<< poly >>
+rect -18 20 21 33
+rect -18 -27 21 -19
+rect -18 -42 72 -27
+rect 56 -76 72 -42
+rect 57 -84 59 -76
+<< locali >>
+rect -41 9 -24 17
+rect -41 -16 -24 -8
+rect 27 9 44 17
+rect 27 -16 44 -8
+use sky130_hilas_poly2m1 sky130_hilas_poly2m1_2
+timestamp 1607270135
+transform 1 0 68 0 -1 -77
+box -9 -26 24 25
+use sky130_hilas_poly2m1 sky130_hilas_poly2m1_0
+timestamp 1607270135
+transform 1 0 -83 0 1 7
+box -9 -26 24 25
+<< end >>
diff --git a/mag/sky130_hilas_pFETdevice01e.mag b/mag/sky130_hilas_pFETdevice01e.mag
new file mode 100644
index 0000000..df415c4
--- /dev/null
+++ b/mag/sky130_hilas_pFETdevice01e.mag
@@ -0,0 +1,47 @@
+magic
+tech sky130A
+timestamp 1608055794
+<< nwell >>
+rect -121 -55 82 44
+<< pmos >>
+rect -18 -19 21 20
+<< pdiff >>
+rect -46 9 -18 20
+rect -46 -8 -41 9
+rect -24 -8 -18 9
+rect -46 -19 -18 -8
+rect 21 9 48 20
+rect 21 -8 27 9
+rect 44 -8 48 9
+rect 21 -19 48 -8
+<< pdiffc >>
+rect -41 -8 -24 9
+rect 27 -8 44 9
+<< poly >>
+rect -18 20 21 33
+rect -80 -27 -54 -19
+rect -18 -27 21 -19
+rect -80 -42 21 -27
+<< locali >>
+rect -55 9 -24 17
+rect -55 -1 -41 9
+rect -57 -3 -41 -1
+rect -41 -16 -24 -8
+rect 27 9 44 17
+rect 27 -16 44 -8
+<< metal2 >>
+rect -121 -3 -84 16
+rect -121 -45 -83 -26
+use sky130_hilas_poly2m2 sky130_hilas_poly2m2_0
+timestamp 1607270276
+transform 0 1 -84 -1 0 -28
+box -9 -26 24 29
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 -73 0 1 9
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 57 0 1 -1
+box -14 -15 20 18
+<< end >>
diff --git a/mag/sky130_hilas_pFETmed.mag b/mag/sky130_hilas_pFETmed.mag
new file mode 100644
index 0000000..cbeba70
--- /dev/null
+++ b/mag/sky130_hilas_pFETmed.mag
@@ -0,0 +1,88 @@
+magic
+tech sky130A
+timestamp 1607969308
+<< nwell >>
+rect 147 -22 266 265
+<< pmos >>
+rect 194 -4 220 247
+<< pdiff >>
+rect 165 223 194 247
+rect 165 206 171 223
+rect 188 206 194 223
+rect 165 189 194 206
+rect 165 172 171 189
+rect 188 172 194 189
+rect 165 155 194 172
+rect 165 138 171 155
+rect 188 138 194 155
+rect 165 121 194 138
+rect 165 104 171 121
+rect 188 104 194 121
+rect 165 87 194 104
+rect 165 70 171 87
+rect 188 70 194 87
+rect 165 53 194 70
+rect 165 36 171 53
+rect 188 36 194 53
+rect 165 19 194 36
+rect 165 2 171 19
+rect 188 2 194 19
+rect 165 -4 194 2
+rect 220 223 248 247
+rect 220 206 226 223
+rect 243 206 248 223
+rect 220 189 248 206
+rect 220 172 226 189
+rect 243 172 248 189
+rect 220 155 248 172
+rect 220 138 226 155
+rect 243 138 248 155
+rect 220 121 248 138
+rect 220 104 226 121
+rect 243 104 248 121
+rect 220 87 248 104
+rect 220 70 226 87
+rect 243 70 248 87
+rect 220 53 248 70
+rect 220 36 226 53
+rect 243 36 248 53
+rect 220 19 248 36
+rect 220 2 226 19
+rect 243 2 248 19
+rect 220 -4 248 2
+<< pdiffc >>
+rect 171 206 188 223
+rect 171 172 188 189
+rect 171 138 188 155
+rect 171 104 188 121
+rect 171 70 188 87
+rect 171 36 188 53
+rect 171 2 188 19
+rect 226 206 243 223
+rect 226 172 243 189
+rect 226 138 243 155
+rect 226 104 243 121
+rect 226 70 243 87
+rect 226 36 243 53
+rect 226 2 243 19
+<< poly >>
+rect 194 247 220 260
+rect 194 -17 220 -4
+<< locali >>
+rect 171 223 188 242
+rect 171 189 188 206
+rect 171 155 188 172
+rect 171 121 188 138
+rect 171 87 188 104
+rect 171 53 188 70
+rect 171 19 188 36
+rect 171 -7 188 2
+rect 226 223 243 242
+rect 226 189 243 206
+rect 226 155 243 172
+rect 226 121 243 138
+rect 226 87 243 104
+rect 226 53 243 70
+rect 226 19 243 36
+rect 226 -8 243 2
+<< end >>
diff --git a/mag/sky130_hilas_pFETmirror.mag b/mag/sky130_hilas_pFETmirror.mag
new file mode 100644
index 0000000..1f01d25
--- /dev/null
+++ b/mag/sky130_hilas_pFETmirror.mag
@@ -0,0 +1,92 @@
+magic
+tech sky130A
+timestamp 1607184666
+<< nwell >>
+rect -61 112 158 285
+<< pmos >>
+rect -40 164 28 194
+rect 64 164 132 194
+<< pdiff >>
+rect -40 218 28 224
+rect -40 201 -32 218
+rect -14 201 4 218
+rect 22 201 28 218
+rect -40 194 28 201
+rect 64 218 132 224
+rect 64 201 72 218
+rect 90 201 109 218
+rect 128 201 132 218
+rect 64 194 132 201
+rect -40 157 28 164
+rect -40 140 -32 157
+rect -14 140 4 157
+rect 22 140 28 157
+rect -40 131 28 140
+rect 64 157 132 164
+rect 64 140 70 157
+rect 88 140 106 157
+rect 124 140 132 157
+rect 64 136 132 140
+rect 71 131 132 136
+<< pdiffc >>
+rect -32 201 -14 218
+rect 4 201 22 218
+rect 72 201 90 218
+rect 109 201 128 218
+rect -32 140 -14 157
+rect 4 140 22 157
+rect 70 140 88 157
+rect 106 140 124 157
+<< nsubdiff >>
+rect -40 253 28 265
+rect -40 236 -32 253
+rect -14 236 4 253
+rect 22 236 28 253
+rect -40 224 28 236
+rect 64 253 132 265
+rect 64 236 72 253
+rect 90 236 109 253
+rect 128 236 132 253
+rect 64 224 132 236
+<< nsubdiffcont >>
+rect -32 236 -14 253
+rect 4 236 22 253
+rect 72 236 90 253
+rect 109 236 128 253
+<< poly >>
+rect -53 164 -40 194
+rect 28 164 64 194
+rect 132 164 145 194
+rect 36 120 53 164
+rect 30 112 57 120
+rect 30 95 35 112
+rect 52 95 57 112
+rect 30 87 57 95
+<< polycont >>
+rect 35 95 52 112
+<< locali >>
+rect -40 236 -32 253
+rect -14 236 4 253
+rect 22 236 72 253
+rect 90 236 109 253
+rect 128 236 136 253
+rect -40 218 136 236
+rect -40 201 -32 218
+rect -14 201 4 218
+rect 22 201 72 218
+rect 90 201 109 218
+rect 128 201 136 218
+rect -40 140 -32 157
+rect -14 140 4 157
+rect 22 140 31 157
+rect 62 140 70 157
+rect 88 140 106 157
+rect 124 140 132 157
+rect -5 123 31 140
+rect -5 112 60 123
+rect -5 95 35 112
+rect 52 95 60 112
+rect -5 87 60 95
+rect -5 82 22 87
+rect 85 82 110 140
+<< end >>
diff --git a/mag/sky130_hilas_pFETmirror02.mag b/mag/sky130_hilas_pFETmirror02.mag
new file mode 100644
index 0000000..2c8ef09
--- /dev/null
+++ b/mag/sky130_hilas_pFETmirror02.mag
@@ -0,0 +1,79 @@
+magic
+tech sky130A
+timestamp 1607207238
+<< nwell >>
+rect -61 89 67 373
+<< pmos >>
+rect -40 295 28 325
+rect -40 164 28 194
+<< pdiff >>
+rect -40 349 28 354
+rect -40 331 -33 349
+rect -15 331 3 349
+rect 21 331 28 349
+rect -40 325 28 331
+rect -40 289 28 295
+rect -40 271 -32 289
+rect -15 271 4 289
+rect 22 271 28 289
+rect -40 265 28 271
+rect -40 218 28 224
+rect -40 201 -32 218
+rect -14 201 4 218
+rect 22 201 28 218
+rect -40 194 28 201
+rect -40 157 28 164
+rect -40 140 -32 157
+rect -14 140 4 157
+rect 22 140 28 157
+rect -40 131 28 140
+<< pdiffc >>
+rect -33 331 -15 349
+rect 3 331 21 349
+rect -32 271 -15 289
+rect 4 271 22 289
+rect -32 201 -14 218
+rect 4 201 22 218
+rect -32 140 -14 157
+rect 4 140 22 157
+<< nsubdiff >>
+rect -40 253 28 265
+rect -40 236 -32 253
+rect -14 236 4 253
+rect 22 236 28 253
+rect -40 224 28 236
+<< nsubdiffcont >>
+rect -32 236 -14 253
+rect 4 236 22 253
+<< poly >>
+rect -53 295 -40 325
+rect 28 295 53 325
+rect 36 194 53 295
+rect -53 164 -40 194
+rect 28 164 53 194
+rect 36 112 53 164
+<< locali >>
+rect -41 331 -33 349
+rect -15 331 3 349
+rect 21 331 29 349
+rect -40 271 -32 289
+rect -15 271 4 289
+rect 22 271 30 289
+rect -40 253 30 271
+rect -40 236 -32 253
+rect -14 236 4 253
+rect 22 236 30 253
+rect -40 218 30 236
+rect -40 201 -32 218
+rect -14 201 4 218
+rect 22 201 30 218
+rect -40 140 -32 157
+rect -14 140 4 157
+rect 22 140 31 157
+rect -5 112 31 140
+rect -5 95 28 112
+use sky130_hilas_poly2li sky130_hilas_poly2li_0
+timestamp 1607178257
+transform 0 1 34 -1 0 108
+box -9 -14 18 19
+<< end >>
diff --git a/mag/sky130_hilas_pTransistorPair.mag b/mag/sky130_hilas_pTransistorPair.mag
new file mode 100644
index 0000000..bf0b1f9
--- /dev/null
+++ b/mag/sky130_hilas_pTransistorPair.mag
@@ -0,0 +1,67 @@
+magic
+tech sky130A
+timestamp 1608384750
+<< nwell >>
+rect 133 -140 319 -133
+rect 267 -169 312 -146
+<< poly >>
+rect 225 -104 248 -100
+rect 227 -407 248 -406
+<< locali >>
+rect 279 -70 301 -61
+rect 279 -78 287 -70
+rect 174 -192 192 -86
+rect 247 -133 252 -120
+rect 235 -146 252 -133
+rect 272 -352 279 -350
+rect 272 -366 280 -352
+rect 249 -435 256 -409
+<< metal1 >>
+rect 283 -265 304 -88
+<< metal2 >>
+rect 225 -169 312 -146
+rect 225 -170 268 -169
+rect 273 -249 320 -224
+rect 255 -352 310 -327
+rect 201 -438 289 -413
+use sky130_hilas_m12m2 sky130_hilas_m12m2_0
+timestamp 1607949437
+transform 1 0 287 0 1 -244
+box -9 -10 23 22
+use sky130_hilas_li2m2 sky130_hilas_li2m2_2
+timestamp 1607089160
+transform -1 0 290 0 -1 -338
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_1
+timestamp 1607089160
+transform 1 0 248 0 1 -159
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_3
+timestamp 1607089160
+transform -1 0 275 0 -1 -421
+box -14 -15 20 18
+use sky130_hilas_li2m2 sky130_hilas_li2m2_0
+timestamp 1607089160
+transform 1 0 175 0 1 -287
+box -14 -15 20 18
+use sky130_hilas_pTransistorVert01 sky130_hilas_pTransistorVert01_1
+timestamp 1607343381
+transform 1 0 496 0 1 5
+box -363 -444 -177 -145
+use sky130_hilas_poly2li sky130_hilas_poly2li_1
+timestamp 1607178257
+transform 1 0 236 0 1 -426
+box -9 -14 18 19
+use sky130_hilas_poly2li sky130_hilas_poly2li_0
+timestamp 1607178257
+transform 1 0 234 0 1 -123
+box -9 -14 18 19
+use sky130_hilas_li2m1 sky130_hilas_li2m1_0
+timestamp 1607179295
+transform 1 0 291 0 1 -85
+box -10 -8 13 21
+use sky130_hilas_pTransistorVert01 sky130_hilas_pTransistorVert01_0
+timestamp 1607343381
+transform 1 0 496 0 1 310
+box -363 -444 -177 -145
+<< end >>
diff --git a/mag/sky130_hilas_pTransistorVert01.mag b/mag/sky130_hilas_pTransistorVert01.mag
new file mode 100644
index 0000000..ee68066
--- /dev/null
+++ b/mag/sky130_hilas_pTransistorVert01.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+timestamp 1607343381
+<< nwell >>
+rect -363 -444 -177 -145
+<< mvpmos >>
+rect -298 -396 -248 -193
+<< mvpdiff >>
+rect -329 -200 -298 -193
+rect -329 -217 -322 -200
+rect -305 -217 -298 -200
+rect -329 -234 -298 -217
+rect -329 -251 -322 -234
+rect -305 -251 -298 -234
+rect -329 -268 -298 -251
+rect -329 -285 -322 -268
+rect -305 -285 -298 -268
+rect -329 -302 -298 -285
+rect -329 -319 -322 -302
+rect -305 -319 -298 -302
+rect -329 -336 -298 -319
+rect -329 -353 -322 -336
+rect -305 -353 -298 -336
+rect -329 -370 -298 -353
+rect -329 -387 -322 -370
+rect -305 -387 -298 -370
+rect -329 -396 -298 -387
+rect -248 -201 -210 -193
+rect -248 -218 -241 -201
+rect -224 -218 -210 -201
+rect -248 -235 -210 -218
+rect -248 -252 -241 -235
+rect -224 -252 -210 -235
+rect -248 -269 -210 -252
+rect -248 -286 -241 -269
+rect -224 -286 -210 -269
+rect -248 -303 -210 -286
+rect -248 -320 -241 -303
+rect -224 -320 -210 -303
+rect -248 -337 -210 -320
+rect -248 -354 -241 -337
+rect -224 -354 -210 -337
+rect -248 -371 -210 -354
+rect -248 -388 -241 -371
+rect -224 -388 -210 -371
+rect -248 -396 -210 -388
+<< mvpdiffc >>
+rect -322 -217 -305 -200
+rect -322 -251 -305 -234
+rect -322 -285 -305 -268
+rect -322 -319 -305 -302
+rect -322 -353 -305 -336
+rect -322 -387 -305 -370
+rect -241 -218 -224 -201
+rect -241 -252 -224 -235
+rect -241 -286 -224 -269
+rect -241 -320 -224 -303
+rect -241 -354 -224 -337
+rect -241 -388 -224 -371
+<< poly >>
+rect -298 -193 -248 -175
+rect -298 -411 -248 -396
+<< locali >>
+rect -322 -200 -304 -192
+rect -305 -217 -304 -200
+rect -322 -234 -304 -217
+rect -305 -251 -304 -234
+rect -322 -268 -304 -251
+rect -305 -285 -304 -268
+rect -322 -302 -304 -285
+rect -305 -319 -304 -302
+rect -322 -336 -304 -319
+rect -305 -353 -304 -336
+rect -322 -370 -304 -353
+rect -305 -387 -304 -370
+rect -241 -201 -224 -193
+rect -241 -235 -224 -218
+rect -241 -269 -224 -252
+rect -241 -303 -224 -286
+rect -241 -337 -224 -320
+rect -241 -371 -224 -354
+rect -322 -397 -304 -387
+rect -249 -388 -241 -371
+rect -224 -388 -216 -371
+<< end >>
diff --git a/mag/sky130_hilas_poly2li.mag b/mag/sky130_hilas_poly2li.mag
new file mode 100644
index 0000000..d45feba
--- /dev/null
+++ b/mag/sky130_hilas_poly2li.mag
@@ -0,0 +1,14 @@
+magic
+tech sky130A
+timestamp 1607178257
+<< poly >>
+rect -9 11 18 19
+rect -9 -6 -4 11
+rect 13 -6 18 11
+rect -9 -14 18 -6
+<< polycont >>
+rect -4 -6 13 11
+<< locali >>
+rect -4 11 13 19
+rect -4 -14 13 -6
+<< end >>
diff --git a/mag/sky130_hilas_poly2m1.mag b/mag/sky130_hilas_poly2m1.mag
new file mode 100644
index 0000000..fdae0be
--- /dev/null
+++ b/mag/sky130_hilas_poly2m1.mag
@@ -0,0 +1,26 @@
+magic
+tech sky130A
+timestamp 1607270135
+<< poly >>
+rect -9 17 24 25
+rect -9 0 -1 17
+rect 16 0 24 17
+rect -9 -8 24 0
+<< polycont >>
+rect -1 0 16 17
+<< locali >>
+rect -3 17 18 25
+rect -3 0 -1 17
+rect 16 0 18 17
+rect -3 -3 18 0
+rect -3 -18 -1 -3
+rect 16 -18 18 -3
+<< viali >>
+rect -1 -20 16 -3
+<< metal1 >>
+rect -3 3 19 25
+rect -4 -3 19 3
+rect -4 -20 -1 -3
+rect 16 -20 19 -3
+rect -4 -26 19 -20
+<< end >>
diff --git a/mag/sky130_hilas_poly2m2.mag b/mag/sky130_hilas_poly2m2.mag
new file mode 100644
index 0000000..c2abe28
--- /dev/null
+++ b/mag/sky130_hilas_poly2m2.mag
@@ -0,0 +1,35 @@
+magic
+tech sky130A
+timestamp 1607270276
+<< poly >>
+rect -9 17 24 25
+rect -9 0 -1 17
+rect 16 0 24 17
+rect -9 -8 24 0
+<< polycont >>
+rect -1 0 16 17
+<< locali >>
+rect -3 17 18 25
+rect -3 0 -1 17
+rect 16 0 18 17
+rect -3 -3 18 0
+rect -3 -18 -1 -3
+rect 16 -18 18 -3
+<< viali >>
+rect -1 -20 16 -3
+<< metal1 >>
+rect -8 26 24 29
+rect -8 0 -5 26
+rect 21 0 24 26
+rect -8 -3 24 0
+rect -4 -20 -1 -3
+rect 16 -20 19 -3
+rect -4 -26 19 -20
+<< via1 >>
+rect -5 0 21 26
+<< metal2 >>
+rect -8 26 24 29
+rect -8 0 -5 26
+rect 21 0 24 26
+rect -8 -3 24 0
+<< end >>
diff --git a/mag/sky130_hilas_polyresistorGND.mag b/mag/sky130_hilas_polyresistorGND.mag
new file mode 100644
index 0000000..4e6daa9
--- /dev/null
+++ b/mag/sky130_hilas_polyresistorGND.mag
@@ -0,0 +1,234 @@
+magic
+tech sky130A
+timestamp 1626558701
+<< psubdiff >>
+rect -2715 816 2607 820
+rect -2715 799 -2677 816
+rect 2586 799 2607 816
+rect -2715 796 2607 799
+rect -2715 793 -2691 796
+rect -2715 33 -2711 793
+rect -2694 33 -2691 793
+rect 2742 794 2766 820
+rect -2715 17 -2691 33
+rect 2742 85 2746 794
+rect 2763 85 2766 794
+rect 2742 65 2766 85
+<< psubdiffcont >>
+rect -2677 799 2586 816
+rect -2711 33 -2694 793
+rect 2746 85 2763 794
+<< poly >>
+rect -642 959 -593 968
+rect -642 942 -632 959
+rect -615 942 -593 959
+rect -642 925 -593 942
+rect -642 908 -632 925
+rect -615 908 -593 925
+rect -642 891 -593 908
+rect -642 874 -632 891
+rect -615 874 -593 891
+rect -642 857 -593 874
+rect -642 840 -632 857
+rect -615 840 -593 857
+rect -642 833 -593 840
+rect 5 963 70 968
+rect 5 946 43 963
+rect 60 946 70 963
+rect 5 929 70 946
+rect 5 912 43 929
+rect 60 912 70 929
+rect 5 895 70 912
+rect 5 878 43 895
+rect 60 878 70 895
+rect 5 861 70 878
+rect 5 844 43 861
+rect 60 844 70 861
+rect 5 833 70 844
+rect 2621 812 2727 818
+rect 2621 795 2630 812
+rect 2718 795 2727 812
+rect 2621 788 2727 795
+rect -2682 772 2727 788
+rect -2682 746 -2666 772
+rect 2621 771 2727 772
+rect -2682 730 2730 746
+rect -2682 704 -2666 705
+rect 2714 704 2730 730
+rect -2682 688 2730 704
+rect -2682 665 -2666 688
+rect -2682 649 2730 665
+rect 2714 624 2730 649
+rect -2682 608 2730 624
+rect -2682 586 -2666 608
+rect -2682 570 2730 586
+rect -2682 547 -2666 548
+rect 2714 547 2730 570
+rect -2682 531 2730 547
+rect -2682 507 -2666 531
+rect -2682 491 2730 507
+rect -2682 469 -2666 470
+rect 2714 469 2730 491
+rect -2682 453 2730 469
+rect -2682 427 -2666 453
+rect -2682 411 2730 427
+rect 2714 386 2730 411
+rect -2682 370 2730 386
+rect -2682 349 -2667 370
+rect -2682 333 2730 349
+rect 2714 311 2730 333
+rect -2682 295 2730 311
+rect -2682 273 -2666 295
+rect -2682 257 2730 273
+rect 2714 234 2730 257
+rect -2682 218 2730 234
+rect -2682 196 -2666 218
+rect -2682 180 2730 196
+rect 2714 158 2730 180
+rect -2680 142 2730 158
+rect -2680 121 -2664 142
+rect -2680 105 2731 121
+rect 2715 84 2731 105
+rect -2677 68 2731 84
+rect -2677 46 -2661 68
+rect -2677 30 2730 46
+rect 2714 7 2730 30
+rect -62 -1 2730 7
+rect -67 -18 -50 -1
+rect -33 -18 -16 -1
+rect 1 -18 18 -1
+rect 35 -18 52 -1
+rect 69 -18 86 -1
+rect 103 -18 120 -1
+rect 137 -9 2730 -1
+rect 137 -18 174 -9
+rect -62 -27 174 -18
+<< polycont >>
+rect -632 942 -615 959
+rect -632 908 -615 925
+rect -632 874 -615 891
+rect -632 840 -615 857
+rect 43 946 60 963
+rect 43 912 60 929
+rect 43 878 60 895
+rect 43 844 60 861
+rect 2630 795 2718 812
+rect -50 -18 -33 -1
+rect -16 -18 1 -1
+rect 18 -18 35 -1
+rect 52 -18 69 -1
+rect 86 -18 103 -1
+rect 120 -18 137 -1
+<< npolyres >>
+rect -593 832 5 968
+<< locali >>
+rect -635 959 -613 967
+rect -635 855 -632 959
+rect -640 840 -632 855
+rect -615 855 -613 959
+rect 39 963 63 971
+rect -615 840 -607 855
+rect -640 836 -607 840
+rect 39 844 43 963
+rect 60 844 63 963
+rect 39 836 63 844
+rect -2711 799 -2677 816
+rect 2586 812 2763 816
+rect 2586 799 2630 812
+rect -2711 795 2630 799
+rect -2711 793 -2677 795
+rect -2694 778 -2677 793
+rect -287 789 601 795
+rect -287 778 -277 789
+rect -2694 776 -277 778
+rect 592 778 601 789
+rect 2718 794 2763 812
+rect 2718 778 2746 794
+rect 592 776 2746 778
+rect 2746 68 2763 85
+rect -2711 16 -2694 33
+<< viali >>
+rect -632 925 -615 942
+rect -632 891 -615 908
+rect -632 857 -615 874
+rect 43 929 60 946
+rect 43 895 60 912
+rect 43 861 60 878
+rect -2677 778 -287 795
+rect 601 778 2718 795
+rect -67 -18 -50 -1
+rect -33 -18 -16 -1
+rect 1 -18 18 -1
+rect 35 -18 52 -1
+rect 69 -18 86 -1
+rect 103 -18 120 -1
+rect 137 -18 154 -1
+<< metal1 >>
+rect -643 968 -402 1032
+rect -641 942 -600 968
+rect -641 925 -632 942
+rect -615 925 -600 942
+rect -641 908 -600 925
+rect -641 891 -632 908
+rect -615 891 -600 908
+rect -641 874 -600 891
+rect 32 946 73 979
+rect 32 929 43 946
+rect 60 929 73 946
+rect 32 912 73 929
+rect 32 895 43 912
+rect 60 895 73 912
+rect 32 878 73 895
+rect 32 875 43 878
+rect -641 857 -632 874
+rect -615 857 -600 874
+rect -641 833 -600 857
+rect -62 861 43 875
+rect 60 875 73 878
+rect 60 861 174 875
+rect -2716 814 -279 816
+rect -2722 810 -279 814
+rect -2722 795 -2667 810
+rect -2722 778 -2677 795
+rect -287 778 -279 810
+rect -2722 775 -279 778
+rect -2722 -50 -2681 775
+rect -62 25 174 861
+rect 601 815 2630 816
+rect 595 814 2630 815
+rect 595 810 2724 814
+rect 595 778 601 810
+rect 2687 795 2724 810
+rect 2718 778 2724 795
+rect 595 776 2724 778
+rect 595 775 2721 776
+rect -74 -1 174 25
+rect -74 -18 -67 -1
+rect -50 -18 -33 -1
+rect -16 -18 1 -1
+rect 18 -18 35 -1
+rect 52 -18 69 -1
+rect 86 -18 103 -1
+rect 120 -18 137 -1
+rect 154 -18 174 -1
+rect -74 -57 174 -18
+<< via1 >>
+rect -2667 795 -287 810
+rect -2667 784 -287 795
+rect 601 795 2687 810
+rect 601 784 2687 795
+<< metal2 >>
+rect -2749 810 2798 820
+rect -2749 784 -2667 810
+rect -287 784 601 810
+rect 2687 784 2798 810
+rect -2749 681 2798 784
+rect -2749 51 2798 191
+<< labels >>
+rlabel metal1 -642 983 -404 1022 0 INPUT
+port 2 nsew
+rlabel metal1 -74 -57 174 -30 0 OUTPUT
+port 3 nsew
+rlabel metal1 -2722 -50 -2681 -39 0 VGND
+port 4 nsew
+<< end >>
diff --git a/mag/sky130_hilas_resistor01.mag b/mag/sky130_hilas_resistor01.mag
new file mode 100644
index 0000000..f369d0a
--- /dev/null
+++ b/mag/sky130_hilas_resistor01.mag
@@ -0,0 +1,55 @@
+magic
+tech sky130A
+timestamp 1626535775
+<< psubdiff >>
+rect -131 148 491 156
+rect -131 131 -116 148
+rect -99 131 491 148
+rect -131 124 491 131
+<< psubdiffcont >>
+rect -116 131 -99 148
+<< poly >>
+rect -119 193 -75 206
+rect -119 176 -106 193
+rect -89 176 -75 193
+rect -119 164 -75 176
+rect 438 195 484 206
+rect 438 178 453 195
+rect 470 178 487 195
+rect 438 164 484 178
+<< polycont >>
+rect -106 176 -89 193
+rect 453 178 470 195
+<< npolyres >>
+rect -75 164 438 206
+<< locali >>
+rect -89 176 -81 193
+rect 445 178 453 195
+rect 445 176 487 178
+rect -127 131 -116 148
+<< viali >>
+rect -123 176 -106 193
+rect 470 178 487 195
+rect -99 131 -82 148
+<< metal1 >>
+rect -143 193 -86 198
+rect -143 176 -123 193
+rect -106 176 -86 193
+rect -143 171 -86 176
+rect 453 195 506 201
+rect 453 178 470 195
+rect 487 178 506 195
+rect 453 171 506 178
+rect -102 148 -76 151
+rect -128 144 -99 148
+rect -143 131 -99 144
+rect -82 131 -76 148
+rect -143 128 -76 131
+<< labels >>
+rlabel metal1 -142 171 -133 198 0 TERM1
+port 1 nsew
+rlabel metal1 494 171 506 201 0 TERM2
+port 2 nsew
+rlabel metal1 -143 128 -134 144 0 VGND
+port 3 nsew
+<< end >>
diff --git a/mag/sky130_hilas_swc2x2varactor.mag b/mag/sky130_hilas_swc2x2varactor.mag
new file mode 100644
index 0000000..177b16f
--- /dev/null
+++ b/mag/sky130_hilas_swc2x2varactor.mag
@@ -0,0 +1,250 @@
+magic
+tech sky130A
+timestamp 1606663783
+<< error_p >>
+rect -1466 227 -1381 259
+rect -1393 135 -1387 141
+rect -1341 135 -1335 141
+rect -1399 77 -1393 83
+rect -1335 77 -1329 83
+rect -869 77 -863 83
+rect -820 77 -814 83
+rect -772 54 -769 77
+rect -1393 25 -1387 31
+rect -1341 25 -1335 31
+rect -875 4 -869 10
+rect -814 4 -808 10
+rect -772 4 -769 27
+rect -324 16 -298 238
+rect -1399 -32 -1393 -26
+rect -1335 -32 -1329 -26
+rect -873 -51 -872 -47
+rect -873 -72 -867 -66
+rect -820 -72 -814 -66
+rect -1393 -83 -1387 -77
+rect -1341 -83 -1335 -77
+rect -1400 -133 -1393 -127
+rect -1335 -133 -1329 -127
+rect -879 -147 -873 -141
+rect -814 -147 -808 -141
+rect -471 -175 -451 -167
+rect -1394 -183 -1388 -177
+rect -1341 -183 -1335 -177
+rect -1400 -233 -1394 -227
+rect -1335 -233 -1329 -227
+rect -900 -244 -875 -223
+rect -900 -248 -869 -244
+rect -806 -248 -800 -242
+rect -900 -275 -875 -248
+rect -1394 -283 -1388 -277
+rect -1341 -283 -1335 -277
+rect -1400 -333 -1394 -327
+rect -1335 -333 -1329 -327
+rect -884 -362 -875 -344
+rect -866 -362 -865 -361
+rect -800 -362 -794 -356
+rect -778 -362 -775 -250
+rect -916 -364 -875 -362
+rect -867 -363 -775 -362
+rect -866 -364 -775 -363
+rect -891 -387 -875 -364
+rect -521 -408 -491 -407
+rect -554 -441 -507 -440
+rect -425 -442 -423 -356
+<< nwell >>
+rect -1466 175 -1275 227
+rect -1465 -440 -1275 175
+rect -992 26 -713 224
+rect -994 -253 -712 26
+rect -990 -440 -712 -253
+rect -572 -440 -425 226
+rect -324 17 2 238
+rect -324 16 -2 17
+rect -507 -442 -425 -440
+<< mvpmos >>
+rect -521 116 -491 166
+rect -222 143 -172 173
+rect -222 81 -172 112
+rect -150 81 -100 112
+rect -521 -21 -491 30
+rect -521 -94 -491 -42
+rect -521 -175 -491 -123
+rect -521 -246 -491 -196
+rect -521 -381 -491 -331
+<< mvvaractor >>
+rect -1393 77 -1335 135
+rect -1393 -32 -1335 25
+rect -869 4 -814 77
+rect -1393 -133 -1335 -83
+rect -873 -147 -814 -72
+rect -1394 -233 -1335 -183
+rect -1394 -333 -1335 -283
+rect -875 -362 -800 -248
+rect -875 -364 -866 -362
+<< mvpdiff >>
+rect -521 189 -491 193
+rect -521 172 -515 189
+rect -497 172 -491 189
+rect -521 166 -491 172
+rect -256 167 -222 173
+rect -256 150 -247 167
+rect -229 150 -222 167
+rect -256 143 -222 150
+rect -172 166 -141 173
+rect -172 149 -165 166
+rect -146 149 -141 166
+rect -172 143 -141 149
+rect -521 110 -491 116
+rect -521 93 -515 110
+rect -497 93 -491 110
+rect -521 88 -491 93
+rect -256 105 -222 112
+rect -256 88 -247 105
+rect -229 88 -222 105
+rect -256 81 -222 88
+rect -172 81 -150 112
+rect -100 105 -66 112
+rect -100 88 -93 105
+rect -73 88 -66 105
+rect -100 81 -66 88
+rect -521 53 -491 58
+rect -521 36 -515 53
+rect -497 36 -491 53
+rect -521 30 -491 36
+rect -521 -42 -491 -21
+rect -521 -100 -491 -94
+rect -521 -117 -515 -100
+rect -497 -117 -491 -100
+rect -521 -123 -491 -117
+rect -521 -196 -491 -175
+rect -521 -252 -491 -246
+rect -521 -269 -515 -252
+rect -497 -269 -491 -252
+rect -521 -273 -491 -269
+rect -521 -308 -491 -304
+rect -521 -325 -515 -308
+rect -497 -325 -491 -308
+rect -521 -331 -491 -325
+rect -521 -387 -491 -381
+rect -521 -404 -515 -387
+rect -497 -404 -491 -387
+rect -521 -408 -491 -404
+<< mvpdiffc >>
+rect -515 172 -497 189
+rect -247 150 -229 167
+rect -165 149 -146 166
+rect -515 93 -497 110
+rect -247 88 -229 105
+rect -93 88 -73 105
+rect -515 36 -497 53
+rect -515 -117 -497 -100
+rect -515 -269 -497 -252
+rect -515 -325 -497 -308
+rect -515 -404 -497 -387
+<< psubdiff >>
+rect -656 -361 -630 -349
+rect -656 -378 -652 -361
+rect -634 -378 -630 -361
+rect -656 -390 -630 -378
+<< mvnsubdiff >>
+rect -1393 135 -1335 182
+rect -869 77 -814 191
+rect -1393 25 -1335 77
+rect -100 183 -67 187
+rect -100 169 -66 183
+rect -100 151 -93 169
+rect -73 151 -66 169
+rect -100 139 -66 151
+rect -1393 -83 -1335 -32
+rect -869 -43 -814 4
+rect -872 -51 -814 -43
+rect -873 -72 -814 -51
+rect -1394 -183 -1335 -133
+rect -873 -190 -814 -147
+rect -1394 -283 -1335 -233
+rect -875 -248 -800 -190
+rect -1394 -360 -1335 -333
+rect -1394 -387 -1379 -360
+rect -1351 -387 -1335 -360
+rect -866 -364 -800 -362
+rect -1394 -397 -1335 -387
+rect -875 -403 -800 -364
+<< psubdiffcont >>
+rect -652 -378 -634 -361
+<< mvnsubdiffcont >>
+rect -93 151 -73 169
+rect -1379 -387 -1351 -360
+<< poly >>
+rect -1436 77 -1393 135
+rect -1335 77 -1292 135
+rect -222 173 -172 187
+rect -555 166 -534 168
+rect -555 116 -521 166
+rect -491 116 -478 166
+rect -915 54 -869 77
+rect -951 27 -869 54
+rect -1435 -32 -1393 25
+rect -1335 -32 -1292 25
+rect -915 4 -869 27
+rect -814 54 -772 77
+rect -814 27 -743 54
+rect -555 30 -534 116
+rect -222 112 -172 143
+rect -137 127 -117 187
+rect -150 112 -100 127
+rect -222 66 -172 81
+rect -150 67 -100 81
+rect -814 4 -772 27
+rect -555 -21 -521 30
+rect -491 -21 -476 30
+rect -1435 -133 -1393 -83
+rect -1335 -133 -1291 -83
+rect -915 -147 -873 -72
+rect -814 -147 -771 -72
+rect -535 -94 -521 -42
+rect -491 -94 -447 -42
+rect -471 -123 -447 -94
+rect -1436 -233 -1394 -183
+rect -1335 -233 -1292 -183
+rect -534 -175 -521 -123
+rect -491 -167 -447 -123
+rect -491 -175 -472 -167
+rect -471 -175 -447 -167
+rect -534 -246 -521 -196
+rect -491 -246 -472 -196
+rect -1436 -333 -1394 -283
+rect -1335 -333 -1292 -283
+rect -927 -364 -875 -250
+rect -800 -362 -778 -248
+rect -537 -381 -521 -331
+rect -491 -381 -475 -331
+<< locali >>
+rect -523 172 -515 189
+rect -497 172 -489 189
+rect -256 150 -247 167
+rect -229 150 -221 167
+rect -166 166 -146 175
+rect -166 149 -165 166
+rect -166 141 -146 149
+rect -93 169 -73 180
+rect -523 93 -515 110
+rect -497 93 -489 110
+rect -93 105 -73 151
+rect -256 88 -247 105
+rect -229 88 -221 105
+rect -93 80 -73 88
+rect -523 36 -515 53
+rect -497 36 -489 53
+rect -524 -117 -515 -100
+rect -497 -117 -489 -100
+rect -523 -269 -515 -252
+rect -497 -269 -489 -252
+rect -523 -325 -515 -308
+rect -497 -325 -489 -308
+rect -1379 -360 -1351 -352
+rect -660 -378 -652 -361
+rect -634 -378 -626 -361
+rect -1379 -395 -1351 -387
+rect -523 -404 -515 -387
+rect -497 -404 -489 -387
+<< end >>
diff --git a/mag/sky130_hilas_swc4x1BiasCell.mag b/mag/sky130_hilas_swc4x1BiasCell.mag
new file mode 100644
index 0000000..178d5d0
--- /dev/null
+++ b/mag/sky130_hilas_swc4x1BiasCell.mag
@@ -0,0 +1,325 @@
+magic
+tech sky130A
+timestamp 1625403878
+<< error_s >>
+rect 168 160 174 166
+rect 273 160 279 166
+rect -206 150 -200 156
+rect -153 150 -147 156
+rect -212 100 -206 106
+rect -147 100 -141 106
+rect 162 96 168 102
+rect 279 96 285 102
+rect -206 41 -200 47
+rect -153 41 -147 47
+rect 168 43 174 49
+rect 273 43 279 49
+rect -212 -9 -206 -3
+rect -147 -9 -141 -3
+rect 162 -21 168 -15
+rect 279 -21 285 -15
+rect 168 -142 174 -136
+rect 273 -142 279 -136
+rect -206 -148 -200 -142
+rect -153 -148 -147 -142
+rect -1 -147 16 -143
+rect -212 -198 -206 -192
+rect -147 -198 -141 -192
+rect 162 -206 168 -200
+rect 279 -206 285 -200
+rect 168 -258 174 -252
+rect 273 -258 279 -252
+rect -206 -265 -200 -259
+rect -153 -265 -147 -259
+rect -212 -315 -206 -309
+rect -147 -315 -141 -309
+rect 162 -322 168 -316
+rect 279 -322 285 -316
+<< nwell >>
+rect 112 220 335 223
+rect -264 37 -263 160
+rect 488 -21 497 -13
+rect 632 -72 667 -71
+rect 632 -88 649 -72
+rect 666 -88 667 -72
+rect 112 -382 335 -380
+<< psubdiff >>
+rect -6 82 19 105
+rect -6 65 -2 82
+rect 15 65 19 82
+rect -6 37 19 65
+rect 396 79 421 107
+rect 396 62 400 79
+rect 417 62 421 79
+rect 396 36 421 62
+rect -6 -45 20 -3
+rect -6 -62 -1 -45
+rect 16 -62 20 -45
+rect -6 -79 20 -62
+rect -6 -96 -1 -79
+rect 16 -96 20 -79
+rect -6 -113 20 -96
+rect -6 -130 -1 -113
+rect 16 -130 20 -113
+rect -6 -143 20 -130
+rect 396 -39 423 -18
+rect 396 -56 401 -39
+rect 418 -56 423 -39
+rect 396 -73 423 -56
+rect 396 -90 401 -73
+rect 418 -90 423 -73
+rect 396 -107 423 -90
+rect 396 -124 401 -107
+rect 418 -124 423 -107
+rect 396 -142 423 -124
+rect -1 -147 16 -143
+<< psubdiffcont >>
+rect -2 65 15 82
+rect 400 62 417 79
+rect -1 -62 16 -45
+rect -1 -96 16 -79
+rect -1 -130 16 -113
+rect 401 -56 418 -39
+rect 401 -90 418 -73
+rect 401 -124 418 -107
+<< poly >>
+rect 319 147 489 151
+rect -107 114 130 138
+rect 319 135 488 147
+rect -107 5 128 29
+rect 319 -9 488 8
+rect 649 -72 667 -71
+rect 665 -88 667 -72
+rect -107 -175 130 -151
+rect 320 -167 488 -150
+rect -105 -295 132 -271
+rect 320 -309 488 -292
+<< polycont >>
+rect 632 -88 649 -71
+<< locali >>
+rect 623 -88 632 -71
+<< viali >>
+rect -2 82 15 99
+rect -2 48 15 65
+rect 400 79 417 96
+rect 400 45 417 62
+rect -1 -45 16 -28
+rect -1 -79 16 -62
+rect -1 -113 16 -96
+rect -1 -147 16 -130
+rect 401 -39 418 -22
+rect 401 -73 418 -56
+rect 649 -88 667 -71
+rect 401 -107 418 -90
+rect 401 -141 418 -124
+<< metal1 >>
+rect -228 -382 -188 223
+rect -7 99 20 223
+rect 177 213 215 223
+rect -7 82 -2 99
+rect 15 82 20 99
+rect -7 65 20 82
+rect -7 48 -2 65
+rect 15 48 20 65
+rect -7 -28 20 48
+rect -7 -45 -1 -28
+rect 16 -45 20 -28
+rect -7 -62 20 -45
+rect -7 -79 -1 -62
+rect 16 -79 20 -62
+rect -7 -96 20 -79
+rect -7 -113 -1 -96
+rect 16 -113 20 -96
+rect -7 -130 20 -113
+rect -7 -147 -1 -130
+rect 16 -147 20 -130
+rect -7 -224 20 -147
+rect 396 96 421 223
+rect 611 216 627 223
+rect 648 216 667 223
+rect 692 216 708 223
+rect 396 79 400 96
+rect 417 79 421 96
+rect 396 62 421 79
+rect 396 45 400 62
+rect 417 45 421 62
+rect 396 -22 421 45
+rect 396 -39 401 -22
+rect 418 -39 421 -22
+rect 396 -56 421 -39
+rect 396 -73 401 -56
+rect 418 -73 421 -56
+rect 654 -68 667 -66
+rect 396 -90 421 -73
+rect 396 -107 401 -90
+rect 418 -107 421 -90
+rect 646 -71 670 -68
+rect 646 -88 649 -71
+rect 667 -88 670 -71
+rect 646 -91 670 -88
+rect 656 -95 667 -91
+rect 396 -124 421 -107
+rect 396 -141 401 -124
+rect 418 -141 421 -124
+rect 396 -221 421 -141
+rect 395 -224 423 -221
+rect -9 -227 22 -224
+rect -9 -253 -7 -227
+rect 20 -253 22 -227
+rect 394 -225 424 -224
+rect 394 -251 396 -225
+rect 422 -251 424 -225
+rect 394 -252 424 -251
+rect -9 -255 22 -253
+rect 395 -254 423 -252
+rect -7 -382 20 -255
+rect 177 -382 215 -372
+rect 396 -382 421 -254
+rect 611 -381 627 -374
+rect 648 -381 667 -374
+rect 692 -381 708 -374
+<< via1 >>
+rect -7 -253 20 -227
+rect 396 -251 422 -225
+<< metal2 >>
+rect 487 166 497 173
+rect 487 155 500 166
+rect 735 155 744 173
+rect -264 112 540 130
+rect 735 112 744 130
+rect -264 111 -249 112
+rect -266 30 -252 32
+rect -266 24 497 30
+rect -266 12 500 24
+rect 736 12 745 30
+rect 488 -20 497 -17
+rect 488 -31 500 -20
+rect 735 -31 744 -13
+rect 485 -146 500 -129
+rect 734 -146 745 -128
+rect -263 -187 500 -171
+rect -262 -188 500 -187
+rect 733 -189 744 -171
+rect 393 -225 425 -224
+rect -10 -253 -7 -227
+rect 20 -230 23 -227
+rect 393 -230 396 -225
+rect 20 -247 396 -230
+rect 20 -253 23 -247
+rect 393 -251 396 -247
+rect 422 -251 425 -225
+rect 393 -252 425 -251
+rect -263 -286 500 -269
+rect -184 -295 -30 -286
+rect 733 -288 744 -270
+rect 487 -330 500 -313
+rect 733 -331 744 -313
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_1
+timestamp 1608066871
+transform 1 0 1188 0 1 18
+box -1451 -400 -1278 -210
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_0
+timestamp 1608066871
+transform 1 0 1188 0 1 135
+box -1451 -400 -1278 -210
+use sky130_hilas_FGVaractorCapacitor sky130_hilas_FGVaractorCapacitor_0
+timestamp 1606741561
+transform 1 0 1069 0 1 14
+box -957 -395 -734 -209
+use sky130_hilas_FGVaractorCapacitor sky130_hilas_FGVaractorCapacitor_1
+timestamp 1606741561
+transform 1 0 1069 0 1 130
+box -957 -395 -734 -209
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_1
+timestamp 1607386385
+transform 1 0 777 0 1 -428
+box -289 47 -33 232
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_2
+timestamp 1607386385
+transform 1 0 777 0 -1 -31
+box -289 47 -33 232
+use sky130_hilas_wellContact sky130_hilas_wellContact_1
+timestamp 1606753443
+transform 1 0 1185 0 1 293
+box -1449 -441 -1275 -255
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_2
+timestamp 1608066871
+transform 1 0 1188 0 1 324
+box -1451 -400 -1278 -210
+use sky130_hilas_FGVaractorCapacitor sky130_hilas_FGVaractorCapacitor_2
+timestamp 1606741561
+transform 1 0 1069 0 1 315
+box -957 -395 -734 -209
+use sky130_hilas_wellContact sky130_hilas_wellContact_0
+timestamp 1606753443
+transform 1 0 1588 0 1 286
+box -1449 -441 -1275 -255
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_0
+timestamp 1607386385
+transform 1 0 777 0 1 -128
+box -289 47 -33 232
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_3
+timestamp 1608066871
+transform 1 0 1188 0 1 433
+box -1451 -400 -1278 -210
+use sky130_hilas_FGVaractorCapacitor sky130_hilas_FGVaractorCapacitor_3
+timestamp 1606741561
+transform 1 0 1069 0 1 432
+box -957 -395 -734 -209
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_3
+timestamp 1607386385
+transform 1 0 777 0 -1 270
+box -289 47 -33 232
+<< labels >>
+rlabel metal2 -264 111 -252 130 0 ROW1
+port 1 nsew analog default
+rlabel metal2 -266 13 -254 32 0 ROW2
+port 2 nsew analog default
+rlabel metal2 -263 -187 -251 -171 0 ROW3
+port 3 nsew analog default
+rlabel metal2 -263 -285 -249 -270 0 ROW4
+port 4 nsew analog default
+rlabel metal1 -228 209 -188 223 0 VTUN
+port 5 nsew analog default
+rlabel metal1 -228 -382 -188 -372 0 VTUN
+port 5 nsew analog default
+rlabel metal1 177 -382 215 -372 0 GATE1
+port 6 nsew analog default
+rlabel metal1 177 213 215 223 0 GATE1
+port 6 nsew analog default
+rlabel metal1 692 216 708 223 0 VINJ
+port 7 nsew power default
+rlabel metal1 611 216 627 223 0 VPWR
+port 8 nsew power default
+rlabel metal1 648 216 667 223 0 COLSEL1
+rlabel metal1 692 -381 708 -374 0 VINJ
+port 7 nsew power default
+rlabel metal1 611 -381 627 -374 0 VPWR
+port 8 nsew power default
+rlabel metal1 648 -381 667 -374 0 COLSEL1
+port 9 nsew analog default
+rlabel metal2 735 155 744 173 0 DRAIN1
+port 10 nsew analog default
+rlabel metal2 735 112 744 130 0 ROW1
+port 11 nsew analog default
+rlabel metal2 735 -31 744 -13 0 DRAIN2
+port 13 nsew
+rlabel metal2 736 12 745 30 0 ROW2
+port 12 nsew analog default
+rlabel metal2 734 -146 745 -128 0 DRAIN3
+port 14 nsew analog default
+rlabel metal2 733 -189 744 -171 0 ROW3
+port 15 nsew analog default
+rlabel metal2 733 -288 744 -270 0 ROW4
+port 16 nsew analog default
+rlabel metal2 733 -331 744 -313 0 DRAIN4
+port 17 nsew analog default
+rlabel metal1 -7 215 20 223 0 VGND
+port 18 nsew
+rlabel metal1 396 218 421 223 0 VGND
+port 18 nsew
+rlabel metal1 -7 -382 20 -375 0 VGND
+port 18 nsew
+rlabel metal1 396 -382 421 -375 0 VGND
+port 18 nsew
+<< end >>
diff --git a/mag/sky130_hilas_swc4x1cellOverlap.mag b/mag/sky130_hilas_swc4x1cellOverlap.mag
new file mode 100644
index 0000000..f7fd39b
--- /dev/null
+++ b/mag/sky130_hilas_swc4x1cellOverlap.mag
@@ -0,0 +1,381 @@
+magic
+tech sky130A
+timestamp 1607258550
+<< error_s >>
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+rect 424 -413 453 -385
+<< nwell >>
+rect 632 -72 667 -71
+rect 632 -88 649 -72
+rect 666 -88 667 -72
+<< poly >>
+rect 453 147 489 151
+rect -107 114 130 138
+rect 453 135 488 147
+rect -107 5 128 29
+rect 453 -9 488 8
+rect 649 -72 667 -71
+rect 665 -88 667 -72
+rect -107 -175 130 -151
+rect 320 -167 488 -150
+rect -105 -295 132 -271
+rect 320 -309 488 -292
+<< polycont >>
+rect 632 -88 649 -71
+<< locali >>
+rect 623 -88 632 -71
+<< viali >>
+rect 649 -88 667 -71
+<< metal1 >>
+rect -228 -382 -188 217
+rect 654 -68 667 -66
+rect 646 -71 670 -68
+rect 646 -88 649 -71
+rect 667 -88 670 -71
+rect 646 -91 670 -88
+rect 656 -95 667 -91
+<< metal2 >>
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+rect -264 -20 496 -13
+rect -264 -31 500 -20
+rect -262 -146 500 -129
+rect -262 -188 500 -171
+rect -262 -286 500 -269
+rect -184 -295 -30 -286
+rect -262 -330 500 -313
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_0
+timestamp 1606740587
+transform 1 0 1188 0 1 135
+box -1451 -400 -1278 -210
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_1
+timestamp 1606740587
+transform 1 0 1188 0 1 18
+box -1451 -400 -1278 -210
+use sky130_hilas_overlapCap01 sky130_hilas_overlapCap01_2
+timestamp 1607257541
+transform 1 0 503 0 1 -188
+box -287 -71 0 137
+use sky130_hilas_overlapCap01 sky130_hilas_overlapCap01_3
+timestamp 1607257541
+transform 1 0 503 0 1 -342
+box -287 -71 0 137
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_1
+timestamp 1606750506
+transform 1 0 777 0 1 -428
+box -289 47 -33 232
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_2
+timestamp 1606750506
+transform 1 0 777 0 -1 -31
+box -289 47 -33 232
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_2
+timestamp 1606740587
+transform 1 0 1188 0 1 324
+box -1451 -400 -1278 -210
+use sky130_hilas_wellContact sky130_hilas_wellContact_1
+timestamp 1606753443
+transform 1 0 1185 0 1 293
+box -1449 -441 -1275 -255
+use sky130_hilas_TunCap01 sky130_hilas_TunCap01_3
+timestamp 1606740587
+transform 1 0 1188 0 1 433
+box -1451 -400 -1278 -210
+use sky130_hilas_overlapCap01 sky130_hilas_overlapCap01_1
+timestamp 1607257541
+transform 1 0 504 0 1 -32
+box -287 -71 0 137
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_0
+timestamp 1606750506
+transform 1 0 777 0 1 -128
+box -289 47 -33 232
+use sky130_hilas_overlapCap01 sky130_hilas_overlapCap01_0
+timestamp 1607257541
+transform 1 0 504 0 1 121
+box -287 -71 0 137
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_3
+timestamp 1606750506
+transform 1 0 777 0 -1 270
+box -289 47 -33 232
+<< end >>
diff --git a/mag/sky130_hilas_swc4x1cellOverlap2.mag b/mag/sky130_hilas_swc4x1cellOverlap2.mag
new file mode 100644
index 0000000..bbabf68
--- /dev/null
+++ b/mag/sky130_hilas_swc4x1cellOverlap2.mag
@@ -0,0 +1,331 @@
+magic
+tech sky130A
+timestamp 1607392100
+<< error_s >>
+rect -91 192 -62 210
+rect 155 190 184 206
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+rect 313 -364 342 -349
+rect 392 -364 421 -349
+<< nwell >>
+rect 632 -72 667 -71
+rect 632 -88 649 -72
+rect 666 -88 667 -72
+<< poly >>
+rect 469 147 489 151
+rect -19 114 130 138
+rect 469 135 488 147
+rect -19 5 128 29
+rect 469 -9 488 8
+rect 649 -72 667 -71
+rect 665 -88 667 -72
+rect -19 -175 130 -151
+rect 469 -167 488 -150
+rect -19 -295 132 -271
+rect 469 -309 488 -292
+<< polycont >>
+rect 632 -88 649 -71
+<< locali >>
+rect 623 -88 632 -71
+<< viali >>
+rect 649 -88 667 -71
+<< metal1 >>
+rect -90 -382 -63 223
+rect 654 -68 667 -66
+rect 646 -71 670 -68
+rect 646 -88 649 -71
+rect 667 -88 670 -71
+rect 646 -91 670 -88
+rect 656 -95 667 -91
+<< metal2 >>
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+rect -191 155 500 166
+rect -191 112 710 130
+rect -191 24 497 30
+rect -191 12 500 24
+rect -191 -20 496 -13
+rect -191 -31 500 -20
+rect -191 -146 500 -129
+rect -191 -188 500 -171
+rect -191 -286 500 -269
+rect -191 -330 500 -313
+use sky130_hilas_nOverlapCap01 sky130_hilas_nOverlapCap01_3
+timestamp 1607262215
+transform 1 0 -79 0 1 -327
+box -62 -43 67 86
+use sky130_hilas_nOverlapCap01 sky130_hilas_nOverlapCap01_2
+timestamp 1607262215
+transform 1 0 -79 0 1 -173
+box -62 -43 67 86
+use sky130_hilas_overlapCap02a sky130_hilas_overlapCap02a_3
+timestamp 1607261501
+transform 1 0 609 0 1 -328
+box -521 -54 -121 110
+use sky130_hilas_overlapCap02a sky130_hilas_overlapCap02a_2
+timestamp 1607261501
+transform 1 0 609 0 1 -181
+box -521 -54 -121 110
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_1
+timestamp 1607386385
+transform 1 0 777 0 1 -428
+box -289 47 -33 232
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_2
+timestamp 1607386385
+transform 1 0 777 0 -1 -31
+box -289 47 -33 232
+use sky130_hilas_nOverlapCap01 sky130_hilas_nOverlapCap01_1
+timestamp 1607262215
+transform 1 0 -79 0 1 -28
+box -62 -43 67 86
+use sky130_hilas_overlapCap02a sky130_hilas_overlapCap02a_1
+timestamp 1607261501
+transform 1 0 609 0 1 -34
+box -521 -54 -121 110
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_0
+timestamp 1607386385
+transform 1 0 777 0 1 -128
+box -289 47 -33 232
+use sky130_hilas_nOverlapCap01 sky130_hilas_nOverlapCap01_0
+timestamp 1607262215
+transform 1 0 -79 0 1 124
+box -62 -43 67 86
+use sky130_hilas_overlapCap02a sky130_hilas_overlapCap02a_0
+timestamp 1607261501
+transform 1 0 609 0 1 113
+box -521 -54 -121 110
+use sky130_hilas_horizPcell01 sky130_hilas_horizPcell01_3
+timestamp 1607386385
+transform 1 0 777 0 -1 270
+box -289 47 -33 232
+<< end >>
diff --git a/mag/sky130_hilas_swc4x2cell.mag b/mag/sky130_hilas_swc4x2cell.mag
new file mode 100644
index 0000000..9990f7a
--- /dev/null
+++ b/mag/sky130_hilas_swc4x2cell.mag
@@ -0,0 +1,236 @@
+magic
+tech sky130A
+timestamp 1625491916
+<< error_s >>
+rect -539 538 -533 544
+rect -434 538 -428 544
+rect 432 538 438 544
+rect 537 538 543 544
+rect -113 528 -107 534
+rect -60 528 -54 534
+rect 58 528 64 534
+rect 111 528 117 534
+rect -545 474 -539 480
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+<< metal1 >>
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+rect -984 595 -952 597
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+rect 280 -4 304 3
+rect 441 -4 479 11
+rect 673 -4 697 2
+rect 875 -3 891 3
+rect 912 -3 931 3
+rect 956 -3 972 3
+<< via1 >>
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+rect 959 569 985 595
+<< metal2 >>
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+rect -955 587 -699 595
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+rect 995 347 1009 365
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+rect 1000 189 1009 207
+rect -334 134 342 152
+rect -1004 90 -997 108
+rect 1000 90 1009 108
+rect -1004 47 -997 65
+rect 1000 47 1009 65
+use sky130_hilas_cellAttempt01 sky130_hilas_cellAttempt01_1
+timestamp 1625402619
+transform -1 0 -260 0 1 378
+box -264 -382 744 223
+use sky130_hilas_cellAttempt01 sky130_hilas_cellAttempt01_0
+timestamp 1625402619
+transform 1 0 264 0 1 378
+box -264 -382 744 223
+<< labels >>
+rlabel metal1 441 591 479 601 0 GATE2
+port 1 nsew analog default
+rlabel metal1 -72 -4 -32 8 0 VTUN
+port 2 nsew power default
+rlabel metal1 36 -4 76 8 0 VTUN
+port 2 nsew power default
+rlabel metal1 36 591 76 601 0 VTUN
+port 2 nsew power default
+rlabel metal1 -72 588 -32 601 0 VTUN
+port 2 nsew power default
+rlabel metal1 -475 591 -437 601 0 GATE1
+port 3 nsew analog default
+rlabel metal1 -475 -4 -437 5 0 GATE1
+port 3 nsew analog default
+rlabel metal1 956 -3 972 3 0 VINJ
+port 4 nsew power default
+rlabel metal1 441 -4 479 11 0 GATE2
+port 1 nsew analog default
+rlabel metal1 912 596 931 601 0 SelectGate2
+rlabel metal1 956 596 972 601 0 VINJ
+port 6 nsew power default
+rlabel metal1 -968 596 -952 601 0 VINJ
+port 6 nsew power default
+rlabel metal1 -927 596 -908 601 0 GATESELECT1
+port 10 nsew analog default
+rlabel metal1 -968 -4 -952 2 0 VINJ
+port 6 nsew power default
+rlabel metal1 -927 -3 -908 3 0 GATESELECT1
+port 10 nsew analog default
+rlabel metal1 -887 596 -871 601 0 COL1
+port 12 nsew analog default
+rlabel metal1 -887 -3 -871 3 0 COL1
+port 12 nsew analog default
+rlabel metal1 912 -3 931 3 0 GATESELECT2
+port 11 nsew analog default
+rlabel metal1 875 -3 891 3 0 COL2
+port 13 nsew analog default
+rlabel metal1 875 596 891 601 0 COL2
+port 13 nsew analog default
+rlabel metal2 -1004 490 -997 509 0 ROW1
+port 14 nsew analog default
+rlabel metal2 -1004 390 -997 409 0 ROW2
+port 15 nsew analog default
+rlabel metal2 -1004 533 -997 552 0 DRAIN1
+port 16 nsew analog default
+rlabel metal2 -1004 347 -997 365 0 DRAIN2
+port 17 nsew analog default
+rlabel metal2 -1004 232 -997 250 0 DRAIN3
+port 18 nsew analog default
+rlabel metal2 -1004 189 -997 207 0 ROW3
+port 19 nsew analog default
+rlabel metal2 -1004 90 -997 108 0 ROW4
+port 20 nsew analog default
+rlabel metal2 -1004 47 -997 65 0 DRAIN4
+port 21 nsew analog default
+rlabel metal2 999 533 1008 551 0 DRAIN1
+port 16 nsew analog default
+rlabel metal2 999 490 1008 508 0 ROW1
+port 14 nsew analog default
+rlabel metal2 1000 390 1009 408 0 ROW2
+port 15 nsew
+rlabel metal2 1000 347 1009 365 0 DRAIN2
+port 17 nsew analog default
+rlabel metal2 1000 232 1009 250 0 DRAIN3
+port 18 nsew analog default
+rlabel metal2 1000 189 1009 207 0 ROW3
+port 19 nsew analog default
+rlabel metal2 1000 90 1009 108 0 ROW4
+port 20 nsew analog default
+rlabel metal2 1000 47 1009 65 0 DRAIN4
+port 21 nsew
+rlabel metal1 -693 595 -669 601 0 VGND
+port 22 nsew
+rlabel metal1 -693 -4 -669 4 0 VGND
+port 22 nsew
+rlabel metal1 -300 -4 -276 3 0 VGND
+port 22 nsew
+rlabel metal1 -300 595 -276 601 0 VGND
+port 22 nsew
+rlabel metal1 280 -4 304 3 0 VGND
+port 22 nsew
+rlabel metal1 673 -4 697 2 0 VGND
+port 22 nsew
+rlabel metal1 280 596 304 601 0 VGND
+port 22 nsew
+rlabel metal1 673 594 697 601 0 VGND
+port 22 nsew
+<< end >>
diff --git a/mag/sky130_hilas_swc4x2cellOverlap.mag b/mag/sky130_hilas_swc4x2cellOverlap.mag
new file mode 100644
index 0000000..0039042
--- /dev/null
+++ b/mag/sky130_hilas_swc4x2cellOverlap.mag
@@ -0,0 +1,586 @@
+magic
+tech sky130A
+timestamp 1608301303
+<< error_s >>
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+<< metal1 >>
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+rect 663 729 679 736
+rect 700 729 719 736
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+<< metal2 >>
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+rect -1001 964 -994 982
+rect 785 964 796 982
+rect -1001 921 -994 939
+rect 785 921 796 939
+rect -1001 822 -994 840
+rect 785 822 796 840
+rect -1001 779 -994 797
+rect 785 779 796 797
+use sky130_hilas_swc4x1cellOverlap2 sky130_hilas_swc4x1cellOverlap2_0
+timestamp 1607392100
+transform 1 0 52 0 1 1110
+box -191 -382 744 223
+use sky130_hilas_swc4x1cellOverlap2 sky130_hilas_swc4x1cellOverlap2_1
+timestamp 1607392100
+transform -1 0 -257 0 1 1110
+box -191 -382 744 223
+<< labels >>
+rlabel metal1 -884 1327 -868 1333 0 VERT1
+port 1 nsew analog default
+rlabel metal1 -965 1327 -949 1333 0 VINJ
+port 10 nsew
+rlabel metal1 -924 1327 -905 1333 0 GATESELECT1
+port 11 nsew analog default
+rlabel metal2 -1001 1265 -993 1283 0 DRAIN1
+port 3 nsew analog default
+rlabel metal2 -1001 1222 -993 1240 0 HORIZ1
+port 2 nsew analog default
+rlabel metal2 -1001 1122 -993 1140 0 HORIZ2
+port 4 nsew analog default
+rlabel metal2 -1001 1079 -993 1097 0 DRAIN2
+port 5 nsew analog default
+rlabel metal2 -1001 964 -994 982 0 DRAIN3
+port 6 nsew analog default
+rlabel metal2 -1001 921 -994 939 0 HORIZ3
+port 7 nsew analog default
+rlabel metal2 -1001 822 -994 840 0 HORIZ4
+port 8 nsew analog default
+rlabel metal2 -1001 779 -994 797 0 DRAIN4
+port 9 nsew analog default
+rlabel metal1 -965 729 -949 736 0 VINJ
+port 10 nsew power default
+rlabel metal1 -884 729 -868 736 0 VERT1
+port 1 nsew analog default
+rlabel metal1 -924 729 -905 736 0 GATESELECT1
+port 11 nsew analog default
+rlabel metal1 744 729 760 736 0 VINJ
+port 10 nsew power default
+rlabel metal1 663 1326 679 1333 0 VERT2
+port 12 nsew analog default
+rlabel metal1 700 1326 719 1333 0 GATESELECT2
+port 13 nsew analog default
+rlabel metal1 744 1326 760 1333 0 VINJ
+port 10 nsew power default
+rlabel metal1 663 729 679 736 0 VERT2
+port 12 nsew analog default
+rlabel metal1 700 729 719 736 0 GATESELECT2
+port 13 nsew analog default
+rlabel metal2 785 1265 796 1283 0 DRAIN1
+port 3 nsew analog default
+rlabel metal2 786 1222 797 1240 0 HORIZ1
+port 2 nsew analog default
+rlabel metal2 786 1122 797 1140 0 HORIZ2
+port 4 nsew analog default
+rlabel metal2 786 1079 797 1097 0 DRAIN2
+port 5 nsew analog default
+rlabel metal2 785 964 796 982 0 DRAIN3
+port 6 nsew analog default
+rlabel metal2 785 921 796 939 0 HORIZ3
+port 7 nsew analog default
+rlabel metal2 785 822 796 840 0 HORIZ4
+port 8 nsew analog default
+rlabel metal2 785 779 796 797 0 DRAIN
+port 14 nsew analog default
+rlabel metal1 328 1328 352 1333 0 GATE2
+port 15 nsew analog default
+rlabel metal1 328 728 352 734 0 GATE2
+port 15 nsew analog default
+rlabel metal1 -557 1327 -532 1333 0 GATE1
+port 16 nsew analog default
+rlabel metal1 -557 728 -532 734 0 GATE1
+port 16 nsew analog default
+rlabel metal1 -196 1325 -166 1333 0 VTUN
+port 17 nsew analog default
+rlabel metal1 -38 1325 -8 1333 0 VTUN
+rlabel metal1 -196 728 -166 736 0 VTUN
+port 17 nsew analog default
+rlabel metal1 -38 728 -8 736 0 VTUN
+port 17 nsew analog default
+<< end >>
diff --git a/mag/sky130_hilas_wellContact.mag b/mag/sky130_hilas_wellContact.mag
new file mode 100644
index 0000000..5683e0e
--- /dev/null
+++ b/mag/sky130_hilas_wellContact.mag
@@ -0,0 +1,23 @@
+magic
+tech sky130A
+timestamp 1606753443
+<< nwell >>
+rect -1449 -440 -1275 -256
+<< mvnsubdiff >>
+rect -1394 -360 -1335 -331
+rect -1394 -387 -1379 -360
+rect -1351 -387 -1335 -360
+rect -1394 -405 -1335 -387
+<< mvnsubdiffcont >>
+rect -1379 -387 -1351 -360
+<< locali >>
+rect -1406 -360 -1351 -352
+rect -1406 -395 -1351 -387
+<< viali >>
+rect -1406 -387 -1379 -360
+<< metal1 >>
+rect -1412 -360 -1373 -255
+rect -1412 -387 -1406 -360
+rect -1379 -387 -1373 -360
+rect -1412 -441 -1373 -387
+<< end >>
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
new file mode 100644
index 0000000..714c649
--- /dev/null
+++ b/mag/user_analog_project_wrapper.mag
@@ -0,0 +1,2759 @@
+magic
+tech sky130A
+timestamp 1626828319
+<< error_p >>
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+rect 191034 314581 191037 314584
+rect 186053 313997 186056 314000
+rect 191034 313997 191037 314000
+rect 186056 313994 186059 313997
+rect 191031 313994 191034 313997
+<< metal1 >>
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+rect 291760 2545 292400 2601
+rect -400 1954 240 2010
+rect 291760 1954 292400 2010
+rect -400 1363 240 1419
+rect 291760 1363 292400 1419
+rect -400 772 240 828
+rect 291760 772 292400 828
+<< via3 >>
+rect 255444 346190 262547 350931
+rect 114257 335455 119370 335799
+rect 186003 335466 191335 335668
+rect 124052 334787 127445 335149
+rect 176867 334905 180418 335101
+rect 950 317066 2340 324150
+rect 945 274772 2231 282005
+rect 186056 313997 191034 314584
+rect 1140 102619 3439 109573
+rect 176853 311484 180595 312345
+rect 194386 311873 197359 312003
+rect 194386 309164 194509 311873
+rect 194509 309164 197218 311873
+rect 197218 309164 197359 311873
+rect 194386 309057 197359 309164
+rect 107774 291484 109861 294958
+rect 288863 315226 291366 321612
+rect 287797 270874 290554 276962
+rect 65591 113155 70628 119497
+rect 289048 112815 290745 119736
+rect 287969 68550 290989 75653
+<< metal4 >>
+rect 255168 350931 262840 350996
+rect 255168 346190 255444 350931
+rect 262547 346190 262840 350931
+rect 255168 345441 262840 346190
+rect 113966 339720 262676 345275
+rect 113966 335799 119521 339720
+rect 113966 335455 114257 335799
+rect 119370 335455 119521 335799
+rect 900 324150 6035 324201
+rect 900 317066 950 324150
+rect 2340 321082 6035 324150
+rect 2340 317387 34744 321082
+rect 2340 317066 6035 317387
+rect 900 316981 6035 317066
+rect 31049 295049 34744 317387
+rect 113966 297007 119521 335455
+rect 123646 335149 127552 335299
+rect 123646 334787 124052 335149
+rect 127445 334787 127552 335149
+rect 31049 294958 110021 295049
+rect 31049 291484 107774 294958
+rect 109861 291484 110021 294958
+rect 31049 291354 110021 291484
+rect 778 282005 4486 282389
+rect 778 274772 945 282005
+rect 2231 281468 4486 282005
+rect 113966 281468 119596 297007
+rect 2231 275661 119596 281468
+rect 2231 274772 4486 275661
+rect 778 274572 4486 274772
+rect 65342 119497 71089 120119
+rect 65342 113155 65591 119497
+rect 70628 113155 71089 119497
+rect 996 109573 9186 109717
+rect 996 102619 1140 109573
+rect 3439 108251 9186 109573
+rect 65342 108251 71089 113155
+rect 3439 102619 71089 108251
+rect 996 102504 71089 102619
+rect 110906 76122 116193 275661
+rect 123646 275407 127552 334787
+rect 176783 335101 180689 336160
+rect 176783 334905 176867 335101
+rect 180418 334905 180689 335101
+rect 176783 312345 180689 334905
+rect 176783 311484 176853 312345
+rect 180595 311484 180689 312345
+rect 185922 335668 191477 339720
+rect 185922 335466 186003 335668
+rect 191335 335466 191477 335668
+rect 185922 314584 191477 335466
+rect 285412 321612 291624 321871
+rect 285412 320390 288863 321612
+rect 185922 313997 186056 314584
+rect 191034 313997 191477 314584
+rect 185922 312301 191477 313997
+rect 267876 316939 288863 320390
+rect 194301 312376 195024 312387
+rect 267876 312376 271327 316939
+rect 285412 315226 288863 316939
+rect 291366 315226 291624 321612
+rect 285412 315140 291624 315226
+rect 176783 275407 180689 311484
+rect 194301 312003 271327 312376
+rect 194301 309057 194386 312003
+rect 197359 309057 271327 312003
+rect 194301 308935 271327 309057
+rect 194370 308925 271327 308935
+rect 283891 276962 290899 277307
+rect 283891 275407 287797 276962
+rect 123646 271501 287797 275407
+rect 259145 227099 263606 271501
+rect 283891 270874 287797 271501
+rect 290554 270874 290899 276962
+rect 283891 270414 290899 270874
+rect 258418 222638 263606 227099
+rect 259145 119185 263605 222638
+rect 284588 119736 291137 120207
+rect 284588 119185 289048 119736
+rect 259145 114725 289048 119185
+rect 284588 112815 289048 114725
+rect 290745 112815 291137 119736
+rect 284588 112361 291137 112815
+rect 110906 76081 290030 76122
+rect 110906 75653 291153 76081
+rect 110906 70835 287969 75653
+rect 282682 68550 287969 70835
+rect 290989 68550 291153 75653
+rect 282682 68162 291153 68550
+rect 282682 68060 290030 68162
+<< comment >>
+rect -50 352000 292050 352050
+rect -50 0 0 352000
+rect 292000 0 292050 352000
+rect -50 -50 292050 0
+use m12m3 m12m3_29
+timestamp 1626781805
+transform 1 0 133012 0 1 303846
+box -25 -21 1232 1087
+use m12m3 m12m3_27
+timestamp 1626781805
+transform 1 0 133012 0 1 309660
+box -25 -21 1232 1087
+use m12m3 m12m3_26
+timestamp 1626781805
+transform 1 0 133074 0 1 312091
+box -25 -21 1232 1087
+use m12m3 m12m3_25
+timestamp 1626781805
+transform 1 0 133074 0 1 315106
+box -25 -21 1232 1087
+use m12m3 m12m3_28
+timestamp 1626781805
+transform 1 0 132948 0 1 306753
+box -25 -21 1232 1087
+use m12m3 m12m3_18
+timestamp 1626781805
+transform 1 0 172206 0 1 315227
+box -25 -21 1232 1087
+use m12m3 m12m3_30
+timestamp 1626781805
+transform 1 0 174268 0 1 313861
+box -25 -21 1232 1087
+use m12m3 m12m3_22
+timestamp 1626781805
+transform 1 0 133124 0 1 323749
+box -25 -21 1232 1087
+use m12m3 m12m3_24
+timestamp 1626781805
+transform 1 0 133108 0 1 318171
+box -25 -21 1232 1087
+use m12m3 m12m3_23
+timestamp 1626781805
+transform 1 0 133057 0 1 321019
+box -25 -21 1232 1087
+use m12m3 m12m3_8
+timestamp 1626781805
+transform 1 0 168404 0 1 316575
+box -25 -21 1232 1087
+use m12m3 m12m3_15
+timestamp 1626781805
+transform 1 0 172166 0 1 323714
+box -25 -21 1232 1087
+use m12m3 m12m3_16
+timestamp 1626781805
+transform 1 0 172288 0 1 320912
+box -25 -21 1232 1087
+use m12m3 m12m3_17
+timestamp 1626781805
+transform 1 0 172247 0 1 317988
+box -25 -21 1232 1087
+use m12m3 m12m3_21
+timestamp 1626781805
+transform 1 0 133124 0 1 326479
+box -25 -21 1232 1087
+use m12m3 m12m3_20
+timestamp 1626781805
+transform 1 0 133108 0 1 329511
+box -25 -21 1232 1087
+use m12m3 m12m3_12
+timestamp 1626781805
+transform 1 0 172166 0 1 332200
+box -25 -21 1232 1087
+use m12m3 m12m3_13
+timestamp 1626781805
+transform 1 0 172247 0 1 329276
+box -25 -21 1232 1087
+use m12m3 m12m3_14
+timestamp 1626781805
+transform 1 0 172247 0 1 326759
+box -25 -21 1232 1087
+use m12m3 m12m3_1
+timestamp 1626781805
+transform 1 0 136237 0 1 338302
+box -25 -21 1232 1087
+use m12m3 m12m3_19
+timestamp 1626781805
+transform 1 0 133041 0 1 332459
+box -25 -21 1232 1087
+use m12m3 m12m3_11
+timestamp 1626781805
+transform 1 0 167963 0 1 339248
+box -25 -21 1232 1087
+use m12m3 m12m3_0
+timestamp 1626781805
+transform 1 0 139001 0 1 340528
+box -25 -21 1232 1087
+use m12m3 m12m3_3
+timestamp 1626781805
+transform 1 0 146062 0 1 345056
+box -25 -21 1232 1087
+use m12m3 m12m3_2
+timestamp 1626781805
+transform 1 0 141764 0 1 342702
+box -25 -21 1232 1087
+use m12m3 m12m3_4
+timestamp 1626781805
+transform 1 0 150284 0 1 347359
+box -25 -21 1232 1087
+use m12m3 m12m3_9
+timestamp 1626781805
+transform 1 0 162436 0 1 343623
+box -25 -21 1232 1087
+use m12m3 m12m3_7
+timestamp 1626781805
+transform 1 0 159571 0 1 345926
+box -25 -21 1232 1087
+use m12m3 m12m3_10
+timestamp 1626781805
+transform 1 0 165200 0 1 341397
+box -25 -21 1232 1087
+use m12m3 m12m3_5
+timestamp 1626781805
+transform 1 0 153098 0 1 349789
+box -25 -21 1232 1087
+use m12m3 m12m3_6
+timestamp 1626781805
+transform 1 0 156526 0 1 348894
+box -25 -21 1232 1087
+use sky130_hilas_TopProtectStructure sky130_hilas_TopProtectStructure_0
+timestamp 1626780777
+transform 1 0 149914 0 1 321560
+box -15468 -24337 21817 14573
+<< labels >>
+flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -400 190932 240 190988 0 FreeSans 560 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -400 169321 240 169377 0 FreeSans 560 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -400 147710 240 147766 0 FreeSans 560 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -400 126199 240 126255 0 FreeSans 560 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -400 62388 240 62444 0 FreeSans 560 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -400 40777 240 40833 0 FreeSans 560 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -400 19166 240 19222 0 FreeSans 560 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -400 8455 240 8511 0 FreeSans 560 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 291760 156826 292400 156882 0 FreeSans 560 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 291760 179437 292400 179493 0 FreeSans 560 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 291760 202648 292400 202704 0 FreeSans 560 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 291760 224859 292400 224915 0 FreeSans 560 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 291760 247070 292400 247126 0 FreeSans 560 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 291760 291781 292400 291837 0 FreeSans 560 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -400 255765 240 255821 0 FreeSans 560 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -400 234154 240 234210 0 FreeSans 560 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -400 212543 240 212599 0 FreeSans 560 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 291760 135206 292400 135262 0 FreeSans 560 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -400 190341 240 190397 0 FreeSans 560 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -400 168730 240 168786 0 FreeSans 560 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -400 147119 240 147175 0 FreeSans 560 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -400 125608 240 125664 0 FreeSans 560 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -400 61797 240 61853 0 FreeSans 560 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -400 40186 240 40242 0 FreeSans 560 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -400 18575 240 18631 0 FreeSans 560 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -400 7864 240 7920 0 FreeSans 560 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 291760 157417 292400 157473 0 FreeSans 560 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 291760 180028 292400 180084 0 FreeSans 560 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 291760 203239 292400 203295 0 FreeSans 560 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 291760 225450 292400 225506 0 FreeSans 560 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 291760 247661 292400 247717 0 FreeSans 560 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 291760 292372 292400 292428 0 FreeSans 560 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -400 255174 240 255230 0 FreeSans 560 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -400 233563 240 233619 0 FreeSans 560 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -400 211952 240 212008 0 FreeSans 560 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 291150 338992 292400 341492 0 FreeSans 560 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 340121 850 342621 0 FreeSans 560 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 283297 351150 285797 352400 0 FreeSans 960 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 232697 351150 235197 352400 0 FreeSans 960 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 206697 351150 209197 352400 0 FreeSans 960 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 60097 351150 62597 352400 0 FreeSans 960 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 34097 351150 36597 352400 0 FreeSans 960 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 8097 351150 10597 352400 0 FreeSans 960 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 163397 351150 164497 352400 0 FreeSans 960 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 112547 351150 113647 352400 0 FreeSans 960 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 86697 351150 87797 352400 0 FreeSans 960 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 162147 351150 163247 352400 0 FreeSans 960 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 111297 351150 112397 352400 0 FreeSans 960 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 85447 351150 86547 352400 0 FreeSans 960 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 291760 1363 292400 1419 0 FreeSans 560 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 291760 204421 292400 204477 0 FreeSans 560 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 291760 226632 292400 226688 0 FreeSans 560 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 291760 248843 292400 248899 0 FreeSans 560 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 291760 293554 292400 293610 0 FreeSans 560 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -400 253992 240 254048 0 FreeSans 560 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -400 232381 240 232437 0 FreeSans 560 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -400 210770 240 210826 0 FreeSans 560 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -400 189159 240 189215 0 FreeSans 560 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -400 167548 240 167604 0 FreeSans 560 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -400 145937 240 145993 0 FreeSans 560 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 291760 3727 292400 3783 0 FreeSans 560 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -400 124426 240 124482 0 FreeSans 560 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -400 60615 240 60671 0 FreeSans 560 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -400 39004 240 39060 0 FreeSans 560 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -400 17393 240 17449 0 FreeSans 560 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -400 6682 240 6738 0 FreeSans 560 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -400 4318 240 4374 0 FreeSans 560 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -400 1954 240 2010 0 FreeSans 560 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 291760 6091 292400 6147 0 FreeSans 560 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 291760 8455 292400 8511 0 FreeSans 560 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 291760 10819 292400 10875 0 FreeSans 560 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 291760 24048 292400 24104 0 FreeSans 560 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 291760 46377 292400 46433 0 FreeSans 560 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 291760 136388 292400 136444 0 FreeSans 560 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 291760 158599 292400 158655 0 FreeSans 560 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 291760 181210 292400 181266 0 FreeSans 560 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 291760 772 292400 828 0 FreeSans 560 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 291760 203830 292400 203886 0 FreeSans 560 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 291760 226041 292400 226097 0 FreeSans 560 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 291760 248252 292400 248308 0 FreeSans 560 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 291760 292963 292400 293019 0 FreeSans 560 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -400 254583 240 254639 0 FreeSans 560 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -400 232972 240 233028 0 FreeSans 560 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -400 211361 240 211417 0 FreeSans 560 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -400 189750 240 189806 0 FreeSans 560 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -400 168139 240 168195 0 FreeSans 560 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -400 146528 240 146584 0 FreeSans 560 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 291760 3136 292400 3192 0 FreeSans 560 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -400 125017 240 125073 0 FreeSans 560 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -400 61206 240 61262 0 FreeSans 560 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -400 39595 240 39651 0 FreeSans 560 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -400 17984 240 18040 0 FreeSans 560 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -400 7273 240 7329 0 FreeSans 560 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -400 4909 240 4965 0 FreeSans 560 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -400 2545 240 2601 0 FreeSans 560 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 291760 5500 292400 5556 0 FreeSans 560 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 291760 7864 292400 7920 0 FreeSans 560 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 291760 10228 292400 10284 0 FreeSans 560 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 291760 23457 292400 23513 0 FreeSans 560 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 291760 45786 292400 45842 0 FreeSans 560 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 291760 135797 292400 135853 0 FreeSans 560 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 291760 158008 292400 158064 0 FreeSans 560 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 291760 180619 292400 180675 0 FreeSans 560 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 291760 2545 292400 2601 0 FreeSans 560 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 291760 205603 292400 205659 0 FreeSans 560 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 291760 227814 292400 227870 0 FreeSans 560 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 291760 250025 292400 250081 0 FreeSans 560 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 291760 294736 292400 294792 0 FreeSans 560 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -400 252810 240 252866 0 FreeSans 560 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -400 231199 240 231255 0 FreeSans 560 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -400 209588 240 209644 0 FreeSans 560 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -400 187977 240 188033 0 FreeSans 560 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -400 166366 240 166422 0 FreeSans 560 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -400 144755 240 144811 0 FreeSans 560 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 291760 4909 292400 4965 0 FreeSans 560 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -400 123244 240 123300 0 FreeSans 560 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -400 59433 240 59489 0 FreeSans 560 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -400 37822 240 37878 0 FreeSans 560 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -400 16211 240 16267 0 FreeSans 560 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -400 5500 240 5556 0 FreeSans 560 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -400 3136 240 3192 0 FreeSans 560 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -400 772 240 828 0 FreeSans 560 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 291760 7273 292400 7329 0 FreeSans 560 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 291760 9637 292400 9693 0 FreeSans 560 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 291760 12001 292400 12057 0 FreeSans 560 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 291760 25230 292400 25286 0 FreeSans 560 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 291760 47559 292400 47615 0 FreeSans 560 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 291760 137570 292400 137626 0 FreeSans 560 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 291760 159781 292400 159837 0 FreeSans 560 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 291760 182392 292400 182448 0 FreeSans 560 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 291760 1954 292400 2010 0 FreeSans 560 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 291760 205012 292400 205068 0 FreeSans 560 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 291760 227223 292400 227279 0 FreeSans 560 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 291760 249434 292400 249490 0 FreeSans 560 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 291760 294145 292400 294201 0 FreeSans 560 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -400 253401 240 253457 0 FreeSans 560 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -400 231790 240 231846 0 FreeSans 560 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -400 210179 240 210235 0 FreeSans 560 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -400 188568 240 188624 0 FreeSans 560 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -400 166957 240 167013 0 FreeSans 560 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -400 145346 240 145402 0 FreeSans 560 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 291760 4318 292400 4374 0 FreeSans 560 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -400 123835 240 123891 0 FreeSans 560 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -400 60024 240 60080 0 FreeSans 560 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -400 38413 240 38469 0 FreeSans 560 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -400 16802 240 16858 0 FreeSans 560 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -400 6091 240 6147 0 FreeSans 560 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -400 3727 240 3783 0 FreeSans 560 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -400 1363 240 1419 0 FreeSans 560 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 291760 6682 292400 6738 0 FreeSans 560 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 291760 9046 292400 9102 0 FreeSans 560 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 291760 11410 292400 11466 0 FreeSans 560 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 291760 24639 292400 24695 0 FreeSans 560 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 291760 46968 292400 47024 0 FreeSans 560 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 291760 136979 292400 137035 0 FreeSans 560 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 291760 159190 292400 159246 0 FreeSans 560 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 291760 181801 292400 181857 0 FreeSans 560 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 62908 -400 62964 240 0 FreeSans 560 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 240208 -400 240264 240 0 FreeSans 560 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 241981 -400 242037 240 0 FreeSans 560 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 243754 -400 243810 240 0 FreeSans 560 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 245527 -400 245583 240 0 FreeSans 560 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 247300 -400 247356 240 0 FreeSans 560 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 249073 -400 249129 240 0 FreeSans 560 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 250846 -400 250902 240 0 FreeSans 560 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 252619 -400 252675 240 0 FreeSans 560 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 254392 -400 254448 240 0 FreeSans 560 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 256165 -400 256221 240 0 FreeSans 560 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 80638 -400 80694 240 0 FreeSans 560 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 257938 -400 257994 240 0 FreeSans 560 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 259711 -400 259767 240 0 FreeSans 560 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 261484 -400 261540 240 0 FreeSans 560 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 263257 -400 263313 240 0 FreeSans 560 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 265030 -400 265086 240 0 FreeSans 560 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 266803 -400 266859 240 0 FreeSans 560 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 268576 -400 268632 240 0 FreeSans 560 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 270349 -400 270405 240 0 FreeSans 560 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 272122 -400 272178 240 0 FreeSans 560 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 273895 -400 273951 240 0 FreeSans 560 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 82411 -400 82467 240 0 FreeSans 560 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 275668 -400 275724 240 0 FreeSans 560 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 277441 -400 277497 240 0 FreeSans 560 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 279214 -400 279270 240 0 FreeSans 560 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 280987 -400 281043 240 0 FreeSans 560 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 282760 -400 282816 240 0 FreeSans 560 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 284533 -400 284589 240 0 FreeSans 560 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 286306 -400 286362 240 0 FreeSans 560 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 288079 -400 288135 240 0 FreeSans 560 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 84184 -400 84240 240 0 FreeSans 560 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 85957 -400 86013 240 0 FreeSans 560 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 87730 -400 87786 240 0 FreeSans 560 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 89503 -400 89559 240 0 FreeSans 560 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 91276 -400 91332 240 0 FreeSans 560 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 93049 -400 93105 240 0 FreeSans 560 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 94822 -400 94878 240 0 FreeSans 560 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 96595 -400 96651 240 0 FreeSans 560 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 64681 -400 64737 240 0 FreeSans 560 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 98368 -400 98424 240 0 FreeSans 560 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 100141 -400 100197 240 0 FreeSans 560 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 101914 -400 101970 240 0 FreeSans 560 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 103687 -400 103743 240 0 FreeSans 560 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 105460 -400 105516 240 0 FreeSans 560 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 107233 -400 107289 240 0 FreeSans 560 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 109006 -400 109062 240 0 FreeSans 560 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 110779 -400 110835 240 0 FreeSans 560 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 112552 -400 112608 240 0 FreeSans 560 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 114325 -400 114381 240 0 FreeSans 560 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 66454 -400 66510 240 0 FreeSans 560 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 116098 -400 116154 240 0 FreeSans 560 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 117871 -400 117927 240 0 FreeSans 560 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 119644 -400 119700 240 0 FreeSans 560 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 121417 -400 121473 240 0 FreeSans 560 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 123190 -400 123246 240 0 FreeSans 560 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 124963 -400 125019 240 0 FreeSans 560 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 126736 -400 126792 240 0 FreeSans 560 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 128509 -400 128565 240 0 FreeSans 560 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 130282 -400 130338 240 0 FreeSans 560 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 132055 -400 132111 240 0 FreeSans 560 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 68227 -400 68283 240 0 FreeSans 560 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 133828 -400 133884 240 0 FreeSans 560 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 135601 -400 135657 240 0 FreeSans 560 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 137374 -400 137430 240 0 FreeSans 560 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 139147 -400 139203 240 0 FreeSans 560 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 140920 -400 140976 240 0 FreeSans 560 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 142693 -400 142749 240 0 FreeSans 560 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 144466 -400 144522 240 0 FreeSans 560 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 146239 -400 146295 240 0 FreeSans 560 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 148012 -400 148068 240 0 FreeSans 560 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 149785 -400 149841 240 0 FreeSans 560 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 70000 -400 70056 240 0 FreeSans 560 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 151558 -400 151614 240 0 FreeSans 560 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 153331 -400 153387 240 0 FreeSans 560 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 155104 -400 155160 240 0 FreeSans 560 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 156877 -400 156933 240 0 FreeSans 560 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 158650 -400 158706 240 0 FreeSans 560 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 160423 -400 160479 240 0 FreeSans 560 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 162196 -400 162252 240 0 FreeSans 560 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 163969 -400 164025 240 0 FreeSans 560 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 165742 -400 165798 240 0 FreeSans 560 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 167515 -400 167571 240 0 FreeSans 560 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 71773 -400 71829 240 0 FreeSans 560 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 169288 -400 169344 240 0 FreeSans 560 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 171061 -400 171117 240 0 FreeSans 560 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 172834 -400 172890 240 0 FreeSans 560 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 174607 -400 174663 240 0 FreeSans 560 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 176380 -400 176436 240 0 FreeSans 560 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 178153 -400 178209 240 0 FreeSans 560 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 179926 -400 179982 240 0 FreeSans 560 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 181699 -400 181755 240 0 FreeSans 560 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 183472 -400 183528 240 0 FreeSans 560 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 185245 -400 185301 240 0 FreeSans 560 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 73546 -400 73602 240 0 FreeSans 560 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 187018 -400 187074 240 0 FreeSans 560 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 188791 -400 188847 240 0 FreeSans 560 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 190564 -400 190620 240 0 FreeSans 560 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 192337 -400 192393 240 0 FreeSans 560 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 194110 -400 194166 240 0 FreeSans 560 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 195883 -400 195939 240 0 FreeSans 560 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 197656 -400 197712 240 0 FreeSans 560 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 199429 -400 199485 240 0 FreeSans 560 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 201202 -400 201258 240 0 FreeSans 560 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 202975 -400 203031 240 0 FreeSans 560 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 75319 -400 75375 240 0 FreeSans 560 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 204748 -400 204804 240 0 FreeSans 560 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 206521 -400 206577 240 0 FreeSans 560 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 208294 -400 208350 240 0 FreeSans 560 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 210067 -400 210123 240 0 FreeSans 560 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 211840 -400 211896 240 0 FreeSans 560 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 213613 -400 213669 240 0 FreeSans 560 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 215386 -400 215442 240 0 FreeSans 560 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 217159 -400 217215 240 0 FreeSans 560 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 218932 -400 218988 240 0 FreeSans 560 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 220705 -400 220761 240 0 FreeSans 560 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 77092 -400 77148 240 0 FreeSans 560 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 222478 -400 222534 240 0 FreeSans 560 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 224251 -400 224307 240 0 FreeSans 560 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 226024 -400 226080 240 0 FreeSans 560 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 227797 -400 227853 240 0 FreeSans 560 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 229570 -400 229626 240 0 FreeSans 560 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 231343 -400 231399 240 0 FreeSans 560 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 233116 -400 233172 240 0 FreeSans 560 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 234889 -400 234945 240 0 FreeSans 560 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 236662 -400 236718 240 0 FreeSans 560 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 238435 -400 238491 240 0 FreeSans 560 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 78865 -400 78921 240 0 FreeSans 560 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 63499 -400 63555 240 0 FreeSans 560 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 240799 -400 240855 240 0 FreeSans 560 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 242572 -400 242628 240 0 FreeSans 560 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 244345 -400 244401 240 0 FreeSans 560 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 246118 -400 246174 240 0 FreeSans 560 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 247891 -400 247947 240 0 FreeSans 560 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 249664 -400 249720 240 0 FreeSans 560 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 251437 -400 251493 240 0 FreeSans 560 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 253210 -400 253266 240 0 FreeSans 560 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 254983 -400 255039 240 0 FreeSans 560 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 256756 -400 256812 240 0 FreeSans 560 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 81229 -400 81285 240 0 FreeSans 560 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 258529 -400 258585 240 0 FreeSans 560 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 260302 -400 260358 240 0 FreeSans 560 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 262075 -400 262131 240 0 FreeSans 560 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 263848 -400 263904 240 0 FreeSans 560 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 265621 -400 265677 240 0 FreeSans 560 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 267394 -400 267450 240 0 FreeSans 560 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 269167 -400 269223 240 0 FreeSans 560 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 270940 -400 270996 240 0 FreeSans 560 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 272713 -400 272769 240 0 FreeSans 560 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 274486 -400 274542 240 0 FreeSans 560 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 83002 -400 83058 240 0 FreeSans 560 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 276259 -400 276315 240 0 FreeSans 560 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 278032 -400 278088 240 0 FreeSans 560 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 279805 -400 279861 240 0 FreeSans 560 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 281578 -400 281634 240 0 FreeSans 560 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 283351 -400 283407 240 0 FreeSans 560 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 285124 -400 285180 240 0 FreeSans 560 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 286897 -400 286953 240 0 FreeSans 560 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 288670 -400 288726 240 0 FreeSans 560 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 84775 -400 84831 240 0 FreeSans 560 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 86548 -400 86604 240 0 FreeSans 560 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 88321 -400 88377 240 0 FreeSans 560 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 90094 -400 90150 240 0 FreeSans 560 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 91867 -400 91923 240 0 FreeSans 560 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 93640 -400 93696 240 0 FreeSans 560 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 95413 -400 95469 240 0 FreeSans 560 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 97186 -400 97242 240 0 FreeSans 560 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 65272 -400 65328 240 0 FreeSans 560 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 98959 -400 99015 240 0 FreeSans 560 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 100732 -400 100788 240 0 FreeSans 560 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 102505 -400 102561 240 0 FreeSans 560 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 104278 -400 104334 240 0 FreeSans 560 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 106051 -400 106107 240 0 FreeSans 560 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 107824 -400 107880 240 0 FreeSans 560 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 109597 -400 109653 240 0 FreeSans 560 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 111370 -400 111426 240 0 FreeSans 560 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 113143 -400 113199 240 0 FreeSans 560 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 114916 -400 114972 240 0 FreeSans 560 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 67045 -400 67101 240 0 FreeSans 560 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 116689 -400 116745 240 0 FreeSans 560 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 118462 -400 118518 240 0 FreeSans 560 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 120235 -400 120291 240 0 FreeSans 560 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 122008 -400 122064 240 0 FreeSans 560 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 123781 -400 123837 240 0 FreeSans 560 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 125554 -400 125610 240 0 FreeSans 560 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 127327 -400 127383 240 0 FreeSans 560 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 129100 -400 129156 240 0 FreeSans 560 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 130873 -400 130929 240 0 FreeSans 560 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 132646 -400 132702 240 0 FreeSans 560 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 68818 -400 68874 240 0 FreeSans 560 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 134419 -400 134475 240 0 FreeSans 560 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 136192 -400 136248 240 0 FreeSans 560 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 137965 -400 138021 240 0 FreeSans 560 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 139738 -400 139794 240 0 FreeSans 560 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 141511 -400 141567 240 0 FreeSans 560 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 143284 -400 143340 240 0 FreeSans 560 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 145057 -400 145113 240 0 FreeSans 560 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 146830 -400 146886 240 0 FreeSans 560 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 148603 -400 148659 240 0 FreeSans 560 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 150376 -400 150432 240 0 FreeSans 560 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 70591 -400 70647 240 0 FreeSans 560 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 152149 -400 152205 240 0 FreeSans 560 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 153922 -400 153978 240 0 FreeSans 560 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 155695 -400 155751 240 0 FreeSans 560 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 157468 -400 157524 240 0 FreeSans 560 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 159241 -400 159297 240 0 FreeSans 560 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 161014 -400 161070 240 0 FreeSans 560 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 162787 -400 162843 240 0 FreeSans 560 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 164560 -400 164616 240 0 FreeSans 560 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 166333 -400 166389 240 0 FreeSans 560 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 168106 -400 168162 240 0 FreeSans 560 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 72364 -400 72420 240 0 FreeSans 560 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 169879 -400 169935 240 0 FreeSans 560 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 171652 -400 171708 240 0 FreeSans 560 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 173425 -400 173481 240 0 FreeSans 560 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 175198 -400 175254 240 0 FreeSans 560 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 176971 -400 177027 240 0 FreeSans 560 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 178744 -400 178800 240 0 FreeSans 560 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 180517 -400 180573 240 0 FreeSans 560 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 182290 -400 182346 240 0 FreeSans 560 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 184063 -400 184119 240 0 FreeSans 560 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 185836 -400 185892 240 0 FreeSans 560 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 74137 -400 74193 240 0 FreeSans 560 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 187609 -400 187665 240 0 FreeSans 560 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 189382 -400 189438 240 0 FreeSans 560 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 191155 -400 191211 240 0 FreeSans 560 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 192928 -400 192984 240 0 FreeSans 560 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 194701 -400 194757 240 0 FreeSans 560 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 196474 -400 196530 240 0 FreeSans 560 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 198247 -400 198303 240 0 FreeSans 560 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 200020 -400 200076 240 0 FreeSans 560 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 201793 -400 201849 240 0 FreeSans 560 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 203566 -400 203622 240 0 FreeSans 560 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 75910 -400 75966 240 0 FreeSans 560 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 205339 -400 205395 240 0 FreeSans 560 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 207112 -400 207168 240 0 FreeSans 560 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 208885 -400 208941 240 0 FreeSans 560 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 210658 -400 210714 240 0 FreeSans 560 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 212431 -400 212487 240 0 FreeSans 560 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 214204 -400 214260 240 0 FreeSans 560 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 215977 -400 216033 240 0 FreeSans 560 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 217750 -400 217806 240 0 FreeSans 560 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 219523 -400 219579 240 0 FreeSans 560 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 221296 -400 221352 240 0 FreeSans 560 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 77683 -400 77739 240 0 FreeSans 560 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 223069 -400 223125 240 0 FreeSans 560 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 224842 -400 224898 240 0 FreeSans 560 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 226615 -400 226671 240 0 FreeSans 560 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 228388 -400 228444 240 0 FreeSans 560 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 230161 -400 230217 240 0 FreeSans 560 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 231934 -400 231990 240 0 FreeSans 560 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 233707 -400 233763 240 0 FreeSans 560 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 235480 -400 235536 240 0 FreeSans 560 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 237253 -400 237309 240 0 FreeSans 560 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 239026 -400 239082 240 0 FreeSans 560 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 79456 -400 79512 240 0 FreeSans 560 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 64090 -400 64146 240 0 FreeSans 560 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 241390 -400 241446 240 0 FreeSans 560 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 243163 -400 243219 240 0 FreeSans 560 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 244936 -400 244992 240 0 FreeSans 560 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 246709 -400 246765 240 0 FreeSans 560 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 248482 -400 248538 240 0 FreeSans 560 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 250255 -400 250311 240 0 FreeSans 560 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 252028 -400 252084 240 0 FreeSans 560 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 253801 -400 253857 240 0 FreeSans 560 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 255574 -400 255630 240 0 FreeSans 560 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 257347 -400 257403 240 0 FreeSans 560 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 81820 -400 81876 240 0 FreeSans 560 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 259120 -400 259176 240 0 FreeSans 560 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 260893 -400 260949 240 0 FreeSans 560 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 262666 -400 262722 240 0 FreeSans 560 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 264439 -400 264495 240 0 FreeSans 560 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 266212 -400 266268 240 0 FreeSans 560 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 267985 -400 268041 240 0 FreeSans 560 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 269758 -400 269814 240 0 FreeSans 560 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 271531 -400 271587 240 0 FreeSans 560 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 273304 -400 273360 240 0 FreeSans 560 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 275077 -400 275133 240 0 FreeSans 560 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 83593 -400 83649 240 0 FreeSans 560 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 276850 -400 276906 240 0 FreeSans 560 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 278623 -400 278679 240 0 FreeSans 560 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 280396 -400 280452 240 0 FreeSans 560 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 282169 -400 282225 240 0 FreeSans 560 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 283942 -400 283998 240 0 FreeSans 560 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 285715 -400 285771 240 0 FreeSans 560 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 287488 -400 287544 240 0 FreeSans 560 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 289261 -400 289317 240 0 FreeSans 560 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 85366 -400 85422 240 0 FreeSans 560 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 87139 -400 87195 240 0 FreeSans 560 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 88912 -400 88968 240 0 FreeSans 560 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 90685 -400 90741 240 0 FreeSans 560 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 92458 -400 92514 240 0 FreeSans 560 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 94231 -400 94287 240 0 FreeSans 560 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 96004 -400 96060 240 0 FreeSans 560 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 97777 -400 97833 240 0 FreeSans 560 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 65863 -400 65919 240 0 FreeSans 560 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 99550 -400 99606 240 0 FreeSans 560 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 101323 -400 101379 240 0 FreeSans 560 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 103096 -400 103152 240 0 FreeSans 560 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 104869 -400 104925 240 0 FreeSans 560 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 106642 -400 106698 240 0 FreeSans 560 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 108415 -400 108471 240 0 FreeSans 560 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 110188 -400 110244 240 0 FreeSans 560 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 111961 -400 112017 240 0 FreeSans 560 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 113734 -400 113790 240 0 FreeSans 560 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 115507 -400 115563 240 0 FreeSans 560 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 67636 -400 67692 240 0 FreeSans 560 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 117280 -400 117336 240 0 FreeSans 560 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 119053 -400 119109 240 0 FreeSans 560 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 120826 -400 120882 240 0 FreeSans 560 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 122599 -400 122655 240 0 FreeSans 560 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 124372 -400 124428 240 0 FreeSans 560 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 126145 -400 126201 240 0 FreeSans 560 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 127918 -400 127974 240 0 FreeSans 560 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 129691 -400 129747 240 0 FreeSans 560 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 131464 -400 131520 240 0 FreeSans 560 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 133237 -400 133293 240 0 FreeSans 560 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 69409 -400 69465 240 0 FreeSans 560 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 135010 -400 135066 240 0 FreeSans 560 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 136783 -400 136839 240 0 FreeSans 560 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 138556 -400 138612 240 0 FreeSans 560 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 140329 -400 140385 240 0 FreeSans 560 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 142102 -400 142158 240 0 FreeSans 560 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 143875 -400 143931 240 0 FreeSans 560 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 145648 -400 145704 240 0 FreeSans 560 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 147421 -400 147477 240 0 FreeSans 560 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 149194 -400 149250 240 0 FreeSans 560 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 150967 -400 151023 240 0 FreeSans 560 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 71182 -400 71238 240 0 FreeSans 560 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 152740 -400 152796 240 0 FreeSans 560 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 154513 -400 154569 240 0 FreeSans 560 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 156286 -400 156342 240 0 FreeSans 560 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 158059 -400 158115 240 0 FreeSans 560 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 159832 -400 159888 240 0 FreeSans 560 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 161605 -400 161661 240 0 FreeSans 560 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 163378 -400 163434 240 0 FreeSans 560 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 165151 -400 165207 240 0 FreeSans 560 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 166924 -400 166980 240 0 FreeSans 560 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 168697 -400 168753 240 0 FreeSans 560 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 72955 -400 73011 240 0 FreeSans 560 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 170470 -400 170526 240 0 FreeSans 560 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 172243 -400 172299 240 0 FreeSans 560 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 174016 -400 174072 240 0 FreeSans 560 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 175789 -400 175845 240 0 FreeSans 560 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 177562 -400 177618 240 0 FreeSans 560 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 179335 -400 179391 240 0 FreeSans 560 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 181108 -400 181164 240 0 FreeSans 560 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 182881 -400 182937 240 0 FreeSans 560 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 184654 -400 184710 240 0 FreeSans 560 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 186427 -400 186483 240 0 FreeSans 560 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 74728 -400 74784 240 0 FreeSans 560 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 188200 -400 188256 240 0 FreeSans 560 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 189973 -400 190029 240 0 FreeSans 560 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 191746 -400 191802 240 0 FreeSans 560 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 193519 -400 193575 240 0 FreeSans 560 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 195292 -400 195348 240 0 FreeSans 560 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 197065 -400 197121 240 0 FreeSans 560 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 198838 -400 198894 240 0 FreeSans 560 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 200611 -400 200667 240 0 FreeSans 560 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 202384 -400 202440 240 0 FreeSans 560 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 204157 -400 204213 240 0 FreeSans 560 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 76501 -400 76557 240 0 FreeSans 560 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 205930 -400 205986 240 0 FreeSans 560 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 207703 -400 207759 240 0 FreeSans 560 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 209476 -400 209532 240 0 FreeSans 560 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 211249 -400 211305 240 0 FreeSans 560 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 213022 -400 213078 240 0 FreeSans 560 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 214795 -400 214851 240 0 FreeSans 560 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 216568 -400 216624 240 0 FreeSans 560 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 218341 -400 218397 240 0 FreeSans 560 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 220114 -400 220170 240 0 FreeSans 560 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 221887 -400 221943 240 0 FreeSans 560 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 78274 -400 78330 240 0 FreeSans 560 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 223660 -400 223716 240 0 FreeSans 560 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 225433 -400 225489 240 0 FreeSans 560 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 227206 -400 227262 240 0 FreeSans 560 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 228979 -400 229035 240 0 FreeSans 560 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 230752 -400 230808 240 0 FreeSans 560 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 232525 -400 232581 240 0 FreeSans 560 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 234298 -400 234354 240 0 FreeSans 560 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 236071 -400 236127 240 0 FreeSans 560 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 237844 -400 237900 240 0 FreeSans 560 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 239617 -400 239673 240 0 FreeSans 560 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 80047 -400 80103 240 0 FreeSans 560 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 289852 -400 289908 240 0 FreeSans 560 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 290443 -400 290499 240 0 FreeSans 560 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 291034 -400 291090 240 0 FreeSans 560 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 291625 -400 291681 240 0 FreeSans 560 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 291170 319892 292400 322292 0 FreeSans 560 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 291170 314892 292400 317292 0 FreeSans 560 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 321921 830 324321 0 FreeSans 560 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 316921 830 319321 0 FreeSans 560 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 291170 270281 292400 272681 0 FreeSans 560 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 291170 275281 292400 277681 0 FreeSans 560 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 291170 117615 292400 120015 0 FreeSans 560 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 291170 112615 292400 115015 0 FreeSans 560 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 102444 830 104844 0 FreeSans 560 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 107444 830 109844 0 FreeSans 560 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 260297 351170 262697 352400 0 FreeSans 960 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 255297 351170 257697 352400 0 FreeSans 960 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 291170 73415 292400 75815 0 FreeSans 560 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 291170 68415 292400 70815 0 FreeSans 560 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 279721 830 282121 0 FreeSans 560 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 274721 830 277121 0 FreeSans 560 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 291170 95715 292400 98115 0 FreeSans 560 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 291170 90715 292400 93115 0 FreeSans 560 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 86444 830 88844 0 FreeSans 560 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 81444 830 83844 0 FreeSans 560 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 262 -400 318 240 0 FreeSans 560 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 853 -400 909 240 0 FreeSans 560 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 1444 -400 1500 240 0 FreeSans 560 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 3808 -400 3864 240 0 FreeSans 560 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 23902 -400 23958 240 0 FreeSans 560 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 25675 -400 25731 240 0 FreeSans 560 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 27448 -400 27504 240 0 FreeSans 560 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 29221 -400 29277 240 0 FreeSans 560 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 30994 -400 31050 240 0 FreeSans 560 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 32767 -400 32823 240 0 FreeSans 560 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 34540 -400 34596 240 0 FreeSans 560 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 36313 -400 36369 240 0 FreeSans 560 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 38086 -400 38142 240 0 FreeSans 560 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 39859 -400 39915 240 0 FreeSans 560 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 6172 -400 6228 240 0 FreeSans 560 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 41632 -400 41688 240 0 FreeSans 560 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 43405 -400 43461 240 0 FreeSans 560 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 45178 -400 45234 240 0 FreeSans 560 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 46951 -400 47007 240 0 FreeSans 560 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 48724 -400 48780 240 0 FreeSans 560 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 50497 -400 50553 240 0 FreeSans 560 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 52270 -400 52326 240 0 FreeSans 560 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 54043 -400 54099 240 0 FreeSans 560 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 55816 -400 55872 240 0 FreeSans 560 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 57589 -400 57645 240 0 FreeSans 560 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 8536 -400 8592 240 0 FreeSans 560 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 59362 -400 59418 240 0 FreeSans 560 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 61135 -400 61191 240 0 FreeSans 560 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 10900 -400 10956 240 0 FreeSans 560 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 13264 -400 13320 240 0 FreeSans 560 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 15037 -400 15093 240 0 FreeSans 560 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 16810 -400 16866 240 0 FreeSans 560 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 18583 -400 18639 240 0 FreeSans 560 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 20356 -400 20412 240 0 FreeSans 560 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 22129 -400 22185 240 0 FreeSans 560 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 2035 -400 2091 240 0 FreeSans 560 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 4399 -400 4455 240 0 FreeSans 560 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 24493 -400 24549 240 0 FreeSans 560 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 26266 -400 26322 240 0 FreeSans 560 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 28039 -400 28095 240 0 FreeSans 560 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 29812 -400 29868 240 0 FreeSans 560 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 31585 -400 31641 240 0 FreeSans 560 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 33358 -400 33414 240 0 FreeSans 560 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 35131 -400 35187 240 0 FreeSans 560 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 36904 -400 36960 240 0 FreeSans 560 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 38677 -400 38733 240 0 FreeSans 560 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 40450 -400 40506 240 0 FreeSans 560 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 6763 -400 6819 240 0 FreeSans 560 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 42223 -400 42279 240 0 FreeSans 560 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 43996 -400 44052 240 0 FreeSans 560 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 45769 -400 45825 240 0 FreeSans 560 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 47542 -400 47598 240 0 FreeSans 560 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 49315 -400 49371 240 0 FreeSans 560 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 51088 -400 51144 240 0 FreeSans 560 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 52861 -400 52917 240 0 FreeSans 560 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 54634 -400 54690 240 0 FreeSans 560 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 56407 -400 56463 240 0 FreeSans 560 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 58180 -400 58236 240 0 FreeSans 560 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 9127 -400 9183 240 0 FreeSans 560 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 59953 -400 60009 240 0 FreeSans 560 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 61726 -400 61782 240 0 FreeSans 560 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 11491 -400 11547 240 0 FreeSans 560 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 13855 -400 13911 240 0 FreeSans 560 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 15628 -400 15684 240 0 FreeSans 560 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 17401 -400 17457 240 0 FreeSans 560 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 19174 -400 19230 240 0 FreeSans 560 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 20947 -400 21003 240 0 FreeSans 560 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 22720 -400 22776 240 0 FreeSans 560 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 4990 -400 5046 240 0 FreeSans 560 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 25084 -400 25140 240 0 FreeSans 560 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 26857 -400 26913 240 0 FreeSans 560 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 28630 -400 28686 240 0 FreeSans 560 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 30403 -400 30459 240 0 FreeSans 560 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 32176 -400 32232 240 0 FreeSans 560 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 33949 -400 34005 240 0 FreeSans 560 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 35722 -400 35778 240 0 FreeSans 560 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 37495 -400 37551 240 0 FreeSans 560 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 39268 -400 39324 240 0 FreeSans 560 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 41041 -400 41097 240 0 FreeSans 560 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 7354 -400 7410 240 0 FreeSans 560 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 42814 -400 42870 240 0 FreeSans 560 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 44587 -400 44643 240 0 FreeSans 560 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 46360 -400 46416 240 0 FreeSans 560 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 48133 -400 48189 240 0 FreeSans 560 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 49906 -400 49962 240 0 FreeSans 560 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 51679 -400 51735 240 0 FreeSans 560 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 53452 -400 53508 240 0 FreeSans 560 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 55225 -400 55281 240 0 FreeSans 560 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 56998 -400 57054 240 0 FreeSans 560 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 58771 -400 58827 240 0 FreeSans 560 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 9718 -400 9774 240 0 FreeSans 560 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 60544 -400 60600 240 0 FreeSans 560 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 62317 -400 62373 240 0 FreeSans 560 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 12082 -400 12138 240 0 FreeSans 560 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 14446 -400 14502 240 0 FreeSans 560 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 16219 -400 16275 240 0 FreeSans 560 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 17992 -400 18048 240 0 FreeSans 560 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 19765 -400 19821 240 0 FreeSans 560 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 21538 -400 21594 240 0 FreeSans 560 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 23311 -400 23367 240 0 FreeSans 560 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 5581 -400 5637 240 0 FreeSans 560 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 7945 -400 8001 240 0 FreeSans 560 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 10309 -400 10365 240 0 FreeSans 560 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 12673 -400 12729 240 0 FreeSans 560 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 2626 -400 2682 240 0 FreeSans 560 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 3217 -400 3273 240 0 FreeSans 560 90 0 0 wbs_we_i
+port 677 nsew signal input
+<< properties >>
+string FIXED_BBOX 0 0 292000 352000
+<< end >>
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/example_por.v
deleted file mode 100644
index d318fba..0000000
--- a/verilog/rtl/example_por.v
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-`timescale 1 ns / 1 ps
-
-// This is just a copy of simple_por.v from the Caravel project, used
-// as an analog user project example.
-
-module example_por(
-`ifdef USE_POWER_PINS
- inout vdd3v3,
- inout vdd1v8,
- inout vss,
-`endif
- output porb_h,
- output porb_l,
- output por_l
-);
-
- wire mid, porb_h;
- reg inode;
-
- // This is a behavioral model! Actual circuit is a resitor dumping
- // current (slowly) from vdd3v3 onto a capacitor, and this fed into
- // two schmitt triggers for strong hysteresis/glitch tolerance.
-
- initial begin
- inode <= 1'b0;
- end
-
- // Emulate current source on capacitor as a 500ns delay either up or
- // down. Note that this is sped way up for verilog simulation; the
- // actual circuit is set to a 15ms delay.
-
- always @(posedge vdd3v3) begin
- #500 inode <= 1'b1;
- end
- always @(negedge vdd3v3) begin
- #500 inode <= 1'b0;
- end
-
- // Instantiate two shmitt trigger buffers in series
-
- sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
-`ifdef USE_POWER_PINS
- .VPWR(vdd3v3),
- .VGND(vss),
- .VPB(vdd3v3),
- .VNB(vss),
-`endif
- .A(inode),
- .X(mid)
- );
-
- sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
-`ifdef USE_POWER_PINS
- .VPWR(vdd3v3),
- .VGND(vss),
- .VPB(vdd3v3),
- .VNB(vss),
-`endif
- .A(mid),
- .X(porb_h)
- );
-
- sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
-`ifdef USE_POWER_PINS
- .VPWR(vdd3v3),
- .VPB(vdd3v3),
- .LVPWR(vdd1v8),
- .VNB(vss),
- .VGND(vss),
-`endif
- .A(porb_h),
- .X(porb_l)
- );
-
- // since this is behavioral anyway, but this should be
- // replaced by a proper inverter
- assign por_l = ~porb_l;
-endmodule
-`default_nettype wire
diff --git a/verilog/rtl/sky130_hilas_TopLevelProtectStructure.v b/verilog/rtl/sky130_hilas_TopLevelProtectStructure.v
deleted file mode 100644
index 4f29dd3..0000000
--- a/verilog/rtl/sky130_hilas_TopLevelProtectStructure.v
+++ /dev/null
@@ -1,287 +0,0 @@
-/** Copyright 2020 The Hilas PDK Authors
- *
- * This file is part of HILAS.
- *
- * HILAS is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * HILAS is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with HILAS. If not, see <https://www.gnu.org/licenses/>.
- *
- * Licensed under the Lesser General Public License, Version 3.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * https://www.gnu.org/licenses/lgpl-3.0.en.html
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * SPDX-License-Identifier: LGPL-3.0
- *
- *
- */
-`ifndef SKY130_HILAS_TOPLEVELTESTSTRUCTURE
-`define SKY130_HILAS_TOPLEVELTESTSTRUCTURE
-
-/**
- * sky130_hilas_TopLevelTestStructure: top level test structure
- *
- * Verilog wrapper for sky130_hilas_TopLevelTestStructure.
- *
- * WARNING: This file is autogenerated, do not modify directly!
- */
-
-`timescale 1ns / 1ps
-`default_nettype none
-
-
-`ifdef USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TopLevelTestStructure (
- DIG23,
- DIG22,
- DIG21,
- DIG29,
- DIG28,
- DIG27,
- DIG26,
- DIG25,
- DIG20,
- DIG19,
- DIG18,
- DIG17,
- DIG16,
- DIG15,
- DIG14,
- DIG13,
- DIG12,
- DIG11,
- DIG10,
- DIG09,
- DIG08,
- DIG07,
- DIG06,
- DIG05,
- DIG04,
- DIG03,
- DIG02,
- DIG01,
- GENERALGATE02,
- DRAINOUT,
- ROWTERM2,
- COLUMN2,
- COLUMN1,
- GATE2,
- DRAININJECT,
- VTUN,
- VREFCHAR,
- CHAROUTPUT,
- LARGECAPACITOR,
- DRAIN6N,
- DRAIN6P,
- DRAIN5P,
- DRAIN4P,
- DRAIN5N,
- DRAIN4N,
- DRAIN3P,
- DRAIN2P,
- DRAIN3N,
- SOURCEN,
- SOURCEP,
- GATE1,
- VINJ,
- VGND,
- VPWR,
- VNB,
- VPB
-);
- inout DIG23;
- inout DIG22;
- inout DIG21;
- inout DIG29;
- inout DIG28;
- inout DIG27;
- inout DIG26;
- inout DIG25;
- inout DIG20;
- inout DIG19;
- inout DIG18;
- inout DIG17;
- inout DIG16;
- inout DIG15;
- inout DIG14;
- inout DIG13;
- inout DIG12;
- inout DIG11;
- inout DIG10;
- inout DIG09;
- inout DIG08;
- inout DIG07;
- inout DIG06;
- inout DIG05;
- inout DIG04;
- inout DIG03;
- inout DIG02;
- inout DIG01;
- inout GENERALGATE02;
- inout DRAINOUT;
- inout ROWTERM2;
- inout COLUMN2;
- inout COLUMN1;
- inout GATE2;
- inout DRAININJECT;
- inout VTUN;
- inout VREFCHAR;
- inout CHAROUTPUT;
- inout LARGECAPACITOR;
- inout DRAIN6N;
- inout DRAIN6P;
- inout DRAIN5P;
- inout DRAIN4P;
- inout DRAIN5N;
- inout DRAIN4N;
- inout DRAIN3P;
- inout DRAIN2P;
- inout DRAIN3N;
- inout SOURCEN;
- inout SOURCEP;
- inout GATE1;
- inout VINJ;
- inout VGND;
- inout VPWR;
- inout VNB;
- inout VPB;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`else // If not USE_POWER_PINS
-/*********************************************************/
-
-`celldefine
-module sky130_hilas_TopLevelTestStructure (
- DIG23,
- DIG22,
- DIG21,
- DIG29,
- DIG28,
- DIG27,
- DIG26,
- DIG25,
- DIG20,
- DIG19,
- DIG18,
- DIG17,
- DIG16,
- DIG15,
- DIG14,
- DIG13,
- DIG12,
- DIG11,
- DIG10,
- DIG09,
- DIG08,
- DIG07,
- DIG06,
- DIG05,
- DIG04,
- DIG03,
- DIG02,
- DIG01,
- GENERALGATE02,
- DRAINOUT,
- ROWTERM2,
- COLUMN2,
- COLUMN1,
- GATE2,
- DRAININJECT,
- VTUN,
- VREFCHAR,
- CHAROUTPUT,
- LARGECAPACITOR,
- DRAIN6N,
- DRAIN6P,
- DRAIN5P,
- DRAIN4P,
- DRAIN5N,
- DRAIN4N,
- DRAIN3P,
- DRAIN2P,
- DRAIN3N,
- SOURCEN,
- SOURCEP,
- GATE1,
- VINJ
-);
- inout DIG23;
- inout DIG22;
- inout DIG21;
- inout DIG29;
- inout DIG28;
- inout DIG27;
- inout DIG26;
- inout DIG25;
- inout DIG20;
- inout DIG19;
- inout DIG18;
- inout DIG17;
- inout DIG16;
- inout DIG15;
- inout DIG14;
- inout DIG13;
- inout DIG12;
- inout DIG11;
- inout DIG10;
- inout DIG09;
- inout DIG08;
- inout DIG07;
- inout DIG06;
- inout DIG05;
- inout DIG04;
- inout DIG03;
- inout DIG02;
- inout DIG01;
- inout GENERALGATE02;
- inout DRAINOUT;
- inout ROWTERM2;
- inout COLUMN2;
- inout COLUMN1;
- inout GATE2;
- inout DRAININJECT;
- inout VTUN;
- inout VREFCHAR;
- inout CHAROUTPUT;
- inout LARGECAPACITOR;
- inout DRAIN6N;
- inout DRAIN6P;
- inout DRAIN5P;
- inout DRAIN4P;
- inout DRAIN5N;
- inout DRAIN4N;
- inout DRAIN3P;
- inout DRAIN2P;
- inout DRAIN3N;
- inout SOURCEN;
- inout SOURCEP;
- inout GATE1;
- inout VINJ;
-endmodule
-`endcelldefine
-
-/*********************************************************/
-`endif // USE_POWER_PINS
-
-`default_nettype wire
-`endif // SKY130_HILAS_TOPLEVELTESTSTRUCTURE
diff --git a/verilog/rtl/sky130_hilas_sc.v b/verilog/rtl/sky130_hilas_sc.v
new file mode 100644
index 0000000..39b369d
--- /dev/null
+++ b/verilog/rtl/sky130_hilas_sc.v
@@ -0,0 +1,9832 @@
+/** Copyright 2020 The Hilas PDK Authors
+ *
+ * This file is part of HILAS.
+ *
+ * HILAS is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * HILAS is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with HILAS. If not, see <https://www.gnu.org/licenses/>.
+ *
+ * Licensed under the Lesser General Public License, Version 3.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * https://www.gnu.org/licenses/lgpl-3.0.en.html
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: LGPL-3.0
+ *
+ *
+ */
+
+
+
+
+`define USE_POWER_PINS 1
+
+`ifndef SKY130_HILAS_POLY2M1
+`define SKY130_HILAS_POLY2M1
+
+/**
+ * sky130_hilas_poly2m1: polysilicon layer to m1 contact
+ *
+ * Verilog wrapper for sky130_hilas_poly2m1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2m1 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2m1 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_POLY2M1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TA2CELL_1FG_STRONG
+`define SKY130_HILAS_TA2CELL_1FG_STRONG
+
+/**
+ * sky130_hilas_TA2Cell_1FG_Strong: Two transimpedance amps with one (of two) amplifiers using floating-gate inputs. FG amplifier with normal linear range.
+ *
+ * Verilog wrapper for sky130_hilas_TA2Cell_1FG_Strong.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_1FG_Strong (
+ VTUN,
+ PROG,
+ GATE1,
+ VIN11,
+ VINJ,
+ VIN22,
+ VIN21,
+ OUTPUT2,
+ OUTPUT1,
+ GATESEL1,
+ GATESEL2,
+ DRAIN1,
+ DRAIN2,
+ VIN12,
+ GATE2,
+ RUN,
+ VPWR,
+ VGND,
+ VNB,
+ VPB
+);
+ inout VTUN;
+ inout PROG;
+ inout GATE1;
+ inout VIN11;
+ inout VINJ;
+ inout VIN22;
+ inout VIN21;
+ inout OUTPUT2;
+ inout OUTPUT1;
+ inout GATESEL1;
+ inout GATESEL2;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout VIN12;
+ inout GATE2;
+ inout RUN;
+ inout VPWR;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_1FG_Strong (
+ VTUN,
+ PROG,
+ GATE1,
+ VIN11,
+ VINJ,
+ VIN22,
+ VIN21,
+ OUTPUT2,
+ OUTPUT1,
+ GATESEL1,
+ GATESEL2,
+ DRAIN1,
+ DRAIN2,
+ VIN12,
+ GATE2,
+ RUN
+);
+ inout VTUN;
+ inout PROG;
+ inout GATE1;
+ inout VIN11;
+ inout VINJ;
+ inout VIN22;
+ inout VIN21;
+ inout OUTPUT2;
+ inout OUTPUT1;
+ inout GATESEL1;
+ inout GATESEL2;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout VIN12;
+ inout GATE2;
+ inout RUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TA2CELL_1FG_STRONG
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NMIRROR03
+`define SKY130_HILAS_NMIRROR03
+
+/**
+ * sky130_hilas_nMirror03: None
+ *
+ * Verilog wrapper for sky130_hilas_nMirror03.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nMirror03 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nMirror03 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_NMIRROR03
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETMIRROR
+`define SKY130_HILAS_PFETMIRROR
+
+/**
+ * sky130_hilas_pFETmirror: pFET current mirror
+ *
+ * Verilog wrapper for sky130_hilas_pFETmirror.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmirror (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmirror (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETMIRROR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGCHARACTERIZATION01
+`define SKY130_HILAS_FGCHARACTERIZATION01
+
+/**
+ * sky130_hilas_FGcharacterization01: FG test strucure that uses a capacitor around a transconductance amplifier
+ *
+ * Verilog wrapper for sky130_hilas_FGcharacterization01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGcharacterization01 (
+ VTUN,
+ GATE1,
+ GATE3,
+ VTUNOVERLAP01,
+ GATE2,
+ GATE4,
+ LARGECAPACITOR,
+ VINJ,
+ OUTPUT,
+ VREF,
+ VBIAS,
+ DRAIN1,
+ SOURCE1,
+ VGND,
+ VNB,
+ VPB
+);
+ inout VTUN;
+ inout GATE1;
+ inout GATE3;
+ inout VTUNOVERLAP01;
+ inout GATE2;
+ inout GATE4;
+ inout LARGECAPACITOR;
+ inout VINJ;
+ inout OUTPUT;
+ inout VREF;
+ inout VBIAS;
+ inout DRAIN1;
+ inout SOURCE1;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGcharacterization01 (
+ VTUN,
+ GATE1,
+ GATE3,
+ VTUNOVERLAP01,
+ GATE2,
+ GATE4,
+ LARGECAPACITOR,
+ VINJ,
+ OUTPUT,
+ VREF,
+ VBIAS,
+ DRAIN1,
+ SOURCE1
+);
+ inout VTUN;
+ inout GATE1;
+ inout GATE3;
+ inout VTUNOVERLAP01;
+ inout GATE2;
+ inout GATE4;
+ inout LARGECAPACITOR;
+ inout VINJ;
+ inout OUTPUT;
+ inout VREF;
+ inout VBIAS;
+ inout DRAIN1;
+ inout SOURCE1;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_FGCHARACTERIZATION01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFET03
+`define SKY130_HILAS_NFET03
+
+/**
+ * sky130_hilas_nFET03: None
+ *
+ * Verilog wrapper for sky130_hilas_nFET03.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFET03 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFET03 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_NFET03
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NOVERLAPCAP01
+`define SKY130_HILAS_NOVERLAPCAP01
+
+/**
+ * sky130_hilas_nOverlapCap01: overlap capacitor based capacitor (nFET)
+ *
+ * Verilog wrapper for sky130_hilas_nOverlapCap01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nOverlapCap01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nOverlapCap01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_NOVERLAPCAP01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01C
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01C
+
+/**
+ * sky130_hilas_DAC6TransistorStack01c: None
+ *
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01c.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01c (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01c (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DAC6TRANSISTORSTACK01C
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATESINGLE01PART2
+`define SKY130_HILAS_TGATESINGLE01PART2
+
+/**
+ * sky130_hilas_TgateSingle01Part2: None
+ *
+ * Verilog wrapper for sky130_hilas_TgateSingle01Part2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01Part2 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01Part2 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TGATESINGLE01PART2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TA2CELL_NOFG
+`define SKY130_HILAS_TA2CELL_NOFG
+
+/**
+ * sky130_hilas_TA2Cell_NoFG: Two transimpedane amplifiers with no floating-gate inputs.
+ *
+ * Verilog wrapper for sky130_hilas_TA2Cell_NoFG.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_NoFG (
+ COLSEL1,
+ VIN12,
+ VIN21,
+ VIN22,
+ OUTPUT1,
+ OUTPUT2,
+ DRAIN1,
+ DRAIN2,
+ VTUN,
+ GATE1,
+ VINJ,
+ VIN11,
+ VGND,
+ VPWR,
+ VNB,
+ VPB
+);
+ inout COLSEL1;
+ inout VIN12;
+ inout VIN21;
+ inout VIN22;
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout VTUN;
+ inout GATE1;
+ inout VINJ;
+ inout VIN11;
+ inout VGND;
+ inout VPWR;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_NoFG (
+ COLSEL1,
+ VIN12,
+ VIN21,
+ VIN22,
+ OUTPUT1,
+ OUTPUT2,
+ DRAIN1,
+ DRAIN2,
+ VTUN,
+ GATE1,
+ VINJ,
+ VIN11
+);
+ inout COLSEL1;
+ inout VIN12;
+ inout VIN21;
+ inout VIN22;
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout VTUN;
+ inout GATE1;
+ inout VINJ;
+ inout VIN11;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TA2CELL_NOFG
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TOPLEVELTEXTSTRUCTURE
+`define SKY130_HILAS_TOPLEVELTEXTSTRUCTURE
+
+/**
+ * sky130_hilas_TopLevelTextStructure: top level test structure
+ *
+ * Verilog wrapper for sky130_hilas_TopLevelTextStructure.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TopLevelTextStructure (
+ DIG23,
+ DIG22,
+ DIG21,
+ DIG29,
+ DIG28,
+ DIG27,
+ DIG26,
+ DIG25,
+ DIG20,
+ DIG19,
+ DIG18,
+ DIG17,
+ DIG16,
+ DIG15,
+ DIG14,
+ DIG13,
+ DIG12,
+ DIG11,
+ DIG10,
+ DIG09,
+ DIG08,
+ DIG07,
+ DIG06,
+ DIG05,
+ DIG04,
+ DIG03,
+ DIG02,
+ DIG01,
+ GENERALGATE02,
+ DRAINOUT,
+ ROWTERM2,
+ COLUMN2,
+ COLUMN1,
+ GATE2,
+ DRAININJECT,
+ VTUN,
+ VREFCHAR,
+ CHAROUTPUT,
+ LARGECAPACITOR,
+ DRAIN6N,
+ DRAIN6P,
+ DRAIN5P,
+ DARIN4P,
+ DRAIN5N,
+ DRAIN4N,
+ DRAIN3P,
+ DRAIN2P,
+ DRAIN3N,
+ SOURCEN,
+ SOURCEP,
+ GATE1,
+ VINJ,
+ VGND,
+ VPWR,
+ VNB,
+ VPB
+);
+ inout DIG23;
+ inout DIG22;
+ inout DIG21;
+ inout DIG29;
+ inout DIG28;
+ inout DIG27;
+ inout DIG26;
+ inout DIG25;
+ inout DIG20;
+ inout DIG19;
+ inout DIG18;
+ inout DIG17;
+ inout DIG16;
+ inout DIG15;
+ inout DIG14;
+ inout DIG13;
+ inout DIG12;
+ inout DIG11;
+ inout DIG10;
+ inout DIG09;
+ inout DIG08;
+ inout DIG07;
+ inout DIG06;
+ inout DIG05;
+ inout DIG04;
+ inout DIG03;
+ inout DIG02;
+ inout DIG01;
+ inout GENERALGATE02;
+ inout DRAINOUT;
+ inout ROWTERM2;
+ inout COLUMN2;
+ inout COLUMN1;
+ inout GATE2;
+ inout DRAININJECT;
+ inout VTUN;
+ inout VREFCHAR;
+ inout CHAROUTPUT;
+ inout LARGECAPACITOR;
+ inout DRAIN6N;
+ inout DRAIN6P;
+ inout DRAIN5P;
+ inout DARIN4P;
+ inout DRAIN5N;
+ inout DRAIN4N;
+ inout DRAIN3P;
+ inout DRAIN2P;
+ inout DRAIN3N;
+ inout SOURCEN;
+ inout SOURCEP;
+ inout GATE1;
+ inout VINJ;
+ inout VGND;
+ inout VPWR;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TopLevelTextStructure (
+ DIG23,
+ DIG22,
+ DIG21,
+ DIG29,
+ DIG28,
+ DIG27,
+ DIG26,
+ DIG25,
+ DIG20,
+ DIG19,
+ DIG18,
+ DIG17,
+ DIG16,
+ DIG15,
+ DIG14,
+ DIG13,
+ DIG12,
+ DIG11,
+ DIG10,
+ DIG09,
+ DIG08,
+ DIG07,
+ DIG06,
+ DIG05,
+ DIG04,
+ DIG03,
+ DIG02,
+ DIG01,
+ GENERALGATE02,
+ DRAINOUT,
+ ROWTERM2,
+ COLUMN2,
+ COLUMN1,
+ GATE2,
+ DRAININJECT,
+ VTUN,
+ VREFCHAR,
+ CHAROUTPUT,
+ LARGECAPACITOR,
+ DRAIN6N,
+ DRAIN6P,
+ DRAIN5P,
+ DARIN4P,
+ DRAIN5N,
+ DRAIN4N,
+ DRAIN3P,
+ DRAIN2P,
+ DRAIN3N,
+ SOURCEN,
+ SOURCEP,
+ GATE1,
+ VINJ
+);
+ inout DIG23;
+ inout DIG22;
+ inout DIG21;
+ inout DIG29;
+ inout DIG28;
+ inout DIG27;
+ inout DIG26;
+ inout DIG25;
+ inout DIG20;
+ inout DIG19;
+ inout DIG18;
+ inout DIG17;
+ inout DIG16;
+ inout DIG15;
+ inout DIG14;
+ inout DIG13;
+ inout DIG12;
+ inout DIG11;
+ inout DIG10;
+ inout DIG09;
+ inout DIG08;
+ inout DIG07;
+ inout DIG06;
+ inout DIG05;
+ inout DIG04;
+ inout DIG03;
+ inout DIG02;
+ inout DIG01;
+ inout GENERALGATE02;
+ inout DRAINOUT;
+ inout ROWTERM2;
+ inout COLUMN2;
+ inout COLUMN1;
+ inout GATE2;
+ inout DRAININJECT;
+ inout VTUN;
+ inout VREFCHAR;
+ inout CHAROUTPUT;
+ inout LARGECAPACITOR;
+ inout DRAIN6N;
+ inout DRAIN6P;
+ inout DRAIN5P;
+ inout DARIN4P;
+ inout DRAIN5N;
+ inout DRAIN4N;
+ inout DRAIN3P;
+ inout DRAIN2P;
+ inout DRAIN3N;
+ inout SOURCEN;
+ inout SOURCEP;
+ inout GATE1;
+ inout VINJ;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TOPLEVELTEXTSTRUCTURE
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETLARGE
+`define SKY130_HILAS_PFETLARGE
+
+/**
+ * sky130_hilas_pFETLarge: Single Large (W/L=100) pFET Transistor
+ *
+ * Verilog wrapper for sky130_hilas_pFETLarge.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETLarge (
+ GATE,
+ SOURCE,
+ DRAIN,
+ WELL,
+ VNB,
+ VPB
+);
+ inout GATE;
+ inout SOURCE;
+ inout DRAIN;
+ inout WELL;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETLarge (
+ GATE,
+ SOURCE,
+ DRAIN,
+ WELL
+);
+ inout GATE;
+ inout SOURCE;
+ inout DRAIN;
+ inout WELL;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETLARGE
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_VINJINV2
+`define SKY130_HILAS_VINJINV2
+
+/**
+ * sky130_hilas_VinjInv2: logical inverter for VINJ-level voltages
+ *
+ * Verilog wrapper for sky130_hilas_VinjInv2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjInv2 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjInv2 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_VINJINV2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DECOUPVINJ00
+`define SKY130_HILAS_DECOUPVINJ00
+
+/**
+ * sky130_hilas_DecoupVinj00:
+ *
+ * Verilog wrapper for sky130_hilas_DecoupVinj00.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DecoupVinj00 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DecoupVinj00 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DECOUPVINJ00
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_LI2M2
+`define SKY130_HILAS_LI2M2
+
+/**
+ * sky130_hilas_li2m2: local interconnect to m2 contact
+ *
+ * Verilog wrapper for sky130_hilas_li2m2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_li2m2 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_li2m2 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_LI2M2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPACITORSIZE03
+`define SKY130_HILAS_CAPACITORSIZE03
+
+/**
+ * sky130_hilas_capacitorSize03: mid-large cap
+ *
+ * Verilog wrapper for sky130_hilas_capacitorSize03.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize03 (
+ CAPTERM02,
+ CAPTERM01,
+ VNB,
+ VPB
+);
+ inout CAPTERM02;
+ inout CAPTERM01;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize03 (
+ CAPTERM02,
+ CAPTERM01
+);
+ inout CAPTERM02;
+ inout CAPTERM01;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_CAPACITORSIZE03
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X1BIASCELL
+`define SKY130_HILAS_SWC4X1BIASCELL
+
+/**
+ * sky130_hilas_swc4x1BiasCell: 4x1 array of FG switch cell configured pFET as current sources
+ *
+ * Verilog wrapper for sky130_hilas_swc4x1BiasCell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1BiasCell (
+ ROW1,
+ ROW2,
+ ROW3,
+ ROW4,
+ VTUN,
+ GATE1,
+ VINJ,
+ COLSEL1,
+ DRAIN1,
+ DRAIN2,
+ DRAIN3,
+ DRAIN4,
+ VPWR,
+ VGND,
+ VNB,
+ VPB
+);
+ inout ROW1;
+ inout ROW2;
+ inout ROW3;
+ inout ROW4;
+ inout VTUN;
+ inout GATE1;
+ inout VINJ;
+ inout COLSEL1;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout DRAIN3;
+ inout DRAIN4;
+ inout VPWR;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1BiasCell (
+ ROW1,
+ ROW2,
+ ROW3,
+ ROW4,
+ VTUN,
+ GATE1,
+ VINJ,
+ COLSEL1,
+ DRAIN1,
+ DRAIN2,
+ DRAIN3,
+ DRAIN4
+);
+ inout ROW1;
+ inout ROW2;
+ inout ROW3;
+ inout ROW4;
+ inout VTUN;
+ inout GATE1;
+ inout VINJ;
+ inout COLSEL1;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout DRAIN3;
+ inout DRAIN4;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_SWC4X1BIASCELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_STEPUPDIGITALPART1
+`define SKY130_HILAS_STEPUPDIGITALPART1
+
+/**
+ * sky130_hilas_StepUpDigitalPart1: step-up level shifter part
+ *
+ * Verilog wrapper for sky130_hilas_StepUpDigitalPart1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigitalPart1 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigitalPart1 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_STEPUPDIGITALPART1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01E
+`define SKY130_HILAS_PFETDEVICE01E
+
+/**
+ * sky130_hilas_pFETdevice01e: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01e.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01e (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01e (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETDEVICE01E
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01AA
+`define SKY130_HILAS_PFETDEVICE01AA
+
+/**
+ * sky130_hilas_pFETdevice01aa: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01aa.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01aa (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01aa (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETDEVICE01AA
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPMODULE02
+`define SKY130_HILAS_CAPMODULE02
+
+/**
+ * sky130_hilas_CapModule02: None
+ *
+ * Verilog wrapper for sky130_hilas_CapModule02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule02 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule02 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_CAPMODULE02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGTRANS2X1CELL
+`define SKY130_HILAS_FGTRANS2X1CELL
+
+/**
+ * sky130_hilas_FGtrans2x1cell: None
+ *
+ * Verilog wrapper for sky130_hilas_FGtrans2x1cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGtrans2x1cell (
+ COLSEL1,
+ VINJ,
+ DRAIN1,
+ DRAIN2,
+ PROG,
+ RUN,
+ VIN2,
+ VIN1,
+ GATE1,
+ VTUN,
+ COL1,
+ ROW1,
+ ROW2,
+ VGND,
+ VNB,
+ VPB
+);
+ inout COLSEL1;
+ inout VINJ;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout PROG;
+ inout RUN;
+ inout VIN2;
+ inout VIN1;
+ inout GATE1;
+ inout VTUN;
+ inout COL1;
+ inout ROW1;
+ inout ROW2;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGtrans2x1cell (
+ COLSEL1,
+ VINJ,
+ DRAIN1,
+ DRAIN2,
+ PROG,
+ RUN,
+ VIN2,
+ VIN1,
+ GATE1,
+ VTUN,
+ COL1,
+ ROW1,
+ ROW2
+);
+ inout COLSEL1;
+ inout VINJ;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout PROG;
+ inout RUN;
+ inout VIN2;
+ inout VIN1;
+ inout GATE1;
+ inout VTUN;
+ inout COL1;
+ inout ROW1;
+ inout ROW2;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_FGTRANS2X1CELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPMODULE01A
+`define SKY130_HILAS_CAPMODULE01A
+
+/**
+ * sky130_hilas_CapModule01a: primitive cap, variant 01a
+ *
+ * Verilog wrapper for sky130_hilas_CapModule01a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule01a (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule01a (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_CAPMODULE01A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPACITORSIZE01
+`define SKY130_HILAS_CAPACITORSIZE01
+
+/**
+ * sky130_hilas_capacitorSize01: smallest cap
+ *
+ * Verilog wrapper for sky130_hilas_capacitorSize01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize01 (
+ CAPTERM02,
+ CAPTERM01,
+ VNB,
+ VPB
+);
+ inout CAPTERM02;
+ inout CAPTERM01;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize01 (
+ CAPTERM02,
+ CAPTERM01
+);
+ inout CAPTERM02;
+ inout CAPTERM01;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_CAPACITORSIZE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01
+`define SKY130_HILAS_PFETDEVICE01
+
+/**
+ * sky130_hilas_pFETdevice01: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETDEVICE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATE4DOUBLE01
+`define SKY130_HILAS_TGATE4DOUBLE01
+
+/**
+ * sky130_hilas_Tgate4Double01: 4 double-throw transmission gates
+ *
+ * Verilog wrapper for sky130_hilas_Tgate4Double01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Tgate4Double01 (
+ INPUT1_1,
+ SELECT1,
+ SELECT2,
+ INPUT2_2,
+ INPUT1_2,
+ SELECT3,
+ INPUT2_3,
+ SELECT4,
+ INPUT2_4,
+ INPUT1_4,
+ OUTPUT4,
+ OUTPUT3,
+ OUTPUT2,
+ OUTPUT1,
+ INPUT2_1,
+ INPUT1_3,
+ VGND,
+ VNB,
+ VPB
+);
+ inout INPUT1_1;
+ inout SELECT1;
+ inout SELECT2;
+ inout INPUT2_2;
+ inout INPUT1_2;
+ inout SELECT3;
+ inout INPUT2_3;
+ inout SELECT4;
+ inout INPUT2_4;
+ inout INPUT1_4;
+ inout OUTPUT4;
+ inout OUTPUT3;
+ inout OUTPUT2;
+ inout OUTPUT1;
+ inout INPUT2_1;
+ inout INPUT1_3;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Tgate4Double01 (
+ INPUT1_1,
+ SELECT1,
+ SELECT2,
+ INPUT2_2,
+ INPUT1_2,
+ SELECT3,
+ INPUT2_3,
+ SELECT4,
+ INPUT2_4,
+ INPUT1_4,
+ OUTPUT4,
+ OUTPUT3,
+ OUTPUT2,
+ OUTPUT1,
+ INPUT2_1,
+ INPUT1_3
+);
+ inout INPUT1_1;
+ inout SELECT1;
+ inout SELECT2;
+ inout INPUT2_2;
+ inout INPUT1_2;
+ inout SELECT3;
+ inout INPUT2_3;
+ inout SELECT4;
+ inout INPUT2_4;
+ inout INPUT1_4;
+ inout OUTPUT4;
+ inout OUTPUT3;
+ inout OUTPUT2;
+ inout OUTPUT1;
+ inout INPUT2_1;
+ inout INPUT1_3;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TGATE4DOUBLE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATEVINJ01
+`define SKY130_HILAS_TGATEVINJ01
+
+/**
+ * sky130_hilas_TgateVinj01: None
+ *
+ * Verilog wrapper for sky130_hilas_TgateVinj01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateVinj01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateVinj01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TGATEVINJ01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CELLATTEMPT01
+`define SKY130_HILAS_CELLATTEMPT01
+
+/**
+ * sky130_hilas_cellAttempt01: 4x1 array of FG switch cell, Varactor capacitor cell
+ *
+ * Verilog wrapper for sky130_hilas_cellAttempt01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_cellAttempt01 (
+ VTUN,
+ VINJ,
+ COLSEL1,
+ COL1,
+ GATE1,
+ DRAIN1,
+ ROW3,
+ DRAIN2,
+ ROW2,
+ DRAIN3,
+ ROW4,
+ DRAIN4,
+ ROW1,
+ VGND,
+ VNB,
+ VPB
+);
+ inout VTUN;
+ inout VINJ;
+ inout COLSEL1;
+ inout COL1;
+ inout GATE1;
+ inout DRAIN1;
+ inout ROW3;
+ inout DRAIN2;
+ inout ROW2;
+ inout DRAIN3;
+ inout ROW4;
+ inout DRAIN4;
+ inout ROW1;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_cellAttempt01 (
+ VTUN,
+ VINJ,
+ COLSEL1,
+ COL1,
+ GATE1,
+ DRAIN1,
+ ROW3,
+ DRAIN2,
+ ROW2,
+ DRAIN3,
+ ROW4,
+ DRAIN4,
+ ROW1
+);
+ inout VTUN;
+ inout VINJ;
+ inout COLSEL1;
+ inout COL1;
+ inout GATE1;
+ inout DRAIN1;
+ inout ROW3;
+ inout DRAIN2;
+ inout ROW2;
+ inout DRAIN3;
+ inout ROW4;
+ inout DRAIN4;
+ inout ROW1;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_CELLATTEMPT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_M22M4
+`define SKY130_HILAS_M22M4
+
+/**
+ * sky130_hilas_m22m4: m2 to m4 contact
+ *
+ * Verilog wrapper for sky130_hilas_m22m4.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_m22m4 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_m22m4 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_M22M4
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_POLY2M2
+`define SKY130_HILAS_POLY2M2
+
+/**
+ * sky130_hilas_poly2m2: polysilicon layer to m2 contact
+ *
+ * Verilog wrapper for sky130_hilas_poly2m2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2m2 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2m2 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_POLY2M2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TACOREBLOCK
+`define SKY130_HILAS_TACOREBLOCK
+
+/**
+ * sky130_hilas_TACoreBlock: None
+ *
+ * Verilog wrapper for sky130_hilas_TACoreBlock.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TACOREBLOCK
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01B
+`define SKY130_HILAS_PFETDEVICE01B
+
+/**
+ * sky130_hilas_pFETdevice01b: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01b.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01b (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01b (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETDEVICE01B
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_STEPUPDIGITAL
+`define SKY130_HILAS_STEPUPDIGITAL
+
+/**
+ * sky130_hilas_StepUpDigital: a single level shifter
+ *
+ * Verilog wrapper for sky130_hilas_StepUpDigital.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigital (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_StepUpDigital (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_STEPUPDIGITAL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_RESISTOR01
+`define SKY130_HILAS_RESISTOR01
+
+/**
+ * sky130_hilas_resistor01:
+ *
+ * Verilog wrapper for sky130_hilas_resistor01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_resistor01 (
+ TERM1,
+ TERM2,
+ VGND,
+ VNB,
+ VPB
+);
+ inout TERM1;
+ inout TERM2;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_resistor01 (
+ TERM1,
+ TERM2
+);
+ inout TERM1;
+ inout TERM2;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_RESISTOR01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NDIFFTHOXCONTACT
+`define SKY130_HILAS_NDIFFTHOXCONTACT
+
+/**
+ * sky130_hilas_nDiffThOxContact: None
+ *
+ * Verilog wrapper for sky130_hilas_nDiffThOxContact.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nDiffThOxContact (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nDiffThOxContact (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_NDIFFTHOXCONTACT
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_VINJNOR3
+`define SKY130_HILAS_VINJNOR3
+
+/**
+ * sky130_hilas_VinjNOR3: 3-input NOR gate capable of VING voltage
+ *
+ * Verilog wrapper for sky130_hilas_VinjNOR3.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjNOR3 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjNOR3 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_VINJNOR3
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETMIRRORPAIRS2
+`define SKY130_HILAS_NFETMIRRORPAIRS2
+
+/**
+ * sky130_hilas_nFETmirrorPairs2: None
+ *
+ * Verilog wrapper for sky130_hilas_nFETmirrorPairs2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs2 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs2 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_NFETMIRRORPAIRS2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETMIRRORPAIRS
+`define SKY130_HILAS_NFETMIRRORPAIRS
+
+/**
+ * sky130_hilas_nFETmirrorPairs: pairs of nFET current mirrors
+ *
+ * Verilog wrapper for sky130_hilas_nFETmirrorPairs.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmirrorPairs (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_NFETMIRRORPAIRS
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_VINJDIODEPROTECT01
+`define SKY130_HILAS_VINJDIODEPROTECT01
+
+/**
+ * sky130_hilas_VinjDiodeProtect01: protective ESD diode for VINJ line
+ *
+ * Verilog wrapper for sky130_hilas_VinjDiodeProtect01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjDiodeProtect01 (
+ VINJ,
+ INPUT,
+ VGND,
+ VNB,
+ VPB
+);
+ inout VINJ;
+ inout INPUT;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjDiodeProtect01 (
+ VINJ,
+ INPUT
+);
+ inout VINJ;
+ inout INPUT;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_VINJDIODEPROTECT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_LEVELSHIFT4INPUTUP
+`define SKY130_HILAS_LEVELSHIFT4INPUTUP
+
+/**
+ * sky130_hilas_LevelShift4InputUp: 4-channel level shifter
+ *
+ * Verilog wrapper for sky130_hilas_LevelShift4InputUp.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LevelShift4InputUp (
+ INPUT1,
+ INPUT2,
+ INPUT3,
+ INPUT4,
+ VINJ,
+ OUTPUT1,
+ OUTPUT2,
+ OUTPUT3,
+ OUTPUT4,
+ VPWR,
+ VGND,
+ VNB,
+ VPB
+);
+ inout INPUT1;
+ inout INPUT2;
+ inout INPUT3;
+ inout INPUT4;
+ inout VINJ;
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout OUTPUT3;
+ inout OUTPUT4;
+ inout VPWR;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LevelShift4InputUp (
+ INPUT1,
+ INPUT2,
+ INPUT3,
+ INPUT4,
+ VINJ,
+ OUTPUT1,
+ OUTPUT2,
+ OUTPUT3,
+ OUTPUT4
+);
+ inout INPUT1;
+ inout INPUT2;
+ inout INPUT3;
+ inout INPUT4;
+ inout VINJ;
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout OUTPUT3;
+ inout OUTPUT4;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_LEVELSHIFT4INPUTUP
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_WTA4STAGE01
+`define SKY130_HILAS_WTA4STAGE01
+
+/**
+ * sky130_hilas_WTA4Stage01: 4-input winner-take-all circuit. Connects directly to array of swc4x2cell. Can array vertically. Needs one nFET transistor current source.
+ *
+ * Verilog wrapper for sky130_hilas_WTA4Stage01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTA4Stage01 (
+ OUTPUT1,
+ OUTPUT2,
+ OUTPUT3,
+ OUTPUT4,
+ INPUT1,
+ INPUT2,
+ INPUT3,
+ INPUT4,
+ DRAIN1,
+ DRAIN2,
+ DRAIN3,
+ DRAIN4,
+ GATE1,
+ VTUN,
+ WTAMIDDLENODE,
+ COLSEL1,
+ VINJ,
+ VGND,
+ VPWR,
+ VNB,
+ VPB
+);
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout OUTPUT3;
+ inout OUTPUT4;
+ inout INPUT1;
+ inout INPUT2;
+ inout INPUT3;
+ inout INPUT4;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout DRAIN3;
+ inout DRAIN4;
+ inout GATE1;
+ inout VTUN;
+ inout WTAMIDDLENODE;
+ inout COLSEL1;
+ inout VINJ;
+ inout VGND;
+ inout VPWR;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTA4Stage01 (
+ OUTPUT1,
+ OUTPUT2,
+ OUTPUT3,
+ OUTPUT4,
+ INPUT1,
+ INPUT2,
+ INPUT3,
+ INPUT4,
+ DRAIN1,
+ DRAIN2,
+ DRAIN3,
+ DRAIN4,
+ GATE1,
+ VTUN,
+ WTAMIDDLENODE,
+ COLSEL1,
+ VINJ
+);
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout OUTPUT3;
+ inout OUTPUT4;
+ inout INPUT1;
+ inout INPUT2;
+ inout INPUT3;
+ inout INPUT4;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout DRAIN3;
+ inout DRAIN4;
+ inout GATE1;
+ inout VTUN;
+ inout WTAMIDDLENODE;
+ inout COLSEL1;
+ inout VINJ;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_WTA4STAGE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01B
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01B
+
+/**
+ * sky130_hilas_DAC6TransistorStack01b: None
+ *
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01b.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01b (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01b (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DAC6TRANSISTORSTACK01B
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TRANS4SMALL
+`define SKY130_HILAS_TRANS4SMALL
+
+/**
+ * sky130_hilas_Trans4small: 3 small nFETs + 3 small pFETs
+ *
+ * Verilog wrapper for sky130_hilas_Trans4small.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Trans4small (
+ NFET_SOURCE1,
+ NFET_GATE1,
+ NFET_SOURCE2,
+ NFET_GATE2,
+ NFET_SOURCE3,
+ NFET_GATE3,
+ PFET_SOURCE1,
+ PFET_GATE1,
+ PFET_SOURCE2,
+ PFET_GATE2,
+ PFET_SOURCE3,
+ PFET_GATE3,
+ WELL,
+ PFET_DRAIN3,
+ PFET_DRAIN2,
+ PFET_DRAIN1,
+ NFET_DRAIN3,
+ NFET_DRAIN2,
+ NFET_DRAIN1,
+ VGND,
+ VNB,
+ VPB
+);
+ inout NFET_SOURCE1;
+ inout NFET_GATE1;
+ inout NFET_SOURCE2;
+ inout NFET_GATE2;
+ inout NFET_SOURCE3;
+ inout NFET_GATE3;
+ inout PFET_SOURCE1;
+ inout PFET_GATE1;
+ inout PFET_SOURCE2;
+ inout PFET_GATE2;
+ inout PFET_SOURCE3;
+ inout PFET_GATE3;
+ inout WELL;
+ inout PFET_DRAIN3;
+ inout PFET_DRAIN2;
+ inout PFET_DRAIN1;
+ inout NFET_DRAIN3;
+ inout NFET_DRAIN2;
+ inout NFET_DRAIN1;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Trans4small (
+ NFET_SOURCE1,
+ NFET_GATE1,
+ NFET_SOURCE2,
+ NFET_GATE2,
+ NFET_SOURCE3,
+ NFET_GATE3,
+ PFET_SOURCE1,
+ PFET_GATE1,
+ PFET_SOURCE2,
+ PFET_GATE2,
+ PFET_SOURCE3,
+ PFET_GATE3,
+ WELL,
+ PFET_DRAIN3,
+ PFET_DRAIN2,
+ PFET_DRAIN1,
+ NFET_DRAIN3,
+ NFET_DRAIN2,
+ NFET_DRAIN1
+);
+ inout NFET_SOURCE1;
+ inout NFET_GATE1;
+ inout NFET_SOURCE2;
+ inout NFET_GATE2;
+ inout NFET_SOURCE3;
+ inout NFET_GATE3;
+ inout PFET_SOURCE1;
+ inout PFET_GATE1;
+ inout PFET_SOURCE2;
+ inout PFET_GATE2;
+ inout PFET_SOURCE3;
+ inout PFET_GATE3;
+ inout WELL;
+ inout PFET_DRAIN3;
+ inout PFET_DRAIN2;
+ inout PFET_DRAIN1;
+ inout NFET_DRAIN3;
+ inout NFET_DRAIN2;
+ inout NFET_DRAIN1;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TRANS4SMALL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_LEFTPROTECTION
+`define SKY130_HILAS_LEFTPROTECTION
+
+/**
+ * sky130_hilas_LeftProtection:
+ *
+ * Verilog wrapper for sky130_hilas_LeftProtection.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LeftProtection (
+ IO25,
+ IO26,
+ IO27,
+ IO28,
+ IO29,
+ IO30,
+ IO31,
+ IO32,
+ IO33,
+ IO34,
+ IO35,
+ IO36,
+ IO37,
+ PIN1,
+ PIN2,
+ PIN4,
+ PIN5,
+ PIN6,
+ PIN7,
+ PIN8,
+ PIN9,
+ PIN10,
+ PIN11,
+ PIN12,
+ PIN13,
+ VNB,
+ VPB
+);
+ inout IO25;
+ inout IO26;
+ inout IO27;
+ inout IO28;
+ inout IO29;
+ inout IO30;
+ inout IO31;
+ inout IO32;
+ inout IO33;
+ inout IO34;
+ inout IO35;
+ inout IO36;
+ inout IO37;
+ inout PIN1;
+ inout PIN2;
+ inout PIN4;
+ inout PIN5;
+ inout PIN6;
+ inout PIN7;
+ inout PIN8;
+ inout PIN9;
+ inout PIN10;
+ inout PIN11;
+ inout PIN12;
+ inout PIN13;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_LeftProtection (
+ IO25,
+ IO26,
+ IO27,
+ IO28,
+ IO29,
+ IO30,
+ IO31,
+ IO32,
+ IO33,
+ IO34,
+ IO35,
+ IO36,
+ IO37,
+ PIN1,
+ PIN2,
+ PIN4,
+ PIN5,
+ PIN6,
+ PIN7,
+ PIN8,
+ PIN9,
+ PIN10,
+ PIN11,
+ PIN12,
+ PIN13
+);
+ inout IO25;
+ inout IO26;
+ inout IO27;
+ inout IO28;
+ inout IO29;
+ inout IO30;
+ inout IO31;
+ inout IO32;
+ inout IO33;
+ inout IO34;
+ inout IO35;
+ inout IO36;
+ inout IO37;
+ inout PIN1;
+ inout PIN2;
+ inout PIN4;
+ inout PIN5;
+ inout PIN6;
+ inout PIN7;
+ inout PIN8;
+ inout PIN9;
+ inout PIN10;
+ inout PIN11;
+ inout PIN12;
+ inout PIN13;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_LEFTPROTECTION
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGBIASWEAKGATE2X1CELL
+`define SKY130_HILAS_FGBIASWEAKGATE2X1CELL
+
+/**
+ * sky130_hilas_FGBiasWeakGate2x1cell: 2x1 array of FG switch cells configured as pFET current sources with weak capacitive gate inputs
+ *
+ * Verilog wrapper for sky130_hilas_FGBiasWeakGate2x1cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGBiasWeakGate2x1cell (
+ DRAIN1,
+ VIN11,
+ ROW1,
+ ROW2,
+ VINJ,
+ COLSEL1,
+ GATE1,
+ VTUN,
+ DRAIN2,
+ VIN12,
+ COMMONSOURCE,
+ VGND,
+ VNB,
+ VPB
+);
+ inout DRAIN1;
+ inout VIN11;
+ inout ROW1;
+ inout ROW2;
+ inout VINJ;
+ inout COLSEL1;
+ inout GATE1;
+ inout VTUN;
+ inout DRAIN2;
+ inout VIN12;
+ inout COMMONSOURCE;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGBiasWeakGate2x1cell (
+ DRAIN1,
+ VIN11,
+ ROW1,
+ ROW2,
+ VINJ,
+ COLSEL1,
+ GATE1,
+ VTUN,
+ DRAIN2,
+ VIN12,
+ COMMONSOURCE
+);
+ inout DRAIN1;
+ inout VIN11;
+ inout ROW1;
+ inout ROW2;
+ inout VINJ;
+ inout COLSEL1;
+ inout GATE1;
+ inout VTUN;
+ inout DRAIN2;
+ inout VIN12;
+ inout COMMONSOURCE;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_FGBIASWEAKGATE2X1CELL
+
+
+//--------EOF---------
+
+`ifndef USER_ANALOG_PROJECT_WRAPPER
+`define USER_ANALOG_PROJECT_WRAPPER
+
+/**
+ * user_analog_project_wrapper:
+ *
+ * Verilog wrapper for user_analog_project_wrapper.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module user_analog_project_wrapper (
+ gpio_analog[0],
+ gpio_analog[10],
+ gpio_analog[11],
+ gpio_analog[12],
+ gpio_analog[13],
+ gpio_analog[14],
+ gpio_analog[15],
+ gpio_analog[16],
+ gpio_analog[17],
+ gpio_analog[1],
+ gpio_analog[2],
+ gpio_analog[3],
+ gpio_analog[4],
+ gpio_analog[5],
+ gpio_analog[6],
+ gpio_analog[7],
+ gpio_analog[8],
+ gpio_analog[9],
+ gpio_noesd[0],
+ gpio_noesd[10],
+ gpio_noesd[11],
+ gpio_noesd[12],
+ gpio_noesd[13],
+ gpio_noesd[14],
+ gpio_noesd[15],
+ gpio_noesd[16],
+ gpio_noesd[17],
+ gpio_noesd[1],
+ gpio_noesd[2],
+ gpio_noesd[3],
+ gpio_noesd[4],
+ gpio_noesd[5],
+ gpio_noesd[6],
+ gpio_noesd[7],
+ gpio_noesd[8],
+ gpio_noesd[9],
+ io_analog[0],
+ io_analog[10],
+ io_analog[1],
+ io_analog[2],
+ io_analog[3],
+ io_analog[4],
+ io_analog[5],
+ io_analog[6],
+ io_analog[7],
+ io_analog[8],
+ io_analog[9],
+ io_clamp_high[0],
+ io_clamp_high[1],
+ io_clamp_high[2],
+ io_clamp_low[0],
+ io_clamp_low[1],
+ io_clamp_low[2],
+ io_in[0],
+ io_in[10],
+ io_in[11],
+ io_in[12],
+ io_in[13],
+ io_in[14],
+ io_in[15],
+ io_in[16],
+ io_in[17],
+ io_in[18],
+ io_in[19],
+ io_in[1],
+ io_in[20],
+ io_in[21],
+ io_in[22],
+ io_in[23],
+ io_in[24],
+ io_in[25],
+ io_in[26],
+ io_in[2],
+ io_in[3],
+ io_in[4],
+ io_in[5],
+ io_in[6],
+ io_in[7],
+ io_in[8],
+ io_in[9],
+ io_in_3v3[0],
+ io_in_3v3[10],
+ io_in_3v3[11],
+ io_in_3v3[12],
+ io_in_3v3[13],
+ io_in_3v3[14],
+ io_in_3v3[15],
+ io_in_3v3[16],
+ io_in_3v3[17],
+ io_in_3v3[18],
+ io_in_3v3[19],
+ io_in_3v3[1],
+ io_in_3v3[20],
+ io_in_3v3[21],
+ io_in_3v3[22],
+ io_in_3v3[23],
+ io_in_3v3[24],
+ io_in_3v3[25],
+ io_in_3v3[26],
+ io_in_3v3[2],
+ io_in_3v3[3],
+ io_in_3v3[4],
+ io_in_3v3[5],
+ io_in_3v3[6],
+ io_in_3v3[7],
+ io_in_3v3[8],
+ io_in_3v3[9],
+ io_oeb[0],
+ io_oeb[10],
+ io_oeb[11],
+ io_oeb[12],
+ io_oeb[13],
+ io_oeb[14],
+ io_oeb[15],
+ io_oeb[16],
+ io_oeb[17],
+ io_oeb[18],
+ io_oeb[19],
+ io_oeb[1],
+ io_oeb[20],
+ io_oeb[21],
+ io_oeb[22],
+ io_oeb[23],
+ io_oeb[24],
+ io_oeb[25],
+ io_oeb[26],
+ io_oeb[2],
+ io_oeb[3],
+ io_oeb[4],
+ io_oeb[5],
+ io_oeb[6],
+ io_oeb[7],
+ io_oeb[8],
+ io_oeb[9],
+ io_out[0],
+ io_out[10],
+ io_out[11],
+ io_out[12],
+ io_out[13],
+ io_out[14],
+ io_out[15],
+ io_out[16],
+ io_out[17],
+ io_out[18],
+ io_out[19],
+ io_out[1],
+ io_out[20],
+ io_out[21],
+ io_out[22],
+ io_out[23],
+ io_out[24],
+ io_out[25],
+ io_out[26],
+ io_out[2],
+ io_out[3],
+ io_out[4],
+ io_out[5],
+ io_out[6],
+ io_out[7],
+ io_out[8],
+ io_out[9],
+ la_data_in[0],
+ la_data_in[100],
+ la_data_in[101],
+ la_data_in[102],
+ la_data_in[103],
+ la_data_in[104],
+ la_data_in[105],
+ la_data_in[106],
+ la_data_in[107],
+ la_data_in[108],
+ la_data_in[109],
+ la_data_in[10],
+ la_data_in[110],
+ la_data_in[111],
+ la_data_in[112],
+ la_data_in[113],
+ la_data_in[114],
+ la_data_in[115],
+ la_data_in[116],
+ la_data_in[117],
+ la_data_in[118],
+ la_data_in[119],
+ la_data_in[11],
+ la_data_in[120],
+ la_data_in[121],
+ la_data_in[122],
+ la_data_in[123],
+ la_data_in[124],
+ la_data_in[125],
+ la_data_in[126],
+ la_data_in[127],
+ la_data_in[12],
+ la_data_in[13],
+ la_data_in[14],
+ la_data_in[15],
+ la_data_in[16],
+ la_data_in[17],
+ la_data_in[18],
+ la_data_in[19],
+ la_data_in[1],
+ la_data_in[20],
+ la_data_in[21],
+ la_data_in[22],
+ la_data_in[23],
+ la_data_in[24],
+ la_data_in[25],
+ la_data_in[26],
+ la_data_in[27],
+ la_data_in[28],
+ la_data_in[29],
+ la_data_in[2],
+ la_data_in[30],
+ la_data_in[31],
+ la_data_in[32],
+ la_data_in[33],
+ la_data_in[34],
+ la_data_in[35],
+ la_data_in[36],
+ la_data_in[37],
+ la_data_in[38],
+ la_data_in[39],
+ la_data_in[3],
+ la_data_in[40],
+ la_data_in[41],
+ la_data_in[42],
+ la_data_in[43],
+ la_data_in[44],
+ la_data_in[45],
+ la_data_in[46],
+ la_data_in[47],
+ la_data_in[48],
+ la_data_in[49],
+ la_data_in[4],
+ la_data_in[50],
+ la_data_in[51],
+ la_data_in[52],
+ la_data_in[53],
+ la_data_in[54],
+ la_data_in[55],
+ la_data_in[56],
+ la_data_in[57],
+ la_data_in[58],
+ la_data_in[59],
+ la_data_in[5],
+ la_data_in[60],
+ la_data_in[61],
+ la_data_in[62],
+ la_data_in[63],
+ la_data_in[64],
+ la_data_in[65],
+ la_data_in[66],
+ la_data_in[67],
+ la_data_in[68],
+ la_data_in[69],
+ la_data_in[6],
+ la_data_in[70],
+ la_data_in[71],
+ la_data_in[72],
+ la_data_in[73],
+ la_data_in[74],
+ la_data_in[75],
+ la_data_in[76],
+ la_data_in[77],
+ la_data_in[78],
+ la_data_in[79],
+ la_data_in[7],
+ la_data_in[80],
+ la_data_in[81],
+ la_data_in[82],
+ la_data_in[83],
+ la_data_in[84],
+ la_data_in[85],
+ la_data_in[86],
+ la_data_in[87],
+ la_data_in[88],
+ la_data_in[89],
+ la_data_in[8],
+ la_data_in[90],
+ la_data_in[91],
+ la_data_in[92],
+ la_data_in[93],
+ la_data_in[94],
+ la_data_in[95],
+ la_data_in[96],
+ la_data_in[97],
+ la_data_in[98],
+ la_data_in[99],
+ la_data_in[9],
+ la_data_out[0],
+ la_data_out[100],
+ la_data_out[101],
+ la_data_out[102],
+ la_data_out[103],
+ la_data_out[104],
+ la_data_out[105],
+ la_data_out[106],
+ la_data_out[107],
+ la_data_out[108],
+ la_data_out[109],
+ la_data_out[10],
+ la_data_out[110],
+ la_data_out[111],
+ la_data_out[112],
+ la_data_out[113],
+ la_data_out[114],
+ la_data_out[115],
+ la_data_out[116],
+ la_data_out[117],
+ la_data_out[118],
+ la_data_out[119],
+ la_data_out[11],
+ la_data_out[120],
+ la_data_out[121],
+ la_data_out[122],
+ la_data_out[123],
+ la_data_out[124],
+ la_data_out[125],
+ la_data_out[126],
+ la_data_out[127],
+ la_data_out[12],
+ la_data_out[13],
+ la_data_out[14],
+ la_data_out[15],
+ la_data_out[16],
+ la_data_out[17],
+ la_data_out[18],
+ la_data_out[19],
+ la_data_out[1],
+ la_data_out[20],
+ la_data_out[21],
+ la_data_out[22],
+ la_data_out[23],
+ la_data_out[24],
+ la_data_out[25],
+ la_data_out[26],
+ la_data_out[27],
+ la_data_out[28],
+ la_data_out[29],
+ la_data_out[2],
+ la_data_out[30],
+ la_data_out[31],
+ la_data_out[32],
+ la_data_out[33],
+ la_data_out[34],
+ la_data_out[35],
+ la_data_out[36],
+ la_data_out[37],
+ la_data_out[38],
+ la_data_out[39],
+ la_data_out[3],
+ la_data_out[40],
+ la_data_out[41],
+ la_data_out[42],
+ la_data_out[43],
+ la_data_out[44],
+ la_data_out[45],
+ la_data_out[46],
+ la_data_out[47],
+ la_data_out[48],
+ la_data_out[49],
+ la_data_out[4],
+ la_data_out[50],
+ la_data_out[51],
+ la_data_out[52],
+ la_data_out[53],
+ la_data_out[54],
+ la_data_out[55],
+ la_data_out[56],
+ la_data_out[57],
+ la_data_out[58],
+ la_data_out[59],
+ la_data_out[5],
+ la_data_out[60],
+ la_data_out[61],
+ la_data_out[62],
+ la_data_out[63],
+ la_data_out[64],
+ la_data_out[65],
+ la_data_out[66],
+ la_data_out[67],
+ la_data_out[68],
+ la_data_out[69],
+ la_data_out[6],
+ la_data_out[70],
+ la_data_out[71],
+ la_data_out[72],
+ la_data_out[73],
+ la_data_out[74],
+ la_data_out[75],
+ la_data_out[76],
+ la_data_out[77],
+ la_data_out[78],
+ la_data_out[79],
+ la_data_out[7],
+ la_data_out[80],
+ la_data_out[81],
+ la_data_out[82],
+ la_data_out[83],
+ la_data_out[84],
+ la_data_out[85],
+ la_data_out[86],
+ la_data_out[87],
+ la_data_out[88],
+ la_data_out[89],
+ la_data_out[8],
+ la_data_out[90],
+ la_data_out[91],
+ la_data_out[92],
+ la_data_out[93],
+ la_data_out[94],
+ la_data_out[95],
+ la_data_out[96],
+ la_data_out[97],
+ la_data_out[98],
+ la_data_out[99],
+ la_data_out[9],
+ la_oenb[0],
+ la_oenb[100],
+ la_oenb[101],
+ la_oenb[102],
+ la_oenb[103],
+ la_oenb[104],
+ la_oenb[105],
+ la_oenb[106],
+ la_oenb[107],
+ la_oenb[108],
+ la_oenb[109],
+ la_oenb[10],
+ la_oenb[110],
+ la_oenb[111],
+ la_oenb[112],
+ la_oenb[113],
+ la_oenb[114],
+ la_oenb[115],
+ la_oenb[116],
+ la_oenb[117],
+ la_oenb[118],
+ la_oenb[119],
+ la_oenb[11],
+ la_oenb[120],
+ la_oenb[121],
+ la_oenb[122],
+ la_oenb[123],
+ la_oenb[124],
+ la_oenb[125],
+ la_oenb[126],
+ la_oenb[127],
+ la_oenb[12],
+ la_oenb[13],
+ la_oenb[14],
+ la_oenb[15],
+ la_oenb[16],
+ la_oenb[17],
+ la_oenb[18],
+ la_oenb[19],
+ la_oenb[1],
+ la_oenb[20],
+ la_oenb[21],
+ la_oenb[22],
+ la_oenb[23],
+ la_oenb[24],
+ la_oenb[25],
+ la_oenb[26],
+ la_oenb[27],
+ la_oenb[28],
+ la_oenb[29],
+ la_oenb[2],
+ la_oenb[30],
+ la_oenb[31],
+ la_oenb[32],
+ la_oenb[33],
+ la_oenb[34],
+ la_oenb[35],
+ la_oenb[36],
+ la_oenb[37],
+ la_oenb[38],
+ la_oenb[39],
+ la_oenb[3],
+ la_oenb[40],
+ la_oenb[41],
+ la_oenb[42],
+ la_oenb[43],
+ la_oenb[44],
+ la_oenb[45],
+ la_oenb[46],
+ la_oenb[47],
+ la_oenb[48],
+ la_oenb[49],
+ la_oenb[4],
+ la_oenb[50],
+ la_oenb[51],
+ la_oenb[52],
+ la_oenb[53],
+ la_oenb[54],
+ la_oenb[55],
+ la_oenb[56],
+ la_oenb[57],
+ la_oenb[58],
+ la_oenb[59],
+ la_oenb[5],
+ la_oenb[60],
+ la_oenb[61],
+ la_oenb[62],
+ la_oenb[63],
+ la_oenb[64],
+ la_oenb[65],
+ la_oenb[66],
+ la_oenb[67],
+ la_oenb[68],
+ la_oenb[69],
+ la_oenb[6],
+ la_oenb[70],
+ la_oenb[71],
+ la_oenb[72],
+ la_oenb[73],
+ la_oenb[74],
+ la_oenb[75],
+ la_oenb[76],
+ la_oenb[77],
+ la_oenb[78],
+ la_oenb[79],
+ la_oenb[7],
+ la_oenb[80],
+ la_oenb[81],
+ la_oenb[82],
+ la_oenb[83],
+ la_oenb[84],
+ la_oenb[85],
+ la_oenb[86],
+ la_oenb[87],
+ la_oenb[88],
+ la_oenb[89],
+ la_oenb[8],
+ la_oenb[90],
+ la_oenb[91],
+ la_oenb[92],
+ la_oenb[93],
+ la_oenb[94],
+ la_oenb[95],
+ la_oenb[96],
+ la_oenb[97],
+ la_oenb[98],
+ la_oenb[99],
+ la_oenb[9],
+ user_clock2,
+ user_irq[0],
+ user_irq[1],
+ user_irq[2],
+ vccd1,
+ vccd2,
+ vdda1,
+ vdda2,
+ vssa1,
+ vssa2,
+ vssd1,
+ vssd2,
+ wb_clk_i,
+ wb_rst_i,
+ wbs_ack_o,
+ wbs_adr_i[0],
+ wbs_adr_i[10],
+ wbs_adr_i[11],
+ wbs_adr_i[12],
+ wbs_adr_i[13],
+ wbs_adr_i[14],
+ wbs_adr_i[15],
+ wbs_adr_i[16],
+ wbs_adr_i[17],
+ wbs_adr_i[18],
+ wbs_adr_i[19],
+ wbs_adr_i[1],
+ wbs_adr_i[20],
+ wbs_adr_i[21],
+ wbs_adr_i[22],
+ wbs_adr_i[23],
+ wbs_adr_i[24],
+ wbs_adr_i[25],
+ wbs_adr_i[26],
+ wbs_adr_i[27],
+ wbs_adr_i[28],
+ wbs_adr_i[29],
+ wbs_adr_i[2],
+ wbs_adr_i[30],
+ wbs_adr_i[31],
+ wbs_adr_i[3],
+ wbs_adr_i[4],
+ wbs_adr_i[5],
+ wbs_adr_i[6],
+ wbs_adr_i[7],
+ wbs_adr_i[8],
+ wbs_adr_i[9],
+ wbs_cyc_i,
+ wbs_dat_i[0],
+ wbs_dat_i[10],
+ wbs_dat_i[11],
+ wbs_dat_i[12],
+ wbs_dat_i[13],
+ wbs_dat_i[14],
+ wbs_dat_i[15],
+ wbs_dat_i[16],
+ wbs_dat_i[17],
+ wbs_dat_i[18],
+ wbs_dat_i[19],
+ wbs_dat_i[1],
+ wbs_dat_i[20],
+ wbs_dat_i[21],
+ wbs_dat_i[22],
+ wbs_dat_i[23],
+ wbs_dat_i[24],
+ wbs_dat_i[25],
+ wbs_dat_i[26],
+ wbs_dat_i[27],
+ wbs_dat_i[28],
+ wbs_dat_i[29],
+ wbs_dat_i[2],
+ wbs_dat_i[30],
+ wbs_dat_i[31],
+ wbs_dat_i[3],
+ wbs_dat_i[4],
+ wbs_dat_i[5],
+ wbs_dat_i[6],
+ wbs_dat_i[7],
+ wbs_dat_i[8],
+ wbs_dat_i[9],
+ wbs_dat_o[0],
+ wbs_dat_o[10],
+ wbs_dat_o[11],
+ wbs_dat_o[12],
+ wbs_dat_o[13],
+ wbs_dat_o[14],
+ wbs_dat_o[15],
+ wbs_dat_o[16],
+ wbs_dat_o[17],
+ wbs_dat_o[18],
+ wbs_dat_o[19],
+ wbs_dat_o[1],
+ wbs_dat_o[20],
+ wbs_dat_o[21],
+ wbs_dat_o[22],
+ wbs_dat_o[23],
+ wbs_dat_o[24],
+ wbs_dat_o[25],
+ wbs_dat_o[26],
+ wbs_dat_o[27],
+ wbs_dat_o[28],
+ wbs_dat_o[29],
+ wbs_dat_o[2],
+ wbs_dat_o[30],
+ wbs_dat_o[31],
+ wbs_dat_o[3],
+ wbs_dat_o[4],
+ wbs_dat_o[5],
+ wbs_dat_o[6],
+ wbs_dat_o[7],
+ wbs_dat_o[8],
+ wbs_dat_o[9],
+ wbs_sel_i[0],
+ wbs_sel_i[1],
+ wbs_sel_i[2],
+ wbs_sel_i[3],
+ wbs_stb_i,
+ wbs_we_i,
+ VNB,
+ VPB
+);
+ inout gpio_analog[0];
+ inout gpio_analog[10];
+ inout gpio_analog[11];
+ inout gpio_analog[12];
+ inout gpio_analog[13];
+ inout gpio_analog[14];
+ inout gpio_analog[15];
+ inout gpio_analog[16];
+ inout gpio_analog[17];
+ inout gpio_analog[1];
+ inout gpio_analog[2];
+ inout gpio_analog[3];
+ inout gpio_analog[4];
+ inout gpio_analog[5];
+ inout gpio_analog[6];
+ inout gpio_analog[7];
+ inout gpio_analog[8];
+ inout gpio_analog[9];
+ inout gpio_noesd[0];
+ inout gpio_noesd[10];
+ inout gpio_noesd[11];
+ inout gpio_noesd[12];
+ inout gpio_noesd[13];
+ inout gpio_noesd[14];
+ inout gpio_noesd[15];
+ inout gpio_noesd[16];
+ inout gpio_noesd[17];
+ inout gpio_noesd[1];
+ inout gpio_noesd[2];
+ inout gpio_noesd[3];
+ inout gpio_noesd[4];
+ inout gpio_noesd[5];
+ inout gpio_noesd[6];
+ inout gpio_noesd[7];
+ inout gpio_noesd[8];
+ inout gpio_noesd[9];
+ inout io_analog[0];
+ inout io_analog[10];
+ inout io_analog[1];
+ inout io_analog[2];
+ inout io_analog[3];
+ inout io_analog[4];
+ inout io_analog[5];
+ inout io_analog[6];
+ inout io_analog[7];
+ inout io_analog[8];
+ inout io_analog[9];
+ inout io_clamp_high[0];
+ inout io_clamp_high[1];
+ inout io_clamp_high[2];
+ inout io_clamp_low[0];
+ inout io_clamp_low[1];
+ inout io_clamp_low[2];
+ inout io_in[0];
+ inout io_in[10];
+ inout io_in[11];
+ inout io_in[12];
+ inout io_in[13];
+ inout io_in[14];
+ inout io_in[15];
+ inout io_in[16];
+ inout io_in[17];
+ inout io_in[18];
+ inout io_in[19];
+ inout io_in[1];
+ inout io_in[20];
+ inout io_in[21];
+ inout io_in[22];
+ inout io_in[23];
+ inout io_in[24];
+ inout io_in[25];
+ inout io_in[26];
+ inout io_in[2];
+ inout io_in[3];
+ inout io_in[4];
+ inout io_in[5];
+ inout io_in[6];
+ inout io_in[7];
+ inout io_in[8];
+ inout io_in[9];
+ inout io_in_3v3[0];
+ inout io_in_3v3[10];
+ inout io_in_3v3[11];
+ inout io_in_3v3[12];
+ inout io_in_3v3[13];
+ inout io_in_3v3[14];
+ inout io_in_3v3[15];
+ inout io_in_3v3[16];
+ inout io_in_3v3[17];
+ inout io_in_3v3[18];
+ inout io_in_3v3[19];
+ inout io_in_3v3[1];
+ inout io_in_3v3[20];
+ inout io_in_3v3[21];
+ inout io_in_3v3[22];
+ inout io_in_3v3[23];
+ inout io_in_3v3[24];
+ inout io_in_3v3[25];
+ inout io_in_3v3[26];
+ inout io_in_3v3[2];
+ inout io_in_3v3[3];
+ inout io_in_3v3[4];
+ inout io_in_3v3[5];
+ inout io_in_3v3[6];
+ inout io_in_3v3[7];
+ inout io_in_3v3[8];
+ inout io_in_3v3[9];
+ inout io_oeb[0];
+ inout io_oeb[10];
+ inout io_oeb[11];
+ inout io_oeb[12];
+ inout io_oeb[13];
+ inout io_oeb[14];
+ inout io_oeb[15];
+ inout io_oeb[16];
+ inout io_oeb[17];
+ inout io_oeb[18];
+ inout io_oeb[19];
+ inout io_oeb[1];
+ inout io_oeb[20];
+ inout io_oeb[21];
+ inout io_oeb[22];
+ inout io_oeb[23];
+ inout io_oeb[24];
+ inout io_oeb[25];
+ inout io_oeb[26];
+ inout io_oeb[2];
+ inout io_oeb[3];
+ inout io_oeb[4];
+ inout io_oeb[5];
+ inout io_oeb[6];
+ inout io_oeb[7];
+ inout io_oeb[8];
+ inout io_oeb[9];
+ inout io_out[0];
+ inout io_out[10];
+ inout io_out[11];
+ inout io_out[12];
+ inout io_out[13];
+ inout io_out[14];
+ inout io_out[15];
+ inout io_out[16];
+ inout io_out[17];
+ inout io_out[18];
+ inout io_out[19];
+ inout io_out[1];
+ inout io_out[20];
+ inout io_out[21];
+ inout io_out[22];
+ inout io_out[23];
+ inout io_out[24];
+ inout io_out[25];
+ inout io_out[26];
+ inout io_out[2];
+ inout io_out[3];
+ inout io_out[4];
+ inout io_out[5];
+ inout io_out[6];
+ inout io_out[7];
+ inout io_out[8];
+ inout io_out[9];
+ inout la_data_in[0];
+ inout la_data_in[100];
+ inout la_data_in[101];
+ inout la_data_in[102];
+ inout la_data_in[103];
+ inout la_data_in[104];
+ inout la_data_in[105];
+ inout la_data_in[106];
+ inout la_data_in[107];
+ inout la_data_in[108];
+ inout la_data_in[109];
+ inout la_data_in[10];
+ inout la_data_in[110];
+ inout la_data_in[111];
+ inout la_data_in[112];
+ inout la_data_in[113];
+ inout la_data_in[114];
+ inout la_data_in[115];
+ inout la_data_in[116];
+ inout la_data_in[117];
+ inout la_data_in[118];
+ inout la_data_in[119];
+ inout la_data_in[11];
+ inout la_data_in[120];
+ inout la_data_in[121];
+ inout la_data_in[122];
+ inout la_data_in[123];
+ inout la_data_in[124];
+ inout la_data_in[125];
+ inout la_data_in[126];
+ inout la_data_in[127];
+ inout la_data_in[12];
+ inout la_data_in[13];
+ inout la_data_in[14];
+ inout la_data_in[15];
+ inout la_data_in[16];
+ inout la_data_in[17];
+ inout la_data_in[18];
+ inout la_data_in[19];
+ inout la_data_in[1];
+ inout la_data_in[20];
+ inout la_data_in[21];
+ inout la_data_in[22];
+ inout la_data_in[23];
+ inout la_data_in[24];
+ inout la_data_in[25];
+ inout la_data_in[26];
+ inout la_data_in[27];
+ inout la_data_in[28];
+ inout la_data_in[29];
+ inout la_data_in[2];
+ inout la_data_in[30];
+ inout la_data_in[31];
+ inout la_data_in[32];
+ inout la_data_in[33];
+ inout la_data_in[34];
+ inout la_data_in[35];
+ inout la_data_in[36];
+ inout la_data_in[37];
+ inout la_data_in[38];
+ inout la_data_in[39];
+ inout la_data_in[3];
+ inout la_data_in[40];
+ inout la_data_in[41];
+ inout la_data_in[42];
+ inout la_data_in[43];
+ inout la_data_in[44];
+ inout la_data_in[45];
+ inout la_data_in[46];
+ inout la_data_in[47];
+ inout la_data_in[48];
+ inout la_data_in[49];
+ inout la_data_in[4];
+ inout la_data_in[50];
+ inout la_data_in[51];
+ inout la_data_in[52];
+ inout la_data_in[53];
+ inout la_data_in[54];
+ inout la_data_in[55];
+ inout la_data_in[56];
+ inout la_data_in[57];
+ inout la_data_in[58];
+ inout la_data_in[59];
+ inout la_data_in[5];
+ inout la_data_in[60];
+ inout la_data_in[61];
+ inout la_data_in[62];
+ inout la_data_in[63];
+ inout la_data_in[64];
+ inout la_data_in[65];
+ inout la_data_in[66];
+ inout la_data_in[67];
+ inout la_data_in[68];
+ inout la_data_in[69];
+ inout la_data_in[6];
+ inout la_data_in[70];
+ inout la_data_in[71];
+ inout la_data_in[72];
+ inout la_data_in[73];
+ inout la_data_in[74];
+ inout la_data_in[75];
+ inout la_data_in[76];
+ inout la_data_in[77];
+ inout la_data_in[78];
+ inout la_data_in[79];
+ inout la_data_in[7];
+ inout la_data_in[80];
+ inout la_data_in[81];
+ inout la_data_in[82];
+ inout la_data_in[83];
+ inout la_data_in[84];
+ inout la_data_in[85];
+ inout la_data_in[86];
+ inout la_data_in[87];
+ inout la_data_in[88];
+ inout la_data_in[89];
+ inout la_data_in[8];
+ inout la_data_in[90];
+ inout la_data_in[91];
+ inout la_data_in[92];
+ inout la_data_in[93];
+ inout la_data_in[94];
+ inout la_data_in[95];
+ inout la_data_in[96];
+ inout la_data_in[97];
+ inout la_data_in[98];
+ inout la_data_in[99];
+ inout la_data_in[9];
+ inout la_data_out[0];
+ inout la_data_out[100];
+ inout la_data_out[101];
+ inout la_data_out[102];
+ inout la_data_out[103];
+ inout la_data_out[104];
+ inout la_data_out[105];
+ inout la_data_out[106];
+ inout la_data_out[107];
+ inout la_data_out[108];
+ inout la_data_out[109];
+ inout la_data_out[10];
+ inout la_data_out[110];
+ inout la_data_out[111];
+ inout la_data_out[112];
+ inout la_data_out[113];
+ inout la_data_out[114];
+ inout la_data_out[115];
+ inout la_data_out[116];
+ inout la_data_out[117];
+ inout la_data_out[118];
+ inout la_data_out[119];
+ inout la_data_out[11];
+ inout la_data_out[120];
+ inout la_data_out[121];
+ inout la_data_out[122];
+ inout la_data_out[123];
+ inout la_data_out[124];
+ inout la_data_out[125];
+ inout la_data_out[126];
+ inout la_data_out[127];
+ inout la_data_out[12];
+ inout la_data_out[13];
+ inout la_data_out[14];
+ inout la_data_out[15];
+ inout la_data_out[16];
+ inout la_data_out[17];
+ inout la_data_out[18];
+ inout la_data_out[19];
+ inout la_data_out[1];
+ inout la_data_out[20];
+ inout la_data_out[21];
+ inout la_data_out[22];
+ inout la_data_out[23];
+ inout la_data_out[24];
+ inout la_data_out[25];
+ inout la_data_out[26];
+ inout la_data_out[27];
+ inout la_data_out[28];
+ inout la_data_out[29];
+ inout la_data_out[2];
+ inout la_data_out[30];
+ inout la_data_out[31];
+ inout la_data_out[32];
+ inout la_data_out[33];
+ inout la_data_out[34];
+ inout la_data_out[35];
+ inout la_data_out[36];
+ inout la_data_out[37];
+ inout la_data_out[38];
+ inout la_data_out[39];
+ inout la_data_out[3];
+ inout la_data_out[40];
+ inout la_data_out[41];
+ inout la_data_out[42];
+ inout la_data_out[43];
+ inout la_data_out[44];
+ inout la_data_out[45];
+ inout la_data_out[46];
+ inout la_data_out[47];
+ inout la_data_out[48];
+ inout la_data_out[49];
+ inout la_data_out[4];
+ inout la_data_out[50];
+ inout la_data_out[51];
+ inout la_data_out[52];
+ inout la_data_out[53];
+ inout la_data_out[54];
+ inout la_data_out[55];
+ inout la_data_out[56];
+ inout la_data_out[57];
+ inout la_data_out[58];
+ inout la_data_out[59];
+ inout la_data_out[5];
+ inout la_data_out[60];
+ inout la_data_out[61];
+ inout la_data_out[62];
+ inout la_data_out[63];
+ inout la_data_out[64];
+ inout la_data_out[65];
+ inout la_data_out[66];
+ inout la_data_out[67];
+ inout la_data_out[68];
+ inout la_data_out[69];
+ inout la_data_out[6];
+ inout la_data_out[70];
+ inout la_data_out[71];
+ inout la_data_out[72];
+ inout la_data_out[73];
+ inout la_data_out[74];
+ inout la_data_out[75];
+ inout la_data_out[76];
+ inout la_data_out[77];
+ inout la_data_out[78];
+ inout la_data_out[79];
+ inout la_data_out[7];
+ inout la_data_out[80];
+ inout la_data_out[81];
+ inout la_data_out[82];
+ inout la_data_out[83];
+ inout la_data_out[84];
+ inout la_data_out[85];
+ inout la_data_out[86];
+ inout la_data_out[87];
+ inout la_data_out[88];
+ inout la_data_out[89];
+ inout la_data_out[8];
+ inout la_data_out[90];
+ inout la_data_out[91];
+ inout la_data_out[92];
+ inout la_data_out[93];
+ inout la_data_out[94];
+ inout la_data_out[95];
+ inout la_data_out[96];
+ inout la_data_out[97];
+ inout la_data_out[98];
+ inout la_data_out[99];
+ inout la_data_out[9];
+ inout la_oenb[0];
+ inout la_oenb[100];
+ inout la_oenb[101];
+ inout la_oenb[102];
+ inout la_oenb[103];
+ inout la_oenb[104];
+ inout la_oenb[105];
+ inout la_oenb[106];
+ inout la_oenb[107];
+ inout la_oenb[108];
+ inout la_oenb[109];
+ inout la_oenb[10];
+ inout la_oenb[110];
+ inout la_oenb[111];
+ inout la_oenb[112];
+ inout la_oenb[113];
+ inout la_oenb[114];
+ inout la_oenb[115];
+ inout la_oenb[116];
+ inout la_oenb[117];
+ inout la_oenb[118];
+ inout la_oenb[119];
+ inout la_oenb[11];
+ inout la_oenb[120];
+ inout la_oenb[121];
+ inout la_oenb[122];
+ inout la_oenb[123];
+ inout la_oenb[124];
+ inout la_oenb[125];
+ inout la_oenb[126];
+ inout la_oenb[127];
+ inout la_oenb[12];
+ inout la_oenb[13];
+ inout la_oenb[14];
+ inout la_oenb[15];
+ inout la_oenb[16];
+ inout la_oenb[17];
+ inout la_oenb[18];
+ inout la_oenb[19];
+ inout la_oenb[1];
+ inout la_oenb[20];
+ inout la_oenb[21];
+ inout la_oenb[22];
+ inout la_oenb[23];
+ inout la_oenb[24];
+ inout la_oenb[25];
+ inout la_oenb[26];
+ inout la_oenb[27];
+ inout la_oenb[28];
+ inout la_oenb[29];
+ inout la_oenb[2];
+ inout la_oenb[30];
+ inout la_oenb[31];
+ inout la_oenb[32];
+ inout la_oenb[33];
+ inout la_oenb[34];
+ inout la_oenb[35];
+ inout la_oenb[36];
+ inout la_oenb[37];
+ inout la_oenb[38];
+ inout la_oenb[39];
+ inout la_oenb[3];
+ inout la_oenb[40];
+ inout la_oenb[41];
+ inout la_oenb[42];
+ inout la_oenb[43];
+ inout la_oenb[44];
+ inout la_oenb[45];
+ inout la_oenb[46];
+ inout la_oenb[47];
+ inout la_oenb[48];
+ inout la_oenb[49];
+ inout la_oenb[4];
+ inout la_oenb[50];
+ inout la_oenb[51];
+ inout la_oenb[52];
+ inout la_oenb[53];
+ inout la_oenb[54];
+ inout la_oenb[55];
+ inout la_oenb[56];
+ inout la_oenb[57];
+ inout la_oenb[58];
+ inout la_oenb[59];
+ inout la_oenb[5];
+ inout la_oenb[60];
+ inout la_oenb[61];
+ inout la_oenb[62];
+ inout la_oenb[63];
+ inout la_oenb[64];
+ inout la_oenb[65];
+ inout la_oenb[66];
+ inout la_oenb[67];
+ inout la_oenb[68];
+ inout la_oenb[69];
+ inout la_oenb[6];
+ inout la_oenb[70];
+ inout la_oenb[71];
+ inout la_oenb[72];
+ inout la_oenb[73];
+ inout la_oenb[74];
+ inout la_oenb[75];
+ inout la_oenb[76];
+ inout la_oenb[77];
+ inout la_oenb[78];
+ inout la_oenb[79];
+ inout la_oenb[7];
+ inout la_oenb[80];
+ inout la_oenb[81];
+ inout la_oenb[82];
+ inout la_oenb[83];
+ inout la_oenb[84];
+ inout la_oenb[85];
+ inout la_oenb[86];
+ inout la_oenb[87];
+ inout la_oenb[88];
+ inout la_oenb[89];
+ inout la_oenb[8];
+ inout la_oenb[90];
+ inout la_oenb[91];
+ inout la_oenb[92];
+ inout la_oenb[93];
+ inout la_oenb[94];
+ inout la_oenb[95];
+ inout la_oenb[96];
+ inout la_oenb[97];
+ inout la_oenb[98];
+ inout la_oenb[99];
+ inout la_oenb[9];
+ inout user_clock2;
+ inout user_irq[0];
+ inout user_irq[1];
+ inout user_irq[2];
+ inout vccd1;
+ inout vccd2;
+ inout vdda1;
+ inout vdda2;
+ inout vssa1;
+ inout vssa2;
+ inout vssd1;
+ inout vssd2;
+ inout wb_clk_i;
+ inout wb_rst_i;
+ inout wbs_ack_o;
+ inout wbs_adr_i[0];
+ inout wbs_adr_i[10];
+ inout wbs_adr_i[11];
+ inout wbs_adr_i[12];
+ inout wbs_adr_i[13];
+ inout wbs_adr_i[14];
+ inout wbs_adr_i[15];
+ inout wbs_adr_i[16];
+ inout wbs_adr_i[17];
+ inout wbs_adr_i[18];
+ inout wbs_adr_i[19];
+ inout wbs_adr_i[1];
+ inout wbs_adr_i[20];
+ inout wbs_adr_i[21];
+ inout wbs_adr_i[22];
+ inout wbs_adr_i[23];
+ inout wbs_adr_i[24];
+ inout wbs_adr_i[25];
+ inout wbs_adr_i[26];
+ inout wbs_adr_i[27];
+ inout wbs_adr_i[28];
+ inout wbs_adr_i[29];
+ inout wbs_adr_i[2];
+ inout wbs_adr_i[30];
+ inout wbs_adr_i[31];
+ inout wbs_adr_i[3];
+ inout wbs_adr_i[4];
+ inout wbs_adr_i[5];
+ inout wbs_adr_i[6];
+ inout wbs_adr_i[7];
+ inout wbs_adr_i[8];
+ inout wbs_adr_i[9];
+ inout wbs_cyc_i;
+ inout wbs_dat_i[0];
+ inout wbs_dat_i[10];
+ inout wbs_dat_i[11];
+ inout wbs_dat_i[12];
+ inout wbs_dat_i[13];
+ inout wbs_dat_i[14];
+ inout wbs_dat_i[15];
+ inout wbs_dat_i[16];
+ inout wbs_dat_i[17];
+ inout wbs_dat_i[18];
+ inout wbs_dat_i[19];
+ inout wbs_dat_i[1];
+ inout wbs_dat_i[20];
+ inout wbs_dat_i[21];
+ inout wbs_dat_i[22];
+ inout wbs_dat_i[23];
+ inout wbs_dat_i[24];
+ inout wbs_dat_i[25];
+ inout wbs_dat_i[26];
+ inout wbs_dat_i[27];
+ inout wbs_dat_i[28];
+ inout wbs_dat_i[29];
+ inout wbs_dat_i[2];
+ inout wbs_dat_i[30];
+ inout wbs_dat_i[31];
+ inout wbs_dat_i[3];
+ inout wbs_dat_i[4];
+ inout wbs_dat_i[5];
+ inout wbs_dat_i[6];
+ inout wbs_dat_i[7];
+ inout wbs_dat_i[8];
+ inout wbs_dat_i[9];
+ inout wbs_dat_o[0];
+ inout wbs_dat_o[10];
+ inout wbs_dat_o[11];
+ inout wbs_dat_o[12];
+ inout wbs_dat_o[13];
+ inout wbs_dat_o[14];
+ inout wbs_dat_o[15];
+ inout wbs_dat_o[16];
+ inout wbs_dat_o[17];
+ inout wbs_dat_o[18];
+ inout wbs_dat_o[19];
+ inout wbs_dat_o[1];
+ inout wbs_dat_o[20];
+ inout wbs_dat_o[21];
+ inout wbs_dat_o[22];
+ inout wbs_dat_o[23];
+ inout wbs_dat_o[24];
+ inout wbs_dat_o[25];
+ inout wbs_dat_o[26];
+ inout wbs_dat_o[27];
+ inout wbs_dat_o[28];
+ inout wbs_dat_o[29];
+ inout wbs_dat_o[2];
+ inout wbs_dat_o[30];
+ inout wbs_dat_o[31];
+ inout wbs_dat_o[3];
+ inout wbs_dat_o[4];
+ inout wbs_dat_o[5];
+ inout wbs_dat_o[6];
+ inout wbs_dat_o[7];
+ inout wbs_dat_o[8];
+ inout wbs_dat_o[9];
+ inout wbs_sel_i[0];
+ inout wbs_sel_i[1];
+ inout wbs_sel_i[2];
+ inout wbs_sel_i[3];
+ inout wbs_stb_i;
+ inout wbs_we_i;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module user_analog_project_wrapper (
+ gpio_analog[0],
+ gpio_analog[10],
+ gpio_analog[11],
+ gpio_analog[12],
+ gpio_analog[13],
+ gpio_analog[14],
+ gpio_analog[15],
+ gpio_analog[16],
+ gpio_analog[17],
+ gpio_analog[1],
+ gpio_analog[2],
+ gpio_analog[3],
+ gpio_analog[4],
+ gpio_analog[5],
+ gpio_analog[6],
+ gpio_analog[7],
+ gpio_analog[8],
+ gpio_analog[9],
+ gpio_noesd[0],
+ gpio_noesd[10],
+ gpio_noesd[11],
+ gpio_noesd[12],
+ gpio_noesd[13],
+ gpio_noesd[14],
+ gpio_noesd[15],
+ gpio_noesd[16],
+ gpio_noesd[17],
+ gpio_noesd[1],
+ gpio_noesd[2],
+ gpio_noesd[3],
+ gpio_noesd[4],
+ gpio_noesd[5],
+ gpio_noesd[6],
+ gpio_noesd[7],
+ gpio_noesd[8],
+ gpio_noesd[9],
+ io_analog[0],
+ io_analog[10],
+ io_analog[1],
+ io_analog[2],
+ io_analog[3],
+ io_analog[4],
+ io_analog[5],
+ io_analog[6],
+ io_analog[7],
+ io_analog[8],
+ io_analog[9],
+ io_clamp_high[0],
+ io_clamp_high[1],
+ io_clamp_high[2],
+ io_clamp_low[0],
+ io_clamp_low[1],
+ io_clamp_low[2],
+ io_in[0],
+ io_in[10],
+ io_in[11],
+ io_in[12],
+ io_in[13],
+ io_in[14],
+ io_in[15],
+ io_in[16],
+ io_in[17],
+ io_in[18],
+ io_in[19],
+ io_in[1],
+ io_in[20],
+ io_in[21],
+ io_in[22],
+ io_in[23],
+ io_in[24],
+ io_in[25],
+ io_in[26],
+ io_in[2],
+ io_in[3],
+ io_in[4],
+ io_in[5],
+ io_in[6],
+ io_in[7],
+ io_in[8],
+ io_in[9],
+ io_in_3v3[0],
+ io_in_3v3[10],
+ io_in_3v3[11],
+ io_in_3v3[12],
+ io_in_3v3[13],
+ io_in_3v3[14],
+ io_in_3v3[15],
+ io_in_3v3[16],
+ io_in_3v3[17],
+ io_in_3v3[18],
+ io_in_3v3[19],
+ io_in_3v3[1],
+ io_in_3v3[20],
+ io_in_3v3[21],
+ io_in_3v3[22],
+ io_in_3v3[23],
+ io_in_3v3[24],
+ io_in_3v3[25],
+ io_in_3v3[26],
+ io_in_3v3[2],
+ io_in_3v3[3],
+ io_in_3v3[4],
+ io_in_3v3[5],
+ io_in_3v3[6],
+ io_in_3v3[7],
+ io_in_3v3[8],
+ io_in_3v3[9],
+ io_oeb[0],
+ io_oeb[10],
+ io_oeb[11],
+ io_oeb[12],
+ io_oeb[13],
+ io_oeb[14],
+ io_oeb[15],
+ io_oeb[16],
+ io_oeb[17],
+ io_oeb[18],
+ io_oeb[19],
+ io_oeb[1],
+ io_oeb[20],
+ io_oeb[21],
+ io_oeb[22],
+ io_oeb[23],
+ io_oeb[24],
+ io_oeb[25],
+ io_oeb[26],
+ io_oeb[2],
+ io_oeb[3],
+ io_oeb[4],
+ io_oeb[5],
+ io_oeb[6],
+ io_oeb[7],
+ io_oeb[8],
+ io_oeb[9],
+ io_out[0],
+ io_out[10],
+ io_out[11],
+ io_out[12],
+ io_out[13],
+ io_out[14],
+ io_out[15],
+ io_out[16],
+ io_out[17],
+ io_out[18],
+ io_out[19],
+ io_out[1],
+ io_out[20],
+ io_out[21],
+ io_out[22],
+ io_out[23],
+ io_out[24],
+ io_out[25],
+ io_out[26],
+ io_out[2],
+ io_out[3],
+ io_out[4],
+ io_out[5],
+ io_out[6],
+ io_out[7],
+ io_out[8],
+ io_out[9],
+ la_data_in[0],
+ la_data_in[100],
+ la_data_in[101],
+ la_data_in[102],
+ la_data_in[103],
+ la_data_in[104],
+ la_data_in[105],
+ la_data_in[106],
+ la_data_in[107],
+ la_data_in[108],
+ la_data_in[109],
+ la_data_in[10],
+ la_data_in[110],
+ la_data_in[111],
+ la_data_in[112],
+ la_data_in[113],
+ la_data_in[114],
+ la_data_in[115],
+ la_data_in[116],
+ la_data_in[117],
+ la_data_in[118],
+ la_data_in[119],
+ la_data_in[11],
+ la_data_in[120],
+ la_data_in[121],
+ la_data_in[122],
+ la_data_in[123],
+ la_data_in[124],
+ la_data_in[125],
+ la_data_in[126],
+ la_data_in[127],
+ la_data_in[12],
+ la_data_in[13],
+ la_data_in[14],
+ la_data_in[15],
+ la_data_in[16],
+ la_data_in[17],
+ la_data_in[18],
+ la_data_in[19],
+ la_data_in[1],
+ la_data_in[20],
+ la_data_in[21],
+ la_data_in[22],
+ la_data_in[23],
+ la_data_in[24],
+ la_data_in[25],
+ la_data_in[26],
+ la_data_in[27],
+ la_data_in[28],
+ la_data_in[29],
+ la_data_in[2],
+ la_data_in[30],
+ la_data_in[31],
+ la_data_in[32],
+ la_data_in[33],
+ la_data_in[34],
+ la_data_in[35],
+ la_data_in[36],
+ la_data_in[37],
+ la_data_in[38],
+ la_data_in[39],
+ la_data_in[3],
+ la_data_in[40],
+ la_data_in[41],
+ la_data_in[42],
+ la_data_in[43],
+ la_data_in[44],
+ la_data_in[45],
+ la_data_in[46],
+ la_data_in[47],
+ la_data_in[48],
+ la_data_in[49],
+ la_data_in[4],
+ la_data_in[50],
+ la_data_in[51],
+ la_data_in[52],
+ la_data_in[53],
+ la_data_in[54],
+ la_data_in[55],
+ la_data_in[56],
+ la_data_in[57],
+ la_data_in[58],
+ la_data_in[59],
+ la_data_in[5],
+ la_data_in[60],
+ la_data_in[61],
+ la_data_in[62],
+ la_data_in[63],
+ la_data_in[64],
+ la_data_in[65],
+ la_data_in[66],
+ la_data_in[67],
+ la_data_in[68],
+ la_data_in[69],
+ la_data_in[6],
+ la_data_in[70],
+ la_data_in[71],
+ la_data_in[72],
+ la_data_in[73],
+ la_data_in[74],
+ la_data_in[75],
+ la_data_in[76],
+ la_data_in[77],
+ la_data_in[78],
+ la_data_in[79],
+ la_data_in[7],
+ la_data_in[80],
+ la_data_in[81],
+ la_data_in[82],
+ la_data_in[83],
+ la_data_in[84],
+ la_data_in[85],
+ la_data_in[86],
+ la_data_in[87],
+ la_data_in[88],
+ la_data_in[89],
+ la_data_in[8],
+ la_data_in[90],
+ la_data_in[91],
+ la_data_in[92],
+ la_data_in[93],
+ la_data_in[94],
+ la_data_in[95],
+ la_data_in[96],
+ la_data_in[97],
+ la_data_in[98],
+ la_data_in[99],
+ la_data_in[9],
+ la_data_out[0],
+ la_data_out[100],
+ la_data_out[101],
+ la_data_out[102],
+ la_data_out[103],
+ la_data_out[104],
+ la_data_out[105],
+ la_data_out[106],
+ la_data_out[107],
+ la_data_out[108],
+ la_data_out[109],
+ la_data_out[10],
+ la_data_out[110],
+ la_data_out[111],
+ la_data_out[112],
+ la_data_out[113],
+ la_data_out[114],
+ la_data_out[115],
+ la_data_out[116],
+ la_data_out[117],
+ la_data_out[118],
+ la_data_out[119],
+ la_data_out[11],
+ la_data_out[120],
+ la_data_out[121],
+ la_data_out[122],
+ la_data_out[123],
+ la_data_out[124],
+ la_data_out[125],
+ la_data_out[126],
+ la_data_out[127],
+ la_data_out[12],
+ la_data_out[13],
+ la_data_out[14],
+ la_data_out[15],
+ la_data_out[16],
+ la_data_out[17],
+ la_data_out[18],
+ la_data_out[19],
+ la_data_out[1],
+ la_data_out[20],
+ la_data_out[21],
+ la_data_out[22],
+ la_data_out[23],
+ la_data_out[24],
+ la_data_out[25],
+ la_data_out[26],
+ la_data_out[27],
+ la_data_out[28],
+ la_data_out[29],
+ la_data_out[2],
+ la_data_out[30],
+ la_data_out[31],
+ la_data_out[32],
+ la_data_out[33],
+ la_data_out[34],
+ la_data_out[35],
+ la_data_out[36],
+ la_data_out[37],
+ la_data_out[38],
+ la_data_out[39],
+ la_data_out[3],
+ la_data_out[40],
+ la_data_out[41],
+ la_data_out[42],
+ la_data_out[43],
+ la_data_out[44],
+ la_data_out[45],
+ la_data_out[46],
+ la_data_out[47],
+ la_data_out[48],
+ la_data_out[49],
+ la_data_out[4],
+ la_data_out[50],
+ la_data_out[51],
+ la_data_out[52],
+ la_data_out[53],
+ la_data_out[54],
+ la_data_out[55],
+ la_data_out[56],
+ la_data_out[57],
+ la_data_out[58],
+ la_data_out[59],
+ la_data_out[5],
+ la_data_out[60],
+ la_data_out[61],
+ la_data_out[62],
+ la_data_out[63],
+ la_data_out[64],
+ la_data_out[65],
+ la_data_out[66],
+ la_data_out[67],
+ la_data_out[68],
+ la_data_out[69],
+ la_data_out[6],
+ la_data_out[70],
+ la_data_out[71],
+ la_data_out[72],
+ la_data_out[73],
+ la_data_out[74],
+ la_data_out[75],
+ la_data_out[76],
+ la_data_out[77],
+ la_data_out[78],
+ la_data_out[79],
+ la_data_out[7],
+ la_data_out[80],
+ la_data_out[81],
+ la_data_out[82],
+ la_data_out[83],
+ la_data_out[84],
+ la_data_out[85],
+ la_data_out[86],
+ la_data_out[87],
+ la_data_out[88],
+ la_data_out[89],
+ la_data_out[8],
+ la_data_out[90],
+ la_data_out[91],
+ la_data_out[92],
+ la_data_out[93],
+ la_data_out[94],
+ la_data_out[95],
+ la_data_out[96],
+ la_data_out[97],
+ la_data_out[98],
+ la_data_out[99],
+ la_data_out[9],
+ la_oenb[0],
+ la_oenb[100],
+ la_oenb[101],
+ la_oenb[102],
+ la_oenb[103],
+ la_oenb[104],
+ la_oenb[105],
+ la_oenb[106],
+ la_oenb[107],
+ la_oenb[108],
+ la_oenb[109],
+ la_oenb[10],
+ la_oenb[110],
+ la_oenb[111],
+ la_oenb[112],
+ la_oenb[113],
+ la_oenb[114],
+ la_oenb[115],
+ la_oenb[116],
+ la_oenb[117],
+ la_oenb[118],
+ la_oenb[119],
+ la_oenb[11],
+ la_oenb[120],
+ la_oenb[121],
+ la_oenb[122],
+ la_oenb[123],
+ la_oenb[124],
+ la_oenb[125],
+ la_oenb[126],
+ la_oenb[127],
+ la_oenb[12],
+ la_oenb[13],
+ la_oenb[14],
+ la_oenb[15],
+ la_oenb[16],
+ la_oenb[17],
+ la_oenb[18],
+ la_oenb[19],
+ la_oenb[1],
+ la_oenb[20],
+ la_oenb[21],
+ la_oenb[22],
+ la_oenb[23],
+ la_oenb[24],
+ la_oenb[25],
+ la_oenb[26],
+ la_oenb[27],
+ la_oenb[28],
+ la_oenb[29],
+ la_oenb[2],
+ la_oenb[30],
+ la_oenb[31],
+ la_oenb[32],
+ la_oenb[33],
+ la_oenb[34],
+ la_oenb[35],
+ la_oenb[36],
+ la_oenb[37],
+ la_oenb[38],
+ la_oenb[39],
+ la_oenb[3],
+ la_oenb[40],
+ la_oenb[41],
+ la_oenb[42],
+ la_oenb[43],
+ la_oenb[44],
+ la_oenb[45],
+ la_oenb[46],
+ la_oenb[47],
+ la_oenb[48],
+ la_oenb[49],
+ la_oenb[4],
+ la_oenb[50],
+ la_oenb[51],
+ la_oenb[52],
+ la_oenb[53],
+ la_oenb[54],
+ la_oenb[55],
+ la_oenb[56],
+ la_oenb[57],
+ la_oenb[58],
+ la_oenb[59],
+ la_oenb[5],
+ la_oenb[60],
+ la_oenb[61],
+ la_oenb[62],
+ la_oenb[63],
+ la_oenb[64],
+ la_oenb[65],
+ la_oenb[66],
+ la_oenb[67],
+ la_oenb[68],
+ la_oenb[69],
+ la_oenb[6],
+ la_oenb[70],
+ la_oenb[71],
+ la_oenb[72],
+ la_oenb[73],
+ la_oenb[74],
+ la_oenb[75],
+ la_oenb[76],
+ la_oenb[77],
+ la_oenb[78],
+ la_oenb[79],
+ la_oenb[7],
+ la_oenb[80],
+ la_oenb[81],
+ la_oenb[82],
+ la_oenb[83],
+ la_oenb[84],
+ la_oenb[85],
+ la_oenb[86],
+ la_oenb[87],
+ la_oenb[88],
+ la_oenb[89],
+ la_oenb[8],
+ la_oenb[90],
+ la_oenb[91],
+ la_oenb[92],
+ la_oenb[93],
+ la_oenb[94],
+ la_oenb[95],
+ la_oenb[96],
+ la_oenb[97],
+ la_oenb[98],
+ la_oenb[99],
+ la_oenb[9],
+ user_clock2,
+ user_irq[0],
+ user_irq[1],
+ user_irq[2],
+ vccd1,
+ vccd2,
+ vdda1,
+ vdda2,
+ vssa1,
+ vssa2,
+ vssd1,
+ vssd2,
+ wb_clk_i,
+ wb_rst_i,
+ wbs_ack_o,
+ wbs_adr_i[0],
+ wbs_adr_i[10],
+ wbs_adr_i[11],
+ wbs_adr_i[12],
+ wbs_adr_i[13],
+ wbs_adr_i[14],
+ wbs_adr_i[15],
+ wbs_adr_i[16],
+ wbs_adr_i[17],
+ wbs_adr_i[18],
+ wbs_adr_i[19],
+ wbs_adr_i[1],
+ wbs_adr_i[20],
+ wbs_adr_i[21],
+ wbs_adr_i[22],
+ wbs_adr_i[23],
+ wbs_adr_i[24],
+ wbs_adr_i[25],
+ wbs_adr_i[26],
+ wbs_adr_i[27],
+ wbs_adr_i[28],
+ wbs_adr_i[29],
+ wbs_adr_i[2],
+ wbs_adr_i[30],
+ wbs_adr_i[31],
+ wbs_adr_i[3],
+ wbs_adr_i[4],
+ wbs_adr_i[5],
+ wbs_adr_i[6],
+ wbs_adr_i[7],
+ wbs_adr_i[8],
+ wbs_adr_i[9],
+ wbs_cyc_i,
+ wbs_dat_i[0],
+ wbs_dat_i[10],
+ wbs_dat_i[11],
+ wbs_dat_i[12],
+ wbs_dat_i[13],
+ wbs_dat_i[14],
+ wbs_dat_i[15],
+ wbs_dat_i[16],
+ wbs_dat_i[17],
+ wbs_dat_i[18],
+ wbs_dat_i[19],
+ wbs_dat_i[1],
+ wbs_dat_i[20],
+ wbs_dat_i[21],
+ wbs_dat_i[22],
+ wbs_dat_i[23],
+ wbs_dat_i[24],
+ wbs_dat_i[25],
+ wbs_dat_i[26],
+ wbs_dat_i[27],
+ wbs_dat_i[28],
+ wbs_dat_i[29],
+ wbs_dat_i[2],
+ wbs_dat_i[30],
+ wbs_dat_i[31],
+ wbs_dat_i[3],
+ wbs_dat_i[4],
+ wbs_dat_i[5],
+ wbs_dat_i[6],
+ wbs_dat_i[7],
+ wbs_dat_i[8],
+ wbs_dat_i[9],
+ wbs_dat_o[0],
+ wbs_dat_o[10],
+ wbs_dat_o[11],
+ wbs_dat_o[12],
+ wbs_dat_o[13],
+ wbs_dat_o[14],
+ wbs_dat_o[15],
+ wbs_dat_o[16],
+ wbs_dat_o[17],
+ wbs_dat_o[18],
+ wbs_dat_o[19],
+ wbs_dat_o[1],
+ wbs_dat_o[20],
+ wbs_dat_o[21],
+ wbs_dat_o[22],
+ wbs_dat_o[23],
+ wbs_dat_o[24],
+ wbs_dat_o[25],
+ wbs_dat_o[26],
+ wbs_dat_o[27],
+ wbs_dat_o[28],
+ wbs_dat_o[29],
+ wbs_dat_o[2],
+ wbs_dat_o[30],
+ wbs_dat_o[31],
+ wbs_dat_o[3],
+ wbs_dat_o[4],
+ wbs_dat_o[5],
+ wbs_dat_o[6],
+ wbs_dat_o[7],
+ wbs_dat_o[8],
+ wbs_dat_o[9],
+ wbs_sel_i[0],
+ wbs_sel_i[1],
+ wbs_sel_i[2],
+ wbs_sel_i[3],
+ wbs_stb_i,
+ wbs_we_i
+);
+ inout gpio_analog[0];
+ inout gpio_analog[10];
+ inout gpio_analog[11];
+ inout gpio_analog[12];
+ inout gpio_analog[13];
+ inout gpio_analog[14];
+ inout gpio_analog[15];
+ inout gpio_analog[16];
+ inout gpio_analog[17];
+ inout gpio_analog[1];
+ inout gpio_analog[2];
+ inout gpio_analog[3];
+ inout gpio_analog[4];
+ inout gpio_analog[5];
+ inout gpio_analog[6];
+ inout gpio_analog[7];
+ inout gpio_analog[8];
+ inout gpio_analog[9];
+ inout gpio_noesd[0];
+ inout gpio_noesd[10];
+ inout gpio_noesd[11];
+ inout gpio_noesd[12];
+ inout gpio_noesd[13];
+ inout gpio_noesd[14];
+ inout gpio_noesd[15];
+ inout gpio_noesd[16];
+ inout gpio_noesd[17];
+ inout gpio_noesd[1];
+ inout gpio_noesd[2];
+ inout gpio_noesd[3];
+ inout gpio_noesd[4];
+ inout gpio_noesd[5];
+ inout gpio_noesd[6];
+ inout gpio_noesd[7];
+ inout gpio_noesd[8];
+ inout gpio_noesd[9];
+ inout io_analog[0];
+ inout io_analog[10];
+ inout io_analog[1];
+ inout io_analog[2];
+ inout io_analog[3];
+ inout io_analog[4];
+ inout io_analog[5];
+ inout io_analog[6];
+ inout io_analog[7];
+ inout io_analog[8];
+ inout io_analog[9];
+ inout io_clamp_high[0];
+ inout io_clamp_high[1];
+ inout io_clamp_high[2];
+ inout io_clamp_low[0];
+ inout io_clamp_low[1];
+ inout io_clamp_low[2];
+ inout io_in[0];
+ inout io_in[10];
+ inout io_in[11];
+ inout io_in[12];
+ inout io_in[13];
+ inout io_in[14];
+ inout io_in[15];
+ inout io_in[16];
+ inout io_in[17];
+ inout io_in[18];
+ inout io_in[19];
+ inout io_in[1];
+ inout io_in[20];
+ inout io_in[21];
+ inout io_in[22];
+ inout io_in[23];
+ inout io_in[24];
+ inout io_in[25];
+ inout io_in[26];
+ inout io_in[2];
+ inout io_in[3];
+ inout io_in[4];
+ inout io_in[5];
+ inout io_in[6];
+ inout io_in[7];
+ inout io_in[8];
+ inout io_in[9];
+ inout io_in_3v3[0];
+ inout io_in_3v3[10];
+ inout io_in_3v3[11];
+ inout io_in_3v3[12];
+ inout io_in_3v3[13];
+ inout io_in_3v3[14];
+ inout io_in_3v3[15];
+ inout io_in_3v3[16];
+ inout io_in_3v3[17];
+ inout io_in_3v3[18];
+ inout io_in_3v3[19];
+ inout io_in_3v3[1];
+ inout io_in_3v3[20];
+ inout io_in_3v3[21];
+ inout io_in_3v3[22];
+ inout io_in_3v3[23];
+ inout io_in_3v3[24];
+ inout io_in_3v3[25];
+ inout io_in_3v3[26];
+ inout io_in_3v3[2];
+ inout io_in_3v3[3];
+ inout io_in_3v3[4];
+ inout io_in_3v3[5];
+ inout io_in_3v3[6];
+ inout io_in_3v3[7];
+ inout io_in_3v3[8];
+ inout io_in_3v3[9];
+ inout io_oeb[0];
+ inout io_oeb[10];
+ inout io_oeb[11];
+ inout io_oeb[12];
+ inout io_oeb[13];
+ inout io_oeb[14];
+ inout io_oeb[15];
+ inout io_oeb[16];
+ inout io_oeb[17];
+ inout io_oeb[18];
+ inout io_oeb[19];
+ inout io_oeb[1];
+ inout io_oeb[20];
+ inout io_oeb[21];
+ inout io_oeb[22];
+ inout io_oeb[23];
+ inout io_oeb[24];
+ inout io_oeb[25];
+ inout io_oeb[26];
+ inout io_oeb[2];
+ inout io_oeb[3];
+ inout io_oeb[4];
+ inout io_oeb[5];
+ inout io_oeb[6];
+ inout io_oeb[7];
+ inout io_oeb[8];
+ inout io_oeb[9];
+ inout io_out[0];
+ inout io_out[10];
+ inout io_out[11];
+ inout io_out[12];
+ inout io_out[13];
+ inout io_out[14];
+ inout io_out[15];
+ inout io_out[16];
+ inout io_out[17];
+ inout io_out[18];
+ inout io_out[19];
+ inout io_out[1];
+ inout io_out[20];
+ inout io_out[21];
+ inout io_out[22];
+ inout io_out[23];
+ inout io_out[24];
+ inout io_out[25];
+ inout io_out[26];
+ inout io_out[2];
+ inout io_out[3];
+ inout io_out[4];
+ inout io_out[5];
+ inout io_out[6];
+ inout io_out[7];
+ inout io_out[8];
+ inout io_out[9];
+ inout la_data_in[0];
+ inout la_data_in[100];
+ inout la_data_in[101];
+ inout la_data_in[102];
+ inout la_data_in[103];
+ inout la_data_in[104];
+ inout la_data_in[105];
+ inout la_data_in[106];
+ inout la_data_in[107];
+ inout la_data_in[108];
+ inout la_data_in[109];
+ inout la_data_in[10];
+ inout la_data_in[110];
+ inout la_data_in[111];
+ inout la_data_in[112];
+ inout la_data_in[113];
+ inout la_data_in[114];
+ inout la_data_in[115];
+ inout la_data_in[116];
+ inout la_data_in[117];
+ inout la_data_in[118];
+ inout la_data_in[119];
+ inout la_data_in[11];
+ inout la_data_in[120];
+ inout la_data_in[121];
+ inout la_data_in[122];
+ inout la_data_in[123];
+ inout la_data_in[124];
+ inout la_data_in[125];
+ inout la_data_in[126];
+ inout la_data_in[127];
+ inout la_data_in[12];
+ inout la_data_in[13];
+ inout la_data_in[14];
+ inout la_data_in[15];
+ inout la_data_in[16];
+ inout la_data_in[17];
+ inout la_data_in[18];
+ inout la_data_in[19];
+ inout la_data_in[1];
+ inout la_data_in[20];
+ inout la_data_in[21];
+ inout la_data_in[22];
+ inout la_data_in[23];
+ inout la_data_in[24];
+ inout la_data_in[25];
+ inout la_data_in[26];
+ inout la_data_in[27];
+ inout la_data_in[28];
+ inout la_data_in[29];
+ inout la_data_in[2];
+ inout la_data_in[30];
+ inout la_data_in[31];
+ inout la_data_in[32];
+ inout la_data_in[33];
+ inout la_data_in[34];
+ inout la_data_in[35];
+ inout la_data_in[36];
+ inout la_data_in[37];
+ inout la_data_in[38];
+ inout la_data_in[39];
+ inout la_data_in[3];
+ inout la_data_in[40];
+ inout la_data_in[41];
+ inout la_data_in[42];
+ inout la_data_in[43];
+ inout la_data_in[44];
+ inout la_data_in[45];
+ inout la_data_in[46];
+ inout la_data_in[47];
+ inout la_data_in[48];
+ inout la_data_in[49];
+ inout la_data_in[4];
+ inout la_data_in[50];
+ inout la_data_in[51];
+ inout la_data_in[52];
+ inout la_data_in[53];
+ inout la_data_in[54];
+ inout la_data_in[55];
+ inout la_data_in[56];
+ inout la_data_in[57];
+ inout la_data_in[58];
+ inout la_data_in[59];
+ inout la_data_in[5];
+ inout la_data_in[60];
+ inout la_data_in[61];
+ inout la_data_in[62];
+ inout la_data_in[63];
+ inout la_data_in[64];
+ inout la_data_in[65];
+ inout la_data_in[66];
+ inout la_data_in[67];
+ inout la_data_in[68];
+ inout la_data_in[69];
+ inout la_data_in[6];
+ inout la_data_in[70];
+ inout la_data_in[71];
+ inout la_data_in[72];
+ inout la_data_in[73];
+ inout la_data_in[74];
+ inout la_data_in[75];
+ inout la_data_in[76];
+ inout la_data_in[77];
+ inout la_data_in[78];
+ inout la_data_in[79];
+ inout la_data_in[7];
+ inout la_data_in[80];
+ inout la_data_in[81];
+ inout la_data_in[82];
+ inout la_data_in[83];
+ inout la_data_in[84];
+ inout la_data_in[85];
+ inout la_data_in[86];
+ inout la_data_in[87];
+ inout la_data_in[88];
+ inout la_data_in[89];
+ inout la_data_in[8];
+ inout la_data_in[90];
+ inout la_data_in[91];
+ inout la_data_in[92];
+ inout la_data_in[93];
+ inout la_data_in[94];
+ inout la_data_in[95];
+ inout la_data_in[96];
+ inout la_data_in[97];
+ inout la_data_in[98];
+ inout la_data_in[99];
+ inout la_data_in[9];
+ inout la_data_out[0];
+ inout la_data_out[100];
+ inout la_data_out[101];
+ inout la_data_out[102];
+ inout la_data_out[103];
+ inout la_data_out[104];
+ inout la_data_out[105];
+ inout la_data_out[106];
+ inout la_data_out[107];
+ inout la_data_out[108];
+ inout la_data_out[109];
+ inout la_data_out[10];
+ inout la_data_out[110];
+ inout la_data_out[111];
+ inout la_data_out[112];
+ inout la_data_out[113];
+ inout la_data_out[114];
+ inout la_data_out[115];
+ inout la_data_out[116];
+ inout la_data_out[117];
+ inout la_data_out[118];
+ inout la_data_out[119];
+ inout la_data_out[11];
+ inout la_data_out[120];
+ inout la_data_out[121];
+ inout la_data_out[122];
+ inout la_data_out[123];
+ inout la_data_out[124];
+ inout la_data_out[125];
+ inout la_data_out[126];
+ inout la_data_out[127];
+ inout la_data_out[12];
+ inout la_data_out[13];
+ inout la_data_out[14];
+ inout la_data_out[15];
+ inout la_data_out[16];
+ inout la_data_out[17];
+ inout la_data_out[18];
+ inout la_data_out[19];
+ inout la_data_out[1];
+ inout la_data_out[20];
+ inout la_data_out[21];
+ inout la_data_out[22];
+ inout la_data_out[23];
+ inout la_data_out[24];
+ inout la_data_out[25];
+ inout la_data_out[26];
+ inout la_data_out[27];
+ inout la_data_out[28];
+ inout la_data_out[29];
+ inout la_data_out[2];
+ inout la_data_out[30];
+ inout la_data_out[31];
+ inout la_data_out[32];
+ inout la_data_out[33];
+ inout la_data_out[34];
+ inout la_data_out[35];
+ inout la_data_out[36];
+ inout la_data_out[37];
+ inout la_data_out[38];
+ inout la_data_out[39];
+ inout la_data_out[3];
+ inout la_data_out[40];
+ inout la_data_out[41];
+ inout la_data_out[42];
+ inout la_data_out[43];
+ inout la_data_out[44];
+ inout la_data_out[45];
+ inout la_data_out[46];
+ inout la_data_out[47];
+ inout la_data_out[48];
+ inout la_data_out[49];
+ inout la_data_out[4];
+ inout la_data_out[50];
+ inout la_data_out[51];
+ inout la_data_out[52];
+ inout la_data_out[53];
+ inout la_data_out[54];
+ inout la_data_out[55];
+ inout la_data_out[56];
+ inout la_data_out[57];
+ inout la_data_out[58];
+ inout la_data_out[59];
+ inout la_data_out[5];
+ inout la_data_out[60];
+ inout la_data_out[61];
+ inout la_data_out[62];
+ inout la_data_out[63];
+ inout la_data_out[64];
+ inout la_data_out[65];
+ inout la_data_out[66];
+ inout la_data_out[67];
+ inout la_data_out[68];
+ inout la_data_out[69];
+ inout la_data_out[6];
+ inout la_data_out[70];
+ inout la_data_out[71];
+ inout la_data_out[72];
+ inout la_data_out[73];
+ inout la_data_out[74];
+ inout la_data_out[75];
+ inout la_data_out[76];
+ inout la_data_out[77];
+ inout la_data_out[78];
+ inout la_data_out[79];
+ inout la_data_out[7];
+ inout la_data_out[80];
+ inout la_data_out[81];
+ inout la_data_out[82];
+ inout la_data_out[83];
+ inout la_data_out[84];
+ inout la_data_out[85];
+ inout la_data_out[86];
+ inout la_data_out[87];
+ inout la_data_out[88];
+ inout la_data_out[89];
+ inout la_data_out[8];
+ inout la_data_out[90];
+ inout la_data_out[91];
+ inout la_data_out[92];
+ inout la_data_out[93];
+ inout la_data_out[94];
+ inout la_data_out[95];
+ inout la_data_out[96];
+ inout la_data_out[97];
+ inout la_data_out[98];
+ inout la_data_out[99];
+ inout la_data_out[9];
+ inout la_oenb[0];
+ inout la_oenb[100];
+ inout la_oenb[101];
+ inout la_oenb[102];
+ inout la_oenb[103];
+ inout la_oenb[104];
+ inout la_oenb[105];
+ inout la_oenb[106];
+ inout la_oenb[107];
+ inout la_oenb[108];
+ inout la_oenb[109];
+ inout la_oenb[10];
+ inout la_oenb[110];
+ inout la_oenb[111];
+ inout la_oenb[112];
+ inout la_oenb[113];
+ inout la_oenb[114];
+ inout la_oenb[115];
+ inout la_oenb[116];
+ inout la_oenb[117];
+ inout la_oenb[118];
+ inout la_oenb[119];
+ inout la_oenb[11];
+ inout la_oenb[120];
+ inout la_oenb[121];
+ inout la_oenb[122];
+ inout la_oenb[123];
+ inout la_oenb[124];
+ inout la_oenb[125];
+ inout la_oenb[126];
+ inout la_oenb[127];
+ inout la_oenb[12];
+ inout la_oenb[13];
+ inout la_oenb[14];
+ inout la_oenb[15];
+ inout la_oenb[16];
+ inout la_oenb[17];
+ inout la_oenb[18];
+ inout la_oenb[19];
+ inout la_oenb[1];
+ inout la_oenb[20];
+ inout la_oenb[21];
+ inout la_oenb[22];
+ inout la_oenb[23];
+ inout la_oenb[24];
+ inout la_oenb[25];
+ inout la_oenb[26];
+ inout la_oenb[27];
+ inout la_oenb[28];
+ inout la_oenb[29];
+ inout la_oenb[2];
+ inout la_oenb[30];
+ inout la_oenb[31];
+ inout la_oenb[32];
+ inout la_oenb[33];
+ inout la_oenb[34];
+ inout la_oenb[35];
+ inout la_oenb[36];
+ inout la_oenb[37];
+ inout la_oenb[38];
+ inout la_oenb[39];
+ inout la_oenb[3];
+ inout la_oenb[40];
+ inout la_oenb[41];
+ inout la_oenb[42];
+ inout la_oenb[43];
+ inout la_oenb[44];
+ inout la_oenb[45];
+ inout la_oenb[46];
+ inout la_oenb[47];
+ inout la_oenb[48];
+ inout la_oenb[49];
+ inout la_oenb[4];
+ inout la_oenb[50];
+ inout la_oenb[51];
+ inout la_oenb[52];
+ inout la_oenb[53];
+ inout la_oenb[54];
+ inout la_oenb[55];
+ inout la_oenb[56];
+ inout la_oenb[57];
+ inout la_oenb[58];
+ inout la_oenb[59];
+ inout la_oenb[5];
+ inout la_oenb[60];
+ inout la_oenb[61];
+ inout la_oenb[62];
+ inout la_oenb[63];
+ inout la_oenb[64];
+ inout la_oenb[65];
+ inout la_oenb[66];
+ inout la_oenb[67];
+ inout la_oenb[68];
+ inout la_oenb[69];
+ inout la_oenb[6];
+ inout la_oenb[70];
+ inout la_oenb[71];
+ inout la_oenb[72];
+ inout la_oenb[73];
+ inout la_oenb[74];
+ inout la_oenb[75];
+ inout la_oenb[76];
+ inout la_oenb[77];
+ inout la_oenb[78];
+ inout la_oenb[79];
+ inout la_oenb[7];
+ inout la_oenb[80];
+ inout la_oenb[81];
+ inout la_oenb[82];
+ inout la_oenb[83];
+ inout la_oenb[84];
+ inout la_oenb[85];
+ inout la_oenb[86];
+ inout la_oenb[87];
+ inout la_oenb[88];
+ inout la_oenb[89];
+ inout la_oenb[8];
+ inout la_oenb[90];
+ inout la_oenb[91];
+ inout la_oenb[92];
+ inout la_oenb[93];
+ inout la_oenb[94];
+ inout la_oenb[95];
+ inout la_oenb[96];
+ inout la_oenb[97];
+ inout la_oenb[98];
+ inout la_oenb[99];
+ inout la_oenb[9];
+ inout user_clock2;
+ inout user_irq[0];
+ inout user_irq[1];
+ inout user_irq[2];
+ inout vccd1;
+ inout vccd2;
+ inout vdda1;
+ inout vdda2;
+ inout vssa1;
+ inout vssa2;
+ inout vssd1;
+ inout vssd2;
+ inout wb_clk_i;
+ inout wb_rst_i;
+ inout wbs_ack_o;
+ inout wbs_adr_i[0];
+ inout wbs_adr_i[10];
+ inout wbs_adr_i[11];
+ inout wbs_adr_i[12];
+ inout wbs_adr_i[13];
+ inout wbs_adr_i[14];
+ inout wbs_adr_i[15];
+ inout wbs_adr_i[16];
+ inout wbs_adr_i[17];
+ inout wbs_adr_i[18];
+ inout wbs_adr_i[19];
+ inout wbs_adr_i[1];
+ inout wbs_adr_i[20];
+ inout wbs_adr_i[21];
+ inout wbs_adr_i[22];
+ inout wbs_adr_i[23];
+ inout wbs_adr_i[24];
+ inout wbs_adr_i[25];
+ inout wbs_adr_i[26];
+ inout wbs_adr_i[27];
+ inout wbs_adr_i[28];
+ inout wbs_adr_i[29];
+ inout wbs_adr_i[2];
+ inout wbs_adr_i[30];
+ inout wbs_adr_i[31];
+ inout wbs_adr_i[3];
+ inout wbs_adr_i[4];
+ inout wbs_adr_i[5];
+ inout wbs_adr_i[6];
+ inout wbs_adr_i[7];
+ inout wbs_adr_i[8];
+ inout wbs_adr_i[9];
+ inout wbs_cyc_i;
+ inout wbs_dat_i[0];
+ inout wbs_dat_i[10];
+ inout wbs_dat_i[11];
+ inout wbs_dat_i[12];
+ inout wbs_dat_i[13];
+ inout wbs_dat_i[14];
+ inout wbs_dat_i[15];
+ inout wbs_dat_i[16];
+ inout wbs_dat_i[17];
+ inout wbs_dat_i[18];
+ inout wbs_dat_i[19];
+ inout wbs_dat_i[1];
+ inout wbs_dat_i[20];
+ inout wbs_dat_i[21];
+ inout wbs_dat_i[22];
+ inout wbs_dat_i[23];
+ inout wbs_dat_i[24];
+ inout wbs_dat_i[25];
+ inout wbs_dat_i[26];
+ inout wbs_dat_i[27];
+ inout wbs_dat_i[28];
+ inout wbs_dat_i[29];
+ inout wbs_dat_i[2];
+ inout wbs_dat_i[30];
+ inout wbs_dat_i[31];
+ inout wbs_dat_i[3];
+ inout wbs_dat_i[4];
+ inout wbs_dat_i[5];
+ inout wbs_dat_i[6];
+ inout wbs_dat_i[7];
+ inout wbs_dat_i[8];
+ inout wbs_dat_i[9];
+ inout wbs_dat_o[0];
+ inout wbs_dat_o[10];
+ inout wbs_dat_o[11];
+ inout wbs_dat_o[12];
+ inout wbs_dat_o[13];
+ inout wbs_dat_o[14];
+ inout wbs_dat_o[15];
+ inout wbs_dat_o[16];
+ inout wbs_dat_o[17];
+ inout wbs_dat_o[18];
+ inout wbs_dat_o[19];
+ inout wbs_dat_o[1];
+ inout wbs_dat_o[20];
+ inout wbs_dat_o[21];
+ inout wbs_dat_o[22];
+ inout wbs_dat_o[23];
+ inout wbs_dat_o[24];
+ inout wbs_dat_o[25];
+ inout wbs_dat_o[26];
+ inout wbs_dat_o[27];
+ inout wbs_dat_o[28];
+ inout wbs_dat_o[29];
+ inout wbs_dat_o[2];
+ inout wbs_dat_o[30];
+ inout wbs_dat_o[31];
+ inout wbs_dat_o[3];
+ inout wbs_dat_o[4];
+ inout wbs_dat_o[5];
+ inout wbs_dat_o[6];
+ inout wbs_dat_o[7];
+ inout wbs_dat_o[8];
+ inout wbs_dat_o[9];
+ inout wbs_sel_i[0];
+ inout wbs_sel_i[1];
+ inout wbs_sel_i[2];
+ inout wbs_sel_i[3];
+ inout wbs_stb_i;
+ inout wbs_we_i;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // USER_ANALOG_PROJECT_WRAPPER
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
+`define SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
+
+/**
+ * sky130_hilas_FGHugeVaractorCapacitor01: one large varactor cap
+ *
+ * Verilog wrapper for sky130_hilas_FGHugeVaractorCapacitor01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGHugeVaractorCapacitor01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGHugeVaractorCapacitor01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TRANS2MED
+`define SKY130_HILAS_TRANS2MED
+
+/**
+ * sky130_hilas_Trans2med: None
+ *
+ * Verilog wrapper for sky130_hilas_Trans2med.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Trans2med (
+ GATE1N,
+ GATE2P,
+ GATE1P,
+ GATE2N,
+ SOURCE1P,
+ SOURCE2P,
+ SOURCE2N,
+ SOURCE1N,
+ DRAIN1N,
+ DRAIN2N,
+ DRAIN1P,
+ DRAIN2P,
+ WELL,
+ VGND,
+ VNB,
+ VPB
+);
+ inout GATE1N;
+ inout GATE2P;
+ inout GATE1P;
+ inout GATE2N;
+ inout SOURCE1P;
+ inout SOURCE2P;
+ inout SOURCE2N;
+ inout SOURCE1N;
+ inout DRAIN1N;
+ inout DRAIN2N;
+ inout DRAIN1P;
+ inout DRAIN2P;
+ inout WELL;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Trans2med (
+ GATE1N,
+ GATE2P,
+ GATE1P,
+ GATE2N,
+ SOURCE1P,
+ SOURCE2P,
+ SOURCE2N,
+ SOURCE1N,
+ DRAIN1N,
+ DRAIN2N,
+ DRAIN1P,
+ DRAIN2P,
+ WELL
+);
+ inout GATE1N;
+ inout GATE2P;
+ inout GATE1P;
+ inout GATE2N;
+ inout SOURCE1P;
+ inout SOURCE2P;
+ inout SOURCE2N;
+ inout SOURCE1N;
+ inout DRAIN1N;
+ inout DRAIN2N;
+ inout DRAIN1P;
+ inout DRAIN2P;
+ inout WELL;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TRANS2MED
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFET03A
+`define SKY130_HILAS_NFET03A
+
+/**
+ * sky130_hilas_nFET03a: None
+ *
+ * Verilog wrapper for sky130_hilas_nFET03a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFET03a (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFET03a (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_NFET03A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGVARACTORCAPACITOR
+`define SKY130_HILAS_FGVARACTORCAPACITOR
+
+/**
+ * sky130_hilas_FGVaractorCapacitor: varactor cap for floating-gate charge storage
+ *
+ * Verilog wrapper for sky130_hilas_FGVaractorCapacitor.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_FGVARACTORCAPACITOR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X2CELL
+`define SKY130_HILAS_SWC4X2CELL
+
+/**
+ * sky130_hilas_swc4x2cell: 4x2 array of FG switch cell, Varactor capacitor cell
+ *
+ * Verilog wrapper for sky130_hilas_swc4x2cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x2cell (
+ COL1,
+ COL2,
+ DRAIN1,
+ DRAIN2,
+ DRAIN3,
+ DRAIN4,
+ GATE1,
+ GATE2,
+ GATESELECT1,
+ GATESELECT2,
+ ROW1,
+ ROW2,
+ ROW3,
+ ROW4,
+ VINJ,
+ VTUN,
+ VGND,
+ VNB,
+ VPB
+);
+ inout COL1;
+ inout COL2;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout DRAIN3;
+ inout DRAIN4;
+ inout GATE1;
+ inout GATE2;
+ inout GATESELECT1;
+ inout GATESELECT2;
+ inout ROW1;
+ inout ROW2;
+ inout ROW3;
+ inout ROW4;
+ inout VINJ;
+ inout VTUN;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x2cell (
+ COL1,
+ COL2,
+ DRAIN1,
+ DRAIN2,
+ DRAIN3,
+ DRAIN4,
+ GATE1,
+ GATE2,
+ GATESELECT1,
+ GATESELECT2,
+ ROW1,
+ ROW2,
+ ROW3,
+ ROW4,
+ VINJ,
+ VTUN
+);
+ inout COL1;
+ inout COL2;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout DRAIN3;
+ inout DRAIN4;
+ inout GATE1;
+ inout GATE2;
+ inout GATESELECT1;
+ inout GATESELECT2;
+ inout ROW1;
+ inout ROW2;
+ inout ROW3;
+ inout ROW4;
+ inout VINJ;
+ inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_SWC4X2CELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_ALL
+`define SKY130_HILAS_ALL
+
+/**
+ * sky130_hilas_all: A design which contains all cells (?)
+ *
+ * Verilog wrapper for sky130_hilas_all.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_all (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_all (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_ALL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DOUBLETGATE01
+`define SKY130_HILAS_DOUBLETGATE01
+
+/**
+ * sky130_hilas_DoubleTGate01: 2x1 array of transmission gates
+ *
+ * Verilog wrapper for sky130_hilas_DoubleTGate01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DoubleTGate01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DoubleTGate01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DOUBLETGATE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TUNCAP01
+`define SKY130_HILAS_TUNCAP01
+
+/**
+ * sky130_hilas_TunCap01: None
+ *
+ * Verilog wrapper for sky130_hilas_TunCap01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunCap01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunCap01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TUNCAP01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01A
+`define SKY130_HILAS_PFETDEVICE01A
+
+/**
+ * sky130_hilas_pFETdevice01a: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01a (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01a (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETDEVICE01A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TUNVARACTORCAPCITOR
+`define SKY130_HILAS_TUNVARACTORCAPCITOR
+
+/**
+ * sky130_hilas_TunVaractorCapcitor: Tunneling capacitor using a standard varactor capacitor
+ *
+ * Verilog wrapper for sky130_hilas_TunVaractorCapcitor.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunVaractorCapcitor (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TunVaractorCapcitor (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TUNVARACTORCAPCITOR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DECOUPVINJ01
+`define SKY130_HILAS_DECOUPVINJ01
+
+/**
+ * sky130_hilas_DecoupVinj01:
+ *
+ * Verilog wrapper for sky130_hilas_DecoupVinj01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DecoupVinj01 (
+ VGND,
+ VNB,
+ VPB
+);
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DecoupVinj01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DECOUPVINJ01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TACOREBLOCK2
+`define SKY130_HILAS_TACOREBLOCK2
+
+/**
+ * sky130_hilas_TACoreBlock2: None
+ *
+ * Verilog wrapper for sky130_hilas_TACoreBlock2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock2 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TACoreBlock2 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TACOREBLOCK2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TOPPROTECTION
+`define SKY130_HILAS_TOPPROTECTION
+
+/**
+ * sky130_hilas_TopProtection:
+ *
+ * Verilog wrapper for sky130_hilas_TopProtection.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TopProtection (
+ ANALOG00,
+ ANALOG01,
+ ANALOG02,
+ ANALOG03,
+ ANALOG04,
+ ANALOG05,
+ ANALOG06,
+ ANALOG07,
+ ANALOG08,
+ ANALOG09,
+ ANALOG10,
+ PIN1,
+ PIN2,
+ PIN3,
+ PIN4,
+ PIN5,
+ PIN6,
+ PIN7,
+ PIN8,
+ PIN9,
+ PIN10,
+ VTUN,
+ VNB,
+ VPB
+);
+ inout ANALOG00;
+ inout ANALOG01;
+ inout ANALOG02;
+ inout ANALOG03;
+ inout ANALOG04;
+ inout ANALOG05;
+ inout ANALOG06;
+ inout ANALOG07;
+ inout ANALOG08;
+ inout ANALOG09;
+ inout ANALOG10;
+ inout PIN1;
+ inout PIN2;
+ inout PIN3;
+ inout PIN4;
+ inout PIN5;
+ inout PIN6;
+ inout PIN7;
+ inout PIN8;
+ inout PIN9;
+ inout PIN10;
+ inout VTUN;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TopProtection (
+ ANALOG00,
+ ANALOG01,
+ ANALOG02,
+ ANALOG03,
+ ANALOG04,
+ ANALOG05,
+ ANALOG06,
+ ANALOG07,
+ ANALOG08,
+ ANALOG09,
+ ANALOG10,
+ PIN1,
+ PIN2,
+ PIN3,
+ PIN4,
+ PIN5,
+ PIN6,
+ PIN7,
+ PIN8,
+ PIN9,
+ PIN10,
+ VTUN
+);
+ inout ANALOG00;
+ inout ANALOG01;
+ inout ANALOG02;
+ inout ANALOG03;
+ inout ANALOG04;
+ inout ANALOG05;
+ inout ANALOG06;
+ inout ANALOG07;
+ inout ANALOG08;
+ inout ANALOG09;
+ inout ANALOG10;
+ inout PIN1;
+ inout PIN2;
+ inout PIN3;
+ inout PIN4;
+ inout PIN5;
+ inout PIN6;
+ inout PIN7;
+ inout PIN8;
+ inout PIN9;
+ inout PIN10;
+ inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TOPPROTECTION
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_WTASINGLESTAGE01
+`define SKY130_HILAS_WTASINGLESTAGE01
+
+/**
+ * sky130_hilas_WTAsinglestage01: None
+ *
+ * Verilog wrapper for sky130_hilas_WTAsinglestage01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTAsinglestage01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTAsinglestage01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_WTASINGLESTAGE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETLARGEPART1
+`define SKY130_HILAS_PFETLARGEPART1
+
+/**
+ * sky130_hilas_pFETLargePart1: Part of the W/L=100 pFET transistor
+ *
+ * Verilog wrapper for sky130_hilas_pFETLargePart1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETLargePart1 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETLargePart1 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETLARGEPART1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATESINGLE01
+`define SKY130_HILAS_TGATESINGLE01
+
+/**
+ * sky130_hilas_TgateSingle01: None
+ *
+ * Verilog wrapper for sky130_hilas_TgateSingle01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TGATESINGLE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01C
+`define SKY130_HILAS_PFETDEVICE01C
+
+/**
+ * sky130_hilas_pFETdevice01c: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01c.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01c (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01c (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETDEVICE01C
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_POLYRESISTORGND
+`define SKY130_HILAS_POLYRESISTORGND
+
+/**
+ * sky130_hilas_polyresistorGND: protective current-limiting resistor to ground
+ *
+ * Verilog wrapper for sky130_hilas_polyresistorGND.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_polyresistorGND (
+ INPUT,
+ OUTPUT,
+ VGND,
+ VNB,
+ VPB
+);
+ inout INPUT;
+ inout OUTPUT;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_polyresistorGND (
+ INPUT,
+ OUTPUT
+);
+ inout INPUT;
+ inout OUTPUT;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_POLYRESISTORGND
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_INVERT01
+`define SKY130_HILAS_INVERT01
+
+/**
+ * sky130_hilas_invert01: None
+ *
+ * Verilog wrapper for sky130_hilas_invert01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_invert01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_invert01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_INVERT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATEDOUBLE01
+`define SKY130_HILAS_TGATEDOUBLE01
+
+/**
+ * sky130_hilas_TgateDouble01: None
+ *
+ * Verilog wrapper for sky130_hilas_TgateDouble01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateDouble01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateDouble01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TGATEDOUBLE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X2CELLOVERLAP
+`define SKY130_HILAS_SWC4X2CELLOVERLAP
+
+/**
+ * sky130_hilas_swc4x2cellOverlap: Core switch cell, built with overlap capacitor
+ *
+ * Verilog wrapper for sky130_hilas_swc4x2cellOverlap.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x2cellOverlap (
+ VERT1,
+ HORIZ1,
+ DRAIN1,
+ HORIZ2,
+ DRAIN2,
+ DRAIN3,
+ HORIZ3,
+ HORIZ4,
+ DRAIN4,
+ VINJ,
+ GATESELECT1,
+ VERT2,
+ GATESELECT2,
+ GATE2,
+ GATE1,
+ VTUN,
+ VNB,
+ VPB
+);
+ inout VERT1;
+ inout HORIZ1;
+ inout DRAIN1;
+ inout HORIZ2;
+ inout DRAIN2;
+ inout DRAIN3;
+ inout HORIZ3;
+ inout HORIZ4;
+ inout DRAIN4;
+ inout VINJ;
+ inout GATESELECT1;
+ inout VERT2;
+ inout GATESELECT2;
+ inout GATE2;
+ inout GATE1;
+ inout VTUN;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x2cellOverlap (
+ VERT1,
+ HORIZ1,
+ DRAIN1,
+ HORIZ2,
+ DRAIN2,
+ DRAIN3,
+ HORIZ3,
+ HORIZ4,
+ DRAIN4,
+ VINJ,
+ GATESELECT1,
+ VERT2,
+ GATESELECT2,
+ GATE2,
+ GATE1,
+ VTUN
+);
+ inout VERT1;
+ inout HORIZ1;
+ inout DRAIN1;
+ inout HORIZ2;
+ inout DRAIN2;
+ inout DRAIN3;
+ inout HORIZ3;
+ inout HORIZ4;
+ inout DRAIN4;
+ inout VINJ;
+ inout GATESELECT1;
+ inout VERT2;
+ inout GATESELECT2;
+ inout GATE2;
+ inout GATE1;
+ inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_SWC4X2CELLOVERLAP
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_OVERLAPCAP02
+`define SKY130_HILAS_OVERLAPCAP02
+
+/**
+ * sky130_hilas_overlapCap02: overlap capacitor based capacitor)
+ *
+ * Verilog wrapper for sky130_hilas_overlapCap02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap02 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap02 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_OVERLAPCAP02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01A
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01A
+
+/**
+ * sky130_hilas_DAC6TransistorStack01a: None
+ *
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01a (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01a (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DAC6TRANSISTORSTACK01A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGBIAS2X1CELL
+`define SKY130_HILAS_FGBIAS2X1CELL
+
+/**
+ * sky130_hilas_FGBias2x1cell: None
+ *
+ * Verilog wrapper for sky130_hilas_FGBias2x1cell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGBias2x1cell (
+ DRAIN1,
+ DRAIN4,
+ GATECOL,
+ GATE_CONTROL,
+ OUTPUT1,
+ OUTPUT2,
+ VINJ,
+ VTUN,
+ VGND,
+ VNB,
+ VPB
+);
+ inout DRAIN1;
+ inout DRAIN4;
+ inout GATECOL;
+ inout GATE_CONTROL;
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout VINJ;
+ inout VTUN;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGBias2x1cell (
+ DRAIN1,
+ DRAIN4,
+ GATECOL,
+ GATE_CONTROL,
+ OUTPUT1,
+ OUTPUT2,
+ VINJ,
+ VTUN
+);
+ inout DRAIN1;
+ inout DRAIN4;
+ inout GATECOL;
+ inout GATE_CONTROL;
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout VINJ;
+ inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_FGBIAS2X1CELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_OVERLAPCAP02A
+`define SKY130_HILAS_OVERLAPCAP02A
+
+/**
+ * sky130_hilas_overlapCap02a: overlap capacitor based capacitor
+ *
+ * Verilog wrapper for sky130_hilas_overlapCap02a.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap02a (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap02a (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_OVERLAPCAP02A
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGVARACTORCAPACITOR02
+`define SKY130_HILAS_FGVARACTORCAPACITOR02
+
+/**
+ * sky130_hilas_FGVaractorCapacitor02: variant 2, varactor cap for floating-gate charge storage
+ *
+ * Verilog wrapper for sky130_hilas_FGVaractorCapacitor02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor02 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorCapacitor02 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_FGVARACTORCAPACITOR02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DRAINSELECT01
+`define SKY130_HILAS_DRAINSELECT01
+
+/**
+ * sky130_hilas_drainSelect01: multiplexor for drain selection for 4 drain lines, pitch matched
+ *
+ * Verilog wrapper for sky130_hilas_drainSelect01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_drainSelect01 (
+ DRAIN4,
+ DRAIN3,
+ DRAIN2,
+ DRAIN1,
+ VINJ,
+ DRAIN_MUX,
+ SELECT4,
+ SELECT3,
+ SELECT2,
+ SELECT1,
+ VGND,
+ VNB,
+ VPB
+);
+ inout DRAIN4;
+ inout DRAIN3;
+ inout DRAIN2;
+ inout DRAIN1;
+ inout VINJ;
+ inout DRAIN_MUX;
+ inout SELECT4;
+ inout SELECT3;
+ inout SELECT2;
+ inout SELECT1;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_drainSelect01 (
+ DRAIN4,
+ DRAIN3,
+ DRAIN2,
+ DRAIN1,
+ VINJ,
+ DRAIN_MUX,
+ SELECT4,
+ SELECT3,
+ SELECT2,
+ SELECT1
+);
+ inout DRAIN4;
+ inout DRAIN3;
+ inout DRAIN2;
+ inout DRAIN1;
+ inout VINJ;
+ inout DRAIN_MUX;
+ inout SELECT4;
+ inout SELECT3;
+ inout SELECT2;
+ inout SELECT1;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DRAINSELECT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_HORIZTRANSCELL01
+`define SKY130_HILAS_HORIZTRANSCELL01
+
+/**
+ * sky130_hilas_horizTransCell01: None
+ *
+ * Verilog wrapper for sky130_hilas_horizTransCell01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizTransCell01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizTransCell01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_HORIZTRANSCELL01
+
+
+//--------EOF---------
+
+`ifndef M12M3
+`define M12M3
+
+/**
+ * m12m3:
+ *
+ * Verilog wrapper for m12m3.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module m12m3 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module m12m3 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // M12M3
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC5BIT01
+`define SKY130_HILAS_DAC5BIT01
+
+/**
+ * sky130_hilas_DAC5bit01: 5-bit digital-to-analog converter (under 6.05um at the moment; thinking through expansion to 6bit and 7bit, and they would use this cell
+ *
+ * Verilog wrapper for sky130_hilas_DAC5bit01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC5bit01 (
+ A0,
+ A1,
+ A2,
+ A3,
+ A4,
+ OUT,
+ VPWR,
+ VNB,
+ VPB
+);
+ inout A0;
+ inout A1;
+ inout A2;
+ inout A3;
+ inout A4;
+ inout OUT;
+ inout VPWR;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC5bit01 (
+ A0,
+ A1,
+ A2,
+ A3,
+ A4,
+ OUT
+);
+ inout A0;
+ inout A1;
+ inout A2;
+ inout A3;
+ inout A4;
+ inout OUT;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DAC5BIT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC6BIT01
+`define SKY130_HILAS_DAC6BIT01
+
+/**
+ * sky130_hilas_DAC6bit01: None
+ *
+ * Verilog wrapper for sky130_hilas_DAC6bit01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6bit01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6bit01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DAC6BIT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01D
+`define SKY130_HILAS_PFETDEVICE01D
+
+/**
+ * sky130_hilas_pFETdevice01d: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01d.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01d (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01d (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETDEVICE01D
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETLARGEPART1
+`define SKY130_HILAS_NFETLARGEPART1
+
+/**
+ * sky130_hilas_nFETLargePart1: None
+ *
+ * Verilog wrapper for sky130_hilas_nFETLargePart1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETLargePart1 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETLargePart1 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_NFETLARGEPART1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_POLY2LI
+`define SKY130_HILAS_POLY2LI
+
+/**
+ * sky130_hilas_poly2li: polysilicon layer to li contact
+ *
+ * Verilog wrapper for sky130_hilas_poly2li.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2li (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_poly2li (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_POLY2LI
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_HORIZPCELL01
+`define SKY130_HILAS_HORIZPCELL01
+
+/**
+ * sky130_hilas_horizPcell01: None
+ *
+ * Verilog wrapper for sky130_hilas_horizPcell01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizPcell01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_horizPcell01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_HORIZPCELL01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DECOUP_CAP_00
+`define SKY130_HILAS_DECOUP_CAP_00
+
+/**
+ * sky130_hilas_decoup_cap_00: decoupling cap (intended as fill)
+ *
+ * Verilog wrapper for sky130_hilas_decoup_cap_00.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_decoup_cap_00 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_decoup_cap_00 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DECOUP_CAP_00
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_FGVARACTORTUNNELCAP01
+`define SKY130_HILAS_FGVARACTORTUNNELCAP01
+
+/**
+ * sky130_hilas_FGVaractorTunnelCap01: Tunneling cpacitor using a standard varactor capacitor
+ *
+ * Verilog wrapper for sky130_hilas_FGVaractorTunnelCap01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorTunnelCap01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_FGVaractorTunnelCap01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_FGVARACTORTUNNELCAP01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPACITORSIZE04
+`define SKY130_HILAS_CAPACITORSIZE04
+
+/**
+ * sky130_hilas_capacitorSize04: large cap
+ *
+ * Verilog wrapper for sky130_hilas_capacitorSize04.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize04 (
+ CAP1TERM02,
+ CAP2TERM02,
+ CAP2TERM01,
+ CAP1TERM01,
+ VNB,
+ VPB
+);
+ inout CAP1TERM02;
+ inout CAP2TERM02;
+ inout CAP2TERM01;
+ inout CAP1TERM01;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize04 (
+ CAP1TERM02,
+ CAP2TERM02,
+ CAP2TERM01,
+ CAP1TERM01
+);
+ inout CAP1TERM02;
+ inout CAP2TERM02;
+ inout CAP2TERM01;
+ inout CAP1TERM01;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_CAPACITORSIZE04
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_LI2M1
+`define SKY130_HILAS_LI2M1
+
+/**
+ * sky130_hilas_li2m1: local interconnect to m1 contact
+ *
+ * Verilog wrapper for sky130_hilas_li2m1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_li2m1 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_li2m1 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_LI2M1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_RIGHTPROTECTION
+`define SKY130_HILAS_RIGHTPROTECTION
+
+/**
+ * sky130_hilas_RightProtection:
+ *
+ * Verilog wrapper for sky130_hilas_RightProtection.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_RightProtection (
+ IO7,
+ IO8,
+ IO9,
+ IO10,
+ IO11,
+ IO13,
+ IO12,
+ PIN1,
+ PIN2,
+ PIN3,
+ PIN4,
+ PIN5,
+ PIN6,
+ PIN7,
+ VNB,
+ VPB
+);
+ inout IO7;
+ inout IO8;
+ inout IO9;
+ inout IO10;
+ inout IO11;
+ inout IO13;
+ inout IO12;
+ inout PIN1;
+ inout PIN2;
+ inout PIN3;
+ inout PIN4;
+ inout PIN5;
+ inout PIN6;
+ inout PIN7;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_RightProtection (
+ IO7,
+ IO8,
+ IO9,
+ IO10,
+ IO11,
+ IO13,
+ IO12,
+ PIN1,
+ PIN2,
+ PIN3,
+ PIN4,
+ PIN5,
+ PIN6,
+ PIN7
+);
+ inout IO7;
+ inout IO8;
+ inout IO9;
+ inout IO10;
+ inout IO11;
+ inout IO13;
+ inout IO12;
+ inout PIN1;
+ inout PIN2;
+ inout PIN3;
+ inout PIN4;
+ inout PIN5;
+ inout PIN6;
+ inout PIN7;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_RIGHTPROTECTION
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPACITORARRAY01
+`define SKY130_HILAS_CAPACITORARRAY01
+
+/**
+ * sky130_hilas_capacitorArray01: selectable capacitor array
+ *
+ * Verilog wrapper for sky130_hilas_capacitorArray01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorArray01 (
+ CAPTERM2,
+ CAPTERM1,
+ VINJ,
+ GATESELECT,
+ VTUN,
+ GATE,
+ DRAIN2,
+ DRAIN1,
+ DRAIN4,
+ DRAIN3,
+ VGND,
+ VNB,
+ VPB
+);
+ inout CAPTERM2;
+ inout CAPTERM1;
+ inout VINJ;
+ inout GATESELECT;
+ inout VTUN;
+ inout GATE;
+ inout DRAIN2;
+ inout DRAIN1;
+ inout DRAIN4;
+ inout DRAIN3;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorArray01 (
+ CAPTERM2,
+ CAPTERM1,
+ VINJ,
+ GATESELECT,
+ VTUN,
+ GATE,
+ DRAIN2,
+ DRAIN1,
+ DRAIN4,
+ DRAIN3
+);
+ inout CAPTERM2;
+ inout CAPTERM1;
+ inout VINJ;
+ inout GATESELECT;
+ inout VTUN;
+ inout GATE;
+ inout DRAIN2;
+ inout DRAIN1;
+ inout DRAIN4;
+ inout DRAIN3;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_CAPACITORARRAY01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_M12M2
+`define SKY130_HILAS_M12M2
+
+/**
+ * sky130_hilas_m12m2: m1 to m2 contact
+ *
+ * Verilog wrapper for sky130_hilas_m12m2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_m12m2 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_m12m2 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_M12M2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETMED
+`define SKY130_HILAS_PFETMED
+
+/**
+ * sky130_hilas_pFETmed: Medium-sized (W/L=10) pFET transistor
+ *
+ * Verilog wrapper for sky130_hilas_pFETmed.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmed (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmed (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETMED
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP2
+`define SKY130_HILAS_SWC4X1CELLOVERLAP2
+
+/**
+ * sky130_hilas_swc4x1cellOverlap2: 4x1 analog mux with overlap
+ *
+ * Verilog wrapper for sky130_hilas_swc4x1cellOverlap2.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1cellOverlap2 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1cellOverlap2 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_SWC4X1CELLOVERLAP2
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC2X2VARACTOR
+`define SKY130_HILAS_SWC2X2VARACTOR
+
+/**
+ * sky130_hilas_swc2x2varactor: ?? Is this part of the library?
+ *
+ * Verilog wrapper for sky130_hilas_swc2x2varactor.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc2x2varactor (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc2x2varactor (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_SWC2X2VARACTOR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_OVERLAPCAP01
+`define SKY130_HILAS_OVERLAPCAP01
+
+/**
+ * sky130_hilas_overlapCap01: overlap capacitor based capacitor
+ *
+ * Verilog wrapper for sky130_hilas_overlapCap01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_overlapCap01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_OVERLAPCAP01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01
+`define SKY130_HILAS_DAC6TRANSISTORSTACK01
+
+/**
+ * sky130_hilas_DAC6TransistorStack01: None
+ *
+ * Verilog wrapper for sky130_hilas_DAC6TransistorStack01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DAC6TransistorStack01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DAC6TRANSISTORSTACK01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PTRANSISTORPAIR
+`define SKY130_HILAS_PTRANSISTORPAIR
+
+/**
+ * sky130_hilas_pTransistorPair: None
+ *
+ * Verilog wrapper for sky130_hilas_pTransistorPair.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pTransistorPair (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pTransistorPair (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PTRANSISTORPAIR
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DECOUP_CAP_01
+`define SKY130_HILAS_DECOUP_CAP_01
+
+/**
+ * sky130_hilas_decoup_cap_01: decoupling cap (intended as fill), variant
+ *
+ * Verilog wrapper for sky130_hilas_decoup_cap_01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_decoup_cap_01 (
+ VPWR,
+ VNB,
+ VPB
+);
+ inout VPWR;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_decoup_cap_01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DECOUP_CAP_01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TA2SIGNALBIASCELL
+`define SKY130_HILAS_TA2SIGNALBIASCELL
+
+/**
+ * sky130_hilas_TA2SignalBiasCell: None
+ *
+ * Verilog wrapper for sky130_hilas_TA2SignalBiasCell.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2SignalBiasCell (
+ VOUT_AMP2,
+ VOUT_AMP1,
+ VIN22,
+ VIN21,
+ VIN11,
+ VIN12,
+ VBIAS2,
+ VBIAS1,
+ VGND,
+ VPWR,
+ VNB,
+ VPB
+);
+ inout VOUT_AMP2;
+ inout VOUT_AMP1;
+ inout VIN22;
+ inout VIN21;
+ inout VIN11;
+ inout VIN12;
+ inout VBIAS2;
+ inout VBIAS1;
+ inout VGND;
+ inout VPWR;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2SignalBiasCell (
+ VOUT_AMP2,
+ VOUT_AMP1,
+ VIN22,
+ VIN21,
+ VIN11,
+ VIN12,
+ VBIAS2,
+ VBIAS1
+);
+ inout VOUT_AMP2;
+ inout VOUT_AMP1;
+ inout VIN22;
+ inout VIN21;
+ inout VIN11;
+ inout VIN12;
+ inout VBIAS2;
+ inout VBIAS1;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TA2SIGNALBIASCELL
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATESINGLE01PART1
+`define SKY130_HILAS_TGATESINGLE01PART1
+
+/**
+ * sky130_hilas_TgateSingle01Part1: None
+ *
+ * Verilog wrapper for sky130_hilas_TgateSingle01Part1.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01Part1 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TgateSingle01Part1 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TGATESINGLE01PART1
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TGATE4SINGLE01
+`define SKY130_HILAS_TGATE4SINGLE01
+
+/**
+ * sky130_hilas_Tgate4Single01: 4 single-throw transmission gates
+ *
+ * Verilog wrapper for sky130_hilas_Tgate4Single01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Tgate4Single01 (
+ INPUT1_4,
+ SELECT4,
+ SELECT3,
+ INPUT1_3,
+ INPUT1_2,
+ SELECT2,
+ SELECT1,
+ INPUT1_1,
+ OUTPUT1,
+ OUTPUT2,
+ OUTPUT3,
+ OUTPUT4,
+ VPWR,
+ VGND,
+ VNB,
+ VPB
+);
+ inout INPUT1_4;
+ inout SELECT4;
+ inout SELECT3;
+ inout INPUT1_3;
+ inout INPUT1_2;
+ inout SELECT2;
+ inout SELECT1;
+ inout INPUT1_1;
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout OUTPUT3;
+ inout OUTPUT4;
+ inout VPWR;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_Tgate4Single01 (
+ INPUT1_4,
+ SELECT4,
+ SELECT3,
+ INPUT1_3,
+ INPUT1_2,
+ SELECT2,
+ SELECT1,
+ INPUT1_1,
+ OUTPUT1,
+ OUTPUT2,
+ OUTPUT3,
+ OUTPUT4
+);
+ inout INPUT1_4;
+ inout SELECT4;
+ inout SELECT3;
+ inout INPUT1_3;
+ inout INPUT1_2;
+ inout SELECT2;
+ inout SELECT1;
+ inout INPUT1_1;
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout OUTPUT3;
+ inout OUTPUT4;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TGATE4SINGLE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_WTA4STAGE01
+`define SKY130_HILAS_WTA4STAGE01
+
+/**
+ * sky130_hilas_WTA4stage01: single-element of WTA circuit
+ *
+ * Verilog wrapper for sky130_hilas_WTA4stage01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTA4stage01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTA4stage01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_WTA4STAGE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_DUALTACORE01
+`define SKY130_HILAS_DUALTACORE01
+
+/**
+ * sky130_hilas_DualTACore01: None
+ *
+ * Verilog wrapper for sky130_hilas_DualTACore01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DualTACore01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_DualTACore01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_DUALTACORE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_VINJDECODE2TO4
+`define SKY130_HILAS_VINJDECODE2TO4
+
+/**
+ * sky130_hilas_VinjDecode2to4: a 2-to-4 decoder capable of handling VINJ voltage
+ *
+ * Verilog wrapper for sky130_hilas_VinjDecode2to4.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjDecode2to4 (
+ OUTPUT00,
+ OUTPUT01,
+ OUTPUT10,
+ OUTPUT11,
+ VINJ,
+ IN2,
+ IN1,
+ ENABLE,
+ VGND,
+ VNB,
+ VPB
+);
+ inout OUTPUT00;
+ inout OUTPUT01;
+ inout OUTPUT10;
+ inout OUTPUT11;
+ inout VINJ;
+ inout IN2;
+ inout IN1;
+ inout ENABLE;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_VinjDecode2to4 (
+ OUTPUT00,
+ OUTPUT01,
+ OUTPUT10,
+ OUTPUT11,
+ VINJ,
+ IN2,
+ IN1,
+ ENABLE
+);
+ inout OUTPUT00;
+ inout OUTPUT01;
+ inout OUTPUT10;
+ inout OUTPUT11;
+ inout VINJ;
+ inout IN2;
+ inout IN1;
+ inout ENABLE;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_VINJDECODE2TO4
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_MCAP2M4
+`define SKY130_HILAS_MCAP2M4
+
+/**
+ * sky130_hilas_mcap2m4: metal capacitor layer contact to m4
+ *
+ * Verilog wrapper for sky130_hilas_mcap2m4.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_mcap2m4 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_mcap2m4 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_MCAP2M4
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_TA2CELL_1FG
+`define SKY130_HILAS_TA2CELL_1FG
+
+/**
+ * sky130_hilas_TA2Cell_1FG: Two transimpedance amps with one (of two) amplifiers using floating-gate
+ inputs. FG amplifier with wide linear range.
+ *
+ * Verilog wrapper for sky130_hilas_TA2Cell_1FG.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_1FG (
+ VIN12,
+ VIN11,
+ VIN21,
+ VIN22,
+ VINJ,
+ OUTPUT1,
+ OUTPUT2,
+ DRAIN1,
+ DRAIN2,
+ COLSEL2,
+ GATE2,
+ GATE1,
+ COLSEL1,
+ VTUN,
+ VPWR,
+ VGND,
+ VNB,
+ VPB
+);
+ inout VIN12;
+ inout VIN11;
+ inout VIN21;
+ inout VIN22;
+ inout VINJ;
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout COLSEL2;
+ inout GATE2;
+ inout GATE1;
+ inout COLSEL1;
+ inout VTUN;
+ inout VPWR;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_TA2Cell_1FG (
+ VIN12,
+ VIN11,
+ VIN21,
+ VIN22,
+ VINJ,
+ OUTPUT1,
+ OUTPUT2,
+ DRAIN1,
+ DRAIN2,
+ COLSEL2,
+ GATE2,
+ GATE1,
+ COLSEL1,
+ VTUN
+);
+ inout VIN12;
+ inout VIN11;
+ inout VIN21;
+ inout VIN22;
+ inout VINJ;
+ inout OUTPUT1;
+ inout OUTPUT2;
+ inout DRAIN1;
+ inout DRAIN2;
+ inout COLSEL2;
+ inout GATE2;
+ inout GATE1;
+ inout COLSEL1;
+ inout VTUN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_TA2CELL_1FG
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP
+`define SKY130_HILAS_SWC4X1CELLOVERLAP
+
+/**
+ * sky130_hilas_swc4x1cellOverlap: 4x1 array of FG switch cell using overlap capacitors
+ *
+ * Verilog wrapper for sky130_hilas_swc4x1cellOverlap.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1cellOverlap (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_swc4x1cellOverlap (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_SWC4X1CELLOVERLAP
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETDEVICE01BA
+`define SKY130_HILAS_PFETDEVICE01BA
+
+/**
+ * sky130_hilas_pFETdevice01ba: pFET transistor used in DAC block
+ *
+ * Verilog wrapper for sky130_hilas_pFETdevice01ba.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01ba (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETdevice01ba (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETDEVICE01BA
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETMED
+`define SKY130_HILAS_NFETMED
+
+/**
+ * sky130_hilas_nFETmed: None
+ *
+ * Verilog wrapper for sky130_hilas_nFETmed.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmed (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETmed (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_NFETMED
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PTRANSISTORVERT01
+`define SKY130_HILAS_PTRANSISTORVERT01
+
+/**
+ * sky130_hilas_pTransistorVert01: None
+ *
+ * Verilog wrapper for sky130_hilas_pTransistorVert01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pTransistorVert01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pTransistorVert01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PTRANSISTORVERT01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_WELLCONTACT
+`define SKY130_HILAS_WELLCONTACT
+
+/**
+ * sky130_hilas_wellContact: contact to a well block, typically used for contacting tunneling junctions in a well.
+ *
+ * Verilog wrapper for sky130_hilas_wellContact.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_wellContact (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_wellContact (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_WELLCONTACT
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPACITORSIZE02
+`define SKY130_HILAS_CAPACITORSIZE02
+
+/**
+ * sky130_hilas_capacitorSize02: mid-small cap
+ *
+ * Verilog wrapper for sky130_hilas_capacitorSize02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize02 (
+ CAPTERM02,
+ CAPTERM01,
+ VNB,
+ VPB
+);
+ inout CAPTERM02;
+ inout CAPTERM01;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_capacitorSize02 (
+ CAPTERM02,
+ CAPTERM01
+);
+ inout CAPTERM02;
+ inout CAPTERM01;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_CAPACITORSIZE02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_PFETMIRROR02
+`define SKY130_HILAS_PFETMIRROR02
+
+/**
+ * sky130_hilas_pFETmirror02: second pFET current mirror
+ *
+ * Verilog wrapper for sky130_hilas_pFETmirror02.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmirror02 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_pFETmirror02 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_PFETMIRROR02
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_WTABLOCKSAMPLE01
+`define SKY130_HILAS_WTABLOCKSAMPLE01
+
+/**
+ * sky130_hilas_WTAblockSample01: None
+ *
+ * Verilog wrapper for sky130_hilas_WTAblockSample01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTAblockSample01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_WTAblockSample01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_WTABLOCKSAMPLE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPMODULE01
+`define SKY130_HILAS_CAPMODULE01
+
+/**
+ * sky130_hilas_CapModule01: None
+ *
+ * Verilog wrapper for sky130_hilas_CapModule01.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule01 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule01 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_CAPMODULE01
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_CAPMODULE03
+`define SKY130_HILAS_CAPMODULE03
+
+/**
+ * sky130_hilas_CapModule03: None
+ *
+ * Verilog wrapper for sky130_hilas_CapModule03.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule03 (
+ VNB,
+ VPB
+);
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_CapModule03 (
+
+);
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_CAPMODULE03
+
+
+//--------EOF---------
+
+`ifndef SKY130_HILAS_NFETLARGE
+`define SKY130_HILAS_NFETLARGE
+
+/**
+ * sky130_hilas_nFETLarge: Single Large (W//L=100) nFET Transistor
+ *
+ * Verilog wrapper for sky130_hilas_nFETLarge.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETLarge (
+ GATE,
+ SOURCE,
+ DRAIN,
+ VGND,
+ VNB,
+ VPB
+);
+ inout GATE;
+ inout SOURCE;
+ inout DRAIN;
+ inout VGND;
+ inout VNB;
+ inout VPB;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_hilas_nFETLarge (
+ GATE,
+ SOURCE,
+ DRAIN
+);
+ inout GATE;
+ inout SOURCE;
+ inout DRAIN;
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif // SKY130_HILAS_NFETLARGE
+
+
+//--------EOF---------
\ No newline at end of file
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
deleted file mode 100644
index 94412da..0000000
--- a/verilog/rtl/user_analog_proj_example.v
+++ /dev/null
@@ -1,221 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`include "example_por.v"
-
-/*
- * I/O mapping for analog
- *
- * mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
- * mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
- * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
- * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
- * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
- * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
- * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
- * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
- * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
- * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
- * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
- * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
- * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
- * mprj_io[24] --- --- user_analog[10]
- * mprj_io[23] --- --- user_analog[9]
- * mprj_io[22] --- --- user_analog[8]
- * mprj_io[21] --- --- user_analog[7]
- * mprj_io[20] --- --- user_analog[6] clamp[2]
- * mprj_io[19] --- --- user_analog[5] clamp[1]
- * mprj_io[18] --- --- user_analog[4] clamp[0]
- * mprj_io[17] --- --- user_analog[3]
- * mprj_io[16] --- --- user_analog[2]
- * mprj_io[15] --- --- user_analog[1]
- * mprj_io[14] --- --- user_analog[0]
- * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
- * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
- * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
- * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
- * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
- * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
- * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
- * mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
- * mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
- * mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
- * mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
- * mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
- * mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
- * mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
- *
- */
-
-/*
- *----------------------------------------------------------------
- *
- * user_analog_proj_example
- *
- * This is an example of a (trivially simple) analog user project,
- * showing how the user project can connect to the I/O pads, both
- * the digital pads, the analog connection on the digital pads,
- * and the dedicated analog pins used as an additional power supply
- * input, with a connected ESD clamp.
- *
- * See the testbench in directory "mprj_por" for the example
- * program that drives this user project.
- *
- *----------------------------------------------------------------
- */
-
-module user_analog_proj_example (
-`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
-`endif
-
- // Wishbone Slave ports (WB MI A)
- input wb_clk_i,
- input wb_rst_i,
- input wbs_stb_i,
- input wbs_cyc_i,
- input wbs_we_i,
- input [3:0] wbs_sel_i,
- input [31:0] wbs_dat_i,
- input [31:0] wbs_adr_i,
- output wbs_ack_o,
- output [31:0] wbs_dat_o,
-
- // Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oenb,
-
- // IOs
- input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
- input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
- output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
-
- // GPIO-analog
- inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
- inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
-
- // Dedicated analog
- inout [`ANALOG_PADS-1:0] io_analog,
- inout [2:0] io_clamp_high,
- inout [2:0] io_clamp_low,
-
- // Clock
- input user_clock2,
-
- // IRQ
- output [2:0] irq
-);
- wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
- wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
- wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
- wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
- wire [`ANALOG_PADS-1:0] io_analog;
-
- // wire [31:0] rdata;
- // wire [31:0] wdata;
-
- // wire valid;
- // wire [3:0] wstrb;
-
- wire isupply; // Independent 3.3V supply
- wire io16, io15, io12, io11;
-
- // WB MI A
- // assign valid = wbs_cyc_i && wbs_stb_i;
- // assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- // assign wbs_dat_o = rdata;
- // assign wdata = wbs_dat_i;
-
- // IO --- unused (no need to connect to anything)
- // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0;
- // assign io_out[14:13] = 11'b0;
- // assign io_out[10:0] = 11'b0;
-
- // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1;
- // assign io_oeb[14:13] = 11'b1;
- // assign io_oeb[10:0] = 11'b1;
-
- // IO --- enable outputs on 11, 12, 15, and 16
- assign io_out[12:11] = {io12, io11};
- assign io_oeb[12:11] = {vssd1, vssd1};
-
- assign io_out[16:15] = {io16, io15};
- assign io_oeb[16:15] = {vssd1, vssd1};
-
- // IRQ
- assign irq = 3'b000; // Unused
-
- // LA --- unused (no need to connect to anything)
- // assign la_data_out = {128{1'b0}}; // Unused
-
- // Instantiate the POR. Connect the digital power to user area 1
- // VCCD, and connect the analog power to user area 1 VDDA.
-
- // Monitor the 3.3V output with mprj_io[10] = gpio_analog[3]
- // Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12]
-
- example_por por1 (
- `ifdef USE_POWER_PINS
- .vdd3v3(vdda1),
- .vdd1v8(vccd1),
- .vss(vssa1),
- `endif
- .porb_h(gpio_analog[3]), // 3.3V domain output
- .porb_l(io11), // 1.8V domain output
- .por_l(io12) // 1.8V domain output
- );
-
- // Instantiate 2nd POR with the analog power supply on one of the
- // analog pins. NOTE: io_analog[4] = mproj_io[18] and is the same
- // pad with io_clamp_high/low[0].
-
- `ifdef USE_POWER_PINS
- assign isupply = io_analog[4];
- assign io_clamp_high[0] = isupply;
- assign io_clamp_low[0] = vssa1;
-
- // Tie off remaining clamps
- assign io_clamp_high[2:1] = vssa1;
- assign io_clamp_low[2:1] = vssa1;
- `endif
-
- // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7]
- // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16]
-
- example_por por2 (
- `ifdef USE_POWER_PINS
- .vdd3v3(isupply),
- .vdd1v8(vccd1),
- .vss(vssa1),
- `endif
- .porb_h(gpio_analog[7]), // 3.3V domain output
- .porb_l(io15), // 1.8V domain output
- .por_l(io16) // 1.8V domain output
- );
-
-endmodule
-
-`default_nettype wire
