commit fa268ca3be806bc4759b41a08d53b4df3c93ff5b
author hamzashabbir517 <shabbirhamza517@gmail.com> Wed Jun 09 23:05:55 2021 +0500
committer hamzashabbir517 <shabbirhamza517@gmail.com> Wed Jun 09 23:05:55 2021 +0500
tree c209d2888b83e132148de6c05ae85b34919537d6
parent 75eef9a28fc49681fad6ab41d52f8c22f43a7f60

Added Project Files

verilog/rtl/BrqRV_EB1/design/eb1_lsu_dccm_mem.sv

diff --git a/verilog/rtl/BrqRV_EB1/design/eb1_lsu_dccm_mem.sv b/verilog/rtl/BrqRV_EB1/design/eb1_lsu_dccm_mem.sv
index 9613df1..ac4765b 100644
--- a/verilog/rtl/BrqRV_EB1/design/eb1_lsu_dccm_mem.sv
+++ b/verilog/rtl/BrqRV_EB1/design/eb1_lsu_dccm_mem.sv
@@ -312,7 +312,7 @@
 									.csb0(~dccm_clken[i]),
 									.web0(~wren_bank[i]),
 									.wmask0(4'hf),
-									.addr0(addr_bank[i][7:0]),
+									.addr0(addr_bank[i]),
 									.din0(wr_data_bank[i][31:0]),
 									.dout0(dccm_bank_dout[i][31:0]),
     									.clk1(clk),

verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_dccm_mem.sv

diff --git a/verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_dccm_mem.sv b/verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_dccm_mem.sv
index 9613df1..ac4765b 100644
--- a/verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_dccm_mem.sv
+++ b/verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_dccm_mem.sv
@@ -312,7 +312,7 @@
 									.csb0(~dccm_clken[i]),
 									.web0(~wren_bank[i]),
 									.wmask0(4'hf),
-									.addr0(addr_bank[i][7:0]),
+									.addr0(addr_bank[i]),
 									.din0(wr_data_bank[i][31:0]),
 									.dout0(dccm_bank_dout[i][31:0]),
     									.clk1(clk),