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foss-eda-tools / third_party / shuttle / sky130 / mpw-002 / slot-036 / 1f58e13282a9f04d5e9fc351eaabb86264d17b5b
commit1f58e13282a9f04d5e9fc351eaabb86264d17b5b[log] [tgz]
authorhamzashabbir517 <shabbirhamza517@gmail.com>Thu Jun 17 17:02:25 2021 +0500
committerhamzashabbir517 <shabbirhamza517@gmail.com>Thu Jun 17 17:02:25 2021 +0500
treec669287c09e9e6d54765057a2d946e8e31d62ee3
parent5b1bade630b83a6eb0970a53ebc2466bc9289f38 [diff]
Update
4 files changed
tree: c669287c09e9e6d54765057a2d946e8e31d62ee3
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. caravel
  13. .gitignore
  14. .gitmodules
  15. info.yaml
  16. LICENSE
  17. Makefile
  18. README.md
README.md

BrqRV EB1 RISC-V Core 1.0 from MERL

This repository contains the brqrv eb1 Core design RTL. Brqrv Eb1 Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I), Compressed Instruction (C), Multiplication And Division (M), And Instruction-Fetch Fence, And Csr Extensions. The Core Contains A 4-Stage, Scalar, In-Order Pipeline

Block Diagram

Directory Structure

├── verlog                          #   User verilog Directory
│   ├── rtl                         #   RTL
│   ├── dv                          #   Design Verification
│   ├── gl                          #   Gate Level Netlis

The BrqRV_EB1 Source Code is avaialable here

├── verlog                               #   User verilog Directory
│   ├── rtl                              #   RTL
|       ├── Brqrv_EB1                    #   BrqRV_EB1 folder
|           ├── Brqrv_EB1.v                                     #   BrqRV_EB1 source file
|           ├── sky130_sram_1kbyte_1rw1r_32x256_8.v             #   1KB sram

The Design Verification Testbench is available here

├── verlog                               #   User verilog Directory
│   ├── dv                               #   Design Verification
│       ├── BrqRV_EB1                    #   Design Test Directory
│       ├── hex                          #   Hex files folder
│       ├── asm                          #   Assmebly files folder

The synthesized netlist is present here:

├── verlog                               #   User verilog Directory
│   ├── gl                               #   Gate Level Netlis
│       ├── BrqRV_EB1                    #   User Design Netlist

The hardened macros are placed here:

├── def                                 #    def Directory
│   ├── BrqRV_EB1                       #    User Design def

├── lef                                 #    lef Directory
│   ├── BrqRV_EB1                       #    User Design lef

├── gds                                 #    gds Directory
│   ├── BrqRV_EB1                       #    User Design gds

Testing of Design

Go to verilog/dv/BrqRV_EB1/ directory

  1. Set the GCC_PATH environment variable.
  2. Set the PDK_PATH environment variable.
  3. Copy the given program hex file into uart.hex.
  4. run the make commad for RTL simulation
  5. run the SIM=GL make command for netlist simulation

Note: Dont forget to add 0x00000FFF instruction in the end of the uart.hex to stop the uart transmission if you are using your own codes.