Update

verilog/dv/BrqRV_EB1/Makefile

diff --git a/verilog/dv/BrqRV_EB1/Makefile b/verilog/dv/BrqRV_EB1/Makefile
index a4f5684..1cfd1c1 100644
--- a/verilog/dv/BrqRV_EB1/Makefile
+++ b/verilog/dv/BrqRV_EB1/Makefile
@@ -25,7 +25,7 @@
 ## User Project Pointers
 UPRJ_VERILOG_PATH ?= ../../../verilog
 UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_RTL_PATH_BRQ = $(UPRJ_VERILOG_PATH)/rtl/BrqRV_EB1/design/openlane/
+UPRJ_RTL_PATH_BRQ = $(UPRJ_VERILOG_PATH)/rtl/BrqRV_EB1/
 UPRJ_BEHAVIOURAL_MODELS = ../
 
 ## RISCV GCC