| commit | dd0565d9c8e85bbd1929c447bf20e1fed0d129be | [log] [tgz] |
|---|---|---|
| author | hamzashabbir517 <shabbirhamza517@gmail.com> | Sat Jul 03 08:21:45 2021 +0500 |
| committer | hamzashabbir517 <shabbirhamza517@gmail.com> | Sat Jul 03 08:21:45 2021 +0500 |
| tree | f552d2f7fe0c5e1ccc53fe414591fad3566a8991 | |
| parent | a9754e2469e5a11c479a2588cb60f7818ce2e3b6 [diff] |
Update
diff --git a/verilog/dv/BrqRV_EB1/Makefile b/verilog/dv/BrqRV_EB1/Makefile index a4f5684..1cfd1c1 100644 --- a/verilog/dv/BrqRV_EB1/Makefile +++ b/verilog/dv/BrqRV_EB1/Makefile
@@ -25,7 +25,7 @@ ## User Project Pointers UPRJ_VERILOG_PATH ?= ../../../verilog UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_RTL_PATH_BRQ = $(UPRJ_VERILOG_PATH)/rtl/BrqRV_EB1/design/openlane/ +UPRJ_RTL_PATH_BRQ = $(UPRJ_VERILOG_PATH)/rtl/BrqRV_EB1/ UPRJ_BEHAVIOURAL_MODELS = ../ ## RISCV GCC