Added Project Files
diff --git a/verilog/rtl/BrqRV_EB1/design/eb1_ifu_iccm_mem.sv b/verilog/rtl/BrqRV_EB1/design/eb1_ifu_iccm_mem.sv
index e91f6c5..8b1bdf4 100644
--- a/verilog/rtl/BrqRV_EB1/design/eb1_ifu_iccm_mem.sv
+++ b/verilog/rtl/BrqRV_EB1/design/eb1_ifu_iccm_mem.sv
@@ -234,7 +234,7 @@
.csb0(~iccm_clken[i]),
.web0(~wren_bank[i]),
.wmask0(4'hf),
- .addr0(addr_bank[i][7:0]),
+ .addr0(addr_bank[i]),
.din0(iccm_bank_wr_data[i][31:0]),
.dout0(iccm_bank_dout[i][31:0]),
.clk1(clk),
diff --git a/verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_iccm_mem.sv b/verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_iccm_mem.sv
index e91f6c5..8b1bdf4 100644
--- a/verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_iccm_mem.sv
+++ b/verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_iccm_mem.sv
@@ -234,7 +234,7 @@
.csb0(~iccm_clken[i]),
.web0(~wren_bank[i]),
.wmask0(4'hf),
- .addr0(addr_bank[i][7:0]),
+ .addr0(addr_bank[i]),
.din0(iccm_bank_wr_data[i][31:0]),
.dout0(iccm_bank_dout[i][31:0]),
.clk1(clk),
