Update
diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
index e31e678..b6def5d 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -63,7 +63,7 @@
initial begin
wait(mprj_ready == 1'b1)
// Observe Output pins [35:8] for factorial
- wait(mprj_io_0 == 28'h0000001);
+ /*wait(mprj_io_0 == 28'h0000001);
wait(mprj_io_0 == 28'h0000002);
wait(mprj_io_0 == 28'h0000006);
wait(mprj_io_0 == 28'h0000018);
@@ -73,7 +73,7 @@
wait(mprj_io_0 == 28'h0009D80);
wait(mprj_io_0 == 28'h0058980);
wait(mprj_io_0 == 28'h0375F00);
-
+ */
// Observe Output pins [35:8] for prime_num
/*wait(mprj_io_0 == 28'd1);
wait(mprj_io_0 == 28'd3);
@@ -94,7 +94,7 @@
//wait(mprj_io_0 == 28'd5);
// Observe Output pins [35:8] for power
- //wait(mprj_io_0 == 28'd64);
+ wait(mprj_io_0 == 28'd64);
// Observe Output pins [35:8] for flip number
//wait(mprj_io_0 == 28'd4889874);
diff --git a/verilog/dv/hex/uart.hex b/verilog/dv/hex/uart.hex
index 6a24372..e8e3012 100755
--- a/verilog/dv/hex/uart.hex
+++ b/verilog/dv/hex/uart.hex
@@ -1,9 +1,8 @@
@00000000
-B0 20 10 73 B8 20 10 73 90 73 40 91 04 37 7F 90
-01 B7 F0 04 46 85 D0 58 00 A0 04 93 00 00 03 13
-00 10 05 93 00 10 06 13 02 B3 00 01 20 23 00 60
-03 05 00 54 9A E3 04 11 04 37 FE 64 A8 29 F0 04
-04 11 C0 0C 00 B1 A0 23 8D 63 01 91 06 85 00 96
-00 10 05 93 00 10 06 13 02 C5 85 B3 FE D6 02 E3
-BF DD 06 05 D0 58 01 B7 0F F0 02 93 00 51 80 23
-FE 00 0A E3 00 01 00 01 00 00 0F FF
+B0 20 10 73 B8 20 10 73 5F 55 50 B7 55 50 80 93
+7C 00 90 73 90 73 40 91 00 01 7F 90 F0 04 04 37
+D0 58 09 B7 00 23 42 91 42 8D 00 54 00 54 02 23
+00 04 02 83 00 04 03 03 00 44 03 83 03 33 13 FD
+13 FD 02 53 00 03 84 63 FE 03 9B E3 00 69 80 23
+D0 58 01 B7 0F F0 02 93 00 51 80 23 FE 00 0A E3
+00 01 00 01 00 00 0F FF
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index d84ad9e..5e51a46 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,8 +25,8 @@
`include "gl/user_proj_example.v"
`else
`include "user_project_wrapper.v"
- `include "power.v"
- //`include "user_proj_example.v"
- //`include "BrqRV_EB1/BrqRV_EB1.v"
+ //`include "power.v"
+ `include "user_proj_example.v"
+ `include "BrqRV_EB1/BrqRV_EB1.v"
`include "BrqRV_EB1/sky130_sram_1kbyte_1rw1r_32x256_8.v"
`endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 7eb8d1b..520348a 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -127,7 +127,7 @@
.user_clock2(user_clock2),
// IRQ
- .irq(user_irq)
+ .user_irq(user_irq)
);
endmodule // user_project_wrapper
