Update
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3483216..a08394e 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -22,9 +22,7 @@
// Assume default net type to be wire because GL netlists don't have the wire definitions
`default_nettype wire
`include "gl/user_project_wrapper.v"
- //`include "gl/user_proj_example.v"
- `include "powered_netlist.v"
- `include "BrqRV_EB1/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+ `include "gl/user_proj_example.v"
`else
`include "user_project_wrapper.v"
`include "powered_netlist.v"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 2e0e44b..7eb8d1b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -119,6 +119,12 @@
.io_in (io_in),
.io_out(io_out),
.io_oeb(io_oeb),
+
+ // analog
+ .analog_io(analog_io),
+
+ // Independent clock
+ .user_clock2(user_clock2),
// IRQ
.irq(user_irq)
