commit	56ffa54239154b42edeb151452c3e880b72359f2	[log] [tgz]
author	hamzashabbir517 <shabbirhamza517@gmail.com>	Sun Jun 13 09:09:45 2021 +0500
committer	hamzashabbir517 <shabbirhamza517@gmail.com>	Sun Jun 13 09:09:45 2021 +0500
tree	bb8dcc3364ee4e8fd32000b7195a646e34ab1fed
parent	53b59767457e742e7c4b6440654c42b6a99a3944 [diff]

Update

verilog/rtl/BrqRV_EB1/configs/brqrv.config[Deleted - diff]
verilog/rtl/BrqRV_EB1/configs/brqrv_config_gen.py[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/BrqRV_EB1.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/Defines/common_defines.vh[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/Defines/eb1_param.vh[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/Defines/eb1_pdef.vh[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/Defines/pd_defines.vh[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/ahb_to_axi4.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/axi4_to_ahb.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/beh_lib.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/common_defines.vh[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dbg/eb1_dbg.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dec/cdecode[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dec/csrdecode[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dec/decode[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dec/eb1_dec.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dec/eb1_dec_decode_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dec/eb1_dec_gpr_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dec/eb1_dec_ib_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dec/eb1_dec_tlu_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dec/eb1_dec_trigger.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dmi/dmi_jtag_to_core_sync.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dmi/dmi_wrapper.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dmi/rvjtag_tap.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dmi_jtag_to_core_sync.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/dmi_wrapper.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_brqrv.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_brqrv_wrapper.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_dbg.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_dec.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_dec_decode_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_dec_gpr_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_dec_ib_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_dec_tlu_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_dec_trigger.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_def.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_dma_ctrl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_exu.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_exu_alu_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_exu_div_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_exu_mul_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_ifu.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_ifu_aln_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_ifu_bp_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_ifu_compress_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_ifu_ic_mem.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_ifu_iccm_mem.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_ifu_ifc_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_ifu_mem_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lib.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lsu.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lsu_addrcheck.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lsu_bus_buffer.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lsu_bus_intf.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lsu_clkdomain.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lsu_dccm_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lsu_dccm_mem.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lsu_ecc.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lsu_lsc_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lsu_stbuf.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_lsu_trigger.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_mem.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_param.vh[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_pdef.vh[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/eb1_pic_ctrl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/exu/eb1_exu.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/exu/eb1_exu_alu_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/exu/eb1_exu_div_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/exu/eb1_exu_mul_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/flist.formal[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/flist.questa[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/iccm_controller.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_aln_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_bp_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_compress_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_ic_mem.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_iccm_mem.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_ifc_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/ifu/eb1_ifu_mem_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/include/eb1_def.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lib/ahb_to_axi4.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lib/axi4_to_ahb.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lib/beh_lib.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lib/eb1_lib.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lib/mem_lib.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_addrcheck.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_bus_buffer.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_bus_intf.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_clkdomain.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_dccm_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_dccm_mem.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_ecc.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_lsc_ctl.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_stbuf.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/lsu/eb1_lsu_trigger.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/openlane/BrqRV_EB1.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/openlane/BrqRV_EB1.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/openlane/sky130_sram_1kbyte_1rw1r_32x256_8.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/pd_defines.vh[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/rvjtag_tap.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/sky130_sram_1kbyte_1rw1r_32x256_8.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/soc_files/iccm_controller.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/soc_files/tb_prog.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/soc_files/uart_rx_prog.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/design/uart_rx_prog.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/SimJTAG.cc[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/SimJTAG.v[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/ahb_sif.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/cmark.c[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/cmark.ld[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/cmark.mki[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/cmark_dccm.ld[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/cmark_dccm.mki[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/cmark_iccm.ld[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/cmark_iccm.mki[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/crt0.s[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/custom.s[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/factorial.s[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/hello_world.ld[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/hello_world.s[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/hello_world_dccm.ld[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/hello_world_dccm.s[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/hello_world_iccm.ld[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/hello_world_iccm.s[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/asm/printf.c[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/axi_lsu_dma_bridge.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/dasm.svi[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/flist[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/hex/cmark.hex[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/hex/cmark_dccm.hex[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/hex/cmark_iccm.hex[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/hex/data.hex[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/hex/hello_world.hex[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/hex/hello_world_dccm.hex[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/hex/hello_world_iccm.hex[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/hex/program.hex[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/input.tcl[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/link.ld[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/remote_bitbang.cc[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/remote_bitbang.h[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/tb_top.sv[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/test_tb_top.cpp[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/tests/Coremark/Makefile[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/tests/Coremark/cmark.c[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/tests/Coremark/printf.c[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/tests/dhry/README[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/tests/dhry/crt0.s[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/tests/dhry/dhry.h[Deleted - diff]
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verilog/rtl/BrqRV_EB1/testbench/tests/dhry/dhry_1.c[Deleted - diff]
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verilog/rtl/BrqRV_EB1/testbench/tests/dhry/printf.c[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/tests/hello_world/Makefile[Deleted - diff]
verilog/rtl/BrqRV_EB1/testbench/tests/hello_world/hello_world.s[Deleted - diff]
verilog/rtl/BrqRV_EB1/tools/JSON.pm[Deleted - diff]
verilog/rtl/BrqRV_EB1/tools/Makefile[Deleted - diff]
verilog/rtl/BrqRV_EB1/tools/addassign[Deleted - diff]
verilog/rtl/BrqRV_EB1/tools/coredecode[Deleted - diff]
verilog/rtl/BrqRV_EB1/tools/picmap[Deleted - diff]
verilog/rtl/BrqRV_EB1/tools/smalldiv[Deleted - diff]
verilog/rtl/BrqRV_EB1/tools/unrollforverilator[Deleted - diff]
verilog/rtl/BrqRV_EB1/tools/vivado.tcl[Deleted - diff]
verilog/rtl/uprj_netlists.v[diff]

165 files changed

tree: bb8dcc3364ee4e8fd32000b7195a646e34ab1fed

README.md

BrqRV EB1 RISC-V Core 1.0 from MERL

This repository contains the brqrv eb1 Core design RTL. Brqrv Eb1 Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I), Compressed Instruction (C), Multiplication And Division (M), And Instruction-Fetch Fence, And Csr Extensions. The Core Contains A 4-Stage, Scalar, In-Order Pipeline

Block Diagram

Directory Structure

├── verlog                          #   User verilog Directory
│   ├── rtl                         #   RTL
│   ├── dv                          #   Design Verification
│   ├── gl                          #   Gate Level Netlis

The BrqRV_EB1 Source Code is avaialable here

├── verlog                               #   User verilog Directory
│   ├── rtl                              #   RTL
|       ├── Brqrv_EB1                    #   BrqRV_EB1 folder
|           ├── Brqrv_EB1.v                                     #   BrqRV_EB1 source file
|           ├── sky130_sram_1kbyte_1rw1r_32x256_8.v             #   1KB sram

The Design Verification Testbench is available here

├── verlog                               #   User verilog Directory
│   ├── dv                               #   Design Verification
│       ├── BrqRV_EB1                    #   Design Test Directory
│       ├── hex                          #   Hex files folder
│       ├── asm                          #   Assmebly files folder

The synthesized netlist is present here:

├── verlog                               #   User verilog Directory
│   ├── gl                               #   Gate Level Netlis
│       ├── BrqRV_EB1                    #   User Design Netlist

The hardened macros are placed here:

├── def                                 #    def Directory
│   ├── BrqRV_EB1                       #    User Design def

├── lef                                 #    lef Directory
│   ├── BrqRV_EB1                       #    User Design lef

├── gds                                 #    gds Directory
│   ├── BrqRV_EB1                       #    User Design gds

Testing of Design

Go to verilog/dv/BrqRV_EB1/ directory

Set the GCC_PATH environment variable.
Set the PDK_PATH environment variable.
Copy the given program hex file into uart.hex.
run the make commad for RTL simulation
run the SIM=GL make command for netlist simulation

Note: Dont forget to add 0x00000FFF instruction in the end of the uart.hex to stop the uart transmission if you are using your own codes.