Update
diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
index 7d7d8d9..26c66ad 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -75,17 +75,20 @@
wait(mprj_io_0 == 28'h0375F00);
*/
// Observe Output pins [35:8] for prime_num
- wait(mprj_io_0 == 28'd1);
+ /*wait(mprj_io_0 == 28'd1);
wait(mprj_io_0 == 28'd3);
wait(mprj_io_0 == 28'd5);
wait(mprj_io_0 == 28'd7);
wait(mprj_io_0 == 28'd11);
- wait(mprj_io_0 == 28'd13);
- //wait(mprj_io_0 == 28'h00013B0);
- //wait(mprj_io_0 == 28'h0009D80);
- //wait(mprj_io_0 == 28'h0058980);
- //wait(mprj_io_0 == 28'h0375F00);
- $display("MPRJ-IO state = %h ", mprj_io[35:8]);
+ wait(mprj_io_0 == 28'd13);*/
+ // Observe Output pins [35:8] for multliplication_table
+ wait(mprj_io_0 == 28'd5);
+ wait(mprj_io_0 == 28'd10);
+ wait(mprj_io_0 == 28'd15);
+ wait(mprj_io_0 == 28'd20);
+ wait(mprj_io_0 == 28'd25);
+ wait(mprj_io_0 == 28'd30);
+ $display("MPRJ-IO state = %d ", mprj_io[35:8]);
`ifdef GL
$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
@@ -121,7 +124,7 @@
end
always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %h ", mprj_io[35:8]);
+ #1 $display("MPRJ-IO state = %d ", mprj_io[35:8]);
end
wire flash_csb;
diff --git a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.sv b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.sv
index 321d707..ba95911 100644
--- a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.sv
+++ b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.sv
@@ -1213,8 +1213,8 @@
TIMER_LEGAL_EN : 5'h01
})
(
- input logic vccd1,
- input logic vssd1,
+ input logic VPWR,
+ input logic VGND,
input logic clk,
input logic rst_l,
input logic dbg_rst_l,
@@ -1234,7 +1234,7 @@
output logic [31:0] trace_rv_i_tval_ip,
// Bus signals
-`ifdef RV_BUILD_AXI4
+
//-------------------------- LSU AXI signals--------------------------
// AXI Write Channels
output logic lsu_axi_awvalid,
@@ -1415,7 +1415,7 @@
output logic [63:0] dma_axi_rdata,
output logic [1:0] dma_axi_rresp,
output logic dma_axi_rlast,
-`endif
+
`ifdef RV_BUILD_AHB_LITE
//// AHB LITE BUS
@@ -3966,8 +3966,8 @@
})
(
- input logic vccd1,
- input logic vssd1,
+ input logic VPWR,
+ input logic VGND,
input logic clk,
input logic rst_l,
input logic dccm_clk_override,
@@ -18901,7 +18901,7 @@
// Performance debug info
//
//
-`ifdef DUMP_BTB_ON
+/*`ifdef DUMP_BTB_ON
logic exu_mp_valid; // conditional branch mispredict
logic exu_mp_way; // conditional branch mispredict
logic exu_mp_ataken; // direction is actual taken
@@ -18969,6 +18969,7 @@
endfunction
`endif
+*/
endmodule // eb1_ifu
//********************************************************************************
@@ -21650,10 +21651,10 @@
SB_BUS_TAG : 8'h01 ,
TIMER_LEGAL_EN : 5'h01
})(
- `ifdef USE_POWER_PINS
- input logic vccd1,
- input logic vssd1,
- `endif
+
+ input logic VPWR,
+ input logic VGND,
+
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low
@@ -21811,10 +21812,8 @@
);*/
sky130_sram_1kbyte_1rw1r_32x256_8 sram(
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
+ .vccd1(VPWR),
+ .vssd1(VGND),
.clk0(clk),
.csb0(~iccm_clken[i]),
.web0(~wren_bank[i]),
@@ -21874,10 +21873,10 @@
);*/
sky130_sram_1kbyte_1rw1r_32x256_8 sram(
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
+
+ .vccd1(VPWR),
+ .vssd1(VGND),
+
.clk0(clk),
.csb0(~iccm_clken[i]),
.web0(~wren_bank[i]),
@@ -27937,10 +27936,10 @@
SB_BUS_TAG : 8'h01 ,
TIMER_LEGAL_EN : 5'h01
})(
-`ifdef USE_POWER_PINS
- input logic vccd1,
- input logic vssd1,
- `endif
+
+ input logic VPWR,
+ input logic VGND,
+
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low
@@ -28115,10 +28114,10 @@
);
*/
sky130_sram_1kbyte_1rw1r_32x256_8 sram(
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
+
+ .vccd1(VPWR),
+ .vssd1(VGND),
+
.clk0(clk),
.csb0(~dccm_clken[i]),
.web0(~wren_bank[i]),
@@ -28162,10 +28161,10 @@
.*
);*/
sky130_sram_1kbyte_1rw1r_32x256_8 sram(
- `ifdef USE_POWER_PINS
- .vccd1(vccd1),
- .vssd1(vssd1),
- `endif
+
+ .vccd1(VPWR),
+ .vssd1(VGND),
+
.clk0(clk),
.csb0(~dccm_clken[i]),
.web0(~wren_bank[i]),
@@ -31565,7 +31564,7 @@
logic SE;
assign SE = 0;
- sky130_fd_sc_hd__dlclkp_1 clkhdr( .CLK(clk), .GCLK(l1clk), .GATE(en)); /*clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));*/
+ sky130_fd_sc_hd__dlclkp_1 clkhdr( .VPWR(1'b1), .VGND(1'b0), .CLK(clk), .GCLK(l1clk), .GATE(en)); /*clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));*/
endmodule // rvclkhdr
@@ -31582,7 +31581,7 @@
assign SE = 0;
- sky130_fd_sc_hd__dlclkp_1 clkhdr( .CLK(clk), .GCLK(l1clk), .GATE(en)); //clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
+ sky130_fd_sc_hd__dlclkp_1 clkhdr( .VPWR(1'b1), .VGND(1'b0), .CLK(clk), .GCLK(l1clk), .GATE(en)); //clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
endmodule
diff --git a/verilog/rtl/BrqRV_EB1/LICENSE b/verilog/rtl/BrqRV_EB1/LICENSE
deleted file mode 100644
index 4b24f09..0000000
--- a/verilog/rtl/BrqRV_EB1/LICENSE
+++ /dev/null
@@ -1,69 +0,0 @@
-Apache License
-Version 2.0, January 2004
-http://www.apache.org/licenses/
-
-TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
-
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diff --git a/verilog/rtl/BrqRV_EB1/README.md b/verilog/rtl/BrqRV_EB1/README.md
deleted file mode 100644
index 8b13789..0000000
--- a/verilog/rtl/BrqRV_EB1/README.md
+++ /dev/null
@@ -1 +0,0 @@
-
