Update
diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
index a057aa2..e529863 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -63,7 +63,7 @@
initial begin
wait(mprj_ready == 1'b1)
// Observe Output pins [35:8] for factorial
- wait(mprj_io_0 == 28'h0000001);
+ /*wait(mprj_io_0 == 28'h0000001);
wait(mprj_io_0 == 28'h0000002);
wait(mprj_io_0 == 28'h0000006);
wait(mprj_io_0 == 28'h0000018);
@@ -73,7 +73,7 @@
wait(mprj_io_0 == 28'h0009D80);
wait(mprj_io_0 == 28'h0058980);
wait(mprj_io_0 == 28'h0375F00);
-
+ */
// Observe Output pins [35:8] for prime_num
/*wait(mprj_io_0 == 28'd1);
wait(mprj_io_0 == 28'd3);
@@ -83,13 +83,13 @@
wait(mprj_io_0 == 28'd13);
*/
// Observe Output pins [35:8] for multliplication_table
- /*wait(mprj_io_0 == 28'd5);
+ wait(mprj_io_0 == 28'd5);
wait(mprj_io_0 == 28'd10);
wait(mprj_io_0 == 28'd15);
wait(mprj_io_0 == 28'd20);
wait(mprj_io_0 == 28'd25);
wait(mprj_io_0 == 28'd30);
- */
+
// Observe Output pins [35:8] for mean & Determinant
//wait(mprj_io_0 == 28'd5);
@@ -125,7 +125,7 @@
//wait(mprj_io_0 == 28'd2);
//wait(mprj_io_0 == 28'd1);
//wait(mprj_io_0 == 28'd0);
- $display("MPRJ-IO state = %d ", mprj_io[35:8]);
+ $display("MPRJ-IO state = %d, at time = %0t ", mprj_io[35:8],$time);
`ifdef GL
$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
diff --git a/verilog/dv/hex/uart.hex b/verilog/dv/hex/uart.hex
index 6a24372..5509980 100755
--- a/verilog/dv/hex/uart.hex
+++ b/verilog/dv/hex/uart.hex
@@ -1,9 +1,6 @@
@00000000
-B0 20 10 73 B8 20 10 73 90 73 40 91 04 37 7F 90
-01 B7 F0 04 46 85 D0 58 00 A0 04 93 00 00 03 13
-00 10 05 93 00 10 06 13 02 B3 00 01 20 23 00 60
-03 05 00 54 9A E3 04 11 04 37 FE 64 A8 29 F0 04
-04 11 C0 0C 00 B1 A0 23 8D 63 01 91 06 85 00 96
-00 10 05 93 00 10 06 13 02 C5 85 B3 FE D6 02 E3
-BF DD 06 05 D0 58 01 B7 0F F0 02 93 00 51 80 23
+B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92
+44 99 44 15 03 B7 43 01 0E 37 F0 04 03 05 D0 58
+02 64 02 B3 00 53 A0 23 00 5E 20 23 0E 11 03 91
+FE 93 17 E3 D0 58 01 B7 0F F0 02 93 00 51 80 23
FE 00 0A E3 00 01 00 01 00 00 0F FF
diff --git a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
index ae6dc92..5a071dc 100644
--- a/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
+++ b/verilog/rtl/BrqRV_EB1/BrqRV_EB1.v
@@ -15312,7 +15312,7 @@
);
end
else if (pt[917-:8] == 8) begin : iccm
- sky130_sram_1kbyte_1rw1r_32x256_8 sram(
+ /*sky130_sram_1kbyte_1rw1r_32x256_8 sram(
`ifdef USE_POWER_PINS
.vccd1(VPWR),
.vssd1(VGND),
@@ -15328,7 +15328,21 @@
.csb1(1'b1),
.addr1(8'h00),
.dout1()
- );
+ );*/
+ DFFRAM iccm
+ (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(clk),
+ .WE({4{wren_bank[i]}}),
+ .EN(iccm_clken[i]),
+ .Di(iccm_bank_wr_data[(i * 39) + 31-:32]),
+ .Do(iccm_bank_dout[(i * 39) + 31-:32]),
+ .A(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)])
+ );
+
end
else if (pt[917-:8] == 9) begin : iccm
ram_512x39 iccm_bank(
@@ -20872,7 +20886,7 @@
);
end
else if (DCCM_INDEX_DEPTH == 256) begin : dccm
- sky130_sram_1kbyte_1rw1r_32x256_8 sram(
+ /*sky130_sram_1kbyte_1rw1r_32x256_8 sram(
`ifdef USE_POWER_PINS
.vccd1(VPWR),
.vssd1(VGND),
@@ -20888,7 +20902,20 @@
.csb1(1'b1),
.addr1(8'h00),
.dout1()
- );
+ );*/
+ DFFRAM dccm
+ (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(clk),
+ .WE({4{wren_bank[i]}}),
+ .EN(dccm_clken[i]),
+ .Di(wr_data_bank[(i * pt[1360-:10]) + 31-:32]),
+ .Do(dccm_bank_dout[(i * pt[1360-:10]) + 31-:32]),
+ .A(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)])
+ );
end
else if (DCCM_INDEX_DEPTH == 128) begin : dccm
ram_128x39 dccm_bank(
@@ -22978,11 +23005,13 @@
assign ecc_error = en & (ecc_check[6:0] != 0);
endmodule
module rvclkhdr (
+
en,
clk,
scan_mode,
l1clk
);
+
input wire en;
input wire clk;
input wire scan_mode;
@@ -22990,6 +23019,10 @@
wire SE;
assign SE = 0;
sky130_fd_sc_hd__dlclkp_1 clkhdr(
+ `ifdef USE_POWER_PINS
+ .VPWR(1'b1),
+ .VGND(1'b0),
+ `endif
.CLK(clk),
.GCLK(l1clk),
.GATE(en)
@@ -23001,6 +23034,7 @@
scan_mode,
l1clk
);
+
input wire en;
input wire clk;
input wire scan_mode;
@@ -23008,6 +23042,10 @@
wire SE;
assign SE = 0;
sky130_fd_sc_hd__dlclkp_1 clkhdr(
+ `ifdef USE_POWER_PINS
+ .VPWR(1'b1),
+ .VGND(1'b0),
+ `endif
.CLK(clk),
.GCLK(l1clk),
.GATE(en)
diff --git a/verilog/rtl/BrqRV_EB1/DFFRAM.v b/verilog/rtl/BrqRV_EB1/DFFRAM.v
new file mode 100644
index 0000000..b80677f
--- /dev/null
+++ b/verilog/rtl/BrqRV_EB1/DFFRAM.v
@@ -0,0 +1,176 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`ifndef USE_CUSTOM_DFFRAM
+
+module DFFRAM(
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input CLK,
+ input [3:0] WE,
+ input EN,
+ input [31:0] Di,
+ output reg [31:0] Do,
+ input [7:0] A
+);
+
+
+reg [31:0] mem [0:`MEM_WORDS-1];
+
+always @(posedge CLK) begin
+ if (EN == 1'b1) begin
+ Do <= mem[A];
+ if (WE[0]) mem[A][ 7: 0] <= Di[ 7: 0];
+ if (WE[1]) mem[A][15: 8] <= Di[15: 8];
+ if (WE[2]) mem[A][23:16] <= Di[23:16];
+ if (WE[3]) mem[A][31:24] <= Di[31:24];
+ end
+end
+endmodule
+
+`else
+
+module DFFRAM #( parameter COLS=1)
+(
+`ifdef USE_POWER_PINS
+ VPWR,
+ VGND,
+`endif
+ CLK,
+ WE,
+ EN,
+ Di,
+ Do,
+ A
+);
+
+ input CLK;
+ input [3:0] WE;
+ input EN;
+ input [31:0] Di;
+ output [31:0] Do;
+ input [7+$clog2(COLS):0] A;
+
+`ifdef USE_POWER_PINS
+ input VPWR;
+ input VGND;
+`endif
+
+ wire [31:0] DOUT [COLS-1:0];
+ wire [31:0] Do_pre;
+ wire [COLS-1:0] EN_lines;
+
+ generate
+ genvar i;
+ for (i=0; i<COLS; i=i+1) begin : COLUMN
+ DFFRAM_COL4 RAMCOLS (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK),
+ .WE(WE),
+ .EN(EN_lines[i]),
+ .Di(Di),
+ .Do(DOUT[i]),
+ .A(A[7:0])
+ );
+ end
+ if(COLS==4) begin
+ MUX4x1_32 MUX (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .A0(DOUT[0]),
+ .A1(DOUT[1]),
+ .A2(DOUT[2]),
+ .A3(DOUT[3]),
+ .S(A[9:8]),
+ .X(Do_pre)
+ );
+ DEC2x4 DEC (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(EN),
+ .A(A[9:8]),
+ .SEL(EN_lines)
+ );
+ end
+ else if(COLS==2) begin
+ MUX2x1_32 MUX (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .A0(DOUT[0]),
+ .A1(DOUT[1]),
+ .S(A[8]),
+ .X(Do_pre)
+ );
+ //sky130_fd_sc_hd__inv_4 DEC0 ( .Y(EN_lines[0]), .A(A[8]) );
+ //sky130_fd_sc_hd__clkbuf_4 DEC1 (.X(EN_lines[1]), .A(A[8]) );
+ DEC1x2 DEC (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(EN),
+ .A(A[8]),
+ .SEL(EN_lines[1:0])
+ );
+
+ end
+ else begin
+ PASS MUX (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .A(DOUT[0]),
+ .X(Do_pre)
+ );
+ sky130_fd_sc_hd__clkbuf_4 ENBUF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(EN_lines[0]),
+ .A(EN)
+ );
+ end
+ endgenerate
+
+ sky130_fd_sc_hd__clkbuf_4 DOBUF[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(Do),
+ .A(Do_pre)
+ );
+
+endmodule
+
+`endif
\ No newline at end of file
diff --git a/verilog/rtl/BrqRV_EB1/DFFRAMBB.v b/verilog/rtl/BrqRV_EB1/DFFRAMBB.v
new file mode 100644
index 0000000..22ab55e
--- /dev/null
+++ b/verilog/rtl/BrqRV_EB1/DFFRAMBB.v
@@ -0,0 +1,784 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ Building blocks for DFF based RAM compiler for SKY130A
+ BYTE : 8 memory cells used as a building block for WORD module
+ WORD : 32-bit memory word with select and byte-level WE
+ DEC6x64 : 2x4 Binary Decoder
+ DEC6x64 : 6x64 Binary decoder
+ MUX4x1_32 : 32-bit 4x1 MUX
+ MUX2x1_32 : 32-bit 2x1 MUX
+ SRAM64x32 : Tri-state buffers based 64x32 DFF RAM
+ DFFRAM_COL4 : A single column of 4 SRAM64x32 blocks using 4x1 multiplexors
+*/
+/*
+ Author: Mohamed Shalan (mshalan@aucegypt.edu)
+*/
+
+module BYTE (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input CLK,
+ input WE,
+ input SEL,
+ input [7:0] Di,
+ output [7:0] Do
+);
+
+ wire [7:0] q_wire;
+ wire we_wire;
+ wire SEL_B;
+ wire GCLK;
+
+ sky130_fd_sc_hd__inv_1 INV(
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .Y(SEL_B),
+ .A(SEL)
+ );
+
+ sky130_fd_sc_hd__and2_1 CGAND(
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .A(SEL),
+ .B(WE),
+ .X(we_wire)
+ );
+
+ sky130_fd_sc_hd__dlclkp_1 CG(
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .CLK(CLK),
+ .GCLK(GCLK),
+ .GATE(we_wire)
+ );
+
+ generate
+ genvar i;
+ for(i=0; i<8; i=i+1) begin : BIT
+ sky130_fd_sc_hd__dfxtp_1 FF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .D(Di[i]),
+ .Q(q_wire[i]),
+ .CLK(GCLK)
+ );
+
+ sky130_fd_sc_hd__ebufn_2 OBUF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .A(q_wire[i]),
+ .Z(Do[i]),
+ .TE_B(SEL_B)
+ );
+
+ end
+ endgenerate
+
+endmodule
+
+
+module WORD32 (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input CLK,
+ input [3:0] WE,
+ input SEL,
+ input [31:0] Di,
+ output [31:0] Do
+);
+
+ BYTE B0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK), .WE(WE[0]), .SEL(SEL), .Di(Di[7:0]), .Do(Do[7:0]) );
+
+ BYTE B1 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK), .WE(WE[1]), .SEL(SEL), .Di(Di[15:8]), .Do(Do[15:8]) );
+
+ BYTE B2 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK), .WE(WE[2]), .SEL(SEL), .Di(Di[23:16]), .Do(Do[23:16]) );
+
+ BYTE B3 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK), .WE(WE[3]), .SEL(SEL), .Di(Di[31:24]), .Do(Do[31:24]) );
+
+endmodule
+
+module DEC1x2 (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input EN,
+ input [0:0] A,
+ output [1:0] SEL
+);
+ sky130_fd_sc_hd__and2b_2 AND1 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[0]),
+ .A_N(A),
+ .B(EN)
+ );
+
+ sky130_fd_sc_hd__and2_2 AND3 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[1]),
+ .A(A),
+ .B(A[0])
+ );
+
+endmodule
+
+module DEC2x4 (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input EN,
+ input [1:0] A,
+ output [3:0] SEL
+);
+ sky130_fd_sc_hd__nor3b_4 AND0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .Y(SEL[0]),
+ .A(A[0]),
+ .B(A[1]),
+ .C_N(EN)
+ );
+
+ sky130_fd_sc_hd__and3b_4 AND1 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[1]),
+ .A_N(A[1]),
+ .B(A[0]),
+ .C(EN)
+ );
+
+ sky130_fd_sc_hd__and3b_4 AND2 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[2]),
+ .A_N(A[0]),
+ .B(A[1]),
+ .C(EN)
+ );
+
+ sky130_fd_sc_hd__and3_4 AND3 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[3]),
+ .A(A[1]),
+ .B(A[0]),
+ .C(EN)
+ );
+
+endmodule
+
+module DEC3x8 (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input EN,
+ input [2:0] A,
+ output [7:0] SEL
+);
+ sky130_fd_sc_hd__nor4b_2 AND0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .Y(SEL[0]),
+ .A(A[0]),
+ .B(A[1]),
+ .C(A[2]),
+ .D_N(EN)
+ ); // 000
+
+ sky130_fd_sc_hd__and4bb_2 AND1 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[1]),
+ .A_N(A[2]),
+ .B_N(A[1]),
+ .C(A[0]),
+ .D(EN)
+ ); // 001
+
+ sky130_fd_sc_hd__and4bb_2 AND2 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[2]),
+ .A_N(A[2]),
+ .B_N(A[0]),
+ .C(A[1]),
+ .D(EN)
+ ); // 010
+
+ sky130_fd_sc_hd__and4b_2 AND3 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[3]),
+ .A_N(A[2]),
+ .B(A[1]),
+ .C(A[0]),
+ .D(EN)
+ ); // 011
+
+ sky130_fd_sc_hd__and4bb_2 AND4 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[4]),
+ .A_N(A[0]),
+ .B_N(A[1]),
+ .C(A[2]),
+ .D(EN)
+ ); // 100
+
+ sky130_fd_sc_hd__and4b_2 AND5 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[5]),
+ .A_N(A[1]),
+ .B(A[0]),
+ .C(A[2]),
+ .D(EN)
+ ); // 101
+
+ sky130_fd_sc_hd__and4b_2 AND6 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[6]),
+ .A_N(A[0]),
+ .B(A[1]),
+ .C(A[2]),
+ .D(EN)
+ ); // 110
+
+ sky130_fd_sc_hd__and4_2 AND7 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(SEL[7]),
+ .A(A[0]),
+ .B(A[1]),
+ .C(A[2]),
+ .D(EN)
+ ); // 111
+endmodule
+
+
+module DEC6x64 (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input EN,
+ input [5:0] A,
+ output [63:0] SEL
+);
+ wire [7:0] SEL0_w ;
+ wire [2:0] A_buf;
+
+ DEC3x8 DEC_L0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(EN),
+ .A(A[5:3]),
+ .SEL(SEL0_w)
+ );
+
+ sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(A_buf),
+ .A(A[2:0])
+ );
+
+ generate
+ genvar i;
+ for(i=0; i<8; i=i+1) begin : DEC_L1
+ DEC3x8 U (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(SEL0_w[i]),
+ .A(A_buf),
+ .SEL(SEL[7+8*i: 8*i])
+ );
+ end
+ endgenerate
+endmodule
+
+module MUX2x1_32(
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input [31:0] A0, A1,
+ input [0:0] S,
+ output [31:0] X
+);
+ sky130_fd_sc_hd__mux2_1 MUX[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .A0(A0),
+ .A1(A1),
+ .S(S[0]),
+ .X(X)
+ );
+
+endmodule
+
+module MUX4x1_32(
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input [31:0] A0, A1, A2, A3,
+ input [1:0] S,
+ output [31:0] X
+);
+ sky130_fd_sc_hd__mux4_1 MUX[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .A0(A0),
+ .A1(A1),
+ .A2(A2),
+ .A3(A3),
+ .S0(S[0]),
+ .S1(S[1]),
+ .X(X)
+ );
+endmodule
+
+module PASS (
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input [31:0] A,
+ output [31:0] X
+);
+ assign X = A;
+endmodule
+
+module SRAM64x32(
+`ifdef USE_POWER_PINS
+ input VPWR,
+ input VGND,
+`endif
+ input CLK,
+ input [3:0] WE,
+ input EN,
+ input [31:0] Di,
+ output [31:0] Do,
+ input [5:0] A
+);
+
+ wire [63:0] SEL;
+ wire [31:0] Do_pre;
+ wire [31:0] Di_buf;
+ wire CLK_buf;
+ wire [3:0] WE_buf;
+
+ sky130_fd_sc_hd__clkbuf_16 CLKBUF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(CLK_buf),
+ .A(CLK)
+ );
+
+ sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(WE_buf),
+ .A(WE)
+ );
+
+ sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(Di_buf),
+ .A(Di)
+ );
+
+ DEC6x64 DEC (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(EN),
+ .A(A),
+ .SEL(SEL)
+ );
+
+ generate
+ genvar i;
+ for (i=0; i< 64; i=i+1) begin : WORD
+ WORD32 W (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK_buf),
+ .WE(WE_buf),
+ .SEL(SEL[i]),
+ .Di(Di_buf),
+ .Do(Do_pre)
+ );
+ end
+ endgenerate
+
+ // Ensure that the Do_pre lines are not floating when EN = 0
+ wire lo;
+ wire float_buf_en;
+ sky130_fd_sc_hd__clkbuf_4 FBUFENBUF(
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(float_buf_en),
+ .A(EN)
+ );
+
+ sky130_fd_sc_hd__conb_1 TIE (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .LO(lo),
+ .HI()
+ );
+
+ sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .A( lo ),
+ .Z(Do_pre),
+ .TE_B(float_buf_en)
+ );
+
+ generate
+ //genvar i;
+ for(i=0; i<32; i=i+1) begin : OUT
+ sky130_fd_sc_hd__dfxtp_1 FF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .D(Do_pre[i]),
+ .Q(Do[i]),
+ .CLK(CLK)
+ );
+ end
+ endgenerate
+
+endmodule
+
+module DFFRAM_COL4
+(
+`ifdef USE_POWER_PINS
+ VPWR,
+ VGND,
+`endif
+ CLK,
+ WE,
+ EN,
+ Di,
+ Do,
+ A
+);
+
+ input CLK;
+ input [3:0] WE;
+ input EN;
+ input [31:0] Di;
+ output [31:0] Do;
+ input [7:0] A;
+
+`ifdef USE_POWER_PINS
+ input VPWR;
+ input VGND;
+`endif
+
+ wire [31:0] Di_buf;
+ wire [31:0] Do_pre;
+ wire CLK_buf;
+ wire [3:0] WE_buf;
+ wire [5:3] A_buf;
+
+ wire [31:0] Do_B_0_0;
+ wire [31:0] Do_B_0_1;
+ wire [31:0] Do_B_0_2;
+ wire [31:0] Do_B_0_3;
+
+ wire [3:0] row_sel;
+
+ sky130_fd_sc_hd__clkbuf_8 CLKBUF (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(CLK_buf),
+ .A(CLK)
+ );
+
+ sky130_fd_sc_hd__clkbuf_8 WEBUF[3:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(WE_buf),
+ .A(WE)
+ );
+
+ sky130_fd_sc_hd__clkbuf_8 DIBUF[31:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(Di_buf),
+ .A(Di)
+ );
+
+ sky130_fd_sc_hd__clkbuf_16 ABUF[2:0] (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ .VPB(VPWR),
+ .VNB(VGND),
+ `endif
+ .X(A_buf),
+ .A(A[5:3])
+ );
+
+ DEC2x4 DEC (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .EN(EN),
+ .A(A[7:6]),
+ .SEL(row_sel)
+ );
+
+ SRAM64x32 B_0_0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK_buf),
+ .WE(WE_buf),
+ .EN(row_sel[0]),
+ .Di(Di_buf),
+ .Do(Do_B_0_0),
+ .A({A_buf,A[2:0]})
+ );
+
+ SRAM64x32 B_0_1 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK_buf),
+ .WE(WE_buf),
+ .EN(row_sel[1]),
+ .Di(Di_buf),
+ .Do(Do_B_0_1),
+ .A({A_buf,A[2:0]})
+ );
+
+ SRAM64x32 B_0_2 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK_buf),
+ .WE(WE_buf),
+ .EN(row_sel[2]),
+ .Di(Di_buf),
+ .Do(Do_B_0_2),
+ .A({A_buf,A[2:0]})
+ );
+
+ SRAM64x32 B_0_3 (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .CLK(CLK_buf),
+ .WE(WE_buf),
+ .EN(row_sel[3]),
+ .Di(Di_buf),
+ .Do(Do_B_0_3),
+ .A({A_buf,A[2:0]})
+ );
+
+ MUX4x1_32 MUX (
+ `ifdef USE_POWER_PINS
+ .VPWR(VPWR),
+ .VGND(VGND),
+ `endif
+ .A0(Do_B_0_0),
+ .A1(Do_B_0_1),
+ .A2(Do_B_0_2),
+ .A3(Do_B_0_3),
+ .S(A[7:6]),
+ .X(Do)
+ );
+
+endmodule
+
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index aa790d5..745e8d9 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,6 +25,8 @@
`include "gl/user_proj_example.v"
`else
`include "BrqRV_EB1/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+ //`include "BrqRV_EB1/DFFRAM.v"
+ //`include "BrqRV_EB1/DFFRAMBB.v"
// for netlist verification
//`include "../gl/user_project_wrapper.v"
