Update
diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
index 331c80b..725a32d 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -100,9 +100,30 @@
//wait(mprj_io_0 == 28'd4889874);
// Observe Output pins [35:8] for Queue
- wait(mprj_io_0 == 28'd5);
- wait(mprj_io_0 == 28'd6);
+ //wait(mprj_io_0 == 28'd5);
+ //wait(mprj_io_0 == 28'd6);
+ //wait(mprj_io_0 == 28'd7);
+
+ // Observe Output pins [35:8] for perfect square
+ //wait(mprj_io_0 == 28'd5);
+
+ // Observe Output pins [35:8] for counter / ascending / reverse
+ wait(mprj_io_0 == 28'd15);
+ wait(mprj_io_0 == 28'd14);
+ wait(mprj_io_0 == 28'd13);
+ wait(mprj_io_0 == 28'd12);
+ wait(mprj_io_0 == 28'd11);
+ wait(mprj_io_0 == 28'd10);
+ wait(mprj_io_0 == 28'd9);
+ wait(mprj_io_0 == 28'd8);
wait(mprj_io_0 == 28'd7);
+ wait(mprj_io_0 == 28'd6);
+ wait(mprj_io_0 == 28'd5);
+ wait(mprj_io_0 == 28'd4);
+ wait(mprj_io_0 == 28'd3);
+ wait(mprj_io_0 == 28'd2);
+ wait(mprj_io_0 == 28'd1);
+ wait(mprj_io_0 == 28'd0);
$display("MPRJ-IO state = %d ", mprj_io[35:8]);
`ifdef GL
diff --git a/verilog/dv/asm/ascending_num.s b/verilog/dv/asm/ascending_num.s
new file mode 100644
index 0000000..2d2f268
--- /dev/null
+++ b/verilog/dv/asm/ascending_num.s
@@ -0,0 +1,48 @@
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+//Prime numbers in a given range
+
+// li x1, 0x5f555555
+// csrw 0x7c0, x1
+
+csrw minstret, zero
+csrw minstreth, zero
+
+li x4, 4 // Neccessary for terminating code
+csrw 0x7f9 ,x4 // Neccessary for terminating code
+nop
+
+li s0,0xB // UPPER BOUND
+li t0,0 // COUNTER
+li t1,0xf0040000 // BASE ADRESS
+li t2,STDOUT
+
+LOOP:
+
+sw t0,0(t1)
+sw t0,0(t2)
+addi t2,t2,4
+addi t1,t1,4
+beq t0,s0,END
+addi t0,t0,1
+
+j LOOP
+
+END:
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+ li x3, STDOUT
+ addi x5, x0, 0xff
+ sb x5, 0(x3)
+ beq x0, x0, _finish
+.rept 100
+ nop
+.endr
diff --git a/verilog/dv/asm/counter.s b/verilog/dv/asm/counter.s
new file mode 100644
index 0000000..c20cd62
--- /dev/null
+++ b/verilog/dv/asm/counter.s
@@ -0,0 +1,71 @@
+//Counter_loop (Count/Increment 1 till 10)
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+
+
+ // Code to execute
+.section .text
+.global _start
+_start:
+
+ // Clear minstret
+ csrw minstret, zero
+ csrw minstreth, zero
+ li x1, 0x5f555555
+ csrw 0x7c0, x1
+ li x1, 4
+ csrw 0x7f9, x1
+
+ li x8, 0xf0040000 // dccm address
+ li x3, STDOUT
+ addi x9, x0, 0xA //no of values needs to be count
+ addi x6, x0, 0
+ addi x12, x0, 0 //initial value to start loop
+ addi x11, x0, 0 //increment value from x12 save in x11 register
+ addi x13, x0, 0
+
+
+store:
+ add x5, x0, x6
+ sw x5, 0(x8)
+ addi x6, x6, 1
+ addi x8, x8, 4
+ bne x9, x6, store
+ li x8, 0xf0040000
+ j counter_loop
+
+next:
+ sw x11, 0(x8)
+ addi x8, x8, 4
+ sw x11, 0(x3)
+ addi x3, x3, 4
+ beq x13, x9, _finish
+ addi x13, x13, 1
+ addi x11, x0, 1
+ addi x12, x0, 1
+
+counter_loop:
+
+ addi x11, x12, 1
+ beq x12, x13, next
+ addi x12, x12, 1
+ j counter_loop
+
+
+
+
+
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+ li x3, STDOUT
+ addi x5, x0, 0xff
+ sb x5, 0(x3)
+ beq x0, x0, _finish
+.rept 100
+ nop
+.endr
+
diff --git a/verilog/dv/asm/perfect_square.s b/verilog/dv/asm/perfect_square.s
new file mode 100644
index 0000000..85fe821
--- /dev/null
+++ b/verilog/dv/asm/perfect_square.s
@@ -0,0 +1,43 @@
+// SQ_root of number
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+
+ csrw minstret, zero
+ csrw minstreth, zero
+
+ li x4, 4 // Neccessary for terminating code
+ csrw 0x7f9 ,x4 // Neccessary for terminating code
+
+ li x8, 0xf0040000 // dccm address
+ li x3, STDOUT // axi address
+ li x13, 0 // initial value
+ li x12, 25 // sqrt number
+ addi x6, x0, 0 // counter
+ li x11, 200
+
+
+sq_root:
+ addi x6, x6, 1
+ mul x9, x6, x6
+ beq x11, x6, _finish
+ bne x12, x9, sq_root
+ sw x6, 0(x8)
+ sw x6, 0(x3)
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+ li x3, STDOUT
+ addi x5, x0, 0xff
+ sb x5, 0(x3)
+ beq x0, x0, _finish
+.rept 100
+ nop
+.endr
diff --git a/verilog/dv/asm/reverse_number.s b/verilog/dv/asm/reverse_number.s
new file mode 100644
index 0000000..390e301
--- /dev/null
+++ b/verilog/dv/asm/reverse_number.s
@@ -0,0 +1,50 @@
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+//Prime numbers in a given range
+
+// li x1, 0x5f555555
+// csrw 0x7c0, x1
+
+csrw minstret, zero
+csrw minstreth, zero
+
+li x4, 4 // Neccessary for terminating code
+csrw 0x7f9 ,x4 // Neccessary for terminating code
+nop
+
+li s0,15 // UPPER BOUND
+li t0,0 // COUNTER
+li t1,0xf0040000 // BASE ADRESS
+li t3,1
+addi t0,s0,0
+li t2,STDOUT
+
+LOOP:
+
+sw t0,0(t1)
+sw t0,0(t2)
+addi t2,t2,4
+addi t1,t1,4
+beqz t0,END
+sub t0,t0,t3
+
+j LOOP
+
+END:
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+ li x3, STDOUT
+ addi x5, x0, 0xff
+ sb x5, 0(x3)
+ beq x0, x0, _finish
+.rept 100
+ nop
+.endr
diff --git a/verilog/dv/hex/ascending_num b/verilog/dv/hex/ascending_num
new file mode 100644
index 0000000..d93b3a2
--- /dev/null
+++ b/verilog/dv/hex/ascending_num
@@ -0,0 +1,6 @@
+@00000000
+B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92
+42 81 44 2D F0 04 03 37 D0 58 03 B7 00 53 20 23
+00 53 A0 23 03 11 03 91 00 82 84 63 B7 FD 02 85
+D0 58 01 B7 0F F0 02 93 00 51 80 23 FE 00 0A E3
+00 01 00 01 00 00 0F FF
diff --git a/verilog/dv/hex/counter.hex b/verilog/dv/hex/counter.hex
new file mode 100644
index 0000000..0feda45
--- /dev/null
+++ b/verilog/dv/hex/counter.hex
@@ -0,0 +1,10 @@
+@00000000
+B0 20 10 73 B8 20 10 73 5F 55 50 B7 55 50 80 93
+7C 00 90 73 90 73 40 91 04 37 7F 90 01 B7 F0 04
+04 93 D0 58 03 13 00 A0 06 13 00 00 05 93 00 00
+06 93 00 00 02 B3 00 00 20 23 00 60 03 05 00 54
+9A E3 04 11 04 37 FE 64 A8 29 F0 04 04 11 C0 0C
+00 B1 A0 23 8D 63 01 91 06 85 00 96 00 10 05 93
+00 10 06 13 00 16 05 93 FE D6 02 E3 BF DD 06 05
+D0 58 01 B7 0F F0 02 93 00 51 80 23 FE 00 0A E3
+00 01 00 01 00 00 0F FF
diff --git a/verilog/dv/hex/perfect_square.hex b/verilog/dv/hex/perfect_square.hex
new file mode 100644
index 0000000..fd0b465
--- /dev/null
+++ b/verilog/dv/hex/perfect_square.hex
@@ -0,0 +1,6 @@
+@00000000
+B0 20 10 73 B8 20 10 73 10 73 42 11 04 37 7F 92
+01 B7 F0 04 46 81 D0 58 03 13 46 65 05 93 00 00
+03 05 0C 80 02 63 04 B3 00 65 88 63 FE 96 1B E3
+00 64 20 23 00 61 A0 23 D0 58 01 B7 0F F0 02 93
+00 51 80 23 FE 00 0A E3 00 01 00 01 00 00 0F FF
diff --git a/verilog/dv/hex/reverse_num.hex b/verilog/dv/hex/reverse_num.hex
new file mode 100644
index 0000000..ea36e87
--- /dev/null
+++ b/verilog/dv/hex/reverse_num.hex
@@ -0,0 +1,6 @@
+@00000000
+B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92
+42 81 44 3D F0 04 03 37 02 93 4E 05 03 B7 00 04
+20 23 D0 58 A0 23 00 53 03 91 00 53 85 63 03 11
+82 B3 00 02 B7 F5 41 C2 D0 58 01 B7 0F F0 02 93
+00 51 80 23 FE 00 0A E3 00 01 00 01 00 00 0F FF
diff --git a/verilog/dv/hex/uart.hex b/verilog/dv/hex/uart.hex
index 5a3b56e..729fbe7 100755
--- a/verilog/dv/hex/uart.hex
+++ b/verilog/dv/hex/uart.hex
@@ -1,12 +1,6 @@
@00000000
-B0 20 10 73 B8 20 10 73 10 73 42 11 04 37 7F 92
-04 93 F0 04 09 13 00 50 09 93 00 60 0A 13 00 70
-02 93 00 30 03 13 00 00 03 93 00 10 0E 13 00 20
-00 EF 00 30 A0 0D 00 60 87 63 02 85 87 63 00 62
-88 63 00 72 80 82 01 C2 B7 FD C0 04 01 24 22 23
-24 23 B7 E5 B7 CD 01 34 00 04 22 83 00 44 23 03
-00 84 23 83 D0 58 0B 37 00 5B 20 23 00 01 0B 11
-00 01 00 01 20 23 00 01 0B 11 00 6B 00 01 00 01
-20 23 00 01 00 01 00 7B 00 01 00 01 D0 58 01 B7
-0F F0 02 93 00 51 80 23 FE 00 0A E3 00 01 00 01
-00 00 0F FF
+B0 20 10 73 B8 20 10 73 10 73 42 11 00 01 7F 92
+42 81 44 3D F0 04 03 37 02 93 4E 05 03 B7 00 04
+20 23 D0 58 A0 23 00 53 03 91 00 53 85 63 03 11
+82 B3 00 02 B7 F5 41 C2 D0 58 01 B7 0F F0 02 93
+00 51 80 23 FE 00 0A E3 00 01 00 01 00 00 0F FF
