F-Class bug fix
diff --git a/verilog/rtl/fpu_lib.sv b/verilog/rtl/fpu_lib.sv
index 5953873..9d4ebf8 100644
--- a/verilog/rtl/fpu_lib.sv
+++ b/verilog/rtl/fpu_lib.sv
@@ -31,14 +31,14 @@
assign sig_zero = |sig ? 1'b0 : 1'b1;
assign exp_one = &exp ? 1'b1 : 1'b0;
- assign is_pos_zero = !sign & exp_zero & sig_zero;
- assign is_neg_zero = sign & exp_zero & sig_zero;
- assign is_pos_subnorm = !sign & exp_zero;
- assign is_neg_subnorm = sign & exp_zero;
- assign is_pos_inf = !sign & exp_one & sig_zero;
- assign is_neg_inf = sign & exp_one & sig_zero;
- assign is_qNaN = exp_one & !sig_zero & sig[22];
- assign is_sNaN = exp_one & !sig_zero & !sig[22];
+ assign is_pos_zero = !sign & exp_zero & sig_zero;
+ assign is_neg_zero = sign & exp_zero & sig_zero;
+ assign is_pos_subnorm = !sign & exp_zero & !sig_zero;
+ assign is_neg_subnorm = sign & exp_zero & !sig_zero;
+ assign is_pos_inf = !sign & exp_one & sig_zero;
+ assign is_neg_inf = sign & exp_one & sig_zero;
+ assign is_qNaN = exp_one & !sig_zero & sig[22];
+ assign is_sNaN = exp_one & !sig_zero & !sig[22];
assign is_pos_norm = (is_pos_zero | is_neg_zero | is_pos_subnorm | is_neg_subnorm | is_pos_inf | is_neg_inf |
is_qNaN | is_sNaN) ? 1'b0 : ~sign ? 1'b1 : 1'b0;
