minor changes
diff --git a/verilog/rtl/user_proj_example.sv b/verilog/rtl/user_proj_example.sv
index 0d00ab2..c1b44f3 100644
--- a/verilog/rtl/user_proj_example.sv
+++ b/verilog/rtl/user_proj_example.sv
@@ -89,6 +89,7 @@
wire wb_valid_ns;
wire [31:0] fpu_result;
+ wire [31:0] data;
assign la_write_en = |la_write;
assign addr = la_write_en ? la_addr : rdwraddr;
@@ -99,7 +100,7 @@
.fpu_result (fpu_result ),
.fpu_valids ({valid_out, op_out} ),
.addr (addr ),
- .wren (wb_valid ),
+ .wren (wb_valid | la_write_en ),
.wrdata (data ),
.exceptions (exceptions ),
.rddata (int_rddata ),
