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mpw-002
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slot-035
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bf4c2189f1e4390b7afb8674f740050925497a18
commit
bf4c2189f1e4390b7afb8674f740050925497a18
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log
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author
aghaalizeb-lm <agha.ali@lampromellon.com>
Tue Jun 08 10:19:58 2021 +0500
committer
aghaalizeb-lm <agha.ali@lampromellon.com>
Tue Jun 08 10:19:58 2021 +0500
tree
9112afe11b43763521a22620750554f8b18878d1
parent
801dfcdf7d765cef46532c7c31e44bfd7094243e
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minor changes
verilog/rtl/user_proj_example.sv
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1 file changed
tree: 9112afe11b43763521a22620750554f8b18878d1
.github/
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README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.