commit a79eb3f262c7116ca4b3ffc0e0738ae59a3a6bf6
author aghaalizeb-lm <agha.ali@lampromellon.com> Tue Jun 08 12:54:03 2021 +0500
committer aghaalizeb-lm <agha.ali@lampromellon.com> Tue Jun 08 12:54:03 2021 +0500
tree 519dae319843ff7578482643468f267e4442ee48
parent bf4c2189f1e4390b7afb8674f740050925497a18

la output logic fix

verilog/rtl/user_proj_example.sv

diff --git a/verilog/rtl/user_proj_example.sv b/verilog/rtl/user_proj_example.sv
index c1b44f3..76aba0a 100644
--- a/verilog/rtl/user_proj_example.sv
+++ b/verilog/rtl/user_proj_example.sv
@@ -197,7 +197,7 @@
   
   assign valid_out                = {sqrt_valid_out,div_valid_out,valid_in[8:0]};
 
-  assign wb_valid_ns              =( |valid_out | wb_valid) ? wb_valid : wb_valid_f;
+  assign wb_valid_ns              = (|valid_out | wb_valid | la_write_en) ? (wb_valid | la_write_en) : wb_valid_f;
 
   rvdff #(1) wb_valid_ff (.clk(clk), .rst_l(rst_l), .din(wb_valid_ns), .dout(wb_valid_f));