commit 8d705a64eb6908489518c487983ea6db5a46773a
author aghaalizeb-lm <agha.ali@lampromellon.com> Tue Jun 08 16:08:24 2021 +0500
committer aghaalizeb-lm <agha.ali@lampromellon.com> Tue Jun 08 16:08:24 2021 +0500
tree 0158525555bc60d27da5c1bc719e9384bdbc3368
parent a79eb3f262c7116ca4b3ffc0e0738ae59a3a6bf6

la output logic fix

verilog/rtl/user_proj_example.sv

diff --git a/verilog/rtl/user_proj_example.sv b/verilog/rtl/user_proj_example.sv
index 76aba0a..6da3354 100644
--- a/verilog/rtl/user_proj_example.sv
+++ b/verilog/rtl/user_proj_example.sv
@@ -319,7 +319,7 @@
     assign io_oeb = {(37){~rst}};
 
     // LA
-    assign la_data_out = {{(127-BITS){1'b0}}, rdata};
+    assign la_data_out = {{(127-BITS){1'b0}}, io_out};
     // Assuming LA probes [31:0] are for controlling the input register  
     assign la_write = ~la_oenb[31:0] & ~valid;
     // Assuming LA probes [65:64] are for controlling the count clk & reset