commit: 84d883c6d968b30538eded872dff48f7f0fb1779
[log]
author: komaljaved-lm <komal.javed@lampromellon.com>
Tue May 25 14:41:14 2021 +0500
committer: komaljaved-lm <komal.javed@lampromellon.com>
Tue May 25 14:41:14 2021 +0500
tree: 86961da6e68f655f506e3a055f88d54caebe7114
parent: b1d661a138deee8991f3be5e5a794f0aa6043b91 [diff]

deleted extra files

verilog/rtl/attachments(1)/add_sub.sv[Deleted - diff]
verilog/rtl/attachments(1)/compare.sv[Deleted - diff]
verilog/rtl/attachments(1)/config.tcl[Deleted - diff]
verilog/rtl/attachments(1)/config_1.tcl[Deleted - diff]
verilog/rtl/attachments(1)/defines.v[Deleted - diff]
verilog/rtl/attachments(1)/defs.vi[Deleted - diff]
verilog/rtl/attachments(1)/divider.sv[Deleted - diff]
verilog/rtl/attachments(1)/f_class.sv[Deleted - diff]
verilog/rtl/attachments(1)/float_to_int.sv[Deleted - diff]
verilog/rtl/attachments(1)/fpu.sv[Deleted - diff]
verilog/rtl/attachments(1)/fpu_lib.sv[Deleted - diff]
verilog/rtl/attachments(1)/fused_mul.sv[Deleted - diff]
verilog/rtl/attachments(1)/int_to_float.sv[Deleted - diff]
verilog/rtl/attachments(1)/macro.cfg[Deleted - diff]
verilog/rtl/attachments(1)/min_max.sv[Deleted - diff]
verilog/rtl/attachments(1)/multiplier.sv[Deleted - diff]
verilog/rtl/attachments(1)/registers.sv[Deleted - diff]
verilog/rtl/attachments(1)/sign_inject.sv[Deleted - diff]
verilog/rtl/attachments(1)/sqrt_fpu.sv[Deleted - diff]
verilog/rtl/attachments(1)/uprj_netlists.v[Deleted - diff]
verilog/rtl/attachments(1)/user_project_example.sv[Deleted - diff]
verilog/rtl/attachments(1)/user_project_wrapper.v[Deleted - diff]

22 files changed

tree: 86961da6e68f655f506e3a055f88d54caebe7114

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.