deleted extra files
diff --git "a/verilog/rtl/attachments\0501\051/add_sub.sv" "b/verilog/rtl/attachments\0501\051/add_sub.sv"
deleted file mode 100644
index 1c159f4..0000000
--- "a/verilog/rtl/attachments\0501\051/add_sub.sv"
+++ /dev/null
@@ -1,171 +0,0 @@
-//`include "fpu_lib.sv"
-
-module add_sub(
- input wire [31:0] in_x,
- input wire [31:0] in_y,
- input wire operation,
- input wire [2:0] round_mode,
- output wire [31:0] out_z,
- output wire [4:0] exceptions);
-
- wire sign_x, sign_y;
- wire [7:0] exp_x, exp_y, exp_a, exp_b, subnorm_exp, norm_exp;
- wire [22:0] mant_x, mant_y, mant_a, mant_b;
-
- wire x_is_zero, x_is_inf, x_is_qNaN, x_is_sNaN;
- wire y_is_zero, y_is_inf, y_is_qNaN, y_is_sNaN;
- wire a_is_subnorm, b_is_subnorm;
- wire hd_bit_a, hd_bit_b;
-
- wire [26:0] arg1, arg2;
- wire [26:0] rt_shift_mant;
- wire [26:0] lt_shft_mant, norm_sum;
- wire [26:0] mant_sum;
- wire [23:0] rounded_mant;
- wire [31:0] inter_result, of_result;
-
- wire comp, exp_shft_comp;
- wire operator_y, subtract;
- wire cout, cout_check;
-
- wire [7:0] exp_diff;
- wire [4:0] ld_zero_cnt, inc_dec_exp_amt;
- wire [7:0] inter_shft_amt, shft_amt;
- wire round_of;
-
- wire sign_z;
- wire [7:0] exp_z;
- wire [22:0] mant_z;
-
- wire invalid_operation;
- wire divide_by_zero;
- wire overflow;
- wire underflow;
- wire inexact;
- wire [9:0] x_check_res, y_check_res;
-
- // checking inputs for special values
- special_check #(8, 24) check_x (.in(in_x), .result(x_check_res));
- special_check #(8, 24) check_y (.in(in_y), .result(y_check_res));
-
- assign x_is_zero = x_check_res[3] | x_check_res[4];
- assign x_is_inf = x_check_res[0] | x_check_res[7];
- assign x_is_qNaN = x_check_res[9];
- assign x_is_sNaN = x_check_res[8];
-
- assign y_is_zero = y_check_res[3] | y_check_res[4];
- assign y_is_inf = y_check_res[0] | y_check_res[7];
- assign y_is_qNaN = y_check_res[9];
- assign y_is_sNaN = y_check_res[8];
-
- // unpacking inputs
- assign sign_x = in_x[31];
- assign sign_y = in_y[31];
- assign exp_x = in_x[30:23];
- assign exp_y = in_y[30:23];
- assign mant_x = in_x[22:0];
- assign mant_y = in_y[22:0];
-
- // comparing both numbers
- assign comp = (exp_y > exp_x) ? 1'b1 : (exp_y != exp_x) ? 1'b0 : (mant_y > mant_x);
-
- // determining operation to be performed
- assign operator_y = sign_y ^ operation;
- assign subtract = sign_x ^ operator_y;
-
- // determining output sign
- assign sign_z = x_is_zero ? (operator_y) : (y_is_zero ? sign_x :
- (subtract ? (comp ? operator_y : sign_x) : sign_x));
-
- // swapping operands
- assign {exp_a, mant_a} = comp ? {exp_y, mant_y} : {exp_x, mant_x};
- assign {exp_b, mant_b} = comp ? {exp_x, mant_x} : {exp_y, mant_y};
-
- // checking for subnormal numbers
- assign a_is_subnorm = (|exp_a == 0);
- assign b_is_subnorm = (|exp_b == 0);
-
- // checking difference in exponents
- assign exp_diff = (a_is_subnorm | b_is_subnorm) & (exp_a != exp_b) ? (exp_a - exp_b - 1)
- : (exp_a - exp_b);
-
- // generating hidden bits
- assign hd_bit_a = !a_is_subnorm;
- assign hd_bit_b = !b_is_subnorm;
-
- // right shifting mantissa to make exponents equal
- right_shifter exp_equalizer (.mantisa({hd_bit_b, mant_b, 3'b000}), .shift_amount(exp_diff),
- .out(rt_shift_mant));
-
- // computing sum of the mantissas
- assign arg1 = {hd_bit_a, mant_a, 3'b0};
- assign arg2 = subtract ? (~rt_shift_mant + 27'b1) : rt_shift_mant;
-
- assign {cout, mant_sum} = {1'b0,arg1} + {1'b0,arg2};
- assign cout_check = cout & ~subtract;
-
- leading_zero norm_dist_checker (.in(mant_sum[26:3]), .out(ld_zero_cnt));
-
- // computing the shift amount
- assign inter_shft_amt = a_is_subnorm ? 8'b0 : {3'b0, ld_zero_cnt};
- assign exp_shft_comp = (exp_a <= inter_shft_amt);
- assign shft_amt = exp_shft_comp ? (exp_a - |exp_a) : inter_shft_amt;
-
- left_shifter #(27) norm_shifter (.mantisa(mant_sum), .shift_amount(shft_amt),
- .out(lt_shft_mant));
-
- // determining the exponent increment/decrement
- assign norm_sum = cout_check ? {cout, mant_sum[26:2], |mant_sum[1:0]} : lt_shft_mant;
- assign inc_dec_exp_amt = a_is_subnorm ? 5'b0 : cout_check ? 5'b1 : shft_amt;
-
- rounding add_sub_rounder (.sign(sign_z), .mantisa(norm_sum), .round_mode(round_mode),
- .rounded_mantisa(rounded_mant), .rounding_overflow(round_of));
-
- // determine exponent in case of normal numbers
- assign norm_exp = cout_check ? (exp_a + inc_dec_exp_amt + round_of) :
- (exp_a - inc_dec_exp_amt + round_of);
-
- // determine exponent in case of subnormal numbers
- assign subnorm_exp = (rounded_mant[23] & !(|norm_exp)) ? 8'b1 :
- (norm_exp - ((hd_bit_a | hd_bit_b) & exp_shft_comp & !rounded_mant[23]));
-
- assign {exp_z, mant_z} = x_is_zero ? {exp_y, mant_y} : (y_is_zero ? {exp_x, mant_x} :
- ((mant_x == mant_y) & (exp_x == exp_y) & subtract ? 'd0 :
- {subnorm_exp, rounded_mant[22:0]}));
-
- // result check for special numbers
- assign inter_result = (x_is_qNaN | y_is_qNaN) ? {1'h0, 8'hff, 23'h400000} :
- ((x_is_inf | y_is_inf) ? {sign_z, 8'hff, 23'h0} : ((exp_z == 8'hff) ?
- {sign_z, exp_z, 23'd0} : {sign_z, exp_z, mant_z}));
-
- assign invalid_operation = !(x_is_qNaN | y_is_qNaN) & (x_is_inf & y_is_inf & subtract) |
- x_is_sNaN | y_is_sNaN;
-
- // does not occur in addition subtraction
- assign divide_by_zero = 0;
-
- assign overflow = !(x_is_qNaN | y_is_qNaN) & &exp_z & !(x_is_inf | y_is_inf | x_is_qNaN |
- y_is_qNaN | x_is_sNaN | y_is_sNaN);
-
- // determining result in case of overflow
- assign of_result = ({32{(round_mode == 3'h0) | (round_mode == 3'h4)}} & {sign_z, 8'hff, 23'h0}) |
- ({32{round_mode == 3'h1}} & {sign_z, 8'hfe, 23'h7fffff}) |
- ({32{round_mode == 3'h2}} & (sign_z ? {1'h1, 8'hff, 23'h0} :
- {1'h0, 8'hfe, 23'h7fffff})) |
- ({32{round_mode == 3'h3}} & (sign_z ? {1'h1, 8'hfe, 23'h7fffff} :
- {1'h0, 8'hff, 23'h0}));
-
- // does not occur in addition subtraction
- assign underflow = 0;
-
- assign inexact = !(x_is_qNaN | y_is_qNaN) & (|norm_sum[2:0] | overflow | underflow) &
- !(x_is_zero | y_is_zero | x_is_qNaN | y_is_qNaN | x_is_sNaN | y_is_sNaN |
- x_is_inf | y_is_inf);
-
- assign exceptions = {invalid_operation, divide_by_zero, overflow, underflow, inexact};
-
- // assign output
- assign out_z = overflow ? of_result : underflow ? 32'd0 : invalid_operation ?
- {1'h0, 8'hff, 23'h400000} : inter_result;
-
-endmodule
diff --git "a/verilog/rtl/attachments\0501\051/compare.sv" "b/verilog/rtl/attachments\0501\051/compare.sv"
deleted file mode 100644
index 3c74700..0000000
--- "a/verilog/rtl/attachments\0501\051/compare.sv"
+++ /dev/null
@@ -1,87 +0,0 @@
-//`include "fpu_lib.sv"
-
-module compare#(parameter exp_width = 8, parameter mant_width = 24)
-(
- input wire [(exp_width + mant_width)-1:0] a,
- input wire [(exp_width + mant_width)-1:0] b,
- input wire [1:0] op,
-
- output wire [(exp_width + mant_width)-1:0] out,
- output wire [4:0] exceptions
-);
- wire lt, gt, eq, unordered;
- wire sign_a, sign_b;
- wire [exp_width-1:0] exp_a, exp_b;
- wire [mant_width-2:0] mant_a, mant_b;
-
- wire is_a_zero, is_a_inf, is_a_qNaN, is_a_sNaN;
- wire is_b_zero, is_b_inf, is_b_qNaN, is_b_sNaN;
- wire both_inf, both_zero;
- wire ordered, exp_equal;
- wire lt_mag, eq_mag, ordered_eq, ordered_lt;
- wire invalid, div_by_zero, overflow, underflow, inexact;
- wire [9:0] spec_value_chk_a, spec_value_chk_b;
-
-
-// extracting sign,exponent and mantissa of numbers
- assign {sign_a,exp_a,mant_a} = a;
- assign {sign_b,exp_b,mant_b} = b;
-
-// module to check for special values
- special_check #(exp_width,mant_width) special_check_a (.in (a), .result(spec_value_chk_a));
- special_check #(exp_width,mant_width) special_check_b (.in (b), .result(spec_value_chk_b));
-
- assign is_a_zero = spec_value_chk_a[3] | spec_value_chk_a[4];
- assign is_a_inf = spec_value_chk_a[0] | spec_value_chk_a[7];
- assign is_a_qNaN = spec_value_chk_a[9];
- assign is_a_sNaN = spec_value_chk_a[8];
-
- assign is_b_zero = spec_value_chk_b[3] | spec_value_chk_b[4];
- assign is_b_inf = spec_value_chk_b[0] | spec_value_chk_b[7];
- assign is_b_qNaN = spec_value_chk_b[9];
- assign is_b_sNaN = spec_value_chk_b[8];
-
-// check if inputs are valid or not
- assign ordered = !(is_a_qNaN || is_b_qNaN) && !(is_a_sNaN || is_b_sNaN);
- assign both_inf = is_a_inf && is_b_inf;
- assign both_zero = is_a_zero && is_b_zero;
-
-// comparison of exponents
- assign exp_equal = (exp_a == exp_b);
-
-// comparison of mantissas
- assign lt_mag = (exp_a < exp_b) || (exp_equal && (mant_a < mant_b));
- assign eq_mag = exp_equal && (mant_a == mant_b);
-
-// valid inputs and equal
- assign ordered_eq = both_zero || (sign_a == sign_b) && (both_inf || eq_mag);
-
-// valid inputs and a is less than b
- assign ordered_lt = !both_zero && ((sign_a && !sign_b) || (!both_inf && ((sign_a && !lt_mag && ! eq_mag)
- || (!sign_b && lt_mag))));
-
- assign lt = ordered && ordered_lt;
- assign eq = ordered && ordered_eq;
- assign gt = ordered && !ordered_eq && !ordered_lt;
-
-// invalid exception would be generated if any or both numbers are NaN
- assign invalid = is_a_sNaN || is_b_sNaN || ((is_a_qNaN || is_b_qNaN) && !(op == 3'b010));
-
-
-// unordered flag is set to high if any or both inputs are NaN
- assign unordered = !ordered;
-
-// hardwired exceptions that cannot be flagged in comparator
- assign div_by_zero = 1'b0;
- assign overflow = 1'b0;
- assign underflow = 1'b0;
- assign inexact = 1'b0;
-
- assign exceptions = {invalid, div_by_zero, overflow, underflow, inexact};
-
-
- assign out = ({32{op == 3'b10}} & {31'b0,eq}) |
- ({32{op == 3'b01}} & {31'b0,lt}) |
- ({32{op == 3'b00}} & ({31'b0,lt} | {31'b0,eq}));
-
-endmodule
diff --git "a/verilog/rtl/attachments\0501\051/config.tcl" "b/verilog/rtl/attachments\0501\051/config.tcl"
deleted file mode 100644
index 80904ef..0000000
--- "a/verilog/rtl/attachments\0501\051/config.tcl"
+++ /dev/null
@@ -1,69 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# Base Configurations. Don't Touch
-# section begin
-set script_dir [file dirname [file normalize [info script]]]
-
-source $script_dir/../../caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
-
-set ::env(DESIGN_NAME) user_project_wrapper
-#section end
-
-# User Configurations
-
-## Source Verilog Files
-set ::env(VERILOG_FILES) "\
- $script_dir/../../caravel/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_project_wrapper.v"
-
-## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
-
-set ::env(CLOCK_PERIOD) "20"
-
-## Internal Macros
-### Macro Placement
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
-
-### Black-box verilog and views
-set ::env(VERILOG_FILES_BLACKBOX) "\
- $script_dir/../../caravel/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_project_example.sv"
-
-set ::env(EXTRA_LEFS) "\
- $script_dir/../../lef/user_proj_example.lef"
-
-set ::env(EXTRA_GDS_FILES) "\
- $script_dir/../../gds/user_proj_example.gds"
-
-set ::env(GLB_RT_MAXLAYER) 5
-
-set ::env(FP_PDN_CHECK_NODES) 0
-
-# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
diff --git "a/verilog/rtl/attachments\0501\051/config_1.tcl" "b/verilog/rtl/attachments\0501\051/config_1.tcl"
deleted file mode 100644
index 12f5d47..0000000
--- "a/verilog/rtl/attachments\0501\051/config_1.tcl"
+++ /dev/null
@@ -1,42 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-set script_dir [file dirname [file normalize [info script]]]
-
-set ::env(DESIGN_NAME) user_proj_example
-
-set ::env(VERILOG_FILES) "\
- $script_dir/../../caravel/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_project_example.sv"
-
-set ::env(CLOCK_PORT) ""
-set ::env(CLOCK_NET) "seq_det.clk"
-set ::env(CLOCK_PERIOD) "10"
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 600"
-set ::env(DESIGN_IS_CORE) 0
-
-set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
-set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
-
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.1
-set ::env(CLOCK_TREE_SYNTH) 0
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 1
diff --git "a/verilog/rtl/attachments\0501\051/defines.v" "b/verilog/rtl/attachments\0501\051/defines.v"
deleted file mode 100644
index 3c9e595..0000000
--- "a/verilog/rtl/attachments\0501\051/defines.v"
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-// Global parameters
-
-`define MPRJ_IO_PADS 38
-`define MPRJ_PWR_PADS 4 /* vdda1, vccd1, vdda2, vccd2 */
-
-// Size of soc_mem_synth
-
-// Type and size of soc_mem
-// `define USE_OPENRAM
-`define USE_CUSTOM_DFFRAM
-// don't change the following without double checking addr widths
-`define MEM_WORDS 256
-
-// Number of columns in the custom memory; takes one of three values:
-// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
-`define COLS 1
-
-// not really parameterized but just to easily keep track of the number
-// of ram_block across different modules
-`define RAM_BLOCKS 2
-
-// Clock divisor default value
-`define CLK_DIV 3'b010
-
-// GPIO conrol default mode and enable
-`define DM_INIT 3'b110
-`define OENB_INIT 1'b1
\ No newline at end of file
diff --git "a/verilog/rtl/attachments\0501\051/defs.vi" "b/verilog/rtl/attachments\0501\051/defs.vi"
deleted file mode 100644
index 0d545af..0000000
--- "a/verilog/rtl/attachments\0501\051/defs.vi"
+++ /dev/null
@@ -1,23 +0,0 @@
-
-`define flControl_default `flControl_tininessAfterRounding
-
-`define HardFloat_propagateNaNPayloads
-
-`define HardFloat_signDefaultNaN 0
-`define HardFloat_fractDefaultNaN(sigWidth) {1'b1, {((sigWidth) - 2){1'b0}}}
-
-`define round_near_even 3'b000
-`define round_minMag 3'b001
-`define round_min 3'b010
-`define round_max 3'b011
-`define round_near_maxMag 3'b100
-`define round_odd 3'b110
-
-`define floatControlWidth 1
-`define flControl_tininessBeforeRounding 1'b0
-`define flControl_tininessAfterRounding 1'b1
-
-`define flRoundOpt_sigMSBitAlwaysZero 1
-`define flRoundOpt_subnormsAlwaysExact 2
-`define flRoundOpt_neverUnderflows 4
-`define flRoundOpt_neverOverflows 8
diff --git "a/verilog/rtl/attachments\0501\051/divider.sv" "b/verilog/rtl/attachments\0501\051/divider.sv"
deleted file mode 100644
index 75871d6..0000000
--- "a/verilog/rtl/attachments\0501\051/divider.sv"
+++ /dev/null
@@ -1,166 +0,0 @@
-//`include "fpu_lib.sv"
-
-module divider#( parameter exp_width = 8, parameter mant_width = 24, parameter options = 0)
-(
- input wire rst_l,
- input wire clk,
- input wire in_valid,
- input wire [(exp_width + mant_width)-1:0] a,
- input wire [(exp_width + mant_width)-1:0] b,
- input wire [2:0] round_mode,
- input wire cancel,
-
- output wire in_ready,
- output wire out_valid,
- output wire [(exp_width + mant_width)-1:0] out,
- output wire [4:0] exceptions
-);
-
-function integer clog2;
- input integer a;
-
- begin
- a = a - 1;
- for (clog2 = 0; a > 0; clog2 = clog2 + 1) a = a>>1;
- end
-
-endfunction
-
- wire is_a_qNaN, is_a_inf, is_a_zero, is_a_sNaN, sign_a;
- wire signed [(exp_width+1):0] sexp_a;
- wire [mant_width:0] mant_a;
-
- wire is_b_qNaN, is_b_inf, is_b_zero, is_b_sNaN, sign_b;
- wire signed [(exp_width+1):0] sexp_b;
- wire [mant_width:0] mant_b;
- wire [(exp_width + mant_width):0] oper1, oper2;
-
- wire [2:0] roundingModeOut;
- wire invalid_excep;
- wire infinite_excep;
- wire is_out_NaN;
- wire is_out_inf;
- wire is_out_zero;
- wire out_sign;
- wire signed [(exp_width + 1):0] out_sexp;
- wire [(mant_width + 2):0] out_mant;
-
- wire not_sNaN_invalid_exc ;
- wire major_excep;
- wire is_res_NaN;
- wire is_res_inf;
- wire is_res_zero;
- wire sign_res;
- wire spec_case_a;
- wire spec_case_b;
- wire norm_case;
- wire signed [(exp_width + 2):0] sexp_quot;
- wire signed [(exp_width + 1):0] s_sat_exp_quot;
-
- wire [(clog2(mant_width + 3) - 1):0] cycle_num, cycle_num_in;
- wire major_exc_z;
- wire is_NaN_z, is_inf_z, is_zero_z, sign_z;
- wire signed [(exp_width + 1):0] sexp_z;
- wire [(mant_width - 2):0] mant_b_z;
- wire [2:0] round_mode_z;
-
- wire [(mant_width + 1):0] rem_z, rem_z_in;
- wire not_zero_rem_z;
- wire [(mant_width + 1):0] mantx_z, mantx_z_in;
- wire idle;
- wire entering;
- wire entering_norm_case;
- wire skipCycle2;
-
- wire [1:0] dec_hi_mant_a;
- wire [(mant_width + 2):0] rem;
- wire [mant_width:0] bit_mask;
- wire [(mant_width + 1):0] trail_term;
- wire signed [(mant_width + 3):0] trail_rem;
- wire new_bit;
- wire cancel_reset;
-
- assign cancel_reset = rst_l & !cancel;
-
- exponent #(exp_width, mant_width) exp_a (.in(a), .out(oper1));
- exponent #(exp_width, mant_width) exp_b (.in(b), .out(oper2));
-
- mac_spec_check #(exp_width,mant_width ) mac_spec_check_a (.in(oper1), .is_qNaN (is_a_qNaN), .is_inf(is_a_inf), .is_zero(is_a_zero),
- .is_sNaN(is_a_sNaN),.sign(sign_a), .s_exp(sexp_a), .sig(mant_a) );
-
-
- mac_spec_check #(exp_width,mant_width ) mac_spec_check_b (.in(oper2), .is_qNaN (is_b_qNaN), .is_inf(is_b_inf), .is_zero(is_b_zero),
- .is_sNaN(is_b_sNaN),.sign(sign_b), .s_exp(sexp_b), .sig(mant_b) );
-
- assign not_sNaN_invalid_exc = (is_a_zero && is_b_zero) || (is_a_inf && is_b_inf);
- assign major_excep = is_a_sNaN || is_b_sNaN || not_sNaN_invalid_exc || (!is_a_qNaN && !is_a_inf && is_b_zero);
- assign is_res_NaN = is_a_qNaN || is_b_qNaN || not_sNaN_invalid_exc;
-
- assign is_res_inf = is_a_inf || is_b_zero;
- assign is_res_zero = is_a_zero || is_b_inf;
- assign sign_res = sign_a ^ sign_b;
-
- assign spec_case_a = is_a_qNaN || is_a_inf || is_a_zero;
- assign spec_case_b = is_b_qNaN || is_b_inf || is_b_zero;
- assign norm_case = !spec_case_a && !spec_case_b;
-
- assign sexp_quot = sexp_a + {{3{sexp_b[exp_width]}}, ~sexp_b[(exp_width - 1):0]};
- assign s_sat_exp_quot = {(7<<(exp_width - 2) <= sexp_quot) ? 4'b0110 :
- sexp_quot[(exp_width + 1):(exp_width - 2)], sexp_quot[(exp_width - 3): 0]};
-
- assign idle = (cycle_num == 0);
- assign in_ready = (cycle_num <= 1);
- assign entering = in_ready && in_valid;
- assign entering_norm_case = entering && norm_case;
- assign skipCycle2 = (cycle_num == 3) && mantx_z[mant_width + 1];
-
- assign cycle_num_in = (entering && !norm_case ? 1 : 0)
- | (entering_norm_case ? (mant_width + 2) : 0)
- | (!idle && !skipCycle2 ? cycle_num - 1 : 0)
- | (!idle && skipCycle2 ? 1 : 0);
-
- rvdffe #(clog2(mant_width + 3)) cycle_num_ff (.clk(clk), .rst_l(cancel_reset), .din(cycle_num_in), .en(!idle || in_valid), .dout(cycle_num));
-
- rvdffe #(1) major_exc_z_ff (.clk(clk), .rst_l(cancel_reset), .din(major_excep), .en(entering), .dout(major_exc_z));
- rvdffe #(1) is_NaN_z_ff (.clk(clk), .rst_l(cancel_reset), .din(is_res_NaN), .en(entering), .dout(is_NaN_z));
- rvdffe #(1) is_inf_z_ff (.clk(clk), .rst_l(cancel_reset), .din(is_res_inf), .en(entering), .dout(is_inf_z));
- rvdffe #(1) is_zero_z_ff (.clk(clk), .rst_l(cancel_reset), .din(is_res_zero), .en(entering), .dout(is_zero_z));
- rvdffe #(1) sign_z_ff (.clk(clk), .rst_l(cancel_reset), .din(sign_res), .en(entering), .dout(sign_z));
-
- rvdffe #((exp_width + 2)) sexp_z_ff (.clk(clk), .rst_l(cancel_reset), .din(s_sat_exp_quot), .en(entering_norm_case), .dout(sexp_z));
- rvdffe #(3) round_mode_z_ff (.clk(clk), .rst_l(cancel_reset), .din(round_mode), .en(entering_norm_case), .dout(round_mode_z));
- rvdffe #((mant_width - 1)) mant_b_z_ff (.clk(clk), .rst_l(cancel_reset), .din(mant_b[(mant_width - 2):0]), .en(entering_norm_case), .dout(mant_b_z));
-
- assign dec_hi_mant_a = mant_a[(mant_width - 1):(mant_width - 2)] - 1;
- assign rem = (in_ready ? mant_a<<1 : 0) | (!in_ready ? rem_z<<1 : 0);
- assign bit_mask = ({{(mant_width + 2){1'b0}}, 1'b1}<<cycle_num)>>2;
- assign trail_term = ( in_ready ? mant_b<<1 : 0)
- |(!in_ready ? {1'b1, mant_b_z}<<1 : 0);
- assign trail_rem = rem - trail_term;
- assign new_bit = (0 <= trail_rem);
-
- assign rem_z_in = new_bit ? trail_rem : rem;
- rvdffe #((mant_width + 2)) rem_z_ff (.clk(clk), .rst_l(cancel_reset), .din(rem_z_in), .en(entering_norm_case || (cycle_num > 2)), .dout(rem_z));
- rvdffe #(1) not_zero_rem_z_ff (.clk(clk), .rst_l(cancel_reset), .din((trail_rem != 0)), .en(entering_norm_case || (!in_ready && new_bit)), .dout(not_zero_rem_z));
-
- assign mantx_z_in = ( in_ready ? new_bit<<(mant_width + 1) : 0)
- | (!in_ready ? mantx_z | bit_mask : 0);
- rvdffe #((mant_width + 2)) mantx_z_ff (.clk(clk), .rst_l(cancel_reset), .din(mantx_z_in), .en(entering_norm_case || (!in_ready && new_bit)), .dout(mantx_z));
-
- assign out_valid = (cycle_num == 1);
- assign roundingModeOut = round_mode_z;
- assign invalid_excep = major_exc_z && is_NaN_z;
- assign infinite_excep = major_exc_z && !is_NaN_z;
- assign is_out_NaN = is_NaN_z;
- assign is_out_inf = is_inf_z;
- assign is_out_zero = is_zero_z;
- assign out_sign = sign_z;
- assign out_sexp = sexp_z;
- assign out_mant = {mantx_z, not_zero_rem_z};
-
- round_excep #(exp_width, mant_width+2, exp_width,mant_width,0) round_exception
- ( .invalid_excep(invalid_excep), .infinite_excep(infinite_excep), .in_is_NaN(is_out_NaN),
- .in_is_inf(is_out_inf), .in_is_zero(is_out_zero),.in_sign(out_sign),.in_sexp(out_sexp),
- .in_mant(out_mant),.round_mode(round_mode), .result(out), .exceptions(exceptions));
-
-endmodule
diff --git "a/verilog/rtl/attachments\0501\051/f_class.sv" "b/verilog/rtl/attachments\0501\051/f_class.sv"
deleted file mode 100644
index 75a8fd4..0000000
--- "a/verilog/rtl/attachments\0501\051/f_class.sv"
+++ /dev/null
@@ -1,15 +0,0 @@
-// `include "fpu_lib.sv"
-
-module f_class #(parameter exp_width = 8, parameter mant_width = 24)
-(
- input wire [(exp_width + mant_width)-1:0] in,
-
- output wire [31:0] result
-);
- wire [9:0] value_check;
-
- special_check special_chk (.in(in), .result(value_check));
-
- assign result = {22'b0, value_check};
-
-endmodule
diff --git "a/verilog/rtl/attachments\0501\051/float_to_int.sv" "b/verilog/rtl/attachments\0501\051/float_to_int.sv"
deleted file mode 100644
index 2766deb..0000000
--- "a/verilog/rtl/attachments\0501\051/float_to_int.sv"
+++ /dev/null
@@ -1,125 +0,0 @@
-//`include "fpu_lib.sv"
-
-module float_to_int#( parameter exp_width = 8, parameter mant_width = 24, parameter int_width = 32)
-(
- input wire [(exp_width + mant_width)-1:0] num,
- input wire [2:0] round_mode,
- input wire signed_out,
- output wire [(int_width - 1):0] out,
- output wire [4:0] int_exceptions
-);
-
-function integer clog2;
- input integer a;
-
- begin
- a = a - 1;
- for (clog2 = 0; a > 0; clog2 = clog2 + 1) a = a>>1;
- end
-
-endfunction
-
- localparam int_exp_width = clog2(int_width);
- localparam norm_dist_width = clog2(mant_width);
- localparam bound_exp_width = (exp_width <= int_exp_width) ? exp_width - 1 : int_exp_width;
-
- wire sign_num;
- wire [exp_width-1:0] exp_num;
- wire [mant_width-2:0] mant_num;
-
- wire is_num_zero, is_num_inf, is_num_qNaN, is_num_sNaN, exp_zero, mant_zero;
-
- wire [(norm_dist_width-1):0] norm_dist;
-
- wire [exp_width:0] adjusted_exp, exp_final;
- wire is_special, mag_one, mag_below_one;
- wire signed [(exp_width):0] signed_exp;
- wire [(exp_width-1):0] pos_exp;
-
- wire round_mode_near_even, round_mode_min_mag, round_mode_min;
- wire round_mode_max,round_mode_near_max_mag;
-
- wire [(int_width + mant_width)-2:0] shifted_sig;
- wire [int_width+1:0] aligned_sig;
- wire [int_width-1:0] unrounded_int, comp_unrounded_int, rounded_int;
-
- wire common_inexact, round_incr_near_even, round_incr_near_max_mag, round_incr;
- wire mag_one_overflow, common_overflow;
-
- wire invalid, overflow, inexact;
- wire [(int_width-1):0] exc_out;
- wire [9:0] num_check_res;
-
-
- assign {sign_num, exp_num, mant_num} = num;
-
- special_check #(exp_width,mant_width) special_check_in (.in (num), .result(num_check_res));
-
- assign is_num_zero = num_check_res[3] | num_check_res[4];
- assign is_num_inf = num_check_res[0] | num_check_res[7];
- assign is_num_qNaN = num_check_res[9];
- assign is_num_sNaN = num_check_res[8];
-
-// check exponent and mantissa is zero (needs to be a better way)
- assign exp_zero = (exp_num == 0);
- assign mant_zero = (mant_num == 0);
-
-// computing location of first one
- lead_zero_param#(mant_width-1, norm_dist_width) countLeadingZeros(mant_num, norm_dist);
-
- assign adjusted_exp = (exp_zero ? norm_dist ^ ((1 << (exp_width+1))-1) : exp_num)
- + ((1<<(exp_width-1)) | (exp_zero ? 2:1));
-
- assign is_special = (adjusted_exp[exp_width:(exp_width - 1)] == 'b11);
- assign exp_final[exp_width:(exp_width - 2)] = is_special ? {2'b11, !mant_zero} :is_num_zero ? 3'b000 :
- adjusted_exp[exp_width:(exp_width - 2)];
- assign exp_final[(exp_width - 3):0] = adjusted_exp;
-
- assign signed_exp = exp_final;
- assign mag_one = signed_exp[exp_width];
- assign pos_exp = signed_exp[(exp_width-1):0];
- assign mag_below_one = !mag_one && (&pos_exp);
-
- assign round_mode_near_even = (round_mode == `round_near_even);
- assign round_mode_min_mag = (round_mode == `round_minMag);
- assign round_mode_min = (round_mode == `round_min);
- assign round_mode_max = (round_mode == `round_max);
- assign round_mode_near_max_mag = (round_mode == `round_near_maxMag);
-
- assign shifted_sig = {mag_one,mant_num[(mant_width-2):0]} <<
- (mag_one ? signed_exp[(bound_exp_width - 1):0] : 0);
- assign aligned_sig = {shifted_sig>>(mant_width-2), |shifted_sig[(mant_width-3):0]};
- assign unrounded_int = aligned_sig >> 2;
-
- assign common_inexact = mag_one ? |aligned_sig[1:0] : !is_num_zero;
-
- assign round_incr_near_even = (mag_one && ((&aligned_sig[2:1]) || (&aligned_sig[1:0])))
- || (mag_below_one && (|aligned_sig[1:0]) );
- assign round_incr_near_max_mag = (mag_one && aligned_sig[1]) || mag_below_one ;
-
- assign round_incr = (round_mode_near_even && round_incr_near_even) ||
- (round_mode_near_max_mag && round_incr_near_max_mag) ||
- ((round_mode_min )) && (sign_num && common_inexact) ||
- (round_mode_max && (!sign_num && common_inexact));
-
-
- assign comp_unrounded_int = sign_num ? ~unrounded_int : unrounded_int;
- assign rounded_int = ((round_incr ^ sign_num) ? comp_unrounded_int+1 : comp_unrounded_int) ;
-
- assign mag_one_overflow = (pos_exp == int_width-1);
- assign common_overflow = mag_one ? (pos_exp >= int_width) || (signed_out ? (sign_num ? mag_one_overflow
- && ((|unrounded_int[(int_width-2):0]) ||round_incr)
- : mag_one_overflow) : sign_num) : !signed_out && sign_num && round_incr;
-
- assign invalid = is_num_qNaN || is_num_sNaN || is_num_inf;
- assign overflow = !invalid && common_overflow;
- assign inexact = !invalid && !common_overflow && common_inexact;
-
- int_excep #(int_width) integer_exception (.signed_out(signed_out), .is_qNaN(is_num_qNaN), .is_sNaN(is_num_sNaN),
- .sign(sign_num) , .execp_out(exc_out));
-
- assign out = (invalid || common_overflow) ? exc_out : rounded_int;
-
- assign int_exceptions = {invalid,1'b0, overflow, 1'b0, inexact};
-
-endmodule
diff --git "a/verilog/rtl/attachments\0501\051/fpu.sv" "b/verilog/rtl/attachments\0501\051/fpu.sv"
deleted file mode 100644
index c6c5b01..0000000
--- "a/verilog/rtl/attachments\0501\051/fpu.sv"
+++ /dev/null
@@ -1,210 +0,0 @@
-`include "compare.sv"
-`include "add_sub.sv"
-`include "fpu_lib.sv"
-`include "float_to_int.sv"
-`include "f_class.sv"
-`include "divider.sv"
-`include "min_max.sv"
-`include "multiplier.sv"
-`include "sign_inject.sv"
-`include "int_to_float.sv"
-`include "fused_mul.sv"
-`include "sqrt_fpu.sv"
-`include "registers.sv"
-
-module fpu_top
-(
- input wire clk,
- input wire rst_l, // active low reset
-
- input wire wb_valid, // valid signal from wb
- input wire [31:0] rdwraddr, // read/write address from wb
- input wire [31:0] wrdata, // write data received from wb
-
- input wire [31:0] la_write, // wire analyzer write enable
- input wire [31:0] la_data, // wire analyzer write data
- input wire [31:0] la_addr, // wire analyzer address
-//outputs
- output wire illegal_op,
- output wire inter_gen,
-
- output wire [31:0] rddata, // read data sent to wb
- output wire [31:0] out, // to GPIO
- output wire [4:0] exceptions // on hold for now
-);
- wire la_write_en;
-
- wire [31:0] a;
- wire [31:0] b;
- wire [31:0] c;
-
- wire [1:0] op_in;
- wire [1:0] op_out;
-
- wire [2:0] round_mode;
-
- wire [10:0] valid_in; // (sqrt, div, fma, multi, add-sub, f2i, i2f, min-max, comp, sign_inj, f-class)
- wire [10:0] valid_out;
-
- wire [31:0] fclass_out;
-
- wire [4:0] cmp_exceptions;
- wire [31:0] cmp_out;
-
- wire [4:0] min_max_exceptions;
- wire [31:0] min_max_out;
-
- wire [4:0] itof_exceptions;
- wire [31:0] itof_out;
-
- wire [4:0] ftoi_exceptions;
- wire [31:0] ftoi_out;
-
- wire [31:0] sinj_out;
-
- wire [4:0] add_sub_exceptions;
- wire [31:0] add_sub_out;
-
- wire [4:0] mul_exceptions;
- wire [31:0] mul_out;
-
- wire [4:0] mac_exceptions;
- wire [31:0] mac_out;
-
- wire [4:0] sqrt_exceptions;
- wire [31:0] sqrt_out;
-
- wire [4:0] div_exceptions;
- wire [31:0] div_out;
- wire div_valid_out;
- wire sqrt_valid_out;
-
- wire [4:0] excep_temp;
- wire [31:0] out_temp;
-
- wire [31:0] int_rddata;
- wire [31:0] addr;
-
- assign la_write_en = |la_write;
- assign addr = la_write_en ? la_addr : rdwraddr;
-
- fpu_registers csrs ( .clk (clk ),
- .rst_l (rst_l ),
- .fpu_result (out ),
- .fpu_valids ({valid_out, op_out} ),
- .addr (addr ),
- .wren (wb_valid ),
- .wrdata (wrdata ),
- .exceptions (exceptions ),
- .rddata (int_rddata ),
- .opA (a ),
- .opB (b ),
- .opC (c ),
- .frm (round_mode ),
- .op_valids ({valid_in, op_in} ),
- .inter_gen (inter_gen ));
-
- f_class #(8,24) fpu_fclass ( .in (a ),
- .result (fclass_out ) );
-
- sign_inject #(8,24) fpu_sgn_inj ( .a (a ),
- .b (b ),
- .op (op_in ),
- .out (sinj_out ) );
-
- compare #(8,24) fpu_comp ( .a (a ),
- .b (b ),
- .op (op_in ),
- .out (cmp_out ),
- .exceptions (cmp_exceptions ) );
-
- min_max #(8,24) fpu_min_max ( .a (a ),
- .b (b ),
- .op (op_in[0] ),
- .out (min_max_out ),
- .exceptions (min_max_exceptions ) );
-
- int_to_float #(32,8,24) fpu_i2f ( .signed_in (op_in[0] ),
- .num (a ),
- .round_mode (round_mode ),
- .out (itof_out ),
- .exceptions (itof_exceptions ) );
-
- float_to_int #(8,24) fpu_f2i ( .num (a ),
- .round_mode (round_mode ),
- .signed_out (op_in[0] ),
- .out (ftoi_out ),
- .int_exceptions (ftoi_exceptions ) );
-
- add_sub fpu_add_sub ( .in_x (a ),
- .in_y (b ),
- .operation (op_in[0] ),
- .round_mode (round_mode ),
- .out_z (add_sub_out ),
- .exceptions (add_sub_exceptions ) );
-
- multiplier #(8,24) fpu_mult ( .a (a ),
- .b (b ),
- .round_mode (round_mode ),
- .exceptions (mul_exceptions ),
- .out (mul_out ) );
-
- fused_multiply #(8,24) fpu_fma ( .a (a ),
- .b (b ),
- .c (c ),
- .op (op_in ),
- .round_mode (round_mode ),
- .out (mac_out ),
- .exceptions (mac_exceptions ) );
-
- divider #(8,24) fpu_divider ( .rst_l (rst_l ),
- .clk (clk ),
- .in_valid (valid_in[9] ),
- .a (a ),
- .b (b ),
- .round_mode (round_mode ),
- .cancel (1'b0 ),
- .in_ready (in_ready ),
- .out_valid (div_valid_out ),
- .out (div_out ),
- .exceptions (div_exceptions ) );
-
- sqrt #(8,24) fpu_sqrt ( .clk (clk ),
- .rst_l (rst_l ),
- .in_valid (valid_in[10] ),
- .a (a ),
- .round_mode (round_mode ),
- .cancel (1'b0 ),
- .in_ready (in_ready ),
- .out_valid (sqrt_valid_out ),
- .out (sqrt_out ),
- .exceptions (sqrt_exceptions ) );
-
-// check for illegal op in case of sign inject and compare result
- assign illegal_op = ((valid_in[1] || valid_in[2]) && (op_in == 2'b11)) ? 1'b1 : 1'b0;
-
-// output operation performed
- assign op_out = ({valid_in[1] || valid_in[2] || valid_in[3] || valid_in[6] || valid_in[8]}) ? op_in : 2'b0;
-
- assign valid_out = {sqrt_valid_out,div_valid_out,valid_in[8:0]};
-
-// return output data according to module enable
- assign {out, exceptions} = ({37{illegal_op}} & {32'b0 ,5'b0 }) |
- ({37{valid_in[10 & wb_valid]}} & {sqrt_out ,sqrt_exceptions }) |
- ({37{valid_in[9] & wb_valid}} & {div_out ,div_exceptions }) |
- ({37{valid_in[8] & wb_valid}} & {mac_out ,mac_exceptions }) |
- ({37{valid_in[7] & wb_valid}} & {mul_out ,mul_exceptions }) |
- ({37{valid_in[6] & wb_valid}} & {add_sub_out,add_sub_exceptions}) |
- ({37{valid_in[5] & wb_valid}} & {ftoi_out ,ftoi_exceptions }) |
- ({37{valid_in[4] & wb_valid}} & {itof_out ,ftoi_exceptions }) |
- ({37{valid_in[3] & wb_valid}} & {min_max_out,min_max_exceptions}) |
- ({37{valid_in[2] & wb_valid}} & {cmp_out ,cmp_exceptions }) |
- ({37{valid_in[1] & wb_valid}} & {sinj_out ,5'b0 }) |
- ({37{valid_in[0] & wb_valid}} & {fclass_out ,5'b0 });
-
-// data to be read from memory
- assign rddata = wb_valid ? 32'b0 : la_write_en ? (la_write & la_data) : int_rddata;
-
-endmodule
-
-
diff --git "a/verilog/rtl/attachments\0501\051/fpu_lib.sv" "b/verilog/rtl/attachments\0501\051/fpu_lib.sv"
deleted file mode 100644
index 92cffb2..0000000
--- "a/verilog/rtl/attachments\0501\051/fpu_lib.sv"
+++ /dev/null
@@ -1,658 +0,0 @@
-`include "defs.vi"
-
-module special_check #(parameter exp_width = 8, parameter mant_width = 24)
-(
- input wire [(exp_width + mant_width-1):0] in,
-
- output wire [9:0] result
-);
-
- wire is_pos_zero;
- wire is_neg_zero;
- wire is_pos_inf;
- wire is_neg_inf;
- wire is_pos_subnorm;
- wire is_neg_subnorm;
- wire is_pos_norm;
- wire is_neg_norm;
- wire is_qNaN;
- wire is_sNaN;
-
- wire sign;
- wire [exp_width-1:0] exp;
- wire [(mant_width-2):0] sig;
-
- wire exp_zero, exp_one, sig_zero;
-
-
- assign {sign, exp, sig} = in;
-
- assign exp_zero = |exp ? 1'b0 : 1'b1;
- assign sig_zero = |sig ? 1'b0 : 1'b1;
- assign exp_one = &exp ? 1'b1 : 1'b0;
-
- assign is_pos_zero = !sign & exp_zero & sig_zero;
- assign is_neg_zero = sign & exp_zero & sig_zero;
- assign is_pos_subnorm = !sign & exp_zero;
- assign is_neg_subnorm = sign & exp_zero;
- assign is_pos_inf = !sign & exp_one & sig_zero;
- assign is_neg_inf = sign & exp_one & sig_zero;
- assign is_qNaN = exp_one & !sig_zero & sig[22];
- assign is_sNaN = exp_one & !sig_zero & !sig[22];
-
- assign is_pos_norm = (is_pos_zero | is_neg_zero | is_pos_subnorm | is_neg_subnorm | is_pos_inf | is_neg_inf |
- is_qNaN | is_sNaN) ? 1'b0 : ~sign ? 1'b1 : 1'b0;
-
- assign is_neg_norm = (is_pos_zero | is_neg_zero | is_pos_subnorm | is_neg_subnorm | is_pos_inf | is_neg_inf |
- is_qNaN | is_sNaN) ? 1'b0 : sign ? 1'b1 : 1'b0;
-
- assign result = {is_qNaN, is_sNaN, is_pos_inf, is_pos_norm, is_pos_subnorm, is_pos_zero, is_neg_zero,
- is_neg_subnorm, is_neg_norm, is_neg_inf};
-endmodule
-
-module mac_spec_check #(parameter exp_width = 3, parameter mant_width = 3)
-(
- input wire [(exp_width + mant_width):0] in,
-
- output wire is_qNaN,
- output wire is_inf,
- output wire is_zero,
- output wire is_sNaN,
- output wire sign,
- output wire signed [(exp_width+1):0] s_exp,
- output wire [mant_width:0] sig
-);
-
- wire [exp_width:0] exp;
- wire [(mant_width - 2):0] mant;
- wire is_ssNaN;
- wire is_spec;
-
- assign {sign, exp, mant} = in;
-
- assign is_ssNaN = (in[(exp_width + mant_width - 1):(exp_width + mant_width - 3)] == 'b111);
- assign is_spec = (exp>>(exp_width - 1) == 'b11);
- assign is_qNaN = is_spec && exp[exp_width - 2];
- assign is_inf = is_spec && !exp[exp_width - 2];
- assign is_zero = (exp>>(exp_width - 2) == 'b000);
- assign is_sNaN = is_ssNaN && !in[mant_width - 2];
-
- assign s_exp = exp;
- assign sig = {1'b0, !is_zero, mant};
-
-endmodule
-
-module rounding
-(
- input wire sign,
- input wire [26:0] mantisa,
- input wire [2:0] round_mode,
-
- output wire [23:0] rounded_mantisa,
- output wire rounding_overflow
-);
-
- wire [23:0] rne, rtz, rdn, rup, rmm;
- wire rne_overflow, rtz_overflow, rdn_overflow, rup_overflow, rmm_overflow;
-
- assign {rne_overflow, rne} = mantisa[2] ? (|mantisa[1:0] ? ({1'b0, mantisa[26:3]} + 1'b1)
- : ({1'b0, mantisa[26:3]} + mantisa[3])) : {1'b0, mantisa[26:3]};
-
- assign {rtz_overflow, rtz} = {1'b0, mantisa[26:3]};
-
- assign {rdn_overflow, rdn} = |mantisa[2:0] ? (sign ? ({1'b0, mantisa[26:3]} + 1'b1)
- : {1'b0, mantisa[26:3]}) : {1'b0, mantisa[26:3]};
-
- assign {rup_overflow, rup} = |mantisa[2:0] ? (sign ? {1'b0, mantisa[26:3]}
- : ({1'b0, mantisa[26:3]} + 1'b1)) : {1'b0, mantisa[26:3]};
- assign {rmm_overflow, rmm} = mantisa[2] ? ({1'b0, mantisa[26:3]} + 1'b1) : {1'b0, mantisa[26:3]};
-
- assign rounded_mantisa = ({24{round_mode == 3'b000}} & rne) |
- ({24{round_mode == 3'b001}} & rtz) |
- ({24{round_mode == 3'b010}} & rdn) |
- ({24{round_mode == 3'b011}} & rup) |
- ({24{round_mode == 3'b100}} & rmm);
-
- assign rounding_overflow = ((round_mode == 3'b000) & rne_overflow) |
- ((round_mode == 3'b001) & rtz_overflow) |
- ((round_mode == 3'b010) & rdn_overflow) |
- ((round_mode == 3'b011) & rup_overflow) |
- ((round_mode == 3'b100) & rmm_overflow);
-
-endmodule
-
-
-module leading_zero
-(
- input wire [23:0] in,
-
- output wire [4:0] out
-);
- assign out[4:0] = ({5{(in[22] & (&(~(in[23]))))}} & 5'd1) |
- ({5{(in[21] & (&(~(in[23:22]))))}} & 5'd2) |
- ({5{(in[20] & (&(~(in[23:21]))))}} & 5'd3) |
- ({5{(in[19] & (&(~(in[23:20]))))}} & 5'd4) |
- ({5{(in[18] & (&(~(in[23:19]))))}} & 5'd5) |
- ({5{(in[17] & (&(~(in[23:18]))))}} & 5'd6) |
- ({5{(in[16] & (&(~(in[23:17]))))}} & 5'd7) |
- ({5{(in[15] & (&(~(in[23:16]))))}} & 5'd8) |
- ({5{(in[14] & (&(~(in[23:15]))))}} & 5'd9) |
- ({5{(in[13] & (&(~(in[23:14]))))}} & 5'd10) |
- ({5{(in[12] & (&(~(in[23:13]))))}} & 5'd11) |
- ({5{(in[11] & (&(~(in[23:12]))))}} & 5'd12) |
- ({5{(in[10] & (&(~(in[23:11]))))}} & 5'd13) |
- ({5{(in[9] & (&(~(in[23:10]))))}} & 5'd14) |
- ({5{(in[8] & (&(~(in[23: 9]))))}} & 5'd15) |
- ({5{(in[7] & (&(~(in[23: 8]))))}} & 5'd16) |
- ({5{(in[6] & (&(~(in[23: 7]))))}} & 5'd17) |
- ({5{(in[5] & (&(~(in[23: 6]))))}} & 5'd18) |
- ({5{(in[4] & (&(~(in[23: 5]))))}} & 5'd19) |
- ({5{(in[3] & (&(~(in[23: 4]))))}} & 5'd20) |
- ({5{(in[2] & (&(~(in[23: 3]))))}} & 5'd21) |
- ({5{(in[1] & (&(~(in[23: 2]))))}} & 5'd22) |
- ({5{(in[0] & (&(~(in[23: 1]))))}} & 5'd23);
-
-endmodule
-
-
-module leading_ones
-(
- input wire [31:0] in,
- output wire [4:0] out
-);
-
-assign out [4:0] = ({5{(in[31])}} & 5'd31) |
- ({5{(in[30] & (&(~(in[31]))))}} & 5'd30) |
- ({5{(in[29] & (&(~(in[31:30]))))}} & 5'd29) |
- ({5{(in[28] & (&(~(in[31:29]))))}} & 5'd28) |
- ({5{(in[27] & (&(~(in[31:28]))))}} & 5'd27) |
- ({5{(in[26] & (&(~(in[31:27]))))}} & 5'd26) |
- ({5{(in[25] & (&(~(in[31:26]))))}} & 5'd25) |
- ({5{(in[24] & (&(~(in[31:25]))))}} & 5'd24) |
- ({5{(in[23] & (&(~(in[31:24]))))}} & 5'd23) |
- ({5{(in[22] & (&(~(in[31:23]))))}} & 5'd22) |
- ({5{(in[21] & (&(~(in[31:22]))))}} & 5'd21) |
- ({5{(in[20] & (&(~(in[31:21]))))}} & 5'd20) |
- ({5{(in[19] & (&(~(in[31:20]))))}} & 5'd19) |
- ({5{(in[18] & (&(~(in[31:19]))))}} & 5'd18) |
- ({5{(in[17] & (&(~(in[31:18]))))}} & 5'd17) |
- ({5{(in[16] & (&(~(in[31:17]))))}} & 5'd16) |
- ({5{(in[15] & (&(~(in[31:16]))))}} & 5'd15) |
- ({5{(in[14] & (&(~(in[31:15]))))}} & 5'd14) |
- ({5{(in[13] & (&(~(in[31:14]))))}} & 5'd13) |
- ({5{(in[12] & (&(~(in[31:13]))))}} & 5'd12) |
- ({5{(in[11] & (&(~(in[31:12]))))}} & 5'd11) |
- ({5{(in[10] & (&(~(in[31:11]))))}} & 5'd10) |
- ({5{(in[9] & (&(~(in[31:10]))))}} & 5'd9) |
- ({5{(in[8] & (&(~(in[31:9]))))}} & 5'd8) |
- ({5{(in[7] & (&(~(in[31:8]))))}} & 5'd7) |
- ({5{(in[6] & (&(~(in[31:7]))))}} & 5'd6) |
- ({5{(in[5] & (&(~(in[31:6]))))}} & 5'd5) |
- ({5{(in[4] & (&(~(in[31:5]))))}} & 5'd4) |
- ({5{(in[3] & (&(~(in[31:4]))))}} & 5'd3) |
- ({5{(in[2] & (&(~(in[31:3]))))}} & 5'd2) |
- ({5{(in[1] & (&(~(in[31:2]))))}} & 5'd1) |
- ({5{(in[0] & (&(~(in[31:1]))))}} & 5'd0);
-endmodule
-
-module left_shifter #(parameter mant = 24)
-(
- input wire [mant-1:0] mantisa,
- input wire [7:0] shift_amount,
-
- output wire [mant-1:0] out
-);
-
- wire [mant-1:0] temp;
-
- assign temp = mantisa << shift_amount;
- assign out = {temp[mant-1:1], mantisa[0]};
-
-endmodule
-
-module right_shifter
-(
- input wire [26:0] mantisa,
- input wire [7:0] shift_amount,
-
- output wire [26:0] out
-);
-
- assign out = ({27{(shift_amount[7:0]==8'd0)}} & mantisa) |
- ({27{(shift_amount[7:0]==8'd1)}} & {1'd0, mantisa[26:2], |mantisa[1:0]}) |
- ({27{(shift_amount[7:0]==8'd2)}} & {2'd0, mantisa[26:3], |mantisa[2:0]}) |
- ({27{(shift_amount[7:0]==8'd3)}} & {3'd0, mantisa[26:4], |mantisa[3:0]}) |
- ({27{(shift_amount[7:0]==8'd4)}} & {4'd0, mantisa[26:5], |mantisa[4:0]}) |
- ({27{(shift_amount[7:0]==8'd5)}} & {5'd0, mantisa[26:6], |mantisa[5:0]}) |
- ({27{(shift_amount[7:0]==8'd6)}} & {6'd0, mantisa[26:7], |mantisa[6:0]}) |
- ({27{(shift_amount[7:0]==8'd7)}} & {7'd0, mantisa[26:8], |mantisa[7:0]}) |
- ({27{(shift_amount[7:0]==8'd8)}} & {8'd0, mantisa[26:9], |mantisa[8:0]}) |
- ({27{(shift_amount[7:0]==8'd9)}} & {9'd0, mantisa[26:10], |mantisa[9:0]}) |
- ({27{(shift_amount[7:0]==8'd10)}} & {10'd0, mantisa[26:11], |mantisa[10:0]}) |
- ({27{(shift_amount[7:0]==8'd11)}} & {11'd0, mantisa[26:12], |mantisa[11:0]}) |
- ({27{(shift_amount[7:0]==8'd12)}} & {12'd0, mantisa[26:13], |mantisa[12:0]}) |
- ({27{(shift_amount[7:0]==8'd13)}} & {13'd0, mantisa[26:14], |mantisa[13:0]}) |
- ({27{(shift_amount[7:0]==8'd14)}} & {14'd0, mantisa[26:15], |mantisa[14:0]}) |
- ({27{(shift_amount[7:0]==8'd15)}} & {15'd0, mantisa[26:16], |mantisa[15:0]}) |
- ({27{(shift_amount[7:0]==8'd16)}} & {16'd0, mantisa[26:17], |mantisa[16:0]}) |
- ({27{(shift_amount[7:0]==8'd17)}} & {17'd0, mantisa[26:18], |mantisa[17:0]}) |
- ({27{(shift_amount[7:0]==8'd18)}} & {18'd0, mantisa[26:19], |mantisa[18:0]}) |
- ({27{(shift_amount[7:0]==8'd19)}} & {19'd0, mantisa[26:20], |mantisa[19:0]}) |
- ({27{(shift_amount[7:0]==8'd20)}} & {20'd0, mantisa[26:21], |mantisa[20:0]}) |
- ({27{(shift_amount[7:0]==8'd21)}} & {21'd0, mantisa[26:22], |mantisa[21:0]}) |
- ({27{(shift_amount[7:0]==8'd22)}} & {22'd0, mantisa[26:23], |mantisa[22:0]}) |
- ({27{(shift_amount[7:0]==8'd23)}} & {23'd0, mantisa[26:24], |mantisa[23:0]}) |
- ({27{(shift_amount[7:0]==8'd24)}} & {24'd0, mantisa[26:25], |mantisa[24:0]}) |
- ({27{(shift_amount[7:0]==8'd25)}} & {25'd0, mantisa[26], |mantisa[25:0]}) |
- ({27{(shift_amount[7:0]>=8'd26)}} & {26'd0, |mantisa[26:0]});
-endmodule
-
-module int_excep #(parameter width = 1)
-(
- input wire signed_out,
- input wire is_qNaN,
- input wire is_sNaN,
- input wire sign,
-
- output wire [(width - 1):0] execp_out
-);
- wire max_int;
-
- assign max_int = is_qNaN || is_sNaN || !sign;
- assign execp_out = {signed_out ^ max_int, {(width - 1){max_int}}};
-
-endmodule
-
-module rvdff #( parameter WIDTH=1, SHORT=0 )
- ( input wire [(WIDTH-1):0] din,
- input wire clk,
- input wire rst_l,
-
- output reg [(WIDTH-1):0] dout
- );
-
-if (SHORT == 1) begin
- assign dout = din;
-end
-else begin
-`ifdef RV_CLOCKGATE
- always @(posedge tb_top.clk) begin
- #0 $strobe("CG: %0t %m din %x dout %x clk %b width %d",$time,din,dout,clk,WIDTH);
- end
-`endif
-
- always @(posedge clk or negedge rst_l) begin
- if (rst_l == 0)
- dout[WIDTH-1:0] <= 0;
- else
- dout[WIDTH-1:0] <= din[WIDTH-1:0];
- end
-
-end
-endmodule
-
-module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 )
- (
- input wire [WIDTH-1:0] din,
- input wire en,
- input wire clk,
- input wire rst_l,
- output wire [WIDTH-1:0] dout
- );
-
- wire l1clk;
-
-if (SHORT == 1) begin : genblock
- if (1) begin : genblock
- assign dout = din;
- end
-end
-else begin : genblock
-
-// `ifndef RV_PHYSICAL
-// if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
-// `endif
-
- rvdff #(WIDTH) dff (.din(din), .dout(dout), .rst_l(rst_l), .clk(l1clk));
-
-// `ifndef RV_PHYSICAL
-// end
-// // else
-// // $error("%m: rvdffe must be WIDTH >= 8");
-// `endif
-end // else: !if(SHORT == 1)
-
-endmodule // rvdffe
-
-module exponent #(parameter exp_width = 8, parameter mant_width = 24)
-(
- input wire [(exp_width + mant_width - 1):0] in,
- output wire [(exp_width + mant_width):0] out
-);
-
-function integer clog2;
- input integer a;
-
- begin
- a = a - 1;
- for (clog2 = 0; a > 0; clog2 = clog2 + 1) a = a>>1;
- end
-
-endfunction
-
- localparam norm_dist_width = clog2(mant_width);
-
- wire sign;
- wire exp_in_zero, is_special, mant_in_zero, is_zero;
- wire [(exp_width - 1):0] exp_in;
- wire [(mant_width - 2):0] mant_in, sbnorm_mant;
- wire [exp_width:0] exp_adjusted, exp;
- wire [(norm_dist_width - 1):0] norm_dist;
-
- assign {sign, exp_in, mant_in} = in;
- assign exp_in_zero = (exp_in == 0);
- assign mant_in_zero = (mant_in == 0);
-
- lead_zero_param#(mant_width - 1, norm_dist_width) countLeadingZeros(mant_in, norm_dist);
-
- assign sbnorm_mant = (mant_in<<norm_dist)<<1;
- assign exp_adjusted = (exp_in_zero ? norm_dist ^ ((1<<(exp_width + 1)) - 1) : exp_in) + ((1<<(exp_width - 1)) | (exp_in_zero ? 2 : 1));
- assign is_zero = exp_in_zero && mant_in_zero;
- assign is_special = (exp_adjusted[exp_width:(exp_width - 1)] == 'b11);
-
- assign exp[exp_width:(exp_width - 2)] = is_special ? {2'b11, !mant_in_zero} : is_zero ? 3'b000 : exp_adjusted[exp_width:(exp_width - 2)];
- assign exp[(exp_width - 3):0] = exp_adjusted;
- assign out = {sign, exp, exp_in_zero ? sbnorm_mant : mant_in};
-
-endmodule
-
-module invert#(parameter width = 1)
-(
- input wire [(width - 1):0] in,
- output wire [(width - 1):0] out
-);
- genvar ix;
- generate
- for (ix = 0; ix < width; ix = ix + 1) begin :bt
- assign out[ix] = in[width - 1 - ix];
- end
- endgenerate
-
-endmodule
-
-module low_mask_hi_lo#( parameter in_width = 1, parameter top_bound = 1, parameter bottom_bound = 0 )
-(
- input wire [(in_width - 1):0] in,
- output wire [(top_bound - bottom_bound - 1):0] out
-);
- localparam num_in_vals = 1<<in_width;
- wire signed [num_in_vals:0] c;
- wire [(top_bound - bottom_bound - 1):0] reverse_out;
-
- assign c[num_in_vals] = 1;
- assign c[(num_in_vals - 1):0] = 0;
- assign reverse_out = (c>>>in)>>(num_in_vals - top_bound);
- invert #(top_bound - bottom_bound) reverse_hi(reverse_out, out);
-endmodule
-
-module low_mask_lo_hi#( parameter in_width = 1, parameter top_bound = 0, parameter bottom_bound = 1)
-(
- input wire [(in_width - 1):0] in,
- output wire [(bottom_bound - top_bound - 1):0] out
-);
-
- localparam num_in_vals = 1<<in_width;
- wire signed [num_in_vals:0] c;
- wire [(bottom_bound - top_bound - 1):0] reverse_out;
-
- assign c[num_in_vals] = 1;
- assign c[(num_in_vals - 1):0] = 0;
- assign reverse_out = (c>>>~in)>>(top_bound + 1);
- invert #(bottom_bound - top_bound) reverse_lo(reverse_out, out);
-
-endmodule
-
-module compress_by2#(parameter in_width = 1)
-(
- input wire [(in_width - 1):0] in,
- output wire [((in_width - 1)/2):0] out
-);
-
- localparam bit_num_reduced = (in_width - 1)/2;
-
- genvar ix;
- generate
- for (ix = 0; ix < bit_num_reduced; ix = ix + 1) begin :bt
- assign out[ix] = |in[(ix*2 + 1):ix*2];
- end
- endgenerate
-
- assign out[bit_num_reduced] = |in[(in_width - 1):bit_num_reduced*2];
-endmodule
-
-module compress_by4#(parameter in_width = 1)
-(
- input wire [(in_width - 1):0] in,
- output wire [(in_width - 1)/4:0] out
-);
-
- localparam bit_num_reduced = (in_width - 1)/4;
- genvar ix;
- generate
- for (ix = 0; ix < bit_num_reduced; ix = ix + 1) begin :bt
- assign out[ix] = |in[(ix*4 + 3):ix*4];
- end
- endgenerate
-
- assign out[bit_num_reduced] = |in[(in_width - 1):bit_num_reduced*4];
-endmodule
-
-module lead_zero_param#(parameter in_width = 1, parameter count_width = 1)
-(
- input wire [(in_width - 1):0] in,
- output wire [(count_width - 1):0] count
-);
-
- wire [(in_width - 1):0] reverse_in;
- wire [in_width:0] one_least_reverse_in;
-
- invert #(in_width) reverse_num(in, reverse_in);
- assign one_least_reverse_in = {1'b1, reverse_in} & ({1'b0, ~reverse_in} + 1);
-
- genvar ix;
- generate
- for (ix = 0; ix <= in_width; ix = ix + 1) begin :bt
- wire [(count_width - 1):0] count_so_far;
- if (ix == 0) begin
- assign count_so_far = 0;
- end
- else begin
- assign count_so_far = bt[ix - 1].count_so_far | (one_least_reverse_in[ix] ? ix : 0);
- if (ix == in_width)
- assign count = count_so_far;
- end
- end
- endgenerate
-endmodule
-
-module round_excep#( parameter in_exp_width = 8, parameter in_mant_width = 24, parameter out_exp_width = 8,
- parameter out_mant_width = 24, parameter options = 0 )
-(
- input wire invalid_excep,
- input wire infinite_excep,
- input wire in_is_NaN,
- input wire in_is_inf,
- input wire in_is_zero,
- input wire in_sign,
- input wire signed [(in_exp_width + 1):0] in_sexp,
- input wire [in_mant_width:0] in_mant,
- input wire [2:0] round_mode,
-
- output wire [(out_exp_width + out_mant_width)-1:0] result,
- output wire [4:0] exceptions
-);
-
-function integer clog2;
- input integer a;
-
- begin
- a = a - 1;
- for (clog2 = 0; a > 0; clog2 = clog2 + 1) a = a>>1;
- end
-
-endfunction
-
- localparam sigMSBitAlwaysZero = ((options & `flRoundOpt_sigMSBitAlwaysZero) != 0);
- localparam effectiveInSigWidth = sigMSBitAlwaysZero ? in_mant_width : in_mant_width + 1;
- localparam neverUnderflows = ((options & (`flRoundOpt_neverUnderflows | `flRoundOpt_subnormsAlwaysExact))!= 0)
- || (in_exp_width < out_exp_width);
- localparam neverOverflows = ((options & `flRoundOpt_neverOverflows) != 0) || (in_exp_width < out_exp_width);
- localparam adjustedExpWidth = (in_exp_width < out_exp_width) ? out_exp_width + 1 : (in_exp_width == out_exp_width)?
- in_exp_width + 2 : in_exp_width + 3;
- localparam outNaNExp = 7<<(out_exp_width - 2);
- localparam outInfExp = 6<<(out_exp_width - 2);
- localparam outMaxFiniteExp = outInfExp - 1;
- localparam outMinNormExp = (1<<(out_exp_width - 1)) + 2;
- localparam outMinNonzeroExp = outMinNormExp - out_mant_width + 1;
- localparam [out_exp_width:0] min_norm_exp = (1<<(out_exp_width - 1)) + 2;
- localparam norm_dist_width = clog2(in_mant_width);
-
- wire roundmode_near_even, roundmode_min_mag, roundmode_min, roundmode_max, roundmode_max_mag, round_mag_up;
- wire is_out_NaN;
- wire signed [(adjustedExpWidth - 1):0] adjusted_sexp;
- wire [(out_mant_width + 2):0] adjusted_mant;
- wire notNaN_is_special_inf_out, common_case, overflow, underflow, inexact, sign_out;
- wire overflow_round_magup, peg_min_nonzero_mag_out, peg_max_finite_mag_out, notNaN_is_inf_out;
- wire [out_exp_width:0] exp_out;
- wire [(out_mant_width - 2):0] mant_out;
- wire [(out_exp_width+out_mant_width):0] out;
- wire is_NaN, is_inf, is_zero, sign_res, is_subnorm;
- wire signed [(out_exp_width+1):0] s_exp;
- wire [out_mant_width:0] mant;
- wire [(norm_dist_width - 1):0] subnorm_shift_dist;
- wire [(out_exp_width - 1):0] exp_res;
- wire [(out_mant_width - 2):0] mant_res;
- wire [out_exp_width:0] common_exp_out;
- wire [(out_mant_width - 2):0] common_mant_out;
- wire common_overflow, common_total_underflow, common_underflow;
- wire common_inexact;
- wire do_shift_mant_down1;
-
- assign roundmode_near_even = (round_mode == `round_near_even);
- assign roundmode_min_mag = (round_mode == `round_minMag);
- assign roundmode_min = (round_mode == `round_min);
- assign roundmode_max = (round_mode == `round_max);
- assign roundmode_max_mag = (round_mode == `round_near_maxMag);
- assign round_mag_up = (roundmode_min && in_sign) || (roundmode_max && !in_sign);
-
- assign is_out_NaN = invalid_excep || (!infinite_excep && in_is_NaN);
- assign adjusted_sexp = in_sexp + ((1<<out_exp_width) - (1<<in_exp_width));
-
- assign adjusted_mant = in_mant;
-
- assign do_shift_mant_down1 = sigMSBitAlwaysZero ? 0 : adjusted_mant[out_mant_width + 2];
-
- generate
- if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= out_mant_width) ) begin
- assign common_exp_out = adjusted_sexp + do_shift_mant_down1;
- assign common_mant_out = do_shift_mant_down1 ? adjusted_mant>>3 : adjusted_mant>>2;
- end
- else begin
-
- wire [(out_mant_width + 2):0] roundMask;
-
- if (neverUnderflows) begin
- assign roundMask = {do_shift_mant_down1, 2'b11};
- end
- else begin
- wire [out_mant_width:0] roundMask_main;
-
- low_mask_lo_hi#(out_exp_width + 1,outMinNormExp-out_mant_width-1,outMinNormExp) lowmask_roundmask
- ( adjusted_sexp[out_exp_width:0], roundMask_main );
- assign roundMask = {roundMask_main | do_shift_mant_down1, 2'b11};
- end
-
- wire [(out_mant_width + 2):0] shifted_round_mask, round_pos_mask;
- wire round_pos_bit , any_round_extra, any_round, round_incr;
-
- assign shifted_round_mask = roundMask>>1;
- assign round_pos_mask = ~shifted_round_mask & roundMask;
- assign round_pos_bit = (|(adjusted_mant[(out_mant_width + 2):3] & round_pos_mask[(out_mant_width + 2):3])) || ((|(adjusted_mant[2:0] & round_pos_mask[2:0])));
- assign any_round_extra = (|(adjusted_mant[(out_mant_width + 2):3] & shifted_round_mask[(out_mant_width + 2):3])) || ((|(adjusted_mant[2:0] & shifted_round_mask[2:0])));
- assign any_round = round_pos_bit || any_round_extra;
-
- wire [(out_mant_width + 1):0] rounded_mant;
- wire signed [adjustedExpWidth:0] sext_adjusted_exp,s_rounded_exp;
-
- assign round_incr = ((roundmode_near_even || roundmode_max_mag) && round_pos_bit) || (round_mag_up && any_round);
- assign rounded_mant = round_incr ? (((adjusted_mant | roundMask)>>2) + 1) & ~(roundmode_near_even && round_pos_bit && !any_round_extra
- ? roundMask>>1 : 0) : (adjusted_mant & ~roundMask)>>2;
- assign sext_adjusted_exp = adjusted_sexp;
- assign s_rounded_exp = sext_adjusted_exp + (rounded_mant>>out_mant_width);
-
-
- assign common_exp_out = s_rounded_exp;
- assign common_mant_out = do_shift_mant_down1 ? rounded_mant>>1 : rounded_mant;
- assign common_overflow = neverOverflows ? 0 : (s_rounded_exp>>>(out_exp_width - 1) >= 3);
- assign common_total_underflow = neverUnderflows ? 0 : (s_rounded_exp < outMinNonzeroExp);
-
- wire unbound_range_round_posbit, unbound_range_any_round, unbound_range_round_incr, round_carry ;
-
- assign unbound_range_round_posbit = do_shift_mant_down1 ? adjusted_mant[2] : adjusted_mant[1];
- assign unbound_range_any_round = (do_shift_mant_down1 && adjusted_mant[2]) || (|adjusted_mant[1:0]);
- assign unbound_range_round_incr = ((roundmode_near_even || roundmode_max_mag) && unbound_range_round_posbit)
- || (round_mag_up && unbound_range_any_round);
-
- assign round_carry = do_shift_mant_down1 ? rounded_mant[out_mant_width + 1] : rounded_mant[out_mant_width];
- assign common_underflow = neverUnderflows ? 0 : common_total_underflow || (any_round && (adjusted_sexp>>>out_exp_width <= 0)
- && (do_shift_mant_down1 ? roundMask[3] : roundMask[2]) && !(((`flControl_tininessAfterRounding) != 0)
- && !(do_shift_mant_down1 ? roundMask[4] : roundMask[3]) && round_carry && round_pos_bit
- && unbound_range_round_incr));
- assign common_inexact = common_total_underflow || any_round;
- end
- endgenerate
-
- assign notNaN_is_special_inf_out = infinite_excep || in_is_inf;
- assign common_case = !is_out_NaN && !notNaN_is_special_inf_out && !in_is_zero;
- assign overflow = common_case && common_overflow;
- assign underflow = common_case && common_underflow;
- assign inexact = overflow || (common_case && common_inexact);
-
- assign overflow_round_magup = roundmode_near_even || roundmode_max_mag || round_mag_up;
- assign peg_min_nonzero_mag_out = common_case && common_total_underflow && (round_mag_up);
- assign peg_max_finite_mag_out = overflow && !overflow_round_magup;
- assign notNaN_is_inf_out = notNaN_is_special_inf_out || (overflow && overflow_round_magup);
-
- assign sign_out = is_out_NaN ? `HardFloat_signDefaultNaN : in_sign;
-
- assign exp_out = (common_exp_out & ~(in_is_zero || common_total_underflow ? 7<<(out_exp_width - 2) : 0)
- & ~(peg_min_nonzero_mag_out ? ~outMinNonzeroExp : 0)
- & ~(peg_max_finite_mag_out ? 1<<(out_exp_width - 1) : 0)
- & ~(notNaN_is_inf_out ? 1<<(out_exp_width - 2) : 0))
- | (peg_min_nonzero_mag_out ? outMinNonzeroExp : 0)
- | (peg_max_finite_mag_out ? outMaxFiniteExp : 0)
- | (notNaN_is_inf_out ? outInfExp : 0)
- | (is_out_NaN ? outNaNExp : 0);
-
-
- assign mant_out = (is_out_NaN ? `HardFloat_fractDefaultNaN(out_mant_width) : 0)
- | (!in_is_zero && !common_total_underflow
- ? common_mant_out & `HardFloat_fractDefaultNaN(out_mant_width) : 0)
- | (!is_out_NaN && !in_is_zero && !common_total_underflow
- ? common_mant_out & ~`HardFloat_fractDefaultNaN(out_mant_width): 0)
- | {(out_mant_width - 1){peg_max_finite_mag_out}};
-
-
- assign out = {sign_out, exp_out, mant_out};
- assign exceptions = {invalid_excep, infinite_excep, overflow, underflow, inexact};
-
- mac_spec_check #(out_exp_width, out_mant_width) mac_spec_check_out(.in(out), .is_qNaN(is_NaN), .is_inf(is_inf), .is_zero(is_zero),
- .is_sNaN(), .sign(sign_res), .s_exp(s_exp), .sig(mant));
- assign is_subnorm = (s_exp < min_norm_exp);
-
- assign subnorm_shift_dist = min_norm_exp - 1 - s_exp;
- assign exp_res = (is_subnorm ? 0 : s_exp - min_norm_exp + 1) | (is_NaN || is_inf ? {out_exp_width{1'b1}} : 0);
- assign mant_res = is_subnorm ? (mant>>1)>>subnorm_shift_dist : is_inf ? 0 : mant;
- assign result = {sign_res, exp_res, mant_res};
-
-endmodule
diff --git "a/verilog/rtl/attachments\0501\051/fused_mul.sv" "b/verilog/rtl/attachments\0501\051/fused_mul.sv"
deleted file mode 100644
index 5329299..0000000
--- "a/verilog/rtl/attachments\0501\051/fused_mul.sv"
+++ /dev/null
@@ -1,346 +0,0 @@
-//`include "fpu_lib.sv"
-
-module fused_multiply #(parameter exp_width = 8, parameter mant_width = 24)
-(
- input wire [(exp_width + mant_width)-1:0] a,
- input wire [(exp_width + mant_width)-1:0] b,
- input wire [(exp_width + mant_width)-1:0] c,
- input wire [1:0] op,
- input wire [2:0] round_mode,
-
- output wire [(exp_width + mant_width)-1:0] out,
- output wire [4:0] exceptions
-);
-
-function integer clog2;
- input integer a;
-
- begin
- a = a - 1;
- for (clog2 = 0; a > 0; clog2 = clog2 + 1) a = a>>1;
- end
-
-endfunction
-
- wire invalid_excep, out_is_NaN, out_is_inf, out_is_zero, out_sign;
- wire signed [(exp_width + 1):0] out_s_exp;
- wire [(mant_width + 2):0] out_mant;
- wire [(exp_width + mant_width):0] oper1, oper2, oper3;
-
- exponent #(exp_width, mant_width) exp_a (.in(a), .out(oper1));
- exponent #(exp_width, mant_width) exp_b (.in(b), .out(oper2));
- exponent #(exp_width, mant_width) exp_c (.in(c), .out(oper3));
-
- mul_add #(exp_width, mant_width) mul_add (.op(op), .a(oper1), .b(oper2), .c(oper3), .round_mode(round_mode), .invalid_excep(invalid_excep),
- .out_is_NaN(out_is_NaN), .out_is_inf(out_is_inf), .out_is_zero(out_is_zero), .out_sign(out_sign),
- .out_s_exp(out_s_exp), .out_mant(out_mant) );
-
- round_excep #(exp_width, mant_width+2, exp_width,mant_width,0) round_exception
- ( .invalid_excep(invalid_excep), .infinite_excep(1'b0), .in_is_NaN(out_is_NaN),
- .in_is_inf(out_is_inf), .in_is_zero(out_is_zero),.in_sign(out_sign),.in_sexp(out_s_exp),
- .in_mant(out_mant),.round_mode(round_mode), .result(out), .exceptions(exceptions));
-
-endmodule
-
-module mul_add#(parameter exp_width = 8, parameter mant_width = 24)
-(
- input wire [(exp_width + mant_width):0] a,
- input wire [(exp_width + mant_width):0] b,
- input wire [(exp_width + mant_width):0] c,
- input wire [2:0] round_mode,
- input wire [1:0] op,
-
- output wire invalid_excep,
- output wire out_is_NaN,
- output wire out_is_inf,
- output wire out_is_zero,
- output wire out_sign,
- output wire signed [(exp_width + 1):0] out_s_exp,
- output wire [(mant_width + 2):0] out_mant
-);
-
-function integer clog2;
- input integer a;
-
- begin
- a = a - 1;
- for (clog2 = 0; a > 0; clog2 = clog2 + 1) a = a>>1;
- end
-
-endfunction
-
- wire [(mant_width - 1):0] mul_add_a, mul_add_b;
- wire [(mant_width*2 - 1):0] mul_add_c;
- wire [5:0] intermed_compact_state;
- wire signed [(exp_width + 1):0] intermed_sexp;
- wire [(clog2(mant_width + 1) - 1):0] inter_c_dom_calign_dist;
- wire [(mant_width + 1):0] inter_high_align_sig_c;
- wire [mant_width*2:0] mul_add_res;
-
- mul_add_pre_mul#(exp_width, mant_width) pre_mul(.op(op), .a(a), .b(b), .c(c), .round_mode(round_mode), .mul_add_a(mul_add_a),
- .mul_add_b(mul_add_b), .mul_add_c(mul_add_c), .intermed_compact_state(intermed_compact_state),
- .intermed_sexp(intermed_sexp), .inter_c_dom_calign_dist(inter_c_dom_calign_dist),
- .inter_high_align_sig_c(inter_high_align_sig_c) );
-
- assign mul_add_res = mul_add_a * mul_add_b + mul_add_c;
-
- mul_add_post_mul#(exp_width, mant_width)post_mul(.intermed_compact_state(intermed_compact_state), .intermed_sexp(intermed_sexp),
- .inter_c_dom_calign_dist(inter_c_dom_calign_dist), .inter_high_align_sig_c(inter_high_align_sig_c),
- .mul_add_res(mul_add_res), .round_mode(round_mode), .invalid_excep(invalid_excep),
- .out_is_NaN(out_is_NaN), .out_is_inf(out_is_inf), .out_is_zero(out_is_zero),
- .out_sign(out_sign), .out_s_exp(out_s_exp), .out_mant(out_mant));
-
-endmodule
-
-module mul_add_pre_mul#(parameter exp_width = 8, parameter mant_width = 24)
- (op, a, b, c, round_mode, mul_add_a,
- mul_add_b, mul_add_c, intermed_compact_state,
- intermed_sexp, inter_c_dom_calign_dist,
- inter_high_align_sig_c);
-
-function integer clog2;
- input integer a;
-
- begin
- a = a - 1;
- for (clog2 = 0; a > 0; clog2 = clog2 + 1) a = a>>1;
- end
-
-endfunction
-
- input wire [1:0] op;
- input wire [(exp_width + mant_width):0] a;
- input wire [(exp_width + mant_width):0] b;
- input wire [(exp_width + mant_width):0] c;
- input wire [2:0] round_mode;
-
- output wire [(mant_width - 1):0] mul_add_a;
- output wire [(mant_width - 1):0] mul_add_b;
- output wire [(mant_width*2 - 1):0] mul_add_c;
- output wire [5:0] intermed_compact_state;
- output wire signed [(exp_width + 1):0] intermed_sexp;
- output wire [(clog2(mant_width + 1) - 1):0] inter_c_dom_calign_dist;
- output wire [(mant_width + 1):0] inter_high_align_sig_c;
-
- localparam prod_width = mant_width*2;
- localparam mant_sum_width = mant_width + prod_width + 3;
- localparam c_grain_align = (mant_sum_width - mant_width - 1) & 3;
- localparam c_extra_mask_hi_bound = (mant_sum_width - 1)/4;
- localparam c_extra_mask_lo_bound = (mant_sum_width - mant_width - 1)/4;
-
- wire is_a_qNaN, is_a_inf, is_a_zero, is_a_sNaN, sign_a;
- wire is_b_qNaN, is_b_inf, is_b_zero, is_b_sNaN, sign_b;
- wire is_c_qNaN, is_c_inf, is_c_zero, is_c_sNaN, sign_c;
-
- wire [mant_width:0] mant_a, mant_b, mant_c;
- wire signed [(exp_width + 1):0] sexp_a, sexp_b, sexp_c, sexp_sum;
- wire signed [(exp_width + 2):0] exp_prod_aligned, s_natc_align_dist;
-
- wire sign_prod, sub_mags, op_sign_c, round_mode_min;
- wire is_min_c_align, is_c_dominant, special_sign_out;
- wire reduced_4_c_extra, is_a_orb_NaN, is_any_NaN, is_aorb_inf;
- wire invalid_prod, not_sNaN_invalid_excep, invalid_excep;
- wire not_NaN_add_zeros, special_case, special_notNaN_sign_out ;
-
- wire [(mant_sum_width - 1):0] aligned_mant_c;
- wire [(exp_width + 1):0] pos_nat_c_align_dist;
- wire [(clog2(mant_sum_width) - 1):0] c_align_dist;
- wire signed [(mant_sum_width + 2):0] ext_comp_mant_c;
- wire [(mant_sum_width + 1):0] main_aligned_mant_c;
- wire [(mant_width + c_grain_align):0] grain_aligned_mant_c;
- wire [(mant_width + c_grain_align)/4:0] reduced_4_mant_c;
- wire [(c_extra_mask_hi_bound - c_extra_mask_lo_bound - 1):0] c_extra_mask;
-
- mac_spec_check #(exp_width,mant_width ) mac_spec_check_a (.in (a), .is_qNaN (is_a_qNaN), .is_inf(is_a_inf), .is_zero(is_a_zero),
- .is_sNaN(is_a_sNaN),.sign(sign_a), .s_exp(sexp_a), .sig(mant_a) );
-
- mac_spec_check #(exp_width,mant_width ) mac_spec_check_b (.in (b), .is_qNaN (is_b_qNaN), .is_inf(is_b_inf), .is_zero(is_b_zero),
- .is_sNaN(is_b_sNaN),.sign(sign_b), .s_exp(sexp_b), .sig(mant_b) );
-
- mac_spec_check #(exp_width,mant_width ) mac_spec_check_c (.in(c), .is_qNaN (is_c_qNaN), .is_inf(is_c_inf), .is_zero(is_c_zero),
- .is_sNaN(is_c_sNaN),.sign(sign_c), .s_exp(sexp_c), .sig(mant_c) );
-
- assign sign_prod = sign_a ^ sign_b ^ op[1];
- assign exp_prod_aligned = sexp_a + sexp_b + (-(1<<exp_width) + mant_width + 3);
- assign sub_mags = sign_prod ^ sign_c ^ op[0];
- assign op_sign_c = sign_prod ^ sub_mags;
- assign round_mode_min = (round_mode == `round_min);
-
- assign s_natc_align_dist = exp_prod_aligned - sexp_c;
- assign pos_nat_c_align_dist = s_natc_align_dist[(exp_width + 1):0];
- assign is_min_c_align = is_a_zero || is_b_zero || (s_natc_align_dist < 0);
- assign is_c_dominant = !is_c_zero && (is_min_c_align || (pos_nat_c_align_dist <= mant_width));
- assign sexp_sum = is_c_dominant ? sexp_c : exp_prod_aligned - mant_width;
- assign c_align_dist = is_min_c_align ? 0 : (pos_nat_c_align_dist < mant_sum_width - 1) ?
- pos_nat_c_align_dist[(clog2(mant_sum_width) - 1):0] : mant_sum_width - 1;
- assign ext_comp_mant_c = {sub_mags ? ~mant_c : mant_c, {(mant_sum_width - mant_width + 2){sub_mags}}};
- assign main_aligned_mant_c = ext_comp_mant_c>>>c_align_dist;
- assign grain_aligned_mant_c = mant_c<<c_grain_align;
-
- compress_by4#(mant_width + 1 + c_grain_align) mantc_comp (grain_aligned_mant_c, reduced_4_mant_c);
-
- low_mask_hi_lo#(clog2(mant_sum_width) - 2, c_extra_mask_hi_bound, c_extra_mask_lo_bound)
- extra_mask_c(c_align_dist[(clog2(mant_sum_width) - 1):2], c_extra_mask);
-
- assign reduced_4_c_extra = |(reduced_4_mant_c & c_extra_mask);
- assign aligned_mant_c = {main_aligned_mant_c>>3, sub_mags ? (&main_aligned_mant_c[2:0])
- && !reduced_4_c_extra : (|main_aligned_mant_c[2:0]) || reduced_4_c_extra};
-
- assign is_a_orb_NaN = is_a_qNaN || is_b_qNaN;
- assign is_any_NaN = is_a_orb_NaN || is_c_qNaN;
- assign is_aorb_inf = is_a_inf || is_b_inf;
- assign invalid_prod = (is_a_inf && is_b_zero) || (is_a_zero && is_b_inf);
- assign not_sNaN_invalid_excep = invalid_prod || (!is_a_orb_NaN && is_aorb_inf && is_c_inf && sub_mags);
- assign invalid_excep = is_a_sNaN || is_b_sNaN || is_c_sNaN || not_sNaN_invalid_excep;
- assign not_NaN_add_zeros = (is_a_zero || is_b_zero) && is_c_zero;
- assign special_case = is_any_NaN || is_aorb_inf || is_c_inf || not_NaN_add_zeros;
- assign special_notNaN_sign_out= (is_aorb_inf && sign_prod) || (is_c_inf && op_sign_c) || (not_NaN_add_zeros &&
- !round_mode_min && sign_prod && op_sign_c) || (not_NaN_add_zeros
- && round_mode_min && (sign_prod || op_sign_c));
-
- assign special_sign_out = special_notNaN_sign_out;
- assign mul_add_a = mant_a;
- assign mul_add_b = mant_b;
- assign mul_add_c = aligned_mant_c[prod_width:1];
- assign intermed_compact_state = {special_case, invalid_excep || (!special_case && sign_prod ),
- is_any_NaN || (!special_case && sub_mags ),
- is_aorb_inf || is_c_inf || (!special_case && is_c_dominant ),
- not_NaN_add_zeros || (!special_case && aligned_mant_c[0]),
- special_sign_out};
- assign intermed_sexp = sexp_sum;
- assign inter_c_dom_calign_dist= c_align_dist[(clog2(mant_width + 1) - 1):0];
- assign inter_high_align_sig_c = aligned_mant_c[(mant_sum_width - 1):(prod_width + 1)];
-
-endmodule
-
-module mul_add_post_mul#(parameter exp_width = 8, parameter mant_width = 24)
-( intermed_compact_state, intermed_sexp, inter_c_dom_calign_dist,
- inter_high_align_sig_c, mul_add_res, round_mode, invalid_excep,
- out_is_NaN, out_is_inf, out_is_zero, out_sign, out_s_exp, out_mant);
-
-function integer clog2;
- input integer a;
-
- begin
- a = a - 1;
- for (clog2 = 0; a > 0; clog2 = clog2 + 1) a = a>>1;
- end
-
-endfunction
-
- input wire [5:0] intermed_compact_state;
- input wire signed [(exp_width + 1):0] intermed_sexp;
- input wire [(clog2(mant_width + 1) - 1):0] inter_c_dom_calign_dist;
- input wire [(mant_width + 1):0] inter_high_align_sig_c;
- input wire [mant_width*2:0] mul_add_res;
- input wire [2:0] round_mode;
-
- output wire invalid_excep;
- output wire out_is_NaN;
- output wire out_is_inf;
- output wire out_is_zero;
- output wire out_sign;
- output wire signed [(exp_width + 1):0] out_s_exp;
- output wire [(mant_width + 2):0] out_mant;
-
- localparam prod_width = mant_width*2;
- localparam mant_sum_width = mant_width + prod_width + 3;
-
- wire special_case, special_sign_out;
- wire not_NaN_add_zeros, bit0AlignedSigC;
- wire sign_prod, sub_mags, is_c_dominant;
- wire op_sign_c, round_mode_min, c_dom_sign;
- wire [(mant_width + 1):0] inc_high_aligned_mant_c;
- wire [(mant_sum_width - 1):0] mant_sum;
- wire signed [(exp_width + 1):0] c_dom_sexp;
- wire [(mant_width*2 + 1):0] c_dom_abs_mant_sum;
- wire c_dom_abs_mant_sum_extra;
- wire [(mant_width + 4):0] c_dom_main_mant;
- wire [((mant_width | 3) - 1):0] c_dom_grain_align_low_mant;
- wire [mant_width/4:0] c_dom_reduce_4_low_mant;
- wire [(mant_width/4 - 1):0] cdom_mant_extra_mask;
- wire cdom_reduced_4_mant_extra;
- wire [(mant_width + 2):0] cdom_mant;
- wire not_cdom_mant_sum_sign;
- wire [(prod_width + 2):0] not_cdom_abs_mant_sum;
- wire [(prod_width + 2)/2:0] not_cdom_reduced2_abs_mant_sum;
- wire [(clog2(prod_width + 4) - 2):0] not_cdom_norm_dist_reduced2;
- wire [(clog2(prod_width + 4) - 1):0] not_cdom_near_norm_dist;
- wire signed [(exp_width + 1):0] not_cdom_sexp;
- wire [(mant_width + 4):0] not_cdom_main_mant;
- wire [(((mant_width/2 + 1) | 1) - 1):0] cdom_grain_aligned_low_reduced2_mant;
- wire [(mant_width + 2)/4:0] not_cdom_reduced4_abs_mant_sum;
- wire [((mant_width + 2)/4 - 1):0] not_cdom_mant_extra_mask;
- wire not_cdom_reduced4_mant_extra;
- wire [(mant_width + 2):0] not_cdom_mant;
- wire not_cdom_complete_cancel,not_cdom_sign;
-
- assign special_case = intermed_compact_state[5];
- assign invalid_excep = special_case && intermed_compact_state[4];
- assign out_is_NaN = special_case && intermed_compact_state[3];
- assign out_is_inf = special_case && intermed_compact_state[2];
- assign not_NaN_add_zeros = special_case && intermed_compact_state[1];
- assign sign_prod = intermed_compact_state[4];
- assign sub_mags = intermed_compact_state[3];
- assign is_c_dominant = intermed_compact_state[2];
- assign bit0AlignedSigC = intermed_compact_state[1];
- assign special_sign_out = intermed_compact_state[0];
- assign op_sign_c = sign_prod ^ sub_mags;
-
- assign inc_high_aligned_mant_c = inter_high_align_sig_c + 1;
- assign mant_sum = {mul_add_res[prod_width] ? inc_high_aligned_mant_c : inter_high_align_sig_c,
- mul_add_res[(prod_width - 1):0], bit0AlignedSigC};
- assign round_mode_min = (round_mode == `round_min);
- assign c_dom_sign = op_sign_c;
- assign c_dom_sexp = intermed_sexp - sub_mags;
- assign c_dom_abs_mant_sum = sub_mags ? ~mant_sum[(mant_sum_width - 1):(mant_width + 1)] :
- {1'b0, inter_high_align_sig_c[(mant_width + 1):mant_width],
- mant_sum[(mant_sum_width - 3):(mant_width + 2)]};
-
- assign c_dom_abs_mant_sum_extra = sub_mags ? !(&mant_sum[mant_width:1]) : |mant_sum[(mant_width + 1):1];
- assign c_dom_main_mant = (c_dom_abs_mant_sum<<inter_c_dom_calign_dist)>>(mant_width - 3);
- assign c_dom_grain_align_low_mant = c_dom_abs_mant_sum[(mant_width - 1):0]<<(~mant_width & 3);
-
- compress_by4#(mant_width | 3) cdom_abs_mant_sum( c_dom_grain_align_low_mant, c_dom_reduce_4_low_mant);
-
- low_mask_lo_hi#(clog2(mant_width + 1) - 2, 0, mant_width/4) lowMask_CDom_sigExtraMask
- (inter_c_dom_calign_dist[(clog2(mant_width + 1) - 1):2], cdom_mant_extra_mask );
-
- assign cdom_reduced_4_mant_extra = |(c_dom_reduce_4_low_mant & cdom_mant_extra_mask);
- assign cdom_mant = {c_dom_main_mant>>3, (|c_dom_main_mant[2:0]) || cdom_reduced_4_mant_extra
- || c_dom_abs_mant_sum_extra};
-
- assign not_cdom_mant_sum_sign = mant_sum[prod_width + 3];
- assign not_cdom_abs_mant_sum = not_cdom_mant_sum_sign ? ~mant_sum[(prod_width + 2):0] :
- mant_sum[(prod_width + 2):0] + sub_mags;
-
- compress_by2#(prod_width + 3) not_cdom_mant_sum( not_cdom_abs_mant_sum, not_cdom_reduced2_abs_mant_sum);
-
- lead_zero_param#((prod_width + 2)/2 + 1, clog2(prod_width + 4) - 1) leading_zeros
- (not_cdom_reduced2_abs_mant_sum, not_cdom_norm_dist_reduced2);
-
- assign not_cdom_near_norm_dist = not_cdom_norm_dist_reduced2<<1;
- assign not_cdom_sexp = intermed_sexp - not_cdom_near_norm_dist;
- assign not_cdom_main_mant = ({1'b0, not_cdom_abs_mant_sum}<<not_cdom_near_norm_dist)>>(mant_width-1);
- assign cdom_grain_aligned_low_reduced2_mant = not_cdom_reduced2_abs_mant_sum[mant_width/2:0]<<((mant_width/2) & 1);
-
-
- compress_by2#((mant_width/2 + 1) | 1) not_cdom_reduced2_absmantsum
- (cdom_grain_aligned_low_reduced2_mant, not_cdom_reduced4_abs_mant_sum);
-
- low_mask_lo_hi#(clog2(prod_width + 4)-2,0,(mant_width + 2)/4) not_cdom_mant_mask
- (not_cdom_norm_dist_reduced2[(clog2(prod_width + 4) - 2):1], not_cdom_mant_extra_mask );
-
- assign not_cdom_reduced4_mant_extra = |(not_cdom_reduced4_abs_mant_sum & not_cdom_mant_extra_mask);
- assign not_cdom_mant = {not_cdom_main_mant>>3, (|not_cdom_main_mant[2:0]) || not_cdom_reduced4_mant_extra};
- assign not_cdom_complete_cancel = (not_cdom_mant[(mant_width + 2):(mant_width + 1)] == 0);
- assign not_cdom_sign = not_cdom_complete_cancel ? round_mode_min : sign_prod ^ not_cdom_mant_sum_sign;
-
- assign out_is_zero = not_NaN_add_zeros || (!is_c_dominant && not_cdom_complete_cancel);
- assign out_sign = (special_case && special_sign_out) || (!special_case && is_c_dominant && c_dom_sign)
- || (!special_case && !is_c_dominant && not_cdom_sign );
- assign out_s_exp = is_c_dominant ? c_dom_sexp : not_cdom_sexp;
-
- assign out_mant = is_c_dominant ? cdom_mant : not_cdom_mant;
-
-endmodule
diff --git "a/verilog/rtl/attachments\0501\051/int_to_float.sv" "b/verilog/rtl/attachments\0501\051/int_to_float.sv"
deleted file mode 100644
index 5b7153d..0000000
--- "a/verilog/rtl/attachments\0501\051/int_to_float.sv"
+++ /dev/null
@@ -1,65 +0,0 @@
-//`include "fpu_lib.sv"
-
-module int_to_float #(parameter int_width = 32, parameter exp_width = 8, parameter sig_width = 24)
-(
-// if number is negative signed_in should be 1
- input wire signed_in,
- input wire [(int_width-1):0] num,
- input wire [2:0] round_mode,
-
- output wire [(exp_width+sig_width)-1:0] out,
- output wire [4:0] exceptions
-);
- wire sign;
- wire is_zero,rounding_overflow;
-
- wire [4:0] index, shift_amount;
- wire [22:0] mantissa;
- wire [7:0] exp;
- wire [31:0] shifted_num;
- wire [26:0] mant;
- wire [23:0] rounded_mantissa;
- wire [31:0] new_num;
- wire invalid;
- wire div_by_zero;
- wire overflow;
- wire underflow;
- wire inexact;
-
-// check if input number is zero
- assign is_zero = !(|num);
-// determining sign of result
- assign sign = signed_in && num[int_width-1];
- assign new_num = sign ? -num : num;
-
-// position of leading one
- leading_ones lead_one ( .in (new_num), .out (index));
-
-// calculating shift amount of the basis of leading one
- assign shift_amount = 5'd31 - index;
-// shifting number
- assign shifted_num = new_num << shift_amount;
-
-// compress number to 27 bits
- assign mant = {shifted_num[31:6], |shifted_num[5:0]};
-
-// rounding the number
- rounding rounder(.sign(sign), .mantisa(mant), .round_mode(round_mode), .rounded_mantisa(rounded_mantissa), .rounding_overflow(rounding_overflow));
-
-// exponent of the result
- assign exp = index + 8'd127 + rounding_overflow;
-// mantissa of the result
- assign mantissa = rounded_mantissa[22:0];
-// final result
- assign out = is_zero ? {32'd0} : {sign, exp, mantissa};
-
-// redundant exceptions
- assign invalid = 1'b0;
- assign div_by_zero = 1'b0;
- assign overflow = 1'b0;
- assign underflow = 1'b0;
-// inexact result flag
- assign inexact = |mant[2:0];
- assign exceptions = {invalid, div_by_zero, overflow, underflow, inexact};
-
-endmodule
diff --git "a/verilog/rtl/attachments\0501\051/macro.cfg" "b/verilog/rtl/attachments\0501\051/macro.cfg"
deleted file mode 100644
index 7e0ebba..0000000
--- "a/verilog/rtl/attachments\0501\051/macro.cfg"
+++ /dev/null
@@ -1 +0,0 @@
-mprj 1085 1435 N
diff --git "a/verilog/rtl/attachments\0501\051/min_max.sv" "b/verilog/rtl/attachments\0501\051/min_max.sv"
deleted file mode 100644
index 5c10b41..0000000
--- "a/verilog/rtl/attachments\0501\051/min_max.sv"
+++ /dev/null
@@ -1,48 +0,0 @@
-module min_max#(parameter exp_width = 8, parameter mant_width = 24)
-(
- input wire [(exp_width + mant_width)-1:0] a,
- input wire [(exp_width + mant_width)-1:0] b,
- input wire op, // 1 will return max, 0 will return min
-
- output wire [(exp_width + mant_width)-1:0] out,
- output wire [4:0] exceptions
-);
-
- wire [(exp_width + mant_width)-1:0] max, min, qnan, snan;
- wire [9:0] check_a, check_b;
- wire comp, both_zero, a_nan, b_nan;
- wire pos_comp;
- wire invalid;
-
- special_check #(exp_width, mant_width) spec_check_a (.in(a), .result(check_a));
- special_check #(exp_width, mant_width) spec_check_b (.in(b), .result(check_b));
-
- assign both_zero = (check_a [3] | check_a [4]) & (check_b [3] | check_b [4]) ;
-
- assign pos_comp = (a[(exp_width + mant_width)-2:mant_width-1] == b[(exp_width + mant_width)-2:mant_width-1]) ?
- (a[mant_width-2:0] < b[mant_width-2:0]) : (a[(exp_width + mant_width)-2:mant_width-1] <
- b[(exp_width + mant_width)-2:mant_width-1]);
-
- assign comp = (check_a[1] | check_a[2] | check_a[3]) & (check_b[5] | check_b[6] | check_b[4]) ? 1'b1 :
- (check_b[1] | check_b[2] | check_b[3]) & (check_a[5] | check_a[6] | check_a[4]) ? 1'b0 :
- (check_a[1] | check_a[2] | check_a[3]) & (check_b[1] | check_b[2] | check_b[3]) ? !pos_comp : pos_comp;
-
-
- assign max = (both_zero & check_a[4]) ? a : (both_zero & check_a[3]) ? b : check_a[7] ? a : check_a[0] ?
- b : check_b[0] ? a : comp ? b : a;
-
- assign min = (both_zero & check_a[4]) ? b : (both_zero & check_a[3]) ? a : check_a[7] ? b : check_a[0] ?
- a : check_b[0] ? b : comp ? a : b;
-
- assign qnan = 32'h7fc00000;
-
- assign invalid = check_a[8] || check_b[8];
-
- assign out = (((check_a[9] && check_b[9]) | (check_a[8] && check_b[8]) | (check_a[8] & check_b[9]) | (check_a[9] & check_b[8]))
- ? qnan :((check_a[9] | check_a[8]) ? b : ((check_b[9] | check_b[8]) ? a : (op ? max : min))));
-
- assign exceptions = {invalid, 4'b0};
-
-endmodule
-
-
diff --git "a/verilog/rtl/attachments\0501\051/multiplier.sv" "b/verilog/rtl/attachments\0501\051/multiplier.sv"
deleted file mode 100644
index b4a6e5f..0000000
--- "a/verilog/rtl/attachments\0501\051/multiplier.sv"
+++ /dev/null
@@ -1,98 +0,0 @@
-//`include "fpu_lib.sv"
-module multiplier #(parameter exp_width = 8, parameter mant_width = 24)
-(
- input wire [(exp_width + mant_width-1):0] a,
- input wire [(exp_width + mant_width-1):0] b,
- input wire [2:0] round_mode,
-
- output wire [4:0] exceptions,
- output wire [(exp_width + mant_width)-1:0] out
-);
-
- localparam norm_dis_width = 5;
-
- wire sign_a, sign_b, sign_res;
- wire exp_a_zero, mant_a_zero, exp_b_zero, mant_b_zero;
- wire is_a_zero , is_a_special,is_b_zero , is_b_special;
- wire is_out_inf, is_out_zero, is_out_NaN;
- wire invalid_excep, infinite_excep;
-
- wire [9:0] check_a, check_b;
- wire [exp_width:0] adj_exp_a, adj_exp_b;
- wire [exp_width:0] expa, expb;
- wire [(exp_width-1):0] exp_a, exp_b;
- wire [(mant_width-2):0] mant_a, mant_b;
- wire [(mant_width-2):0] subnorm_mant_a, subnorm_mant_b;
- wire [(norm_dis_width - 1):0] norm_dist_a, norm_dist_b;
- wire [(exp_width+mant_width):0] oper1, oper2;
-
- wire sign_oper1, sign_oper2;
- wire [exp_width:0] exp_oper1, exp_oper2;
- wire [(mant_width-2):0] mant_oper1, mant_oper2;
- wire [mant_width:0] mant_1, mant_2;
- wire signed [(exp_width+1):0] sexp_1, sexp_2;
- wire signed [(exp_width+1):0] exp_unbais;
- wire [(mant_width*2-1):0] mant_prod;
- wire [(mant_width+2):0] prod_comp;
- wire is_zero_oper1, is_zero_oper2;
-
-
- assign {sign_a, exp_a, mant_a} = a;
- assign {sign_b, exp_b, mant_b} = b;
-
- special_check #(exp_width, mant_width) spec_check_a (.in(a), .result(check_a));
- special_check #(exp_width, mant_width) spec_check_b (.in(b), .result(check_b));
-
- assign exp_a_zero = (exp_a == 0);
- assign exp_b_zero = (exp_b == 0);
- assign mant_a_zero = (mant_a == 0);
- assign mant_b_zero = (mant_b == 0);
-
- lead_zero_param #(mant_width-1, norm_dis_width) norm_a (mant_a, norm_dist_a);
- lead_zero_param #(mant_width-1, norm_dis_width) norm_b (mant_b, norm_dist_b);
-
- assign subnorm_mant_a = (mant_a<<norm_dist_a)<<1;
- assign subnorm_mant_b = (mant_b<<norm_dist_b)<<1;
- assign adj_exp_a = (exp_a_zero ? norm_dist_a ^ ((1<<(exp_width + 1)) - 1) : exp_a)
- + ((1<<(exp_width - 1)) | (exp_a_zero ? 2 : 1));
- assign adj_exp_b = (exp_b_zero ? norm_dist_b ^ ((1<<(exp_width + 1)) - 1) : exp_b)
- + ((1<<(exp_width - 1)) | (exp_b_zero ? 2 : 1));
- assign is_a_zero = exp_a_zero && mant_a_zero;
- assign is_b_zero = exp_b_zero && mant_b_zero;
- assign is_a_special = (adj_exp_a[exp_width:(exp_width - 1)] == 'b11);
- assign is_b_special = (adj_exp_b[exp_width:(exp_width - 1)] == 'b11);
- assign expa[exp_width:(exp_width-2)] = is_a_special ? {2'b11, !mant_a_zero} : is_a_zero ? 3'b000
- : adj_exp_a[exp_width:(exp_width - 2)];
- assign expa[(exp_width - 3):0] = adj_exp_a;
- assign expb[exp_width:(exp_width-2)] = is_b_special ? {2'b11, !mant_b_zero} : is_b_zero ? 3'b000
- : adj_exp_b[exp_width:(exp_width - 2)];
- assign expb[(exp_width - 3):0] = adj_exp_b;
- assign oper1 = {sign_a, expa, exp_a_zero ? subnorm_mant_a : mant_a};
- assign oper2 = {sign_b, expb, exp_b_zero ? subnorm_mant_b : mant_b};
-
- assign {sign_oper1, exp_oper1, mant_oper1} = oper1;
- assign {sign_oper2, exp_oper2, mant_oper2} = oper2;
- assign is_zero_oper1 = (exp_oper1>>(exp_width - 2) == 'b000);
- assign is_zero_oper2 = (exp_oper2>>(exp_width - 2) == 'b000);
- assign sexp_1 = exp_oper1;
- assign sexp_2 = exp_oper2;
- assign mant_1 = {1'b0, !is_zero_oper1, mant_oper1};
- assign mant_2 = {1'b0, !is_zero_oper2, mant_oper2};
-
- assign infinite_excep = 1'b0;
- assign invalid_excep = check_a[8] || check_b [8] || ((check_a[7] || check_a[0])
- && (check_b[4] || check_b [3])) || ((check_b[7] || check_b[0])
- && (check_a[4] || check_a[3]));
- assign is_out_inf = check_a[7] || check_a[0] || check_b[7] || check_b [0];
- assign is_out_zero = check_a[4] || check_a[3] || check_b[4] || check_b [3];
- assign is_out_NaN = check_a[9] || check_b[9];
- assign sign_res = sign_a ^ sign_b;
- assign exp_unbais = sexp_1 + sexp_2 - (1<<exp_width);
- assign mant_prod = mant_1 * mant_2;
- assign prod_comp = {mant_prod[(mant_width*2 - 1):(mant_width - 2)], |mant_prod[(mant_width - 3):0]};
-
- round_excep #(exp_width, mant_width+2, exp_width,mant_width,0) round_exception
- ( .invalid_excep(invalid_excep), .infinite_excep(infinite_excep), .in_is_NaN(is_out_NaN),
- .in_is_inf(is_out_inf), .in_is_zero(is_out_zero),.in_sign(sign_res),.in_sexp(exp_unbais),
- .in_mant(prod_comp),.round_mode(round_mode), .result(out), .exceptions(exceptions));
-endmodule
diff --git "a/verilog/rtl/attachments\0501\051/registers.sv" "b/verilog/rtl/attachments\0501\051/registers.sv"
deleted file mode 100644
index f460269..0000000
--- "a/verilog/rtl/attachments\0501\051/registers.sv"
+++ /dev/null
@@ -1,192 +0,0 @@
-module fpu_registers(
- input wire clk,
- input wire rst_l,
- input wire [31:0] fpu_result,
- input wire [12:0] fpu_valids,
- input wire [31:0] addr,
- input wire wren,
- input wire [31:0] wrdata,
- input wire [4:0] exceptions,
-
- output wire inter_gen,
- output wire [31:0] rddata,
- output wire [31:0] opA,
- output wire [31:0] opB,
- output wire [31:0] opC,
- output wire [2:0] frm,
-
- output wire [12:0] op_valids
-);
-
- localparam base_addr = 32'h3000_0000;
-
- wire fpu_result_valid;
-
- assign fpu_result_valid = |fpu_valids[12:2];
-
- // ----------------------------------------------------------------------
- // OPERAND_A (RW)
- // [31:0] OPERAND_A
- localparam OPERAND_A = base_addr + 8'h00;
-
- wire addr_A;
- wire wr_opA;
- wire [31:0] opA_ns;
-
- assign addr_A = (addr[31:0] == OPERAND_A);
- assign wr_opA = wren && addr_A;
- assign opA_ns = wrdata;
-
- rvdffe #(32) opA_ff (.clk(clk), .en(wr_opA), .din(opA_ns), .dout(opA));
-
-
- // ----------------------------------------------------------------------
- // OPERAND_B (RW)
- // [31:0] OPERAND_B
- localparam OPERAND_B = base_addr + 8'h04;
-
- wire addr_B;
- wire wr_opB;
- wire [31:0] opB_ns;
-
- assign addr_B = (addr[31:0] == OPERAND_B);
- assign wr_opB = wren && addr_B;
- assign opB_ns = wrdata;
-
- rvdffe #(32) opB_ff (.clk(clk), .en(wr_opB), .din(opB_ns), .dout(opB));
-
-
- // ----------------------------------------------------------------------
- // OPERAND_C (RW)
- // [31:0] OPERAND_C
- localparam OPERAND_C = base_addr + 8'h08;
-
- wire addr_C;
- wire wr_opC;
- wire [31:0] opC_ns;
-
- assign addr_C = (addr[31:0] == OPERAND_C);
- assign wr_opC = wren && addr_C;
- assign opC_ns = wrdata;
-
- rvdffe #(32) opC_ff (.clk(clk), .en(wr_opC), .din(opC_ns), .dout(opC));
-
-
- // ----------------------------------------------------------------------
- // RESULT (RW)
- // [31:0] RESULT
- localparam RESULT = base_addr + 8'h0C;
-
- wire addr_result;
- wire wr_result;
- wire [31:0] result_ns;
- wire [31:0] result;
-
- assign addr_result = (addr[31:0] == RESULT);
- assign wr_result = fpu_result_valid;
- assign result_ns = fpu_result;
-
- rvdffe #(32) result_ff (.clk(clk), .en(wr_result), .din(result_ns), .dout(result));
-
-
- // ----------------------------------------------------------------------
- // OPERATION_COMPLETED (RW)
- // [1:0] op
- // [14:2] operation_in_flight
- // [31:15] reserved
- localparam OPERATION_COMPLETED = base_addr + 8'h10;
-
- wire addr_op_comp;
- wire wr_op_comp;
- wire [12:0] op_comp_ns;
- wire [12:0] op_comp;
-
- assign addr_op_comp = (addr[31:0] == OPERATION_COMPLETED);
- assign wr_op_comp = fpu_result_valid;
- assign op_comp_ns = fpu_valids;
-
- rvdffe #(13) op_comp_ff (.clk(clk), .en(wr_op_comp), .din(op_comp_ns), .dout(op_comp));
-
-
- // ----------------------------------------------------------------------
- // INTERRUPT_GENERATION (RC)
- // [0] operation done
- // [31:1] reserved
- localparam INTERRUPT_GENERATION = base_addr + 8'h14;
-
- wire addr_intr_gen;
- wire wr_intr_gen;
- wire intr_gen_ns;
- //wire inter_gen;
-
- assign addr_intr_gen = (addr[31:0] == INTERRUPT_GENERATION);
- assign wr_intr_gen = (addr_intr_gen && !wren) || fpu_result_valid;
- assign intr_gen_ns = (addr_intr_gen && !wren) ? 1'b0 : (fpu_result_valid ? 1'b1 : inter_gen);
-
- rvdffe #(1) intr_gen_ff (.clk(clk), .en(wr_intr_gen), .din(intr_gen_ns), .dout(inter_gen));
-
-
- // ----------------------------------------------------------------------
- // OPERATION (RW)
- // [1:0] op
- // [14:2] operation_in_flight
- // [31:15] reserved
- localparam OPERATION = base_addr + 8'h1C;
-
- wire addr_op;
- wire wr_op;
- wire [12:0] op_ns;
-
- assign addr_op = (addr[31:0] == OPERATION);
- assign wr_op = addr_op && wren;
- assign op_ns = wrdata;
-
- rvdffe #(13) op_ff (.clk(clk), .en(wr_op), .din(op_ns), .dout(op_valids));
-
-
- // ----------------------------------------------------------------------
- // FCSR (RW)
- // [7:5] frm - rounding mode
- // [4:0] fflags - accrued exceptions
- localparam FFLAGS = base_addr + 8'h20;
- localparam FRM = base_addr + 8'h24;
- localparam FCSR = base_addr + 8'h28;
-
- wire [4:0] fflags;
- wire [4:0] fflags_ns;
- wire [2:0] frm_ns;
- wire [7:0] fcsr_read;
- wire frm_addr;
- wire fflags_addr;
- wire fcsr_addr;
- wire wr_fflags_r;
- wire wr_frm_r;
- wire wr_fcsr_r;
-
- assign frm_addr = (addr == FRM);
- assign fflags_addr = (addr == FFLAGS);
- assign fcsr_addr = (addr == FCSR);
- assign wr_fflags_r = wren && fflags_addr;
- assign wr_frm_r = wren && frm_addr;
- assign wr_fcsr_r = wren && fcsr_addr;
-
- assign fflags_ns = fpu_result_valid ? exceptions[4:0] : wrdata;
- assign frm_ns = frm_addr ? wrdata[2:0] : wrdata[7:5];
-
- rvdffe #(5) fflags_ff (.clk(clk), .en(wr_fflags_r | wr_fcsr_r), .din(fflags_ns[4:0]), .dout(fflags[4:0]));
- rvdffe #(3) frm_ff (.clk(clk), .en(wr_frm_r | wr_fcsr_r), .din(frm_ns[2:0]), .dout(frm[2:0]));
-
- assign fcsr_read = {frm, fflags};
-
- assign rddata = ({32{addr_A}} & opA) |
- ({32{addr_B}} & opB) |
- ({32{addr_C}} & opC) |
- ({32{addr_result}} & result) |
- ({32{addr_op_comp}} & {19'b0, op_comp}) |
- ({32{addr_intr_gen}} & {31'b0, inter_gen}) |
- ({32{addr_op}} & {19'b0, op_valids}) |
- ({32{frm_addr}} & {29'b0, frm}) |
- ({32{fflags_addr}} & {27'b0, fflags}) |
- ({32{fcsr_addr}} & {24'b0, fcsr_read});
-
-endmodule
diff --git "a/verilog/rtl/attachments\0501\051/sign_inject.sv" "b/verilog/rtl/attachments\0501\051/sign_inject.sv"
deleted file mode 100644
index 86f4475..0000000
--- "a/verilog/rtl/attachments\0501\051/sign_inject.sv"
+++ /dev/null
@@ -1,23 +0,0 @@
-module sign_inject#(parameter exp_width = 8, parameter mant_width = 24)
-(
- input wire [(exp_width + mant_width)-1:0] a,
- input wire [(exp_width + mant_width)-1:0] b,
- input wire [1:0] op,
-
- output wire [(exp_width + mant_width)-1:0] out
-);
-
- wire sign_a, sign_b;
- wire [exp_width-1:0] exp_a , exp_b;
- wire [mant_width-2:0] mant_a, mant_b;
-
- assign {sign_a, exp_a, mant_a} = a;
- assign {sign_b, exp_b, mant_b} = b;
-
- assign out = ({32{op == 2'b00}} & {sign_b, exp_a, mant_a}) |
- ({32{op == 2'b01}} & {!sign_b, exp_a, mant_a}) |
- ({32{op == 2'b10}} & {sign_a^sign_b, exp_a, mant_a});
-
-
-endmodule
-
diff --git "a/verilog/rtl/attachments\0501\051/sqrt_fpu.sv" "b/verilog/rtl/attachments\0501\051/sqrt_fpu.sv"
deleted file mode 100644
index b511f33..0000000
--- "a/verilog/rtl/attachments\0501\051/sqrt_fpu.sv"
+++ /dev/null
@@ -1,140 +0,0 @@
-//`include "fpu_lib.sv"
-
-module sqrt #( parameter exp_width = 8, parameter mant_width = 24, parameter options = 0)
-(
- input wire clk,
- input wire rst_l,
- input wire in_valid,
- input wire [(exp_width + mant_width)-1:0] a,
- input wire [2:0] round_mode,
- input wire cancel,
-
- output wire in_ready,
- output wire out_valid,
- output wire [(exp_width + mant_width)-1:0] out,
- output wire [4:0] exceptions
-);
-
-function integer clog2;
- input integer a;
-
- begin
- a = a - 1;
- for (clog2 = 0; a > 0; clog2 = clog2 + 1) a = a>>1;
- end
-
-endfunction
-
- wire is_a_qNaN, is_a_inf, is_a_zero, is_a_sNaN, sign_a;
- wire signed [(exp_width + 1):0] sexp_a;
- wire [mant_width:0] mant_a;
- wire not_sNaN_inval_excep, major_excep;
- wire is_res_NaN, is_res_inf, is_res_zero, sign_res;
- wire special_case_a, normal_case_sqrt, normal_case_s;
- wire even_sqrt, odd_sqrt;
- wire [(clog2(mant_width + 3) - 1):0] cycle_num, cycle_num_in;
- wire major_exc_z, not_zero_rem_z;
- wire is_NaN_z, is_inf_z, is_zero_z, sign_z;
- wire signed [(exp_width + 1):0] sexp_z, sexp_z_in;
- wire [(mant_width - 2):0] mant_b_z;
- wire [2:0] round_mode_z;
- wire [(mant_width + 1):0] rem_z, rem_z_in;
- wire [(mant_width + 1):0] mantx_z, mantx_z_in;
- wire idle, entering, entering_norm_case, skip_cycle_2;
-
- wire [1:0] dec_hi_mant_a;
- wire [(mant_width + 2):0] rem;
- wire [mant_width:0] bit_mask;
- wire [(mant_width + 1):0] trail_term;
- wire signed [(mant_width + 3):0] trail_rem;
- wire new_bit;
- wire [2:0] round_mode_out;
- wire invalid_excep;
- wire infinite_excep;
- wire is_out_NaN;
- wire is_out_inf;
- wire is_out_zero;
- wire out_sign;
- wire signed [(exp_width + 1):0] out_sexp;
- wire [(mant_width + 2):0] out_mant;
- wire [(exp_width + mant_width):0] num;
- wire cancel_reset;
-
- assign cancel_reset = rst_l & !cancel;
-
- exponent #(exp_width, mant_width) exp_a (.in(a), .out(num));
-
- mac_spec_check #(exp_width,mant_width ) mac_spec_check (.in(num), .is_qNaN (is_a_qNaN), .is_inf(is_a_inf), .is_zero(is_a_zero),
- .is_sNaN(is_a_sNaN),.sign(sign_a), .s_exp(sexp_a), .sig(mant_a) );
-
- assign not_sNaN_inval_excep = !is_a_qNaN && !is_a_zero && sign_a;
- assign major_excep = is_a_sNaN || not_sNaN_inval_excep;
- assign is_res_NaN = is_a_qNaN || not_sNaN_inval_excep;
-
- assign is_res_inf = is_a_inf;
- assign is_res_zero = is_a_zero;
- assign sign_res = sign_a;
- assign special_case_a = is_a_qNaN || is_a_inf || is_a_zero;
- assign normal_case_sqrt = !special_case_a && !sign_a;
- assign normal_case_s = normal_case_sqrt;
- assign even_sqrt = !sexp_a[0];
- assign odd_sqrt = sexp_a[0];
- assign idle = (cycle_num == 0);
- assign in_ready = (cycle_num <= 1);
- assign entering = in_ready && in_valid;
- assign entering_norm_case = entering && normal_case_s;
- assign skip_cycle_2 = (cycle_num == 3) && mantx_z[mant_width + 1];
-
- assign cycle_num_in = (entering && !normal_case_s ? 1 : 0)
- | (entering_norm_case ? ((sexp_a[0] ? mant_width : mant_width + 1)) : 0)
- | (!idle && !skip_cycle_2 ? cycle_num - 1 : 0)
- | (!idle && skip_cycle_2 ? 1 : 0);
-
- rvdffe #(clog2(mant_width + 3)) cycle_num_ff (.clk(clk), .rst_l(cancel_reset), .din(cycle_num_in), .en(!idle || in_valid), .dout(cycle_num));
-
- rvdffe #(1) major_exc_z_ff (.clk(clk), .rst_l(cancel_reset), .din(major_excep), .en(entering), .dout(major_exc_z));
- rvdffe #(1) is_NaN_z_ff (.clk(clk), .rst_l(cancel_reset), .din(is_res_NaN), .en(entering), .dout(is_NaN_z));
- rvdffe #(1) is_inf_z_ff (.clk(clk), .rst_l(cancel_reset), .din(is_res_inf), .en(entering), .dout(is_inf_z));
- rvdffe #(1) is_zero_z_ff (.clk(clk), .rst_l(cancel_reset), .din(is_res_zero), .en(entering), .dout(is_zero_z));
- rvdffe #(1) sign_z_ff (.clk(clk), .rst_l(cancel_reset), .din(sign_res), .en(entering), .dout(sign_z));
-
- assign sexp_z_in = (sexp_a>>>1) + (1<<(exp_width - 1));
- rvdffe #((exp_width + 2)) sexp_z_ff (.clk(clk), .rst_l(cancel_reset), .din(sexp_z_in), .en(entering_norm_case), .dout(sexp_z));
- rvdffe #(3) round_mode_z_ff (.clk(clk), .rst_l(cancel_reset), .din(round_mode), .en(entering_norm_case), .dout(round_mode_z));
-
- assign dec_hi_mant_a = mant_a[(mant_width - 1):(mant_width - 2)] - 1;
- assign rem = (in_ready && !odd_sqrt ? mant_a<<1 : 0) | (in_ready && odd_sqrt
- ? {dec_hi_mant_a, mant_a[(mant_width - 3):0], 3'b0} : 0) | (!in_ready ? rem_z<<1 : 0);
- assign bit_mask = ({{(mant_width + 2){1'b0}}, 1'b1}<<cycle_num)>>2;
- assign trail_term = (in_ready && even_sqrt ? 1<<mant_width : 0)
- | (in_ready && odd_sqrt ? 5<<(mant_width - 1) : 0)
- | (!in_ready ? mantx_z<<1 | bit_mask : 0);
- assign trail_rem = rem - trail_term;
- assign new_bit = (0 <= trail_rem);
-
- assign rem_z_in = new_bit ? trail_rem : rem;
- rvdffe #((mant_width + 2)) rem_z_ff (.clk(clk), .rst_l(cancel_reset), .din(rem_z_in), .en(entering_norm_case || (cycle_num > 2)), .dout(rem_z));
- rvdffe #(1) not_zero_rem_z_ff (.clk(clk), .rst_l(cancel_reset), .din((trail_rem != 0)), .en(entering_norm_case || (!in_ready && new_bit)), .dout(not_zero_rem_z));
-
- assign mantx_z_in = ( in_ready ? 1<<mant_width : 0)
- |( in_ready && odd_sqrt ? new_bit<<(mant_width - 1) : 0)
- |(!in_ready ? mantx_z | bit_mask : 0);
- rvdffe #((mant_width + 2)) mantx_z_ff (.clk(clk), .rst_l(cancel_reset), .din(mantx_z_in), .en(entering_norm_case || (!in_ready && new_bit)), .dout(mantx_z));
-
- assign out_valid = (cycle_num == 1);
- assign round_mode_out = round_mode_z;
- assign invalid_excep = major_exc_z && is_NaN_z;
- assign infinite_excep = 1'b0;
- assign is_out_NaN = is_NaN_z;
- assign is_out_inf = is_inf_z;
- assign is_out_zero = is_zero_z;
- assign out_sign = sign_z;
- assign out_sexp = sexp_z;
- assign out_mant = {mantx_z, not_zero_rem_z};
-
- round_excep #(exp_width, mant_width+2, exp_width,mant_width,0) round_exception
- ( .invalid_excep(invalid_excep), .infinite_excep(infinite_excep), .in_is_NaN(is_out_NaN),
- .in_is_inf(is_out_inf), .in_is_zero(is_out_zero),.in_sign(out_sign),.in_sexp(out_sexp),
- .in_mant(out_mant),.round_mode(round_mode), .result(out), .exceptions(exceptions));
-
-endmodule
diff --git "a/verilog/rtl/attachments\0501\051/uprj_netlists.v" "b/verilog/rtl/attachments\0501\051/uprj_netlists.v"
deleted file mode 100644
index 556d924..0000000
--- "a/verilog/rtl/attachments\0501\051/uprj_netlists.v"
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-// Include caravel global defines for the number of the user project IO pads
-`include "defines.v"
-`define USE_POWER_PINS
-
-`ifdef GL
- // Assume default net type to be wire because GL netlists don't have the wire definitions
- `default_nettype wire
- `include "gl/user_project_wrapper.v"
- `include "gl/user_proj_example.sv"
-`else
- `include "user_project_wrapper.v"
- `include "user_project_example.sv"
-`endif
diff --git "a/verilog/rtl/attachments\0501\051/user_project_example.sv" "b/verilog/rtl/attachments\0501\051/user_project_example.sv"
deleted file mode 100644
index a85198d..0000000
--- "a/verilog/rtl/attachments\0501\051/user_project_example.sv"
+++ /dev/null
@@ -1,342 +0,0 @@
-`include "compare.sv"
-`include "add_sub.sv"
-`include "fpu_lib.sv"
-`include "float_to_int.sv"
-`include "f_class.sv"
-`include "divider.sv"
-`include "min_max.sv"
-`include "multiplier.sv"
-`include "sign_inject.sv"
-`include "int_to_float.sv"
-`include "fused_mul.sv"
-`include "sqrt_fpu.sv"
-`include "registers.sv"
-
-module fpu_top
-(
- input wire clk,
- input wire rst_l, // active low reset
-
- input wire wb_valid, // valid signal from wb
- input wire [31:0] rdwraddr, // read/write address from wb
- input wire [31:0] wrdata, // write data received from wb
-
- input wire [31:0] la_write, // wire analyzer write enable
- input wire [31:0] la_data, // wire analyzer write data
- input wire [31:0] la_addr, // wire analyzer address
-//outputs
- output wire illegal_op,
- output wire inter_gen,
-
- output wire [31:0] rddata, // read data sent to wb
- output wire [31:0] out, // to GPIO
- output wire [4:0] exceptions // on hold for now
-);
- wire la_write_en;
-
- wire [31:0] a;
- wire [31:0] b;
- wire [31:0] c;
-
- wire [1:0] op_in;
- wire [1:0] op_out;
-
- wire [2:0] round_mode;
-
- wire [10:0] valid_in; // (sqrt, div, fma, multi, add-sub, f2i, i2f, min-max, comp, sign_inj, f-class)
- wire [10:0] valid_out;
-
- wire [31:0] fclass_out;
-
- wire [4:0] cmp_exceptions;
- wire [31:0] cmp_out;
-
- wire [4:0] min_max_exceptions;
- wire [31:0] min_max_out;
-
- wire [4:0] itof_exceptions;
- wire [31:0] itof_out;
-
- wire [4:0] ftoi_exceptions;
- wire [31:0] ftoi_out;
-
- wire [31:0] sinj_out;
-
- wire [4:0] add_sub_exceptions;
- wire [31:0] add_sub_out;
-
- wire [4:0] mul_exceptions;
- wire [31:0] mul_out;
-
- wire [4:0] mac_exceptions;
- wire [31:0] mac_out;
-
- wire [4:0] sqrt_exceptions;
- wire [31:0] sqrt_out;
-
- wire [4:0] div_exceptions;
- wire [31:0] div_out;
- wire div_valid_out;
- wire sqrt_valid_out;
-
- wire [4:0] excep_temp;
- wire [31:0] out_temp;
-
- wire [31:0] int_rddata;
- wire [31:0] addr;
-
- assign la_write_en = |la_write;
- assign addr = la_write_en ? la_addr : rdwraddr;
-
- fpu_registers csrs ( .clk (clk ),
- .rst_l (rst_l ),
- .fpu_result (out ),
- .fpu_valids ({valid_out, op_out} ),
- .addr (addr ),
- .wren (wb_valid ),
- .wrdata (wrdata ),
- .exceptions (exceptions ),
- .rddata (int_rddata ),
- .opA (a ),
- .opB (b ),
- .opC (c ),
- .frm (round_mode ),
- .op_valids ({valid_in, op_in} ),
- .inter_gen (inter_gen ));
-
- f_class #(8,24) fpu_fclass ( .in (a ),
- .result (fclass_out ) );
-
- sign_inject #(8,24) fpu_sgn_inj ( .a (a ),
- .b (b ),
- .op (op_in ),
- .out (sinj_out ) );
-
- compare #(8,24) fpu_comp ( .a (a ),
- .b (b ),
- .op (op_in ),
- .out (cmp_out ),
- .exceptions (cmp_exceptions ) );
-
- min_max #(8,24) fpu_min_max ( .a (a ),
- .b (b ),
- .op (op_in[0] ),
- .out (min_max_out ),
- .exceptions (min_max_exceptions ) );
-
- int_to_float #(32,8,24) fpu_i2f ( .signed_in (op_in[0] ),
- .num (a ),
- .round_mode (round_mode ),
- .out (itof_out ),
- .exceptions (itof_exceptions ) );
-
- float_to_int #(8,24) fpu_f2i ( .num (a ),
- .round_mode (round_mode ),
- .signed_out (op_in[0] ),
- .out (ftoi_out ),
- .int_exceptions (ftoi_exceptions ) );
-
- add_sub fpu_add_sub ( .in_x (a ),
- .in_y (b ),
- .operation (op_in[0] ),
- .round_mode (round_mode ),
- .out_z (add_sub_out ),
- .exceptions (add_sub_exceptions ) );
-
- multiplier #(8,24) fpu_mult ( .a (a ),
- .b (b ),
- .round_mode (round_mode ),
- .exceptions (mul_exceptions ),
- .out (mul_out ) );
-
- fused_multiply #(8,24) fpu_fma ( .a (a ),
- .b (b ),
- .c (c ),
- .op (op_in ),
- .round_mode (round_mode ),
- .out (mac_out ),
- .exceptions (mac_exceptions ) );
-
- divider #(8,24) fpu_divider ( .rst_l (rst_l ),
- .clk (clk ),
- .in_valid (valid_in[9] ),
- .a (a ),
- .b (b ),
- .round_mode (round_mode ),
- .cancel (1'b0 ),
- .in_ready ( ),
- .out_valid (div_valid_out ),
- .out (div_out ),
- .exceptions (div_exceptions ) );
-
- sqrt #(8,24) fpu_sqrt ( .clk (clk ),
- .rst_l (rst_l ),
- .in_valid (valid_in[10] ),
- .a (a ),
- .round_mode (round_mode ),
- .cancel (1'b0 ),
- .in_ready ( ),
- .out_valid (sqrt_valid_out ),
- .out (sqrt_out ),
- .exceptions (sqrt_exceptions ) );
-
-// check for illegal op in case of sign inject and compare result
- assign illegal_op = ((valid_in[1] || valid_in[2]) && (op_in == 2'b11)) ? 1'b1 : 1'b0;
-
-// output operation performed
- assign op_out = ({valid_in[1] || valid_in[2] || valid_in[3] || valid_in[6] || valid_in[8]}) ? op_in : 2'b0;
-
- assign valid_out = {sqrt_valid_out,div_valid_out,valid_in[8:0]};
-
-// return output data according to module enable
- assign {out, exceptions} = ({37{illegal_op}} & {32'b0 ,5'b0 }) |
- ({37{valid_in[10 & wb_valid]}} & {sqrt_out ,sqrt_exceptions }) |
- ({37{valid_in[9] & wb_valid}} & {div_out ,div_exceptions }) |
- ({37{valid_in[8] & wb_valid}} & {mac_out ,mac_exceptions }) |
- ({37{valid_in[7] & wb_valid}} & {mul_out ,mul_exceptions }) |
- ({37{valid_in[6] & wb_valid}} & {add_sub_out,add_sub_exceptions}) |
- ({37{valid_in[5] & wb_valid}} & {ftoi_out ,ftoi_exceptions }) |
- ({37{valid_in[4] & wb_valid}} & {itof_out ,ftoi_exceptions }) |
- ({37{valid_in[3] & wb_valid}} & {min_max_out,min_max_exceptions}) |
- ({37{valid_in[2] & wb_valid}} & {cmp_out ,cmp_exceptions }) |
- ({37{valid_in[1] & wb_valid}} & {sinj_out ,5'b0 }) |
- ({37{valid_in[0] & wb_valid}} & {fclass_out ,5'b0 });
-
-// data to be read from memory
- assign rddata = wb_valid ? 32'b0 : la_write_en ? (la_write & la_data) : int_rddata;
-
-endmodule
-
-
-
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_proj_example
- *
- * This is an example of a (trivially simple) user project,
- * showing how the user project can connect to the wire
- * analyzer, the wishbone bus, and the I/O pads.
- *
- * This project generates an integer count, which is output
- * on the user area GPIO pads (digital output only). The
- * wishbone connection allows the project to be controlled
- * (start and stop) from the management SoC program.
- *
- * See the testbenches in directory "mprj_counter" for the
- * example programs that drive this user project. The three
- * testbenches are "io_ports", "la_test1", and "la_test2".
- *
- *-------------------------------------------------------------
- */
-
-module user_proj_example #(
- parameter BITS = 32
-)(
-`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
-`endif
-
- // Wishbone Slave ports (WB MI A)
- input wb_clk_i,
- input wb_rst_i,
- input wbs_stb_i,
- input wbs_cyc_i,
- input wbs_we_i,
- input [3:0] wbs_sel_i,
- input [31:0] wbs_dat_i,
- input [31:0] wbs_adr_i,
- output wbs_ack_o,
- output [31:0] wbs_dat_o,
-
- // wire Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oenb,
-
- // IOs
- input wire [37:0] io_in,
- output wire [37:0] io_out,
- output wire [37:0] io_oeb,
-
- output [2:0]irq
-);
- wire clk;
- wire rst;
-
- wire [31:0] rdata;
- wire [31:0] wdata;
- //wire [BITS-1:0] signal_received;
-
- wire valid;
- wire [3:0] wstrb;
- wire [31:0] la_write;
-
- // WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i && (|wbs_sel_i) && wbs_we_i;
- //assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- assign wbs_dat_o = rdata;
- assign wdata = wbs_dat_i;
-
- // IO
- assign io_out[37:32] = 6'b0;
- assign io_oeb = {(37){~rst}};
-
- // LA
- assign la_data_out = {{(127-BITS){1'b0}}, rdata};
- // Assuming LA probes [31:0] are for controlling the input register
- assign la_write = ~la_oenb[31:0] & ~valid;
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oenb[32]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oenb[33]) ? la_data_in[65]: wb_rst_i;
-
-
- wire illegal_op;
- wire [4:0]exceptions;
-
- assign irq = illegal_op ? 3'b001 : exceptions[0] ? 3'b010 : exceptions[1] ? 3'b011 : exceptions[2] ? 3'b100 : exceptions[3] ? 3'b101 : 3'b000;
-
-
-
- fpu_top fpu (
- .clk(clk),
- .rst_l(~rst),
- //.wren(|wstrb),
- .wb_valid(valid),
- .la_write(la_write),
- .la_data(la_data_in[63:32]),
- .la_addr(la_data_in[31:0]),
- .rdwraddr(wbs_adr_i),
- .wrdata(wdata),
- .rddata(rdata),
- .illegal_op(illegal_op),
- .inter_gen(wbs_ack_o),
- .exceptions(exceptions),
- .out(io_out[31:0]));
-
-endmodule
-
-`default_nettype wire
diff --git "a/verilog/rtl/attachments\0501\051/user_project_wrapper.v" "b/verilog/rtl/attachments\0501\051/user_project_wrapper.v"
deleted file mode 100644
index 2a3462b..0000000
--- "a/verilog/rtl/attachments\0501\051/user_project_wrapper.v"
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_project_wrapper
- *
- * This wrapper enumerates all of the pins available to the
- * user for the user project.
- *
- * An example user project is provided in this wrapper. The
- * example should be removed and replaced with the actual
- * user project.
- *
- *-------------------------------------------------------------
- */
-
-module user_project_wrapper #(
- parameter BITS = 32
-) (
-`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
-`endif
-
- // Wishbone Slave ports (WB MI A)
- input wb_clk_i,
- input wb_rst_i,
- input wbs_stb_i,
- input wbs_cyc_i,
- input wbs_we_i,
- input [3:0] wbs_sel_i,
- input [31:0] wbs_dat_i,
- input [31:0] wbs_adr_i,
- output wbs_ack_o,
- output [31:0] wbs_dat_o,
-
- // Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oenb,
-
- // IOs
- input [`MPRJ_IO_PADS-1:0] io_in,
- output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb,
-
- // Analog (direct connection to GPIO pad---use with caution)
- // Note that analog I/O is not available on the 7 lowest-numbered
- // GPIO pads, and so the analog_io indexing is offset from the
- // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
- inout [`MPRJ_IO_PADS-10:0] analog_io,
-
- // Independent clock (on independent integer divider)
- input user_clock2,
-
- // User maskable interrupt signals
- output [2:0] user_irq
-);
-
-/*--------------------------------------*/
-/* User project is instantiated here */
-/*--------------------------------------*/
-
-user_proj_example mprj (
- `ifdef USE_POWER_PINS
- .vdda1(vdda1), // User area 1 3.3V power
- .vdda2(vdda2), // User area 2 3.3V power
- .vssa1(vssa1), // User area 1 analog ground
- .vssa2(vssa2), // User area 2 analog ground
- .vccd1(vccd1), // User area 1 1.8V power
- .vccd2(vccd2), // User area 2 1.8V power
- .vssd1(vssd1), // User area 1 digital ground
- .vssd2(vssd2), // User area 2 digital ground
- `endif
-
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- // MGMT SoC Wishbone Slave
-
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
-
- // Logic Analyzer
-
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
-
- // IO Pads
-
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
-
- // IRQ
- .irq(user_irq)
-);
-
-endmodule // user_project_wrapper
-
-`default_nettype wire
