Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-035
/
5c21dd967a19aec3febceb31bd0f8e573ad5445f
commit
5c21dd967a19aec3febceb31bd0f8e573ad5445f
[
log
]
author
aghaalizeb-lm <agha.ali@lampromellon.com>
Thu May 27 14:53:15 2021 +0500
committer
aghaalizeb-lm <agha.ali@lampromellon.com>
Thu May 27 14:53:15 2021 +0500
tree
80041eff2279dfca5f1c616074e757b10edc441e
parent
c342274c3796ee290715cca3d13077c5b6ef198d
[
diff
]
wb_valid off cycle bug fix
verilog/rtl/user_proj_example.sv
[
diff
]
1 file changed
tree: 80041eff2279dfca5f1c616074e757b10edc441e
.github/
caravel/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.