commit 53b68a3bb7ade21c9269aaffee78fd6395dc99f7
author aghaalizeb-lm <agha.ali@lampromellon.com> Wed Jun 02 17:10:30 2021 +0500
committer aghaalizeb-lm <agha.ali@lampromellon.com> Wed Jun 02 17:10:30 2021 +0500
tree 547c850d64163a07b7b350c0726ce8e1f213004f
parent bd47ece8b0d6a67eea8ea6f741019b637106a05e

valid out bug fix

verilog/rtl/user_proj_example.sv

diff --git a/verilog/rtl/user_proj_example.sv b/verilog/rtl/user_proj_example.sv
index c660de5..08cd213 100644
--- a/verilog/rtl/user_proj_example.sv
+++ b/verilog/rtl/user_proj_example.sv
@@ -191,7 +191,7 @@
   
   assign valid_out                = {sqrt_valid_out,div_valid_out,valid_in[8:0]};
 
-  assign wb_valid_ns              = |valid_out ? wb_valid : wb_valid_f;
+  assign wb_valid_ns              =( |valid_out | wb_valid) ? wb_valid : wb_valid_f;
 
   rvdff #(1) wb_valid_ff (.clk(clk), .rst_l(rst_l), .din(wb_valid_ns), .dout(wb_valid_f));