| commit | 400a959484c09d26227fcf12fce0430dd7a6e208 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Mon Dec 27 08:46:26 2021 +0000 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Mon Dec 27 08:46:26 2021 +0000 |
| tree | c9d48b6bdaff486a93bca90085ce85c979971cc4 | |
| parent | 5e27cb0b2a3e8c3d1f89eea252db7201f57b9f8c [diff] |
final gds & signoff results
The default rounding mode for all the operations is RNE as highlighted by RISC-V and IEEE-754 spec.
Result of FPU calculation also appers at the 32 GPIO pins.
