update config/verilog for Eric & Konrad
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 34060ff..28b6fbe 100755 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -59,7 +59,7 @@ set ::env(EXTRA_LEFS) [glob $::env(DESIGN_DIR)/macros/lef/*.lef] set ::env(EXTRA_GDS_FILES) [glob $::env(DESIGN_DIR)/macros/gds/*.gds] -set ::env(GLB_RT_ADJUSTMENT) 0.60 +set ::env(GLB_RT_ADJUSTMENT) 0.70 # 0 -> 1: 1 means don't use the layer # l2 is met1 set ::env(GLB_RT_L2_ADJUSTMENT) 0.9
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index dae1bf0..62b1661 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,3 +1,5 @@ wrapped_rgb_mixer 344 464 N wrapped_frequency_counter 344 1228 N wrapped_a51 344 1992 N +wrapper_fibonacci 344 2756 N +pong_wrapper 988 464 N
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 90bd79e..97e0bd8 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -26,12 +26,18 @@ `else `include "user_project_wrapper.v" - // 2 ('A5/1 Wishbone',) : /home/matt/work/asic-workshop/course/participants/group1/jamieiles/a5-1-wb-macro - `include "a5-1-wb-macro/src/wrapper.v" - `include "a5-1-wb-macro/src/Fifo.v" - `include "a5-1-wb-macro/src/A5If.v" - `include "a5-1-wb-macro/src/A5Generator.v" - `include "a5-1-wb-macro/src/A5LFSR.v" - `include "a5-1-wb-macro/src/A5Buffer.v" + // 4 ('Pong',) : /home/matt/work/asic-workshop/course/participants/group2/ericz/wrapped_pong + `include "wrapped_pong/wrapper.v" + `include "wrapped_pong/pong/src/debounce.v" + `include "wrapped_pong/pong/src/rot_encoder.v" + `include "wrapped_pong/pong/src/clkdiv.v" + `include "wrapped_pong/pong/src/screen.v" + `include "wrapped_pong/pong/src/game.v" + `include "wrapped_pong/pong/src/trig.v" + `include "wrapped_pong/pong/src/paddle.v" + `include "wrapped_pong/pong/src/ball.v" + `include "wrapped_pong/pong/src/score.v" + `include "wrapped_pong/pong/src/rnd.v" + `include "wrapped_pong/pong/src/pong.v" `endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index a503f4b..3c01ea6 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -202,6 +202,88 @@ .active (la_data_in[32+2]) ); + wrapper_fibonacci wrapper_fibonacci( + `ifdef USE_POWER_PINS + .vdda1(vdda1), // User area 1 3.3V power + .vdda2(vdda2), // User area 2 3.3V power + .vssa1(vssa1), // User area 1 analog ground + .vssa2(vssa2), // User area 2 analog ground + .vccd1(vccd1), // User area 1 1.8V power + .vccd2(vccd2), // User area 2 1.8V power + .vssd1(vssd1), // User area 1 digital ground + .vssd2(vssd2), // User area 2 digital ground + `endif + + // interface as user_proj_example.v + .wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbs_stb_i (wbs_stb_i), + .wbs_cyc_i (wbs_cyc_i), + .wbs_we_i (wbs_we_i), + .wbs_sel_i (wbs_sel_i), + .wbs_dat_i (wbs_dat_i), + .wbs_adr_i (wbs_adr_i), + .wbs_ack_o (wbs_ack_o), + .wbs_dat_o (wbs_dat_o), + + // only provide first 32 bits to reduce wiring congestion + .la_data_in (la_data_in [31:0]), + .la_data_out(la_data_out[31:0]), + .la_oenb (la_oenb[31:0]), + + // IOs + .io_in (io_in), + .io_out (io_out), + .io_oeb (io_oeb), + + // IRQs + .irq (user_irq), + + // active input, only connect tristated outputs if this is high + .active (la_data_in[32+3]) + ); + + wrapped_pong pong_wrapper( + `ifdef USE_POWER_PINS + .vdda1(vdda1), // User area 1 3.3V power + .vdda2(vdda2), // User area 2 3.3V power + .vssa1(vssa1), // User area 1 analog ground + .vssa2(vssa2), // User area 2 analog ground + .vccd1(vccd1), // User area 1 1.8V power + .vccd2(vccd2), // User area 2 1.8V power + .vssd1(vssd1), // User area 1 digital ground + .vssd2(vssd2), // User area 2 digital ground + `endif + + // interface as user_proj_example.v + .wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbs_stb_i (wbs_stb_i), + .wbs_cyc_i (wbs_cyc_i), + .wbs_we_i (wbs_we_i), + .wbs_sel_i (wbs_sel_i), + .wbs_dat_i (wbs_dat_i), + .wbs_adr_i (wbs_adr_i), + .wbs_ack_o (wbs_ack_o), + .wbs_dat_o (wbs_dat_o), + + // only provide first 32 bits to reduce wiring congestion + .la_data_in (la_data_in [31:0]), + .la_data_out(la_data_out[31:0]), + .la_oenb (la_oenb[31:0]), + + // IOs + .io_in (io_in), + .io_out (io_out), + .io_oeb (io_oeb), + + // IRQs + .irq (user_irq), + + // active input, only connect tristated outputs if this is high + .active (la_data_in[32+4]) + ); + // end of module instantiation