03197b3e3ffd3e90bf3820e69936818f9457b10f - third_party/shuttle/sky130/mpw-002/slot-032

commit	03197b3e3ffd3e90bf3820e69936818f9457b10f	[log] [tgz]
author	ssprasad <ssprasad12a@gmail.com>	Wed Jun 09 20:51:48 2021 +0530
committer	ssprasad <ssprasad12a@gmail.com>	Wed Jun 09 20:51:48 2021 +0530
tree	f5668df20b5f5c09adb626250ba3ff45c0d8bbb9
parent	d3e050539b229d532a45c37a645482e081e344cc [diff]

creating local repo

.github/scripts/build/run-set-id.sh[diff]
.github/scripts/build/run-ship.sh[diff]
.github/scripts/build/run-xor.sh[diff]
.github/scripts/dv/pdkBuild.sh[diff]
.github/scripts/dv/run-dv-wrapper.sh[diff]
.github/scripts/dv/run-dv.sh[diff]
.github/scripts/precheck/precheckBuild.sh[diff]
.github/scripts/precheck/run-precheck-drc.sh[diff]
.github/scripts/precheck/run-precheck.sh[diff]
.github/workflows/auto_update_submodule.yml[diff]
.github/workflows/caravel_build.yml[diff]
.github/workflows/user_project_ci.yml[diff]
.gitignore[diff]
.gitmodules[diff]
LICENSE[diff]
Makefile[diff]
README.md[diff]
def/user_proj_example.def[diff]
def/user_project_wrapper.def[diff]
docs/Makefile[diff]
docs/environment.yml[diff]
docs/requirements.txt[diff]
docs/source/_static/counter_32.png[diff]
docs/source/_static/wrapper.png[diff]
docs/source/conf.py[diff]
docs/source/index.rst[diff]
docs/user_project_wrapper.placement.def.png[Added - diff]
gds/.magicrc[Added - diff]
gds/user_proj_example.gds[Added - diff]
gds/user_proj_example.gds.gz[diff]
gds/user_project_wrapper.gds[Added - diff]
gds/user_project_wrapper.gds.gz[diff]
info.yaml[diff]
lef/user_proj_example.lef[diff]
lef/user_project_wrapper.lef[diff]
mag/user_proj_example.mag[diff]
mag/user_project_wrapper.mag[diff]
mag/user_project_wrapper.mag.gz[Added - diff]
maglef/user_proj_example.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/.gitignore[diff]
openlane/user_proj_example/config.tcl[diff]
openlane/user_proj_example/pin_order.cfg[diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
signoff/user_proj_example/OPENLANE_VERSION[diff]
signoff/user_proj_example/PDK_SOURCES[diff]
signoff/user_proj_example/final_summary_report.csv[diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
signoff/user_project_wrapper_xor/total.txt[diff]
signoff/user_project_wrapper_xor/user_project_wrapper.xor.gds[diff]
signoff/user_project_wrapper_xor/user_project_wrapper.xor.gds.png[diff]
signoff/user_project_wrapper_xor/user_project_wrapper.xor.xml[diff]
signoff/user_project_wrapper_xor/xor.log[diff]
spi/lvs/user_proj_example.spice[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/Makefile[diff]
verilog/dv/README.md[diff]
verilog/dv/input_test/Makefile[Renamed from verilog/dv/io_ports/Makefile - diff]
verilog/dv/input_test/expected_result.rpt[Added - diff]
verilog/dv/input_test/io_ports.c[Renamed from verilog/dv/io_ports/io_ports.c - diff]
verilog/dv/input_test/io_ports.hex[Added - diff]
verilog/dv/input_test/io_ports_tb.v[Copied from verilog/dv/io_ports/io_ports_tb.v - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/la_test2/la_test2_tb.v[Deleted - diff]
verilog/dv/mprj_stimulus/Makefile[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/output_test/Makefile[Copied from verilog/dv/io_ports/Makefile - diff]
verilog/dv/output_test/expected_result.rpt[Added - diff]
verilog/dv/output_test/io_ports.c[Added - diff]
verilog/dv/output_test/io_ports.hex[Added - diff]
verilog/dv/output_test/io_ports.vcd[Added - diff]
verilog/dv/output_test/io_ports_tb.v[Renamed from verilog/dv/io_ports/io_ports_tb.v - diff]
verilog/dv/wb_port/Makefile[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_port/wb_port_tb.v[Deleted - diff]
verilog/gl/user_proj_example.v[diff]
verilog/rtl/gpio_ssp.v[Added - diff]
verilog/rtl/peripheral_top.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_proj_example.v[diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/wishbone2apb.v[Added - diff]

90 files changed

tree: f5668df20b5f5c09adb626250ba3ff45c0d8bbb9