final gds & signoff results
diff --git a/signoff/build/gpio_defaults.out b/signoff/build/gpio_defaults.out
index 31aab63..5690676 100644
--- a/signoff/build/gpio_defaults.out
+++ b/signoff/build/gpio_defaults.out
@@ -1,6 +1,6 @@
Step 1: Create new cells for new GPIO default vectors.
Creating new layout file /mnt/shuttles/shuttle/mpw-two/slot-031/renml/mag/gpio_defaults_block_0403.mag
-Creating new gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-031/renml/verilog/gl/gpio_defaults_block_0403.v
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-031/renml/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-031/renml/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-031/renml/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Layout file /mnt/shuttles/shuttle/mpw-two/slot-031/renml/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
