Add top pll v3
diff --git a/checks/user_analog_project_wrapper.magic.drc.mag b/checks/user_analog_project_wrapper.magic.drc.mag
index b2eadb0..a847a77 100644
--- a/checks/user_analog_project_wrapper.magic.drc.mag
+++ b/checks/user_analog_project_wrapper.magic.drc.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624402262
+timestamp 1624402378
<< checkpaint >>
rect -4732 -4732 588732 708732
<< nwell >>
@@ -3453,72 +3453,72 @@
rect 338617 136437 354407 136579
use mimcap_decoup_1x5 mimcap_decoup_1x5_6
array 0 0 34500 0 2 6522
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 38481 0 1 560871
box 0 -159 34500 6363
use top_pll_v1 top_pll_v1_1
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 14782 0 1 657248
box -656 -33693 50195 2860
use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_2
array 0 0 6724 0 8 6522
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 74005 0 1 616157
box -3351 -3261 3373 3261
use top_pll_v2 top_pll_v2_0
-timestamp 1624402262
+timestamp 1624402378
transform -1 0 133068 0 1 657248
box -656 -33693 50195 2860
use mimcap_decoup_1x5 mimcap_decoup_1x5_5
array 0 0 34500 0 2 6522
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 126717 0 1 559996
box 0 -159 34500 6363
use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_1
array 0 0 6724 0 8 6522
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 144463 0 1 616442
box -3351 -3261 3373 3261
use top_pll_v1 top_pll_v1_0
-timestamp 1624402262
+timestamp 1624402378
transform -1 0 206380 0 1 656706
box -656 -33693 50195 2860
use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_0
array 0 0 6724 0 6 6522
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 220679 0 1 616773
box -3351 -3261 3373 3261
use mimcap_decoup_1x5 mimcap_decoup_1x5_4
array 0 0 34500 0 2 6522
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 197202 0 1 560156
box 0 -159 34500 6363
use bias bias_0
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 202834 0 -1 687483
box -54 -412 44317 2238
use mimcap_decoup_1x5 mimcap_decoup_1x5_3
array 0 0 34500 0 1 6522
-timestamp 1624402262
+timestamp 1624402378
transform -1 0 345445 0 1 602155
box 0 -159 34500 6363
use mimcap_decoup_1x5 mimcap_decoup_1x5_2
array 0 0 34500 0 2 6522
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 291410 0 1 559700
box 0 -159 34500 6363
use res_amp_top res_amp_top_0
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 349695 0 1 630386
box -5005 -972 31038 12726
use mimcap_decoup_1x5 mimcap_decoup_1x5_1
array 0 0 34500 0 2 6522
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 382888 0 1 560156
box 0 -159 34500 6363
use mimcap_decoup_1x5 mimcap_decoup_1x5_0
array 0 0 34500 0 2 6522
-timestamp 1624402262
+timestamp 1624402378
transform 1 0 489384 0 1 560611
box 0 -159 34500 6363
<< labels >>
diff --git a/mag/DFlipFlop.mag b/mag/DFlipFlop.mag
index 23937ec..07ccd05 100644
--- a/mag/DFlipFlop.mag
+++ b/mag/DFlipFlop.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624049879
+timestamp 1624885207
<< nwell >>
rect 559 2292 1181 3068
rect 559 0 1181 776
@@ -110,7 +110,7 @@
rect 219 1320 229 1432
rect 153 1315 229 1320
use clock_inverter clock_inverter_0
-timestamp 1624049879
+timestamp 1624885207
transform 1 0 -1244 0 1 0
box 0 0 1244 3068
use latch_diff latch_diff_1
diff --git a/mag/clock_inverter.mag b/mag/clock_inverter.mag
index 43a94a8..4b5491a 100644
--- a/mag/clock_inverter.mag
+++ b/mag/clock_inverter.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624049879
+timestamp 1624885207
<< metal1 >>
rect 520 2998 530 3028
rect 0 2944 530 2998
@@ -64,6 +64,10 @@
rect 520 40 530 154
rect 714 40 724 154
rect 520 35 724 40
+use trans_gate trans_gate_0
+timestamp 1624653480
+transform 1 0 675 0 -1 723
+box -53 -811 569 723
use inverter_cp_x1 inverter_cp_x1_1
timestamp 1624049879
transform 1 0 0 0 1 2292
@@ -76,10 +80,6 @@
timestamp 1624049879
transform 1 0 0 0 -1 776
box 0 -758 622 776
-use trans_gate trans_gate_0
-timestamp 1624049879
-transform 1 0 675 0 -1 723
-box -53 -811 569 723
<< labels >>
rlabel metal1 0 1504 1244 1564 1 vss
rlabel metal1 0 2944 1244 2998 1 vdd
diff --git a/mag/div_by_2.mag b/mag/div_by_2.mag
index 333a768..8cfb92f 100644
--- a/mag/div_by_2.mag
+++ b/mag/div_by_2.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624402156
+timestamp 1624885207
<< nwell >>
rect 2984 2989 4228 3068
rect 3203 118 4219 142
@@ -167,30 +167,30 @@
rect -76 712 -75 744
rect 2082 743 2148 744
rect -141 711 -75 712
-use DFlipFlop DFlipFlop_0
-timestamp 1624049879
-transform 1 0 1244 0 -1 3068
-box -1244 0 1740 3068
-use inverter_min_x4 inverter_min_x4_0
-timestamp 1624049879
-transform 1 0 3563 0 1 2346
-box -53 -616 665 643
-use inverter_min_x4 inverter_min_x4_1
-timestamp 1624049879
-transform 1 0 3563 0 -1 723
-box -53 -616 665 643
-use inverter_min_x2 inverter_min_x2_1
-timestamp 1624049879
-transform 1 0 3037 0 1 2345
-box -53 -615 473 655
+use clock_inverter clock_inverter_0
+timestamp 1624885207
+transform 1 0 -1244 0 1 0
+box 0 0 1244 3068
use inverter_min_x2 inverter_min_x2_0
timestamp 1624049879
transform 1 0 3037 0 -1 723
box -53 -615 473 655
-use clock_inverter clock_inverter_0
+use inverter_min_x2 inverter_min_x2_1
timestamp 1624049879
-transform 1 0 -1244 0 1 0
-box 0 0 1244 3068
+transform 1 0 3037 0 1 2345
+box -53 -615 473 655
+use inverter_min_x4 inverter_min_x4_1
+timestamp 1624049879
+transform 1 0 3563 0 -1 723
+box -53 -616 665 643
+use inverter_min_x4 inverter_min_x4_0
+timestamp 1624049879
+transform 1 0 3563 0 1 2346
+box -53 -616 665 643
+use DFlipFlop DFlipFlop_0
+timestamp 1624885207
+transform 1 0 1244 0 -1 3068
+box -1244 0 1740 3068
<< labels >>
rlabel metal1 -1244 2944 2984 2998 1 vdd
rlabel metal1 -1244 1498 1313 1570 1 vss
diff --git a/mag/div_by_5.mag b/mag/div_by_5.mag
index 4f8c55d..439235d 100644
--- a/mag/div_by_5.mag
+++ b/mag/div_by_5.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624402156
+timestamp 1624885207
<< nwell >>
rect -556 2925 0 3068
rect -556 2664 57 2925
@@ -317,38 +317,38 @@
rect 9599 884 12343 948
rect 12583 884 12584 948
rect 1990 883 12584 884
-use DFlipFlop DFlipFlop_3
-timestamp 1624049879
-transform 1 0 11596 0 -1 3068
-box -1244 0 1740 3068
-use DFlipFlop DFlipFlop_1
-timestamp 1624049879
-transform 1 0 4784 0 1 0
-box -1244 0 1740 3068
-use DFlipFlop DFlipFlop_2
-timestamp 1624049879
-transform 1 0 8612 0 1 0
-box -1244 0 1740 3068
-use DFlipFlop DFlipFlop_0
-timestamp 1624049879
-transform 1 0 1244 0 1 0
-box -1244 0 1740 3068
-use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_1
-timestamp 1624049879
-transform 1 0 3022 0 -1 1108
-box -38 -49 518 715
use sky130_fd_sc_hs__xor2_1 sky130_fd_sc_hs__xor2_1_0
timestamp 1624049879
transform -1 0 7330 0 1 1960
box -38 -49 806 715
-use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_0
-timestamp 1624049879
-transform 1 0 -518 0 1 1960
-box -38 -49 518 715
use sky130_fd_sc_hs__or2_1 sky130_fd_sc_hs__or2_1_0
timestamp 1624049879
transform 1 0 13374 0 1 1960
box -38 -49 518 715
+use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_0
+timestamp 1624049879
+transform 1 0 -518 0 1 1960
+box -38 -49 518 715
+use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_1
+timestamp 1624049879
+transform 1 0 3022 0 -1 1108
+box -38 -49 518 715
+use DFlipFlop DFlipFlop_0
+timestamp 1624885207
+transform 1 0 1244 0 1 0
+box -1244 0 1740 3068
+use DFlipFlop DFlipFlop_2
+timestamp 1624885207
+transform 1 0 8612 0 1 0
+box -1244 0 1740 3068
+use DFlipFlop DFlipFlop_1
+timestamp 1624885207
+transform 1 0 4784 0 1 0
+box -1244 0 1740 3068
+use DFlipFlop DFlipFlop_3
+timestamp 1624885207
+transform 1 0 11596 0 -1 3068
+box -1244 0 1740 3068
<< labels >>
rlabel metal2 7175 2568 10572 2700 1 Q1
rlabel metal1 6263 2308 7075 2367 1 Q0
diff --git a/mag/extractions/loop_filter_v2_lvs_port.spice b/mag/extractions/loop_filter_v2_lvs_port.spice
new file mode 100644
index 0000000..f0b5116
--- /dev/null
+++ b/mag/extractions/loop_filter_v2_lvs_port.spice
@@ -0,0 +1,91 @@
+* NGSPICE file created from loop_filter_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+.subckt loop_filter_v2 vss in vc_pex D0_cap
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
diff --git a/mag/extractions/loop_filter_v2_pex_c.spice b/mag/extractions/loop_filter_v2_pex_c.spice
index 3f1f29b..81ce56f 100644
--- a/mag/extractions/loop_filter_v2_pex_c.spice
+++ b/mag/extractions/loop_filter_v2_pex_c.spice
@@ -30,71 +30,71 @@
X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-C0 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
-C1 m3_n2650_8000# m3_2669_8000# 2.73fF
-C2 m3_n13288_n2600# m3_n13288_2700# 3.28fF
-C3 m3_n2650_n7900# m3_2669_n7900# 2.73fF
-C4 m3_2669_n13200# m3_n2650_n13200# 2.73fF
-C5 m3_n13288_8000# c1_n13188_n13100# 58.36fF
-C6 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
-C7 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
-C8 m3_n7969_2700# c1_n13188_n13100# 58.86fF
-C9 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
-C10 c1_n13188_n13100# m3_7988_n13200# 60.75fF
-C11 m3_2669_n7900# c1_n13188_n13100# 58.86fF
-C12 m3_n7969_2700# m3_n2650_2700# 2.73fF
-C13 m3_2669_8000# c1_n13188_n13100# 58.61fF
-C14 m3_7988_8000# c1_n13188_n13100# 60.75fF
-C15 m3_n2650_n2600# m3_2669_n2600# 2.73fF
-C16 m3_7988_n13200# m3_2669_n13200# 2.73fF
-C17 m3_2669_n7900# m3_2669_n13200# 3.28fF
-C18 m3_2669_2700# m3_2669_n2600# 3.28fF
-C19 m3_n2650_8000# m3_n7969_8000# 2.73fF
-C20 m3_n13288_2700# m3_n13288_8000# 3.28fF
-C21 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
-C22 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
-C23 m3_7988_n13200# m3_7988_n7900# 3.39fF
-C24 m3_2669_n7900# m3_7988_n7900# 2.73fF
-C25 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
-C26 m3_n13288_2700# m3_n7969_2700# 2.73fF
-C27 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
-C28 m3_n7969_8000# c1_n13188_n13100# 58.61fF
-C29 c1_n13188_n13100# m3_7988_2700# 61.01fF
-C30 m3_7988_n2600# m3_7988_2700# 3.39fF
-C31 m3_2669_n7900# m3_2669_n2600# 3.28fF
-C32 m3_2669_2700# m3_2669_8000# 3.28fF
-C33 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
-C34 m3_n2650_8000# c1_n13188_n13100# 58.61fF
-C35 m3_n7969_n2600# m3_n7969_2700# 3.28fF
-C36 m3_n2650_8000# m3_n2650_2700# 3.28fF
-C37 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
-C38 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
-C39 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
-C40 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
-C41 m3_2669_8000# m3_7988_8000# 2.73fF
-C42 m3_2669_2700# m3_7988_2700# 2.73fF
-C43 m3_7988_n2600# c1_n13188_n13100# 61.01fF
-C44 c1_n13188_n13100# m3_n2650_2700# 58.86fF
-C45 c1_n13188_n13100# m3_2669_n13200# 58.61fF
-C46 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
-C47 m3_n13288_8000# m3_n7969_8000# 2.73fF
-C48 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
-C49 c1_n13188_n13100# m3_7988_n7900# 61.01fF
-C50 m3_7988_n2600# m3_7988_n7900# 3.39fF
-C51 m3_n7969_8000# m3_n7969_2700# 3.28fF
-C52 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
-C53 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
-C54 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
-C55 m3_n13288_2700# c1_n13188_n13100# 58.61fF
-C56 m3_7988_8000# m3_7988_2700# 3.39fF
-C57 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
-C58 m3_2669_n2600# c1_n13188_n13100# 58.86fF
-C59 m3_7988_n2600# m3_2669_n2600# 2.73fF
-C60 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
-C61 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
-C62 m3_2669_2700# c1_n13188_n13100# 58.86fF
-C63 m3_n2650_n2600# m3_n2650_2700# 3.28fF
-C64 m3_2669_2700# m3_n2650_2700# 2.73fF
+C0 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C1 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C2 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C3 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C4 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C5 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C6 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C7 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C8 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C9 m3_n2650_8000# m3_2669_8000# 2.73fF
+C10 m3_n2650_2700# m3_2669_2700# 2.73fF
+C11 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C12 m3_7988_2700# m3_7988_n2600# 3.39fF
+C13 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
+C14 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C15 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C16 m3_2669_n2600# m3_n2650_n2600# 2.73fF
+C17 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C18 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C19 m3_7988_2700# m3_2669_2700# 2.73fF
+C20 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C21 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C22 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C23 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C24 m3_n13288_2700# c1_n13188_n13100# 58.61fF
+C25 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C26 m3_2669_8000# m3_2669_2700# 3.28fF
+C27 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C28 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C29 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C30 m3_2669_8000# c1_n13188_n13100# 58.61fF
+C31 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C32 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C33 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C34 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C35 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C36 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C37 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C38 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C39 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C40 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C41 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C42 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C43 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C44 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C45 m3_2669_n13200# m3_n2650_n13200# 2.73fF
+C46 m3_2669_n2600# m3_2669_2700# 3.28fF
+C47 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C48 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C49 m3_2669_n2600# c1_n13188_n13100# 58.86fF
+C50 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C51 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C52 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C53 m3_7988_2700# m3_7988_8000# 3.39fF
+C54 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C55 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C56 m3_7988_8000# m3_2669_8000# 2.73fF
+C57 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C58 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C59 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C60 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C61 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C62 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C63 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C64 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
C65 c1_n13188_n13100# VSUBS 2.51fF
C66 m3_7988_n13200# VSUBS 12.57fF
C67 m3_2669_n13200# VSUBS 12.37fF
@@ -126,7 +126,7 @@
.subckt cap1_loop_filter VSUBS in out
Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
+ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
-C0 out in 2.17fF
+C0 in out 2.17fF
C1 in VSUBS -10.03fF
C2 out VSUBS 62.40fF
.ends
@@ -137,13 +137,13 @@
X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
-C1 m3_n4309_50# c1_n4209_n4150# 38.10fF
-C2 m3_n4309_50# m3_n4309_n4250# 2.63fF
-C3 m3_10_n4250# m3_n4309_n4250# 1.75fF
-C4 m3_10_n4250# m3_n4309_50# 1.75fF
-C5 c1_110_n4150# c1_n4209_n4150# 1.32fF
-C6 m3_10_n4250# c1_110_n4150# 81.11fF
+C0 m3_n4309_n4250# m3_10_n4250# 1.75fF
+C1 c1_n4209_n4150# m3_n4309_50# 38.10fF
+C2 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
+C3 m3_10_n4250# c1_110_n4150# 81.11fF
+C4 c1_n4209_n4150# c1_110_n4150# 1.32fF
+C5 m3_n4309_n4250# m3_n4309_50# 2.63fF
+C6 m3_10_n4250# m3_n4309_50# 1.75fF
C7 c1_110_n4150# VSUBS 0.12fF
C8 c1_n4209_n4150# VSUBS 0.12fF
C9 m3_n4309_n4250# VSUBS 8.68fF
@@ -170,25 +170,25 @@
X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
-C1 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
-C2 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
-C3 c1_2269_n6300# c1_n2050_n6300# 1.99fF
-C4 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
-C5 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
-C6 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
-C7 m3_n2150_2200# m3_n6469_2200# 1.75fF
-C8 m3_n2150_n6400# m3_2169_n6400# 1.75fF
-C9 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
-C10 c1_n6369_n6300# m3_n6469_2200# 38.10fF
-C11 m3_n2150_2200# m3_2169_n6400# 1.75fF
-C12 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
-C13 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
-C14 m3_n2150_2200# m3_n2150_n2100# 2.63fF
-C15 m3_n2150_n2100# m3_2169_n6400# 1.75fF
-C16 m3_n2150_2200# c1_n2050_n6300# 38.10fF
-C17 m3_n6469_2200# m3_n6469_n2100# 2.63fF
-C18 c1_2269_n6300# m3_2169_n6400# 121.67fF
+C0 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C1 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C2 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C3 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C4 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C5 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C6 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C7 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C8 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C9 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C10 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C11 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C12 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C13 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C14 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C15 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C16 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C17 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C18 m3_2169_n6400# m3_n2150_n6400# 1.75fF
C19 c1_2269_n6300# VSUBS 0.16fF
C20 c1_n2050_n6300# VSUBS 0.16fF
C21 c1_n6369_n6300# VSUBS 0.16fF
@@ -210,8 +210,8 @@
.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
-C0 a_n88_n300# a_n118_n388# 0.11fF
-C1 a_30_n300# a_n88_n300# 0.61fF
+C0 a_n118_n388# a_n88_n300# 0.11fF
+C1 a_n88_n300# a_30_n300# 0.61fF
C2 a_30_n300# w_n226_n510# 0.40fF
C3 a_n88_n300# w_n226_n510# 0.40fF
C4 a_n118_n388# w_n226_n510# 0.28fF
@@ -239,9 +239,9 @@
Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
-C0 cap3_loop_filter_0/in in 0.79fF
-C1 vc_pex in 0.18fF
-C2 in D0_cap 0.07fF
+C0 vc_pex in 0.18fF
+C1 in D0_cap 0.07fF
+C2 in cap3_loop_filter_0/in 0.79fF
C3 vc_pex vss -38.13fF
C4 res_loop_filter_2/out vss 8.49fF
C5 D0_cap vss 0.04fF
diff --git a/mag/extractions/loop_filter_v2_pex_rc.spice b/mag/extractions/loop_filter_v2_pex_rc.spice
index 37936db..93b9843 100644
--- a/mag/extractions/loop_filter_v2_pex_rc.spice
+++ b/mag/extractions/loop_filter_v2_pex_rc.spice
@@ -30,71 +30,71 @@
X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-C0 c1_n13188_n13100# m3_7988_8000# 60.75fF
-C1 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
-C2 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
-C3 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
-C4 c1_n13188_n13100# m3_n13288_8000# 58.36fF
-C5 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
-C6 m3_2669_n7900# m3_7988_n7900# 2.73fF
-C7 c1_n13188_n13100# m3_n2650_2700# 58.86fF
-C8 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
-C9 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
-C10 m3_7988_2700# m3_2669_2700# 2.73fF
-C11 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
-C12 c1_n13188_n13100# m3_2669_8000# 58.61fF
-C13 c1_n13188_n13100# m3_7988_n7900# 61.01fF
-C14 m3_n2650_2700# m3_n7969_2700# 2.73fF
-C15 m3_2669_n2600# m3_2669_2700# 3.28fF
-C16 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
-C17 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
-C18 m3_7988_2700# c1_n13188_n13100# 61.01fF
-C19 m3_n13288_2700# c1_n13188_n13100# 58.61fF
-C20 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
-C21 m3_n2650_2700# m3_n2650_n2600# 3.28fF
-C22 m3_2669_n2600# m3_2669_n7900# 3.28fF
-C23 m3_7988_n13200# c1_n13188_n13100# 60.75fF
-C24 c1_n13188_n13100# m3_2669_2700# 58.86fF
-C25 m3_7988_n13200# m3_2669_n13200# 2.73fF
-C26 m3_n13288_n2600# m3_n13288_2700# 3.28fF
-C27 m3_n13288_2700# m3_n7969_2700# 2.73fF
-C28 m3_2669_n2600# c1_n13188_n13100# 58.86fF
-C29 m3_n2650_2700# m3_n2650_8000# 3.28fF
-C30 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
-C31 c1_n13188_n13100# m3_n7969_8000# 58.61fF
-C32 m3_n2650_8000# m3_2669_8000# 2.73fF
-C33 m3_7988_n2600# m3_7988_n7900# 3.39fF
-C34 m3_n2650_n13200# m3_2669_n13200# 2.73fF
-C35 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
-C36 m3_2669_8000# m3_7988_8000# 2.73fF
-C37 m3_2669_n7900# c1_n13188_n13100# 58.86fF
-C38 m3_n7969_8000# m3_n7969_2700# 3.28fF
-C39 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
-C40 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
-C41 m3_2669_n7900# m3_2669_n13200# 3.28fF
-C42 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
-C43 m3_n7969_2700# m3_n7969_n2600# 3.28fF
-C44 m3_7988_2700# m3_7988_n2600# 3.39fF
-C45 m3_2669_n13200# c1_n13188_n13100# 58.61fF
-C46 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
-C47 m3_2669_n2600# m3_n2650_n2600# 2.73fF
-C48 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
-C49 c1_n13188_n13100# m3_n7969_2700# 58.86fF
-C50 m3_7988_2700# m3_7988_8000# 3.39fF
-C51 m3_2669_n2600# m3_7988_n2600# 2.73fF
-C52 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
-C53 m3_n13288_2700# m3_n13288_8000# 3.28fF
-C54 m3_2669_n7900# m3_n2650_n7900# 2.73fF
-C55 m3_n2650_8000# m3_n7969_8000# 2.73fF
-C56 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
-C57 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
-C58 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
-C59 m3_n13288_8000# m3_n7969_8000# 2.73fF
-C60 m3_7988_n2600# c1_n13188_n13100# 61.01fF
-C61 m3_n2650_2700# m3_2669_2700# 2.73fF
-C62 c1_n13188_n13100# m3_n2650_8000# 58.61fF
-C63 m3_2669_8000# m3_2669_2700# 3.28fF
-C64 m3_7988_n13200# m3_7988_n7900# 3.39fF
+C0 m3_7988_8000# m3_2669_8000# 2.73fF
+C1 m3_2669_n13200# m3_7988_n13200# 2.73fF
+C2 m3_7988_2700# m3_7988_n2600# 3.39fF
+C3 m3_n7969_2700# c1_n13188_n13100# 58.86fF
+C4 m3_7988_2700# m3_2669_2700# 2.73fF
+C5 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C6 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C7 m3_2669_n13200# m3_n2650_n13200# 2.73fF
+C8 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C9 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C10 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C11 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
+C12 m3_n2650_n2600# m3_n7969_n2600# 2.73fF
+C13 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C14 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C15 m3_n7969_2700# m3_n7969_8000# 3.28fF
+C16 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C17 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C18 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C19 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C20 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C21 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C22 m3_7988_2700# m3_7988_8000# 3.39fF
+C23 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C24 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C25 m3_n2650_8000# m3_2669_8000# 2.73fF
+C26 m3_n13288_2700# c1_n13188_n13100# 58.61fF
+C27 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C28 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C29 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C30 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C31 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C32 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C33 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C34 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C35 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C36 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C37 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C38 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C39 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C40 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C41 m3_n7969_2700# m3_n7969_n2600# 3.28fF
+C42 m3_2669_2700# m3_2669_8000# 3.28fF
+C43 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C44 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C45 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C46 m3_2669_2700# m3_2669_n2600# 3.28fF
+C47 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C48 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C49 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C50 m3_2669_n2600# c1_n13188_n13100# 58.86fF
+C51 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C52 m3_2669_2700# m3_n2650_2700# 2.73fF
+C53 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C54 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C55 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C56 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C57 m3_n2650_n2600# m3_n2650_2700# 3.28fF
+C58 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C59 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C60 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C61 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C62 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C63 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C64 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
C65 c1_n13188_n13100# VSUBS 2.51fF
C66 m3_7988_n13200# VSUBS 12.57fF
C67 m3_2669_n13200# VSUBS 12.37fF
@@ -137,13 +137,13 @@
X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 c1_110_n4150# c1_n4209_n4150# 1.32fF
-C1 m3_10_n4250# m3_n4309_50# 1.75fF
-C2 m3_n4309_50# m3_n4309_n4250# 2.63fF
-C3 c1_n4209_n4150# m3_n4309_50# 38.10fF
-C4 m3_10_n4250# m3_n4309_n4250# 1.75fF
-C5 c1_110_n4150# m3_10_n4250# 81.11fF
-C6 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C0 c1_110_n4150# m3_10_n4250# 81.11fF
+C1 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C2 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C3 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C4 m3_10_n4250# m3_n4309_50# 1.75fF
+C5 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C6 m3_n4309_50# m3_n4309_n4250# 2.63fF
C7 c1_110_n4150# VSUBS 0.12fF
C8 c1_n4209_n4150# VSUBS 0.12fF
C9 m3_n4309_n4250# VSUBS 8.68fF
@@ -170,25 +170,25 @@
X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 m3_2169_n6400# m3_n2150_2200# 1.75fF
-C1 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
-C2 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
-C3 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
-C4 c1_n6369_n6300# m3_n6469_2200# 38.10fF
-C5 m3_2169_n6400# c1_2269_n6300# 121.67fF
-C6 m3_n6469_2200# m3_n6469_n2100# 2.63fF
-C7 m3_n2150_n2100# m3_n2150_2200# 2.63fF
-C8 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
-C9 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
-C10 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
-C11 c1_n2050_n6300# m3_n2150_2200# 38.10fF
-C12 m3_n6469_2200# m3_n2150_2200# 1.75fF
-C13 m3_n2150_n6400# m3_2169_n6400# 1.75fF
-C14 c1_n2050_n6300# c1_2269_n6300# 1.99fF
-C15 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
-C16 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C0 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C1 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C2 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C3 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C4 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C5 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C6 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C7 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C8 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C9 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C10 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C11 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C12 c1_2269_n6300# c1_n2050_n6300# 1.99fF
+C13 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C14 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C15 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C16 m3_n6469_2200# c1_n6369_n6300# 38.10fF
C17 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
-C18 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C18 m3_n2150_n2100# m3_n2150_2200# 2.63fF
C19 c1_2269_n6300# VSUBS 0.16fF
C20 c1_n2050_n6300# VSUBS 0.16fF
C21 c1_n6369_n6300# VSUBS 0.16fF
@@ -203,15 +203,15 @@
.subckt cap2_loop_filter VSUBS in out
Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
-C0 in out 8.08fF
+C0 out in 8.08fF
C1 in VSUBS -16.59fF
C2 out VSUBS 13.00fF
.ends
.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
-C0 a_n88_n300# a_30_n300# 0.61fF
-C1 a_n88_n300# a_n118_n388# 0.11fF
+C0 a_n88_n300# a_n118_n388# 0.11fF
+C1 a_n88_n300# a_30_n300# 0.61fF
C2 a_30_n300# w_n226_n510# 0.40fF
C3 a_n88_n300# w_n226_n510# 0.40fF
C4 a_n118_n388# w_n226_n510# 0.28fF
@@ -239,8 +239,8 @@
Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
-C0 vc_pex in 0.18fF
-C1 cap3_loop_filter_0/in in 0.79fF
+C0 cap3_loop_filter_0/in in 0.79fF
+C1 in vc_pex 0.18fF
C2 D0_cap in 0.07fF
C3 vc_pex vss -38.13fF
C4 res_loop_filter_2/out vss 8.49fF
diff --git a/mag/extractions/loop_filter_v2_pex_rc_port.spice b/mag/extractions/loop_filter_v2_pex_rc_port.spice
new file mode 100644
index 0000000..ca8ad9b
--- /dev/null
+++ b/mag/extractions/loop_filter_v2_pex_rc_port.spice
@@ -0,0 +1,249 @@
+* NGSPICE file created from loop_filter_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C1 m3_n2650_8000# m3_2669_8000# 2.73fF
+C2 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C3 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C4 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C5 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C6 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C7 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C8 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C9 m3_n2650_n2600# m3_n2650_2700# 3.28fF
+C10 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C11 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C12 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C13 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C14 m3_7988_n13200# m3_7988_n7900# 3.39fF
+C15 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C16 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C17 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C18 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C19 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C20 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C21 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C22 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C23 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C24 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C25 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C26 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C27 m3_2669_2700# m3_n2650_2700# 2.73fF
+C28 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C29 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C30 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C31 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C32 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C33 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C34 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C35 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C36 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C37 m3_2669_n13200# m3_n2650_n13200# 2.73fF
+C38 m3_7988_n2600# m3_7988_n7900# 3.39fF
+C39 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C40 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C41 m3_n7969_2700# m3_n7969_8000# 3.28fF
+C42 m3_7988_8000# m3_7988_2700# 3.39fF
+C43 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
+C44 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C45 m3_n7969_2700# c1_n13188_n13100# 58.86fF
+C46 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C47 m3_7988_8000# m3_2669_8000# 2.73fF
+C48 m3_7988_n2600# m3_7988_2700# 3.39fF
+C49 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C50 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C51 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C52 m3_n2650_n2600# m3_n7969_n2600# 2.73fF
+C53 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C54 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C55 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C56 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C57 m3_n13288_2700# c1_n13188_n13100# 58.61fF
+C58 m3_7988_2700# m3_2669_2700# 2.73fF
+C59 m3_n7969_2700# m3_n7969_n2600# 3.28fF
+C60 m3_2669_n2600# m3_2669_2700# 3.28fF
+C61 m3_2669_2700# m3_2669_8000# 3.28fF
+C62 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C63 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C64 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n4309_n4250# m3_n4309_50# 2.63fF
+C1 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C2 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
+C3 m3_10_n4250# c1_110_n4150# 81.11fF
+C4 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C5 m3_10_n4250# m3_n4309_50# 1.75fF
+C6 c1_n4209_n4150# m3_n4309_50# 38.10fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 out in 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C1 c1_2269_n6300# m3_2169_n6400# 121.67fF
+C2 c1_n6369_n6300# m3_n6469_2200# 38.10fF
+C3 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C4 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C5 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C6 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C7 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C8 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C9 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C10 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C11 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C12 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C13 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C14 c1_2269_n6300# c1_n2050_n6300# 1.99fF
+C15 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C16 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C17 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
+C18 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_30_n300# a_n88_n300# 0.61fF
+C1 a_n118_n388# a_n88_n300# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vss in vc_pex D0_cap
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 cap3_loop_filter_0/in in 0.79fF
+C2 D0_cap in 0.07fF
+C3 vc_pex vss -2.18fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -35.63fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
diff --git a/mag/extractions/top_pll_v3_lvs.spice b/mag/extractions/top_pll_v3_lvs.spice
new file mode 100644
index 0000000..24190c1
--- /dev/null
+++ b/mag/extractions/top_pll_v3_lvs.spice
@@ -0,0 +1,861 @@
+* NGSPICE file created from top_pll_v3.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt charge_pump vdd Down out iref pswitch nDown biasp Up nswitch vss w_6648_570#
++ nUp
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS w_n311_n338# a_81_n156# a_111_n125# a_15_n125#
++ a_n173_n125# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd vss m1_187_n605# m1_45_n513# m1_45_n513#
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x1 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+.ends
+
+.subckt clock_inverter vss CLK vdd CLK_d nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt latch_diff nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+.ends
+
+.subckt DFlipFlop vdd vss nQ nCLK Q D CLK
+Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
++ latch_diff
+Xlatch_diff_1 nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D latch_diff
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+.ends
+
+.subckt div_by_2 vdd vss nout_div CLK_2 nCLK_2 o1 o2 CLK out_div
+XDFlipFlop_0 vdd vss nout_div DFlipFlop_0/nCLK out_div nout_div DFlipFlop_0/CLK DFlipFlop
+Xclock_inverter_0 vss CLK vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+.ends
+
+.subckt trans_gate_mux2to8 in vss en_pos en_neg out vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd en_neg in out out en_neg en_neg in sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 en_pos vss en_pos in out out en_pos in sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt mux2to1 vss select_0_neg out_a_0 out_a_1 select_0 vdd in_a
+Xtrans_gate_mux2to8_0 in_a vss select_0_neg select_0 out_a_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss select_0 select_0_neg out_a_1 vdd trans_gate_mux2to8
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt div_by_5 nCLK vdd CLK_5 vss CLK
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 vdd vss nQ2 nCLK DFlipFlop_0/Q DFlipFlop_0/D CLK DFlipFlop
+XDFlipFlop_2 vdd vss DFlipFlop_2/nQ nCLK Q1 DFlipFlop_2/D CLK DFlipFlop
+XDFlipFlop_1 vdd vss nQ0 nCLK Q0 DFlipFlop_1/D CLK DFlipFlop
+XDFlipFlop_3 vdd vss DFlipFlop_3/nQ CLK Q1_shift Q1 nCLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt mux2to4 vss out_b_1 vdd select_0 select_0_neg out_a_0 out_a_1 in_a in_b out_b_0
+Xtrans_gate_mux2to8_0 in_a vss select_0_neg select_0 out_a_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss select_0 select_0_neg out_a_1 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_b vss select_0_neg select_0 out_b_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_3 in_b vss select_0 select_0_neg out_b_1 vdd trans_gate_mux2to8
+.ends
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt prescaler_23 nCLK vss vdd CLK_23 CLK MC
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 vdd vss DFlipFlop_0/nQ nCLK Q1 nCLK_23 CLK DFlipFlop
+XDFlipFlop_1 vdd vss nCLK_23 nCLK Q2 DFlipFlop_1/D CLK DFlipFlop
+XDFlipFlop_2 vdd vss DFlipFlop_2/nQ CLK Q2_d Q2 nCLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt freq_div vss vdd s_0 s_1_n s_1 prescaler_23_0/MC clk_d clk_0 clk_pre s_0_n
++ clk_out_mux21 n_clk_0 n_clk_1 out clk_1 clk_2 in_a clk_5 in_b
+Xdiv_by_2_0 vdd vss div_by_2_0/nout_div clk_2 div_by_2_0/nCLK_2 div_by_2_0/o1 div_by_2_0/o2
++ clk_out_mux21 div_by_2_0/out_div div_by_2
+Xmux2to1_0 vss s_0_n clk_pre clk_5 s_0 vdd clk_out_mux21 mux2to1
+Xinverter_min_x4_0 inverter_min_x4_0/in vss clk_d vdd inverter_min_x4
+Xmux2to1_1 vss s_1_n clk_d clk_2 s_1 vdd out mux2to1
+Xinverter_min_x2_0 clk_out_mux21 inverter_min_x4_0/in vss vdd inverter_min_x2
+Xinverter_min_x2_1 s_1 s_1_n vss vdd inverter_min_x2
+Xinverter_min_x2_2 s_0 s_0_n vss vdd inverter_min_x2
+Xdiv_by_5_0 n_clk_1 vdd clk_5 vss clk_1 div_by_5
+Xmux2to4_0 vss n_clk_1 vdd s_0 s_0_n clk_0 clk_1 in_a in_b n_clk_0 mux2to4
+Xprescaler_23_0 n_clk_0 vss vdd clk_pre clk_0 prescaler_23_0/MC prescaler_23
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+.ends
+
+.subckt buffer_salida in out vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+*C1 t VSUBS 0.42fF
+*C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch vctrl in vbp D0 vss out vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+.ends
+
+.subckt ring_osc vctrl vss vdd D0 out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp D0 vss csvco_branch_1/in vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp D0 vss out_vco vdd csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp D0 vss csvco_branch_2/in
++ vdd csvco_branch
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+.ends
+
+.subckt pfd_cp_interface vss vdd Down QA QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 QB vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS w_n359_n309# a_n63_n116# a_n159_n207#
++ a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt nor_pfd vdd out vss A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss vdd B A out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+.ends
+
+.subckt dff_pfd vss vdd Q CLK Reset
+Xnor_pfd_0 vdd nor_pfd_2/A vss CLK Q nor_pfd
+Xnor_pfd_1 vdd Q vss nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 vdd nor_pfd_3/A vss nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 vdd nor_pfd_2/B vss nor_pfd_3/A Reset nor_pfd
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt and_pfd out vss vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+.ends
+
+.subckt PFD vss vdd Reset Down Up A B
+Xdff_pfd_0 vss vdd Up A Reset dff_pfd
+Xdff_pfd_1 vss vdd Down B Reset dff_pfd
+Xand_pfd_0 Reset vss vdd Up Down and_pfd
+.ends
+
+
+* Top level circuit top_pll_v3
+
+Xcharge_pump_0 vdd Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vss nUp
++ charge_pump
+Xloop_filter_v2_0 lf_vc lf_D0 vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vdd vss n_out_div_2 out_by_2 n_out_by_2 out_buffer_div_2 n_out_buffer_div_2
++ out_to_div out_div_2 div_by_2
+Xfreq_div_0 vss vdd s_0 s_1_n s_1 MC clk_d clk_0 clk_pre s_0_n clk_out_mux21 n_clk_0
++ n_clk_1 out_div clk_1 clk_2_f out_by_2 clk_5 n_out_by_2 freq_div
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vss vdd vco_D0 vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div PFD
+.end
+
diff --git a/mag/extractions/top_pll_v3_lvs_port.spice b/mag/extractions/top_pll_v3_lvs_port.spice
new file mode 100644
index 0000000..aeb46a3
--- /dev/null
+++ b/mag/extractions/top_pll_v3_lvs_port.spice
@@ -0,0 +1,854 @@
+* NGSPICE file created from top_pll_v3.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt charge_pump vdd Down out iref pswitch nDown biasp Up nswitch vss w_6648_570#
++ nUp
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS w_n311_n338# a_81_n156# a_111_n125# a_15_n125#
++ a_n173_n125# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd vss m1_187_n605# m1_45_n513# m1_45_n513#
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x1 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+.ends
+
+.subckt clock_inverter vss CLK vdd CLK_d nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt latch_diff nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+.ends
+
+.subckt DFlipFlop vdd vss nQ nCLK Q D CLK
+Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
++ latch_diff
+Xlatch_diff_1 nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D latch_diff
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+.ends
+
+.subckt div_by_2 vdd vss nout_div CLK_2 nCLK_2 o1 o2 CLK out_div
+XDFlipFlop_0 vdd vss nout_div DFlipFlop_0/nCLK out_div nout_div DFlipFlop_0/CLK DFlipFlop
+Xclock_inverter_0 vss CLK vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+.ends
+
+.subckt trans_gate_mux2to8 in vss en_pos en_neg out vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd en_neg in out out en_neg en_neg in sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 en_pos vss en_pos in out out en_pos in sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt mux2to1 vss select_0_neg out_a_0 out_a_1 select_0 vdd in_a
+Xtrans_gate_mux2to8_0 in_a vss select_0_neg select_0 out_a_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss select_0 select_0_neg out_a_1 vdd trans_gate_mux2to8
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt div_by_5 nCLK vdd CLK_5 vss CLK
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 vdd vss nQ2 nCLK DFlipFlop_0/Q DFlipFlop_0/D CLK DFlipFlop
+XDFlipFlop_2 vdd vss DFlipFlop_2/nQ nCLK Q1 DFlipFlop_2/D CLK DFlipFlop
+XDFlipFlop_1 vdd vss nQ0 nCLK Q0 DFlipFlop_1/D CLK DFlipFlop
+XDFlipFlop_3 vdd vss DFlipFlop_3/nQ CLK Q1_shift Q1 nCLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt mux2to4 vss out_b_1 vdd select_0 select_0_neg out_a_0 out_a_1 in_a in_b out_b_0
+Xtrans_gate_mux2to8_0 in_a vss select_0_neg select_0 out_a_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss select_0 select_0_neg out_a_1 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_b vss select_0_neg select_0 out_b_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_3 in_b vss select_0 select_0_neg out_b_1 vdd trans_gate_mux2to8
+.ends
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt prescaler_23 nCLK vss vdd CLK_23 CLK MC
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 vdd vss DFlipFlop_0/nQ nCLK Q1 nCLK_23 CLK DFlipFlop
+XDFlipFlop_1 vdd vss nCLK_23 nCLK Q2 DFlipFlop_1/D CLK DFlipFlop
+XDFlipFlop_2 vdd vss DFlipFlop_2/nQ CLK Q2_d Q2 nCLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt freq_div vss vdd s_0 s_1_n s_1 prescaler_23_0/MC clk_d clk_0 clk_pre s_0_n
++ clk_out_mux21 n_clk_0 n_clk_1 out clk_1 clk_2 in_a clk_5 in_b
+Xdiv_by_2_0 vdd vss div_by_2_0/nout_div clk_2 div_by_2_0/nCLK_2 div_by_2_0/o1 div_by_2_0/o2
++ clk_out_mux21 div_by_2_0/out_div div_by_2
+Xmux2to1_0 vss s_0_n clk_pre clk_5 s_0 vdd clk_out_mux21 mux2to1
+Xinverter_min_x4_0 inverter_min_x4_0/in vss clk_d vdd inverter_min_x4
+Xmux2to1_1 vss s_1_n clk_d clk_2 s_1 vdd out mux2to1
+Xinverter_min_x2_0 clk_out_mux21 inverter_min_x4_0/in vss vdd inverter_min_x2
+Xinverter_min_x2_1 s_1 s_1_n vss vdd inverter_min_x2
+Xinverter_min_x2_2 s_0 s_0_n vss vdd inverter_min_x2
+Xdiv_by_5_0 n_clk_1 vdd clk_5 vss clk_1 div_by_5
+Xmux2to4_0 vss n_clk_1 vdd s_0 s_0_n clk_0 clk_1 in_a in_b n_clk_0 mux2to4
+Xprescaler_23_0 n_clk_0 vss vdd clk_pre clk_0 prescaler_23_0/MC prescaler_23
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+.ends
+
+.subckt buffer_salida in out vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt csvco_branch vctrl in vbp D0 vss out vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+.ends
+
+.subckt ring_osc vctrl vss vdd D0 out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp D0 vss csvco_branch_1/in vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp D0 vss out_vco vdd csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp D0 vss csvco_branch_2/in
++ vdd csvco_branch
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+.ends
+
+.subckt pfd_cp_interface vss vdd Down QA QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 QB vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS w_n359_n309# a_n63_n116# a_n159_n207#
++ a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt nor_pfd vdd out vss A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss vdd B A out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+.ends
+
+.subckt dff_pfd vss vdd Q CLK Reset
+Xnor_pfd_0 vdd nor_pfd_2/A vss CLK Q nor_pfd
+Xnor_pfd_1 vdd Q vss nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 vdd nor_pfd_3/A vss nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 vdd nor_pfd_2/B vss nor_pfd_3/A Reset nor_pfd
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt and_pfd out vss vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+.ends
+
+.subckt PFD vss vdd Reset Down Up A B
+Xdff_pfd_0 vss vdd Up A Reset dff_pfd
+Xdff_pfd_1 vss vdd Down B Reset dff_pfd
+Xand_pfd_0 Reset vss vdd Up Down and_pfd
+.ends
+
+.subckt top_pll_v3 pfd_reset in_ref QA QB Down nDown Up nUp biasp pswitch nswitch
++ vco_vctrl vco_out out_first_buffer out_to_div iref_cp vdd n_clk_1 clk_1 clk_5 clk_pre
++ clk_out_mux21 clk_d clk_2_f out_div s_1 s_1_n MC lf_vc vco_D0
+Xcharge_pump_0 vdd Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vss nUp
++ charge_pump
+Xloop_filter_v2_0 lf_vc lf_D0 vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vdd vss n_out_div_2 out_by_2 n_out_by_2 out_buffer_div_2 n_out_buffer_div_2
++ out_to_div out_div_2 div_by_2
+Xfreq_div_0 vss vdd s_0 s_1_n s_1 MC clk_d clk_0 clk_pre s_0_n clk_out_mux21 n_clk_0
++ n_clk_1 out_div clk_1 clk_2_f out_by_2 clk_5 n_out_by_2 freq_div
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vss vdd vco_D0 vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div PFD
+.ends
+
diff --git a/mag/extractions/top_pll_v3_pex_c.spice b/mag/extractions/top_pll_v3_pex_c.spice
new file mode 100644
index 0000000..4bd8c92
--- /dev/null
+++ b/mag/extractions/top_pll_v3_pex_c.spice
@@ -0,0 +1,3520 @@
+* NGSPICE file created from top_pll_v3.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_2261_n486# w_n2457_n634# 0.02fF
+C1 a_1803_n486# w_n2457_n634# 0.02fF
+C2 a_n29_n486# w_n2457_n634# 0.02fF
+C3 a_n1861_n486# w_n2457_n634# 0.02fF
+C4 a_429_n486# w_n2457_n634# 0.02fF
+C5 a_n945_n486# w_n2457_n634# 0.02fF
+C6 a_887_n486# w_n2457_n634# 0.02fF
+C7 a_1345_n486# w_n2457_n634# 0.02fF
+C8 w_n2457_n634# a_n2319_n486# 0.02fF
+C9 a_n1403_n486# w_n2457_n634# 0.02fF
+C10 a_n487_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_399_n75# a_591_n75# 0.08fF
+C1 a_n657_n75# a_n369_n75# 0.05fF
+C2 a_n945_n75# a_n657_n75# 0.05fF
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+C4 a_495_n75# a_879_n75# 0.03fF
+C5 a_n177_n75# a_15_n75# 0.08fF
+C6 a_n273_n75# a_n465_n75# 0.08fF
+C7 a_n273_n75# a_n177_n75# 0.22fF
+C8 a_495_n75# a_591_n75# 0.22fF
+C9 a_n657_n75# a_n465_n75# 0.08fF
+C10 a_n1229_n75# a_n1137_n75# 0.22fF
+C11 a_687_n75# a_783_n75# 0.22fF
+C12 a_111_n75# a_n177_n75# 0.05fF
+C13 a_n273_n75# a_n561_n75# 0.05fF
+C14 a_n1041_n75# a_n753_n75# 0.05fF
+C15 a_n561_n75# a_n657_n75# 0.22fF
+C16 a_783_n75# a_1167_n75# 0.03fF
+C17 a_n1229_n75# a_n1041_n75# 0.08fF
+C18 a_687_n75# a_879_n75# 0.08fF
+C19 a_207_n75# a_303_n75# 0.22fF
+C20 a_n753_n75# a_n657_n75# 0.22fF
+C21 a_591_n75# a_687_n75# 0.22fF
+C22 a_207_n75# a_n81_n75# 0.05fF
+C23 a_879_n75# a_1167_n75# 0.05fF
+C24 a_n1137_n75# a_n1041_n75# 0.22fF
+C25 a_783_n75# a_879_n75# 0.22fF
+C26 a_687_n75# a_975_n75# 0.05fF
+C27 a_687_n75# a_1071_n75# 0.03fF
+C28 a_207_n75# a_15_n75# 0.08fF
+C29 a_207_n75# a_399_n75# 0.08fF
+C30 a_591_n75# a_783_n75# 0.08fF
+C31 a_n945_n75# a_n849_n75# 0.22fF
+C32 a_303_n75# a_n81_n75# 0.03fF
+C33 a_975_n75# a_1167_n75# 0.08fF
+C34 a_783_n75# a_975_n75# 0.08fF
+C35 a_1071_n75# a_1167_n75# 0.22fF
+C36 a_111_n75# a_207_n75# 0.22fF
+C37 a_n849_n75# a_n465_n75# 0.03fF
+C38 a_783_n75# a_1071_n75# 0.05fF
+C39 a_303_n75# a_15_n75# 0.05fF
+C40 a_303_n75# a_399_n75# 0.22fF
+C41 a_207_n75# a_495_n75# 0.05fF
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+C43 a_591_n75# a_879_n75# 0.05fF
+C44 a_n273_n75# a_n81_n75# 0.08fF
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+C46 a_111_n75# a_303_n75# 0.08fF
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+C48 a_111_n75# a_n81_n75# 0.08fF
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+C50 a_879_n75# a_1071_n75# 0.08fF
+C51 a_n369_n75# a_n465_n75# 0.22fF
+C52 a_n177_n75# a_n369_n75# 0.08fF
+C53 a_n273_n75# a_15_n75# 0.05fF
+C54 a_399_n75# a_15_n75# 0.03fF
+C55 a_303_n75# a_495_n75# 0.08fF
+C56 a_591_n75# a_975_n75# 0.03fF
+C57 a_n753_n75# a_n849_n75# 0.22fF
+C58 a_n273_n75# a_n657_n75# 0.03fF
+C59 a_111_n75# a_15_n75# 0.22fF
+C60 a_111_n75# a_n273_n75# 0.03fF
+C61 a_111_n75# a_399_n75# 0.05fF
+C62 a_n177_n75# a_n465_n75# 0.05fF
+C63 a_n561_n75# a_n369_n75# 0.08fF
+C64 a_n945_n75# a_n561_n75# 0.03fF
+C65 a_975_n75# a_1071_n75# 0.22fF
+C66 a_399_n75# a_495_n75# 0.22fF
+C67 a_n1229_n75# a_n849_n75# 0.03fF
+C68 a_n561_n75# a_n465_n75# 0.22fF
+C69 a_n177_n75# a_n561_n75# 0.03fF
+C70 a_n753_n75# a_n369_n75# 0.03fF
+C71 a_111_n75# a_495_n75# 0.03fF
+C72 a_n945_n75# a_n753_n75# 0.08fF
+C73 a_303_n75# a_687_n75# 0.03fF
+C74 a_n1137_n75# a_n849_n75# 0.05fF
+C75 a_n753_n75# a_n465_n75# 0.05fF
+C76 a_n1229_n75# a_n945_n75# 0.05fF
+C77 a_399_n75# a_687_n75# 0.05fF
+C78 a_n753_n75# a_n561_n75# 0.08fF
+C79 a_n1041_n75# a_n849_n75# 0.08fF
+C80 a_n1137_n75# a_n945_n75# 0.08fF
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+C82 a_495_n75# a_687_n75# 0.08fF
+C83 a_399_n75# a_783_n75# 0.03fF
+C84 a_207_n75# a_n177_n75# 0.03fF
+C85 a_n81_n75# a_n369_n75# 0.05fF
+C86 a_303_n75# a_591_n75# 0.05fF
+C87 a_n1041_n75# a_n945_n75# 0.22fF
+C88 a_n849_n75# a_n657_n75# 0.08fF
+C89 a_495_n75# a_783_n75# 0.05fF
+C90 a_n369_n75# a_15_n75# 0.03fF
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+C92 a_n273_n75# a_n369_n75# 0.22fF
+C93 a_n177_n75# a_n81_n75# 0.22fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n609_n75# a_n989_n75# 0.03fF
+C1 a_639_n75# a_831_n75# 0.08fF
+C2 a_n513_n75# a_n225_n75# 0.05fF
+C3 a_n609_n75# a_n225_n75# 0.03fF
+C4 a_63_n75# a_n321_n75# 0.03fF
+C5 a_735_n75# a_351_n75# 0.03fF
+C6 a_639_n75# a_447_n75# 0.08fF
+C7 a_n417_n75# a_n33_n75# 0.03fF
+C8 a_n129_n75# a_63_n75# 0.08fF
+C9 a_n897_n75# a_n513_n75# 0.03fF
+C10 a_n609_n75# a_n897_n75# 0.05fF
+C11 a_351_n75# a_n33_n75# 0.03fF
+C12 a_n513_n75# a_n321_n75# 0.08fF
+C13 a_735_n75# a_831_n75# 0.22fF
+C14 a_543_n75# a_351_n75# 0.08fF
+C15 a_n129_n75# a_n513_n75# 0.03fF
+C16 a_n609_n75# a_n321_n75# 0.05fF
+C17 a_n927_n101# a_33_n101# 0.08fF
+C18 a_159_n75# a_n33_n75# 0.08fF
+C19 a_n513_n75# a_n801_n75# 0.05fF
+C20 a_543_n75# a_159_n75# 0.03fF
+C21 a_n609_n75# a_n801_n75# 0.08fF
+C22 a_735_n75# a_447_n75# 0.05fF
+C23 a_543_n75# a_831_n75# 0.05fF
+C24 a_351_n75# a_63_n75# 0.05fF
+C25 a_639_n75# a_735_n75# 0.22fF
+C26 a_n417_n75# a_n513_n75# 0.22fF
+C27 a_n609_n75# a_n417_n75# 0.08fF
+C28 a_543_n75# a_447_n75# 0.22fF
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+C30 a_543_n75# a_639_n75# 0.22fF
+C31 a_447_n75# a_63_n75# 0.03fF
+C32 a_n989_n75# a_n705_n75# 0.05fF
+C33 a_543_n75# a_735_n75# 0.08fF
+C34 a_n129_n75# a_255_n75# 0.03fF
+C35 a_n897_n75# a_n705_n75# 0.08fF
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+C38 a_n33_n75# a_63_n75# 0.22fF
+C39 a_n417_n75# a_n705_n75# 0.05fF
+C40 a_351_n75# a_255_n75# 0.22fF
+C41 a_n989_n75# a_n897_n75# 0.22fF
+C42 a_831_n75# a_927_n75# 0.22fF
+C43 a_159_n75# a_255_n75# 0.22fF
+C44 a_n989_n75# a_n801_n75# 0.08fF
+C45 a_n225_n75# a_n321_n75# 0.22fF
+C46 a_n129_n75# a_n225_n75# 0.22fF
+C47 a_639_n75# a_927_n75# 0.05fF
+C48 a_447_n75# a_255_n75# 0.08fF
+C49 a_n417_n75# a_n225_n75# 0.08fF
+C50 a_n129_n75# a_n321_n75# 0.08fF
+C51 a_639_n75# a_255_n75# 0.03fF
+C52 a_n897_n75# a_n801_n75# 0.22fF
+C53 a_n609_n75# a_n513_n75# 0.22fF
+C54 a_735_n75# a_927_n75# 0.08fF
+C55 a_n417_n75# a_n321_n75# 0.22fF
+C56 a_n129_n75# a_n417_n75# 0.05fF
+C57 a_159_n75# a_n225_n75# 0.03fF
+C58 a_n417_n75# a_n801_n75# 0.03fF
+C59 a_543_n75# a_927_n75# 0.03fF
+C60 a_255_n75# a_n33_n75# 0.05fF
+C61 a_159_n75# a_n129_n75# 0.05fF
+C62 a_543_n75# a_255_n75# 0.05fF
+C63 a_255_n75# a_63_n75# 0.08fF
+C64 a_351_n75# a_159_n75# 0.08fF
+C65 a_n513_n75# a_n705_n75# 0.08fF
+C66 a_n609_n75# a_n705_n75# 0.22fF
+C67 a_n33_n75# a_n225_n75# 0.08fF
+C68 a_351_n75# a_447_n75# 0.22fF
+C69 a_447_n75# a_159_n75# 0.05fF
+C70 a_639_n75# a_351_n75# 0.05fF
+C71 a_n33_n75# a_n321_n75# 0.05fF
+C72 a_n225_n75# a_63_n75# 0.05fF
+C73 a_n129_n75# a_n33_n75# 0.22fF
+C74 a_447_n75# a_831_n75# 0.03fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n989_n150# a_n609_n150# 0.07fF
+C1 a_159_n150# a_n129_n150# 0.10fF
+C2 a_351_n150# a_543_n150# 0.16fF
+C3 a_n129_n150# a_n513_n150# 0.07fF
+C4 a_n321_n150# a_n129_n150# 0.16fF
+C5 a_n609_n150# a_n225_n150# 0.07fF
+C6 a_n801_n150# a_n705_n150# 0.43fF
+C7 a_159_n150# a_63_n150# 0.43fF
+C8 a_351_n150# a_159_n150# 0.16fF
+C9 a_927_n150# a_543_n150# 0.07fF
+C10 a_n129_n150# a_255_n150# 0.07fF
+C11 a_639_n150# a_255_n150# 0.07fF
+C12 a_n989_n150# a_n897_n150# 0.43fF
+C13 a_n321_n150# a_63_n150# 0.07fF
+C14 a_n33_n150# a_n225_n150# 0.16fF
+C15 a_63_n150# a_255_n150# 0.16fF
+C16 a_351_n150# a_255_n150# 0.43fF
+C17 a_735_n150# a_639_n150# 0.43fF
+C18 a_351_n150# a_735_n150# 0.07fF
+C19 a_n33_n150# a_n129_n150# 0.43fF
+C20 a_831_n150# a_639_n150# 0.16fF
+C21 a_n801_n150# a_n417_n150# 0.07fF
+C22 a_n927_n247# a_33_n247# 0.09fF
+C23 a_n33_n150# a_63_n150# 0.43fF
+C24 a_351_n150# a_n33_n150# 0.07fF
+C25 a_927_n150# a_735_n150# 0.16fF
+C26 a_n705_n150# a_n417_n150# 0.10fF
+C27 a_n801_n150# a_n513_n150# 0.10fF
+C28 a_447_n150# a_543_n150# 0.43fF
+C29 a_831_n150# a_927_n150# 0.43fF
+C30 a_n705_n150# a_n513_n150# 0.16fF
+C31 a_n321_n150# a_n705_n150# 0.07fF
+C32 a_159_n150# a_447_n150# 0.10fF
+C33 a_n801_n150# a_n609_n150# 0.16fF
+C34 a_n705_n150# a_n609_n150# 0.43fF
+C35 a_447_n150# a_255_n150# 0.16fF
+C36 a_159_n150# a_543_n150# 0.07fF
+C37 a_n225_n150# a_n129_n150# 0.43fF
+C38 a_n897_n150# a_n801_n150# 0.43fF
+C39 a_63_n150# a_n225_n150# 0.10fF
+C40 a_447_n150# a_735_n150# 0.10fF
+C41 a_255_n150# a_543_n150# 0.10fF
+C42 a_n417_n150# a_n513_n150# 0.43fF
+C43 a_n321_n150# a_n417_n150# 0.43fF
+C44 a_n897_n150# a_n705_n150# 0.16fF
+C45 a_159_n150# a_255_n150# 0.43fF
+C46 a_63_n150# a_n129_n150# 0.16fF
+C47 a_735_n150# a_543_n150# 0.16fF
+C48 a_831_n150# a_447_n150# 0.07fF
+C49 a_351_n150# a_639_n150# 0.10fF
+C50 a_n609_n150# a_n417_n150# 0.16fF
+C51 a_n321_n150# a_n513_n150# 0.16fF
+C52 a_351_n150# a_63_n150# 0.10fF
+C53 a_831_n150# a_543_n150# 0.10fF
+C54 a_n989_n150# a_n801_n150# 0.16fF
+C55 a_927_n150# a_639_n150# 0.10fF
+C56 a_n609_n150# a_n513_n150# 0.43fF
+C57 a_n321_n150# a_n609_n150# 0.10fF
+C58 a_n33_n150# a_n417_n150# 0.07fF
+C59 a_n989_n150# a_n705_n150# 0.10fF
+C60 a_159_n150# a_n33_n150# 0.16fF
+C61 a_n33_n150# a_n321_n150# 0.10fF
+C62 a_n33_n150# a_255_n150# 0.10fF
+C63 a_n897_n150# a_n513_n150# 0.07fF
+C64 a_831_n150# a_735_n150# 0.43fF
+C65 a_n897_n150# a_n609_n150# 0.10fF
+C66 a_447_n150# a_639_n150# 0.16fF
+C67 a_n225_n150# a_n417_n150# 0.16fF
+C68 a_447_n150# a_63_n150# 0.07fF
+C69 a_159_n150# a_n225_n150# 0.07fF
+C70 a_351_n150# a_447_n150# 0.43fF
+C71 a_639_n150# a_543_n150# 0.43fF
+C72 a_n225_n150# a_n513_n150# 0.10fF
+C73 a_n417_n150# a_n129_n150# 0.10fF
+C74 a_n321_n150# a_n225_n150# 0.43fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n1103_n44# a_n1461_n44# 0.04fF
+C1 a_1761_n44# a_1403_n44# 0.04fF
+C2 a_n387_n44# a_n29_n44# 0.04fF
+C3 a_n745_n44# a_n387_n44# 0.04fF
+C4 a_1045_n44# a_1403_n44# 0.04fF
+C5 a_687_n44# a_329_n44# 0.04fF
+C6 a_329_n44# a_n29_n44# 0.04fF
+C7 a_n745_n44# a_n1103_n44# 0.04fF
+C8 a_n1461_n44# a_n1819_n44# 0.04fF
+C9 a_687_n44# a_1045_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n561_n150# a_n177_n150# 0.07fF
+C1 a_n945_n150# a_n1229_n150# 0.10fF
+C2 a_783_n150# a_591_n150# 0.16fF
+C3 a_n657_n150# a_n465_n150# 0.16fF
+C4 a_975_n150# a_879_n150# 0.43fF
+C5 a_n1229_n150# a_n849_n150# 0.07fF
+C6 a_n657_n150# a_n753_n150# 0.43fF
+C7 a_n369_n150# a_n273_n150# 0.43fF
+C8 a_n945_n150# a_n1041_n150# 0.43fF
+C9 a_495_n150# a_111_n150# 0.07fF
+C10 a_207_n150# a_591_n150# 0.07fF
+C11 a_975_n150# a_1071_n150# 0.43fF
+C12 a_n1041_n150# a_n849_n150# 0.16fF
+C13 a_n561_n150# a_n465_n150# 0.43fF
+C14 a_207_n150# a_n177_n150# 0.07fF
+C15 a_15_n150# a_n369_n150# 0.07fF
+C16 a_687_n150# a_591_n150# 0.43fF
+C17 a_783_n150# a_399_n150# 0.07fF
+C18 a_303_n150# a_207_n150# 0.43fF
+C19 a_n561_n150# a_n753_n150# 0.16fF
+C20 a_15_n150# a_n273_n150# 0.10fF
+C21 a_n657_n150# a_n561_n150# 0.43fF
+C22 a_n81_n150# a_207_n150# 0.10fF
+C23 a_879_n150# a_1071_n150# 0.16fF
+C24 a_687_n150# a_303_n150# 0.07fF
+C25 a_n1137_n150# a_n1229_n150# 0.43fF
+C26 a_495_n150# a_591_n150# 0.43fF
+C27 a_399_n150# a_207_n150# 0.16fF
+C28 a_783_n150# a_1167_n150# 0.07fF
+C29 a_n273_n150# a_111_n150# 0.07fF
+C30 a_n1137_n150# a_n1041_n150# 0.43fF
+C31 a_495_n150# a_303_n150# 0.16fF
+C32 a_687_n150# a_399_n150# 0.10fF
+C33 a_975_n150# w_n1367_n369# 0.05fF
+C34 a_975_n150# a_591_n150# 0.07fF
+C35 a_15_n150# a_111_n150# 0.43fF
+C36 a_n753_n150# a_n1041_n150# 0.10fF
+C37 a_399_n150# a_495_n150# 0.43fF
+C38 a_n657_n150# a_n1041_n150# 0.07fF
+C39 a_879_n150# w_n1367_n369# 0.04fF
+C40 a_n369_n150# a_n177_n150# 0.16fF
+C41 a_879_n150# a_591_n150# 0.10fF
+C42 a_n273_n150# a_n177_n150# 0.43fF
+C43 w_n1367_n369# a_1071_n150# 0.07fF
+C44 a_n81_n150# a_n369_n150# 0.10fF
+C45 a_n81_n150# a_n273_n150# 0.16fF
+C46 a_n465_n150# a_n369_n150# 0.43fF
+C47 a_15_n150# a_n177_n150# 0.16fF
+C48 a_15_n150# a_303_n150# 0.10fF
+C49 a_687_n150# a_783_n150# 0.43fF
+C50 a_n753_n150# a_n369_n150# 0.07fF
+C51 a_n465_n150# a_n273_n150# 0.16fF
+C52 a_975_n150# a_1167_n150# 0.16fF
+C53 a_15_n150# a_n81_n150# 0.43fF
+C54 a_n945_n150# a_n849_n150# 0.43fF
+C55 a_n657_n150# a_n369_n150# 0.10fF
+C56 a_n177_n150# a_111_n150# 0.10fF
+C57 a_n1041_n150# a_n1229_n150# 0.16fF
+C58 a_303_n150# a_111_n150# 0.16fF
+C59 a_399_n150# a_15_n150# 0.07fF
+C60 a_783_n150# a_495_n150# 0.10fF
+C61 a_n657_n150# a_n273_n150# 0.07fF
+C62 a_n81_n150# a_111_n150# 0.16fF
+C63 a_879_n150# a_1167_n150# 0.10fF
+C64 a_399_n150# a_111_n150# 0.10fF
+C65 a_n561_n150# a_n369_n150# 0.16fF
+C66 a_495_n150# a_207_n150# 0.10fF
+C67 a_783_n150# a_975_n150# 0.16fF
+C68 a_1071_n150# a_1167_n150# 0.43fF
+C69 a_n561_n150# a_n273_n150# 0.10fF
+C70 a_n945_n150# a_n1137_n150# 0.16fF
+C71 a_303_n150# a_591_n150# 0.10fF
+C72 a_687_n150# a_495_n150# 0.16fF
+C73 a_n1137_n150# a_n849_n150# 0.10fF
+C74 a_783_n150# a_879_n150# 0.43fF
+C75 a_n945_n150# a_n753_n150# 0.16fF
+C76 a_n465_n150# a_n849_n150# 0.07fF
+C77 a_399_n150# a_591_n150# 0.16fF
+C78 a_n81_n150# a_n177_n150# 0.43fF
+C79 a_n657_n150# a_n945_n150# 0.10fF
+C80 a_687_n150# a_975_n150# 0.10fF
+C81 a_n81_n150# a_303_n150# 0.07fF
+C82 a_n753_n150# a_n849_n150# 0.43fF
+C83 a_783_n150# a_1071_n150# 0.10fF
+C84 a_399_n150# a_303_n150# 0.43fF
+C85 a_n657_n150# a_n849_n150# 0.16fF
+C86 a_n465_n150# a_n177_n150# 0.10fF
+C87 w_n1367_n369# a_1167_n150# 0.14fF
+C88 a_15_n150# a_207_n150# 0.16fF
+C89 a_n561_n150# a_n945_n150# 0.07fF
+C90 a_687_n150# a_879_n150# 0.16fF
+C91 a_n81_n150# a_n465_n150# 0.07fF
+C92 a_n561_n150# a_n849_n150# 0.10fF
+C93 a_687_n150# a_1071_n150# 0.07fF
+C94 a_495_n150# a_879_n150# 0.07fF
+C95 a_207_n150# a_111_n150# 0.43fF
+C96 a_n753_n150# a_n1137_n150# 0.07fF
+C97 a_n753_n150# a_n465_n150# 0.10fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vss vdd nUp Down w_2544_775# out pswitch iref nDown biasp
++ Up w_6648_570#
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 nswitch pswitch 0.06fF
+C1 pswitch Up 0.70fF
+C2 pswitch vdd 3.98fF
+C3 nswitch out 1.28fF
+C4 out vdd 6.66fF
+C5 out pswitch 4.91fF
+C6 nDown Down 0.13fF
+C7 nUp Down 0.25fF
+C8 iref biasp 0.80fF
+C9 nswitch nDown 0.31fF
+C10 nUp Up 0.15fF
+C11 nswitch Down 2.27fF
+C12 nswitch iref 1.91fF
+C13 nswitch biasp 0.03fF
+C14 nUp pswitch 5.66fF
+C15 biasp vdd 2.64fF
+C16 pswitch biasp 3.11fF
+C17 nswitch vdd 0.07fF
+C18 nUp out 0.31fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_2669_n2600# c1_n13188_n13100# 58.86fF
+C1 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C2 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C3 m3_2669_2700# m3_n2650_2700# 2.73fF
+C4 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C5 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C6 m3_2669_8000# m3_2669_2700# 3.28fF
+C7 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C8 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C9 m3_n7969_2700# c1_n13188_n13100# 58.86fF
+C10 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C11 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C12 m3_7988_2700# m3_7988_n2600# 3.39fF
+C13 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C14 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C15 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C16 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C17 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C18 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
+C19 m3_2669_n13200# m3_n2650_n13200# 2.73fF
+C20 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C21 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C22 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
+C23 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C24 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C25 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C26 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C27 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C28 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C29 m3_2669_8000# c1_n13188_n13100# 58.61fF
+C30 m3_n2650_n2600# m3_n2650_n7900# 3.28fF
+C31 m3_n2650_n2600# m3_n2650_2700# 3.28fF
+C32 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C33 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C34 m3_n2650_n2600# m3_n7969_n2600# 2.73fF
+C35 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C36 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C37 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C38 m3_n13288_2700# c1_n13188_n13100# 58.61fF
+C39 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C40 m3_n7969_2700# m3_n7969_8000# 3.28fF
+C41 m3_7988_2700# m3_7988_8000# 3.39fF
+C42 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C43 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C44 m3_2669_2700# m3_7988_2700# 2.73fF
+C45 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C46 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C47 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C48 m3_2669_2700# m3_2669_n2600# 3.28fF
+C49 m3_2669_n13200# m3_7988_n13200# 2.73fF
+C50 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C51 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C52 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C53 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C54 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C55 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C56 m3_2669_8000# m3_n2650_8000# 2.73fF
+C57 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C58 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C59 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C60 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C61 m3_n7969_2700# m3_n7969_n2600# 3.28fF
+C62 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C63 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C64 m3_2669_8000# m3_7988_8000# 2.73fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
+C1 m3_n4309_n4250# m3_10_n4250# 1.75fF
+C2 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C3 m3_n4309_50# m3_10_n4250# 1.75fF
+C4 m3_n4309_n4250# m3_n4309_50# 2.63fF
+C5 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C6 c1_110_n4150# m3_10_n4250# 81.11fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 out in 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C1 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C2 c1_2269_n6300# m3_2169_n6400# 121.67fF
+C3 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C4 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
+C5 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C6 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C7 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C8 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C9 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C10 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C11 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C12 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C13 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C14 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C15 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C16 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C17 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C18 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 out in 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_n118_n388# a_n88_n300# 0.11fF
+C1 a_30_n300# a_n88_n300# 0.61fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 in cap3_loop_filter_0/in 0.79fF
+C2 in D0_cap 0.07fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS w_n311_n338# a_81_n156# a_111_n125# a_15_n125#
++ a_n173_n125# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n15_n156# a_81_n156# 0.02fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_111_n125# a_15_n125# 0.36fF
+C3 a_n173_n125# a_111_n125# 0.08fF
+C4 a_15_n125# a_n81_n125# 0.36fF
+C5 a_n173_n125# a_n81_n125# 0.36fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_n15_n156# a_n111_n156# 0.02fF
+C8 a_111_n125# VSUBS 0.03fF
+C9 a_15_n125# VSUBS 0.03fF
+C10 a_n81_n125# VSUBS 0.03fF
+C11 a_n173_n125# VSUBS 0.03fF
+C12 a_81_n156# VSUBS 0.05fF
+C13 a_n15_n156# VSUBS 0.05fF
+C14 a_n111_n156# VSUBS 0.05fF
+C15 w_n311_n338# VSUBS 1.56fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_15_n125# 0.36fF
+C1 a_n173_n125# a_111_n125# 0.08fF
+C2 a_111_n125# a_n81_n125# 0.13fF
+C3 a_n111_n151# a_n15_n151# 0.02fF
+C4 a_n15_n151# a_81_n151# 0.02fF
+C5 a_n173_n125# a_15_n125# 0.13fF
+C6 a_n81_n125# a_15_n125# 0.36fF
+C7 a_n173_n125# a_n81_n125# 0.36fF
+C8 a_111_n125# w_n311_n335# 0.04fF
+C9 a_15_n125# w_n311_n335# 0.04fF
+C10 a_n81_n125# w_n311_n335# 0.04fF
+C11 a_n173_n125# w_n311_n335# 0.04fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# vss m1_45_n513# vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd vss m1_187_n605# m1_45_n513# m1_45_n513#
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_45_n513# m1_187_n605# 0.36fF
+C1 m1_187_n605# vdd 0.55fF
+C2 m1_45_n513# vdd 0.69fF
+C3 m1_187_n605# vss 0.73fF
+C4 m1_45_n513# vss 1.10fF
+C5 vdd vss 2.55fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n311_n344# a_n81_n125# 0.09fF
+C1 w_n311_n344# a_111_n125# 0.14fF
+C2 w_n311_n344# a_n173_n125# 0.14fF
+C3 w_n311_n344# a_15_n125# 0.09fF
+C4 a_n81_n125# a_111_n125# 0.13fF
+C5 a_n173_n125# a_n81_n125# 0.36fF
+C6 a_n173_n125# a_111_n125# 0.08fF
+C7 a_15_n125# a_n81_n125# 0.36fF
+C8 a_15_n125# a_111_n125# 0.36fF
+C9 a_n173_n125# a_15_n125# 0.13fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_15_n125# 0.13fF
+C1 a_n173_n125# a_n81_n125# 0.36fF
+C2 a_n81_n125# a_15_n125# 0.36fF
+C3 a_n173_n125# a_111_n125# 0.08fF
+C4 a_111_n125# a_15_n125# 0.36fF
+C5 a_n81_n125# a_111_n125# 0.13fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 in out 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d vss inverter_cp_x1_0/out vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd inverter_cp_x1_2/in 0.21fF
+C1 inverter_cp_x1_2/in CLK 0.31fF
+C2 vdd CLK 0.36fF
+C3 inverter_cp_x1_0/out vdd 0.21fF
+C4 nCLK_d vdd 0.03fF
+C5 inverter_cp_x1_0/out CLK 0.31fF
+C6 inverter_cp_x1_0/out nCLK_d 0.11fF
+C7 inverter_cp_x1_2/in CLK_d 0.12fF
+C8 vdd CLK_d 0.03fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.69fF
+C12 CLK vss 3.03fF
+C13 vdd vss 15.46fF
+C14 nCLK_d vss 1.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_n125_n95# 0.11fF
+C1 a_63_n95# a_n33_n95# 0.28fF
+C2 a_63_n95# a_n125_n95# 0.10fF
+C3 a_63_n95# w_n263_n314# 0.11fF
+C4 a_n125_n95# a_n33_n95# 0.28fF
+C5 w_n263_n314# a_n33_n95# 0.08fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n129_n213# a_n81_n125# 0.10fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_n173_n125# a_n81_n125# 0.36fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n173_n125# a_n129_n213# 0.02fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_111_n125# a_n129_n213# 0.01fF
+C7 a_n81_n125# a_15_n125# 0.36fF
+C8 a_111_n125# a_n173_n125# 0.08fF
+C9 a_n129_n213# a_15_n125# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n81_n183# a_n33_n95# 0.10fF
+C1 a_n125_n95# a_n33_n95# 0.88fF
+C2 a_n125_n95# a_n81_n183# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 nQ nD 0.05fF
+C1 nQ D 0.05fF
+C2 nQ vdd 0.16fF
+C3 Q nD 0.05fF
+C4 Q D 0.05fF
+C5 Q vdd 0.16fF
+C6 nQ m1_657_280# 1.41fF
+C7 CLK m1_657_280# 0.24fF
+C8 Q m1_657_280# 0.94fF
+C9 Q nQ 0.93fF
+C10 D vss 0.53fF
+C11 m1_657_280# vss 1.88fF
+C12 nD vss 0.16fF
+C13 CLK vss 0.87fF
+C14 Q vss -0.55fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vdd vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ nCLK latch_diff_0/nD Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D
++ CLK clock_inverter_0/inverter_cp_x1_0/out
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 nQ latch_diff_1/D 0.11fF
+C1 latch_diff_0/nD vdd 0.14fF
+C2 latch_diff_0/D latch_diff_1/D 0.11fF
+C3 latch_diff_1/D vdd 0.01fF
+C4 latch_diff_0/D vdd 0.09fF
+C5 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
+C6 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C7 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
+C8 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C9 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C10 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C11 latch_diff_1/nD latch_diff_1/D 0.33fF
+C12 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C13 latch_diff_1/nD nQ 0.08fF
+C14 latch_diff_0/D latch_diff_1/nD 0.04fF
+C15 latch_diff_0/D latch_diff_0/m1_657_280# 0.37fF
+C16 latch_diff_0/nD latch_diff_1/D 0.41fF
+C17 latch_diff_1/nD Q 0.01fF
+C18 latch_diff_1/nD vdd 0.02fF
+C19 latch_diff_1/m1_657_280# vss 0.64fF
+C20 nCLK vss 0.83fF
+C21 Q vss -0.92fF
+C22 nQ vss 0.57fF
+C23 latch_diff_0/m1_657_280# vss 0.69fF
+C24 CLK vss 0.83fF
+C25 latch_diff_1/D vss -0.33fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.63fF
+C30 D vss 3.27fF
+C31 vdd vss 31.85fF
+C32 latch_diff_0/nD vss 1.53fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n129_n84# a_159_n84# 0.05fF
+C1 a_n63_n110# a_33_n110# 0.02fF
+C2 a_n221_n84# a_63_n84# 0.05fF
+C3 w_n359_n303# a_n33_n84# 0.05fF
+C4 a_n129_n84# a_63_n84# 0.09fF
+C5 a_n129_n84# a_n221_n84# 0.24fF
+C6 a_129_n110# a_33_n110# 0.02fF
+C7 a_n33_n84# a_159_n84# 0.09fF
+C8 w_n359_n303# a_159_n84# 0.08fF
+C9 a_n159_n110# a_n63_n110# 0.02fF
+C10 a_n33_n84# a_63_n84# 0.24fF
+C11 w_n359_n303# a_63_n84# 0.06fF
+C12 a_n33_n84# a_n221_n84# 0.09fF
+C13 w_n359_n303# a_n221_n84# 0.08fF
+C14 a_n129_n84# a_n33_n84# 0.24fF
+C15 a_n129_n84# w_n359_n303# 0.06fF
+C16 a_159_n84# a_63_n84# 0.24fF
+C17 a_n221_n84# a_159_n84# 0.04fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n221_n42# a_n129_n42# 0.12fF
+C1 a_n221_n42# a_159_n42# 0.02fF
+C2 a_n221_n42# a_63_n42# 0.03fF
+C3 a_n221_n42# a_n33_n42# 0.05fF
+C4 a_159_n42# a_n129_n42# 0.03fF
+C5 a_n129_n42# a_63_n42# 0.05fF
+C6 a_159_n42# a_63_n42# 0.12fF
+C7 a_33_n68# a_n63_n68# 0.02fF
+C8 a_n63_n68# a_n159_n68# 0.02fF
+C9 a_n33_n42# a_n129_n42# 0.12fF
+C10 a_159_n42# a_n33_n42# 0.05fF
+C11 a_n33_n42# a_63_n42# 0.12fF
+C12 a_33_n68# a_129_n68# 0.02fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 vdd in 0.33fF
+C1 out in 0.67fF
+C2 out vdd 0.62fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n125_n42# a_63_n42# 0.05fF
+C1 a_n33_n42# a_63_n42# 0.12fF
+C2 a_n33_n42# a_n125_n42# 0.12fF
+C3 a_33_n68# a_n63_n68# 0.02fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n63_n110# a_33_n110# 0.02fF
+C1 a_n125_n84# a_n33_n84# 0.24fF
+C2 a_n125_n84# w_n263_n303# 0.10fF
+C3 a_63_n84# a_n33_n84# 0.24fF
+C4 a_63_n84# w_n263_n303# 0.10fF
+C5 a_n33_n84# w_n263_n303# 0.07fF
+C6 a_63_n84# a_n125_n84# 0.09fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 out in 0.30fF
+C1 vdd in 0.01fF
+C2 out vdd 0.15fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vdd vss nout_div CLK_2 nCLK_2 o1 o2 CLK out_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD
++ out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C2 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C3 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C4 o2 nCLK_2 0.11fF
+C5 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C6 o2 vdd 0.14fF
+C7 out_div nout_div 0.22fF
+C8 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C9 DFlipFlop_0/nCLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.46fF
+C10 DFlipFlop_0/nCLK nout_div 0.43fF
+C11 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
+C12 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C13 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/CLK -0.48fF
+C14 out_div o1 0.01fF
+C15 out_div vdd 0.03fF
+C16 nout_div DFlipFlop_0/CLK 0.42fF
+C17 DFlipFlop_0/nCLK vdd 0.30fF
+C18 DFlipFlop_0/latch_diff_0/nD nout_div 0.07fF
+C19 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C20 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C21 CLK_2 o1 0.11fF
+C22 CLK_2 vdd 0.08fF
+C23 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C24 nout_div vdd 0.16fF
+C25 DFlipFlop_0/CLK vdd 0.40fF
+C26 nCLK_2 vdd 0.08fF
+C27 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C28 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C29 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C30 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C31 o1 vdd 0.14fF
+C32 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C33 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C34 CLK_2 vss 1.08fF
+C35 o1 vss 2.21fF
+C36 nCLK_2 vss 1.08fF
+C37 o2 vss 2.21fF
+C38 DFlipFlop_0/CLK vss 1.03fF
+C39 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C40 clock_inverter_0/inverter_cp_x1_0/out vss 1.64fF
+C41 CLK vss 3.27fF
+C42 DFlipFlop_0/nCLK vss 1.55fF
+C43 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C46 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C47 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C48 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.59fF
+C51 nout_div vss 4.41fF
+C52 vdd vss 62.89fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+.ends
+
+.subckt trans_gate_mux2to8 in vss out en_pos en_neg vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd en_neg in out out en_neg en_neg in sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 en_pos vss en_pos in out out en_pos in sky130_fd_pr__nfet_01v8_BHR94T
+C0 en_pos en_neg 0.04fF
+C1 en_neg out 0.07fF
+C2 en_neg in 0.28fF
+C3 out vdd 0.27fF
+C4 en_pos out 0.27fF
+C5 in vdd 0.05fF
+C6 en_pos in 0.07fF
+C7 in out 0.36fF
+C8 vdd vss 2.08fF
+C9 in vss 1.12fF
+C10 out vss 0.87fF
+C11 en_pos vss 0.29fF
+C12 en_neg vss 0.31fF
+.ends
+
+.subckt mux2to1 vss select_0_neg out_a_0 out_a_1 select_0 vdd in_a
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 select_0 select_0_neg 0.17fF
+C1 in_a select_0 0.31fF
+C2 in_a out_a_1 0.08fF
+C3 vdd out_a_1 0.06fF
+C4 in_a select_0_neg 0.11fF
+C5 vdd in_a 0.02fF
+C6 select_0_neg out_a_0 0.05fF
+C7 in_a out_a_0 0.08fF
+C8 select_0 out_a_1 0.14fF
+C9 vdd out_a_0 0.06fF
+C10 out_a_1 vss 0.99fF
+C11 vdd vss 4.78fF
+C12 in_a vss 2.00fF
+C13 out_a_0 vss 0.99fF
+C14 select_0_neg vss 1.15fF
+C15 select_0 vss 0.97fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 B VGND 0.10fF
+C1 a_194_125# a_355_368# 0.51fF
+C2 a_158_392# a_194_125# 0.06fF
+C3 B A 0.28fF
+C4 B X 0.13fF
+C5 A a_355_368# 0.02fF
+C6 X a_355_368# 0.17fF
+C7 a_194_125# VPWR 0.33fF
+C8 VGND VPWR 0.01fF
+C9 VPB VPWR 0.06fF
+C10 VPWR A 0.15fF
+C11 B a_355_368# 0.08fF
+C12 X VPWR 0.07fF
+C13 VGND a_194_125# 0.25fF
+C14 a_194_125# A 0.18fF
+C15 X a_194_125# 0.29fF
+C16 VGND A 0.31fF
+C17 B VPWR 0.09fF
+C18 X VGND 0.28fF
+C19 VPWR a_355_368# 0.37fF
+C20 B a_194_125# 0.57fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 a_56_136# VPWR 0.57fF
+C1 X VGND 0.15fF
+C2 VGND A 0.21fF
+C3 VPWR B 0.02fF
+C4 a_56_136# B 0.30fF
+C5 VPB VPWR 0.04fF
+C6 a_56_136# VGND 0.06fF
+C7 X VPWR 0.20fF
+C8 VPWR A 0.07fF
+C9 X a_56_136# 0.26fF
+C10 a_56_136# A 0.17fF
+C11 VGND B 0.03fF
+C12 X B 0.02fF
+C13 A B 0.08fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 B A 0.10fF
+C1 B a_63_368# 0.14fF
+C2 a_63_368# a_152_368# 0.03fF
+C3 B VGND 0.11fF
+C4 VPWR X 0.18fF
+C5 VPWR VPB 0.04fF
+C6 VPWR A 0.05fF
+C7 VPWR a_63_368# 0.29fF
+C8 A X 0.02fF
+C9 a_63_368# X 0.33fF
+C10 VGND X 0.16fF
+C11 B VPWR 0.01fF
+C12 A a_63_368# 0.28fF
+C13 VGND a_63_368# 0.27fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_2/latch_diff_0/nD vss
++ Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in CLK DFlipFlop_0/Q vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ DFlipFlop_3/latch_diff_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/nD DFlipFlop_2/latch_diff_0/m1_657_280# CLK_5 Q1_shift
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D DFlipFlop_1/D nQ0 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/latch_diff_1/nD Q0 DFlipFlop_0/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_0/latch_diff_0/nD DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/D
++ DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_152_368# sky130_fd_sc_hs__and2_1_1/a_56_136#
++ DFlipFlop_3/nQ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 nCLK DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ nCLK DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vdd vss DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ CLK DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 vdd nQ0 0.11fF
+C1 vdd DFlipFlop_3/nQ 0.02fF
+C2 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C3 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.28fF
+C4 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
+C5 vdd DFlipFlop_0/D 0.19fF
+C6 Q0 nQ0 0.33fF
+C7 DFlipFlop_1/D Q1 0.03fF
+C8 nCLK DFlipFlop_1/latch_diff_1/D 0.08fF
+C9 Q0 DFlipFlop_0/D 0.39fF
+C10 DFlipFlop_1/latch_diff_0/nD CLK 0.08fF
+C11 vdd CLK_5 0.15fF
+C12 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C13 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C14 nCLK DFlipFlop_2/D 0.41fF
+C15 nQ0 CLK 0.19fF
+C16 DFlipFlop_3/nQ CLK 0.01fF
+C17 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C18 vdd DFlipFlop_2/D 0.07fF
+C19 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C20 Q0 DFlipFlop_2/D 0.25fF
+C21 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C22 nCLK DFlipFlop_0/Q 0.11fF
+C23 nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
+C24 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C25 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C26 nCLK nQ2 0.10fF
+C27 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C28 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C29 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C30 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C31 sky130_fd_sc_hs__and2_1_1/a_143_136# CLK 0.03fF
+C32 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C33 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C34 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C35 vdd nQ2 0.04fF
+C36 CLK DFlipFlop_2/D 0.14fF
+C37 Q0 DFlipFlop_0/Q 0.21fF
+C38 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C39 Q0 nQ2 0.23fF
+C40 nCLK DFlipFlop_1/D 0.14fF
+C41 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C42 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C43 DFlipFlop_0/Q CLK 0.08fF
+C44 Q0 DFlipFlop_0/latch_diff_1/D 0.23fF
+C45 vdd DFlipFlop_1/D 0.25fF
+C46 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C47 Q1 Q1_shift 0.36fF
+C48 CLK nQ2 0.17fF
+C49 DFlipFlop_2/latch_diff_1/m1_657_280# Q1 0.03fF
+C50 Q0 DFlipFlop_1/D 0.07fF
+C51 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
+C52 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C53 DFlipFlop_3/latch_diff_1/nD Q1 1.24fF
+C54 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C55 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C56 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C57 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C58 DFlipFlop_1/D CLK 0.21fF
+C59 DFlipFlop_2/nQ Q1 0.31fF
+C60 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
+C61 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
+C62 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C63 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C64 nCLK DFlipFlop_1/latch_diff_1/nD 0.16fF
+C65 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C66 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C67 sky130_fd_sc_hs__and2_1_1/a_56_136# CLK 0.06fF
+C68 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
+C69 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C70 nCLK sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.02fF
+C71 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
+C72 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C73 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C74 nCLK Q1 -0.01fF
+C75 vdd Q1 9.49fF
+C76 nQ0 nQ2 0.03fF
+C77 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C78 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C79 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C80 Q0 Q1 9.65fF
+C81 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
+C82 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C83 vdd Q1_shift 0.10fF
+C84 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C85 DFlipFlop_1/D nQ0 0.12fF
+C86 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C87 nCLK DFlipFlop_2/nQ 0.09fF
+C88 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q1 0.21fF
+C89 Q1 CLK -0.10fF
+C90 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C91 DFlipFlop_2/latch_diff_0/D Q1 0.42fF
+C92 vdd DFlipFlop_2/nQ 0.02fF
+C93 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C94 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C95 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C96 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C97 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C98 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C99 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C100 DFlipFlop_0/Q nQ2 0.09fF
+C101 DFlipFlop_2/nQ CLK 0.13fF
+C102 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C103 nCLK vdd 0.34fF
+C104 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C105 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C106 nCLK Q0 0.20fF
+C107 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C108 DFlipFlop_3/latch_diff_0/m1_657_280# Q1 0.28fF
+C109 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C110 Q0 vdd 5.33fF
+C111 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C112 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C113 DFlipFlop_3/latch_diff_0/D CLK 0.11fF
+C114 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C115 Q1 nQ0 0.06fF
+C116 DFlipFlop_3/nQ Q1 0.10fF
+C117 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C118 Q1 DFlipFlop_0/D 0.13fF
+C119 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C120 vdd CLK 0.41fF
+C121 DFlipFlop_3/nQ Q1_shift 0.04fF
+C122 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C123 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C124 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C125 nCLK DFlipFlop_3/latch_diff_1/D 0.14fF
+C126 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C127 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C128 Q0 CLK 0.08fF
+C129 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C130 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C131 nCLK sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.11fF
+C132 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C133 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C134 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C135 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
+C136 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
+C137 Q1 DFlipFlop_2/D 0.10fF
+C138 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C139 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C140 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C141 Q0 sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.26fF
+C142 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
+C143 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
+C144 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C145 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C146 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C147 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
+C148 DFlipFlop_0/Q Q1 0.13fF
+C149 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C150 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C151 Q1 nQ2 0.07fF
+C152 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C153 nCLK nQ0 0.09fF
+C154 nCLK DFlipFlop_3/nQ 0.02fF
+C155 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
+C156 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/nQ vss 0.52fF
+C164 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.64fF
+C170 Q1 vss 8.55fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C172 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C173 Q0 vss 0.53fF
+C174 nQ0 vss 3.42fF
+C175 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C176 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C177 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C178 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C179 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C180 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.58fF
+C181 DFlipFlop_1/D vss 3.72fF
+C182 DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C183 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C184 DFlipFlop_2/nQ vss 0.50fF
+C185 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C186 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C187 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C188 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C190 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C191 DFlipFlop_2/D vss 5.34fF
+C192 DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C193 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C194 nCLK vss 0.89fF
+C195 DFlipFlop_0/Q vss -0.94fF
+C196 nQ2 vss 2.05fF
+C197 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C198 CLK vss 0.07fF
+C199 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C200 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 vdd vss 144.09fF
+C206 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt mux2to4 vss out_b_1 vdd select_0 select_0_neg out_a_0 out_a_1 out_b_0 in_a
++ in_b
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_b vss out_b_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_3 in_b vss out_b_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 select_0_neg out_a_1 0.12fF
+C1 out_b_0 out_a_1 0.88fF
+C2 select_0 in_a 0.31fF
+C3 in_b vdd 0.02fF
+C4 in_a out_a_1 0.08fF
+C5 select_0 vdd 0.02fF
+C6 out_b_0 select_0_neg -0.13fF
+C7 out_b_1 vdd 0.06fF
+C8 out_a_1 vdd 0.06fF
+C9 in_a select_0_neg 0.22fF
+C10 in_a out_b_0 0.11fF
+C11 out_a_0 select_0_neg 0.05fF
+C12 select_0 in_b 0.24fF
+C13 select_0_neg vdd 0.02fF
+C14 out_b_0 vdd 0.06fF
+C15 out_b_1 in_b 0.08fF
+C16 in_b out_a_1 0.08fF
+C17 out_b_1 select_0 0.14fF
+C18 out_a_0 in_a 0.08fF
+C19 select_0 out_a_1 0.18fF
+C20 in_a vdd 0.02fF
+C21 out_a_0 vdd 0.06fF
+C22 select_0_neg in_b 0.10fF
+C23 out_b_0 in_b 0.08fF
+C24 select_0 select_0_neg 0.49fF
+C25 select_0 out_b_0 0.03fF
+C26 out_b_1 vss 0.99fF
+C27 in_b vss 2.00fF
+C28 out_b_0 vss 0.93fF
+C29 out_a_1 vss 0.22fF
+C30 vdd vss 9.53fF
+C31 in_a vss 2.00fF
+C32 out_a_0 vss 0.99fF
+C33 select_0_neg vss 2.56fF
+C34 select_0 vss 2.23fF
+.ends
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X a_304_74# a_443_74# a_524_368#
++ a_27_112#
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 a_226_74# a_304_74# 0.08fF
+C1 S A0 0.04fF
+C2 A1 a_27_112# 0.18fF
+C3 VGND a_27_112# 0.18fF
+C4 A1 VPWR 0.01fF
+C5 VGND VPWR 0.02fF
+C6 X a_27_112# 0.08fF
+C7 X VPWR 0.28fF
+C8 S A1 0.10fF
+C9 a_304_74# a_223_368# 0.05fF
+C10 S VGND 0.07fF
+C11 A0 A1 0.31fF
+C12 VPB a_27_112# 0.01fF
+C13 VGND A0 0.02fF
+C14 VPB VPWR 0.06fF
+C15 a_304_74# a_27_112# 0.58fF
+C16 a_304_74# VPWR 0.13fF
+C17 VGND A1 0.09fF
+C18 S a_304_74# 0.18fF
+C19 A0 a_304_74# 0.23fF
+C20 X A1 0.02fF
+C21 VGND X 0.11fF
+C22 a_443_74# A1 0.07fF
+C23 a_223_368# a_27_112# 0.09fF
+C24 a_304_74# A1 0.69fF
+C25 VGND a_304_74# 0.58fF
+C26 a_27_112# VPWR 0.99fF
+C27 a_304_74# X 0.29fF
+C28 a_443_74# a_304_74# 0.12fF
+C29 S a_27_112# 0.22fF
+C30 S VPWR 0.05fF
+C31 A0 a_27_112# 0.07fF
+C32 a_524_368# a_27_112# 0.06fF
+C33 VGND VNB 0.88fF
+C34 X VNB 0.25fF
+C35 VPWR VNB 0.89fF
+C36 A1 VNB 0.37fF
+C37 A0 VNB 0.23fF
+C38 S VNB 0.34fF
+C39 VPB VNB 0.87fF
+C40 a_304_74# VNB 0.36fF
+C41 a_27_112# VNB 0.65fF
+.ends
+
+.subckt prescaler_23 nCLK vss DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_2/latch_diff_0/nD
++ vdd DFlipFlop_2/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out CLK_23 DFlipFlop_2/latch_diff_0/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_0/latch_diff_0/nD MC DFlipFlop_2/latch_diff_0/D
++ Q2
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1_0/a_304_74# sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__mux2_1_0/a_524_368#
++ sky130_fd_sc_hs__mux2_1_0/a_27_112# sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ nCLK DFlipFlop_0/latch_diff_0/nD
++ Q1 DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_0/D
++ CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK_23 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q2 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ CLK DFlipFlop_2/latch_diff_0/nD
++ Q2_d DFlipFlop_2/latch_diff_1/nD Q2 DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/latch_diff_0/D
++ nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1_0/a_143_136# sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1_1/a_152_368#
++ sky130_fd_sc_hs__or2_1_1/a_63_368# sky130_fd_sc_hs__or2_1
+C0 Q2 vdd 1.63fF
+C1 nCLK Q1 -0.02fF
+C2 DFlipFlop_1/latch_diff_1/D nCLK 0.09fF
+C3 CLK MC 0.08fF
+C4 sky130_fd_sc_hs__and2_1_0/a_56_136# CLK 0.08fF
+C5 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_524_368# 0.04fF
+C6 sky130_fd_sc_hs__or2_1_1/X nCLK_23 0.26fF
+C7 CLK DFlipFlop_1/D 0.40fF
+C8 DFlipFlop_0/latch_diff_1/D CLK 0.04fF
+C9 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.31fF
+C10 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.06fF
+C11 Q2 DFlipFlop_2/nQ 0.13fF
+C12 nCLK nCLK_23 0.11fF
+C13 CLK Q2 0.29fF
+C14 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.02fF
+C15 sky130_fd_sc_hs__mux2_1_0/a_27_112# nCLK_23 0.07fF
+C16 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_443_74# 0.03fF
+C17 Q2 Q2_d 0.66fF
+C18 DFlipFlop_1/latch_diff_1/nD nCLK 0.18fF
+C19 Q1 nCLK_23 0.02fF
+C20 nCLK DFlipFlop_0/nQ 0.11fF
+C21 sky130_fd_sc_hs__mux2_1_0/a_304_74# nCLK_23 0.04fF
+C22 CLK DFlipFlop_2/latch_diff_1/D 0.09fF
+C23 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C24 Q2 DFlipFlop_2/latch_diff_1/nD 0.17fF
+C25 Q2_d DFlipFlop_2/latch_diff_1/D 0.03fF
+C26 nCLK sky130_fd_sc_hs__or2_1_0/X 0.06fF
+C27 sky130_fd_sc_hs__or2_1_1/X MC 0.02fF
+C28 nCLK sky130_fd_sc_hs__or2_1_0/a_63_368# 0.05fF
+C29 CLK vdd 0.34fF
+C30 Q2_d vdd 0.02fF
+C31 DFlipFlop_2/latch_diff_0/m1_657_280# nCLK 0.31fF
+C32 Q1 DFlipFlop_0/nQ -0.02fF
+C33 nCLK MC 0.01fF
+C34 Q1 sky130_fd_sc_hs__or2_1_0/X 0.06fF
+C35 DFlipFlop_0/latch_diff_0/nD nCLK_23 0.12fF
+C36 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.09fF
+C37 sky130_fd_sc_hs__mux2_1_0/a_27_112# MC 0.24fF
+C38 CLK DFlipFlop_2/nQ 0.02fF
+C39 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C40 sky130_fd_sc_hs__and2_1_0/a_143_136# nCLK_23 0.02fF
+C41 nCLK DFlipFlop_1/D 0.16fF
+C42 Q1 MC 0.29fF
+C43 Q2 sky130_fd_sc_hs__or2_1_1/X 0.24fF
+C44 DFlipFlop_1/latch_diff_0/D nCLK 0.02fF
+C45 CLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.33fF
+C46 nCLK_23 DFlipFlop_0/nQ 0.05fF
+C47 Q2_d DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C48 sky130_fd_sc_hs__mux2_1_0/a_443_74# nCLK_23 0.09fF
+C49 CLK_23 vdd 0.16fF
+C50 sky130_fd_sc_hs__or2_1_0/X nCLK_23 0.07fF
+C51 Q2 nCLK 0.29fF
+C52 CLK DFlipFlop_2/latch_diff_1/nD 0.19fF
+C53 Q2 sky130_fd_sc_hs__or2_1_1/a_63_368# 0.09fF
+C54 sky130_fd_sc_hs__or2_1_1/X vdd 0.03fF
+C55 nCLK_23 MC 4.46fF
+C56 nCLK DFlipFlop_2/latch_diff_1/D 0.16fF
+C57 sky130_fd_sc_hs__and2_1_0/a_56_136# nCLK_23 0.14fF
+C58 DFlipFlop_2/latch_diff_0/nD nCLK 0.09fF
+C59 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.29fF
+C60 nCLK vdd -0.55fF
+C61 DFlipFlop_1/D nCLK_23 0.02fF
+C62 DFlipFlop_0/latch_diff_1/D nCLK_23 0.05fF
+C63 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out nCLK_23 0.49fF
+C64 sky130_fd_sc_hs__or2_1_0/X MC 0.09fF
+C65 sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C66 Q1 vdd 0.07fF
+C67 Q2 nCLK_23 0.03fF
+C68 Q2_d sky130_fd_sc_hs__or2_1_1/X 0.03fF
+C69 Q2 DFlipFlop_2/latch_diff_0/D 0.30fF
+C70 nCLK DFlipFlop_2/nQ 0.02fF
+C71 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C72 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.31fF
+C73 sky130_fd_sc_hs__or2_1_0/X DFlipFlop_1/D 0.35fF
+C74 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C75 Q2 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.38fF
+C76 Q1 DFlipFlop_0/latch_diff_1/nD 0.03fF
+C77 nCLK_23 vdd 3.27fF
+C78 CLK Q1 -0.07fF
+C79 CLK DFlipFlop_1/latch_diff_1/D 0.18fF
+C80 nCLK DFlipFlop_2/latch_diff_1/nD 0.12fF
+C81 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C82 Q2 MC 0.18fF
+C83 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C84 nCLK sky130_fd_sc_hs__or2_1_0/a_152_368# 0.01fF
+C85 DFlipFlop_0/latch_diff_1/nD nCLK_23 0.02fF
+C86 sky130_fd_sc_hs__or2_1_0/X vdd 0.03fF
+C87 Q1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.06fF
+C88 CLK nCLK_23 0.22fF
+C89 CLK DFlipFlop_2/latch_diff_0/D 0.13fF
+C90 Q1 sky130_fd_sc_hs__or2_1_0/a_152_368# 0.01fF
+C91 MC vdd 0.88fF
+C92 CLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.05fF
+C93 CLK DFlipFlop_1/latch_diff_1/nD 0.11fF
+C94 CLK DFlipFlop_0/nQ 0.15fF
+C95 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.10fF
+C96 DFlipFlop_1/D vdd 0.07fF
+C97 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.08fF
+C98 CLK sky130_fd_sc_hs__or2_1_0/X 0.01fF
+C99 Q2 DFlipFlop_2/latch_diff_1/D 0.13fF
+C100 CLK DFlipFlop_1/latch_diff_0/nD 0.09fF
+C101 sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C102 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C103 sky130_fd_sc_hs__or2_1_0/X vss 0.92fF
+C104 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.39fF
+C105 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C106 Q2_d vss -0.22fF
+C107 DFlipFlop_2/nQ vss 0.48fF
+C108 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C109 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C110 DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C111 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C112 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C113 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.63fF
+C114 Q2 vss 1.35fF
+C115 DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C116 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.72fF
+C117 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C118 DFlipFlop_1/latch_diff_1/D vss -1.72fF
+C119 DFlipFlop_1/latch_diff_1/nD vss 0.58fF
+C120 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C121 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C122 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C123 DFlipFlop_1/D vss 2.98fF
+C124 DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C125 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C126 nCLK vss -1.56fF
+C127 Q1 vss 0.50fF
+C128 DFlipFlop_0/nQ vss 0.48fF
+C129 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C130 CLK vss -0.69fF
+C131 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C132 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C133 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C134 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C135 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C136 nCLK_23 vss -0.65fF
+C137 vdd vss 113.67fF
+C138 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C139 CLK_23 vss -0.57fF
+C140 sky130_fd_sc_hs__or2_1_1/X vss -0.35fF
+C141 MC vss 2.09fF
+C142 sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.41fF
+C143 sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.69fF
+.ends
+
+.subckt freq_div clk_0 vss n_clk_0 vdd prescaler_23_0/Q2 s_0 s_1_n s_1 prescaler_23_0/nCLK_23
++ prescaler_23_0/MC clk_d prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n
++ clk_pre div_by_5_0/DFlipFlop_2/latch_diff_0/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out div_by_5_0/Q1 div_by_5_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD clk_2 in_a in_b clk_5 prescaler_23_0/DFlipFlop_2/latch_diff_0/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD div_by_5_0/DFlipFlop_2/latch_diff_1/D
+Xdiv_by_2_0 vdd vss div_by_2_0/nout_div clk_2 div_by_2_0/nCLK_2 div_by_2_0/o1 div_by_2_0/o2
++ clk_out_mux21 div_by_2_0/out_div div_by_2
+Xmux2to1_0 vss s_0_n clk_pre clk_5 s_0 vdd clk_out_mux21 mux2to1
+Xinverter_min_x4_0 inverter_min_x4_0/in vss clk_d vdd inverter_min_x4
+Xmux2to1_1 vss s_1_n clk_d clk_2 s_1 vdd out mux2to1
+Xinverter_min_x2_0 clk_out_mux21 inverter_min_x4_0/in vss vdd inverter_min_x2
+Xinverter_min_x2_1 s_1 s_1_n vss vdd inverter_min_x2
+Xinverter_min_x2_2 s_0 s_0_n vss vdd inverter_min_x2
+Xdiv_by_5_0 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ vss div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in clk_1
++ div_by_5_0/DFlipFlop_0/Q vdd div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# clk_5 div_by_5_0/Q1_shift div_by_5_0/nQ2
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_by_5_0/DFlipFlop_1/D div_by_5_0/nQ0 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/Q0 div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xmux2to4_0 vss n_clk_1 vdd s_0 s_0_n clk_0 clk_1 n_clk_0 in_a in_b mux2to4
+Xprescaler_23_0 n_clk_0 vss prescaler_23_0/DFlipFlop_0/latch_diff_1/nD prescaler_23_0/nCLK_23
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vdd prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ clk_pre prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# prescaler_23_0/DFlipFlop_0/latch_diff_0/D
++ clk_0 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280#
++ prescaler_23_0/DFlipFlop_0/latch_diff_1/D prescaler_23_0/DFlipFlop_0/latch_diff_0/nD
++ prescaler_23_0/MC prescaler_23_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/Q2 prescaler_23
+C0 n_clk_1 vdd 0.13fF
+C1 n_clk_1 div_by_5_0/DFlipFlop_0/D 0.21fF
+C2 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD n_clk_0 0.13fF
+C3 s_0_n div_by_5_0/Q1_shift 0.04fF
+C4 inverter_min_x4_0/in vdd 0.09fF
+C5 s_0 div_by_5_0/Q1 0.04fF
+C6 clk_1 n_clk_0 -0.03fF
+C7 s_0_n div_by_5_0/DFlipFlop_0/Q 0.24fF
+C8 s_0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out -0.13fF
+C9 s_0 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.30fF
+C10 out s_1_n 0.33fF
+C11 s_0 vdd 3.67fF
+C12 s_0_n n_clk_0 0.31fF
+C13 s_0 div_by_5_0/DFlipFlop_0/D 0.03fF
+C14 clk_0 prescaler_23_0/nCLK_23 0.16fF
+C15 s_1 clk_d 0.22fF
+C16 clk_d vdd 0.23fF
+C17 s_0 div_by_5_0/Q1_shift 0.05fF
+C18 div_by_5_0/DFlipFlop_2/nQ s_0_n 0.04fF
+C19 s_0 div_by_5_0/DFlipFlop_0/Q 0.02fF
+C20 vdd clk_pre 0.17fF
+C21 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/Q1 -0.06fF
+C22 s_0_n clk_1 4.82fF
+C23 s_0_n div_by_5_0/DFlipFlop_3/nQ 0.24fF
+C24 s_0_n clk_out_mux21 0.45fF
+C25 div_by_5_0/DFlipFlop_2/nQ s_0 0.05fF
+C26 div_by_5_0/DFlipFlop_3/latch_diff_1/D s_0_n 0.24fF
+C27 s_0 clk_1 1.36fF
+C28 n_clk_0 prescaler_23_0/nCLK_23 0.16fF
+C29 s_0_n s_0 7.76fF
+C30 s_0_n div_by_5_0/nQ2 0.05fF
+C31 s_0 div_by_5_0/DFlipFlop_3/nQ 0.02fF
+C32 s_0_n div_by_5_0/DFlipFlop_2/D 0.05fF
+C33 s_0 clk_out_mux21 0.68fF
+C34 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# div_by_5_0/Q1_shift -0.02fF
+C35 clk_5 vdd 0.04fF
+C36 s_0_n in_b 0.48fF
+C37 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C38 s_0_n div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.20fF
+C39 div_by_5_0/DFlipFlop_3/latch_diff_1/D s_0 0.02fF
+C40 div_by_5_0/DFlipFlop_0/latch_diff_1/D clk_1 0.11fF
+C41 n_clk_1 in_b 0.05fF
+C42 clk_2 vdd 0.02fF
+C43 s_0_n div_by_5_0/nQ0 0.05fF
+C44 div_by_5_0/Q1_shift clk_5 0.04fF
+C45 clk_out_mux21 clk_pre 1.19fF
+C46 div_by_5_0/DFlipFlop_0/latch_diff_1/D s_0_n 0.04fF
+C47 s_0 div_by_5_0/nQ2 0.05fF
+C48 s_0 div_by_5_0/DFlipFlop_2/D 0.03fF
+C49 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.04fF
+C50 s_0_n div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.37fF
+C51 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_clk_1 0.08fF
+C52 inverter_min_x4_0/in clk_d 0.11fF
+C53 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0_n 0.24fF
+C54 s_0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.02fF
+C55 s_0 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.12fF
+C56 div_by_5_0/DFlipFlop_1/latch_diff_1/D s_0_n 0.04fF
+C57 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_clk_1 0.14fF
+C58 div_by_5_0/Q0 vdd 0.05fF
+C59 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_clk_1 0.11fF
+C60 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_0 0.16fF
+C61 s_0_n div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.05fF
+C62 s_0 div_by_5_0/nQ0 0.05fF
+C63 s_0 clk_pre 0.21fF
+C64 div_by_5_0/DFlipFlop_0/latch_diff_1/D s_0 0.05fF
+C65 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.17fF
+C66 s_0_n div_by_5_0/DFlipFlop_1/D 0.19fF
+C67 clk_0 vdd 0.63fF
+C68 clk_2 s_1_n 0.59fF
+C69 s_0 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.05fF
+C70 s_0 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.36fF
+C71 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0 0.02fF
+C72 prescaler_23_0/DFlipFlop_0/latch_diff_1/D clk_0 0.13fF
+C73 div_by_5_0/DFlipFlop_0/latch_diff_0/nD clk_1 0.08fF
+C74 div_by_5_0/DFlipFlop_1/latch_diff_1/D s_0 0.05fF
+C75 prescaler_23_0/DFlipFlop_0/latch_diff_0/D n_clk_0 0.13fF
+C76 s_0_n clk_5 0.56fF
+C77 clk_out_mux21 clk_5 0.05fF
+C78 out clk_2 0.05fF
+C79 div_by_5_0/DFlipFlop_0/latch_diff_0/nD s_0_n 0.20fF
+C80 div_by_5_0/Q1 vdd -0.02fF
+C81 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_clk_1 0.06fF
+C82 div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/D -0.02fF
+C83 prescaler_23_0/nCLK_23 clk_pre 0.03fF
+C84 s_0 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.10fF
+C85 s_0 div_by_5_0/DFlipFlop_1/D 0.03fF
+C86 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.08fF
+C87 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0_n 0.04fF
+C88 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out s_0_n -0.29fF
+C89 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.24fF
+C90 div_by_5_0/DFlipFlop_0/latch_diff_0/nD s_0 0.12fF
+C91 div_by_5_0/Q0 s_0_n 0.24fF
+C92 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD clk_0 0.09fF
+C93 in_a clk_1 0.05fF
+C94 s_1 s_1_n 0.39fF
+C95 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_clk_0 0.14fF
+C96 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.11fF
+C97 n_clk_0 vdd 0.25fF
+C98 div_by_5_0/Q0 n_clk_1 0.01fF
+C99 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0 0.05fF
+C100 prescaler_23_0/DFlipFlop_0/latch_diff_1/D n_clk_0 0.09fF
+C101 out s_1 0.39fF
+C102 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out s_0 -0.19fF
+C103 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.20fF
+C104 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.02fF
+C105 clk_1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
+C106 div_by_5_0/Q0 s_0 0.02fF
+C107 clk_1 vdd 0.16fF
+C108 s_0_n div_by_5_0/Q1 0.21fF
+C109 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_clk_1 0.03fF
+C110 clk_1 div_by_5_0/DFlipFlop_0/D 0.14fF
+C111 s_0_n div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out -0.01fF
+C112 s_0_n div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.31fF
+C113 s_0 in_a 0.30fF
+C114 s_0_n vdd 2.53fF
+C115 clk_out_mux21 vdd 0.14fF
+C116 div_by_5_0/Q1 n_clk_1 0.15fF
+C117 s_0_n div_by_5_0/DFlipFlop_0/D 0.05fF
+C118 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD clk_0 0.09fF
+C119 s_0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.12fF
+C120 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C121 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C122 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C123 prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C124 prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C125 prescaler_23_0/Q2_d vss -0.69fF
+C126 prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C127 prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C128 prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C129 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C130 prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C131 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C132 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C133 prescaler_23_0/Q2 vss 0.55fF
+C134 prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C135 prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C136 prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C137 prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C138 prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C139 prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C140 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C141 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C142 prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C143 prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C144 prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C145 n_clk_0 vss -5.35fF
+C146 prescaler_23_0/Q1 vss 0.07fF
+C147 prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C148 prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C149 clk_0 vss 0.66fF
+C150 prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C151 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C152 prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C153 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C155 prescaler_23_0/nCLK_23 vss -1.02fF
+C156 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C157 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C158 prescaler_23_0/MC vss 1.07fF
+C159 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C160 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C161 in_b vss 2.02fF
+C162 in_a vss 2.01fF
+C163 s_0_n vss -2.51fF
+C164 s_0 vss 5.84fF
+C165 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C166 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C167 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C168 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C169 div_by_5_0/Q1_shift vss -0.36fF
+C170 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C171 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C172 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C174 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C177 div_by_5_0/Q1 vss 4.35fF
+C178 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C179 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C180 div_by_5_0/Q0 vss 0.29fF
+C181 div_by_5_0/nQ0 vss 0.99fF
+C182 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C183 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C184 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C185 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C186 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C187 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C188 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C189 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C190 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C191 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C192 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C193 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C194 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C195 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C196 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C197 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C198 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C199 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C200 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C201 n_clk_1 vss -0.55fF
+C202 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C203 div_by_5_0/nQ2 vss 1.38fF
+C204 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C205 clk_1 vss -1.34fF
+C206 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C207 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C208 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C209 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C210 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C211 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C212 vdd vss 344.01fF
+C213 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C214 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C215 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C216 out vss 0.93fF
+C217 clk_d vss 0.78fF
+C218 s_1_n vss 1.22fF
+C219 s_1 vss 2.97fF
+C220 inverter_min_x4_0/in vss 2.77fF
+C221 clk_out_mux21 vss 5.29fF
+C222 clk_pre vss 1.30fF
+C223 clk_2 vss 3.46fF
+C224 div_by_2_0/o1 vss 2.20fF
+C225 div_by_2_0/nCLK_2 vss 1.04fF
+C226 div_by_2_0/o2 vss 2.08fF
+C227 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C228 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C229 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C230 div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C231 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C232 div_by_2_0/out_div vss -0.80fF
+C233 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C234 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C235 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C236 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C237 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C238 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C239 div_by_2_0/nout_div vss 2.62fF
+C240 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n129_n600# a_n221_n600# 7.87fF
+C1 a_n257_n777# a_n221_n600# 0.25fF
+C2 a_n129_n600# a_n257_n777# 0.29fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n221_n300# a_n257_n404# 0.21fF
+C1 a_n221_n300# a_n129_n300# 4.05fF
+C2 a_n257_n404# a_n129_n300# 0.30fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out vdd in vss
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 out a_3996_n100# 55.19fF
+C1 a_678_n100# a_3996_n100# 6.52fF
+C2 vdd a_3996_n100# 3.68fF
+C3 vdd out 47.17fF
+C4 a_678_n100# in 0.81fF
+C5 vdd in 0.02fF
+C6 a_678_n100# vdd 0.08fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_n33_n238# 0.02fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 a_15_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_15_n150# 0.51fF
+C1 a_n33_181# w_n211_n369# 0.05fF
+C2 a_n73_n150# a_n33_181# 0.01fF
+C3 a_15_n150# a_n33_181# 0.01fF
+C4 a_n73_n150# w_n211_n369# 0.20fF
+C5 a_15_n150# w_n211_n369# 0.20fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n417_n150# a_n321_n150# 0.43fF
+C1 a_255_n150# a_63_n150# 0.16fF
+C2 a_n509_n150# a_n465_172# 0.01fF
+C3 a_n417_n150# a_n129_n150# 0.10fF
+C4 a_n321_n150# a_n129_n150# 0.16fF
+C5 a_n225_n150# a_159_n150# 0.07fF
+C6 a_255_n150# a_447_n150# 0.16fF
+C7 a_n225_n150# a_n33_n150# 0.16fF
+C8 a_n225_n150# a_n465_172# 0.10fF
+C9 a_351_n150# a_159_n150# 0.16fF
+C10 a_n33_n150# a_159_n150# 0.16fF
+C11 a_159_n150# a_n465_172# 0.10fF
+C12 a_n129_n150# a_255_n150# 0.07fF
+C13 a_n33_n150# a_351_n150# 0.07fF
+C14 a_351_n150# a_n465_172# 0.10fF
+C15 a_n417_n150# a_n509_n150# 0.43fF
+C16 a_n225_n150# a_63_n150# 0.10fF
+C17 a_n33_n150# a_n465_172# 0.10fF
+C18 a_n321_n150# a_n509_n150# 0.16fF
+C19 a_159_n150# a_63_n150# 0.43fF
+C20 a_n129_n150# a_n509_n150# 0.07fF
+C21 a_351_n150# a_63_n150# 0.10fF
+C22 a_n33_n150# a_63_n150# 0.43fF
+C23 a_n465_172# a_63_n150# 0.10fF
+C24 a_n417_n150# a_n225_n150# 0.16fF
+C25 a_n321_n150# a_n225_n150# 0.43fF
+C26 a_159_n150# a_447_n150# 0.10fF
+C27 a_351_n150# a_447_n150# 0.43fF
+C28 a_n129_n150# a_n225_n150# 0.43fF
+C29 a_447_n150# a_n465_172# 0.01fF
+C30 a_n417_n150# a_n33_n150# 0.07fF
+C31 a_n417_n150# a_n465_172# 0.10fF
+C32 a_n129_n150# a_159_n150# 0.10fF
+C33 a_n321_n150# a_n33_n150# 0.10fF
+C34 a_n321_n150# a_n465_172# 0.10fF
+C35 a_n129_n150# a_n33_n150# 0.43fF
+C36 a_n129_n150# a_n465_172# 0.10fF
+C37 a_447_n150# a_63_n150# 0.07fF
+C38 a_255_n150# a_159_n150# 0.43fF
+C39 a_255_n150# a_351_n150# 0.43fF
+C40 a_n321_n150# a_63_n150# 0.07fF
+C41 a_n33_n150# a_255_n150# 0.10fF
+C42 a_255_n150# a_n465_172# 0.10fF
+C43 a_n129_n150# a_63_n150# 0.16fF
+C44 a_n225_n150# a_n509_n150# 0.10fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_255_n150# w_n647_n369# 0.05fF
+C1 a_159_n150# a_n33_n150# 0.16fF
+C2 a_351_n150# a_n33_n150# 0.07fF
+C3 w_n647_n369# a_n129_n150# 0.02fF
+C4 a_n465_n247# a_n33_n150# 0.08fF
+C5 w_n647_n369# a_63_n150# 0.02fF
+C6 a_n509_n150# a_n129_n150# 0.07fF
+C7 a_n225_n150# a_n129_n150# 0.43fF
+C8 a_n225_n150# a_63_n150# 0.10fF
+C9 a_n465_n247# a_n417_n150# 0.08fF
+C10 a_447_n150# a_159_n150# 0.10fF
+C11 a_447_n150# a_351_n150# 0.43fF
+C12 a_n321_n150# a_n33_n150# 0.10fF
+C13 a_n509_n150# w_n647_n369# 0.14fF
+C14 w_n647_n369# a_n225_n150# 0.04fF
+C15 a_159_n150# a_351_n150# 0.16fF
+C16 a_n509_n150# a_n225_n150# 0.10fF
+C17 a_255_n150# a_n33_n150# 0.10fF
+C18 a_n321_n150# a_n417_n150# 0.43fF
+C19 a_159_n150# a_n465_n247# 0.08fF
+C20 a_351_n150# a_n465_n247# 0.08fF
+C21 a_n33_n150# a_n129_n150# 0.43fF
+C22 a_63_n150# a_n33_n150# 0.43fF
+C23 a_n417_n150# a_n129_n150# 0.10fF
+C24 a_447_n150# a_255_n150# 0.16fF
+C25 w_n647_n369# a_n33_n150# 0.02fF
+C26 a_n225_n150# a_n33_n150# 0.16fF
+C27 a_n321_n150# a_n465_n247# 0.08fF
+C28 a_159_n150# a_255_n150# 0.43fF
+C29 a_447_n150# a_63_n150# 0.07fF
+C30 w_n647_n369# a_n417_n150# 0.07fF
+C31 a_255_n150# a_351_n150# 0.43fF
+C32 a_n509_n150# a_n417_n150# 0.43fF
+C33 a_159_n150# a_n129_n150# 0.10fF
+C34 a_255_n150# a_n465_n247# 0.08fF
+C35 a_n225_n150# a_n417_n150# 0.16fF
+C36 a_447_n150# w_n647_n369# 0.14fF
+C37 a_159_n150# a_63_n150# 0.43fF
+C38 a_351_n150# a_63_n150# 0.10fF
+C39 a_n465_n247# a_n129_n150# 0.08fF
+C40 a_n465_n247# a_63_n150# 0.08fF
+C41 a_159_n150# w_n647_n369# 0.04fF
+C42 a_351_n150# w_n647_n369# 0.07fF
+C43 a_159_n150# a_n225_n150# 0.07fF
+C44 a_n465_n247# w_n647_n369# 0.47fF
+C45 a_n321_n150# a_n129_n150# 0.16fF
+C46 a_n321_n150# a_63_n150# 0.07fF
+C47 a_n417_n150# a_n33_n150# 0.07fF
+C48 a_n465_n247# a_n225_n150# 0.08fF
+C49 a_255_n150# a_n129_n150# 0.07fF
+C50 a_255_n150# a_63_n150# 0.16fF
+C51 a_n321_n150# w_n647_n369# 0.05fF
+C52 a_n321_n150# a_n509_n150# 0.16fF
+C53 a_63_n150# a_n129_n150# 0.16fF
+C54 a_n321_n150# a_n225_n150# 0.43fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_15_n11# 0.15fF
+C1 a_n73_n11# a_n33_n99# 0.02fF
+C2 a_15_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# a_20_n114# 0.42fF
+C1 a_20_n114# w_n216_n334# 0.20fF
+C2 a_n78_n114# w_n216_n334# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vdd 0.01fF
+C1 vbulkp vdd 0.04fF
+C2 in out 0.11fF
+C3 vbulkp out 0.08fF
+C4 vss in 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 vss out vdd inverter_csvco_0/vss
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 D0 inverter_csvco_0/vss 0.02fF
+C1 in inverter_csvco_0/vss 0.01fF
+C2 out cap_vco_0/t 0.70fF
+C3 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C4 vdd vbp 1.21fF
+C5 out inverter_csvco_0/vdd 0.02fF
+C6 vctrl inverter_csvco_0/vss 0.87fF
+C7 out inverter_csvco_0/vss 0.03fF
+C8 cap_vco_0/t vdd 0.04fF
+C9 out D0 0.09fF
+C10 out in 0.06fF
+C11 inverter_csvco_0/vdd vbp 0.75fF
+C12 inverter_csvco_0/vdd in 0.01fF
+C13 inverter_csvco_0/vdd vdd 1.89fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vss vdd csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 vss
++ csvco_branch_1/in vdd csvco_branch_0/inverter_csvco_0/vss csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 vss out_vco vdd csvco_branch_2/inverter_csvco_0/vss csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 vss csvco_branch_2/in vdd csvco_branch_1/inverter_csvco_0/vss csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss 0.06fF
+C1 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C2 vctrl D0 4.41fF
+C3 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C4 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
+C5 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C6 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C7 out_vco csvco_branch_1/in 0.76fF
+C8 csvco_branch_2/vbp vdd 1.49fF
+C9 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
+C10 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C11 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C12 csvco_branch_2/vbp vctrl 0.06fF
+C13 csvco_branch_2/in out_vco 0.58fF
+C14 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 vdd o1 0.09fF
+C1 vdd out_div 0.17fF
+C2 out_pad vdd 0.10fF
+C3 o1 out_div 0.11fF
+C4 out_pad out_div 0.15fF
+C5 vdd vss 14.54fF
+C6 in_vco vss 0.83fF
+C7 out_pad vss 0.70fF
+C8 out_div vss 3.00fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n225_n125# a_63_n125# 0.08fF
+C1 a_n129_n125# a_159_n125# 0.08fF
+C2 a_n159_n151# a_n255_n151# 0.02fF
+C3 a_n33_n125# a_n225_n125# 0.13fF
+C4 a_33_n151# a_129_n151# 0.02fF
+C5 a_225_n151# a_129_n151# 0.02fF
+C6 a_n63_n151# a_33_n151# 0.02fF
+C7 a_n317_n125# a_63_n125# 0.06fF
+C8 a_n33_n125# a_n317_n125# 0.08fF
+C9 a_n129_n125# a_n225_n125# 0.36fF
+C10 a_159_n125# a_n225_n125# 0.06fF
+C11 a_n129_n125# a_n317_n125# 0.13fF
+C12 a_n63_n151# a_n159_n151# 0.02fF
+C13 a_n33_n125# a_63_n125# 0.36fF
+C14 a_255_n125# a_63_n125# 0.13fF
+C15 a_n33_n125# a_255_n125# 0.08fF
+C16 a_n129_n125# a_63_n125# 0.13fF
+C17 a_159_n125# a_63_n125# 0.36fF
+C18 a_n225_n125# a_n317_n125# 0.36fF
+C19 a_n33_n125# a_n129_n125# 0.36fF
+C20 a_n33_n125# a_159_n125# 0.13fF
+C21 a_255_n125# a_n129_n125# 0.06fF
+C22 a_255_n125# a_159_n125# 0.36fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n317_n125# a_n129_n125# 0.13fF
+C1 a_n317_n125# a_63_n125# 0.06fF
+C2 a_255_n125# w_n455_n344# 0.11fF
+C3 a_n225_n125# a_n129_n125# 0.36fF
+C4 w_n455_n344# a_n33_n125# 0.05fF
+C5 a_n225_n125# a_63_n125# 0.08fF
+C6 a_255_n125# a_n33_n125# 0.08fF
+C7 a_129_n154# a_33_n154# 0.02fF
+C8 a_159_n125# a_n225_n125# 0.06fF
+C9 a_n317_n125# w_n455_n344# 0.11fF
+C10 a_n129_n125# a_63_n125# 0.13fF
+C11 a_n317_n125# a_n33_n125# 0.08fF
+C12 a_159_n125# a_n129_n125# 0.08fF
+C13 a_159_n125# a_63_n125# 0.36fF
+C14 a_n225_n125# w_n455_n344# 0.06fF
+C15 a_n255_n154# a_n159_n154# 0.02fF
+C16 a_n225_n125# a_n33_n125# 0.13fF
+C17 w_n455_n344# a_n129_n125# 0.04fF
+C18 w_n455_n344# a_63_n125# 0.04fF
+C19 a_n317_n125# a_n225_n125# 0.36fF
+C20 a_255_n125# a_n129_n125# 0.06fF
+C21 a_n63_n154# a_n159_n154# 0.02fF
+C22 a_159_n125# w_n455_n344# 0.06fF
+C23 a_255_n125# a_63_n125# 0.13fF
+C24 a_n129_n125# a_n33_n125# 0.36fF
+C25 a_129_n154# a_225_n154# 0.02fF
+C26 a_255_n125# a_159_n125# 0.36fF
+C27 a_33_n154# a_n63_n154# 0.02fF
+C28 a_n33_n125# a_63_n125# 0.36fF
+C29 a_159_n125# a_n33_n125# 0.13fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 out in 0.85fF
+C1 in vdd 0.04fF
+C2 out vdd 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss vdd inverter_cp_x1_0/out inverter_cp_x1_2/in Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown vss inverter_cp_x1_0/out vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd inverter_cp_x1_2/in 0.42fF
+C1 QA vdd 0.02fF
+C2 vdd Up 0.60fF
+C3 vdd inverter_cp_x1_0/out 0.18fF
+C4 Up inverter_cp_x1_2/in 0.12fF
+C5 vdd nUp 0.14fF
+C6 Down nDown 0.23fF
+C7 nUp Up 0.20fF
+C8 vdd nDown 0.80fF
+C9 QB vdd 0.02fF
+C10 Down inverter_cp_x1_0/out 0.12fF
+C11 inverter_cp_x1_0/out nDown 0.11fF
+C12 inverter_cp_x1_2/in vss 2.01fF
+C13 QA vss 1.09fF
+C14 inverter_cp_x1_0/out vss 1.72fF
+C15 QB vss 1.09fF
+C16 vdd vss 28.20fF
+C17 nUp vss 1.32fF
+C18 Up vss 2.53fF
+C19 Down vss 1.17fF
+C20 nDown vss 2.77fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 w_n359_n309# a_n221_n90# 0.09fF
+C1 a_n63_n116# a_n159_n207# 0.12fF
+C2 a_63_n90# a_159_n90# 0.26fF
+C3 a_63_n90# a_n33_n90# 0.26fF
+C4 w_n359_n309# a_63_n90# 0.06fF
+C5 a_n221_n90# a_63_n90# 0.06fF
+C6 a_n129_n90# a_159_n90# 0.06fF
+C7 a_n33_n90# a_n129_n90# 0.26fF
+C8 w_n359_n309# a_n129_n90# 0.06fF
+C9 a_n33_n90# a_159_n90# 0.09fF
+C10 a_n221_n90# a_n129_n90# 0.26fF
+C11 w_n359_n309# a_159_n90# 0.09fF
+C12 w_n359_n309# a_n33_n90# 0.05fF
+C13 a_63_n90# a_n129_n90# 0.09fF
+C14 a_n221_n90# a_159_n90# 0.04fF
+C15 a_n221_n90# a_n33_n90# 0.09fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n125_n45# a_n33_n45# 0.13fF
+C1 a_63_n45# a_n33_n45# 0.13fF
+C2 a_33_n71# a_n129_71# 0.04fF
+C3 a_63_n45# a_n125_n45# 0.05fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 vdd A 0.09fF
+C1 B A 0.24fF
+C2 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C3 A out 0.06fF
+C4 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
+C5 vdd out 0.11fF
+C6 B out 0.40fF
+C7 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out 0.08fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A Reset nor_pfd_2/B
+Xnor_pfd_0 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss CLK Q nor_pfd
+Xnor_pfd_1 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_3/A Reset nor_pfd
+C0 Q nor_pfd_2/B 2.22fF
+C1 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C2 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C4 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C5 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C6 vdd nor_pfd_3/A 0.09fF
+C7 Reset nor_pfd_3/A 0.12fF
+C8 nor_pfd_2/A vdd -0.01fF
+C9 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C10 Q nor_pfd_3/A 0.98fF
+C11 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C12 Q nor_pfd_2/A 1.38fF
+C13 Q vdd 0.08fF
+C14 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C15 CLK Q 0.04fF
+C16 Q Reset 0.14fF
+C17 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C18 vdd nor_pfd_2/B 0.02fF
+C19 Reset nor_pfd_2/B 0.43fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_n45# a_159_n45# 0.03fF
+C1 a_n129_n45# a_n221_n45# 0.13fF
+C2 a_n129_n45# a_63_n45# 0.05fF
+C3 a_n159_n173# a_n63_n71# 0.10fF
+C4 a_n33_n45# a_159_n45# 0.05fF
+C5 a_n221_n45# a_n33_n45# 0.05fF
+C6 a_63_n45# a_n33_n45# 0.13fF
+C7 a_n129_n45# a_n33_n45# 0.13fF
+C8 a_n221_n45# a_159_n45# 0.02fF
+C9 a_63_n45# a_159_n45# 0.13fF
+C10 a_n221_n45# a_63_n45# 0.03fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n99_n187# a_33_n187# 0.04fF
+C1 a_63_n90# a_n33_n90# 0.26fF
+C2 a_n125_n90# a_n33_n90# 0.26fF
+C3 a_63_n90# a_n125_n90# 0.09fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n73_n45# a_15_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 w_n211_n309# a_15_n90# 0.09fF
+C1 a_15_n90# a_n73_n90# 0.31fF
+C2 w_n211_n309# a_n73_n90# 0.04fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# out vss vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 a_656_410# A 0.04fF
+C1 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
+C2 a_656_410# vdd 0.20fF
+C3 out a_656_410# 0.20fF
+C4 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C5 B A 0.33fF
+C6 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C7 A vdd 0.05fF
+C8 B a_656_410# 0.30fF
+C9 out vdd 0.10fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Reset Down Up A B
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A Reset dff_pfd_0/nor_pfd_2/B
++ dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A Reset dff_pfd_1/nor_pfd_2/B
++ dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# Reset vss vdd Up Down and_pfd
+C0 vdd Up 1.62fF
+C1 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C2 Down Up 0.06fF
+C3 Reset vdd 0.02fF
+C4 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
+C5 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
+C6 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C7 vdd Down 0.08fF
+C8 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C9 dff_pfd_1/nor_pfd_2/B vdd 0.04fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+
+* Top level circuit top_pll_v3
+
+Xcharge_pump_0 nswitch vss vdd nUp Down charge_pump_0/w_2544_775# vco_vctrl pswitch
++ iref_cp nDown biasp Up vss charge_pump
+Xloop_filter_v2_0 lf_vc lf_D0 vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vdd vss n_out_div_2 out_by_2 n_out_by_2 out_buffer_div_2 n_out_buffer_div_2
++ out_to_div out_div_2 div_by_2
+Xfreq_div_0 clk_0 vss n_clk_0 vdd freq_div_0/prescaler_23_0/Q2 s_0 s_1_n s_1 freq_div_0/prescaler_23_0/nCLK_23
++ MC clk_d freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n clk_pre
++ freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out_div freq_div_0/div_by_5_0/Q1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ clk_2_f out_by_2 n_out_by_2 clk_5 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D
++ freq_div
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad vdd out_to_buffer vss buffer_salida
+Xring_osc_0 vco_vctrl vss vdd ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vss
++ vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div PFD
+C0 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D vco_vctrl 0.09fF
+C1 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.65fF
+C2 QA vdd -0.04fF
+C3 s_0 n_out_by_2 0.14fF
+C4 iref_cp Down 0.09fF
+C5 lf_vc MC 0.20fF
+C6 vco_vctrl s_0 0.45fF
+C7 clk_0 vco_vctrl -0.26fF
+C8 nUp biasp -0.16fF
+C9 nDown nswitch 0.76fF
+C10 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C11 Up biasp 0.26fF
+C12 pswitch nUp 0.93fF
+C13 vco_vctrl freq_div_0/prescaler_23_0/Q2 0.06fF
+C14 s_0_n n_out_by_2 0.14fF
+C15 nUp Up 2.72fF
+C16 s_0 out_to_div 0.94fF
+C17 pswitch Up 1.98fF
+C18 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD 0.09fF
+C19 vco_vctrl s_0_n 0.34fF
+C20 out_to_buffer out_to_div 0.13fF
+C21 nswitch Down 0.54fF
+C22 s_1_n out_div 0.09fF
+C23 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C24 nDown vdd 0.22fF
+C25 vco_D0 vdd 0.03fF
+C26 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD -0.42fF
+C27 vdd buffer_salida_0/a_678_n100# 0.24fF
+C28 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D 0.53fF
+C29 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C30 nDown Down 2.55fF
+C31 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D -0.42fF
+C32 freq_div_0/div_by_5_0/Q1 vco_vctrl 0.10fF
+C33 nDown charge_pump_0/w_2544_775# 0.05fF
+C34 clk_1 n_out_by_2 -0.10fF
+C35 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vco_vctrl 0.15fF
+C36 clk_1 vco_vctrl -0.04fF
+C37 nDown biasp 0.26fF
+C38 vco_vctrl n_clk_1 0.23fF
+C39 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
+C40 out_div clk_d 0.60fF
+C41 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C42 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD 1.23fF
+C43 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vco_vctrl 0.34fF
+C44 nUp nDown -0.09fF
+C45 pswitch nDown 0.53fF
+C46 clk_0 vdd 0.13fF
+C47 charge_pump_0/w_2544_775# Down -0.23fF
+C48 vco_vctrl vdd 0.58fF
+C49 out_to_buffer vdd 0.07fF
+C50 out_to_buffer buffer_salida_0/a_678_n100# 0.21fF
+C51 nUp vdd 0.05fF
+C52 vco_vctrl MC 0.33fF
+C53 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vco_vctrl 0.17fF
+C54 out_by_2 n_out_by_2 0.27fF
+C55 biasp Down 1.24fF
+C56 Up vdd 0.28fF
+C57 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vco_vctrl 0.82fF
+C58 s_1 out_div 0.37fF
+C59 vco_vctrl freq_div_0/prescaler_23_0/nCLK_23 0.06fF
+C60 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C61 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C62 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C63 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C64 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C65 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C66 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C67 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C68 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C69 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C70 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C71 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C72 QB vss 3.15fF
+C73 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C74 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C75 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C76 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C77 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C78 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C79 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C80 pfd_reset vss 1.87fF
+C81 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C82 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C83 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C84 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C85 QA vss 3.49fF
+C86 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C87 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C88 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C89 in_ref vss 0.84fF
+C90 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C91 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.66fF
+C92 nUp vss 0.12fF
+C93 Up vss -4.26fF
+C94 Down vss 1.89fF
+C95 nDown vss 2.59fF
+C96 out_to_buffer vss 1.92fF
+C97 out_to_div vss 8.72fF
+C98 out_first_buffer vss 2.15fF
+C99 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C100 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C101 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C102 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C103 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C104 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C105 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C106 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C107 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C108 vco_out vss 1.65fF
+C109 vco_D0 vss -4.72fF
+C110 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C111 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C112 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C113 out_to_pad vss 7.15fF
+C114 buffer_salida_0/a_3996_n100# vss 48.29fF
+C115 buffer_salida_0/a_678_n100# vss 13.38fF
+C116 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C117 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C118 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C119 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C120 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C121 freq_div_0/prescaler_23_0/Q2_d vss -0.69fF
+C122 freq_div_0/prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C123 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C124 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C125 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C126 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C127 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C128 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C129 freq_div_0/prescaler_23_0/Q2 vss 0.55fF
+C130 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C131 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C132 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C133 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C134 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C135 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C136 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C137 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C138 freq_div_0/prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C139 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C140 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C141 n_clk_0 vss -6.63fF
+C142 freq_div_0/prescaler_23_0/Q1 vss 0.07fF
+C143 freq_div_0/prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C144 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C145 clk_0 vss -0.36fF
+C146 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C147 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C148 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C149 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C150 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C151 freq_div_0/prescaler_23_0/nCLK_23 vss -1.02fF
+C152 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C153 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C154 MC vss -1.42fF
+C155 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C156 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C157 n_out_by_2 vss 4.53fF
+C158 out_by_2 vss 4.18fF
+C159 s_0_n vss -3.95fF
+C160 s_0 vss 5.61fF
+C161 freq_div_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C162 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C163 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C164 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C165 freq_div_0/div_by_5_0/Q1_shift vss -0.36fF
+C166 freq_div_0/div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C167 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C168 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C169 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C170 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C171 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C172 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C173 freq_div_0/div_by_5_0/Q1 vss 4.35fF
+C174 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C175 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C176 freq_div_0/div_by_5_0/Q0 vss 0.29fF
+C177 freq_div_0/div_by_5_0/nQ0 vss 0.99fF
+C178 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C179 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C180 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C181 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C182 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C183 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C184 freq_div_0/div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C185 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C186 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C187 freq_div_0/div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C188 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C189 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C190 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C191 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C192 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C193 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C194 freq_div_0/div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C195 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C196 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C197 n_clk_1 vss -0.57fF
+C198 freq_div_0/div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C199 freq_div_0/div_by_5_0/nQ2 vss 1.38fF
+C200 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C201 clk_1 vss -2.22fF
+C202 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C203 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C204 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C205 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C206 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C207 freq_div_0/div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C208 vdd vss 573.83fF
+C209 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C210 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C211 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C212 out_div vss 3.34fF
+C213 clk_d vss 1.26fF
+C214 s_1_n vss -2.01fF
+C215 s_1 vss 1.77fF
+C216 freq_div_0/inverter_min_x4_0/in vss 2.71fF
+C217 clk_5 vss -0.23fF
+C218 clk_out_mux21 vss 3.65fF
+C219 clk_pre vss 1.67fF
+C220 clk_2_f vss 3.29fF
+C221 freq_div_0/div_by_2_0/o1 vss 2.08fF
+C222 freq_div_0/div_by_2_0/nCLK_2 vss 1.04fF
+C223 freq_div_0/div_by_2_0/o2 vss 2.08fF
+C224 freq_div_0/div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C225 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C226 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C227 freq_div_0/div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C228 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C229 freq_div_0/div_by_2_0/out_div vss -0.82fF
+C230 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C231 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C232 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C233 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C234 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C235 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C236 freq_div_0/div_by_2_0/nout_div vss 2.62fF
+C237 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C238 out_buffer_div_2 vss 1.57fF
+C239 n_out_buffer_div_2 vss 1.57fF
+C240 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C241 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C242 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C243 div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C244 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C245 out_div_2 vss -0.70fF
+C246 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C247 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C248 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C249 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C250 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C251 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C252 n_out_div_2 vss 2.11fF
+C253 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C254 lf_vc vss -60.88fF
+C255 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C256 lf_D0 vss 0.01fF
+C257 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C258 nswitch vss 4.61fF
+C259 biasp vss 5.46fF
+C260 iref_cp vss 2.44fF
+C261 vco_vctrl vss -30.43fF
+C262 pswitch vss 2.72fF
+.end
+
diff --git a/mag/extractions/top_pll_v3_pex_c_port.spice b/mag/extractions/top_pll_v3_pex_c_port.spice
new file mode 100644
index 0000000..6410f8b
--- /dev/null
+++ b/mag/extractions/top_pll_v3_pex_c_port.spice
@@ -0,0 +1,3527 @@
+* NGSPICE file created from top_pll_v3.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_n29_n486# w_n2457_n634# 0.02fF
+C1 a_n1861_n486# w_n2457_n634# 0.02fF
+C2 a_429_n486# w_n2457_n634# 0.02fF
+C3 a_n945_n486# w_n2457_n634# 0.02fF
+C4 a_887_n486# w_n2457_n634# 0.02fF
+C5 a_1345_n486# w_n2457_n634# 0.02fF
+C6 w_n2457_n634# a_2261_n486# 0.02fF
+C7 a_n1403_n486# w_n2457_n634# 0.02fF
+C8 a_n487_n486# w_n2457_n634# 0.02fF
+C9 w_n2457_n634# a_n2319_n486# 0.02fF
+C10 a_1803_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n1041_n75# a_n849_n75# 0.08fF
+C1 a_n561_n75# a_n657_n75# 0.22fF
+C2 a_n81_n75# a_n465_n75# 0.03fF
+C3 a_n369_n75# a_15_n75# 0.03fF
+C4 a_207_n75# a_399_n75# 0.08fF
+C5 a_591_n75# a_495_n75# 0.22fF
+C6 a_1071_n75# a_879_n75# 0.08fF
+C7 a_n657_n75# a_n369_n75# 0.05fF
+C8 a_n753_n75# a_n657_n75# 0.22fF
+C9 a_111_n75# a_207_n75# 0.22fF
+C10 a_303_n75# a_399_n75# 0.22fF
+C11 a_207_n75# a_495_n75# 0.05fF
+C12 a_207_n75# a_n81_n75# 0.05fF
+C13 a_n657_n75# a_n465_n75# 0.08fF
+C14 a_1071_n75# a_975_n75# 0.22fF
+C15 a_111_n75# a_303_n75# 0.08fF
+C16 a_n945_n75# a_n561_n75# 0.03fF
+C17 a_207_n75# a_15_n75# 0.08fF
+C18 a_303_n75# a_495_n75# 0.08fF
+C19 a_303_n75# a_n81_n75# 0.03fF
+C20 a_111_n75# a_n273_n75# 0.03fF
+C21 a_n945_n75# a_n753_n75# 0.08fF
+C22 a_n177_n75# a_n561_n75# 0.03fF
+C23 a_111_n75# a_399_n75# 0.05fF
+C24 a_n273_n75# a_n81_n75# 0.08fF
+C25 a_303_n75# a_15_n75# 0.05fF
+C26 a_687_n75# a_783_n75# 0.22fF
+C27 a_399_n75# a_495_n75# 0.22fF
+C28 a_n1229_n75# a_n945_n75# 0.05fF
+C29 a_n1041_n75# a_n657_n75# 0.03fF
+C30 a_1071_n75# a_1167_n75# 0.22fF
+C31 a_n177_n75# a_n369_n75# 0.08fF
+C32 a_n273_n75# a_15_n75# 0.05fF
+C33 a_n657_n75# a_n849_n75# 0.08fF
+C34 a_111_n75# a_495_n75# 0.03fF
+C35 a_111_n75# a_n81_n75# 0.08fF
+C36 a_687_n75# a_879_n75# 0.08fF
+C37 a_399_n75# a_15_n75# 0.03fF
+C38 a_n273_n75# a_n657_n75# 0.03fF
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+C40 a_n561_n75# a_n369_n75# 0.08fF
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+C42 a_n753_n75# a_n561_n75# 0.08fF
+C43 a_591_n75# a_687_n75# 0.22fF
+C44 a_111_n75# a_15_n75# 0.22fF
+C45 a_783_n75# a_879_n75# 0.22fF
+C46 a_687_n75# a_975_n75# 0.05fF
+C47 a_n561_n75# a_n465_n75# 0.22fF
+C48 a_n81_n75# a_15_n75# 0.22fF
+C49 a_n753_n75# a_n369_n75# 0.03fF
+C50 a_n1041_n75# a_n945_n75# 0.22fF
+C51 a_207_n75# a_n177_n75# 0.03fF
+C52 a_591_n75# a_783_n75# 0.08fF
+C53 a_n945_n75# a_n849_n75# 0.22fF
+C54 a_n369_n75# a_n465_n75# 0.22fF
+C55 a_n753_n75# a_n465_n75# 0.05fF
+C56 a_783_n75# a_975_n75# 0.08fF
+C57 a_687_n75# a_303_n75# 0.03fF
+C58 a_591_n75# a_879_n75# 0.05fF
+C59 a_n1137_n75# a_n753_n75# 0.03fF
+C60 a_879_n75# a_975_n75# 0.22fF
+C61 a_n273_n75# a_n177_n75# 0.22fF
+C62 a_n561_n75# a_n849_n75# 0.05fF
+C63 a_n1229_n75# a_n1137_n75# 0.22fF
+C64 a_687_n75# a_399_n75# 0.05fF
+C65 a_591_n75# a_975_n75# 0.03fF
+C66 a_n1041_n75# a_n753_n75# 0.05fF
+C67 a_n273_n75# a_n561_n75# 0.05fF
+C68 a_1167_n75# a_783_n75# 0.03fF
+C69 a_111_n75# a_n177_n75# 0.05fF
+C70 a_n753_n75# a_n849_n75# 0.22fF
+C71 a_591_n75# a_207_n75# 0.03fF
+C72 a_n1229_n75# a_n1041_n75# 0.08fF
+C73 a_783_n75# a_399_n75# 0.03fF
+C74 a_687_n75# a_495_n75# 0.08fF
+C75 a_n273_n75# a_n369_n75# 0.22fF
+C76 a_n177_n75# a_n81_n75# 0.22fF
+C77 a_n1229_n75# a_n849_n75# 0.03fF
+C78 a_n465_n75# a_n849_n75# 0.03fF
+C79 a_1167_n75# a_879_n75# 0.05fF
+C80 a_n945_n75# a_n657_n75# 0.05fF
+C81 a_591_n75# a_303_n75# 0.05fF
+C82 a_n1137_n75# a_n1041_n75# 0.22fF
+C83 a_n273_n75# a_n465_n75# 0.08fF
+C84 a_n177_n75# a_15_n75# 0.08fF
+C85 a_1071_n75# a_687_n75# 0.03fF
+C86 a_783_n75# a_495_n75# 0.05fF
+C87 a_n1137_n75# a_n849_n75# 0.05fF
+C88 a_1167_n75# a_975_n75# 0.08fF
+C89 a_207_n75# a_303_n75# 0.22fF
+C90 a_591_n75# a_399_n75# 0.08fF
+C91 a_n81_n75# a_n369_n75# 0.05fF
+C92 a_1071_n75# a_783_n75# 0.05fF
+C93 a_879_n75# a_495_n75# 0.03fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_543_n75# a_831_n75# 0.05fF
+C1 a_n321_n75# a_63_n75# 0.03fF
+C2 a_n33_n75# a_n417_n75# 0.03fF
+C3 a_735_n75# a_927_n75# 0.08fF
+C4 a_447_n75# a_63_n75# 0.03fF
+C5 a_n897_n75# a_n609_n75# 0.05fF
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+C7 a_n801_n75# a_n989_n75# 0.08fF
+C8 a_447_n75# a_159_n75# 0.05fF
+C9 a_n801_n75# a_n417_n75# 0.03fF
+C10 a_351_n75# a_n33_n75# 0.03fF
+C11 a_831_n75# a_927_n75# 0.22fF
+C12 a_n801_n75# a_n897_n75# 0.22fF
+C13 a_351_n75# a_63_n75# 0.05fF
+C14 a_543_n75# a_927_n75# 0.03fF
+C15 a_n705_n75# a_n609_n75# 0.22fF
+C16 a_351_n75# a_159_n75# 0.08fF
+C17 a_n609_n75# a_n225_n75# 0.03fF
+C18 a_n129_n75# a_n513_n75# 0.03fF
+C19 a_n225_n75# a_n33_n75# 0.08fF
+C20 a_n927_n101# a_33_n101# 0.08fF
+C21 a_255_n75# a_n129_n75# 0.03fF
+C22 a_n801_n75# a_n705_n75# 0.22fF
+C23 a_n129_n75# a_n321_n75# 0.08fF
+C24 a_n225_n75# a_63_n75# 0.05fF
+C25 a_255_n75# a_639_n75# 0.03fF
+C26 a_543_n75# a_159_n75# 0.03fF
+C27 a_n225_n75# a_159_n75# 0.03fF
+C28 a_639_n75# a_447_n75# 0.08fF
+C29 a_n129_n75# a_n417_n75# 0.05fF
+C30 a_n513_n75# a_n321_n75# 0.08fF
+C31 a_n801_n75# a_n609_n75# 0.08fF
+C32 a_255_n75# a_447_n75# 0.08fF
+C33 a_n513_n75# a_n417_n75# 0.22fF
+C34 a_n33_n75# a_63_n75# 0.22fF
+C35 a_639_n75# a_735_n75# 0.22fF
+C36 a_159_n75# a_n33_n75# 0.08fF
+C37 a_351_n75# a_639_n75# 0.05fF
+C38 a_n897_n75# a_n513_n75# 0.03fF
+C39 a_n321_n75# a_n417_n75# 0.22fF
+C40 a_255_n75# a_351_n75# 0.22fF
+C41 a_159_n75# a_63_n75# 0.22fF
+C42 a_639_n75# a_831_n75# 0.08fF
+C43 a_735_n75# a_447_n75# 0.05fF
+C44 a_351_n75# a_447_n75# 0.22fF
+C45 a_n989_n75# a_n897_n75# 0.22fF
+C46 a_n225_n75# a_n129_n75# 0.22fF
+C47 a_639_n75# a_543_n75# 0.22fF
+C48 a_n705_n75# a_n513_n75# 0.08fF
+C49 a_831_n75# a_447_n75# 0.03fF
+C50 a_n225_n75# a_n513_n75# 0.05fF
+C51 a_255_n75# a_543_n75# 0.05fF
+C52 a_351_n75# a_735_n75# 0.03fF
+C53 a_543_n75# a_447_n75# 0.22fF
+C54 a_639_n75# a_927_n75# 0.05fF
+C55 a_n705_n75# a_n321_n75# 0.03fF
+C56 a_n129_n75# a_n33_n75# 0.22fF
+C57 a_n225_n75# a_n321_n75# 0.22fF
+C58 a_n705_n75# a_n989_n75# 0.05fF
+C59 a_n609_n75# a_n513_n75# 0.22fF
+C60 a_n705_n75# a_n417_n75# 0.05fF
+C61 a_735_n75# a_831_n75# 0.22fF
+C62 a_n225_n75# a_n417_n75# 0.08fF
+C63 a_n129_n75# a_63_n75# 0.08fF
+C64 a_n609_n75# a_n321_n75# 0.05fF
+C65 a_255_n75# a_n33_n75# 0.05fF
+C66 a_n705_n75# a_n897_n75# 0.08fF
+C67 a_543_n75# a_735_n75# 0.08fF
+C68 a_351_n75# a_543_n75# 0.08fF
+C69 a_n129_n75# a_159_n75# 0.05fF
+C70 a_n989_n75# a_n609_n75# 0.03fF
+C71 a_n33_n75# a_n321_n75# 0.05fF
+C72 a_n801_n75# a_n513_n75# 0.05fF
+C73 a_n609_n75# a_n417_n75# 0.08fF
+C74 a_255_n75# a_63_n75# 0.08fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_255_n150# a_543_n150# 0.10fF
+C1 a_63_n150# a_n33_n150# 0.43fF
+C2 a_159_n150# a_447_n150# 0.10fF
+C3 a_639_n150# a_543_n150# 0.43fF
+C4 a_n513_n150# a_n129_n150# 0.07fF
+C5 a_n225_n150# a_n609_n150# 0.07fF
+C6 a_n989_n150# a_n801_n150# 0.16fF
+C7 a_159_n150# a_n225_n150# 0.07fF
+C8 a_639_n150# a_831_n150# 0.16fF
+C9 a_n897_n150# a_n801_n150# 0.43fF
+C10 a_159_n150# a_n129_n150# 0.10fF
+C11 a_255_n150# a_159_n150# 0.43fF
+C12 a_159_n150# a_n33_n150# 0.16fF
+C13 a_n417_n150# a_n801_n150# 0.07fF
+C14 a_351_n150# a_447_n150# 0.43fF
+C15 a_735_n150# a_927_n150# 0.16fF
+C16 a_n321_n150# a_63_n150# 0.07fF
+C17 a_n417_n150# a_n225_n150# 0.16fF
+C18 a_735_n150# a_543_n150# 0.16fF
+C19 a_n705_n150# a_n321_n150# 0.07fF
+C20 a_255_n150# a_351_n150# 0.43fF
+C21 a_n417_n150# a_n129_n150# 0.10fF
+C22 a_n321_n150# a_n513_n150# 0.16fF
+C23 a_639_n150# a_351_n150# 0.10fF
+C24 a_543_n150# a_927_n150# 0.07fF
+C25 a_735_n150# a_831_n150# 0.43fF
+C26 a_351_n150# a_n33_n150# 0.07fF
+C27 a_n417_n150# a_n33_n150# 0.07fF
+C28 a_n321_n150# a_n609_n150# 0.10fF
+C29 a_255_n150# a_447_n150# 0.16fF
+C30 a_n705_n150# a_n513_n150# 0.16fF
+C31 a_927_n150# a_831_n150# 0.43fF
+C32 a_639_n150# a_447_n150# 0.16fF
+C33 a_n225_n150# a_n129_n150# 0.43fF
+C34 a_159_n150# a_63_n150# 0.43fF
+C35 a_543_n150# a_831_n150# 0.10fF
+C36 a_n705_n150# a_n609_n150# 0.43fF
+C37 a_n33_n150# a_n225_n150# 0.16fF
+C38 a_159_n150# a_543_n150# 0.07fF
+C39 a_n513_n150# a_n609_n150# 0.43fF
+C40 a_255_n150# a_n129_n150# 0.07fF
+C41 a_639_n150# a_255_n150# 0.07fF
+C42 a_n705_n150# a_n989_n150# 0.10fF
+C43 a_n33_n150# a_n129_n150# 0.43fF
+C44 a_255_n150# a_n33_n150# 0.10fF
+C45 a_735_n150# a_351_n150# 0.07fF
+C46 a_n417_n150# a_n321_n150# 0.43fF
+C47 a_33_n247# a_n927_n247# 0.09fF
+C48 a_n705_n150# a_n897_n150# 0.16fF
+C49 a_n989_n150# a_n609_n150# 0.07fF
+C50 a_351_n150# a_63_n150# 0.10fF
+C51 a_n897_n150# a_n513_n150# 0.07fF
+C52 a_735_n150# a_447_n150# 0.10fF
+C53 a_351_n150# a_543_n150# 0.16fF
+C54 a_n705_n150# a_n417_n150# 0.10fF
+C55 a_n897_n150# a_n609_n150# 0.10fF
+C56 a_n417_n150# a_n513_n150# 0.43fF
+C57 a_n321_n150# a_n225_n150# 0.43fF
+C58 a_447_n150# a_63_n150# 0.07fF
+C59 a_n705_n150# a_n801_n150# 0.43fF
+C60 a_n989_n150# a_n897_n150# 0.43fF
+C61 a_n801_n150# a_n513_n150# 0.10fF
+C62 a_n321_n150# a_n129_n150# 0.16fF
+C63 a_543_n150# a_447_n150# 0.43fF
+C64 a_n417_n150# a_n609_n150# 0.16fF
+C65 a_63_n150# a_n225_n150# 0.10fF
+C66 a_735_n150# a_639_n150# 0.43fF
+C67 a_351_n150# a_159_n150# 0.16fF
+C68 a_n321_n150# a_n33_n150# 0.10fF
+C69 a_n801_n150# a_n609_n150# 0.16fF
+C70 a_63_n150# a_n129_n150# 0.16fF
+C71 a_n225_n150# a_n513_n150# 0.10fF
+C72 a_255_n150# a_63_n150# 0.16fF
+C73 a_639_n150# a_927_n150# 0.10fF
+C74 a_447_n150# a_831_n150# 0.07fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n1461_n44# a_n1819_n44# 0.04fF
+C1 a_n29_n44# a_329_n44# 0.04fF
+C2 a_n1103_n44# a_n745_n44# 0.04fF
+C3 a_n387_n44# a_n745_n44# 0.04fF
+C4 a_1045_n44# a_1403_n44# 0.04fF
+C5 a_1761_n44# a_1403_n44# 0.04fF
+C6 a_329_n44# a_687_n44# 0.04fF
+C7 a_687_n44# a_1045_n44# 0.04fF
+C8 a_n1103_n44# a_n1461_n44# 0.04fF
+C9 a_n29_n44# a_n387_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_879_n150# a_1167_n150# 0.10fF
+C1 a_n1041_n150# a_n1137_n150# 0.43fF
+C2 a_n273_n150# a_111_n150# 0.07fF
+C3 a_111_n150# a_15_n150# 0.43fF
+C4 a_n753_n150# a_n465_n150# 0.10fF
+C5 a_n849_n150# a_n1229_n150# 0.07fF
+C6 a_n561_n150# a_n369_n150# 0.16fF
+C7 w_n1367_n369# a_1167_n150# 0.14fF
+C8 a_975_n150# a_879_n150# 0.43fF
+C9 a_111_n150# a_n81_n150# 0.16fF
+C10 a_591_n150# a_687_n150# 0.43fF
+C11 a_783_n150# a_1071_n150# 0.10fF
+C12 a_975_n150# w_n1367_n369# 0.05fF
+C13 a_n1137_n150# a_n849_n150# 0.10fF
+C14 a_495_n150# a_303_n150# 0.16fF
+C15 a_111_n150# a_303_n150# 0.16fF
+C16 a_111_n150# a_n177_n150# 0.10fF
+C17 a_n465_n150# a_n369_n150# 0.43fF
+C18 a_n945_n150# a_n1229_n150# 0.10fF
+C19 a_879_n150# w_n1367_n369# 0.04fF
+C20 a_n753_n150# a_n369_n150# 0.07fF
+C21 a_n945_n150# a_n1137_n150# 0.16fF
+C22 a_591_n150# a_495_n150# 0.43fF
+C23 a_687_n150# a_1071_n150# 0.07fF
+C24 a_783_n150# a_687_n150# 0.43fF
+C25 a_207_n150# a_399_n150# 0.16fF
+C26 a_207_n150# a_15_n150# 0.16fF
+C27 a_n657_n150# a_n1041_n150# 0.07fF
+C28 a_207_n150# a_n81_n150# 0.10fF
+C29 a_495_n150# a_783_n150# 0.10fF
+C30 a_n273_n150# a_n657_n150# 0.07fF
+C31 a_591_n150# a_975_n150# 0.07fF
+C32 a_15_n150# a_399_n150# 0.07fF
+C33 a_n753_n150# a_n1137_n150# 0.07fF
+C34 a_207_n150# a_303_n150# 0.43fF
+C35 a_n657_n150# a_n849_n150# 0.16fF
+C36 a_207_n150# a_n177_n150# 0.07fF
+C37 a_n1041_n150# a_n849_n150# 0.16fF
+C38 a_n273_n150# a_15_n150# 0.10fF
+C39 a_495_n150# a_687_n150# 0.16fF
+C40 a_1071_n150# a_1167_n150# 0.43fF
+C41 a_399_n150# a_303_n150# 0.43fF
+C42 a_n273_n150# a_n81_n150# 0.16fF
+C43 a_591_n150# a_879_n150# 0.10fF
+C44 a_15_n150# a_n81_n150# 0.43fF
+C45 a_207_n150# a_591_n150# 0.07fF
+C46 a_783_n150# a_1167_n150# 0.07fF
+C47 a_975_n150# a_1071_n150# 0.43fF
+C48 a_n657_n150# a_n945_n150# 0.10fF
+C49 a_n945_n150# a_n1041_n150# 0.43fF
+C50 a_15_n150# a_303_n150# 0.10fF
+C51 a_783_n150# a_975_n150# 0.16fF
+C52 a_n273_n150# a_n177_n150# 0.43fF
+C53 a_15_n150# a_n177_n150# 0.16fF
+C54 a_n657_n150# a_n561_n150# 0.43fF
+C55 a_303_n150# a_n81_n150# 0.07fF
+C56 a_591_n150# a_399_n150# 0.16fF
+C57 a_n81_n150# a_n177_n150# 0.43fF
+C58 a_879_n150# a_1071_n150# 0.16fF
+C59 a_n945_n150# a_n849_n150# 0.43fF
+C60 a_111_n150# a_495_n150# 0.07fF
+C61 a_n273_n150# a_n561_n150# 0.10fF
+C62 a_783_n150# a_879_n150# 0.43fF
+C63 a_n1137_n150# a_n1229_n150# 0.43fF
+C64 w_n1367_n369# a_1071_n150# 0.07fF
+C65 a_n657_n150# a_n465_n150# 0.16fF
+C66 a_n561_n150# a_n849_n150# 0.10fF
+C67 a_975_n150# a_687_n150# 0.10fF
+C68 a_n657_n150# a_n753_n150# 0.43fF
+C69 a_591_n150# a_303_n150# 0.10fF
+C70 a_n273_n150# a_n465_n150# 0.16fF
+C71 a_n561_n150# a_n177_n150# 0.07fF
+C72 a_783_n150# a_399_n150# 0.07fF
+C73 a_n753_n150# a_n1041_n150# 0.10fF
+C74 a_n465_n150# a_n849_n150# 0.07fF
+C75 a_n465_n150# a_n81_n150# 0.07fF
+C76 a_n945_n150# a_n561_n150# 0.07fF
+C77 a_879_n150# a_687_n150# 0.16fF
+C78 a_n753_n150# a_n849_n150# 0.43fF
+C79 a_n657_n150# a_n369_n150# 0.10fF
+C80 a_n465_n150# a_n177_n150# 0.10fF
+C81 a_399_n150# a_687_n150# 0.10fF
+C82 a_n273_n150# a_n369_n150# 0.43fF
+C83 a_15_n150# a_n369_n150# 0.07fF
+C84 a_495_n150# a_879_n150# 0.07fF
+C85 a_207_n150# a_495_n150# 0.10fF
+C86 a_n561_n150# a_n465_n150# 0.43fF
+C87 a_n945_n150# a_n753_n150# 0.16fF
+C88 a_n81_n150# a_n369_n150# 0.10fF
+C89 a_207_n150# a_111_n150# 0.43fF
+C90 a_975_n150# a_1167_n150# 0.16fF
+C91 a_n753_n150# a_n561_n150# 0.16fF
+C92 a_591_n150# a_783_n150# 0.16fF
+C93 a_495_n150# a_399_n150# 0.43fF
+C94 a_n369_n150# a_n177_n150# 0.16fF
+C95 a_n1041_n150# a_n1229_n150# 0.16fF
+C96 a_111_n150# a_399_n150# 0.10fF
+C97 a_687_n150# a_303_n150# 0.07fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vss vdd nUp Down w_2544_775# out pswitch iref nDown biasp
++ Up w_6648_570#
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 nUp Up 0.15fF
+C1 biasp iref 0.80fF
+C2 vdd out 6.66fF
+C3 nDown nswitch 0.31fF
+C4 vdd nswitch 0.07fF
+C5 biasp nswitch 0.03fF
+C6 pswitch out 4.91fF
+C7 Down nswitch 2.27fF
+C8 pswitch nswitch 0.06fF
+C9 nUp Down 0.25fF
+C10 Up pswitch 0.70fF
+C11 nUp pswitch 5.66fF
+C12 iref nswitch 1.91fF
+C13 Down nDown 0.13fF
+C14 out nswitch 1.28fF
+C15 vdd biasp 2.64fF
+C16 nUp out 0.31fF
+C17 vdd pswitch 3.98fF
+C18 biasp pswitch 3.11fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C1 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C2 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C3 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C4 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C5 m3_n2650_n2600# m3_n2650_n7900# 3.28fF
+C6 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C7 m3_7988_8000# m3_7988_2700# 3.39fF
+C8 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C9 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C10 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C11 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C12 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C13 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C14 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C15 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C16 m3_2669_2700# m3_2669_8000# 3.28fF
+C17 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C18 m3_2669_2700# m3_n2650_2700# 2.73fF
+C19 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C20 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C21 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C22 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C23 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C24 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C25 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
+C26 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C27 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C28 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C29 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C30 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C31 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C32 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C33 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C34 m3_2669_8000# m3_7988_8000# 2.73fF
+C35 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C36 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C37 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C38 m3_2669_8000# m3_n2650_8000# 2.73fF
+C39 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C40 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C41 m3_2669_n13200# m3_7988_n13200# 2.73fF
+C42 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C43 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C44 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C45 m3_2669_n2600# m3_n2650_n2600# 2.73fF
+C46 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C47 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C48 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C49 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C50 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C51 m3_2669_2700# m3_7988_2700# 2.73fF
+C52 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C53 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C54 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C55 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C56 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
+C57 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C58 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C59 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C60 m3_n2650_n2600# m3_n2650_2700# 3.28fF
+C61 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C62 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C63 m3_2669_2700# m3_2669_n2600# 3.28fF
+C64 m3_7988_n2600# m3_7988_2700# 3.39fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_10_n4250# m3_n4309_50# 1.75fF
+C1 c1_n4209_n4150# m3_n4309_50# 38.10fF
+C2 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C3 m3_10_n4250# c1_110_n4150# 81.11fF
+C4 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C5 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C6 c1_n4209_n4150# c1_110_n4150# 1.32fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 in out 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C1 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C2 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C3 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C4 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C5 m3_n2150_2200# m3_n6469_2200# 1.75fF
+C6 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C7 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C8 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C9 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C10 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C11 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C12 m3_n2150_2200# m3_n2150_n2100# 2.63fF
+C13 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C14 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C15 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C16 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C17 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C18 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_30_n300# a_n88_n300# 0.61fF
+C1 a_n118_n388# a_n88_n300# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in cap3_loop_filter_0/in 0.79fF
+C1 in D0_cap 0.07fF
+C2 in vc_pex 0.18fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS w_n311_n338# a_81_n156# a_111_n125# a_15_n125#
++ a_n173_n125# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_81_n156# a_n15_n156# 0.02fF
+C1 a_15_n125# a_n81_n125# 0.36fF
+C2 a_111_n125# a_15_n125# 0.36fF
+C3 a_n173_n125# a_15_n125# 0.13fF
+C4 a_111_n125# a_n81_n125# 0.13fF
+C5 a_n111_n156# a_n15_n156# 0.02fF
+C6 a_n173_n125# a_n81_n125# 0.36fF
+C7 a_111_n125# a_n173_n125# 0.08fF
+C8 a_111_n125# VSUBS 0.03fF
+C9 a_15_n125# VSUBS 0.03fF
+C10 a_n81_n125# VSUBS 0.03fF
+C11 a_n173_n125# VSUBS 0.03fF
+C12 a_81_n156# VSUBS 0.05fF
+C13 a_n15_n156# VSUBS 0.05fF
+C14 a_n111_n156# VSUBS 0.05fF
+C15 w_n311_n338# VSUBS 1.56fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n15_n151# a_n111_n151# 0.02fF
+C1 a_n173_n125# a_n81_n125# 0.36fF
+C2 a_n15_n151# a_81_n151# 0.02fF
+C3 a_111_n125# a_n173_n125# 0.08fF
+C4 a_111_n125# a_n81_n125# 0.13fF
+C5 a_n173_n125# a_15_n125# 0.13fF
+C6 a_n81_n125# a_15_n125# 0.36fF
+C7 a_111_n125# a_15_n125# 0.36fF
+C8 a_111_n125# w_n311_n335# 0.04fF
+C9 a_15_n125# w_n311_n335# 0.04fF
+C10 a_n81_n125# w_n311_n335# 0.04fF
+C11 a_n173_n125# w_n311_n335# 0.04fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# vss m1_45_n513# vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd vss m1_187_n605# m1_45_n513# m1_45_n513#
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_187_n605# vdd 0.55fF
+C1 m1_187_n605# m1_45_n513# 0.36fF
+C2 m1_45_n513# vdd 0.69fF
+C3 m1_187_n605# vss 0.73fF
+C4 m1_45_n513# vss 1.10fF
+C5 vdd vss 2.55fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n311_n344# a_n173_n125# 0.14fF
+C1 a_n81_n125# a_111_n125# 0.13fF
+C2 a_15_n125# a_n173_n125# 0.13fF
+C3 a_15_n125# w_n311_n344# 0.09fF
+C4 a_n173_n125# a_111_n125# 0.08fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 w_n311_n344# a_111_n125# 0.14fF
+C7 w_n311_n344# a_n81_n125# 0.09fF
+C8 a_15_n125# a_111_n125# 0.36fF
+C9 a_15_n125# a_n81_n125# 0.36fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n173_n125# 0.08fF
+C1 a_111_n125# a_n81_n125# 0.13fF
+C2 a_15_n125# a_n173_n125# 0.13fF
+C3 a_15_n125# a_n81_n125# 0.36fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 in out 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d vss inverter_cp_x1_0/out vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd CLK_d 0.03fF
+C1 inverter_cp_x1_0/out vdd 0.21fF
+C2 CLK inverter_cp_x1_2/in 0.31fF
+C3 nCLK_d inverter_cp_x1_0/out 0.11fF
+C4 inverter_cp_x1_2/in CLK_d 0.12fF
+C5 inverter_cp_x1_0/out CLK 0.31fF
+C6 nCLK_d vdd 0.03fF
+C7 CLK vdd 0.36fF
+C8 vdd inverter_cp_x1_2/in 0.21fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.69fF
+C12 CLK vss 3.03fF
+C13 vdd vss 15.46fF
+C14 nCLK_d vss 1.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_63_n95# 0.11fF
+C1 a_n125_n95# a_63_n95# 0.10fF
+C2 w_n263_n314# a_n33_n95# 0.08fF
+C3 a_n33_n95# a_n125_n95# 0.28fF
+C4 w_n263_n314# a_n125_n95# 0.11fF
+C5 a_n33_n95# a_63_n95# 0.28fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n129_n213# a_111_n125# 0.01fF
+C1 a_15_n125# a_n173_n125# 0.13fF
+C2 a_n129_n213# a_n173_n125# 0.02fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_n129_n213# a_15_n125# 0.10fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 a_n173_n125# a_111_n125# 0.08fF
+C8 a_n129_n213# a_n81_n125# 0.10fF
+C9 a_15_n125# a_111_n125# 0.36fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n81_n183# a_n125_n95# 0.16fF
+C1 a_n33_n95# a_n125_n95# 0.88fF
+C2 a_n81_n183# a_n33_n95# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 D Q 0.05fF
+C1 Q nD 0.05fF
+C2 vdd nQ 0.16fF
+C3 nQ m1_657_280# 1.41fF
+C4 D nQ 0.05fF
+C5 nQ Q 0.93fF
+C6 nQ nD 0.05fF
+C7 m1_657_280# CLK 0.24fF
+C8 vdd Q 0.16fF
+C9 Q m1_657_280# 0.94fF
+C10 D vss 0.53fF
+C11 m1_657_280# vss 1.88fF
+C12 nD vss 0.16fF
+C13 CLK vss 0.87fF
+C14 Q vss -0.55fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vdd vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ nCLK latch_diff_0/nD Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D
++ CLK clock_inverter_0/inverter_cp_x1_0/out
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C1 latch_diff_1/D vdd 0.01fF
+C2 latch_diff_1/nD nQ 0.08fF
+C3 latch_diff_0/nD vdd 0.14fF
+C4 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
+C5 latch_diff_0/D latch_diff_0/m1_657_280# 0.37fF
+C6 latch_diff_0/nD latch_diff_1/D 0.41fF
+C7 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
+C8 latch_diff_0/D vdd 0.09fF
+C9 latch_diff_0/D latch_diff_1/D 0.11fF
+C10 latch_diff_1/nD vdd 0.02fF
+C11 latch_diff_1/nD latch_diff_1/D 0.33fF
+C12 latch_diff_1/nD Q 0.01fF
+C13 latch_diff_0/D latch_diff_1/nD 0.04fF
+C14 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C15 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C16 latch_diff_1/D nQ 0.11fF
+C17 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C18 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C19 latch_diff_1/m1_657_280# vss 0.64fF
+C20 nCLK vss 0.83fF
+C21 Q vss -0.92fF
+C22 nQ vss 0.57fF
+C23 latch_diff_0/m1_657_280# vss 0.69fF
+C24 CLK vss 0.83fF
+C25 latch_diff_1/D vss -0.33fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.63fF
+C30 D vss 3.27fF
+C31 vdd vss 31.85fF
+C32 latch_diff_0/nD vss 1.53fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_159_n84# w_n359_n303# 0.08fF
+C1 a_159_n84# a_n33_n84# 0.09fF
+C2 a_159_n84# a_n129_n84# 0.05fF
+C3 a_63_n84# w_n359_n303# 0.06fF
+C4 a_63_n84# a_n33_n84# 0.24fF
+C5 a_63_n84# a_n129_n84# 0.09fF
+C6 a_159_n84# a_n221_n84# 0.04fF
+C7 a_63_n84# a_n221_n84# 0.05fF
+C8 a_159_n84# a_63_n84# 0.24fF
+C9 a_n159_n110# a_n63_n110# 0.02fF
+C10 a_n33_n84# w_n359_n303# 0.05fF
+C11 a_n129_n84# w_n359_n303# 0.06fF
+C12 a_n33_n84# a_n129_n84# 0.24fF
+C13 a_33_n110# a_n63_n110# 0.02fF
+C14 a_n221_n84# w_n359_n303# 0.08fF
+C15 a_n33_n84# a_n221_n84# 0.09fF
+C16 a_n129_n84# a_n221_n84# 0.24fF
+C17 a_129_n110# a_33_n110# 0.02fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_63_n42# a_159_n42# 0.12fF
+C2 a_n129_n42# a_159_n42# 0.03fF
+C3 a_n221_n42# a_n33_n42# 0.05fF
+C4 a_n63_n68# a_n159_n68# 0.02fF
+C5 a_33_n68# a_129_n68# 0.02fF
+C6 a_63_n42# a_n33_n42# 0.12fF
+C7 a_n221_n42# a_63_n42# 0.03fF
+C8 a_n33_n42# a_n129_n42# 0.12fF
+C9 a_n221_n42# a_n129_n42# 0.12fF
+C10 a_n33_n42# a_159_n42# 0.05fF
+C11 a_n221_n42# a_159_n42# 0.02fF
+C12 a_63_n42# a_n129_n42# 0.05fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 in vdd 0.33fF
+C1 vdd out 0.62fF
+C2 in out 0.67fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n42# a_63_n42# 0.12fF
+C1 a_n125_n42# a_63_n42# 0.05fF
+C2 a_n63_n68# a_33_n68# 0.02fF
+C3 a_n33_n42# a_n125_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n125_n84# a_n33_n84# 0.24fF
+C1 a_63_n84# a_n33_n84# 0.24fF
+C2 a_n125_n84# a_63_n84# 0.09fF
+C3 w_n263_n303# a_n33_n84# 0.07fF
+C4 a_n125_n84# w_n263_n303# 0.10fF
+C5 a_33_n110# a_n63_n110# 0.02fF
+C6 w_n263_n303# a_63_n84# 0.10fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 in vdd 0.01fF
+C1 vdd out 0.15fF
+C2 in out 0.30fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vdd vss nout_div CLK_2 nCLK_2 o1 o2 CLK out_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD
++ out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 o1 CLK_2 0.11fF
+C1 vdd DFlipFlop_0/CLK 0.40fF
+C2 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C3 nout_div out_div 0.22fF
+C4 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C5 vdd DFlipFlop_0/nCLK 0.30fF
+C6 vdd nCLK_2 0.08fF
+C7 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C8 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C9 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C10 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
+C11 o1 vdd 0.14fF
+C12 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C13 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C14 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C15 vdd out_div 0.03fF
+C16 DFlipFlop_0/latch_diff_0/D DFlipFlop_0/nCLK 0.13fF
+C17 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C18 o2 vdd 0.14fF
+C19 vdd CLK_2 0.08fF
+C20 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C21 vdd nout_div 0.16fF
+C22 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C23 nout_div DFlipFlop_0/CLK 0.42fF
+C24 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/CLK -0.48fF
+C25 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C26 DFlipFlop_0/latch_diff_0/nD nout_div 0.07fF
+C27 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C28 o2 nCLK_2 0.11fF
+C29 nout_div DFlipFlop_0/nCLK 0.43fF
+C30 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
+C31 o1 out_div 0.01fF
+C32 DFlipFlop_0/latch_diff_0/D nout_div 0.09fF
+C33 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C34 CLK_2 vss 1.08fF
+C35 o1 vss 2.21fF
+C36 nCLK_2 vss 1.08fF
+C37 o2 vss 2.21fF
+C38 DFlipFlop_0/CLK vss 1.03fF
+C39 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C40 clock_inverter_0/inverter_cp_x1_0/out vss 1.64fF
+C41 CLK vss 3.27fF
+C42 DFlipFlop_0/nCLK vss 1.55fF
+C43 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C46 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C47 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C48 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.59fF
+C51 nout_div vss 4.41fF
+C52 vdd vss 62.89fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+.ends
+
+.subckt trans_gate_mux2to8 in vss out en_pos en_neg vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd en_neg in out out en_neg en_neg in sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 en_pos vss en_pos in out out en_pos in sky130_fd_pr__nfet_01v8_BHR94T
+C0 in en_neg 0.28fF
+C1 out en_neg 0.07fF
+C2 en_pos en_neg 0.04fF
+C3 out in 0.36fF
+C4 en_pos in 0.07fF
+C5 out en_pos 0.27fF
+C6 vdd in 0.05fF
+C7 out vdd 0.27fF
+C8 vdd vss 2.08fF
+C9 in vss 1.12fF
+C10 out vss 0.87fF
+C11 en_pos vss 0.29fF
+C12 en_neg vss 0.31fF
+.ends
+
+.subckt mux2to1 vss select_0_neg out_a_0 out_a_1 select_0 vdd in_a
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 select_0_neg select_0 0.17fF
+C1 select_0_neg in_a 0.11fF
+C2 vdd out_a_0 0.06fF
+C3 vdd out_a_1 0.06fF
+C4 select_0_neg out_a_0 0.05fF
+C5 in_a select_0 0.31fF
+C6 out_a_1 select_0 0.14fF
+C7 in_a out_a_0 0.08fF
+C8 in_a out_a_1 0.08fF
+C9 vdd in_a 0.02fF
+C10 out_a_1 vss 0.99fF
+C11 vdd vss 4.78fF
+C12 in_a vss 2.00fF
+C13 out_a_0 vss 0.99fF
+C14 select_0_neg vss 1.15fF
+C15 select_0 vss 0.97fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 B a_194_125# 0.57fF
+C1 VPWR a_355_368# 0.37fF
+C2 VPWR X 0.07fF
+C3 VPWR VGND 0.01fF
+C4 A a_355_368# 0.02fF
+C5 A VGND 0.31fF
+C6 VPWR a_194_125# 0.33fF
+C7 X a_355_368# 0.17fF
+C8 a_158_392# a_194_125# 0.06fF
+C9 VGND X 0.28fF
+C10 B VPWR 0.09fF
+C11 A a_194_125# 0.18fF
+C12 VPWR VPB 0.06fF
+C13 a_194_125# a_355_368# 0.51fF
+C14 a_194_125# X 0.29fF
+C15 B A 0.28fF
+C16 VGND a_194_125# 0.25fF
+C17 B a_355_368# 0.08fF
+C18 B X 0.13fF
+C19 B VGND 0.10fF
+C20 VPWR A 0.15fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 VPWR VPB 0.04fF
+C1 B a_56_136# 0.30fF
+C2 A a_56_136# 0.17fF
+C3 VGND a_56_136# 0.06fF
+C4 a_56_136# X 0.26fF
+C5 B VPWR 0.02fF
+C6 A VPWR 0.07fF
+C7 VPWR X 0.20fF
+C8 B A 0.08fF
+C9 VGND B 0.03fF
+C10 VGND A 0.21fF
+C11 B X 0.02fF
+C12 VGND X 0.15fF
+C13 VPWR a_56_136# 0.57fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VPWR VPB 0.04fF
+C1 a_63_368# a_152_368# 0.03fF
+C2 VPWR A 0.05fF
+C3 X VGND 0.16fF
+C4 B VGND 0.11fF
+C5 X VPWR 0.18fF
+C6 B VPWR 0.01fF
+C7 a_63_368# VGND 0.27fF
+C8 X A 0.02fF
+C9 a_63_368# VPWR 0.29fF
+C10 B A 0.10fF
+C11 a_63_368# A 0.28fF
+C12 a_63_368# X 0.33fF
+C13 a_63_368# B 0.14fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_2/latch_diff_0/nD vss
++ Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in CLK DFlipFlop_0/Q vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ DFlipFlop_3/latch_diff_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/nD DFlipFlop_2/latch_diff_0/m1_657_280# CLK_5 Q1_shift
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D DFlipFlop_1/D nQ0 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/latch_diff_1/nD Q0 DFlipFlop_0/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_0/latch_diff_0/nD DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/D
++ DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_152_368# sky130_fd_sc_hs__and2_1_1/a_56_136#
++ DFlipFlop_3/nQ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 nCLK DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ nCLK DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vdd vss DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ CLK DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C1 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C2 vdd CLK_5 0.15fF
+C3 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C4 DFlipFlop_3/nQ CLK 0.01fF
+C5 CLK Q0 0.08fF
+C6 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
+C7 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C8 Q1 nCLK -0.01fF
+C9 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C10 Q1 DFlipFlop_3/nQ 0.10fF
+C11 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
+C12 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
+C13 Q1 Q0 9.65fF
+C14 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C15 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C16 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C17 CLK nQ0 0.19fF
+C18 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C19 sky130_fd_sc_hs__and2_1_1/a_56_136# CLK 0.06fF
+C20 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C21 Q1 nQ0 0.06fF
+C22 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C23 nCLK DFlipFlop_1/latch_diff_1/nD 0.16fF
+C24 vdd DFlipFlop_1/D 0.25fF
+C25 Q1 DFlipFlop_0/D 0.13fF
+C26 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C27 DFlipFlop_3/nQ nCLK 0.02fF
+C28 nCLK Q0 0.20fF
+C29 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C30 CLK nQ2 0.17fF
+C31 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C32 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C33 DFlipFlop_0/latch_diff_0/D Q0 0.42fF
+C34 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C35 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C36 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C37 Q1 nQ2 0.07fF
+C38 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C39 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C40 nCLK nQ0 0.09fF
+C41 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C42 nQ0 Q0 0.33fF
+C43 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C44 DFlipFlop_0/Q CLK 0.08fF
+C45 DFlipFlop_2/D CLK 0.14fF
+C46 DFlipFlop_0/D Q0 0.39fF
+C47 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C48 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C49 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C50 Q1 DFlipFlop_0/Q 0.13fF
+C51 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C52 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C53 Q1 DFlipFlop_2/D 0.10fF
+C54 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C55 nCLK nQ2 0.10fF
+C56 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C57 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C58 nQ2 Q0 0.23fF
+C59 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C60 DFlipFlop_1/latch_diff_0/nD CLK 0.08fF
+C61 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_1/D 0.03fF
+C62 DFlipFlop_2/nQ CLK 0.13fF
+C63 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
+C64 Q1_shift vdd 0.10fF
+C65 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C66 Q1 DFlipFlop_2/nQ 0.31fF
+C67 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C68 DFlipFlop_0/Q nCLK 0.11fF
+C69 nQ2 nQ0 0.03fF
+C70 DFlipFlop_2/D nCLK 0.41fF
+C71 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C72 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C73 DFlipFlop_0/Q Q0 0.21fF
+C74 DFlipFlop_2/D Q0 0.25fF
+C75 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C76 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C77 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C78 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C79 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C80 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C81 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C82 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C83 DFlipFlop_2/nQ nCLK 0.09fF
+C84 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C85 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C86 vdd CLK 0.41fF
+C87 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
+C88 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
+C89 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C90 Q1 vdd 9.49fF
+C91 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C92 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C93 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C94 DFlipFlop_0/Q nQ2 0.09fF
+C95 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C96 DFlipFlop_1/D CLK 0.21fF
+C97 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C98 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C99 Q1 DFlipFlop_1/D 0.03fF
+C100 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C101 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C102 nCLK sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.11fF
+C103 nCLK vdd 0.34fF
+C104 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C105 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C106 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C107 DFlipFlop_3/nQ vdd 0.02fF
+C108 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C109 vdd Q0 5.33fF
+C110 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C111 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C112 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C113 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C114 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q0 0.42fF
+C115 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C116 nCLK DFlipFlop_1/D 0.14fF
+C117 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
+C118 vdd nQ0 0.11fF
+C119 DFlipFlop_1/D Q0 0.07fF
+C120 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C121 sky130_fd_sc_hs__and2_1_1/a_56_136# vdd 0.04fF
+C122 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C123 vdd DFlipFlop_0/D 0.19fF
+C124 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C125 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C126 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C127 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C128 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C129 DFlipFlop_1/D nQ0 0.12fF
+C130 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C131 vdd nQ2 0.04fF
+C132 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C133 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C134 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C135 Q1 Q1_shift 0.36fF
+C136 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C137 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C138 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C139 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
+C140 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C141 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C142 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.08fF
+C143 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C144 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
+C145 DFlipFlop_2/D vdd 0.07fF
+C146 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C147 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
+C148 DFlipFlop_1/latch_diff_1/m1_657_280# nQ0 0.21fF
+C149 DFlipFlop_3/nQ Q1_shift 0.04fF
+C150 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C151 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C152 Q1 CLK -0.10fF
+C153 DFlipFlop_2/nQ vdd 0.02fF
+C154 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C155 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C156 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/nQ vss 0.52fF
+C164 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.64fF
+C170 Q1 vss 8.55fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C172 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C173 Q0 vss 0.53fF
+C174 nQ0 vss 3.42fF
+C175 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C176 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C177 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C178 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C179 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C180 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.58fF
+C181 DFlipFlop_1/D vss 3.72fF
+C182 DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C183 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C184 DFlipFlop_2/nQ vss 0.50fF
+C185 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C186 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C187 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C188 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C190 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C191 DFlipFlop_2/D vss 5.34fF
+C192 DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C193 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C194 nCLK vss 0.89fF
+C195 DFlipFlop_0/Q vss -0.94fF
+C196 nQ2 vss 2.05fF
+C197 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C198 CLK vss 0.07fF
+C199 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C200 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 vdd vss 144.09fF
+C206 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt mux2to4 vss out_b_1 vdd select_0 select_0_neg out_a_0 out_a_1 out_b_0 in_a
++ in_b
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_b vss out_b_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_3 in_b vss out_b_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 out_a_0 in_a 0.08fF
+C1 out_b_0 in_a 0.11fF
+C2 out_b_1 in_b 0.08fF
+C3 out_b_0 select_0 0.03fF
+C4 out_b_0 out_a_1 0.88fF
+C5 out_b_0 in_b 0.08fF
+C6 in_a vdd 0.02fF
+C7 select_0 vdd 0.02fF
+C8 out_a_1 vdd 0.06fF
+C9 select_0_neg out_a_0 0.05fF
+C10 select_0_neg out_b_0 -0.13fF
+C11 in_b vdd 0.02fF
+C12 select_0 in_a 0.31fF
+C13 out_a_1 in_a 0.08fF
+C14 out_a_1 select_0 0.18fF
+C15 in_b select_0 0.24fF
+C16 out_a_1 in_b 0.08fF
+C17 select_0_neg vdd 0.02fF
+C18 select_0_neg in_a 0.22fF
+C19 out_b_1 vdd 0.06fF
+C20 select_0_neg select_0 0.49fF
+C21 select_0_neg out_a_1 0.12fF
+C22 out_a_0 vdd 0.06fF
+C23 out_b_0 vdd 0.06fF
+C24 select_0_neg in_b 0.10fF
+C25 out_b_1 select_0 0.14fF
+C26 out_b_1 vss 0.99fF
+C27 in_b vss 2.00fF
+C28 out_b_0 vss 0.93fF
+C29 out_a_1 vss 0.22fF
+C30 vdd vss 9.53fF
+C31 in_a vss 2.00fF
+C32 out_a_0 vss 0.99fF
+C33 select_0_neg vss 2.56fF
+C34 select_0 vss 2.23fF
+.ends
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X a_304_74# a_443_74# a_524_368#
++ a_27_112#
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 A0 S 0.04fF
+C1 VGND VPWR 0.02fF
+C2 X VPWR 0.28fF
+C3 a_304_74# a_443_74# 0.12fF
+C4 A1 A0 0.31fF
+C5 A0 a_27_112# 0.07fF
+C6 A1 S 0.10fF
+C7 a_304_74# VPWR 0.13fF
+C8 X VGND 0.11fF
+C9 S a_27_112# 0.22fF
+C10 a_304_74# VGND 0.58fF
+C11 a_304_74# a_223_368# 0.05fF
+C12 X a_304_74# 0.29fF
+C13 a_524_368# a_27_112# 0.06fF
+C14 a_304_74# a_226_74# 0.08fF
+C15 A1 a_27_112# 0.18fF
+C16 S VPWR 0.05fF
+C17 VPB a_27_112# 0.01fF
+C18 VGND A0 0.02fF
+C19 VGND S 0.07fF
+C20 a_304_74# A0 0.23fF
+C21 a_304_74# S 0.18fF
+C22 A1 a_443_74# 0.07fF
+C23 A1 VPWR 0.01fF
+C24 VPWR a_27_112# 0.99fF
+C25 A1 VGND 0.09fF
+C26 VGND a_27_112# 0.18fF
+C27 X A1 0.02fF
+C28 a_27_112# a_223_368# 0.09fF
+C29 X a_27_112# 0.08fF
+C30 A1 a_304_74# 0.69fF
+C31 a_304_74# a_27_112# 0.58fF
+C32 VPB VPWR 0.06fF
+C33 VGND VNB 0.88fF
+C34 X VNB 0.25fF
+C35 VPWR VNB 0.89fF
+C36 A1 VNB 0.37fF
+C37 A0 VNB 0.23fF
+C38 S VNB 0.34fF
+C39 VPB VNB 0.87fF
+C40 a_304_74# VNB 0.36fF
+C41 a_27_112# VNB 0.65fF
+.ends
+
+.subckt prescaler_23 nCLK vss DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_2/latch_diff_0/nD
++ vdd DFlipFlop_2/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out CLK_23 DFlipFlop_2/latch_diff_0/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_0/latch_diff_0/nD MC DFlipFlop_2/latch_diff_0/D
++ Q2
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1_0/a_304_74# sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__mux2_1_0/a_524_368#
++ sky130_fd_sc_hs__mux2_1_0/a_27_112# sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ nCLK DFlipFlop_0/latch_diff_0/nD
++ Q1 DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_0/D
++ CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK_23 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q2 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ CLK DFlipFlop_2/latch_diff_0/nD
++ Q2_d DFlipFlop_2/latch_diff_1/nD Q2 DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/latch_diff_0/D
++ nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1_0/a_143_136# sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1_1/a_152_368#
++ sky130_fd_sc_hs__or2_1_1/a_63_368# sky130_fd_sc_hs__or2_1
+C0 CLK sky130_fd_sc_hs__or2_1_0/X 0.01fF
+C1 MC sky130_fd_sc_hs__or2_1_0/X 0.09fF
+C2 nCLK_23 DFlipFlop_0/nQ 0.05fF
+C3 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q2 0.38fF
+C4 nCLK DFlipFlop_1/D 0.16fF
+C5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C6 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_524_368# 0.04fF
+C7 CLK Q1 -0.07fF
+C8 nCLK_23 vdd 3.27fF
+C9 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.06fF
+C10 MC Q1 0.29fF
+C11 nCLK DFlipFlop_0/nQ 0.11fF
+C12 CLK_23 vdd 0.16fF
+C13 MC sky130_fd_sc_hs__mux2_1_0/a_27_112# 0.24fF
+C14 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_443_74# 0.09fF
+C15 CLK sky130_fd_sc_hs__and2_1_0/a_56_136# 0.08fF
+C16 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.31fF
+C17 nCLK_23 nCLK 0.11fF
+C18 nCLK_23 Q2 0.03fF
+C19 nCLK DFlipFlop_1/latch_diff_1/D 0.09fF
+C20 MC CLK 0.08fF
+C21 nCLK vdd -0.55fF
+C22 nCLK_23 sky130_fd_sc_hs__or2_1_1/X 0.26fF
+C23 vdd Q2 1.63fF
+C24 sky130_fd_sc_hs__or2_1_1/X vdd 0.03fF
+C25 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C26 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_443_74# 0.03fF
+C27 nCLK Q2 0.29fF
+C28 nCLK_23 DFlipFlop_0/latch_diff_1/D 0.05fF
+C29 sky130_fd_sc_hs__or2_1_1/a_63_368# Q2 0.09fF
+C30 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.31fF
+C31 sky130_fd_sc_hs__or2_1_1/X Q2 0.24fF
+C32 DFlipFlop_1/D sky130_fd_sc_hs__or2_1_0/X 0.35fF
+C33 nCLK DFlipFlop_2/latch_diff_0/nD 0.09fF
+C34 nCLK DFlipFlop_2/latch_diff_1/D 0.16fF
+C35 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.29fF
+C36 nCLK sky130_fd_sc_hs__or2_1_0/a_63_368# 0.05fF
+C37 DFlipFlop_2/latch_diff_1/D Q2 0.13fF
+C38 nCLK_23 DFlipFlop_0/latch_diff_0/nD 0.12fF
+C39 CLK DFlipFlop_1/latch_diff_1/nD 0.11fF
+C40 nCLK_23 DFlipFlop_0/latch_diff_1/nD 0.02fF
+C41 nCLK DFlipFlop_2/nQ 0.02fF
+C42 nCLK_23 sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C43 DFlipFlop_2/nQ Q2 0.13fF
+C44 nCLK DFlipFlop_2/latch_diff_1/nD 0.12fF
+C45 vdd sky130_fd_sc_hs__or2_1_0/X 0.03fF
+C46 DFlipFlop_2/latch_diff_0/D Q2 0.30fF
+C47 DFlipFlop_2/latch_diff_1/nD Q2 0.17fF
+C48 nCLK_23 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.49fF
+C49 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.10fF
+C50 nCLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.31fF
+C51 CLK DFlipFlop_1/D 0.40fF
+C52 DFlipFlop_0/nQ Q1 -0.02fF
+C53 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C54 nCLK sky130_fd_sc_hs__or2_1_0/a_152_368# 0.01fF
+C55 nCLK sky130_fd_sc_hs__or2_1_0/X 0.06fF
+C56 DFlipFlop_1/latch_diff_0/D nCLK 0.02fF
+C57 Q2_d vdd 0.02fF
+C58 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.04fF
+C59 nCLK_23 Q1 0.02fF
+C60 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_27_112# 0.07fF
+C61 CLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.05fF
+C62 vdd Q1 0.07fF
+C63 CLK DFlipFlop_0/nQ 0.15fF
+C64 nCLK_23 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C65 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C66 Q2_d Q2 0.66fF
+C67 DFlipFlop_0/latch_diff_1/m1_657_280# Q1 0.06fF
+C68 nCLK_23 CLK 0.22fF
+C69 sky130_fd_sc_hs__or2_1_1/X Q2_d 0.03fF
+C70 MC nCLK_23 4.46fF
+C71 nCLK Q1 -0.02fF
+C72 CLK DFlipFlop_1/latch_diff_1/D 0.18fF
+C73 CLK vdd 0.34fF
+C74 MC vdd 0.88fF
+C75 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.08fF
+C76 Q2_d DFlipFlop_2/latch_diff_1/D 0.03fF
+C77 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.09fF
+C78 MC nCLK 0.01fF
+C79 CLK Q2 0.29fF
+C80 MC Q2 0.18fF
+C81 MC sky130_fd_sc_hs__or2_1_1/X 0.02fF
+C82 DFlipFlop_2/latch_diff_1/m1_657_280# Q2_d 0.03fF
+C83 CLK DFlipFlop_2/latch_diff_1/D 0.09fF
+C84 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.02fF
+C85 CLK DFlipFlop_1/latch_diff_0/nD 0.09fF
+C86 CLK DFlipFlop_0/latch_diff_1/D 0.04fF
+C87 DFlipFlop_2/latch_diff_1/m1_657_280# CLK 0.33fF
+C88 DFlipFlop_0/latch_diff_1/nD Q1 0.03fF
+C89 CLK DFlipFlop_2/nQ 0.02fF
+C90 nCLK DFlipFlop_1/latch_diff_1/nD 0.18fF
+C91 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1 0.01fF
+C92 sky130_fd_sc_hs__or2_1_0/X Q1 0.06fF
+C93 CLK DFlipFlop_2/latch_diff_0/D 0.13fF
+C94 CLK DFlipFlop_2/latch_diff_1/nD 0.19fF
+C95 nCLK_23 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C96 nCLK_23 DFlipFlop_1/D 0.02fF
+C97 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C98 sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C99 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C100 DFlipFlop_1/D vdd 0.07fF
+C101 sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C102 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C103 sky130_fd_sc_hs__or2_1_0/X vss 0.92fF
+C104 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.39fF
+C105 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C106 Q2_d vss -0.22fF
+C107 DFlipFlop_2/nQ vss 0.48fF
+C108 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C109 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C110 DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C111 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C112 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C113 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.63fF
+C114 Q2 vss 1.35fF
+C115 DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C116 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.72fF
+C117 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C118 DFlipFlop_1/latch_diff_1/D vss -1.72fF
+C119 DFlipFlop_1/latch_diff_1/nD vss 0.58fF
+C120 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C121 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C122 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C123 DFlipFlop_1/D vss 2.98fF
+C124 DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C125 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C126 nCLK vss -1.56fF
+C127 Q1 vss 0.50fF
+C128 DFlipFlop_0/nQ vss 0.48fF
+C129 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C130 CLK vss -0.69fF
+C131 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C132 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C133 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C134 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C135 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C136 nCLK_23 vss -0.65fF
+C137 vdd vss 113.67fF
+C138 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C139 CLK_23 vss -0.57fF
+C140 sky130_fd_sc_hs__or2_1_1/X vss -0.35fF
+C141 MC vss 2.09fF
+C142 sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.41fF
+C143 sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.69fF
+.ends
+
+.subckt freq_div clk_0 vss n_clk_0 vdd s_0 prescaler_23_0/Q2 s_1_n s_1 prescaler_23_0/nCLK_23
++ prescaler_23_0/MC clk_d prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n
++ clk_pre div_by_5_0/DFlipFlop_2/latch_diff_0/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out div_by_5_0/Q1 div_by_5_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD clk_2 in_a in_b clk_5 prescaler_23_0/DFlipFlop_2/latch_diff_0/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD div_by_5_0/DFlipFlop_2/latch_diff_1/D
+Xdiv_by_2_0 vdd vss div_by_2_0/nout_div clk_2 div_by_2_0/nCLK_2 div_by_2_0/o1 div_by_2_0/o2
++ clk_out_mux21 div_by_2_0/out_div div_by_2
+Xmux2to1_0 vss s_0_n clk_pre clk_5 s_0 vdd clk_out_mux21 mux2to1
+Xinverter_min_x4_0 inverter_min_x4_0/in vss clk_d vdd inverter_min_x4
+Xmux2to1_1 vss s_1_n clk_d clk_2 s_1 vdd out mux2to1
+Xinverter_min_x2_0 clk_out_mux21 inverter_min_x4_0/in vss vdd inverter_min_x2
+Xinverter_min_x2_1 s_1 s_1_n vss vdd inverter_min_x2
+Xinverter_min_x2_2 s_0 s_0_n vss vdd inverter_min_x2
+Xdiv_by_5_0 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ vss div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in clk_1
++ div_by_5_0/DFlipFlop_0/Q vdd div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# clk_5 div_by_5_0/Q1_shift div_by_5_0/nQ2
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_by_5_0/DFlipFlop_1/D div_by_5_0/nQ0 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/Q0 div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xmux2to4_0 vss n_clk_1 vdd s_0 s_0_n clk_0 clk_1 n_clk_0 in_a in_b mux2to4
+Xprescaler_23_0 n_clk_0 vss prescaler_23_0/DFlipFlop_0/latch_diff_1/nD prescaler_23_0/nCLK_23
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vdd prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ clk_pre prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# prescaler_23_0/DFlipFlop_0/latch_diff_0/D
++ clk_0 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280#
++ prescaler_23_0/DFlipFlop_0/latch_diff_1/D prescaler_23_0/DFlipFlop_0/latch_diff_0/nD
++ prescaler_23_0/MC prescaler_23_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/Q2 prescaler_23
+C0 clk_1 s_0 1.36fF
+C1 n_clk_1 vdd 0.13fF
+C2 clk_5 vdd 0.04fF
+C3 div_by_5_0/Q0 s_0 0.02fF
+C4 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.02fF
+C5 clk_1 n_clk_0 -0.03fF
+C6 s_0_n div_by_5_0/DFlipFlop_1/D 0.19fF
+C7 n_clk_1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C8 div_by_5_0/DFlipFlop_2/D s_0 0.03fF
+C9 div_by_5_0/Q1_shift div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# -0.02fF
+C10 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out s_0_n -0.29fF
+C11 s_0_n div_by_5_0/nQ2 0.05fF
+C12 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.08fF
+C13 s_0 div_by_5_0/DFlipFlop_2/nQ 0.05fF
+C14 s_0 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.36fF
+C15 s_1_n clk_2 0.59fF
+C16 s_0_n div_by_5_0/nQ0 0.05fF
+C17 div_by_5_0/DFlipFlop_1/latch_diff_1/D s_0_n 0.04fF
+C18 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.04fF
+C19 n_clk_1 in_b 0.05fF
+C20 s_0 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.05fF
+C21 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0_n 0.04fF
+C22 clk_pre clk_out_mux21 1.19fF
+C23 s_0_n div_by_5_0/DFlipFlop_0/Q 0.24fF
+C24 vdd clk_d 0.23fF
+C25 s_0_n div_by_5_0/DFlipFlop_0/D 0.05fF
+C26 s_0 div_by_5_0/Q1 0.04fF
+C27 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_1 0.05fF
+C28 s_0_n clk_out_mux21 0.45fF
+C29 div_by_5_0/DFlipFlop_3/latch_diff_0/D s_0 0.10fF
+C30 s_0 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.12fF
+C31 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_0 0.16fF
+C32 div_by_5_0/Q1_shift s_0_n 0.04fF
+C33 s_0 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.12fF
+C34 div_by_5_0/Q0 n_clk_1 0.01fF
+C35 div_by_5_0/DFlipFlop_1/latch_diff_1/nD s_0 0.02fF
+C36 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.11fF
+C37 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0 0.02fF
+C38 clk_2 vdd 0.02fF
+C39 clk_0 vdd 0.63fF
+C40 clk_pre vdd 0.17fF
+C41 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.11fF
+C42 clk_out_mux21 vdd 0.14fF
+C43 s_1_n out 0.33fF
+C44 s_0_n vdd 2.53fF
+C45 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out s_0 -0.13fF
+C46 s_0_n div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.31fF
+C47 div_by_5_0/DFlipFlop_3/nQ s_0 0.02fF
+C48 clk_0 prescaler_23_0/nCLK_23 0.16fF
+C49 clk_pre prescaler_23_0/nCLK_23 0.03fF
+C50 inverter_min_x4_0/in clk_d 0.11fF
+C51 s_0 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.02fF
+C52 clk_2 out 0.05fF
+C53 s_0_n div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.05fF
+C54 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/D 0.13fF
+C55 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.20fF
+C56 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD clk_0 0.09fF
+C57 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD 0.09fF
+C58 prescaler_23_0/DFlipFlop_0/latch_diff_1/D clk_0 0.13fF
+C59 n_clk_1 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.06fF
+C60 n_clk_1 div_by_5_0/Q1 0.15fF
+C61 s_0 div_by_5_0/DFlipFlop_1/D 0.03fF
+C62 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.11fF
+C63 s_0_n in_b 0.48fF
+C64 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out s_0 -0.19fF
+C65 clk_1 div_by_5_0/DFlipFlop_0/D 0.14fF
+C66 s_0 div_by_5_0/nQ2 0.05fF
+C67 clk_1 s_0_n 4.82fF
+C68 div_by_5_0/nQ0 s_0 0.05fF
+C69 div_by_5_0/Q0 s_0_n 0.24fF
+C70 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.24fF
+C71 clk_1 in_a 0.05fF
+C72 s_1 clk_d 0.22fF
+C73 s_0_n div_by_5_0/DFlipFlop_2/D 0.05fF
+C74 inverter_min_x4_0/in vdd 0.09fF
+C75 div_by_5_0/DFlipFlop_1/latch_diff_1/D s_0 0.05fF
+C76 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.05fF
+C77 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0 0.05fF
+C78 s_1 s_1_n 0.39fF
+C79 s_0 div_by_5_0/DFlipFlop_0/Q 0.02fF
+C80 clk_1 vdd 0.16fF
+C81 s_0 div_by_5_0/DFlipFlop_0/D 0.03fF
+C82 clk_pre s_0 0.21fF
+C83 clk_out_mux21 s_0 0.68fF
+C84 s_0_n div_by_5_0/DFlipFlop_2/nQ 0.04fF
+C85 s_0_n div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.37fF
+C86 s_0_n s_0 7.76fF
+C87 div_by_5_0/Q1_shift s_0 0.05fF
+C88 div_by_5_0/Q0 vdd 0.05fF
+C89 n_clk_0 s_0_n 0.31fF
+C90 n_clk_1 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C91 s_0 in_a 0.30fF
+C92 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.04fF
+C93 div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/D -0.02fF
+C94 s_0_n div_by_5_0/Q1 0.21fF
+C95 s_0 vdd 3.67fF
+C96 div_by_5_0/DFlipFlop_3/latch_diff_0/D s_0_n 0.17fF
+C97 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.20fF
+C98 s_0 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.30fF
+C99 s_0_n div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.20fF
+C100 div_by_5_0/DFlipFlop_1/latch_diff_1/nD s_0_n 0.24fF
+C101 n_clk_0 vdd 0.25fF
+C102 n_clk_0 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C103 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0_n 0.24fF
+C104 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.08fF
+C105 s_0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.12fF
+C106 div_by_5_0/Q1 vdd -0.02fF
+C107 n_clk_1 div_by_5_0/DFlipFlop_0/D 0.21fF
+C108 n_clk_0 prescaler_23_0/nCLK_23 0.16fF
+C109 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.08fF
+C110 clk_5 clk_out_mux21 0.05fF
+C111 div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in -0.06fF
+C112 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out s_0_n -0.01fF
+C113 clk_5 s_0_n 0.56fF
+C114 s_1 out 0.39fF
+C115 div_by_5_0/DFlipFlop_3/nQ s_0_n 0.24fF
+C116 clk_5 div_by_5_0/Q1_shift 0.04fF
+C117 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C118 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD 0.13fF
+C119 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/D 0.09fF
+C120 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C121 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C122 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C123 prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C124 prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C125 prescaler_23_0/Q2_d vss -0.69fF
+C126 prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C127 prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C128 prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C129 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C130 prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C131 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C132 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C133 prescaler_23_0/Q2 vss 0.55fF
+C134 prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C135 prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C136 prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C137 prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C138 prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C139 prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C140 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C141 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C142 prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C143 prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C144 prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C145 n_clk_0 vss -5.35fF
+C146 prescaler_23_0/Q1 vss 0.07fF
+C147 prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C148 prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C149 clk_0 vss 0.66fF
+C150 prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C151 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C152 prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C153 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C155 prescaler_23_0/nCLK_23 vss -1.02fF
+C156 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C157 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C158 prescaler_23_0/MC vss 1.07fF
+C159 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C160 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C161 in_b vss 2.02fF
+C162 in_a vss 2.01fF
+C163 s_0_n vss -2.51fF
+C164 s_0 vss 5.84fF
+C165 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C166 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C167 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C168 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C169 div_by_5_0/Q1_shift vss -0.36fF
+C170 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C171 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C172 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C174 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C177 div_by_5_0/Q1 vss 4.35fF
+C178 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C179 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C180 div_by_5_0/Q0 vss 0.29fF
+C181 div_by_5_0/nQ0 vss 0.99fF
+C182 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C183 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C184 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C185 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C186 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C187 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C188 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C189 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C190 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C191 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C192 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C193 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C194 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C195 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C196 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C197 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C198 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C199 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C200 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C201 n_clk_1 vss -0.55fF
+C202 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C203 div_by_5_0/nQ2 vss 1.38fF
+C204 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C205 clk_1 vss -1.34fF
+C206 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C207 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C208 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C209 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C210 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C211 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C212 vdd vss 344.01fF
+C213 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C214 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C215 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C216 out vss 0.93fF
+C217 clk_d vss 0.78fF
+C218 s_1_n vss 1.22fF
+C219 s_1 vss 2.97fF
+C220 inverter_min_x4_0/in vss 2.77fF
+C221 clk_out_mux21 vss 5.29fF
+C222 clk_pre vss 1.30fF
+C223 clk_2 vss 3.46fF
+C224 div_by_2_0/o1 vss 2.20fF
+C225 div_by_2_0/nCLK_2 vss 1.04fF
+C226 div_by_2_0/o2 vss 2.08fF
+C227 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C228 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C229 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C230 div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C231 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C232 div_by_2_0/out_div vss -0.80fF
+C233 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C234 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C235 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C236 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C237 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C238 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C239 div_by_2_0/nout_div vss 2.62fF
+C240 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n129_n600# a_n257_n777# 0.29fF
+C1 a_n221_n600# a_n257_n777# 0.25fF
+C2 a_n129_n600# a_n221_n600# 7.87fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n129_n300# a_n221_n300# 4.05fF
+C1 a_n257_n404# a_n221_n300# 0.21fF
+C2 a_n257_n404# a_n129_n300# 0.30fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out vdd in vss
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 a_3996_n100# vdd 3.68fF
+C1 in vdd 0.02fF
+C2 vdd a_678_n100# 0.08fF
+C3 a_3996_n100# a_678_n100# 6.52fF
+C4 in a_678_n100# 0.81fF
+C5 vdd out 47.17fF
+C6 a_3996_n100# out 55.19fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n238# a_15_n150# 0.02fF
+C1 a_n33_n238# a_n73_n150# 0.02fF
+C2 a_n73_n150# a_15_n150# 0.51fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n369# a_n73_n150# 0.20fF
+C1 a_n33_181# a_15_n150# 0.01fF
+C2 w_n211_n369# a_n33_181# 0.05fF
+C3 w_n211_n369# a_15_n150# 0.20fF
+C4 a_n33_181# a_n73_n150# 0.01fF
+C5 a_15_n150# a_n73_n150# 0.51fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n465_172# a_n417_n150# 0.10fF
+C1 a_159_n150# a_n465_172# 0.10fF
+C2 a_n465_172# a_63_n150# 0.10fF
+C3 a_n509_n150# a_n321_n150# 0.16fF
+C4 a_n129_n150# a_n321_n150# 0.16fF
+C5 a_n33_n150# a_351_n150# 0.07fF
+C6 a_n465_172# a_447_n150# 0.01fF
+C7 a_255_n150# a_n33_n150# 0.10fF
+C8 a_n225_n150# a_n33_n150# 0.16fF
+C9 a_255_n150# a_351_n150# 0.43fF
+C10 a_n465_172# a_n509_n150# 0.01fF
+C11 a_n33_n150# a_n417_n150# 0.07fF
+C12 a_159_n150# a_n33_n150# 0.16fF
+C13 a_n465_172# a_n129_n150# 0.10fF
+C14 a_159_n150# a_351_n150# 0.16fF
+C15 a_n225_n150# a_n417_n150# 0.16fF
+C16 a_159_n150# a_255_n150# 0.43fF
+C17 a_159_n150# a_n225_n150# 0.07fF
+C18 a_63_n150# a_n33_n150# 0.43fF
+C19 a_63_n150# a_351_n150# 0.10fF
+C20 a_255_n150# a_63_n150# 0.16fF
+C21 a_63_n150# a_n225_n150# 0.10fF
+C22 a_447_n150# a_351_n150# 0.43fF
+C23 a_255_n150# a_447_n150# 0.16fF
+C24 a_n465_172# a_n321_n150# 0.10fF
+C25 a_159_n150# a_63_n150# 0.43fF
+C26 a_n129_n150# a_n33_n150# 0.43fF
+C27 a_159_n150# a_447_n150# 0.10fF
+C28 a_n225_n150# a_n509_n150# 0.10fF
+C29 a_255_n150# a_n129_n150# 0.07fF
+C30 a_n129_n150# a_n225_n150# 0.43fF
+C31 a_63_n150# a_447_n150# 0.07fF
+C32 a_n509_n150# a_n417_n150# 0.43fF
+C33 a_n129_n150# a_n417_n150# 0.10fF
+C34 a_159_n150# a_n129_n150# 0.10fF
+C35 a_n33_n150# a_n321_n150# 0.10fF
+C36 a_n225_n150# a_n321_n150# 0.43fF
+C37 a_n129_n150# a_63_n150# 0.16fF
+C38 a_n321_n150# a_n417_n150# 0.43fF
+C39 a_n465_172# a_n33_n150# 0.10fF
+C40 a_n465_172# a_351_n150# 0.10fF
+C41 a_n465_172# a_255_n150# 0.10fF
+C42 a_n465_172# a_n225_n150# 0.10fF
+C43 a_63_n150# a_n321_n150# 0.07fF
+C44 a_n129_n150# a_n509_n150# 0.07fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n465_n247# a_63_n150# 0.08fF
+C1 a_n321_n150# a_n417_n150# 0.43fF
+C2 a_255_n150# a_n33_n150# 0.10fF
+C3 a_351_n150# a_159_n150# 0.16fF
+C4 w_n647_n369# a_n129_n150# 0.02fF
+C5 w_n647_n369# a_63_n150# 0.02fF
+C6 a_159_n150# a_447_n150# 0.10fF
+C7 a_n129_n150# a_n33_n150# 0.43fF
+C8 a_n321_n150# a_n225_n150# 0.43fF
+C9 a_351_n150# a_447_n150# 0.43fF
+C10 a_n417_n150# a_n129_n150# 0.10fF
+C11 a_n33_n150# a_63_n150# 0.43fF
+C12 a_255_n150# a_159_n150# 0.43fF
+C13 a_255_n150# a_351_n150# 0.43fF
+C14 a_n225_n150# a_n129_n150# 0.43fF
+C15 a_159_n150# a_n129_n150# 0.10fF
+C16 w_n647_n369# a_n509_n150# 0.14fF
+C17 a_n225_n150# a_63_n150# 0.10fF
+C18 a_255_n150# a_447_n150# 0.16fF
+C19 a_159_n150# a_63_n150# 0.43fF
+C20 w_n647_n369# a_n465_n247# 0.47fF
+C21 a_351_n150# a_63_n150# 0.10fF
+C22 a_n465_n247# a_n33_n150# 0.08fF
+C23 a_n417_n150# a_n509_n150# 0.43fF
+C24 a_n465_n247# a_n417_n150# 0.08fF
+C25 a_63_n150# a_447_n150# 0.07fF
+C26 a_n321_n150# a_n129_n150# 0.16fF
+C27 a_n321_n150# a_63_n150# 0.07fF
+C28 a_255_n150# a_n129_n150# 0.07fF
+C29 w_n647_n369# a_n33_n150# 0.02fF
+C30 a_n225_n150# a_n509_n150# 0.10fF
+C31 a_255_n150# a_63_n150# 0.16fF
+C32 w_n647_n369# a_n417_n150# 0.07fF
+C33 a_n465_n247# a_n225_n150# 0.08fF
+C34 a_n465_n247# a_159_n150# 0.08fF
+C35 a_n417_n150# a_n33_n150# 0.07fF
+C36 a_351_n150# a_n465_n247# 0.08fF
+C37 a_n129_n150# a_63_n150# 0.16fF
+C38 w_n647_n369# a_n225_n150# 0.04fF
+C39 w_n647_n369# a_159_n150# 0.04fF
+C40 a_n321_n150# a_n509_n150# 0.16fF
+C41 a_351_n150# w_n647_n369# 0.07fF
+C42 a_n225_n150# a_n33_n150# 0.16fF
+C43 a_n321_n150# a_n465_n247# 0.08fF
+C44 a_159_n150# a_n33_n150# 0.16fF
+C45 a_n225_n150# a_n417_n150# 0.16fF
+C46 a_255_n150# a_n465_n247# 0.08fF
+C47 a_351_n150# a_n33_n150# 0.07fF
+C48 w_n647_n369# a_447_n150# 0.14fF
+C49 a_n321_n150# w_n647_n369# 0.05fF
+C50 a_n129_n150# a_n509_n150# 0.07fF
+C51 a_n465_n247# a_n129_n150# 0.08fF
+C52 a_255_n150# w_n647_n369# 0.05fF
+C53 a_159_n150# a_n225_n150# 0.07fF
+C54 a_n321_n150# a_n33_n150# 0.10fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n73_n11# 0.15fF
+C1 a_n73_n11# a_n33_n99# 0.02fF
+C2 a_15_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# a_20_n114# 0.42fF
+C1 a_20_n114# w_n216_n334# 0.20fF
+C2 a_n78_n114# w_n216_n334# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vdd 0.01fF
+C1 in out 0.11fF
+C2 vbulkp vdd 0.04fF
+C3 in vss 0.01fF
+C4 out vbulkp 0.08fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 vss out vdd inverter_csvco_0/vss
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 inverter_csvco_0/vss in 0.01fF
+C1 in out 0.06fF
+C2 inverter_csvco_0/vss vctrl 0.87fF
+C3 D0 inverter_csvco_0/vss 0.02fF
+C4 in inverter_csvco_0/vdd 0.01fF
+C5 D0 out 0.09fF
+C6 inverter_csvco_0/vss out 0.03fF
+C7 inverter_csvco_0/vdd vbp 0.75fF
+C8 cap_vco_0/t out 0.70fF
+C9 inverter_csvco_0/vdd out 0.02fF
+C10 vdd vbp 1.21fF
+C11 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C12 vdd cap_vco_0/t 0.04fF
+C13 vdd inverter_csvco_0/vdd 1.89fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vss vdd csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 vss
++ csvco_branch_1/in vdd csvco_branch_0/inverter_csvco_0/vss csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 vss out_vco vdd csvco_branch_2/inverter_csvco_0/vss csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 vss csvco_branch_2/in vdd csvco_branch_1/inverter_csvco_0/vss csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C1 vdd csvco_branch_2/vbp 1.49fF
+C2 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C3 out_vco csvco_branch_1/in 0.76fF
+C4 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C5 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
+C6 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C7 vctrl csvco_branch_2/vbp 0.06fF
+C8 out_vco csvco_branch_2/in 0.58fF
+C9 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
+C10 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C11 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C12 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C13 vctrl D0 4.41fF
+C14 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 out_pad out_div 0.15fF
+C1 vdd out_div 0.17fF
+C2 o1 vdd 0.09fF
+C3 out_pad vdd 0.10fF
+C4 o1 out_div 0.11fF
+C5 vdd vss 14.54fF
+C6 in_vco vss 0.83fF
+C7 out_pad vss 0.70fF
+C8 out_div vss 3.00fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n33_n125# a_n225_n125# 0.13fF
+C1 a_n225_n125# a_n129_n125# 0.36fF
+C2 a_n317_n125# a_63_n125# 0.06fF
+C3 a_63_n125# a_159_n125# 0.36fF
+C4 a_225_n151# a_129_n151# 0.02fF
+C5 a_33_n151# a_129_n151# 0.02fF
+C6 a_n33_n125# a_255_n125# 0.08fF
+C7 a_255_n125# a_n129_n125# 0.06fF
+C8 a_n317_n125# a_n225_n125# 0.36fF
+C9 a_63_n125# a_n225_n125# 0.08fF
+C10 a_n33_n125# a_n129_n125# 0.36fF
+C11 a_n225_n125# a_159_n125# 0.06fF
+C12 a_n63_n151# a_n159_n151# 0.02fF
+C13 a_63_n125# a_255_n125# 0.13fF
+C14 a_255_n125# a_159_n125# 0.36fF
+C15 a_n317_n125# a_n33_n125# 0.08fF
+C16 a_63_n125# a_n33_n125# 0.36fF
+C17 a_n317_n125# a_n129_n125# 0.13fF
+C18 a_n33_n125# a_159_n125# 0.13fF
+C19 a_63_n125# a_n129_n125# 0.13fF
+C20 a_n129_n125# a_159_n125# 0.08fF
+C21 a_n63_n151# a_33_n151# 0.02fF
+C22 a_n255_n151# a_n159_n151# 0.02fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n455_n344# a_n33_n125# 0.05fF
+C1 a_n129_n125# a_n317_n125# 0.13fF
+C2 w_n455_n344# a_n317_n125# 0.11fF
+C3 a_33_n154# a_129_n154# 0.02fF
+C4 a_n225_n125# a_63_n125# 0.08fF
+C5 a_n159_n154# a_n63_n154# 0.02fF
+C6 a_225_n154# a_129_n154# 0.02fF
+C7 a_255_n125# a_63_n125# 0.13fF
+C8 a_n129_n125# a_63_n125# 0.13fF
+C9 a_63_n125# w_n455_n344# 0.04fF
+C10 a_159_n125# a_n33_n125# 0.13fF
+C11 a_n225_n125# a_n129_n125# 0.36fF
+C12 a_n225_n125# w_n455_n344# 0.06fF
+C13 a_255_n125# a_n129_n125# 0.06fF
+C14 a_255_n125# w_n455_n344# 0.11fF
+C15 a_n129_n125# w_n455_n344# 0.04fF
+C16 a_n33_n125# a_n317_n125# 0.08fF
+C17 a_159_n125# a_63_n125# 0.36fF
+C18 a_63_n125# a_n33_n125# 0.36fF
+C19 a_33_n154# a_n63_n154# 0.02fF
+C20 a_159_n125# a_n225_n125# 0.06fF
+C21 a_63_n125# a_n317_n125# 0.06fF
+C22 a_n159_n154# a_n255_n154# 0.02fF
+C23 a_255_n125# a_159_n125# 0.36fF
+C24 a_159_n125# a_n129_n125# 0.08fF
+C25 a_159_n125# w_n455_n344# 0.06fF
+C26 a_n225_n125# a_n33_n125# 0.13fF
+C27 a_255_n125# a_n33_n125# 0.08fF
+C28 a_n129_n125# a_n33_n125# 0.36fF
+C29 a_n225_n125# a_n317_n125# 0.36fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 in vdd 0.04fF
+C1 in out 0.85fF
+C2 vdd out 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss vdd inverter_cp_x1_0/out inverter_cp_x1_2/in Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown vss inverter_cp_x1_0/out vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd nUp 0.14fF
+C1 Down nDown 0.23fF
+C2 Down inverter_cp_x1_0/out 0.12fF
+C3 Up inverter_cp_x1_2/in 0.12fF
+C4 inverter_cp_x1_2/in vdd 0.42fF
+C5 QA vdd 0.02fF
+C6 inverter_cp_x1_0/out nDown 0.11fF
+C7 QB vdd 0.02fF
+C8 vdd nDown 0.80fF
+C9 inverter_cp_x1_0/out vdd 0.18fF
+C10 Up vdd 0.60fF
+C11 Up nUp 0.20fF
+C12 inverter_cp_x1_2/in vss 2.01fF
+C13 QA vss 1.09fF
+C14 inverter_cp_x1_0/out vss 1.72fF
+C15 QB vss 1.09fF
+C16 vdd vss 28.20fF
+C17 nUp vss 1.32fF
+C18 Up vss 2.53fF
+C19 Down vss 1.17fF
+C20 nDown vss 2.77fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 w_n359_n309# a_63_n90# 0.06fF
+C1 a_n33_n90# a_n221_n90# 0.09fF
+C2 a_n159_n207# a_n63_n116# 0.12fF
+C3 a_159_n90# a_63_n90# 0.26fF
+C4 w_n359_n309# a_159_n90# 0.09fF
+C5 a_n221_n90# a_63_n90# 0.06fF
+C6 a_n129_n90# a_n33_n90# 0.26fF
+C7 w_n359_n309# a_n221_n90# 0.09fF
+C8 a_159_n90# a_n221_n90# 0.04fF
+C9 a_n129_n90# a_63_n90# 0.09fF
+C10 a_n129_n90# w_n359_n309# 0.06fF
+C11 a_n129_n90# a_159_n90# 0.06fF
+C12 a_n129_n90# a_n221_n90# 0.26fF
+C13 a_n33_n90# a_63_n90# 0.26fF
+C14 w_n359_n309# a_n33_n90# 0.05fF
+C15 a_n33_n90# a_159_n90# 0.09fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_71# a_33_n71# 0.04fF
+C1 a_n125_n45# a_63_n45# 0.05fF
+C2 a_n33_n45# a_63_n45# 0.13fF
+C3 a_n33_n45# a_n125_n45# 0.13fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 out vdd 0.11fF
+C1 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
+C2 A vdd 0.09fF
+C3 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
+C4 out A 0.06fF
+C5 out B 0.40fF
+C6 A B 0.24fF
+C7 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A Reset nor_pfd_2/B
+Xnor_pfd_0 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss CLK Q nor_pfd
+Xnor_pfd_1 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_3/A Reset nor_pfd
+C0 nor_pfd_2/B vdd 0.02fF
+C1 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C2 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C3 Reset nor_pfd_2/B 0.43fF
+C4 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C5 vdd nor_pfd_3/A 0.09fF
+C6 nor_pfd_2/B Q 2.22fF
+C7 Reset nor_pfd_3/A 0.12fF
+C8 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C9 nor_pfd_3/A Q 0.98fF
+C10 vdd nor_pfd_2/A -0.01fF
+C11 nor_pfd_2/B nor_pfd_3/A 0.58fF
+C12 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C13 nor_pfd_2/A Q 1.38fF
+C14 CLK Q 0.04fF
+C15 vdd Q 0.08fF
+C16 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C17 Reset Q 0.14fF
+C18 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C19 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_n45# a_159_n45# 0.03fF
+C1 a_n129_n45# a_63_n45# 0.05fF
+C2 a_n221_n45# a_159_n45# 0.02fF
+C3 a_n221_n45# a_63_n45# 0.03fF
+C4 a_n129_n45# a_n221_n45# 0.13fF
+C5 a_n63_n71# a_n159_n173# 0.10fF
+C6 a_159_n45# a_n33_n45# 0.05fF
+C7 a_63_n45# a_n33_n45# 0.13fF
+C8 a_n129_n45# a_n33_n45# 0.13fF
+C9 a_n221_n45# a_n33_n45# 0.05fF
+C10 a_63_n45# a_159_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n33_n90# a_63_n90# 0.26fF
+C1 a_n125_n90# a_n33_n90# 0.26fF
+C2 a_n125_n90# a_63_n90# 0.09fF
+C3 a_33_n187# a_n99_n187# 0.04fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_15_n45# a_n73_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n73_n90# w_n211_n309# 0.04fF
+C1 a_15_n90# w_n211_n309# 0.09fF
+C2 a_n73_n90# a_15_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# out vss vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 a_656_410# B 0.30fF
+C1 vdd out 0.10fF
+C2 vdd A 0.05fF
+C3 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C4 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C5 a_656_410# out 0.20fF
+C6 A B 0.33fF
+C7 a_656_410# A 0.04fF
+C8 vdd a_656_410# 0.20fF
+C9 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Reset Down Up A B
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A Reset dff_pfd_0/nor_pfd_2/B
++ dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A Reset dff_pfd_1/nor_pfd_2/B
++ dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# Reset vss vdd Up Down and_pfd
+C0 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C1 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C2 dff_pfd_1/nor_pfd_2/B vdd 0.04fF
+C3 vdd Reset 0.02fF
+C4 Down Up 0.06fF
+C5 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C6 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C7 Down vdd 0.08fF
+C8 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C9 vdd Up 1.62fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v3 pfd_reset in_ref QA QB Down nDown Up nUp biasp pswitch nswitch
++ vco_vctrl vco_out out_first_buffer out_to_div iref_cp vdd n_clk_1 clk_1 clk_5 clk_pre
++ clk_out_mux21 clk_d clk_2_f out_div s_1 s_1_n MC lf_vc vco_D0
+Xcharge_pump_0 nswitch vss vdd nUp Down charge_pump_0/w_2544_775# vco_vctrl pswitch
++ iref_cp nDown biasp Up vss charge_pump
+Xloop_filter_v2_0 lf_vc lf_D0 vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vdd vss n_out_div_2 out_by_2 n_out_by_2 out_buffer_div_2 n_out_buffer_div_2
++ out_to_div out_div_2 div_by_2
+Xfreq_div_0 clk_0 vss n_clk_0 vdd s_0 freq_div_0/prescaler_23_0/Q2 s_1_n s_1 freq_div_0/prescaler_23_0/nCLK_23
++ MC clk_d freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n clk_pre
++ freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out_div freq_div_0/div_by_5_0/Q1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ clk_2_f out_by_2 n_out_by_2 clk_5 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D
++ freq_div
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad vdd out_to_buffer vss buffer_salida
+Xring_osc_0 vco_vctrl vss vdd ring_osc_0/csvco_branch_0/inverter_csvco_0/vss ring_osc_0/csvco_branch_2/vbp
++ vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div PFD
+C0 vco_vctrl n_clk_1 0.23fF
+C1 pswitch nUp 0.93fF
+C2 Up nUp 2.72fF
+C3 vdd nUp 0.05fF
+C4 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D 0.53fF
+C5 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C6 clk_0 vco_vctrl -0.26fF
+C7 nDown Down 2.55fF
+C8 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C9 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# 0.34fF
+C10 Up biasp 0.26fF
+C11 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vco_vctrl 0.15fF
+C12 out_by_2 n_out_by_2 0.27fF
+C13 nswitch nDown 0.76fF
+C14 nDown nUp -0.09fF
+C15 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C16 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C17 vco_vctrl freq_div_0/prescaler_23_0/nCLK_23 0.06fF
+C18 nswitch Down 0.54fF
+C19 buffer_salida_0/a_678_n100# out_to_buffer 0.21fF
+C20 charge_pump_0/w_2544_775# nDown 0.05fF
+C21 s_0_n n_out_by_2 0.14fF
+C22 clk_0 vdd 0.13fF
+C23 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.65fF
+C24 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C25 vdd vco_D0 0.03fF
+C26 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD 1.23fF
+C27 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD -0.42fF
+C28 vco_vctrl clk_1 -0.04fF
+C29 nDown biasp 0.26fF
+C30 vco_vctrl s_0 0.45fF
+C31 vco_vctrl vdd 0.58fF
+C32 charge_pump_0/w_2544_775# Down -0.23fF
+C33 s_1_n out_div 0.09fF
+C34 vdd buffer_salida_0/a_678_n100# 0.24fF
+C35 lf_vc MC 0.20fF
+C36 QA vdd -0.04fF
+C37 biasp Down 1.24fF
+C38 vdd out_to_buffer 0.07fF
+C39 vco_vctrl freq_div_0/div_by_5_0/Q1 0.10fF
+C40 MC vco_vctrl 0.33fF
+C41 pswitch Up 1.98fF
+C42 iref_cp Down 0.09fF
+C43 Up vdd 0.28fF
+C44 out_to_div out_to_buffer 0.13fF
+C45 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D 0.09fF
+C46 biasp nUp -0.16fF
+C47 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C48 out_to_div s_0 0.94fF
+C49 vco_vctrl freq_div_0/prescaler_23_0/Q2 0.06fF
+C50 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vco_vctrl 0.09fF
+C51 s_1 out_div 0.37fF
+C52 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vco_vctrl 0.17fF
+C53 pswitch nDown 0.53fF
+C54 vco_vctrl s_0_n 0.34fF
+C55 clk_d out_div 0.60fF
+C56 vdd nDown 0.22fF
+C57 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vco_vctrl -0.42fF
+C58 clk_1 n_out_by_2 -0.10fF
+C59 s_0 n_out_by_2 0.14fF
+C60 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vco_vctrl 0.82fF
+C61 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C62 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C63 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C64 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C65 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C66 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C67 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C68 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C69 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C70 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C71 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C72 QB vss 3.83fF
+C73 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C74 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C75 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C76 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C77 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C78 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C79 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C80 pfd_reset vss 1.87fF
+C81 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C82 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C83 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C84 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C85 QA vss 4.29fF
+C86 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C87 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C88 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C89 in_ref vss 0.84fF
+C90 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C91 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.66fF
+C92 nUp vss 0.30fF
+C93 Up vss 5.34fF
+C94 Down vss 0.91fF
+C95 nDown vss 1.94fF
+C96 out_to_buffer vss 1.92fF
+C97 out_to_div vss 8.72fF
+C98 out_first_buffer vss 2.15fF
+C99 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C100 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C101 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C102 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C103 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C104 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C105 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C106 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C107 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C108 vco_out vss 1.65fF
+C109 vco_D0 vss -4.72fF
+C110 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C111 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C112 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C113 out_to_pad vss 7.15fF
+C114 buffer_salida_0/a_3996_n100# vss 48.29fF
+C115 buffer_salida_0/a_678_n100# vss 13.38fF
+C116 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C117 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C118 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C119 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C120 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C121 freq_div_0/prescaler_23_0/Q2_d vss -0.69fF
+C122 freq_div_0/prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C123 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C124 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C125 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C126 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C127 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C128 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C129 freq_div_0/prescaler_23_0/Q2 vss 0.55fF
+C130 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C131 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C132 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C133 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C134 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C135 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C136 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C137 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C138 freq_div_0/prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C139 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C140 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C141 n_clk_0 vss -6.63fF
+C142 freq_div_0/prescaler_23_0/Q1 vss 0.07fF
+C143 freq_div_0/prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C144 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C145 clk_0 vss -0.36fF
+C146 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C147 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C148 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C149 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C150 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C151 freq_div_0/prescaler_23_0/nCLK_23 vss -1.02fF
+C152 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C153 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C154 MC vss -1.42fF
+C155 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C156 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C157 n_out_by_2 vss 4.53fF
+C158 out_by_2 vss 4.18fF
+C159 s_0_n vss -3.95fF
+C160 s_0 vss 5.61fF
+C161 freq_div_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C162 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C163 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C164 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C165 freq_div_0/div_by_5_0/Q1_shift vss -0.36fF
+C166 freq_div_0/div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C167 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C168 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C169 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C170 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C171 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C172 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C173 freq_div_0/div_by_5_0/Q1 vss 4.35fF
+C174 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C175 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C176 freq_div_0/div_by_5_0/Q0 vss 0.29fF
+C177 freq_div_0/div_by_5_0/nQ0 vss 0.99fF
+C178 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C179 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C180 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C181 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C182 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C183 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C184 freq_div_0/div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C185 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C186 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C187 freq_div_0/div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C188 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C189 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C190 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C191 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C192 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C193 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C194 freq_div_0/div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C195 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C196 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C197 n_clk_1 vss -0.57fF
+C198 freq_div_0/div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C199 freq_div_0/div_by_5_0/nQ2 vss 1.38fF
+C200 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C201 clk_1 vss -2.22fF
+C202 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C203 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C204 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C205 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C206 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C207 freq_div_0/div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C208 vdd vss 573.83fF
+C209 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C210 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C211 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C212 out_div vss 0.60fF
+C213 clk_d vss 1.26fF
+C214 s_1_n vss -2.01fF
+C215 s_1 vss 1.77fF
+C216 freq_div_0/inverter_min_x4_0/in vss 2.71fF
+C217 clk_5 vss -0.23fF
+C218 clk_out_mux21 vss 3.65fF
+C219 clk_pre vss 1.67fF
+C220 clk_2_f vss 3.29fF
+C221 freq_div_0/div_by_2_0/o1 vss 2.08fF
+C222 freq_div_0/div_by_2_0/nCLK_2 vss 1.04fF
+C223 freq_div_0/div_by_2_0/o2 vss 2.08fF
+C224 freq_div_0/div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C225 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C226 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C227 freq_div_0/div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C228 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C229 freq_div_0/div_by_2_0/out_div vss -0.82fF
+C230 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C231 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C232 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C233 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C234 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C235 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C236 freq_div_0/div_by_2_0/nout_div vss 2.62fF
+C237 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C238 out_buffer_div_2 vss 1.57fF
+C239 n_out_buffer_div_2 vss 1.57fF
+C240 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C241 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C242 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C243 div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C244 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C245 out_div_2 vss -0.70fF
+C246 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C247 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C248 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C249 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C250 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C251 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C252 n_out_div_2 vss 2.11fF
+C253 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C254 lf_vc vss -60.88fF
+C255 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C256 lf_D0 vss 0.01fF
+C257 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C258 nswitch vss 4.61fF
+C259 biasp vss 5.46fF
+C260 iref_cp vss 7.56fF
+C261 vco_vctrl vss -30.43fF
+C262 pswitch vss 2.72fF
+.ends
+
diff --git a/mag/extractions/top_pll_v3_pex_rc.spice b/mag/extractions/top_pll_v3_pex_rc.spice
new file mode 100644
index 0000000..dd649ea
--- /dev/null
+++ b/mag/extractions/top_pll_v3_pex_rc.spice
@@ -0,0 +1,3520 @@
+* NGSPICE file created from top_pll_v3.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_n2319_n486# w_n2457_n634# 0.02fF
+C1 a_429_n486# w_n2457_n634# 0.02fF
+C2 a_n1403_n486# w_n2457_n634# 0.02fF
+C3 w_n2457_n634# a_2261_n486# 0.02fF
+C4 w_n2457_n634# a_n1861_n486# 0.02fF
+C5 w_n2457_n634# a_n945_n486# 0.02fF
+C6 a_1803_n486# w_n2457_n634# 0.02fF
+C7 w_n2457_n634# a_n29_n486# 0.02fF
+C8 w_n2457_n634# a_n487_n486# 0.02fF
+C9 w_n2457_n634# a_1345_n486# 0.02fF
+C10 a_887_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_399_n75# a_687_n75# 0.05fF
+C1 a_n369_n75# a_n753_n75# 0.03fF
+C2 a_1167_n75# a_879_n75# 0.05fF
+C3 a_15_n75# a_303_n75# 0.05fF
+C4 a_n369_n75# a_n657_n75# 0.05fF
+C5 a_207_n75# a_495_n75# 0.05fF
+C6 a_15_n75# a_399_n75# 0.03fF
+C7 a_n177_n75# a_111_n75# 0.05fF
+C8 a_n465_n75# a_n561_n75# 0.22fF
+C9 a_591_n75# a_783_n75# 0.08fF
+C10 a_879_n75# a_687_n75# 0.08fF
+C11 a_n465_n75# a_n753_n75# 0.05fF
+C12 a_n1229_n75# a_n945_n75# 0.05fF
+C13 a_n273_n75# a_n561_n75# 0.05fF
+C14 a_975_n75# a_879_n75# 0.22fF
+C15 a_n465_n75# a_n657_n75# 0.08fF
+C16 a_15_n75# a_n177_n75# 0.08fF
+C17 a_n1137_n75# a_n1041_n75# 0.22fF
+C18 a_591_n75# a_495_n75# 0.22fF
+C19 a_n561_n75# a_n849_n75# 0.05fF
+C20 a_111_n75# a_n81_n75# 0.08fF
+C21 a_207_n75# a_111_n75# 0.22fF
+C22 a_n273_n75# a_n657_n75# 0.03fF
+C23 a_n753_n75# a_n849_n75# 0.22fF
+C24 a_399_n75# a_303_n75# 0.22fF
+C25 a_n657_n75# a_n849_n75# 0.08fF
+C26 a_n945_n75# a_n849_n75# 0.22fF
+C27 a_15_n75# a_n369_n75# 0.03fF
+C28 a_15_n75# a_n81_n75# 0.22fF
+C29 a_15_n75# a_207_n75# 0.08fF
+C30 a_1071_n75# a_879_n75# 0.08fF
+C31 a_n273_n75# a_111_n75# 0.03fF
+C32 a_495_n75# a_783_n75# 0.05fF
+C33 a_n561_n75# a_n753_n75# 0.08fF
+C34 a_591_n75# a_687_n75# 0.22fF
+C35 a_n657_n75# a_n561_n75# 0.22fF
+C36 a_n945_n75# a_n561_n75# 0.03fF
+C37 a_591_n75# a_975_n75# 0.03fF
+C38 a_15_n75# a_n273_n75# 0.05fF
+C39 a_n1229_n75# a_n1041_n75# 0.08fF
+C40 a_n945_n75# a_n753_n75# 0.08fF
+C41 a_n657_n75# a_n753_n75# 0.22fF
+C42 a_1167_n75# a_783_n75# 0.03fF
+C43 a_n945_n75# a_n657_n75# 0.05fF
+C44 a_303_n75# a_n81_n75# 0.03fF
+C45 a_207_n75# a_303_n75# 0.22fF
+C46 a_399_n75# a_207_n75# 0.08fF
+C47 a_687_n75# a_783_n75# 0.22fF
+C48 a_n849_n75# a_n1041_n75# 0.08fF
+C49 a_975_n75# a_783_n75# 0.08fF
+C50 a_495_n75# a_111_n75# 0.03fF
+C51 a_n177_n75# a_n369_n75# 0.08fF
+C52 a_591_n75# a_303_n75# 0.05fF
+C53 a_n177_n75# a_n81_n75# 0.22fF
+C54 a_495_n75# a_687_n75# 0.08fF
+C55 a_n1137_n75# a_n1229_n75# 0.22fF
+C56 a_207_n75# a_n177_n75# 0.03fF
+C57 a_399_n75# a_591_n75# 0.08fF
+C58 a_n465_n75# a_n177_n75# 0.05fF
+C59 a_n369_n75# a_n81_n75# 0.05fF
+C60 a_n753_n75# a_n1041_n75# 0.05fF
+C61 a_n1137_n75# a_n849_n75# 0.05fF
+C62 a_207_n75# a_n81_n75# 0.05fF
+C63 a_591_n75# a_879_n75# 0.05fF
+C64 a_1167_n75# a_975_n75# 0.08fF
+C65 a_1071_n75# a_783_n75# 0.05fF
+C66 a_n273_n75# a_n177_n75# 0.22fF
+C67 a_n945_n75# a_n1041_n75# 0.22fF
+C68 a_n657_n75# a_n1041_n75# 0.03fF
+C69 a_n465_n75# a_n369_n75# 0.22fF
+C70 a_399_n75# a_783_n75# 0.03fF
+C71 a_15_n75# a_111_n75# 0.22fF
+C72 a_n465_n75# a_n81_n75# 0.03fF
+C73 a_975_n75# a_687_n75# 0.05fF
+C74 a_n273_n75# a_n369_n75# 0.22fF
+C75 a_303_n75# a_495_n75# 0.08fF
+C76 a_207_n75# a_591_n75# 0.03fF
+C77 a_n273_n75# a_n81_n75# 0.08fF
+C78 a_399_n75# a_495_n75# 0.22fF
+C79 a_879_n75# a_783_n75# 0.22fF
+C80 a_n1137_n75# a_n753_n75# 0.03fF
+C81 a_1167_n75# a_1071_n75# 0.22fF
+C82 a_n177_n75# a_n561_n75# 0.03fF
+C83 a_n1137_n75# a_n945_n75# 0.08fF
+C84 a_n465_n75# a_n273_n75# 0.08fF
+C85 a_495_n75# a_879_n75# 0.03fF
+C86 a_n1229_n75# a_n849_n75# 0.03fF
+C87 a_303_n75# a_111_n75# 0.08fF
+C88 a_n465_n75# a_n849_n75# 0.03fF
+C89 a_1071_n75# a_687_n75# 0.03fF
+C90 a_399_n75# a_111_n75# 0.05fF
+C91 a_n369_n75# a_n561_n75# 0.08fF
+C92 a_1071_n75# a_975_n75# 0.22fF
+C93 a_303_n75# a_687_n75# 0.03fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_159_n75# a_447_n75# 0.05fF
+C1 a_n705_n75# a_n989_n75# 0.05fF
+C2 a_n705_n75# a_n513_n75# 0.08fF
+C3 a_n321_n75# a_n33_n75# 0.05fF
+C4 a_831_n75# a_543_n75# 0.05fF
+C5 a_n609_n75# a_n417_n75# 0.08fF
+C6 a_n321_n75# a_63_n75# 0.03fF
+C7 a_n513_n75# a_n225_n75# 0.05fF
+C8 a_735_n75# a_639_n75# 0.22fF
+C9 a_n33_n75# a_255_n75# 0.05fF
+C10 a_63_n75# a_255_n75# 0.08fF
+C11 a_n705_n75# a_n417_n75# 0.05fF
+C12 a_n897_n75# a_n989_n75# 0.22fF
+C13 a_n513_n75# a_n897_n75# 0.03fF
+C14 a_735_n75# a_351_n75# 0.03fF
+C15 a_735_n75# a_543_n75# 0.08fF
+C16 a_n321_n75# a_n513_n75# 0.08fF
+C17 a_639_n75# a_447_n75# 0.08fF
+C18 a_n225_n75# a_n417_n75# 0.08fF
+C19 a_n129_n75# a_n225_n75# 0.22fF
+C20 a_351_n75# a_159_n75# 0.08fF
+C21 a_159_n75# a_543_n75# 0.03fF
+C22 a_63_n75# a_n33_n75# 0.22fF
+C23 a_351_n75# a_447_n75# 0.22fF
+C24 a_543_n75# a_447_n75# 0.22fF
+C25 a_n321_n75# a_n417_n75# 0.22fF
+C26 a_n321_n75# a_n129_n75# 0.08fF
+C27 a_n801_n75# a_n989_n75# 0.08fF
+C28 a_n513_n75# a_n801_n75# 0.05fF
+C29 a_159_n75# a_n225_n75# 0.03fF
+C30 a_n129_n75# a_255_n75# 0.03fF
+C31 a_351_n75# a_639_n75# 0.05fF
+C32 a_543_n75# a_639_n75# 0.22fF
+C33 a_n801_n75# a_n417_n75# 0.03fF
+C34 a_351_n75# a_543_n75# 0.08fF
+C35 a_n33_n75# a_n417_n75# 0.03fF
+C36 a_n129_n75# a_n33_n75# 0.22fF
+C37 a_159_n75# a_255_n75# 0.22fF
+C38 a_63_n75# a_n129_n75# 0.08fF
+C39 a_n705_n75# a_n609_n75# 0.22fF
+C40 a_927_n75# a_831_n75# 0.22fF
+C41 a_n927_n101# a_33_n101# 0.08fF
+C42 a_447_n75# a_255_n75# 0.08fF
+C43 a_n609_n75# a_n225_n75# 0.03fF
+C44 a_n513_n75# a_n417_n75# 0.22fF
+C45 a_n129_n75# a_n513_n75# 0.03fF
+C46 a_159_n75# a_n33_n75# 0.08fF
+C47 a_735_n75# a_927_n75# 0.08fF
+C48 a_n897_n75# a_n609_n75# 0.05fF
+C49 a_63_n75# a_159_n75# 0.22fF
+C50 a_n321_n75# a_n609_n75# 0.05fF
+C51 a_639_n75# a_255_n75# 0.03fF
+C52 a_63_n75# a_447_n75# 0.03fF
+C53 a_n129_n75# a_n417_n75# 0.05fF
+C54 a_n705_n75# a_n897_n75# 0.08fF
+C55 a_351_n75# a_255_n75# 0.22fF
+C56 a_543_n75# a_255_n75# 0.05fF
+C57 a_n321_n75# a_n705_n75# 0.03fF
+C58 a_735_n75# a_831_n75# 0.22fF
+C59 a_n321_n75# a_n225_n75# 0.22fF
+C60 a_n801_n75# a_n609_n75# 0.08fF
+C61 a_927_n75# a_639_n75# 0.05fF
+C62 a_351_n75# a_n33_n75# 0.03fF
+C63 a_n129_n75# a_159_n75# 0.05fF
+C64 a_831_n75# a_447_n75# 0.03fF
+C65 a_63_n75# a_351_n75# 0.05fF
+C66 a_n705_n75# a_n801_n75# 0.22fF
+C67 a_927_n75# a_543_n75# 0.03fF
+C68 a_n609_n75# a_n989_n75# 0.03fF
+C69 a_n513_n75# a_n609_n75# 0.22fF
+C70 a_n33_n75# a_n225_n75# 0.08fF
+C71 a_735_n75# a_447_n75# 0.05fF
+C72 a_63_n75# a_n225_n75# 0.05fF
+C73 a_831_n75# a_639_n75# 0.08fF
+C74 a_n801_n75# a_n897_n75# 0.22fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n989_n150# a_n609_n150# 0.07fF
+C1 a_447_n150# a_159_n150# 0.10fF
+C2 a_447_n150# a_639_n150# 0.16fF
+C3 a_543_n150# a_735_n150# 0.16fF
+C4 a_63_n150# a_n321_n150# 0.07fF
+C5 a_n513_n150# a_n897_n150# 0.07fF
+C6 a_n417_n150# a_n129_n150# 0.10fF
+C7 a_927_n150# a_831_n150# 0.43fF
+C8 a_n321_n150# a_n129_n150# 0.16fF
+C9 a_447_n150# a_735_n150# 0.10fF
+C10 a_255_n150# a_159_n150# 0.43fF
+C11 a_639_n150# a_255_n150# 0.07fF
+C12 a_n801_n150# a_n897_n150# 0.43fF
+C13 a_63_n150# a_159_n150# 0.43fF
+C14 a_927_n150# a_543_n150# 0.07fF
+C15 a_n513_n150# a_n609_n150# 0.43fF
+C16 a_n33_n150# a_n225_n150# 0.16fF
+C17 a_159_n150# a_n129_n150# 0.10fF
+C18 a_n321_n150# a_n417_n150# 0.43fF
+C19 a_n801_n150# a_n609_n150# 0.16fF
+C20 a_n897_n150# a_n705_n150# 0.16fF
+C21 a_351_n150# a_159_n150# 0.16fF
+C22 a_639_n150# a_351_n150# 0.10fF
+C23 a_n225_n150# a_n609_n150# 0.07fF
+C24 a_543_n150# a_831_n150# 0.10fF
+C25 a_n513_n150# a_n129_n150# 0.07fF
+C26 a_n609_n150# a_n705_n150# 0.43fF
+C27 a_63_n150# a_n225_n150# 0.10fF
+C28 a_351_n150# a_735_n150# 0.07fF
+C29 a_447_n150# a_831_n150# 0.07fF
+C30 a_n513_n150# a_n417_n150# 0.43fF
+C31 a_n225_n150# a_n129_n150# 0.43fF
+C32 a_n321_n150# a_n513_n150# 0.16fF
+C33 a_447_n150# a_543_n150# 0.43fF
+C34 a_n801_n150# a_n417_n150# 0.07fF
+C35 a_639_n150# a_735_n150# 0.43fF
+C36 a_n989_n150# a_n801_n150# 0.16fF
+C37 a_n897_n150# a_n609_n150# 0.10fF
+C38 a_n225_n150# a_n417_n150# 0.16fF
+C39 a_255_n150# a_543_n150# 0.10fF
+C40 a_n321_n150# a_n225_n150# 0.43fF
+C41 a_n33_n150# a_255_n150# 0.10fF
+C42 a_n417_n150# a_n705_n150# 0.10fF
+C43 a_63_n150# a_n33_n150# 0.43fF
+C44 a_n321_n150# a_n705_n150# 0.07fF
+C45 a_n989_n150# a_n705_n150# 0.10fF
+C46 a_447_n150# a_255_n150# 0.16fF
+C47 a_927_n150# a_639_n150# 0.10fF
+C48 a_n225_n150# a_159_n150# 0.07fF
+C49 a_n33_n150# a_n129_n150# 0.43fF
+C50 a_63_n150# a_447_n150# 0.07fF
+C51 a_n927_n247# a_33_n247# 0.09fF
+C52 a_n513_n150# a_n801_n150# 0.10fF
+C53 a_351_n150# a_543_n150# 0.16fF
+C54 a_n33_n150# a_351_n150# 0.07fF
+C55 a_927_n150# a_735_n150# 0.16fF
+C56 a_n33_n150# a_n417_n150# 0.07fF
+C57 a_n513_n150# a_n225_n150# 0.10fF
+C58 a_63_n150# a_255_n150# 0.16fF
+C59 a_n321_n150# a_n33_n150# 0.10fF
+C60 a_447_n150# a_351_n150# 0.43fF
+C61 a_639_n150# a_831_n150# 0.16fF
+C62 a_n513_n150# a_n705_n150# 0.16fF
+C63 a_255_n150# a_n129_n150# 0.07fF
+C64 a_n989_n150# a_n897_n150# 0.43fF
+C65 a_63_n150# a_n129_n150# 0.16fF
+C66 a_543_n150# a_159_n150# 0.07fF
+C67 a_639_n150# a_543_n150# 0.43fF
+C68 a_n801_n150# a_n705_n150# 0.43fF
+C69 a_n417_n150# a_n609_n150# 0.16fF
+C70 a_n33_n150# a_159_n150# 0.16fF
+C71 a_n321_n150# a_n609_n150# 0.10fF
+C72 a_735_n150# a_831_n150# 0.43fF
+C73 a_351_n150# a_255_n150# 0.43fF
+C74 a_63_n150# a_351_n150# 0.10fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n745_n44# a_n1103_n44# 0.04fF
+C1 a_329_n44# a_n29_n44# 0.04fF
+C2 a_n745_n44# a_n387_n44# 0.04fF
+C3 a_687_n44# a_1045_n44# 0.04fF
+C4 a_n1819_n44# a_n1461_n44# 0.04fF
+C5 a_329_n44# a_687_n44# 0.04fF
+C6 a_1761_n44# a_1403_n44# 0.04fF
+C7 a_1403_n44# a_1045_n44# 0.04fF
+C8 a_n29_n44# a_n387_n44# 0.04fF
+C9 a_n1461_n44# a_n1103_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n657_n150# a_n273_n150# 0.07fF
+C1 a_n849_n150# a_n945_n150# 0.43fF
+C2 a_687_n150# a_1071_n150# 0.07fF
+C3 a_783_n150# a_687_n150# 0.43fF
+C4 a_n1137_n150# a_n849_n150# 0.10fF
+C5 a_n81_n150# a_111_n150# 0.16fF
+C6 a_n753_n150# a_n561_n150# 0.16fF
+C7 a_n657_n150# a_n945_n150# 0.10fF
+C8 a_n177_n150# a_n561_n150# 0.07fF
+C9 a_207_n150# a_111_n150# 0.43fF
+C10 a_687_n150# a_303_n150# 0.07fF
+C11 a_207_n150# a_591_n150# 0.07fF
+C12 a_n945_n150# a_n1041_n150# 0.43fF
+C13 a_n465_n150# a_n561_n150# 0.43fF
+C14 a_n1137_n150# a_n1041_n150# 0.43fF
+C15 a_1167_n150# a_975_n150# 0.16fF
+C16 w_n1367_n369# a_975_n150# 0.05fF
+C17 a_1167_n150# a_879_n150# 0.10fF
+C18 w_n1367_n369# a_879_n150# 0.04fF
+C19 a_n273_n150# a_15_n150# 0.10fF
+C20 a_207_n150# a_495_n150# 0.10fF
+C21 a_n177_n150# a_n273_n150# 0.43fF
+C22 a_303_n150# a_15_n150# 0.10fF
+C23 a_n753_n150# a_n945_n150# 0.16fF
+C24 a_n465_n150# a_n273_n150# 0.16fF
+C25 a_n1137_n150# a_n753_n150# 0.07fF
+C26 a_n81_n150# a_n273_n150# 0.16fF
+C27 a_n561_n150# a_n369_n150# 0.16fF
+C28 a_1167_n150# a_1071_n150# 0.43fF
+C29 a_783_n150# a_1167_n150# 0.07fF
+C30 w_n1367_n369# a_1071_n150# 0.07fF
+C31 a_n657_n150# a_n849_n150# 0.16fF
+C32 a_n81_n150# a_303_n150# 0.07fF
+C33 a_687_n150# a_399_n150# 0.10fF
+C34 a_n849_n150# a_n1041_n150# 0.16fF
+C35 a_591_n150# a_975_n150# 0.07fF
+C36 a_207_n150# a_303_n150# 0.43fF
+C37 a_495_n150# a_111_n150# 0.07fF
+C38 a_879_n150# a_591_n150# 0.10fF
+C39 a_n273_n150# a_n369_n150# 0.43fF
+C40 a_495_n150# a_591_n150# 0.43fF
+C41 a_879_n150# a_975_n150# 0.43fF
+C42 a_n657_n150# a_n1041_n150# 0.07fF
+C43 a_399_n150# a_15_n150# 0.07fF
+C44 a_495_n150# a_879_n150# 0.07fF
+C45 a_n849_n150# a_n753_n150# 0.43fF
+C46 a_783_n150# a_591_n150# 0.16fF
+C47 a_n273_n150# a_111_n150# 0.07fF
+C48 a_1071_n150# a_975_n150# 0.43fF
+C49 a_783_n150# a_975_n150# 0.16fF
+C50 a_879_n150# a_1071_n150# 0.16fF
+C51 a_783_n150# a_879_n150# 0.43fF
+C52 a_n657_n150# a_n753_n150# 0.43fF
+C53 a_303_n150# a_111_n150# 0.16fF
+C54 a_783_n150# a_495_n150# 0.10fF
+C55 a_n465_n150# a_n849_n150# 0.07fF
+C56 a_591_n150# a_303_n150# 0.10fF
+C57 a_207_n150# a_399_n150# 0.16fF
+C58 a_n753_n150# a_n1041_n150# 0.10fF
+C59 a_783_n150# a_1071_n150# 0.10fF
+C60 a_n657_n150# a_n465_n150# 0.16fF
+C61 a_n561_n150# a_n273_n150# 0.10fF
+C62 a_495_n150# a_303_n150# 0.16fF
+C63 a_n1229_n150# a_n945_n150# 0.10fF
+C64 a_n1137_n150# a_n1229_n150# 0.43fF
+C65 a_n945_n150# a_n561_n150# 0.07fF
+C66 a_n657_n150# a_n369_n150# 0.10fF
+C67 a_n177_n150# a_15_n150# 0.16fF
+C68 a_399_n150# a_111_n150# 0.10fF
+C69 a_399_n150# a_591_n150# 0.16fF
+C70 a_n465_n150# a_n753_n150# 0.10fF
+C71 a_n177_n150# a_n465_n150# 0.10fF
+C72 a_n81_n150# a_15_n150# 0.43fF
+C73 a_n81_n150# a_n177_n150# 0.43fF
+C74 a_399_n150# a_495_n150# 0.43fF
+C75 a_207_n150# a_15_n150# 0.16fF
+C76 a_n177_n150# a_207_n150# 0.07fF
+C77 a_n1229_n150# a_n849_n150# 0.07fF
+C78 a_n1137_n150# a_n945_n150# 0.16fF
+C79 a_n81_n150# a_n465_n150# 0.07fF
+C80 a_n849_n150# a_n561_n150# 0.10fF
+C81 a_n753_n150# a_n369_n150# 0.07fF
+C82 a_783_n150# a_399_n150# 0.07fF
+C83 a_15_n150# a_n369_n150# 0.07fF
+C84 a_n177_n150# a_n369_n150# 0.16fF
+C85 a_687_n150# a_591_n150# 0.43fF
+C86 a_n81_n150# a_207_n150# 0.10fF
+C87 a_n657_n150# a_n561_n150# 0.43fF
+C88 a_687_n150# a_975_n150# 0.10fF
+C89 a_687_n150# a_879_n150# 0.16fF
+C90 a_n465_n150# a_n369_n150# 0.43fF
+C91 a_n1229_n150# a_n1041_n150# 0.16fF
+C92 a_399_n150# a_303_n150# 0.43fF
+C93 a_n81_n150# a_n369_n150# 0.10fF
+C94 a_687_n150# a_495_n150# 0.16fF
+C95 a_1167_n150# w_n1367_n369# 0.14fF
+C96 a_15_n150# a_111_n150# 0.43fF
+C97 a_n177_n150# a_111_n150# 0.10fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vss vdd nUp Down w_2544_775# out pswitch iref nDown biasp
++ Up w_6648_570#
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 pswitch biasp 3.11fF
+C1 vdd pswitch 3.98fF
+C2 nDown Down 0.13fF
+C3 iref biasp 0.80fF
+C4 pswitch nswitch 0.06fF
+C5 iref nswitch 1.91fF
+C6 nUp pswitch 5.66fF
+C7 out vdd 6.66fF
+C8 nDown nswitch 0.31fF
+C9 out nswitch 1.28fF
+C10 Down nswitch 2.27fF
+C11 vdd biasp 2.64fF
+C12 out pswitch 4.91fF
+C13 pswitch Up 0.70fF
+C14 biasp nswitch 0.03fF
+C15 nUp out 0.31fF
+C16 nUp Down 0.25fF
+C17 nUp Up 0.15fF
+C18 vdd nswitch 0.07fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C1 m3_7988_8000# m3_2669_8000# 2.73fF
+C2 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C3 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C4 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C5 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C6 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C7 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C8 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C9 m3_2669_2700# m3_n2650_2700# 2.73fF
+C10 m3_2669_n2600# c1_n13188_n13100# 58.86fF
+C11 m3_7988_n13200# m3_7988_n7900# 3.39fF
+C12 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C13 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C14 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C15 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C16 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C17 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C18 m3_2669_2700# m3_2669_n2600# 3.28fF
+C19 m3_n2650_n2600# m3_n7969_n2600# 2.73fF
+C20 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C21 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C22 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C23 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C24 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C25 m3_7988_n2600# m3_7988_n7900# 3.39fF
+C26 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C27 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C28 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C29 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C30 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C31 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C32 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C33 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C34 m3_2669_n13200# m3_n2650_n13200# 2.73fF
+C35 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C36 m3_2669_2700# m3_7988_2700# 2.73fF
+C37 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C38 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C39 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C40 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C41 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C42 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C43 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C44 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C45 m3_n2650_n2600# m3_n2650_2700# 3.28fF
+C46 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C47 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C48 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C49 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C50 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C51 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C52 m3_2669_2700# m3_2669_8000# 3.28fF
+C53 m3_2669_n2600# m3_n2650_n2600# 2.73fF
+C54 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C55 m3_7988_2700# m3_7988_8000# 3.39fF
+C56 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C57 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C58 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C59 m3_7988_2700# m3_7988_n2600# 3.39fF
+C60 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C61 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C62 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C63 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C64 m3_n2650_8000# m3_2669_8000# 2.73fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n4309_n4250# m3_n4309_50# 2.63fF
+C1 m3_n4309_50# m3_10_n4250# 1.75fF
+C2 c1_n4209_n4150# m3_n4309_50# 38.10fF
+C3 c1_110_n4150# m3_10_n4250# 81.11fF
+C4 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C5 m3_n4309_n4250# m3_10_n4250# 1.75fF
+C6 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 out in 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C1 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C2 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C3 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
+C4 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C5 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C6 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C7 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C8 m3_n2150_2200# m3_n6469_2200# 1.75fF
+C9 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C10 c1_2269_n6300# c1_n2050_n6300# 1.99fF
+C11 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C12 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C13 c1_2269_n6300# m3_2169_n6400# 121.67fF
+C14 c1_n6369_n6300# m3_n6469_2200# 38.10fF
+C15 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C16 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C17 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C18 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_n88_n300# a_n118_n388# 0.11fF
+C1 a_n88_n300# a_30_n300# 0.61fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 D0_cap in 0.07fF
+C1 cap3_loop_filter_0/in in 0.79fF
+C2 vc_pex in 0.18fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS w_n311_n338# a_81_n156# a_111_n125# a_15_n125#
++ a_n173_n125# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n173_n125# 0.08fF
+C1 a_n15_n156# a_n111_n156# 0.02fF
+C2 a_n15_n156# a_81_n156# 0.02fF
+C3 a_n81_n125# a_15_n125# 0.36fF
+C4 a_n81_n125# a_n173_n125# 0.36fF
+C5 a_n173_n125# a_15_n125# 0.13fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_111_n125# a_15_n125# 0.36fF
+C8 a_111_n125# VSUBS 0.03fF
+C9 a_15_n125# VSUBS 0.03fF
+C10 a_n81_n125# VSUBS 0.03fF
+C11 a_n173_n125# VSUBS 0.03fF
+C12 a_81_n156# VSUBS 0.05fF
+C13 a_n15_n156# VSUBS 0.05fF
+C14 a_n111_n156# VSUBS 0.05fF
+C15 w_n311_n338# VSUBS 1.56fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_81_n151# a_n15_n151# 0.02fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 a_n15_n151# a_n111_n151# 0.02fF
+C3 a_15_n125# a_n173_n125# 0.13fF
+C4 a_n173_n125# a_111_n125# 0.08fF
+C5 a_15_n125# a_n81_n125# 0.36fF
+C6 a_n81_n125# a_111_n125# 0.13fF
+C7 a_n81_n125# a_n173_n125# 0.36fF
+C8 a_111_n125# w_n311_n335# 0.04fF
+C9 a_15_n125# w_n311_n335# 0.04fF
+C10 a_n81_n125# w_n311_n335# 0.04fF
+C11 a_n173_n125# w_n311_n335# 0.04fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# vss m1_45_n513# vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd vss m1_187_n605# m1_45_n513# m1_45_n513#
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_187_n605# m1_45_n513# 0.36fF
+C1 vdd m1_45_n513# 0.69fF
+C2 vdd m1_187_n605# 0.55fF
+C3 m1_187_n605# vss 0.73fF
+C4 m1_45_n513# vss 1.10fF
+C5 vdd vss 2.55fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# w_n311_n344# 0.14fF
+C1 w_n311_n344# a_111_n125# 0.14fF
+C2 a_n81_n125# a_15_n125# 0.36fF
+C3 a_n173_n125# a_15_n125# 0.13fF
+C4 a_111_n125# a_15_n125# 0.36fF
+C5 a_n173_n125# a_n81_n125# 0.36fF
+C6 w_n311_n344# a_15_n125# 0.09fF
+C7 a_111_n125# a_n81_n125# 0.13fF
+C8 a_n173_n125# a_111_n125# 0.08fF
+C9 w_n311_n344# a_n81_n125# 0.09fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_111_n125# 0.36fF
+C1 a_n81_n125# a_111_n125# 0.13fF
+C2 a_n173_n125# a_111_n125# 0.08fF
+C3 a_n81_n125# a_15_n125# 0.36fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 out in 0.32fF
+C1 vdd out 0.10fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d vss inverter_cp_x1_0/out vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 CLK_d inverter_cp_x1_2/in 0.12fF
+C1 CLK_d vdd 0.03fF
+C2 inverter_cp_x1_0/out vdd 0.21fF
+C3 inverter_cp_x1_2/in vdd 0.21fF
+C4 inverter_cp_x1_0/out nCLK_d 0.11fF
+C5 vdd nCLK_d 0.03fF
+C6 inverter_cp_x1_0/out CLK 0.31fF
+C7 inverter_cp_x1_2/in CLK 0.31fF
+C8 vdd CLK 0.36fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.69fF
+C12 CLK vss 3.03fF
+C13 vdd vss 15.46fF
+C14 nCLK_d vss 1.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_63_n95# 0.11fF
+C1 w_n263_n314# a_n125_n95# 0.11fF
+C2 a_63_n95# a_n125_n95# 0.10fF
+C3 w_n263_n314# a_n33_n95# 0.08fF
+C4 a_n33_n95# a_63_n95# 0.28fF
+C5 a_n33_n95# a_n125_n95# 0.28fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_n129_n213# a_111_n125# 0.01fF
+C2 a_n129_n213# a_n81_n125# 0.10fF
+C3 a_111_n125# a_n81_n125# 0.13fF
+C4 a_n129_n213# a_15_n125# 0.10fF
+C5 a_15_n125# a_111_n125# 0.36fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 a_n129_n213# a_n173_n125# 0.02fF
+C8 a_111_n125# a_n173_n125# 0.08fF
+C9 a_n173_n125# a_n81_n125# 0.36fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n81_n183# a_n33_n95# 0.10fF
+C1 a_n81_n183# a_n125_n95# 0.16fF
+C2 a_n125_n95# a_n33_n95# 0.88fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 Q nQ 0.93fF
+C1 nD Q 0.05fF
+C2 nD nQ 0.05fF
+C3 vdd Q 0.16fF
+C4 vdd nQ 0.16fF
+C5 D Q 0.05fF
+C6 m1_657_280# Q 0.94fF
+C7 D nQ 0.05fF
+C8 m1_657_280# CLK 0.24fF
+C9 m1_657_280# nQ 1.41fF
+C10 D vss 0.53fF
+C11 m1_657_280# vss 1.88fF
+C12 nD vss 0.16fF
+C13 CLK vss 0.87fF
+C14 Q vss -0.55fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vdd vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ nCLK latch_diff_0/nD Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D
++ CLK clock_inverter_0/inverter_cp_x1_0/out
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_1/D latch_diff_1/nD 0.33fF
+C1 latch_diff_1/D latch_diff_0/D 0.11fF
+C2 vdd latch_diff_1/nD 0.02fF
+C3 vdd latch_diff_0/D 0.09fF
+C4 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C5 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C6 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C7 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C8 latch_diff_0/D latch_diff_1/nD 0.04fF
+C9 latch_diff_1/D latch_diff_0/nD 0.41fF
+C10 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C11 vdd latch_diff_0/nD 0.14fF
+C12 nQ latch_diff_1/D 0.11fF
+C13 Q latch_diff_1/nD 0.01fF
+C14 latch_diff_1/D vdd 0.01fF
+C15 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C16 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C17 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C18 nQ latch_diff_1/nD 0.08fF
+C19 latch_diff_1/m1_657_280# vss 0.64fF
+C20 nCLK vss 0.83fF
+C21 Q vss -0.92fF
+C22 nQ vss 0.57fF
+C23 latch_diff_0/m1_657_280# vss 0.69fF
+C24 CLK vss 0.83fF
+C25 latch_diff_1/D vss -0.33fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.63fF
+C30 D vss 3.27fF
+C31 vdd vss 31.85fF
+C32 latch_diff_0/nD vss 1.53fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n221_n84# w_n359_n303# 0.08fF
+C1 a_159_n84# a_n221_n84# 0.04fF
+C2 a_n221_n84# a_n33_n84# 0.09fF
+C3 a_33_n110# a_129_n110# 0.02fF
+C4 a_63_n84# w_n359_n303# 0.06fF
+C5 a_63_n84# a_159_n84# 0.24fF
+C6 a_63_n84# a_n33_n84# 0.24fF
+C7 a_n63_n110# a_n159_n110# 0.02fF
+C8 a_n129_n84# a_n221_n84# 0.24fF
+C9 a_n129_n84# a_63_n84# 0.09fF
+C10 a_159_n84# w_n359_n303# 0.08fF
+C11 w_n359_n303# a_n33_n84# 0.05fF
+C12 a_159_n84# a_n33_n84# 0.09fF
+C13 a_n129_n84# w_n359_n303# 0.06fF
+C14 a_n63_n110# a_33_n110# 0.02fF
+C15 a_n129_n84# a_159_n84# 0.05fF
+C16 a_n129_n84# a_n33_n84# 0.24fF
+C17 a_63_n84# a_n221_n84# 0.05fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n159_n68# a_n63_n68# 0.02fF
+C1 a_n33_n42# a_63_n42# 0.12fF
+C2 a_159_n42# a_n129_n42# 0.03fF
+C3 a_n129_n42# a_n221_n42# 0.12fF
+C4 a_159_n42# a_n221_n42# 0.02fF
+C5 a_33_n68# a_129_n68# 0.02fF
+C6 a_n63_n68# a_33_n68# 0.02fF
+C7 a_n129_n42# a_63_n42# 0.05fF
+C8 a_n129_n42# a_n33_n42# 0.12fF
+C9 a_159_n42# a_63_n42# 0.12fF
+C10 a_159_n42# a_n33_n42# 0.05fF
+C11 a_n221_n42# a_63_n42# 0.03fF
+C12 a_n33_n42# a_n221_n42# 0.05fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 vdd out 0.62fF
+C1 in out 0.67fF
+C2 vdd in 0.33fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_63_n42# a_n125_n42# 0.05fF
+C1 a_n33_n42# a_n125_n42# 0.12fF
+C2 a_n33_n42# a_63_n42# 0.12fF
+C3 a_33_n68# a_n63_n68# 0.02fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_63_n84# w_n263_n303# 0.10fF
+C1 a_63_n84# a_n33_n84# 0.24fF
+C2 a_n33_n84# w_n263_n303# 0.07fF
+C3 a_63_n84# a_n125_n84# 0.09fF
+C4 a_n125_n84# w_n263_n303# 0.10fF
+C5 a_n63_n110# a_33_n110# 0.02fF
+C6 a_n125_n84# a_n33_n84# 0.24fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 vdd in 0.01fF
+C1 out in 0.30fF
+C2 vdd out 0.15fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vdd vss nout_div CLK_2 nCLK_2 o1 o2 CLK out_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD
++ out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 o2 vdd 0.14fF
+C1 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C2 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C3 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C4 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C5 o1 vdd 0.14fF
+C6 nCLK_2 vdd 0.08fF
+C7 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C8 vdd nout_div 0.16fF
+C9 o1 CLK_2 0.11fF
+C10 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C11 DFlipFlop_0/latch_diff_0/nD nout_div 0.07fF
+C12 DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.29fF
+C13 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C14 vdd CLK_2 0.08fF
+C15 nout_div DFlipFlop_0/CLK 0.42fF
+C16 vdd DFlipFlop_0/CLK 0.40fF
+C17 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C18 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C19 DFlipFlop_0/latch_diff_0/D DFlipFlop_0/nCLK 0.13fF
+C20 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C21 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C22 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C23 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C24 out_div o1 0.01fF
+C25 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C26 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
+C27 out_div nout_div 0.22fF
+C28 out_div vdd 0.03fF
+C29 nout_div DFlipFlop_0/nCLK 0.43fF
+C30 vdd DFlipFlop_0/nCLK 0.30fF
+C31 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C32 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C33 nCLK_2 o2 0.11fF
+C34 CLK_2 vss 1.08fF
+C35 o1 vss 2.21fF
+C36 nCLK_2 vss 1.08fF
+C37 o2 vss 2.21fF
+C38 DFlipFlop_0/CLK vss 1.03fF
+C39 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C40 clock_inverter_0/inverter_cp_x1_0/out vss 1.64fF
+C41 CLK vss 3.27fF
+C42 DFlipFlop_0/nCLK vss 1.55fF
+C43 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C46 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C47 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C48 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.59fF
+C51 nout_div vss 4.41fF
+C52 vdd vss 62.89fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+.ends
+
+.subckt trans_gate_mux2to8 in vss out en_pos en_neg vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd en_neg in out out en_neg en_neg in sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 en_pos vss en_pos in out out en_pos in sky130_fd_pr__nfet_01v8_BHR94T
+C0 en_neg in 0.28fF
+C1 out en_neg 0.07fF
+C2 en_neg en_pos 0.04fF
+C3 out in 0.36fF
+C4 in en_pos 0.07fF
+C5 vdd in 0.05fF
+C6 out en_pos 0.27fF
+C7 out vdd 0.27fF
+C8 vdd vss 2.08fF
+C9 in vss 1.12fF
+C10 out vss 0.87fF
+C11 en_pos vss 0.29fF
+C12 en_neg vss 0.31fF
+.ends
+
+.subckt mux2to1 vss select_0_neg out_a_0 out_a_1 select_0 vdd in_a
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 out_a_1 in_a 0.08fF
+C1 select_0 select_0_neg 0.17fF
+C2 vdd out_a_0 0.06fF
+C3 out_a_0 select_0_neg 0.05fF
+C4 in_a select_0 0.31fF
+C5 vdd in_a 0.02fF
+C6 in_a select_0_neg 0.11fF
+C7 in_a out_a_0 0.08fF
+C8 out_a_1 select_0 0.14fF
+C9 vdd out_a_1 0.06fF
+C10 out_a_1 vss 0.99fF
+C11 vdd vss 4.78fF
+C12 in_a vss 2.00fF
+C13 out_a_0 vss 0.99fF
+C14 select_0_neg vss 1.15fF
+C15 select_0 vss 0.97fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_194_125# B 0.57fF
+C1 a_194_125# X 0.29fF
+C2 a_194_125# VPWR 0.33fF
+C3 A VGND 0.31fF
+C4 a_158_392# a_194_125# 0.06fF
+C5 a_194_125# a_355_368# 0.51fF
+C6 B X 0.13fF
+C7 B VPWR 0.09fF
+C8 B a_355_368# 0.08fF
+C9 X VPWR 0.07fF
+C10 X a_355_368# 0.17fF
+C11 VPWR a_355_368# 0.37fF
+C12 A a_194_125# 0.18fF
+C13 VPWR VPB 0.06fF
+C14 A B 0.28fF
+C15 VGND a_194_125# 0.25fF
+C16 VGND B 0.10fF
+C17 A VPWR 0.15fF
+C18 A a_355_368# 0.02fF
+C19 VGND X 0.28fF
+C20 VGND VPWR 0.01fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 A VGND 0.21fF
+C1 X VGND 0.15fF
+C2 VPWR A 0.07fF
+C3 VPWR X 0.20fF
+C4 B a_56_136# 0.30fF
+C5 B VGND 0.03fF
+C6 B VPWR 0.02fF
+C7 a_56_136# VGND 0.06fF
+C8 B A 0.08fF
+C9 VPWR a_56_136# 0.57fF
+C10 B X 0.02fF
+C11 A a_56_136# 0.17fF
+C12 a_56_136# X 0.26fF
+C13 VPB VPWR 0.04fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VGND B 0.11fF
+C1 X VGND 0.16fF
+C2 VPWR A 0.05fF
+C3 VGND a_63_368# 0.27fF
+C4 A B 0.10fF
+C5 X A 0.02fF
+C6 a_63_368# A 0.28fF
+C7 VPWR B 0.01fF
+C8 X VPWR 0.18fF
+C9 VPB VPWR 0.04fF
+C10 VPWR a_63_368# 0.29fF
+C11 a_63_368# B 0.14fF
+C12 X a_63_368# 0.33fF
+C13 a_152_368# a_63_368# 0.03fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_2/latch_diff_0/nD vss
++ Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in CLK DFlipFlop_0/Q vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ DFlipFlop_3/latch_diff_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/nD DFlipFlop_2/latch_diff_0/m1_657_280# CLK_5 Q1_shift
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D DFlipFlop_1/D nQ0 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/latch_diff_1/nD Q0 DFlipFlop_0/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_0/latch_diff_0/nD DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/D
++ DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_152_368# sky130_fd_sc_hs__and2_1_1/a_56_136#
++ DFlipFlop_3/nQ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 nCLK DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ nCLK DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vdd vss DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ CLK DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 sky130_fd_sc_hs__and2_1_1/a_56_136# vdd 0.04fF
+C1 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C2 nQ0 nCLK 0.09fF
+C3 Q1_shift vdd 0.10fF
+C4 Q1 DFlipFlop_1/D 0.03fF
+C5 Q0 DFlipFlop_1/D 0.07fF
+C6 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
+C7 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C8 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
+C9 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C10 Q1 Q0 9.65fF
+C11 DFlipFlop_2/D vdd 0.07fF
+C12 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C13 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C14 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C15 DFlipFlop_1/D nCLK 0.14fF
+C16 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
+C17 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C18 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C19 Q1 nCLK -0.01fF
+C20 Q0 nCLK 0.20fF
+C21 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
+C22 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C23 DFlipFlop_3/nQ Q1_shift 0.04fF
+C24 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C25 nQ0 vdd 0.11fF
+C26 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C27 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C28 Q1 DFlipFlop_0/D 0.13fF
+C29 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C30 DFlipFlop_0/D Q0 0.39fF
+C31 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C32 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C33 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C34 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C35 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK 0.14fF
+C36 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C37 Q1 DFlipFlop_0/Q 0.13fF
+C38 Q0 DFlipFlop_0/Q 0.21fF
+C39 DFlipFlop_1/D vdd 0.25fF
+C40 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C41 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
+C42 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.08fF
+C43 Q1 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C44 Q1 vdd 9.49fF
+C45 Q0 vdd 5.33fF
+C46 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C47 DFlipFlop_0/Q nCLK 0.11fF
+C48 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
+C49 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_1/D 0.03fF
+C50 Q1 DFlipFlop_2/nQ 0.31fF
+C51 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C52 nCLK vdd 0.34fF
+C53 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C54 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C55 sky130_fd_sc_hs__xor2_1_0/a_355_368# vdd 0.03fF
+C56 Q1 DFlipFlop_3/nQ 0.10fF
+C57 CLK nQ2 0.17fF
+C58 sky130_fd_sc_hs__and2_1_1/a_56_136# CLK 0.06fF
+C59 DFlipFlop_0/D vdd 0.19fF
+C60 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C61 nCLK DFlipFlop_2/nQ 0.09fF
+C62 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C63 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C64 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C65 Q0 sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.26fF
+C66 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C67 DFlipFlop_3/nQ nCLK 0.02fF
+C68 DFlipFlop_2/D CLK 0.14fF
+C69 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C70 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C71 CLK_5 vdd 0.15fF
+C72 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C73 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C74 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
+C75 nQ0 CLK 0.19fF
+C76 Q1 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C77 DFlipFlop_2/nQ vdd 0.02fF
+C78 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C79 DFlipFlop_0/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C80 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C81 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
+C82 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
+C83 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C84 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C85 DFlipFlop_3/nQ vdd 0.02fF
+C86 nQ0 DFlipFlop_1/latch_diff_0/D 0.09fF
+C87 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C88 Q1 DFlipFlop_3/latch_diff_1/D 0.79fF
+C89 nQ0 DFlipFlop_1/latch_diff_0/nD 0.08fF
+C90 CLK DFlipFlop_1/D 0.21fF
+C91 sky130_fd_sc_hs__and2_1_1/a_143_136# CLK 0.03fF
+C92 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C93 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
+C94 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C95 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
+C96 Q1 CLK -0.10fF
+C97 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C98 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C99 Q0 CLK 0.08fF
+C100 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C101 nQ0 DFlipFlop_1/latch_diff_0/m1_657_280# 0.25fF
+C102 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
+C103 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C104 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
+C105 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C106 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C107 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
+C108 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
+C109 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C110 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C111 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C112 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C113 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C114 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C115 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C116 Q1 DFlipFlop_0/latch_diff_0/D 0.15fF
+C117 nQ0 nQ2 0.03fF
+C118 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C119 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C120 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C121 DFlipFlop_2/latch_diff_0/D nCLK 0.11fF
+C122 DFlipFlop_0/Q CLK 0.08fF
+C123 DFlipFlop_3/latch_diff_1/nD nCLK 0.09fF
+C124 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C125 CLK vdd 0.41fF
+C126 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C127 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C128 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C129 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C130 Q1 nQ2 0.07fF
+C131 Q0 nQ2 0.23fF
+C132 Q1 Q1_shift 0.36fF
+C133 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C134 CLK DFlipFlop_2/nQ 0.13fF
+C135 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C136 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C137 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C138 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
+C139 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C140 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C141 Q1 DFlipFlop_2/D 0.10fF
+C142 CLK DFlipFlop_3/nQ 0.01fF
+C143 nQ2 nCLK 0.10fF
+C144 DFlipFlop_2/D Q0 0.25fF
+C145 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C146 nQ0 DFlipFlop_1/D 0.12fF
+C147 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C148 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C149 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C150 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
+C151 Q1 nQ0 0.06fF
+C152 nQ0 Q0 0.33fF
+C153 DFlipFlop_2/D nCLK 0.41fF
+C154 DFlipFlop_0/Q nQ2 0.09fF
+C155 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C156 nQ2 vdd 0.04fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/nQ vss 0.52fF
+C164 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.64fF
+C170 Q1 vss 8.55fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C172 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C173 Q0 vss 0.53fF
+C174 nQ0 vss 3.42fF
+C175 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C176 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C177 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C178 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C179 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C180 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.58fF
+C181 DFlipFlop_1/D vss 3.72fF
+C182 DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C183 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C184 DFlipFlop_2/nQ vss 0.50fF
+C185 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C186 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C187 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C188 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C190 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C191 DFlipFlop_2/D vss 5.34fF
+C192 DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C193 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C194 nCLK vss 0.89fF
+C195 DFlipFlop_0/Q vss -0.94fF
+C196 nQ2 vss 2.05fF
+C197 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C198 CLK vss 0.07fF
+C199 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C200 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 vdd vss 144.09fF
+C206 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt mux2to4 vss out_b_1 vdd select_0 select_0_neg out_a_0 out_a_1 out_b_0 in_a
++ in_b
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_b vss out_b_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_3 in_b vss out_b_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 select_0 out_a_1 0.18fF
+C1 vdd out_a_1 0.06fF
+C2 vdd select_0 0.02fF
+C3 select_0_neg in_a 0.22fF
+C4 out_b_0 in_a 0.11fF
+C5 out_b_0 select_0_neg -0.13fF
+C6 in_b select_0_neg 0.10fF
+C7 in_b out_b_0 0.08fF
+C8 out_a_0 in_a 0.08fF
+C9 in_b out_b_1 0.08fF
+C10 out_a_0 select_0_neg 0.05fF
+C11 out_a_1 in_a 0.08fF
+C12 out_a_1 select_0_neg 0.12fF
+C13 out_b_0 out_a_1 0.88fF
+C14 select_0 in_a 0.31fF
+C15 select_0 select_0_neg 0.49fF
+C16 select_0 out_b_0 0.03fF
+C17 vdd in_a 0.02fF
+C18 in_b out_a_1 0.08fF
+C19 vdd select_0_neg 0.02fF
+C20 vdd out_b_0 0.06fF
+C21 in_b select_0 0.24fF
+C22 out_b_1 select_0 0.14fF
+C23 vdd in_b 0.02fF
+C24 vdd out_b_1 0.06fF
+C25 vdd out_a_0 0.06fF
+C26 out_b_1 vss 0.99fF
+C27 in_b vss 2.00fF
+C28 out_b_0 vss 0.93fF
+C29 out_a_1 vss 0.22fF
+C30 vdd vss 9.53fF
+C31 in_a vss 2.00fF
+C32 out_a_0 vss 0.99fF
+C33 select_0_neg vss 2.56fF
+C34 select_0 vss 2.23fF
+.ends
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X a_304_74# a_443_74# a_524_368#
++ a_27_112#
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 a_524_368# a_27_112# 0.06fF
+C1 A1 A0 0.31fF
+C2 S A1 0.10fF
+C3 VGND A0 0.02fF
+C4 VGND S 0.07fF
+C5 a_304_74# A0 0.23fF
+C6 S a_304_74# 0.18fF
+C7 VPWR S 0.05fF
+C8 a_27_112# A0 0.07fF
+C9 S a_27_112# 0.22fF
+C10 VGND A1 0.09fF
+C11 X A1 0.02fF
+C12 a_304_74# A1 0.69fF
+C13 VGND X 0.11fF
+C14 VGND a_304_74# 0.58fF
+C15 X a_304_74# 0.29fF
+C16 VPWR A1 0.01fF
+C17 VGND VPWR 0.02fF
+C18 a_223_368# a_304_74# 0.05fF
+C19 a_443_74# A1 0.07fF
+C20 a_304_74# a_226_74# 0.08fF
+C21 VPWR X 0.28fF
+C22 VPWR VPB 0.06fF
+C23 VPWR a_304_74# 0.13fF
+C24 a_27_112# A1 0.18fF
+C25 VGND a_27_112# 0.18fF
+C26 a_443_74# a_304_74# 0.12fF
+C27 X a_27_112# 0.08fF
+C28 a_27_112# VPB 0.01fF
+C29 a_304_74# a_27_112# 0.58fF
+C30 a_223_368# a_27_112# 0.09fF
+C31 S A0 0.04fF
+C32 VPWR a_27_112# 0.99fF
+C33 VGND VNB 0.88fF
+C34 X VNB 0.25fF
+C35 VPWR VNB 0.89fF
+C36 A1 VNB 0.37fF
+C37 A0 VNB 0.23fF
+C38 S VNB 0.34fF
+C39 VPB VNB 0.87fF
+C40 a_304_74# VNB 0.36fF
+C41 a_27_112# VNB 0.65fF
+.ends
+
+.subckt prescaler_23 nCLK vss DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_2/latch_diff_0/nD
++ vdd DFlipFlop_2/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out CLK_23 DFlipFlop_2/latch_diff_0/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_0/latch_diff_0/nD MC DFlipFlop_2/latch_diff_0/D
++ Q2
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1_0/a_304_74# sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__mux2_1_0/a_524_368#
++ sky130_fd_sc_hs__mux2_1_0/a_27_112# sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ nCLK DFlipFlop_0/latch_diff_0/nD
++ Q1 DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_0/D
++ CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK_23 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q2 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ CLK DFlipFlop_2/latch_diff_0/nD
++ Q2_d DFlipFlop_2/latch_diff_1/nD Q2 DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/latch_diff_0/D
++ nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1_0/a_143_136# sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1_1/a_152_368#
++ sky130_fd_sc_hs__or2_1_1/a_63_368# sky130_fd_sc_hs__or2_1
+C0 nCLK vdd -0.55fF
+C1 DFlipFlop_2/nQ CLK 0.02fF
+C2 CLK sky130_fd_sc_hs__or2_1_0/X 0.01fF
+C3 Q1 MC 0.29fF
+C4 sky130_fd_sc_hs__mux2_1_0/a_27_112# MC 0.24fF
+C5 CLK DFlipFlop_1/D 0.40fF
+C6 DFlipFlop_2/latch_diff_1/D Q2 0.13fF
+C7 sky130_fd_sc_hs__and2_1_0/a_56_136# CLK 0.08fF
+C8 DFlipFlop_1/latch_diff_0/nD CLK 0.09fF
+C9 DFlipFlop_2/latch_diff_1/D CLK 0.09fF
+C10 Q2 sky130_fd_sc_hs__or2_1_1/X 0.24fF
+C11 DFlipFlop_2/nQ nCLK 0.02fF
+C12 nCLK sky130_fd_sc_hs__or2_1_0/X 0.06fF
+C13 nCLK DFlipFlop_1/D 0.16fF
+C14 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.29fF
+C15 sky130_fd_sc_hs__or2_1_1/a_63_368# Q2 0.09fF
+C16 nCLK DFlipFlop_2/latch_diff_1/D 0.16fF
+C17 DFlipFlop_2/latch_diff_1/m1_657_280# CLK 0.33fF
+C18 sky130_fd_sc_hs__mux2_1_0/a_443_74# nCLK_23 0.09fF
+C19 vdd nCLK_23 3.27fF
+C20 nCLK sky130_fd_sc_hs__or2_1_0/a_152_368# 0.01fF
+C21 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.31fF
+C22 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.31fF
+C23 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.09fF
+C24 nCLK_23 sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C25 CLK Q2 0.29fF
+C26 DFlipFlop_1/latch_diff_1/D CLK 0.18fF
+C27 nCLK_23 DFlipFlop_1/D 0.02fF
+C28 sky130_fd_sc_hs__and2_1_0/a_56_136# nCLK_23 0.14fF
+C29 vdd Q1 0.07fF
+C30 nCLK_23 DFlipFlop_0/latch_diff_0/nD 0.12fF
+C31 sky130_fd_sc_hs__mux2_1_0/a_524_368# nCLK_23 0.04fF
+C32 nCLK Q2 0.29fF
+C33 nCLK DFlipFlop_1/latch_diff_1/D 0.09fF
+C34 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C35 nCLK_23 sky130_fd_sc_hs__or2_1_1/X 0.26fF
+C36 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C37 Q1 sky130_fd_sc_hs__or2_1_0/X 0.06fF
+C38 vdd MC 0.88fF
+C39 DFlipFlop_1/latch_diff_1/nD CLK 0.11fF
+C40 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C41 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C42 DFlipFlop_2/latch_diff_0/D Q2 0.30fF
+C43 sky130_fd_sc_hs__or2_1_0/X MC 0.09fF
+C44 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.08fF
+C45 DFlipFlop_2/latch_diff_0/D CLK 0.13fF
+C46 nCLK DFlipFlop_1/latch_diff_1/nD 0.18fF
+C47 Q1 sky130_fd_sc_hs__or2_1_0/a_152_368# 0.01fF
+C48 nCLK_23 Q2 0.03fF
+C49 nCLK_23 CLK 0.22fF
+C50 sky130_fd_sc_hs__or2_1_1/X MC 0.02fF
+C51 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C52 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.16fF
+C53 nCLK_23 DFlipFlop_0/latch_diff_1/nD 0.02fF
+C54 DFlipFlop_0/latch_diff_1/D CLK 0.04fF
+C55 nCLK nCLK_23 0.11fF
+C56 Q1 CLK -0.07fF
+C57 DFlipFlop_0/nQ CLK 0.15fF
+C58 CLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.05fF
+C59 Q1 DFlipFlop_0/latch_diff_1/nD 0.03fF
+C60 vdd Q2_d 0.02fF
+C61 Q2 MC 0.18fF
+C62 DFlipFlop_0/latch_diff_1/m1_657_280# Q1 0.06fF
+C63 nCLK Q1 -0.02fF
+C64 nCLK DFlipFlop_0/nQ 0.11fF
+C65 DFlipFlop_2/latch_diff_1/nD Q2 0.17fF
+C66 nCLK_23 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C67 vdd sky130_fd_sc_hs__or2_1_0/X 0.03fF
+C68 CLK MC 0.08fF
+C69 vdd DFlipFlop_1/D 0.07fF
+C70 DFlipFlop_2/latch_diff_1/nD CLK 0.19fF
+C71 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.06fF
+C72 nCLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.31fF
+C73 nCLK MC 0.01fF
+C74 sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__or2_1_1/X 0.03fF
+C75 DFlipFlop_0/latch_diff_1/D nCLK_23 0.05fF
+C76 DFlipFlop_2/latch_diff_1/D Q2_d 0.03fF
+C77 sky130_fd_sc_hs__or2_1_0/X DFlipFlop_1/D 0.35fF
+C78 vdd sky130_fd_sc_hs__or2_1_1/X 0.03fF
+C79 DFlipFlop_2/latch_diff_1/nD nCLK 0.12fF
+C80 nCLK_23 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.49fF
+C81 sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C82 Q2_d sky130_fd_sc_hs__or2_1_1/X 0.03fF
+C83 nCLK DFlipFlop_2/latch_diff_0/nD 0.09fF
+C84 nCLK_23 Q1 0.02fF
+C85 Q2 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.38fF
+C86 nCLK_23 DFlipFlop_0/nQ 0.05fF
+C87 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.04fF
+C88 sky130_fd_sc_hs__mux2_1_0/a_27_112# nCLK_23 0.07fF
+C89 DFlipFlop_2/latch_diff_1/m1_657_280# Q2_d 0.03fF
+C90 nCLK DFlipFlop_1/latch_diff_0/D 0.02fF
+C91 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.10fF
+C92 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.02fF
+C93 nCLK_23 MC 4.46fF
+C94 vdd Q2 1.63fF
+C95 DFlipFlop_0/nQ Q1 -0.02fF
+C96 Q2_d Q2 0.66fF
+C97 vdd CLK 0.34fF
+C98 nCLK sky130_fd_sc_hs__or2_1_0/a_63_368# 0.05fF
+C99 CLK_23 vdd 0.16fF
+C100 DFlipFlop_2/nQ Q2 0.13fF
+C101 sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C102 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C103 sky130_fd_sc_hs__or2_1_0/X vss 0.92fF
+C104 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.39fF
+C105 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C106 Q2_d vss -0.22fF
+C107 DFlipFlop_2/nQ vss 0.48fF
+C108 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C109 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C110 DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C111 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C112 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C113 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.63fF
+C114 Q2 vss 1.35fF
+C115 DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C116 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.72fF
+C117 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C118 DFlipFlop_1/latch_diff_1/D vss -1.72fF
+C119 DFlipFlop_1/latch_diff_1/nD vss 0.58fF
+C120 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C121 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C122 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C123 DFlipFlop_1/D vss 2.98fF
+C124 DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C125 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C126 nCLK vss -1.56fF
+C127 Q1 vss 0.50fF
+C128 DFlipFlop_0/nQ vss 0.48fF
+C129 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C130 CLK vss -0.69fF
+C131 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C132 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C133 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C134 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C135 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C136 nCLK_23 vss -0.65fF
+C137 vdd vss 113.67fF
+C138 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C139 CLK_23 vss -0.57fF
+C140 sky130_fd_sc_hs__or2_1_1/X vss -0.35fF
+C141 MC vss 2.09fF
+C142 sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.41fF
+C143 sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.69fF
+.ends
+
+.subckt freq_div clk_0 vss n_clk_0 vdd prescaler_23_0/Q2 s_0 s_1_n s_1 prescaler_23_0/nCLK_23
++ prescaler_23_0/MC clk_d prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n
++ clk_pre div_by_5_0/DFlipFlop_2/latch_diff_0/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out div_by_5_0/Q1 div_by_5_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD clk_2 in_a in_b clk_5 prescaler_23_0/DFlipFlop_2/latch_diff_0/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD div_by_5_0/DFlipFlop_2/latch_diff_1/D
+Xdiv_by_2_0 vdd vss div_by_2_0/nout_div clk_2 div_by_2_0/nCLK_2 div_by_2_0/o1 div_by_2_0/o2
++ clk_out_mux21 div_by_2_0/out_div div_by_2
+Xmux2to1_0 vss s_0_n clk_pre clk_5 s_0 vdd clk_out_mux21 mux2to1
+Xinverter_min_x4_0 inverter_min_x4_0/in vss clk_d vdd inverter_min_x4
+Xmux2to1_1 vss s_1_n clk_d clk_2 s_1 vdd out mux2to1
+Xinverter_min_x2_0 clk_out_mux21 inverter_min_x4_0/in vss vdd inverter_min_x2
+Xinverter_min_x2_1 s_1 s_1_n vss vdd inverter_min_x2
+Xinverter_min_x2_2 s_0 s_0_n vss vdd inverter_min_x2
+Xdiv_by_5_0 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ vss div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in clk_1
++ div_by_5_0/DFlipFlop_0/Q vdd div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# clk_5 div_by_5_0/Q1_shift div_by_5_0/nQ2
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_by_5_0/DFlipFlop_1/D div_by_5_0/nQ0 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/Q0 div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xmux2to4_0 vss n_clk_1 vdd s_0 s_0_n clk_0 clk_1 n_clk_0 in_a in_b mux2to4
+Xprescaler_23_0 n_clk_0 vss prescaler_23_0/DFlipFlop_0/latch_diff_1/nD prescaler_23_0/nCLK_23
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vdd prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ clk_pre prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# prescaler_23_0/DFlipFlop_0/latch_diff_0/D
++ clk_0 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280#
++ prescaler_23_0/DFlipFlop_0/latch_diff_1/D prescaler_23_0/DFlipFlop_0/latch_diff_0/nD
++ prescaler_23_0/MC prescaler_23_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/Q2 prescaler_23
+C0 s_0 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.05fF
+C1 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0_n 0.04fF
+C2 clk_0 vdd 0.63fF
+C3 s_0_n div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C4 s_0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out -0.13fF
+C5 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD 0.09fF
+C6 vdd s_0_n 2.53fF
+C7 div_by_5_0/DFlipFlop_0/D s_0_n 0.05fF
+C8 div_by_5_0/Q0 s_0 0.02fF
+C9 s_0 div_by_5_0/DFlipFlop_2/D 0.03fF
+C10 s_0 clk_out_mux21 0.68fF
+C11 n_clk_0 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C12 out s_1 0.39fF
+C13 s_0 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.05fF
+C14 s_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.19fF
+C15 s_1_n clk_2 0.59fF
+C16 s_0 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.12fF
+C17 s_0 clk_pre 0.21fF
+C18 vdd n_clk_1 0.13fF
+C19 div_by_5_0/DFlipFlop_0/D n_clk_1 0.21fF
+C20 in_a s_0 0.30fF
+C21 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.08fF
+C22 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C23 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/D 0.09fF
+C24 clk_5 s_0_n 0.56fF
+C25 n_clk_0 clk_1 -0.03fF
+C26 s_0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.02fF
+C27 clk_pre clk_out_mux21 1.19fF
+C28 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_clk_1 0.14fF
+C29 s_0 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.36fF
+C30 clk_d inverter_min_x4_0/in 0.11fF
+C31 s_0 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.30fF
+C32 div_by_5_0/Q1_shift s_0_n 0.04fF
+C33 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/D 0.13fF
+C34 s_0 clk_1 1.36fF
+C35 s_0 div_by_5_0/DFlipFlop_1/D 0.03fF
+C36 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.05fF
+C37 clk_1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
+C38 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_0 0.16fF
+C39 s_0 div_by_5_0/nQ0 0.05fF
+C40 s_0 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.10fF
+C41 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.24fF
+C42 n_clk_0 s_0_n 0.31fF
+C43 s_0 div_by_5_0/nQ2 0.05fF
+C44 clk_5 vdd 0.04fF
+C45 div_by_5_0/DFlipFlop_3/nQ s_0 0.02fF
+C46 div_by_5_0/DFlipFlop_2/nQ s_0_n 0.04fF
+C47 s_0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.12fF
+C48 s_0_n div_by_5_0/DFlipFlop_0/Q 0.24fF
+C49 out clk_2 0.05fF
+C50 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.11fF
+C51 s_0 s_0_n 7.76fF
+C52 s_0_n div_by_5_0/Q1 0.21fF
+C53 div_by_5_0/DFlipFlop_3/latch_diff_1/nD s_0_n 0.04fF
+C54 n_clk_0 prescaler_23_0/nCLK_23 0.16fF
+C55 s_0 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.12fF
+C56 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.11fF
+C57 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out s_0_n -0.01fF
+C58 in_a clk_1 0.05fF
+C59 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_clk_1 0.06fF
+C60 div_by_5_0/Q0 s_0_n 0.24fF
+C61 s_0_n div_by_5_0/DFlipFlop_2/D 0.05fF
+C62 vdd clk_2 0.02fF
+C63 n_clk_0 vdd 0.25fF
+C64 clk_out_mux21 s_0_n 0.45fF
+C65 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD 0.13fF
+C66 div_by_5_0/Q1_shift div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# -0.02fF
+C67 s_0 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.05fF
+C68 n_clk_1 div_by_5_0/Q1 0.15fF
+C69 div_by_5_0/DFlipFlop_1/latch_diff_1/D s_0_n 0.04fF
+C70 s_0 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.02fF
+C71 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out s_0_n -0.29fF
+C72 div_by_5_0/DFlipFlop_2/latch_diff_0/nD s_0_n 0.20fF
+C73 s_0 vdd 3.67fF
+C74 vdd div_by_5_0/Q1 -0.02fF
+C75 div_by_5_0/DFlipFlop_0/D s_0 0.03fF
+C76 div_by_5_0/DFlipFlop_0/D div_by_5_0/Q1 -0.02fF
+C77 clk_5 div_by_5_0/Q1_shift 0.04fF
+C78 div_by_5_0/Q0 n_clk_1 0.01fF
+C79 in_b s_0_n 0.48fF
+C80 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.11fF
+C81 div_by_5_0/Q0 vdd 0.05fF
+C82 clk_pre prescaler_23_0/nCLK_23 0.03fF
+C83 div_by_5_0/DFlipFlop_1/latch_diff_1/nD s_0_n 0.24fF
+C84 vdd clk_out_mux21 0.14fF
+C85 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/Q1 -0.06fF
+C86 clk_d s_1 0.22fF
+C87 clk_d vdd 0.23fF
+C88 prescaler_23_0/DFlipFlop_0/latch_diff_1/D clk_0 0.13fF
+C89 out s_1_n 0.33fF
+C90 s_0_n div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.37fF
+C91 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out s_0_n 0.31fF
+C92 clk_1 s_0_n 4.82fF
+C93 in_b n_clk_1 0.05fF
+C94 clk_pre vdd 0.17fF
+C95 div_by_5_0/DFlipFlop_1/D s_0_n 0.19fF
+C96 s_0 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.02fF
+C97 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.08fF
+C98 div_by_5_0/DFlipFlop_0/latch_diff_1/D s_0_n 0.04fF
+C99 vdd inverter_min_x4_0/in 0.09fF
+C100 div_by_5_0/nQ0 s_0_n 0.05fF
+C101 div_by_5_0/DFlipFlop_3/latch_diff_0/D s_0_n 0.17fF
+C102 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD 0.09fF
+C103 s_1_n s_1 0.39fF
+C104 s_0_n div_by_5_0/nQ2 0.05fF
+C105 div_by_5_0/Q1_shift s_0 0.05fF
+C106 div_by_5_0/DFlipFlop_3/nQ s_0_n 0.24fF
+C107 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.20fF
+C108 clk_5 clk_out_mux21 0.05fF
+C109 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_clk_1 0.03fF
+C110 clk_1 vdd 0.16fF
+C111 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.08fF
+C112 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.02fF
+C113 div_by_5_0/DFlipFlop_0/D clk_1 0.14fF
+C114 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.20fF
+C115 clk_0 prescaler_23_0/nCLK_23 0.16fF
+C116 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# s_0_n 0.05fF
+C117 s_0 div_by_5_0/DFlipFlop_2/nQ 0.05fF
+C118 s_0 div_by_5_0/DFlipFlop_0/Q 0.02fF
+C119 s_0 div_by_5_0/Q1 0.04fF
+C120 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C121 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C122 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C123 prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C124 prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C125 prescaler_23_0/Q2_d vss -0.69fF
+C126 prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C127 prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C128 prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C129 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C130 prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C131 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C132 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C133 prescaler_23_0/Q2 vss 0.55fF
+C134 prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C135 prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C136 prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C137 prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C138 prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C139 prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C140 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C141 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C142 prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C143 prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C144 prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C145 n_clk_0 vss -5.35fF
+C146 prescaler_23_0/Q1 vss 0.07fF
+C147 prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C148 prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C149 clk_0 vss 0.66fF
+C150 prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C151 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C152 prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C153 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C155 prescaler_23_0/nCLK_23 vss -1.02fF
+C156 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C157 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C158 prescaler_23_0/MC vss 1.07fF
+C159 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C160 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C161 in_b vss 2.02fF
+C162 in_a vss 2.01fF
+C163 s_0_n vss -2.51fF
+C164 s_0 vss 5.84fF
+C165 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C166 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C167 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C168 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C169 div_by_5_0/Q1_shift vss -0.36fF
+C170 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C171 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C172 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C174 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C177 div_by_5_0/Q1 vss 4.35fF
+C178 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C179 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C180 div_by_5_0/Q0 vss 0.29fF
+C181 div_by_5_0/nQ0 vss 0.99fF
+C182 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C183 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C184 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C185 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C186 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C187 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C188 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C189 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C190 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C191 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C192 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C193 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C194 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C195 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C196 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C197 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C198 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C199 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C200 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C201 n_clk_1 vss -0.55fF
+C202 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C203 div_by_5_0/nQ2 vss 1.38fF
+C204 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C205 clk_1 vss -1.34fF
+C206 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C207 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C208 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C209 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C210 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C211 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C212 vdd vss 344.01fF
+C213 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C214 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C215 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C216 out vss 0.93fF
+C217 clk_d vss 0.78fF
+C218 s_1_n vss 1.22fF
+C219 s_1 vss 2.97fF
+C220 inverter_min_x4_0/in vss 2.77fF
+C221 clk_out_mux21 vss 5.29fF
+C222 clk_pre vss 1.30fF
+C223 clk_2 vss 3.46fF
+C224 div_by_2_0/o1 vss 2.20fF
+C225 div_by_2_0/nCLK_2 vss 1.04fF
+C226 div_by_2_0/o2 vss 2.08fF
+C227 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C228 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C229 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C230 div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C231 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C232 div_by_2_0/out_div vss -0.80fF
+C233 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C234 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C235 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C236 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C237 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C238 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C239 div_by_2_0/nout_div vss 2.62fF
+C240 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n257_n777# a_n221_n600# 0.25fF
+C1 a_n221_n600# a_n129_n600# 7.87fF
+C2 a_n257_n777# a_n129_n600# 0.29fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n221_n300# a_n129_n300# 4.05fF
+C1 a_n221_n300# a_n257_n404# 0.21fF
+C2 a_n129_n300# a_n257_n404# 0.30fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out vdd in vss
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 vdd in 0.02fF
+C1 in a_678_n100# 0.81fF
+C2 vdd a_3996_n100# 3.68fF
+C3 a_3996_n100# a_678_n100# 6.52fF
+C4 vdd a_678_n100# 0.08fF
+C5 a_3996_n100# out 55.19fF
+C6 vdd out 47.17fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n238# a_15_n150# 0.02fF
+C1 a_n73_n150# a_15_n150# 0.51fF
+C2 a_n73_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n33_181# 0.01fF
+C1 w_n211_n369# a_n73_n150# 0.20fF
+C2 a_n33_181# a_n73_n150# 0.01fF
+C3 a_n33_181# w_n211_n369# 0.05fF
+C4 a_15_n150# a_n73_n150# 0.51fF
+C5 a_15_n150# w_n211_n369# 0.20fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_159_n150# a_447_n150# 0.10fF
+C1 a_n129_n150# a_255_n150# 0.07fF
+C2 a_n129_n150# a_n465_172# 0.10fF
+C3 a_n225_n150# a_n321_n150# 0.43fF
+C4 a_n321_n150# a_n509_n150# 0.16fF
+C5 a_159_n150# a_n33_n150# 0.16fF
+C6 a_n225_n150# a_n129_n150# 0.43fF
+C7 a_n129_n150# a_n509_n150# 0.07fF
+C8 a_351_n150# a_447_n150# 0.43fF
+C9 a_447_n150# a_63_n150# 0.07fF
+C10 a_351_n150# a_n33_n150# 0.07fF
+C11 a_63_n150# a_n33_n150# 0.43fF
+C12 a_n465_172# a_n417_n150# 0.10fF
+C13 a_n225_n150# a_n417_n150# 0.16fF
+C14 a_n509_n150# a_n417_n150# 0.43fF
+C15 a_n321_n150# a_n33_n150# 0.10fF
+C16 a_n129_n150# a_n33_n150# 0.43fF
+C17 a_159_n150# a_351_n150# 0.16fF
+C18 a_159_n150# a_63_n150# 0.43fF
+C19 a_n33_n150# a_n417_n150# 0.07fF
+C20 a_351_n150# a_63_n150# 0.10fF
+C21 a_n465_172# a_255_n150# 0.10fF
+C22 a_159_n150# a_n129_n150# 0.10fF
+C23 a_n225_n150# a_n465_172# 0.10fF
+C24 a_n509_n150# a_n465_172# 0.01fF
+C25 a_n225_n150# a_n509_n150# 0.10fF
+C26 a_n321_n150# a_63_n150# 0.07fF
+C27 a_n129_n150# a_63_n150# 0.16fF
+C28 a_n129_n150# a_n321_n150# 0.16fF
+C29 a_447_n150# a_255_n150# 0.16fF
+C30 a_447_n150# a_n465_172# 0.01fF
+C31 a_n33_n150# a_255_n150# 0.10fF
+C32 a_n33_n150# a_n465_172# 0.10fF
+C33 a_n225_n150# a_n33_n150# 0.16fF
+C34 a_n321_n150# a_n417_n150# 0.43fF
+C35 a_n129_n150# a_n417_n150# 0.10fF
+C36 a_159_n150# a_255_n150# 0.43fF
+C37 a_159_n150# a_n465_172# 0.10fF
+C38 a_159_n150# a_n225_n150# 0.07fF
+C39 a_351_n150# a_255_n150# 0.43fF
+C40 a_351_n150# a_n465_172# 0.10fF
+C41 a_63_n150# a_255_n150# 0.16fF
+C42 a_63_n150# a_n465_172# 0.10fF
+C43 a_n225_n150# a_63_n150# 0.10fF
+C44 a_n321_n150# a_n465_172# 0.10fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n150# a_63_n150# 0.43fF
+C1 w_n647_n369# a_n417_n150# 0.07fF
+C2 a_159_n150# a_63_n150# 0.43fF
+C3 w_n647_n369# a_n33_n150# 0.02fF
+C4 w_n647_n369# a_159_n150# 0.04fF
+C5 a_n509_n150# a_n417_n150# 0.43fF
+C6 a_n225_n150# a_n321_n150# 0.43fF
+C7 a_351_n150# a_n465_n247# 0.08fF
+C8 a_n225_n150# a_n465_n247# 0.08fF
+C9 a_n225_n150# a_n129_n150# 0.43fF
+C10 w_n647_n369# a_63_n150# 0.02fF
+C11 a_255_n150# a_n129_n150# 0.07fF
+C12 a_255_n150# a_n465_n247# 0.08fF
+C13 w_n647_n369# a_n509_n150# 0.14fF
+C14 a_n33_n150# a_351_n150# 0.07fF
+C15 a_159_n150# a_351_n150# 0.16fF
+C16 a_n321_n150# a_n465_n247# 0.08fF
+C17 a_n129_n150# a_n321_n150# 0.16fF
+C18 a_n225_n150# a_n417_n150# 0.16fF
+C19 a_159_n150# a_447_n150# 0.10fF
+C20 a_n225_n150# a_n33_n150# 0.16fF
+C21 a_n225_n150# a_159_n150# 0.07fF
+C22 a_n129_n150# a_n465_n247# 0.08fF
+C23 a_255_n150# a_n33_n150# 0.10fF
+C24 a_255_n150# a_159_n150# 0.43fF
+C25 a_63_n150# a_351_n150# 0.10fF
+C26 a_63_n150# a_447_n150# 0.07fF
+C27 a_n417_n150# a_n321_n150# 0.43fF
+C28 w_n647_n369# a_351_n150# 0.07fF
+C29 w_n647_n369# a_447_n150# 0.14fF
+C30 a_n33_n150# a_n321_n150# 0.10fF
+C31 a_n225_n150# a_63_n150# 0.10fF
+C32 a_n129_n150# a_n417_n150# 0.10fF
+C33 a_n417_n150# a_n465_n247# 0.08fF
+C34 w_n647_n369# a_n225_n150# 0.04fF
+C35 a_255_n150# a_63_n150# 0.16fF
+C36 a_n129_n150# a_n33_n150# 0.43fF
+C37 a_n33_n150# a_n465_n247# 0.08fF
+C38 w_n647_n369# a_255_n150# 0.05fF
+C39 a_n129_n150# a_159_n150# 0.10fF
+C40 a_159_n150# a_n465_n247# 0.08fF
+C41 a_n225_n150# a_n509_n150# 0.10fF
+C42 a_63_n150# a_n321_n150# 0.07fF
+C43 w_n647_n369# a_n321_n150# 0.05fF
+C44 a_n129_n150# a_63_n150# 0.16fF
+C45 a_63_n150# a_n465_n247# 0.08fF
+C46 a_n417_n150# a_n33_n150# 0.07fF
+C47 w_n647_n369# a_n129_n150# 0.02fF
+C48 w_n647_n369# a_n465_n247# 0.47fF
+C49 a_n509_n150# a_n321_n150# 0.16fF
+C50 a_159_n150# a_n33_n150# 0.16fF
+C51 a_351_n150# a_447_n150# 0.43fF
+C52 a_n129_n150# a_n509_n150# 0.07fF
+C53 a_255_n150# a_351_n150# 0.43fF
+C54 a_255_n150# a_447_n150# 0.16fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_n33_n99# 0.02fF
+C1 a_15_n11# a_n73_n11# 0.15fF
+C2 a_15_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_20_n114# 0.20fF
+C1 a_n78_n114# w_n216_n334# 0.20fF
+C2 a_n78_n114# a_20_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vdd 0.01fF
+C1 in out 0.11fF
+C2 vbulkp vdd 0.04fF
+C3 vbulkp out 0.08fF
+C4 in vss 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 vss out vdd inverter_csvco_0/vss
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 inverter_csvco_0/vdd vdd 1.89fF
+C1 out in 0.06fF
+C2 in inverter_csvco_0/vss 0.01fF
+C3 out cap_vco_0/t 0.70fF
+C4 out inverter_csvco_0/vss 0.03fF
+C5 in inverter_csvco_0/vdd 0.01fF
+C6 vctrl inverter_csvco_0/vss 0.87fF
+C7 out inverter_csvco_0/vdd 0.02fF
+C8 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C9 vbp inverter_csvco_0/vdd 0.75fF
+C10 out D0 0.09fF
+C11 D0 inverter_csvco_0/vss 0.02fF
+C12 cap_vco_0/t vdd 0.04fF
+C13 vbp vdd 1.21fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vss vdd csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 vss
++ csvco_branch_1/in vdd csvco_branch_0/inverter_csvco_0/vss csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 vss out_vco vdd csvco_branch_2/inverter_csvco_0/vss csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 vss csvco_branch_2/in vdd csvco_branch_1/inverter_csvco_0/vss csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 D0 csvco_branch_1/inverter_csvco_0/vss 0.68fF
+C1 D0 csvco_branch_0/inverter_csvco_0/vss 0.49fF
+C2 csvco_branch_1/in out_vco 0.76fF
+C3 csvco_branch_2/in out_vco 0.58fF
+C4 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
+C5 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C6 D0 vctrl 4.41fF
+C7 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
+C8 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C9 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C10 vctrl csvco_branch_2/vbp 0.06fF
+C11 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C12 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C13 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C14 vdd csvco_branch_2/vbp 1.49fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 vdd out_pad 0.10fF
+C1 o1 out_div 0.11fF
+C2 out_pad out_div 0.15fF
+C3 vdd out_div 0.17fF
+C4 vdd o1 0.09fF
+C5 vdd vss 14.54fF
+C6 in_vco vss 0.83fF
+C7 out_pad vss 0.70fF
+C8 out_div vss 3.00fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n63_n151# a_n159_n151# 0.02fF
+C1 a_n63_n151# a_33_n151# 0.02fF
+C2 a_225_n151# a_129_n151# 0.02fF
+C3 a_159_n125# a_255_n125# 0.36fF
+C4 a_n129_n125# a_159_n125# 0.08fF
+C5 a_n159_n151# a_n255_n151# 0.02fF
+C6 a_159_n125# a_n33_n125# 0.13fF
+C7 a_n129_n125# a_n317_n125# 0.13fF
+C8 a_63_n125# a_255_n125# 0.13fF
+C9 a_n317_n125# a_n33_n125# 0.08fF
+C10 a_n129_n125# a_63_n125# 0.13fF
+C11 a_n129_n125# a_n225_n125# 0.36fF
+C12 a_63_n125# a_n33_n125# 0.36fF
+C13 a_n225_n125# a_n33_n125# 0.13fF
+C14 a_159_n125# a_63_n125# 0.36fF
+C15 a_159_n125# a_n225_n125# 0.06fF
+C16 a_129_n151# a_33_n151# 0.02fF
+C17 a_n317_n125# a_63_n125# 0.06fF
+C18 a_n317_n125# a_n225_n125# 0.36fF
+C19 a_n129_n125# a_255_n125# 0.06fF
+C20 a_255_n125# a_n33_n125# 0.08fF
+C21 a_63_n125# a_n225_n125# 0.08fF
+C22 a_n129_n125# a_n33_n125# 0.36fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_63_n125# a_255_n125# 0.13fF
+C1 a_63_n125# a_n33_n125# 0.36fF
+C2 a_63_n125# a_n129_n125# 0.13fF
+C3 a_n225_n125# a_n33_n125# 0.13fF
+C4 a_n129_n125# a_n225_n125# 0.36fF
+C5 a_63_n125# a_n225_n125# 0.08fF
+C6 w_n455_n344# a_159_n125# 0.06fF
+C7 a_n63_n154# a_33_n154# 0.02fF
+C8 a_n159_n154# a_n255_n154# 0.02fF
+C9 a_n317_n125# a_n33_n125# 0.08fF
+C10 a_129_n154# a_225_n154# 0.02fF
+C11 a_n317_n125# a_n129_n125# 0.13fF
+C12 w_n455_n344# a_255_n125# 0.11fF
+C13 w_n455_n344# a_n33_n125# 0.05fF
+C14 w_n455_n344# a_n129_n125# 0.04fF
+C15 a_n317_n125# a_63_n125# 0.06fF
+C16 w_n455_n344# a_63_n125# 0.04fF
+C17 a_n317_n125# a_n225_n125# 0.36fF
+C18 w_n455_n344# a_n225_n125# 0.06fF
+C19 a_n63_n154# a_n159_n154# 0.02fF
+C20 a_159_n125# a_255_n125# 0.36fF
+C21 a_159_n125# a_n33_n125# 0.13fF
+C22 a_159_n125# a_n129_n125# 0.08fF
+C23 a_n317_n125# w_n455_n344# 0.11fF
+C24 a_63_n125# a_159_n125# 0.36fF
+C25 a_129_n154# a_33_n154# 0.02fF
+C26 a_159_n125# a_n225_n125# 0.06fF
+C27 a_n33_n125# a_255_n125# 0.08fF
+C28 a_n129_n125# a_255_n125# 0.06fF
+C29 a_n129_n125# a_n33_n125# 0.36fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 out in 0.85fF
+C1 vdd in 0.04fF
+C2 vdd out 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss vdd inverter_cp_x1_0/out inverter_cp_x1_2/in Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown vss inverter_cp_x1_0/out vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd nUp 0.14fF
+C1 nUp Up 0.20fF
+C2 vdd QA 0.02fF
+C3 vdd inverter_cp_x1_2/in 0.42fF
+C4 vdd QB 0.02fF
+C5 inverter_cp_x1_2/in Up 0.12fF
+C6 Down inverter_cp_x1_0/out 0.12fF
+C7 vdd inverter_cp_x1_0/out 0.18fF
+C8 vdd Up 0.60fF
+C9 nDown Down 0.23fF
+C10 vdd nDown 0.80fF
+C11 nDown inverter_cp_x1_0/out 0.11fF
+C12 inverter_cp_x1_2/in vss 2.01fF
+C13 QA vss 1.09fF
+C14 inverter_cp_x1_0/out vss 1.72fF
+C15 QB vss 1.09fF
+C16 vdd vss 28.20fF
+C17 nUp vss 1.32fF
+C18 Up vss 2.53fF
+C19 Down vss 1.17fF
+C20 nDown vss 2.77fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n129_n90# a_n221_n90# 0.26fF
+C1 a_63_n90# a_n221_n90# 0.06fF
+C2 a_n129_n90# a_159_n90# 0.06fF
+C3 a_n33_n90# w_n359_n309# 0.05fF
+C4 a_63_n90# a_159_n90# 0.26fF
+C5 w_n359_n309# a_n221_n90# 0.09fF
+C6 a_n33_n90# a_n221_n90# 0.09fF
+C7 a_159_n90# w_n359_n309# 0.09fF
+C8 a_159_n90# a_n33_n90# 0.09fF
+C9 a_63_n90# a_n129_n90# 0.09fF
+C10 a_n63_n116# a_n159_n207# 0.12fF
+C11 a_159_n90# a_n221_n90# 0.04fF
+C12 a_n129_n90# w_n359_n309# 0.06fF
+C13 a_n129_n90# a_n33_n90# 0.26fF
+C14 a_63_n90# w_n359_n309# 0.06fF
+C15 a_63_n90# a_n33_n90# 0.26fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_71# a_33_n71# 0.04fF
+C1 a_63_n45# a_n125_n45# 0.05fF
+C2 a_63_n45# a_n33_n45# 0.13fF
+C3 a_n125_n45# a_n33_n45# 0.13fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 out B 0.40fF
+C1 A B 0.24fF
+C2 vdd out 0.11fF
+C3 A out 0.06fF
+C4 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
+C5 vdd A 0.09fF
+C6 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out 0.08fF
+C7 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A Reset nor_pfd_2/B
+Xnor_pfd_0 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss CLK Q nor_pfd
+Xnor_pfd_1 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_3/A Reset nor_pfd
+C0 Q nor_pfd_3/A 0.98fF
+C1 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C2 Q CLK 0.04fF
+C3 vdd nor_pfd_2/A -0.01fF
+C4 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C5 vdd nor_pfd_2/B 0.02fF
+C6 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C7 Q nor_pfd_2/A 1.38fF
+C8 Q nor_pfd_2/B 2.22fF
+C9 Q Reset 0.14fF
+C10 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C11 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C12 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C13 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C14 vdd Q 0.08fF
+C15 nor_pfd_3/A Reset 0.12fF
+C16 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C17 Reset nor_pfd_2/B 0.43fF
+C18 vdd nor_pfd_3/A 0.09fF
+C19 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n33_n45# 0.13fF
+C1 a_159_n45# a_n221_n45# 0.02fF
+C2 a_159_n45# a_63_n45# 0.13fF
+C3 a_159_n45# a_n33_n45# 0.05fF
+C4 a_n221_n45# a_n129_n45# 0.13fF
+C5 a_63_n45# a_n129_n45# 0.05fF
+C6 a_n159_n173# a_n63_n71# 0.10fF
+C7 a_n129_n45# a_n33_n45# 0.13fF
+C8 a_63_n45# a_n221_n45# 0.03fF
+C9 a_159_n45# a_n129_n45# 0.03fF
+C10 a_n221_n45# a_n33_n45# 0.05fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n125_n90# a_n33_n90# 0.26fF
+C1 a_n99_n187# a_33_n187# 0.04fF
+C2 a_n125_n90# a_63_n90# 0.09fF
+C3 a_n33_n90# a_63_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n73_n45# a_15_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_15_n90# w_n211_n309# 0.09fF
+C1 a_n73_n90# w_n211_n309# 0.04fF
+C2 a_15_n90# a_n73_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# out vss vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 vdd out 0.10fF
+C1 A a_656_410# 0.04fF
+C2 a_656_410# out 0.20fF
+C3 A B 0.33fF
+C4 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C5 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C6 out sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.03fF
+C7 vdd a_656_410# 0.20fF
+C8 a_656_410# B 0.30fF
+C9 A vdd 0.05fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Reset Down Up A B
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A Reset dff_pfd_0/nor_pfd_2/B
++ dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A Reset dff_pfd_1/nor_pfd_2/B
++ dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# Reset vss vdd Up Down and_pfd
+C0 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C1 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
+C2 Up vdd 1.62fF
+C3 Up Down 0.06fF
+C4 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
+C5 dff_pfd_1/nor_pfd_2/B vdd 0.04fF
+C6 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
+C7 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C8 Down vdd 0.08fF
+C9 Reset vdd 0.02fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+
+* Top level circuit top_pll_v3
+
+Xcharge_pump_0 nswitch vss vdd nUp Down charge_pump_0/w_2544_775# vco_vctrl pswitch
++ iref_cp nDown biasp Up vss charge_pump
+Xloop_filter_v2_0 lf_vc lf_D0 vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vdd vss n_out_div_2 out_by_2 n_out_by_2 out_buffer_div_2 n_out_buffer_div_2
++ out_to_div out_div_2 div_by_2
+Xfreq_div_0 clk_0 vss n_clk_0 vdd freq_div_0/prescaler_23_0/Q2 s_0 s_1_n s_1 freq_div_0/prescaler_23_0/nCLK_23
++ MC clk_d freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n clk_pre
++ freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out_div freq_div_0/div_by_5_0/Q1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ clk_2_f out_by_2 n_out_by_2 clk_5 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D
++ freq_div
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad vdd out_to_buffer vss buffer_salida
+Xring_osc_0 vco_vctrl vss vdd ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vss
++ vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div PFD
+C0 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D 0.53fF
+C1 biasp nUp -0.16fF
+C2 iref_cp Down 0.09fF
+C3 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D 0.09fF
+C4 vco_vctrl freq_div_0/prescaler_23_0/Q2 0.06fF
+C5 clk_d out_div 0.60fF
+C6 vco_vctrl vdd 0.58fF
+C7 vco_vctrl freq_div_0/div_by_5_0/Q1 0.10fF
+C8 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
+C9 vdd nUp 0.05fF
+C10 vco_vctrl n_clk_1 0.23fF
+C11 MC vco_vctrl 0.33fF
+C12 charge_pump_0/w_2544_775# nDown 0.05fF
+C13 Down nDown 2.55fF
+C14 QA vdd -0.04fF
+C15 vco_vctrl s_0_n 0.34fF
+C16 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.15fF
+C17 nswitch nDown 0.76fF
+C18 vco_vctrl clk_0 -0.26fF
+C19 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C20 pswitch Up 1.98fF
+C21 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D -0.42fF
+C22 nUp Up 2.72fF
+C23 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vco_vctrl 0.09fF
+C24 out_to_buffer vdd 0.07fF
+C25 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD -0.42fF
+C26 vco_vctrl s_0 0.45fF
+C27 biasp Down 1.24fF
+C28 n_out_by_2 s_0_n 0.14fF
+C29 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C30 biasp Up 0.26fF
+C31 MC lf_vc 0.20fF
+C32 out_by_2 n_out_by_2 0.27fF
+C33 clk_0 vdd 0.13fF
+C34 vdd Up 0.28fF
+C35 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C36 vdd buffer_salida_0/a_678_n100# 0.24fF
+C37 n_out_by_2 s_0 0.14fF
+C38 charge_pump_0/w_2544_775# Down -0.23fF
+C39 vco_vctrl clk_1 -0.04fF
+C40 out_to_buffer buffer_salida_0/a_678_n100# 0.21fF
+C41 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.65fF
+C42 nswitch Down 0.54fF
+C43 out_to_buffer out_to_div 0.13fF
+C44 s_1 out_div 0.37fF
+C45 pswitch nDown 0.53fF
+C46 nDown nUp -0.09fF
+C47 n_out_by_2 clk_1 -0.10fF
+C48 vco_D0 vdd 0.03fF
+C49 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# 0.82fF
+C50 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vco_vctrl 0.17fF
+C51 pswitch nUp 0.93fF
+C52 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C53 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C54 vco_vctrl freq_div_0/prescaler_23_0/nCLK_23 0.06fF
+C55 biasp nDown 0.26fF
+C56 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# 0.34fF
+C57 out_to_div s_0 0.94fF
+C58 s_1_n out_div 0.09fF
+C59 vdd nDown 0.22fF
+C60 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vco_vctrl 1.23fF
+C61 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C62 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C63 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C64 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C65 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C66 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C67 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C68 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C69 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C70 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C71 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C72 QB vss 3.15fF
+C73 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C74 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C75 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C76 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C77 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C78 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C79 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C80 pfd_reset vss 1.87fF
+C81 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C82 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C83 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C84 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C85 QA vss 3.49fF
+C86 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C87 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C88 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C89 in_ref vss 0.84fF
+C90 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C91 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.66fF
+C92 nUp vss 0.12fF
+C93 Up vss -4.26fF
+C94 Down vss 1.89fF
+C95 nDown vss 2.59fF
+C96 out_to_buffer vss 1.92fF
+C97 out_to_div vss 8.72fF
+C98 out_first_buffer vss 2.15fF
+C99 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C100 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C101 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C102 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C103 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C104 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C105 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C106 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C107 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C108 vco_out vss 1.65fF
+C109 vco_D0 vss -4.72fF
+C110 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C111 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C112 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C113 out_to_pad vss 7.15fF
+C114 buffer_salida_0/a_3996_n100# vss 48.29fF
+C115 buffer_salida_0/a_678_n100# vss 13.38fF
+C116 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C117 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C118 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C119 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C120 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C121 freq_div_0/prescaler_23_0/Q2_d vss -0.69fF
+C122 freq_div_0/prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C123 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C124 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C125 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C126 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C127 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C128 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C129 freq_div_0/prescaler_23_0/Q2 vss 0.55fF
+C130 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C131 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C132 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C133 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C134 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C135 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C136 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C137 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C138 freq_div_0/prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C139 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C140 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C141 n_clk_0 vss -6.63fF
+C142 freq_div_0/prescaler_23_0/Q1 vss 0.07fF
+C143 freq_div_0/prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C144 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C145 clk_0 vss -0.36fF
+C146 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C147 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C148 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C149 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C150 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C151 freq_div_0/prescaler_23_0/nCLK_23 vss -1.02fF
+C152 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C153 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C154 MC vss -1.42fF
+C155 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C156 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C157 n_out_by_2 vss 4.53fF
+C158 out_by_2 vss 4.18fF
+C159 s_0_n vss -3.95fF
+C160 s_0 vss 5.61fF
+C161 freq_div_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C162 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C163 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C164 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C165 freq_div_0/div_by_5_0/Q1_shift vss -0.36fF
+C166 freq_div_0/div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C167 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C168 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C169 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C170 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C171 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C172 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C173 freq_div_0/div_by_5_0/Q1 vss 4.35fF
+C174 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C175 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C176 freq_div_0/div_by_5_0/Q0 vss 0.29fF
+C177 freq_div_0/div_by_5_0/nQ0 vss 0.99fF
+C178 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C179 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C180 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C181 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C182 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C183 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C184 freq_div_0/div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C185 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C186 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C187 freq_div_0/div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C188 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C189 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C190 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C191 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C192 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C193 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C194 freq_div_0/div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C195 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C196 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C197 n_clk_1 vss -0.57fF
+C198 freq_div_0/div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C199 freq_div_0/div_by_5_0/nQ2 vss 1.38fF
+C200 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C201 clk_1 vss -2.22fF
+C202 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C203 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C204 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C205 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C206 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C207 freq_div_0/div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C208 vdd vss 573.83fF
+C209 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C210 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C211 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C212 out_div vss 3.34fF
+C213 clk_d vss 1.26fF
+C214 s_1_n vss -2.01fF
+C215 s_1 vss 1.77fF
+C216 freq_div_0/inverter_min_x4_0/in vss 2.71fF
+C217 clk_5 vss -0.23fF
+C218 clk_out_mux21 vss 3.65fF
+C219 clk_pre vss 1.67fF
+C220 clk_2_f vss 3.29fF
+C221 freq_div_0/div_by_2_0/o1 vss 2.08fF
+C222 freq_div_0/div_by_2_0/nCLK_2 vss 1.04fF
+C223 freq_div_0/div_by_2_0/o2 vss 2.08fF
+C224 freq_div_0/div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C225 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C226 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C227 freq_div_0/div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C228 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C229 freq_div_0/div_by_2_0/out_div vss -0.82fF
+C230 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C231 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C232 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C233 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C234 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C235 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C236 freq_div_0/div_by_2_0/nout_div vss 2.62fF
+C237 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C238 out_buffer_div_2 vss 1.57fF
+C239 n_out_buffer_div_2 vss 1.57fF
+C240 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C241 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C242 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C243 div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C244 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C245 out_div_2 vss -0.70fF
+C246 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C247 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C248 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C249 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C250 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C251 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C252 n_out_div_2 vss 2.11fF
+C253 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C254 lf_vc vss -60.88fF
+C255 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C256 lf_D0 vss 0.01fF
+C257 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C258 nswitch vss 4.61fF
+C259 biasp vss 5.46fF
+C260 iref_cp vss 2.44fF
+C261 vco_vctrl vss -30.43fF
+C262 pswitch vss 2.72fF
+.end
+
diff --git a/mag/extractions/top_pll_v3_pex_rc_port.spice b/mag/extractions/top_pll_v3_pex_rc_port.spice
new file mode 100644
index 0000000..0728c2d
--- /dev/null
+++ b/mag/extractions/top_pll_v3_pex_rc_port.spice
@@ -0,0 +1,3520 @@
+* NGSPICE file created from top_pll_v3.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_887_n486# w_n2457_n634# 0.02fF
+C1 a_n1403_n486# w_n2457_n634# 0.02fF
+C2 a_1803_n486# w_n2457_n634# 0.02fF
+C3 a_429_n486# w_n2457_n634# 0.02fF
+C4 a_n2319_n486# w_n2457_n634# 0.02fF
+C5 a_2261_n486# w_n2457_n634# 0.02fF
+C6 a_n29_n486# w_n2457_n634# 0.02fF
+C7 a_1345_n486# w_n2457_n634# 0.02fF
+C8 a_n1861_n486# w_n2457_n634# 0.02fF
+C9 a_n487_n486# w_n2457_n634# 0.02fF
+C10 a_n945_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_399_n75# a_207_n75# 0.08fF
+C1 a_207_n75# a_495_n75# 0.05fF
+C2 a_n177_n75# a_n561_n75# 0.03fF
+C3 a_n945_n75# a_n753_n75# 0.08fF
+C4 a_399_n75# a_303_n75# 0.22fF
+C5 a_303_n75# a_495_n75# 0.08fF
+C6 a_n273_n75# a_111_n75# 0.03fF
+C7 a_n465_n75# a_n753_n75# 0.05fF
+C8 a_1167_n75# a_783_n75# 0.03fF
+C9 a_n945_n75# a_n561_n75# 0.03fF
+C10 a_15_n75# a_111_n75# 0.22fF
+C11 a_n465_n75# a_n561_n75# 0.22fF
+C12 a_399_n75# a_591_n75# 0.08fF
+C13 a_591_n75# a_879_n75# 0.05fF
+C14 a_207_n75# a_n177_n75# 0.03fF
+C15 a_591_n75# a_495_n75# 0.22fF
+C16 a_399_n75# a_783_n75# 0.03fF
+C17 a_783_n75# a_879_n75# 0.22fF
+C18 a_495_n75# a_783_n75# 0.05fF
+C19 a_n657_n75# a_n369_n75# 0.05fF
+C20 a_n273_n75# a_n369_n75# 0.22fF
+C21 a_207_n75# a_303_n75# 0.22fF
+C22 a_n1137_n75# a_n945_n75# 0.08fF
+C23 a_n273_n75# a_n81_n75# 0.08fF
+C24 a_n657_n75# a_n849_n75# 0.08fF
+C25 a_15_n75# a_n369_n75# 0.03fF
+C26 a_591_n75# a_975_n75# 0.03fF
+C27 a_n1041_n75# a_n849_n75# 0.08fF
+C28 a_783_n75# a_975_n75# 0.08fF
+C29 a_15_n75# a_n81_n75# 0.22fF
+C30 a_n177_n75# a_n465_n75# 0.05fF
+C31 a_591_n75# a_207_n75# 0.03fF
+C32 a_n1137_n75# a_n1229_n75# 0.22fF
+C33 a_399_n75# a_111_n75# 0.05fF
+C34 a_495_n75# a_111_n75# 0.03fF
+C35 a_399_n75# a_687_n75# 0.05fF
+C36 a_879_n75# a_687_n75# 0.08fF
+C37 a_495_n75# a_687_n75# 0.08fF
+C38 a_591_n75# a_303_n75# 0.05fF
+C39 a_n1229_n75# a_n945_n75# 0.05fF
+C40 a_n369_n75# a_n753_n75# 0.03fF
+C41 a_n369_n75# a_n561_n75# 0.08fF
+C42 a_975_n75# a_687_n75# 0.05fF
+C43 a_1071_n75# a_1167_n75# 0.22fF
+C44 a_207_n75# a_111_n75# 0.22fF
+C45 a_n849_n75# a_n753_n75# 0.22fF
+C46 a_591_n75# a_783_n75# 0.08fF
+C47 a_n177_n75# a_111_n75# 0.05fF
+C48 a_n849_n75# a_n561_n75# 0.05fF
+C49 a_303_n75# a_111_n75# 0.08fF
+C50 a_1071_n75# a_879_n75# 0.08fF
+C51 a_303_n75# a_687_n75# 0.03fF
+C52 a_n177_n75# a_n369_n75# 0.08fF
+C53 a_207_n75# a_n81_n75# 0.05fF
+C54 a_1071_n75# a_975_n75# 0.22fF
+C55 a_n177_n75# a_n81_n75# 0.22fF
+C56 a_n1137_n75# a_n849_n75# 0.05fF
+C57 a_591_n75# a_687_n75# 0.22fF
+C58 a_783_n75# a_687_n75# 0.22fF
+C59 a_303_n75# a_n81_n75# 0.03fF
+C60 a_n1041_n75# a_n657_n75# 0.03fF
+C61 a_n273_n75# a_n657_n75# 0.03fF
+C62 a_n369_n75# a_n465_n75# 0.22fF
+C63 a_n945_n75# a_n849_n75# 0.22fF
+C64 a_n81_n75# a_n465_n75# 0.03fF
+C65 a_n849_n75# a_n465_n75# 0.03fF
+C66 a_15_n75# a_n273_n75# 0.05fF
+C67 a_n1229_n75# a_n849_n75# 0.03fF
+C68 a_1071_n75# a_783_n75# 0.05fF
+C69 a_n657_n75# a_n753_n75# 0.22fF
+C70 a_n1041_n75# a_n753_n75# 0.05fF
+C71 a_n81_n75# a_111_n75# 0.08fF
+C72 a_n657_n75# a_n561_n75# 0.22fF
+C73 a_n273_n75# a_n561_n75# 0.05fF
+C74 a_15_n75# a_399_n75# 0.03fF
+C75 a_1071_n75# a_687_n75# 0.03fF
+C76 a_n81_n75# a_n369_n75# 0.05fF
+C77 a_n1137_n75# a_n1041_n75# 0.22fF
+C78 a_1167_n75# a_879_n75# 0.05fF
+C79 a_n273_n75# a_n177_n75# 0.22fF
+C80 a_15_n75# a_207_n75# 0.08fF
+C81 a_n753_n75# a_n561_n75# 0.08fF
+C82 a_15_n75# a_n177_n75# 0.08fF
+C83 a_n945_n75# a_n657_n75# 0.05fF
+C84 a_n945_n75# a_n1041_n75# 0.22fF
+C85 a_399_n75# a_495_n75# 0.22fF
+C86 a_495_n75# a_879_n75# 0.03fF
+C87 a_n657_n75# a_n465_n75# 0.08fF
+C88 a_15_n75# a_303_n75# 0.05fF
+C89 a_1167_n75# a_975_n75# 0.08fF
+C90 a_n273_n75# a_n465_n75# 0.08fF
+C91 a_n1229_n75# a_n1041_n75# 0.08fF
+C92 a_975_n75# a_879_n75# 0.22fF
+C93 a_n1137_n75# a_n753_n75# 0.03fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_63_n75# a_n129_n75# 0.08fF
+C1 a_n513_n75# a_n609_n75# 0.22fF
+C2 a_255_n75# a_447_n75# 0.08fF
+C3 a_63_n75# a_n33_n75# 0.22fF
+C4 a_159_n75# a_n225_n75# 0.03fF
+C5 a_735_n75# a_447_n75# 0.05fF
+C6 a_63_n75# a_255_n75# 0.08fF
+C7 a_255_n75# a_639_n75# 0.03fF
+C8 a_n513_n75# a_n897_n75# 0.03fF
+C9 a_n321_n75# a_n225_n75# 0.22fF
+C10 a_735_n75# a_639_n75# 0.22fF
+C11 a_n129_n75# a_n513_n75# 0.03fF
+C12 a_543_n75# a_831_n75# 0.05fF
+C13 a_927_n75# a_831_n75# 0.22fF
+C14 a_n129_n75# a_n33_n75# 0.22fF
+C15 a_n129_n75# a_255_n75# 0.03fF
+C16 a_543_n75# a_351_n75# 0.08fF
+C17 a_159_n75# a_351_n75# 0.08fF
+C18 a_n321_n75# a_n417_n75# 0.22fF
+C19 a_n33_n75# a_255_n75# 0.05fF
+C20 a_63_n75# a_n225_n75# 0.05fF
+C21 a_n609_n75# a_n225_n75# 0.03fF
+C22 a_831_n75# a_447_n75# 0.03fF
+C23 a_n705_n75# a_n417_n75# 0.05fF
+C24 a_831_n75# a_639_n75# 0.08fF
+C25 a_n801_n75# a_n705_n75# 0.22fF
+C26 a_n129_n75# a_n225_n75# 0.22fF
+C27 a_351_n75# a_447_n75# 0.22fF
+C28 a_n609_n75# a_n417_n75# 0.08fF
+C29 a_n513_n75# a_n225_n75# 0.05fF
+C30 a_63_n75# a_351_n75# 0.05fF
+C31 a_351_n75# a_639_n75# 0.05fF
+C32 a_n33_n75# a_n225_n75# 0.08fF
+C33 a_n801_n75# a_n989_n75# 0.08fF
+C34 a_n801_n75# a_n609_n75# 0.08fF
+C35 a_n129_n75# a_n417_n75# 0.05fF
+C36 a_n801_n75# a_n897_n75# 0.22fF
+C37 a_n513_n75# a_n417_n75# 0.22fF
+C38 a_33_n101# a_n927_n101# 0.08fF
+C39 a_n33_n75# a_n417_n75# 0.03fF
+C40 a_n801_n75# a_n513_n75# 0.05fF
+C41 a_927_n75# a_543_n75# 0.03fF
+C42 a_159_n75# a_543_n75# 0.03fF
+C43 a_831_n75# a_735_n75# 0.22fF
+C44 a_n33_n75# a_351_n75# 0.03fF
+C45 a_255_n75# a_351_n75# 0.22fF
+C46 a_351_n75# a_735_n75# 0.03fF
+C47 a_543_n75# a_447_n75# 0.22fF
+C48 a_159_n75# a_447_n75# 0.05fF
+C49 a_n417_n75# a_n225_n75# 0.08fF
+C50 a_n321_n75# a_n705_n75# 0.03fF
+C51 a_543_n75# a_639_n75# 0.22fF
+C52 a_63_n75# a_159_n75# 0.22fF
+C53 a_927_n75# a_639_n75# 0.05fF
+C54 a_n321_n75# a_63_n75# 0.03fF
+C55 a_n321_n75# a_n609_n75# 0.05fF
+C56 a_159_n75# a_n129_n75# 0.05fF
+C57 a_n705_n75# a_n989_n75# 0.05fF
+C58 a_n705_n75# a_n609_n75# 0.22fF
+C59 a_n801_n75# a_n417_n75# 0.03fF
+C60 a_63_n75# a_447_n75# 0.03fF
+C61 a_n321_n75# a_n129_n75# 0.08fF
+C62 a_447_n75# a_639_n75# 0.08fF
+C63 a_159_n75# a_n33_n75# 0.08fF
+C64 a_n321_n75# a_n513_n75# 0.08fF
+C65 a_255_n75# a_543_n75# 0.05fF
+C66 a_159_n75# a_255_n75# 0.22fF
+C67 a_n609_n75# a_n989_n75# 0.03fF
+C68 a_543_n75# a_735_n75# 0.08fF
+C69 a_n705_n75# a_n897_n75# 0.08fF
+C70 a_n321_n75# a_n33_n75# 0.05fF
+C71 a_927_n75# a_735_n75# 0.08fF
+C72 a_n513_n75# a_n705_n75# 0.08fF
+C73 a_n897_n75# a_n989_n75# 0.22fF
+C74 a_n609_n75# a_n897_n75# 0.05fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_63_n150# a_351_n150# 0.10fF
+C1 a_n513_n150# a_n801_n150# 0.10fF
+C2 a_n801_n150# a_n705_n150# 0.43fF
+C3 a_447_n150# a_351_n150# 0.43fF
+C4 a_n321_n150# a_n129_n150# 0.16fF
+C5 a_n513_n150# a_n609_n150# 0.43fF
+C6 a_n609_n150# a_n705_n150# 0.43fF
+C7 a_n513_n150# a_n321_n150# 0.16fF
+C8 a_n321_n150# a_n705_n150# 0.07fF
+C9 a_447_n150# a_831_n150# 0.07fF
+C10 a_639_n150# a_735_n150# 0.43fF
+C11 a_n513_n150# a_n897_n150# 0.07fF
+C12 a_63_n150# a_447_n150# 0.07fF
+C13 a_n897_n150# a_n705_n150# 0.16fF
+C14 a_n801_n150# a_n609_n150# 0.16fF
+C15 a_63_n150# a_n321_n150# 0.07fF
+C16 a_n33_n150# a_n225_n150# 0.16fF
+C17 a_927_n150# a_831_n150# 0.43fF
+C18 a_n417_n150# a_n225_n150# 0.16fF
+C19 a_159_n150# a_n33_n150# 0.16fF
+C20 a_639_n150# a_543_n150# 0.43fF
+C21 a_n801_n150# a_n897_n150# 0.43fF
+C22 a_n609_n150# a_n321_n150# 0.10fF
+C23 a_351_n150# a_735_n150# 0.07fF
+C24 a_n897_n150# a_n609_n150# 0.10fF
+C25 a_255_n150# a_543_n150# 0.10fF
+C26 a_735_n150# a_831_n150# 0.43fF
+C27 a_159_n150# a_255_n150# 0.43fF
+C28 a_n225_n150# a_n129_n150# 0.43fF
+C29 a_351_n150# a_543_n150# 0.16fF
+C30 a_447_n150# a_735_n150# 0.10fF
+C31 a_159_n150# a_n129_n150# 0.10fF
+C32 a_n513_n150# a_n225_n150# 0.10fF
+C33 a_159_n150# a_351_n150# 0.16fF
+C34 a_543_n150# a_831_n150# 0.10fF
+C35 a_927_n150# a_735_n150# 0.16fF
+C36 a_63_n150# a_n225_n150# 0.10fF
+C37 a_447_n150# a_543_n150# 0.43fF
+C38 a_159_n150# a_63_n150# 0.43fF
+C39 a_159_n150# a_447_n150# 0.10fF
+C40 a_n417_n150# a_n33_n150# 0.07fF
+C41 a_n609_n150# a_n225_n150# 0.07fF
+C42 a_n321_n150# a_n225_n150# 0.43fF
+C43 a_927_n150# a_543_n150# 0.07fF
+C44 a_255_n150# a_n33_n150# 0.10fF
+C45 a_33_n247# a_n927_n247# 0.09fF
+C46 a_n33_n150# a_n129_n150# 0.43fF
+C47 a_n417_n150# a_n129_n150# 0.10fF
+C48 a_n989_n150# a_n705_n150# 0.10fF
+C49 a_543_n150# a_735_n150# 0.16fF
+C50 a_639_n150# a_255_n150# 0.07fF
+C51 a_n33_n150# a_351_n150# 0.07fF
+C52 a_n513_n150# a_n417_n150# 0.43fF
+C53 a_n417_n150# a_n705_n150# 0.10fF
+C54 a_639_n150# a_351_n150# 0.10fF
+C55 a_n801_n150# a_n989_n150# 0.16fF
+C56 a_63_n150# a_n33_n150# 0.43fF
+C57 a_255_n150# a_n129_n150# 0.07fF
+C58 a_639_n150# a_831_n150# 0.16fF
+C59 a_n801_n150# a_n417_n150# 0.07fF
+C60 a_n609_n150# a_n989_n150# 0.07fF
+C61 a_255_n150# a_351_n150# 0.43fF
+C62 a_159_n150# a_543_n150# 0.07fF
+C63 a_n513_n150# a_n129_n150# 0.07fF
+C64 a_159_n150# a_n225_n150# 0.07fF
+C65 a_n417_n150# a_n609_n150# 0.16fF
+C66 a_639_n150# a_447_n150# 0.16fF
+C67 a_n321_n150# a_n33_n150# 0.10fF
+C68 a_n417_n150# a_n321_n150# 0.43fF
+C69 a_n897_n150# a_n989_n150# 0.43fF
+C70 a_n513_n150# a_n705_n150# 0.16fF
+C71 a_63_n150# a_255_n150# 0.16fF
+C72 a_447_n150# a_255_n150# 0.16fF
+C73 a_63_n150# a_n129_n150# 0.16fF
+C74 a_639_n150# a_927_n150# 0.10fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n745_n44# a_n387_n44# 0.04fF
+C1 a_n1461_n44# a_n1819_n44# 0.04fF
+C2 a_n29_n44# a_329_n44# 0.04fF
+C3 a_1403_n44# a_1761_n44# 0.04fF
+C4 a_n29_n44# a_n387_n44# 0.04fF
+C5 a_n1461_n44# a_n1103_n44# 0.04fF
+C6 a_1403_n44# a_1045_n44# 0.04fF
+C7 a_n745_n44# a_n1103_n44# 0.04fF
+C8 a_687_n44# a_329_n44# 0.04fF
+C9 a_1045_n44# a_687_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n369_n150# a_n657_n150# 0.10fF
+C1 a_n657_n150# a_n1041_n150# 0.07fF
+C2 a_n657_n150# a_n561_n150# 0.43fF
+C3 a_n945_n150# a_n1041_n150# 0.43fF
+C4 a_n945_n150# a_n561_n150# 0.07fF
+C5 w_n1367_n369# a_879_n150# 0.04fF
+C6 a_n369_n150# a_n465_n150# 0.43fF
+C7 a_495_n150# a_879_n150# 0.07fF
+C8 a_591_n150# a_303_n150# 0.10fF
+C9 a_n465_n150# a_n561_n150# 0.43fF
+C10 a_n753_n150# a_n1137_n150# 0.07fF
+C11 a_n369_n150# a_n177_n150# 0.16fF
+C12 a_n177_n150# a_111_n150# 0.10fF
+C13 a_n177_n150# a_n561_n150# 0.07fF
+C14 a_495_n150# a_687_n150# 0.16fF
+C15 a_303_n150# a_111_n150# 0.16fF
+C16 a_783_n150# a_879_n150# 0.43fF
+C17 a_n369_n150# a_n753_n150# 0.07fF
+C18 a_n753_n150# a_n1041_n150# 0.10fF
+C19 a_n753_n150# a_n561_n150# 0.16fF
+C20 a_n369_n150# a_15_n150# 0.07fF
+C21 a_783_n150# a_687_n150# 0.43fF
+C22 a_n657_n150# a_n945_n150# 0.10fF
+C23 a_15_n150# a_111_n150# 0.43fF
+C24 a_207_n150# a_n81_n150# 0.10fF
+C25 a_495_n150# a_399_n150# 0.43fF
+C26 a_n657_n150# a_n465_n150# 0.16fF
+C27 a_495_n150# a_207_n150# 0.10fF
+C28 a_1071_n150# a_975_n150# 0.43fF
+C29 a_783_n150# a_399_n150# 0.07fF
+C30 a_591_n150# a_879_n150# 0.10fF
+C31 a_591_n150# a_687_n150# 0.43fF
+C32 a_n657_n150# a_n753_n150# 0.43fF
+C33 a_n465_n150# a_n177_n150# 0.10fF
+C34 a_n753_n150# a_n945_n150# 0.16fF
+C35 a_n753_n150# a_n465_n150# 0.10fF
+C36 a_591_n150# a_399_n150# 0.16fF
+C37 a_n177_n150# a_15_n150# 0.16fF
+C38 a_879_n150# a_975_n150# 0.43fF
+C39 a_591_n150# a_207_n150# 0.07fF
+C40 a_n1137_n150# a_n849_n150# 0.10fF
+C41 a_399_n150# a_111_n150# 0.10fF
+C42 a_15_n150# a_303_n150# 0.10fF
+C43 a_975_n150# a_687_n150# 0.10fF
+C44 w_n1367_n369# a_1167_n150# 0.14fF
+C45 a_n1229_n150# a_n1137_n150# 0.43fF
+C46 a_207_n150# a_111_n150# 0.43fF
+C47 a_n1041_n150# a_n849_n150# 0.16fF
+C48 a_n849_n150# a_n561_n150# 0.10fF
+C49 a_783_n150# a_1167_n150# 0.07fF
+C50 a_n1229_n150# a_n1041_n150# 0.16fF
+C51 a_1071_n150# a_879_n150# 0.16fF
+C52 a_303_n150# a_687_n150# 0.07fF
+C53 a_n657_n150# a_n849_n150# 0.16fF
+C54 a_1071_n150# a_687_n150# 0.07fF
+C55 a_n945_n150# a_n849_n150# 0.43fF
+C56 a_n273_n150# a_n81_n150# 0.16fF
+C57 a_n1229_n150# a_n945_n150# 0.10fF
+C58 a_n465_n150# a_n849_n150# 0.07fF
+C59 a_399_n150# a_303_n150# 0.43fF
+C60 a_n177_n150# a_207_n150# 0.07fF
+C61 a_207_n150# a_303_n150# 0.43fF
+C62 a_15_n150# a_399_n150# 0.07fF
+C63 a_783_n150# a_495_n150# 0.10fF
+C64 a_207_n150# a_15_n150# 0.16fF
+C65 a_n753_n150# a_n849_n150# 0.43fF
+C66 a_1167_n150# a_975_n150# 0.16fF
+C67 a_879_n150# a_687_n150# 0.16fF
+C68 a_591_n150# a_495_n150# 0.43fF
+C69 a_n369_n150# a_n81_n150# 0.10fF
+C70 a_n81_n150# a_111_n150# 0.16fF
+C71 a_399_n150# a_687_n150# 0.10fF
+C72 a_495_n150# a_111_n150# 0.07fF
+C73 a_783_n150# a_591_n150# 0.16fF
+C74 a_n369_n150# a_n273_n150# 0.43fF
+C75 a_n273_n150# a_111_n150# 0.07fF
+C76 a_n273_n150# a_n561_n150# 0.10fF
+C77 a_1071_n150# a_1167_n150# 0.43fF
+C78 w_n1367_n369# a_975_n150# 0.05fF
+C79 a_207_n150# a_399_n150# 0.16fF
+C80 a_783_n150# a_975_n150# 0.16fF
+C81 a_n657_n150# a_n273_n150# 0.07fF
+C82 a_n465_n150# a_n81_n150# 0.07fF
+C83 a_n1137_n150# a_n1041_n150# 0.43fF
+C84 a_n177_n150# a_n81_n150# 0.43fF
+C85 a_n1229_n150# a_n849_n150# 0.07fF
+C86 a_1167_n150# a_879_n150# 0.10fF
+C87 a_n273_n150# a_n465_n150# 0.16fF
+C88 a_303_n150# a_n81_n150# 0.07fF
+C89 a_n273_n150# a_n177_n150# 0.43fF
+C90 a_n369_n150# a_n561_n150# 0.16fF
+C91 a_495_n150# a_303_n150# 0.16fF
+C92 a_15_n150# a_n81_n150# 0.43fF
+C93 a_591_n150# a_975_n150# 0.07fF
+C94 a_1071_n150# w_n1367_n369# 0.07fF
+C95 a_n273_n150# a_15_n150# 0.10fF
+C96 a_n945_n150# a_n1137_n150# 0.16fF
+C97 a_783_n150# a_1071_n150# 0.10fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vss vdd nUp Down w_2544_775# out pswitch iref nDown biasp
++ Up w_6648_570#
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 vdd out 6.66fF
+C1 nUp pswitch 5.66fF
+C2 nUp Up 0.15fF
+C3 iref biasp 0.80fF
+C4 vdd biasp 2.64fF
+C5 nUp out 0.31fF
+C6 nUp Down 0.25fF
+C7 nswitch nDown 0.31fF
+C8 Up pswitch 0.70fF
+C9 nswitch pswitch 0.06fF
+C10 Down nDown 0.13fF
+C11 out pswitch 4.91fF
+C12 nswitch out 1.28fF
+C13 pswitch biasp 3.11fF
+C14 nswitch Down 2.27fF
+C15 nswitch biasp 0.03fF
+C16 nswitch iref 1.91fF
+C17 vdd pswitch 3.98fF
+C18 vdd nswitch 0.07fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n2650_n2600# m3_n2650_2700# 3.28fF
+C1 m3_2669_2700# m3_n2650_2700# 2.73fF
+C2 m3_n2650_n2600# m3_n2650_n7900# 3.28fF
+C3 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C4 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C5 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C6 m3_7988_n13200# m3_7988_n7900# 3.39fF
+C7 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C8 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C9 m3_n7969_2700# c1_n13188_n13100# 58.86fF
+C10 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C11 m3_n2650_n2600# m3_n7969_n2600# 2.73fF
+C12 m3_7988_8000# m3_2669_8000# 2.73fF
+C13 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C14 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C15 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C16 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C17 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C18 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C19 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C20 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C21 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C22 m3_n13288_2700# c1_n13188_n13100# 58.61fF
+C23 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C24 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C25 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C26 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C27 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C28 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C29 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C30 m3_2669_2700# m3_7988_2700# 2.73fF
+C31 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C32 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C33 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C34 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C35 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C36 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C37 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C38 m3_n7969_2700# m3_n7969_n2600# 3.28fF
+C39 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C40 m3_7988_n2600# m3_7988_n7900# 3.39fF
+C41 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C42 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C43 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C44 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C45 m3_7988_n2600# m3_7988_2700# 3.39fF
+C46 m3_n7969_2700# m3_n7969_8000# 3.28fF
+C47 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C48 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C49 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C50 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C51 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C52 m3_2669_2700# m3_2669_8000# 3.28fF
+C53 m3_2669_2700# m3_2669_n2600# 3.28fF
+C54 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C55 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C56 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C57 m3_7988_8000# m3_7988_2700# 3.39fF
+C58 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C59 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C60 m3_n2650_8000# m3_2669_8000# 2.73fF
+C61 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C62 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C63 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C64 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_10_n4250# c1_110_n4150# 81.11fF
+C1 c1_n4209_n4150# c1_110_n4150# 1.32fF
+C2 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C3 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C4 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C5 m3_n4309_50# m3_10_n4250# 1.75fF
+C6 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 in out 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C1 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C2 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C3 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C4 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C5 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C6 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C7 m3_n2150_2200# m3_n6469_2200# 1.75fF
+C8 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C9 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C10 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C11 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C12 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C13 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C14 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C15 m3_n2150_2200# m3_n2150_n2100# 2.63fF
+C16 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
+C17 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
+C18 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_n118_n388# a_n88_n300# 0.11fF
+C1 a_30_n300# a_n88_n300# 0.61fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 vc_pex in 0.18fF
+C1 D0_cap in 0.07fF
+C2 cap3_loop_filter_0/in in 0.79fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS w_n311_n338# a_81_n156# a_111_n125# a_15_n125#
++ a_n173_n125# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_81_n156# a_n15_n156# 0.02fF
+C1 a_n111_n156# a_n15_n156# 0.02fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 a_n173_n125# a_n81_n125# 0.36fF
+C4 a_111_n125# a_n81_n125# 0.13fF
+C5 a_n173_n125# a_15_n125# 0.13fF
+C6 a_111_n125# a_15_n125# 0.36fF
+C7 a_111_n125# a_n173_n125# 0.08fF
+C8 a_111_n125# VSUBS 0.03fF
+C9 a_15_n125# VSUBS 0.03fF
+C10 a_n81_n125# VSUBS 0.03fF
+C11 a_n173_n125# VSUBS 0.03fF
+C12 a_81_n156# VSUBS 0.05fF
+C13 a_n15_n156# VSUBS 0.05fF
+C14 a_n111_n156# VSUBS 0.05fF
+C15 w_n311_n338# VSUBS 1.56fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n15_n151# a_n111_n151# 0.02fF
+C1 a_n15_n151# a_81_n151# 0.02fF
+C2 a_n173_n125# a_111_n125# 0.08fF
+C3 a_n81_n125# a_n173_n125# 0.36fF
+C4 a_15_n125# a_111_n125# 0.36fF
+C5 a_n81_n125# a_15_n125# 0.36fF
+C6 a_15_n125# a_n173_n125# 0.13fF
+C7 a_n81_n125# a_111_n125# 0.13fF
+C8 a_111_n125# w_n311_n335# 0.04fF
+C9 a_15_n125# w_n311_n335# 0.04fF
+C10 a_n81_n125# w_n311_n335# 0.04fF
+C11 a_n173_n125# w_n311_n335# 0.04fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# vss m1_45_n513# vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd vss m1_187_n605# m1_45_n513# m1_45_n513#
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 vdd m1_187_n605# 0.55fF
+C1 m1_45_n513# m1_187_n605# 0.36fF
+C2 vdd m1_45_n513# 0.69fF
+C3 m1_187_n605# vss 0.73fF
+C4 m1_45_n513# vss 1.10fF
+C5 vdd vss 2.55fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_111_n125# 0.13fF
+C1 a_n173_n125# a_n81_n125# 0.36fF
+C2 a_15_n125# w_n311_n344# 0.09fF
+C3 a_15_n125# a_111_n125# 0.36fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_15_n125# a_n81_n125# 0.36fF
+C6 w_n311_n344# a_111_n125# 0.14fF
+C7 a_n173_n125# w_n311_n344# 0.14fF
+C8 a_n81_n125# w_n311_n344# 0.09fF
+C9 a_n173_n125# a_111_n125# 0.08fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_15_n125# 0.36fF
+C1 a_n81_n125# a_n173_n125# 0.36fF
+C2 a_15_n125# a_n173_n125# 0.13fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_111_n125# a_15_n125# 0.36fF
+C5 a_111_n125# a_n173_n125# 0.08fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 in out 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d vss inverter_cp_x1_0/out vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 nCLK_d vdd 0.03fF
+C1 inverter_cp_x1_0/out CLK 0.31fF
+C2 inverter_cp_x1_2/in vdd 0.21fF
+C3 CLK_d inverter_cp_x1_2/in 0.12fF
+C4 CLK_d vdd 0.03fF
+C5 inverter_cp_x1_2/in CLK 0.31fF
+C6 nCLK_d inverter_cp_x1_0/out 0.11fF
+C7 CLK vdd 0.36fF
+C8 inverter_cp_x1_0/out vdd 0.21fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.69fF
+C12 CLK vss 3.03fF
+C13 vdd vss 15.46fF
+C14 nCLK_d vss 1.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_63_n95# 0.28fF
+C1 a_n33_n95# a_n125_n95# 0.28fF
+C2 a_n33_n95# w_n263_n314# 0.08fF
+C3 a_n125_n95# a_63_n95# 0.10fF
+C4 a_63_n95# w_n263_n314# 0.11fF
+C5 a_n125_n95# w_n263_n314# 0.11fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_111_n125# 0.36fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 a_15_n125# a_n129_n213# 0.10fF
+C4 a_n173_n125# a_111_n125# 0.08fF
+C5 a_n81_n125# a_111_n125# 0.13fF
+C6 a_n173_n125# a_n81_n125# 0.36fF
+C7 a_111_n125# a_n129_n213# 0.01fF
+C8 a_n173_n125# a_n129_n213# 0.02fF
+C9 a_n81_n125# a_n129_n213# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n33_n95# 0.88fF
+C1 a_n125_n95# a_n81_n183# 0.16fF
+C2 a_n33_n95# a_n81_n183# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 nD Q 0.05fF
+C1 Q vdd 0.16fF
+C2 m1_657_280# CLK 0.24fF
+C3 nQ D 0.05fF
+C4 m1_657_280# nQ 1.41fF
+C5 nQ nD 0.05fF
+C6 nQ vdd 0.16fF
+C7 D Q 0.05fF
+C8 nQ Q 0.93fF
+C9 m1_657_280# Q 0.94fF
+C10 D vss 0.53fF
+C11 m1_657_280# vss 1.88fF
+C12 nD vss 0.16fF
+C13 CLK vss 0.87fF
+C14 Q vss -0.55fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vdd vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ nCLK latch_diff_0/nD Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D
++ CLK clock_inverter_0/inverter_cp_x1_0/out
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C1 latch_diff_1/nD vdd 0.02fF
+C2 nQ latch_diff_1/D 0.11fF
+C3 vdd latch_diff_0/nD 0.14fF
+C4 nQ latch_diff_1/nD 0.08fF
+C5 vdd latch_diff_0/D 0.09fF
+C6 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C7 latch_diff_1/D latch_diff_1/nD 0.33fF
+C8 latch_diff_1/D latch_diff_0/nD 0.41fF
+C9 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C10 latch_diff_1/D latch_diff_0/D 0.11fF
+C11 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C12 latch_diff_1/nD latch_diff_0/D 0.04fF
+C13 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C14 Q latch_diff_1/nD 0.01fF
+C15 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C16 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C17 latch_diff_1/D latch_diff_1/m1_657_280# 0.32fF
+C18 latch_diff_1/D vdd 0.01fF
+C19 latch_diff_1/m1_657_280# vss 0.64fF
+C20 nCLK vss 0.83fF
+C21 Q vss -0.92fF
+C22 nQ vss 0.57fF
+C23 latch_diff_0/m1_657_280# vss 0.69fF
+C24 CLK vss 0.83fF
+C25 latch_diff_1/D vss -0.33fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.63fF
+C30 D vss 3.27fF
+C31 vdd vss 31.85fF
+C32 latch_diff_0/nD vss 1.53fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 w_n359_n303# a_159_n84# 0.08fF
+C1 a_159_n84# a_63_n84# 0.24fF
+C2 a_129_n110# a_33_n110# 0.02fF
+C3 a_n33_n84# a_n221_n84# 0.09fF
+C4 a_n129_n84# a_n221_n84# 0.24fF
+C5 w_n359_n303# a_63_n84# 0.06fF
+C6 a_n129_n84# a_n33_n84# 0.24fF
+C7 a_n159_n110# a_n63_n110# 0.02fF
+C8 a_159_n84# a_n221_n84# 0.04fF
+C9 a_159_n84# a_n33_n84# 0.09fF
+C10 a_159_n84# a_n129_n84# 0.05fF
+C11 w_n359_n303# a_n221_n84# 0.08fF
+C12 w_n359_n303# a_n33_n84# 0.05fF
+C13 a_63_n84# a_n221_n84# 0.05fF
+C14 w_n359_n303# a_n129_n84# 0.06fF
+C15 a_33_n110# a_n63_n110# 0.02fF
+C16 a_63_n84# a_n33_n84# 0.24fF
+C17 a_63_n84# a_n129_n84# 0.09fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n42# a_159_n42# 0.05fF
+C1 a_n33_n42# a_n129_n42# 0.12fF
+C2 a_n129_n42# a_159_n42# 0.03fF
+C3 a_n63_n68# a_n159_n68# 0.02fF
+C4 a_33_n68# a_129_n68# 0.02fF
+C5 a_63_n42# a_n33_n42# 0.12fF
+C6 a_63_n42# a_159_n42# 0.12fF
+C7 a_63_n42# a_n129_n42# 0.05fF
+C8 a_n33_n42# a_n221_n42# 0.05fF
+C9 a_33_n68# a_n63_n68# 0.02fF
+C10 a_159_n42# a_n221_n42# 0.02fF
+C11 a_n129_n42# a_n221_n42# 0.12fF
+C12 a_63_n42# a_n221_n42# 0.03fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 out in 0.67fF
+C1 in vdd 0.33fF
+C2 out vdd 0.62fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n42# a_n125_n42# 0.12fF
+C1 a_n33_n42# a_63_n42# 0.12fF
+C2 a_n63_n68# a_33_n68# 0.02fF
+C3 a_n125_n42# a_63_n42# 0.05fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 w_n263_n303# a_63_n84# 0.10fF
+C1 w_n263_n303# a_n33_n84# 0.07fF
+C2 a_n125_n84# a_63_n84# 0.09fF
+C3 a_n125_n84# a_n33_n84# 0.24fF
+C4 a_63_n84# a_n33_n84# 0.24fF
+C5 a_n63_n110# a_33_n110# 0.02fF
+C6 w_n263_n303# a_n125_n84# 0.10fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 vdd out 0.15fF
+C1 in out 0.30fF
+C2 vdd in 0.01fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vdd vss nout_div CLK_2 nCLK_2 o1 o2 CLK out_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD
++ out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C1 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C2 vdd o1 0.14fF
+C3 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C4 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C5 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C6 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C7 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C8 nout_div DFlipFlop_0/CLK 0.42fF
+C9 out_div o1 0.01fF
+C10 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/CLK -0.48fF
+C11 vdd DFlipFlop_0/CLK 0.40fF
+C12 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C13 vdd nout_div 0.16fF
+C14 CLK_2 o1 0.11fF
+C15 vdd nCLK_2 0.08fF
+C16 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C17 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
+C18 nout_div out_div 0.22fF
+C19 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C20 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C21 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C22 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C23 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C24 vdd out_div 0.03fF
+C25 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C26 nout_div DFlipFlop_0/nCLK 0.43fF
+C27 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C28 o2 nCLK_2 0.11fF
+C29 vdd o2 0.14fF
+C30 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
+C31 vdd CLK_2 0.08fF
+C32 vdd DFlipFlop_0/nCLK 0.30fF
+C33 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C34 CLK_2 vss 1.08fF
+C35 o1 vss 2.21fF
+C36 nCLK_2 vss 1.08fF
+C37 o2 vss 2.21fF
+C38 DFlipFlop_0/CLK vss 1.03fF
+C39 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C40 clock_inverter_0/inverter_cp_x1_0/out vss 1.64fF
+C41 CLK vss 3.27fF
+C42 DFlipFlop_0/nCLK vss 1.55fF
+C43 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C46 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C47 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C48 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.59fF
+C51 nout_div vss 4.41fF
+C52 vdd vss 62.89fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+.ends
+
+.subckt trans_gate_mux2to8 in vss out en_pos en_neg vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd en_neg in out out en_neg en_neg in sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 en_pos vss en_pos in out out en_pos in sky130_fd_pr__nfet_01v8_BHR94T
+C0 en_pos en_neg 0.04fF
+C1 vdd in 0.05fF
+C2 in out 0.36fF
+C3 en_pos in 0.07fF
+C4 vdd out 0.27fF
+C5 en_pos out 0.27fF
+C6 in en_neg 0.28fF
+C7 out en_neg 0.07fF
+C8 vdd vss 2.08fF
+C9 in vss 1.12fF
+C10 out vss 0.87fF
+C11 en_pos vss 0.29fF
+C12 en_neg vss 0.31fF
+.ends
+
+.subckt mux2to1 vss select_0_neg out_a_0 out_a_1 select_0 vdd in_a
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 select_0 in_a 0.31fF
+C1 out_a_0 vdd 0.06fF
+C2 select_0_neg select_0 0.17fF
+C3 in_a vdd 0.02fF
+C4 out_a_0 in_a 0.08fF
+C5 out_a_1 select_0 0.14fF
+C6 out_a_0 select_0_neg 0.05fF
+C7 out_a_1 vdd 0.06fF
+C8 select_0_neg in_a 0.11fF
+C9 out_a_1 in_a 0.08fF
+C10 out_a_1 vss 0.99fF
+C11 vdd vss 4.78fF
+C12 in_a vss 2.00fF
+C13 out_a_0 vss 0.99fF
+C14 select_0_neg vss 1.15fF
+C15 select_0 vss 0.97fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_194_125# a_158_392# 0.06fF
+C1 a_194_125# X 0.29fF
+C2 VPWR B 0.09fF
+C3 VPWR VGND 0.01fF
+C4 B VGND 0.10fF
+C5 VPWR a_355_368# 0.37fF
+C6 B a_355_368# 0.08fF
+C7 VPWR A 0.15fF
+C8 B A 0.28fF
+C9 VGND A 0.31fF
+C10 VPWR a_194_125# 0.33fF
+C11 a_355_368# A 0.02fF
+C12 a_194_125# B 0.57fF
+C13 a_194_125# VGND 0.25fF
+C14 a_194_125# a_355_368# 0.51fF
+C15 VPWR VPB 0.06fF
+C16 VPWR X 0.07fF
+C17 a_194_125# A 0.18fF
+C18 B X 0.13fF
+C19 X VGND 0.28fF
+C20 X a_355_368# 0.17fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 B VPWR 0.02fF
+C1 a_56_136# A 0.17fF
+C2 VPWR X 0.20fF
+C3 B A 0.08fF
+C4 a_56_136# B 0.30fF
+C5 VPB VPWR 0.04fF
+C6 VGND A 0.21fF
+C7 a_56_136# VGND 0.06fF
+C8 a_56_136# X 0.26fF
+C9 B VGND 0.03fF
+C10 B X 0.02fF
+C11 VPWR A 0.07fF
+C12 a_56_136# VPWR 0.57fF
+C13 VGND X 0.15fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 A X 0.02fF
+C1 a_63_368# X 0.33fF
+C2 VPB VPWR 0.04fF
+C3 A VPWR 0.05fF
+C4 a_63_368# VPWR 0.29fF
+C5 VPWR X 0.18fF
+C6 a_152_368# a_63_368# 0.03fF
+C7 B VGND 0.11fF
+C8 B A 0.10fF
+C9 B a_63_368# 0.14fF
+C10 VGND a_63_368# 0.27fF
+C11 A a_63_368# 0.28fF
+C12 VGND X 0.16fF
+C13 B VPWR 0.01fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_2/latch_diff_0/nD vss
++ Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in CLK DFlipFlop_0/Q vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ DFlipFlop_3/latch_diff_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/nD DFlipFlop_2/latch_diff_0/m1_657_280# CLK_5 Q1_shift
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D DFlipFlop_1/D nQ0 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/latch_diff_1/nD Q0 DFlipFlop_0/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_0/latch_diff_0/nD DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/D
++ DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_152_368# sky130_fd_sc_hs__and2_1_1/a_56_136#
++ DFlipFlop_3/nQ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 nCLK DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ nCLK DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vdd vss DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ CLK DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C1 sky130_fd_sc_hs__xor2_1_0/a_355_368# Q0 0.03fF
+C2 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C3 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C4 sky130_fd_sc_hs__and2_1_1/a_143_136# CLK 0.03fF
+C5 nQ2 Q0 0.23fF
+C6 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C7 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C8 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C9 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
+C10 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C11 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C12 DFlipFlop_2/nQ Q1 0.31fF
+C13 DFlipFlop_3/latch_diff_0/m1_657_280# Q1 0.28fF
+C14 vdd DFlipFlop_2/nQ 0.02fF
+C15 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C16 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C17 sky130_fd_sc_hs__xor2_1_0/a_355_368# vdd 0.03fF
+C18 DFlipFlop_3/nQ CLK 0.01fF
+C19 nQ2 nQ0 0.03fF
+C20 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C21 nQ2 Q1 0.07fF
+C22 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C23 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C24 nQ0 DFlipFlop_1/latch_diff_0/D 0.09fF
+C25 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C26 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C27 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C28 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q1 0.20fF
+C29 nQ2 vdd 0.04fF
+C30 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C31 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C32 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C33 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
+C34 DFlipFlop_3/nQ nCLK 0.02fF
+C35 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C36 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK 0.14fF
+C37 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
+C38 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C39 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C40 DFlipFlop_2/D Q0 0.25fF
+C41 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C42 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C43 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
+C44 CLK Q0 0.08fF
+C45 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C46 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C47 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C48 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C49 sky130_fd_sc_hs__and2_1_0/a_56_136# Q1 0.14fF
+C50 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C51 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C52 DFlipFlop_2/D Q1 0.10fF
+C53 nQ0 CLK 0.19fF
+C54 CLK Q1 -0.10fF
+C55 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C56 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C57 Q0 nCLK 0.20fF
+C58 DFlipFlop_2/D vdd 0.07fF
+C59 CLK vdd 0.41fF
+C60 DFlipFlop_0/latch_diff_1/nD Q1 0.10fF
+C61 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C62 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C63 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C64 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C65 nQ0 nCLK 0.09fF
+C66 nCLK Q1 -0.01fF
+C67 DFlipFlop_3/nQ Q1_shift 0.04fF
+C68 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C69 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C70 vdd nCLK 0.34fF
+C71 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C72 sky130_fd_sc_hs__and2_1_1/a_56_136# CLK 0.06fF
+C73 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C74 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C75 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C76 nQ2 DFlipFlop_0/Q 0.09fF
+C77 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C78 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C79 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C80 DFlipFlop_3/nQ Q1 0.10fF
+C81 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C82 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q1 0.21fF
+C83 DFlipFlop_3/nQ vdd 0.02fF
+C84 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C85 Q1_shift Q1 0.36fF
+C86 DFlipFlop_0/D Q0 0.39fF
+C87 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C88 Q1_shift vdd 0.10fF
+C89 DFlipFlop_1/D CLK 0.21fF
+C90 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C91 nQ0 Q0 0.33fF
+C92 Q0 Q1 9.65fF
+C93 DFlipFlop_0/D Q1 0.13fF
+C94 DFlipFlop_0/Q CLK 0.08fF
+C95 vdd Q0 5.33fF
+C96 DFlipFlop_0/D vdd 0.19fF
+C97 DFlipFlop_3/latch_diff_1/nD nCLK 0.09fF
+C98 DFlipFlop_1/D nCLK 0.14fF
+C99 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C100 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C101 nQ0 Q1 0.06fF
+C102 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C103 DFlipFlop_2/latch_diff_0/D nCLK 0.11fF
+C104 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C105 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C106 DFlipFlop_0/Q nCLK 0.11fF
+C107 nQ0 vdd 0.11fF
+C108 vdd Q1 9.49fF
+C109 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C110 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
+C111 CLK DFlipFlop_2/nQ 0.13fF
+C112 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C113 nQ2 CLK 0.17fF
+C114 DFlipFlop_2/latch_diff_1/m1_657_280# Q1 0.03fF
+C115 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C116 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C117 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C118 DFlipFlop_2/nQ nCLK 0.09fF
+C119 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C120 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C121 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C122 nQ0 DFlipFlop_1/latch_diff_0/nD 0.08fF
+C123 DFlipFlop_2/latch_diff_1/nD CLK 0.09fF
+C124 sky130_fd_sc_hs__and2_1_1/a_56_136# vdd 0.04fF
+C125 nQ2 nCLK 0.10fF
+C126 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C127 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C128 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C129 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q1 0.09fF
+C130 CLK_5 vdd 0.15fF
+C131 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C132 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C133 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C134 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
+C135 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C136 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
+C137 DFlipFlop_1/D Q0 0.07fF
+C138 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C139 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C140 DFlipFlop_2/D CLK 0.14fF
+C141 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
+C142 DFlipFlop_0/Q Q0 0.21fF
+C143 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
+C144 DFlipFlop_3/latch_diff_1/nD Q1 1.24fF
+C145 DFlipFlop_1/D nQ0 0.12fF
+C146 DFlipFlop_1/D Q1 0.03fF
+C147 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C148 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C149 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C150 DFlipFlop_1/D vdd 0.25fF
+C151 DFlipFlop_2/latch_diff_0/D Q1 0.42fF
+C152 DFlipFlop_3/latch_diff_0/D CLK 0.11fF
+C153 DFlipFlop_2/D nCLK 0.41fF
+C154 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C155 DFlipFlop_0/Q Q1 0.13fF
+C156 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/nQ vss 0.52fF
+C164 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.64fF
+C170 Q1 vss 8.55fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C172 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C173 Q0 vss 0.53fF
+C174 nQ0 vss 3.42fF
+C175 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C176 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C177 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C178 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C179 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C180 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.58fF
+C181 DFlipFlop_1/D vss 3.72fF
+C182 DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C183 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C184 DFlipFlop_2/nQ vss 0.50fF
+C185 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C186 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C187 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C188 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C190 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C191 DFlipFlop_2/D vss 5.34fF
+C192 DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C193 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C194 nCLK vss 0.89fF
+C195 DFlipFlop_0/Q vss -0.94fF
+C196 nQ2 vss 2.05fF
+C197 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C198 CLK vss 0.07fF
+C199 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C200 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 vdd vss 144.09fF
+C206 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt mux2to4 vss out_b_1 vdd select_0 select_0_neg out_a_0 out_a_1 out_b_0 in_a
++ in_b
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_b vss out_b_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_3 in_b vss out_b_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 out_b_0 in_a 0.11fF
+C1 in_a select_0_neg 0.22fF
+C2 out_a_0 vdd 0.06fF
+C3 in_a select_0 0.31fF
+C4 in_b out_b_0 0.08fF
+C5 in_a vdd 0.02fF
+C6 in_b select_0_neg 0.10fF
+C7 in_b select_0 0.24fF
+C8 in_b out_b_1 0.08fF
+C9 in_b vdd 0.02fF
+C10 in_a out_a_1 0.08fF
+C11 in_b out_a_1 0.08fF
+C12 in_a out_a_0 0.08fF
+C13 out_b_0 select_0_neg -0.13fF
+C14 out_b_0 select_0 0.03fF
+C15 select_0_neg select_0 0.49fF
+C16 out_b_0 vdd 0.06fF
+C17 out_b_1 select_0 0.14fF
+C18 vdd select_0_neg 0.02fF
+C19 vdd select_0 0.02fF
+C20 out_b_1 vdd 0.06fF
+C21 out_b_0 out_a_1 0.88fF
+C22 out_a_1 select_0_neg 0.12fF
+C23 out_a_1 select_0 0.18fF
+C24 vdd out_a_1 0.06fF
+C25 out_a_0 select_0_neg 0.05fF
+C26 out_b_1 vss 0.99fF
+C27 in_b vss 2.00fF
+C28 out_b_0 vss 0.93fF
+C29 out_a_1 vss 0.22fF
+C30 vdd vss 9.53fF
+C31 in_a vss 2.00fF
+C32 out_a_0 vss 0.99fF
+C33 select_0_neg vss 2.56fF
+C34 select_0 vss 2.23fF
+.ends
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X a_304_74# a_443_74# a_524_368#
++ a_27_112#
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 A1 VPWR 0.01fF
+C1 a_223_368# a_304_74# 0.05fF
+C2 S a_27_112# 0.22fF
+C3 VPB a_27_112# 0.01fF
+C4 a_223_368# a_27_112# 0.09fF
+C5 VPWR VGND 0.02fF
+C6 X VPWR 0.28fF
+C7 a_304_74# VPWR 0.13fF
+C8 A1 VGND 0.09fF
+C9 a_226_74# a_304_74# 0.08fF
+C10 A0 A1 0.31fF
+C11 X A1 0.02fF
+C12 a_27_112# VPWR 0.99fF
+C13 a_304_74# A1 0.69fF
+C14 A0 VGND 0.02fF
+C15 X VGND 0.11fF
+C16 a_27_112# A1 0.18fF
+C17 a_304_74# VGND 0.58fF
+C18 A0 a_304_74# 0.23fF
+C19 X a_304_74# 0.29fF
+C20 S VPWR 0.05fF
+C21 VPB VPWR 0.06fF
+C22 a_27_112# VGND 0.18fF
+C23 A0 a_27_112# 0.07fF
+C24 X a_27_112# 0.08fF
+C25 a_443_74# A1 0.07fF
+C26 a_304_74# a_27_112# 0.58fF
+C27 S A1 0.10fF
+C28 a_524_368# a_27_112# 0.06fF
+C29 S VGND 0.07fF
+C30 S A0 0.04fF
+C31 a_443_74# a_304_74# 0.12fF
+C32 S a_304_74# 0.18fF
+C33 VGND VNB 0.88fF
+C34 X VNB 0.25fF
+C35 VPWR VNB 0.89fF
+C36 A1 VNB 0.37fF
+C37 A0 VNB 0.23fF
+C38 S VNB 0.34fF
+C39 VPB VNB 0.87fF
+C40 a_304_74# VNB 0.36fF
+C41 a_27_112# VNB 0.65fF
+.ends
+
+.subckt prescaler_23 nCLK vss DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_2/latch_diff_0/nD
++ vdd DFlipFlop_2/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out CLK_23 DFlipFlop_2/latch_diff_0/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_0/latch_diff_0/nD MC DFlipFlop_2/latch_diff_0/D
++ Q2
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1_0/a_304_74# sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__mux2_1_0/a_524_368#
++ sky130_fd_sc_hs__mux2_1_0/a_27_112# sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ nCLK DFlipFlop_0/latch_diff_0/nD
++ Q1 DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_0/D
++ CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK_23 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q2 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ CLK DFlipFlop_2/latch_diff_0/nD
++ Q2_d DFlipFlop_2/latch_diff_1/nD Q2 DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/latch_diff_0/D
++ nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1_0/a_143_136# sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1_1/a_152_368#
++ sky130_fd_sc_hs__or2_1_1/a_63_368# sky130_fd_sc_hs__or2_1
+C0 sky130_fd_sc_hs__and2_1_0/a_56_136# nCLK_23 0.14fF
+C1 CLK DFlipFlop_0/nQ 0.15fF
+C2 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.02fF
+C3 sky130_fd_sc_hs__or2_1_1/X Q2 0.24fF
+C4 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.10fF
+C5 CLK DFlipFlop_2/latch_diff_1/D 0.09fF
+C6 nCLK MC 0.01fF
+C7 DFlipFlop_2/latch_diff_0/D CLK 0.13fF
+C8 Q2 DFlipFlop_2/nQ 0.13fF
+C9 vdd Q2 1.63fF
+C10 CLK DFlipFlop_1/D 0.40fF
+C11 CLK nCLK_23 0.22fF
+C12 sky130_fd_sc_hs__mux2_1_0/a_27_112# nCLK_23 0.07fF
+C13 sky130_fd_sc_hs__and2_1_0/a_56_136# CLK 0.08fF
+C14 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C15 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.31fF
+C16 sky130_fd_sc_hs__or2_1_0/a_152_368# nCLK 0.01fF
+C17 Q2_d sky130_fd_sc_hs__or2_1_1/X 0.03fF
+C18 CLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.33fF
+C19 sky130_fd_sc_hs__or2_1_1/a_63_368# Q2 0.09fF
+C20 Q2 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.38fF
+C21 DFlipFlop_2/latch_diff_1/D Q2 0.13fF
+C22 MC sky130_fd_sc_hs__or2_1_0/X 0.09fF
+C23 Q2_d vdd 0.02fF
+C24 DFlipFlop_2/latch_diff_0/D Q2 0.30fF
+C25 nCLK sky130_fd_sc_hs__or2_1_0/X 0.06fF
+C26 MC Q1 0.29fF
+C27 sky130_fd_sc_hs__or2_1_1/X MC 0.02fF
+C28 nCLK Q1 -0.02fF
+C29 nCLK_23 Q2 0.03fF
+C30 vdd MC 0.88fF
+C31 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.29fF
+C32 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.31fF
+C33 nCLK vdd -0.55fF
+C34 nCLK DFlipFlop_2/nQ 0.02fF
+C35 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C36 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.06fF
+C37 Q2_d DFlipFlop_2/latch_diff_1/D 0.03fF
+C38 DFlipFlop_0/latch_diff_1/m1_657_280# Q1 0.06fF
+C39 CLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.05fF
+C40 nCLK DFlipFlop_1/latch_diff_1/nD 0.18fF
+C41 nCLK_23 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.49fF
+C42 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1 0.01fF
+C43 CLK DFlipFlop_2/latch_diff_1/nD 0.19fF
+C44 CLK_23 vdd 0.16fF
+C45 nCLK_23 DFlipFlop_0/latch_diff_1/D 0.05fF
+C46 CLK Q2 0.29fF
+C47 nCLK DFlipFlop_0/nQ 0.11fF
+C48 nCLK DFlipFlop_2/latch_diff_1/D 0.16fF
+C49 Q1 sky130_fd_sc_hs__or2_1_0/X 0.06fF
+C50 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_524_368# 0.04fF
+C51 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_443_74# 0.03fF
+C52 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.08fF
+C53 vdd sky130_fd_sc_hs__or2_1_0/X 0.03fF
+C54 DFlipFlop_1/latch_diff_1/D CLK 0.18fF
+C55 MC nCLK_23 4.46fF
+C56 nCLK DFlipFlop_1/D 0.16fF
+C57 Q2_d DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C58 nCLK sky130_fd_sc_hs__or2_1_0/a_63_368# 0.05fF
+C59 nCLK nCLK_23 0.11fF
+C60 vdd Q1 0.07fF
+C61 vdd sky130_fd_sc_hs__or2_1_1/X 0.03fF
+C62 DFlipFlop_0/latch_diff_1/nD Q1 0.03fF
+C63 CLK DFlipFlop_0/latch_diff_1/D 0.04fF
+C64 DFlipFlop_2/latch_diff_1/nD Q2 0.17fF
+C65 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C66 nCLK_23 DFlipFlop_0/latch_diff_0/nD 0.12fF
+C67 Q1 DFlipFlop_0/nQ -0.02fF
+C68 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C69 CLK MC 0.08fF
+C70 sky130_fd_sc_hs__mux2_1_0/a_27_112# MC 0.24fF
+C71 DFlipFlop_1/D sky130_fd_sc_hs__or2_1_0/X 0.35fF
+C72 nCLK_23 sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C73 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C74 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_443_74# 0.09fF
+C75 sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C76 nCLK DFlipFlop_2/latch_diff_0/nD 0.09fF
+C77 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.09fF
+C78 Q1 nCLK_23 0.02fF
+C79 nCLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.31fF
+C80 sky130_fd_sc_hs__mux2_1_0/a_304_74# nCLK_23 0.04fF
+C81 sky130_fd_sc_hs__or2_1_1/X nCLK_23 0.26fF
+C82 Q2_d Q2 0.66fF
+C83 vdd DFlipFlop_1/D 0.07fF
+C84 DFlipFlop_1/latch_diff_0/nD CLK 0.09fF
+C85 vdd nCLK_23 3.27fF
+C86 DFlipFlop_0/latch_diff_1/nD nCLK_23 0.02fF
+C87 nCLK DFlipFlop_2/latch_diff_1/nD 0.12fF
+C88 MC Q2 0.18fF
+C89 nCLK DFlipFlop_1/latch_diff_0/D 0.02fF
+C90 nCLK Q2 0.29fF
+C91 CLK sky130_fd_sc_hs__or2_1_0/X 0.01fF
+C92 CLK Q1 -0.07fF
+C93 nCLK_23 DFlipFlop_0/nQ 0.05fF
+C94 sky130_fd_sc_hs__and2_1_0/a_143_136# nCLK_23 0.02fF
+C95 DFlipFlop_1/latch_diff_1/D nCLK 0.09fF
+C96 vdd CLK 0.34fF
+C97 CLK DFlipFlop_2/nQ 0.02fF
+C98 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C99 DFlipFlop_1/D nCLK_23 0.02fF
+C100 CLK DFlipFlop_1/latch_diff_1/nD 0.11fF
+C101 sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C102 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C103 sky130_fd_sc_hs__or2_1_0/X vss 0.92fF
+C104 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.39fF
+C105 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C106 Q2_d vss -0.22fF
+C107 DFlipFlop_2/nQ vss 0.48fF
+C108 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C109 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C110 DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C111 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C112 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C113 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.63fF
+C114 Q2 vss 1.35fF
+C115 DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C116 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.72fF
+C117 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C118 DFlipFlop_1/latch_diff_1/D vss -1.72fF
+C119 DFlipFlop_1/latch_diff_1/nD vss 0.58fF
+C120 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C121 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C122 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C123 DFlipFlop_1/D vss 2.98fF
+C124 DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C125 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C126 nCLK vss -1.56fF
+C127 Q1 vss 0.50fF
+C128 DFlipFlop_0/nQ vss 0.48fF
+C129 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C130 CLK vss -0.69fF
+C131 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C132 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C133 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C134 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C135 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C136 nCLK_23 vss -0.65fF
+C137 vdd vss 113.67fF
+C138 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C139 CLK_23 vss -0.57fF
+C140 sky130_fd_sc_hs__or2_1_1/X vss -0.35fF
+C141 MC vss 2.09fF
+C142 sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.41fF
+C143 sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.69fF
+.ends
+
+.subckt freq_div clk_0 vss n_clk_0 vdd s_0 prescaler_23_0/Q2 s_1_n s_1 prescaler_23_0/nCLK_23
++ prescaler_23_0/MC clk_d prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n
++ clk_pre div_by_5_0/DFlipFlop_2/latch_diff_0/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out div_by_5_0/Q1 div_by_5_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD clk_2 in_a in_b clk_5 prescaler_23_0/DFlipFlop_2/latch_diff_0/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD div_by_5_0/DFlipFlop_2/latch_diff_1/D
+Xdiv_by_2_0 vdd vss div_by_2_0/nout_div clk_2 div_by_2_0/nCLK_2 div_by_2_0/o1 div_by_2_0/o2
++ clk_out_mux21 div_by_2_0/out_div div_by_2
+Xmux2to1_0 vss s_0_n clk_pre clk_5 s_0 vdd clk_out_mux21 mux2to1
+Xinverter_min_x4_0 inverter_min_x4_0/in vss clk_d vdd inverter_min_x4
+Xmux2to1_1 vss s_1_n clk_d clk_2 s_1 vdd out mux2to1
+Xinverter_min_x2_0 clk_out_mux21 inverter_min_x4_0/in vss vdd inverter_min_x2
+Xinverter_min_x2_1 s_1 s_1_n vss vdd inverter_min_x2
+Xinverter_min_x2_2 s_0 s_0_n vss vdd inverter_min_x2
+Xdiv_by_5_0 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ vss div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in clk_1
++ div_by_5_0/DFlipFlop_0/Q vdd div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# clk_5 div_by_5_0/Q1_shift div_by_5_0/nQ2
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_by_5_0/DFlipFlop_1/D div_by_5_0/nQ0 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/Q0 div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xmux2to4_0 vss n_clk_1 vdd s_0 s_0_n clk_0 clk_1 n_clk_0 in_a in_b mux2to4
+Xprescaler_23_0 n_clk_0 vss prescaler_23_0/DFlipFlop_0/latch_diff_1/nD prescaler_23_0/nCLK_23
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vdd prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ clk_pre prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# prescaler_23_0/DFlipFlop_0/latch_diff_0/D
++ clk_0 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280#
++ prescaler_23_0/DFlipFlop_0/latch_diff_1/D prescaler_23_0/DFlipFlop_0/latch_diff_0/nD
++ prescaler_23_0/MC prescaler_23_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/Q2 prescaler_23
+C0 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_clk_1 0.06fF
+C1 div_by_5_0/Q1_shift clk_5 0.04fF
+C2 div_by_5_0/nQ0 s_0 0.05fF
+C3 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_clk_1 0.11fF
+C4 div_by_5_0/nQ0 s_0_n 0.05fF
+C5 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD n_clk_0 0.13fF
+C6 prescaler_23_0/DFlipFlop_0/latch_diff_1/D n_clk_0 0.09fF
+C7 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.08fF
+C8 div_by_5_0/DFlipFlop_0/latch_diff_0/nD s_0 0.12fF
+C9 div_by_5_0/DFlipFlop_0/latch_diff_0/nD s_0_n 0.20fF
+C10 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/Q1 -0.06fF
+C11 div_by_5_0/nQ2 s_0 0.05fF
+C12 div_by_5_0/DFlipFlop_1/latch_diff_1/D s_0 0.05fF
+C13 in_b s_0_n 0.48fF
+C14 div_by_5_0/nQ2 s_0_n 0.05fF
+C15 div_by_5_0/DFlipFlop_1/latch_diff_1/D s_0_n 0.04fF
+C16 clk_1 vdd 0.16fF
+C17 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in s_0 -0.36fF
+C18 clk_1 div_by_5_0/DFlipFlop_0/D 0.14fF
+C19 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in s_0_n -0.37fF
+C20 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.08fF
+C21 div_by_5_0/DFlipFlop_1/D s_0 0.03fF
+C22 div_by_5_0/DFlipFlop_1/D s_0_n 0.19fF
+C23 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.11fF
+C24 s_0 div_by_5_0/DFlipFlop_3/nQ 0.02fF
+C25 div_by_5_0/Q0 n_clk_1 0.01fF
+C26 s_0_n div_by_5_0/DFlipFlop_3/nQ 0.24fF
+C27 clk_1 in_a 0.05fF
+C28 clk_d s_1 0.22fF
+C29 clk_1 s_0 1.36fF
+C30 div_by_5_0/Q1 vdd -0.02fF
+C31 clk_1 s_0_n 4.82fF
+C32 div_by_5_0/DFlipFlop_0/D div_by_5_0/Q1 -0.02fF
+C33 div_by_5_0/DFlipFlop_2/nQ s_0 0.05fF
+C34 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_clk_1 0.11fF
+C35 div_by_5_0/DFlipFlop_1/latch_diff_1/nD s_0 0.02fF
+C36 div_by_5_0/DFlipFlop_2/nQ s_0_n 0.04fF
+C37 div_by_5_0/DFlipFlop_1/latch_diff_1/nD s_0_n 0.24fF
+C38 clk_0 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C39 clk_0 vdd 0.63fF
+C40 clk_out_mux21 vdd 0.14fF
+C41 out clk_2 0.05fF
+C42 s_0 div_by_5_0/Q1 0.04fF
+C43 clk_0 prescaler_23_0/nCLK_23 0.16fF
+C44 s_0_n div_by_5_0/Q1 0.21fF
+C45 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out s_0 -0.19fF
+C46 s_0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.12fF
+C47 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out s_0_n -0.29fF
+C48 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.20fF
+C49 n_clk_1 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C50 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD 0.09fF
+C51 clk_d vdd 0.23fF
+C52 div_by_5_0/DFlipFlop_3/latch_diff_1/nD s_0 0.05fF
+C53 s_0 vdd 3.67fF
+C54 s_0 div_by_5_0/DFlipFlop_0/D 0.03fF
+C55 inverter_min_x4_0/in vdd 0.09fF
+C56 clk_out_mux21 s_0 0.68fF
+C57 div_by_5_0/DFlipFlop_3/latch_diff_1/nD s_0_n 0.04fF
+C58 s_0_n vdd 2.53fF
+C59 div_by_5_0/DFlipFlop_0/D s_0_n 0.05fF
+C60 clk_out_mux21 s_0_n 0.45fF
+C61 div_by_5_0/DFlipFlop_0/latch_diff_1/nD s_0 0.02fF
+C62 clk_1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
+C63 div_by_5_0/DFlipFlop_0/latch_diff_1/nD s_0_n 0.24fF
+C64 s_0 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.10fF
+C65 n_clk_1 in_b 0.05fF
+C66 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.17fF
+C67 clk_1 n_clk_0 -0.03fF
+C68 out s_1 0.39fF
+C69 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.05fF
+C70 out s_1_n 0.33fF
+C71 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD 0.09fF
+C72 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.04fF
+C73 div_by_5_0/Q0 vdd 0.05fF
+C74 s_0 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.02fF
+C75 s_0 in_a 0.30fF
+C76 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/D 0.13fF
+C77 div_by_5_0/DFlipFlop_3/latch_diff_1/D s_0_n 0.24fF
+C78 clk_d inverter_min_x4_0/in 0.11fF
+C79 s_0 s_0_n 7.76fF
+C80 div_by_5_0/DFlipFlop_2/latch_diff_0/nD s_0 0.12fF
+C81 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0 0.05fF
+C82 div_by_5_0/DFlipFlop_2/latch_diff_0/nD s_0_n 0.20fF
+C83 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0_n 0.04fF
+C84 clk_pre vdd 0.17fF
+C85 div_by_5_0/DFlipFlop_2/D s_0 0.03fF
+C86 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.08fF
+C87 clk_out_mux21 clk_pre 1.19fF
+C88 div_by_5_0/DFlipFlop_2/D s_0_n 0.05fF
+C89 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0 0.02fF
+C90 div_by_5_0/Q1_shift s_0 0.05fF
+C91 div_by_5_0/Q0 s_0 0.02fF
+C92 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0_n 0.24fF
+C93 div_by_5_0/Q1_shift s_0_n 0.04fF
+C94 clk_pre prescaler_23_0/nCLK_23 0.03fF
+C95 div_by_5_0/Q0 s_0_n 0.24fF
+C96 clk_2 s_1_n 0.59fF
+C97 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# s_0_n 0.05fF
+C98 vdd clk_5 0.04fF
+C99 clk_out_mux21 clk_5 0.05fF
+C100 n_clk_1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C101 vdd n_clk_0 0.25fF
+C102 s_0 div_by_5_0/DFlipFlop_0/Q 0.02fF
+C103 prescaler_23_0/DFlipFlop_0/latch_diff_0/D n_clk_0 0.13fF
+C104 clk_pre s_0 0.21fF
+C105 div_by_5_0/DFlipFlop_0/Q s_0_n 0.24fF
+C106 prescaler_23_0/nCLK_23 n_clk_0 0.16fF
+C107 n_clk_1 div_by_5_0/Q1 0.15fF
+C108 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_clk_0 0.14fF
+C109 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out s_0 -0.13fF
+C110 s_1 s_1_n 0.39fF
+C111 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out s_0_n -0.01fF
+C112 s_0_n clk_5 0.56fF
+C113 s_0_n n_clk_0 0.31fF
+C114 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# div_by_5_0/Q1_shift -0.02fF
+C115 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out s_0 0.30fF
+C116 clk_2 vdd 0.02fF
+C117 n_clk_1 vdd 0.13fF
+C118 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out s_0_n 0.31fF
+C119 n_clk_1 div_by_5_0/DFlipFlop_0/D 0.21fF
+C120 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C121 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C122 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C123 prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C124 prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C125 prescaler_23_0/Q2_d vss -0.69fF
+C126 prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C127 prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C128 prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C129 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C130 prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C131 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C132 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C133 prescaler_23_0/Q2 vss 0.55fF
+C134 prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C135 prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C136 prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C137 prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C138 prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C139 prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C140 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C141 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C142 prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C143 prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C144 prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C145 n_clk_0 vss -5.35fF
+C146 prescaler_23_0/Q1 vss 0.07fF
+C147 prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C148 prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C149 clk_0 vss 0.66fF
+C150 prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C151 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C152 prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C153 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C155 prescaler_23_0/nCLK_23 vss -1.02fF
+C156 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C157 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C158 prescaler_23_0/MC vss 1.07fF
+C159 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C160 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C161 in_b vss 2.02fF
+C162 in_a vss 2.01fF
+C163 s_0_n vss -2.51fF
+C164 s_0 vss 5.84fF
+C165 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C166 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C167 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C168 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C169 div_by_5_0/Q1_shift vss -0.36fF
+C170 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C171 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C172 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C174 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C177 div_by_5_0/Q1 vss 4.35fF
+C178 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C179 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C180 div_by_5_0/Q0 vss 0.29fF
+C181 div_by_5_0/nQ0 vss 0.99fF
+C182 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C183 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C184 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C185 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C186 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C187 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C188 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C189 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C190 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C191 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C192 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C193 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C194 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C195 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C196 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C197 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C198 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C199 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C200 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C201 n_clk_1 vss -0.55fF
+C202 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C203 div_by_5_0/nQ2 vss 1.38fF
+C204 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C205 clk_1 vss -1.34fF
+C206 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C207 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C208 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C209 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C210 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C211 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C212 vdd vss 344.01fF
+C213 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C214 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C215 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C216 out vss 0.93fF
+C217 clk_d vss 0.78fF
+C218 s_1_n vss 1.22fF
+C219 s_1 vss 2.97fF
+C220 inverter_min_x4_0/in vss 2.77fF
+C221 clk_out_mux21 vss 5.29fF
+C222 clk_pre vss 1.30fF
+C223 clk_2 vss 3.46fF
+C224 div_by_2_0/o1 vss 2.20fF
+C225 div_by_2_0/nCLK_2 vss 1.04fF
+C226 div_by_2_0/o2 vss 2.08fF
+C227 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C228 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C229 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C230 div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C231 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C232 div_by_2_0/out_div vss -0.80fF
+C233 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C234 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C235 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C236 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C237 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C238 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C239 div_by_2_0/nout_div vss 2.62fF
+C240 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n221_n600# a_n129_n600# 7.87fF
+C1 a_n129_n600# a_n257_n777# 0.29fF
+C2 a_n221_n600# a_n257_n777# 0.25fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n257_n404# a_n129_n300# 0.30fF
+C1 a_n257_n404# a_n221_n300# 0.21fF
+C2 a_n129_n300# a_n221_n300# 4.05fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out vdd in vss
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 vdd in 0.02fF
+C1 a_3996_n100# out 55.19fF
+C2 vdd out 47.17fF
+C3 a_678_n100# a_3996_n100# 6.52fF
+C4 vdd a_3996_n100# 3.68fF
+C5 a_678_n100# in 0.81fF
+C6 vdd a_678_n100# 0.08fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n33_n238# 0.02fF
+C1 a_n73_n150# a_n33_n238# 0.02fF
+C2 a_15_n150# a_n73_n150# 0.51fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# w_n211_n369# 0.20fF
+C1 a_n73_n150# w_n211_n369# 0.20fF
+C2 a_n33_181# w_n211_n369# 0.05fF
+C3 a_15_n150# a_n73_n150# 0.51fF
+C4 a_15_n150# a_n33_181# 0.01fF
+C5 a_n73_n150# a_n33_181# 0.01fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_351_n150# a_159_n150# 0.16fF
+C1 a_n225_n150# a_n417_n150# 0.16fF
+C2 a_n225_n150# a_n509_n150# 0.10fF
+C3 a_n321_n150# a_n465_172# 0.10fF
+C4 a_351_n150# a_447_n150# 0.43fF
+C5 a_n321_n150# a_n33_n150# 0.10fF
+C6 a_159_n150# a_n465_172# 0.10fF
+C7 a_n417_n150# a_n465_172# 0.10fF
+C8 a_n129_n150# a_63_n150# 0.16fF
+C9 a_n509_n150# a_n465_172# 0.01fF
+C10 a_447_n150# a_n465_172# 0.01fF
+C11 a_n225_n150# a_n465_172# 0.10fF
+C12 a_351_n150# a_n465_172# 0.10fF
+C13 a_159_n150# a_n33_n150# 0.16fF
+C14 a_159_n150# a_255_n150# 0.43fF
+C15 a_n33_n150# a_n417_n150# 0.07fF
+C16 a_n225_n150# a_n33_n150# 0.16fF
+C17 a_447_n150# a_255_n150# 0.16fF
+C18 a_351_n150# a_n33_n150# 0.07fF
+C19 a_351_n150# a_255_n150# 0.43fF
+C20 a_63_n150# a_n321_n150# 0.07fF
+C21 a_n129_n150# a_n321_n150# 0.16fF
+C22 a_n33_n150# a_n465_172# 0.10fF
+C23 a_255_n150# a_n465_172# 0.10fF
+C24 a_63_n150# a_159_n150# 0.43fF
+C25 a_n129_n150# a_159_n150# 0.10fF
+C26 a_n129_n150# a_n417_n150# 0.10fF
+C27 a_n129_n150# a_n509_n150# 0.07fF
+C28 a_63_n150# a_447_n150# 0.07fF
+C29 a_255_n150# a_n33_n150# 0.10fF
+C30 a_n225_n150# a_63_n150# 0.10fF
+C31 a_63_n150# a_351_n150# 0.10fF
+C32 a_n225_n150# a_n129_n150# 0.43fF
+C33 a_63_n150# a_n465_172# 0.10fF
+C34 a_n129_n150# a_n465_172# 0.10fF
+C35 a_n321_n150# a_n417_n150# 0.43fF
+C36 a_n321_n150# a_n509_n150# 0.16fF
+C37 a_63_n150# a_n33_n150# 0.43fF
+C38 a_63_n150# a_255_n150# 0.16fF
+C39 a_n225_n150# a_n321_n150# 0.43fF
+C40 a_n129_n150# a_n33_n150# 0.43fF
+C41 a_n129_n150# a_255_n150# 0.07fF
+C42 a_n417_n150# a_n509_n150# 0.43fF
+C43 a_447_n150# a_159_n150# 0.10fF
+C44 a_n225_n150# a_159_n150# 0.07fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n509_n150# w_n647_n369# 0.14fF
+C1 a_n417_n150# a_n321_n150# 0.43fF
+C2 a_n509_n150# a_n321_n150# 0.16fF
+C3 a_n129_n150# a_63_n150# 0.16fF
+C4 a_n129_n150# w_n647_n369# 0.02fF
+C5 a_n129_n150# a_n321_n150# 0.16fF
+C6 a_159_n150# a_255_n150# 0.43fF
+C7 a_n509_n150# a_n417_n150# 0.43fF
+C8 a_n129_n150# a_n417_n150# 0.10fF
+C9 a_n33_n150# a_159_n150# 0.16fF
+C10 a_n129_n150# a_n509_n150# 0.07fF
+C11 a_n225_n150# a_n465_n247# 0.08fF
+C12 a_n33_n150# a_255_n150# 0.10fF
+C13 a_63_n150# a_n465_n247# 0.08fF
+C14 a_351_n150# a_n465_n247# 0.08fF
+C15 w_n647_n369# a_n465_n247# 0.47fF
+C16 a_n465_n247# a_n321_n150# 0.08fF
+C17 a_n417_n150# a_n465_n247# 0.08fF
+C18 a_159_n150# a_n225_n150# 0.07fF
+C19 a_n129_n150# a_n465_n247# 0.08fF
+C20 a_159_n150# a_447_n150# 0.10fF
+C21 a_159_n150# a_63_n150# 0.43fF
+C22 a_351_n150# a_159_n150# 0.16fF
+C23 a_159_n150# w_n647_n369# 0.04fF
+C24 a_n33_n150# a_n225_n150# 0.16fF
+C25 a_447_n150# a_255_n150# 0.16fF
+C26 a_255_n150# a_63_n150# 0.16fF
+C27 a_351_n150# a_255_n150# 0.43fF
+C28 a_255_n150# w_n647_n369# 0.05fF
+C29 a_n33_n150# a_63_n150# 0.43fF
+C30 a_351_n150# a_n33_n150# 0.07fF
+C31 a_n33_n150# w_n647_n369# 0.02fF
+C32 a_159_n150# a_n129_n150# 0.10fF
+C33 a_n33_n150# a_n321_n150# 0.10fF
+C34 a_n33_n150# a_n417_n150# 0.07fF
+C35 a_n129_n150# a_255_n150# 0.07fF
+C36 a_n33_n150# a_n129_n150# 0.43fF
+C37 a_n225_n150# a_63_n150# 0.10fF
+C38 a_n225_n150# w_n647_n369# 0.04fF
+C39 a_159_n150# a_n465_n247# 0.08fF
+C40 a_n225_n150# a_n321_n150# 0.43fF
+C41 a_447_n150# a_63_n150# 0.07fF
+C42 a_n225_n150# a_n417_n150# 0.16fF
+C43 a_351_n150# a_447_n150# 0.43fF
+C44 a_351_n150# a_63_n150# 0.10fF
+C45 a_255_n150# a_n465_n247# 0.08fF
+C46 a_447_n150# w_n647_n369# 0.14fF
+C47 w_n647_n369# a_63_n150# 0.02fF
+C48 a_351_n150# w_n647_n369# 0.07fF
+C49 a_n225_n150# a_n509_n150# 0.10fF
+C50 a_63_n150# a_n321_n150# 0.07fF
+C51 w_n647_n369# a_n321_n150# 0.05fF
+C52 a_n225_n150# a_n129_n150# 0.43fF
+C53 a_n33_n150# a_n465_n247# 0.08fF
+C54 a_n417_n150# w_n647_n369# 0.07fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_15_n11# 0.15fF
+C1 a_n73_n11# a_n33_n99# 0.02fF
+C2 a_15_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# w_n216_n334# 0.20fF
+C1 a_20_n114# a_n78_n114# 0.42fF
+C2 a_20_n114# w_n216_n334# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in out 0.11fF
+C1 vdd in 0.01fF
+C2 vss in 0.01fF
+C3 out vbulkp 0.08fF
+C4 vdd vbulkp 0.04fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 vss out vdd inverter_csvco_0/vss
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 inverter_csvco_0/vdd out 0.02fF
+C1 inverter_csvco_0/vss out 0.03fF
+C2 inverter_csvco_0/vdd vdd 1.89fF
+C3 in out 0.06fF
+C4 inverter_csvco_0/vss vctrl 0.87fF
+C5 inverter_csvco_0/vdd in 0.01fF
+C6 inverter_csvco_0/vss in 0.01fF
+C7 D0 out 0.09fF
+C8 out cap_vco_0/t 0.70fF
+C9 D0 inverter_csvco_0/vss 0.02fF
+C10 vbp vdd 1.21fF
+C11 vdd cap_vco_0/t 0.04fF
+C12 inverter_csvco_0/vdd vbp 0.75fF
+C13 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vss vdd csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 vss
++ csvco_branch_1/in vdd csvco_branch_0/inverter_csvco_0/vss csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 vss out_vco vdd csvco_branch_2/inverter_csvco_0/vss csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 vss csvco_branch_2/in vdd csvco_branch_1/inverter_csvco_0/vss csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
+C1 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C2 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
+C3 csvco_branch_2/in out_vco 0.58fF
+C4 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
+C5 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C6 out_vco csvco_branch_1/in 0.76fF
+C7 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C8 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C9 vctrl D0 4.41fF
+C10 csvco_branch_2/vbp vdd 1.49fF
+C11 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C12 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss 0.06fF
+C13 csvco_branch_2/vbp vctrl 0.06fF
+C14 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 out_div o1 0.11fF
+C1 out_div out_pad 0.15fF
+C2 o1 vdd 0.09fF
+C3 vdd out_pad 0.10fF
+C4 out_div vdd 0.17fF
+C5 vdd vss 14.54fF
+C6 in_vco vss 0.83fF
+C7 out_pad vss 0.70fF
+C8 out_div vss 3.00fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n317_n125# a_63_n125# 0.06fF
+C1 a_n317_n125# a_n33_n125# 0.08fF
+C2 a_n317_n125# a_n129_n125# 0.13fF
+C3 a_n317_n125# a_n225_n125# 0.36fF
+C4 a_n63_n151# a_n159_n151# 0.02fF
+C5 a_n255_n151# a_n159_n151# 0.02fF
+C6 a_255_n125# a_63_n125# 0.13fF
+C7 a_225_n151# a_129_n151# 0.02fF
+C8 a_255_n125# a_n33_n125# 0.08fF
+C9 a_255_n125# a_n129_n125# 0.06fF
+C10 a_n33_n125# a_63_n125# 0.36fF
+C11 a_255_n125# a_159_n125# 0.36fF
+C12 a_n129_n125# a_63_n125# 0.13fF
+C13 a_n33_n125# a_n129_n125# 0.36fF
+C14 a_159_n125# a_63_n125# 0.36fF
+C15 a_n33_n125# a_159_n125# 0.13fF
+C16 a_n129_n125# a_159_n125# 0.08fF
+C17 a_63_n125# a_n225_n125# 0.08fF
+C18 a_n33_n125# a_n225_n125# 0.13fF
+C19 a_n129_n125# a_n225_n125# 0.36fF
+C20 a_129_n151# a_33_n151# 0.02fF
+C21 a_33_n151# a_n63_n151# 0.02fF
+C22 a_159_n125# a_n225_n125# 0.06fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n33_n125# a_n317_n125# 0.08fF
+C1 a_63_n125# a_n317_n125# 0.06fF
+C2 a_n129_n125# a_n317_n125# 0.13fF
+C3 w_n455_n344# a_n317_n125# 0.11fF
+C4 a_n225_n125# a_n317_n125# 0.36fF
+C5 a_n33_n125# a_63_n125# 0.36fF
+C6 a_n33_n125# a_n129_n125# 0.36fF
+C7 a_33_n154# a_129_n154# 0.02fF
+C8 a_63_n125# a_n129_n125# 0.13fF
+C9 a_n33_n125# a_159_n125# 0.13fF
+C10 a_159_n125# a_63_n125# 0.36fF
+C11 a_n33_n125# w_n455_n344# 0.05fF
+C12 a_n33_n125# a_n225_n125# 0.13fF
+C13 w_n455_n344# a_63_n125# 0.04fF
+C14 a_n225_n125# a_63_n125# 0.08fF
+C15 a_n255_n154# a_n159_n154# 0.02fF
+C16 a_n33_n125# a_255_n125# 0.08fF
+C17 a_63_n125# a_255_n125# 0.13fF
+C18 a_33_n154# a_n63_n154# 0.02fF
+C19 a_159_n125# a_n129_n125# 0.08fF
+C20 w_n455_n344# a_n129_n125# 0.04fF
+C21 a_n225_n125# a_n129_n125# 0.36fF
+C22 w_n455_n344# a_159_n125# 0.06fF
+C23 a_159_n125# a_n225_n125# 0.06fF
+C24 a_225_n154# a_129_n154# 0.02fF
+C25 a_n129_n125# a_255_n125# 0.06fF
+C26 a_n63_n154# a_n159_n154# 0.02fF
+C27 w_n455_n344# a_n225_n125# 0.06fF
+C28 a_159_n125# a_255_n125# 0.36fF
+C29 w_n455_n344# a_255_n125# 0.11fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 vdd in 0.04fF
+C1 out vdd 0.29fF
+C2 out in 0.85fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss vdd inverter_cp_x1_0/out inverter_cp_x1_2/in Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown vss inverter_cp_x1_0/out vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_0/out nDown 0.11fF
+C1 Down inverter_cp_x1_0/out 0.12fF
+C2 Up vdd 0.60fF
+C3 Down nDown 0.23fF
+C4 inverter_cp_x1_0/out vdd 0.18fF
+C5 QA vdd 0.02fF
+C6 inverter_cp_x1_2/in Up 0.12fF
+C7 nUp vdd 0.14fF
+C8 QB vdd 0.02fF
+C9 vdd nDown 0.80fF
+C10 Up nUp 0.20fF
+C11 inverter_cp_x1_2/in vdd 0.42fF
+C12 inverter_cp_x1_2/in vss 2.01fF
+C13 QA vss 1.09fF
+C14 inverter_cp_x1_0/out vss 1.72fF
+C15 QB vss 1.09fF
+C16 vdd vss 28.20fF
+C17 nUp vss 1.32fF
+C18 Up vss 2.53fF
+C19 Down vss 1.17fF
+C20 nDown vss 2.77fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_159_n90# a_n129_n90# 0.06fF
+C1 a_159_n90# a_n33_n90# 0.09fF
+C2 a_n129_n90# a_n33_n90# 0.26fF
+C3 a_n63_n116# a_n159_n207# 0.12fF
+C4 a_63_n90# a_n221_n90# 0.06fF
+C5 w_n359_n309# a_n221_n90# 0.09fF
+C6 w_n359_n309# a_63_n90# 0.06fF
+C7 a_159_n90# a_n221_n90# 0.04fF
+C8 a_159_n90# a_63_n90# 0.26fF
+C9 a_159_n90# w_n359_n309# 0.09fF
+C10 a_n221_n90# a_n129_n90# 0.26fF
+C11 a_63_n90# a_n129_n90# 0.09fF
+C12 a_n221_n90# a_n33_n90# 0.09fF
+C13 a_63_n90# a_n33_n90# 0.26fF
+C14 w_n359_n309# a_n129_n90# 0.06fF
+C15 w_n359_n309# a_n33_n90# 0.05fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_71# a_33_n71# 0.04fF
+C1 a_63_n45# a_n33_n45# 0.13fF
+C2 a_63_n45# a_n125_n45# 0.05fF
+C3 a_n125_n45# a_n33_n45# 0.13fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C1 out B 0.40fF
+C2 A out 0.06fF
+C3 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C4 A vdd 0.09fF
+C5 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C6 out vdd 0.11fF
+C7 A B 0.24fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A Reset nor_pfd_2/B
+Xnor_pfd_0 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss CLK Q nor_pfd
+Xnor_pfd_1 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_3/A Reset nor_pfd
+C0 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C1 vdd nor_pfd_2/B 0.02fF
+C2 CLK Q 0.04fF
+C3 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C4 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C5 nor_pfd_3/A vdd 0.09fF
+C6 nor_pfd_2/A vdd -0.01fF
+C7 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C8 vdd Q 0.08fF
+C9 Reset nor_pfd_2/B 0.43fF
+C10 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C11 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C12 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C13 nor_pfd_3/A Reset 0.12fF
+C14 Q nor_pfd_2/B 2.22fF
+C15 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C16 Reset Q 0.14fF
+C17 nor_pfd_3/A Q 0.98fF
+C18 nor_pfd_2/A Q 1.38fF
+C19 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_n45# a_n221_n45# 0.13fF
+C1 a_63_n45# a_n221_n45# 0.03fF
+C2 a_159_n45# a_n33_n45# 0.05fF
+C3 a_159_n45# a_n129_n45# 0.03fF
+C4 a_n159_n173# a_n63_n71# 0.10fF
+C5 a_n129_n45# a_n33_n45# 0.13fF
+C6 a_159_n45# a_63_n45# 0.13fF
+C7 a_63_n45# a_n33_n45# 0.13fF
+C8 a_159_n45# a_n221_n45# 0.02fF
+C9 a_n33_n45# a_n221_n45# 0.05fF
+C10 a_n129_n45# a_63_n45# 0.05fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_33_n187# a_n99_n187# 0.04fF
+C1 a_n33_n90# a_63_n90# 0.26fF
+C2 a_n125_n90# a_63_n90# 0.09fF
+C3 a_n125_n90# a_n33_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_15_n45# a_n73_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_15_n90# a_n73_n90# 0.31fF
+C1 w_n211_n309# a_n73_n90# 0.04fF
+C2 w_n211_n309# a_15_n90# 0.09fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# out vss vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C1 vdd a_656_410# 0.20fF
+C2 A vdd 0.05fF
+C3 out vdd 0.10fF
+C4 B a_656_410# 0.30fF
+C5 B A 0.33fF
+C6 A a_656_410# 0.04fF
+C7 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C8 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
+C9 out a_656_410# 0.20fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Reset Down Up A B
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A Reset dff_pfd_0/nor_pfd_2/B
++ dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A Reset dff_pfd_1/nor_pfd_2/B
++ dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# Reset vss vdd Up Down and_pfd
+C0 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C1 dff_pfd_1/nor_pfd_2/B vdd 0.04fF
+C2 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
+C3 vdd Reset 0.02fF
+C4 Down Up 0.06fF
+C5 Down vdd 0.08fF
+C6 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C7 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C8 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
+C9 vdd Up 1.62fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v3 pfd_reset in_ref QA QB Down nDown Up nUp biasp pswitch nswitch
++ vco_vctrl vco_out out_first_buffer out_to_div iref_cp vdd n_clk_1 clk_1 clk_5 clk_pre
++ clk_out_mux21 clk_d clk_2_f out_div s_1 s_1_n MC lf_vc vco_D0
+Xcharge_pump_0 nswitch vss vdd nUp Down charge_pump_0/w_2544_775# vco_vctrl pswitch
++ iref_cp nDown biasp Up vss charge_pump
+Xloop_filter_v2_0 lf_vc lf_D0 vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vdd vss n_out_div_2 out_by_2 n_out_by_2 out_buffer_div_2 n_out_buffer_div_2
++ out_to_div out_div_2 div_by_2
+Xfreq_div_0 clk_0 vss n_clk_0 vdd s_0 freq_div_0/prescaler_23_0/Q2 s_1_n s_1 freq_div_0/prescaler_23_0/nCLK_23
++ MC clk_d freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n clk_pre
++ freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out_div freq_div_0/div_by_5_0/Q1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ clk_2_f out_by_2 n_out_by_2 clk_5 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D
++ freq_div
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad vdd out_to_buffer vss buffer_salida
+Xring_osc_0 vco_vctrl vss vdd ring_osc_0/csvco_branch_0/inverter_csvco_0/vss ring_osc_0/csvco_branch_2/vbp
++ vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div PFD
+C0 nDown charge_pump_0/w_2544_775# 0.05fF
+C1 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# 0.17fF
+C2 nswitch nDown 0.76fF
+C3 vco_vctrl vdd 0.58fF
+C4 biasp nDown 0.26fF
+C5 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C6 n_out_by_2 s_0_n 0.14fF
+C7 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD 0.09fF
+C8 vdd out_to_buffer 0.07fF
+C9 Up vdd 0.28fF
+C10 out_by_2 n_out_by_2 0.27fF
+C11 buffer_salida_0/a_678_n100# out_to_buffer 0.21fF
+C12 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D 0.09fF
+C13 QA vdd -0.04fF
+C14 biasp nUp -0.16fF
+C15 out_to_buffer out_to_div 0.13fF
+C16 lf_vc MC 0.20fF
+C17 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D 0.53fF
+C18 s_1_n out_div 0.09fF
+C19 Up nUp 2.72fF
+C20 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C21 vco_vctrl clk_0 -0.26fF
+C22 Up pswitch 1.98fF
+C23 vco_vctrl freq_div_0/prescaler_23_0/Q2 0.06fF
+C24 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.65fF
+C25 s_0 out_to_div 0.94fF
+C26 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D -0.42fF
+C27 charge_pump_0/w_2544_775# Down -0.23fF
+C28 clk_d out_div 0.60fF
+C29 vco_vctrl n_clk_1 0.23fF
+C30 nswitch Down 0.54fF
+C31 biasp Down 1.24fF
+C32 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C33 iref_cp Down 0.09fF
+C34 vdd nDown 0.22fF
+C35 vco_vctrl clk_1 -0.04fF
+C36 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# 0.82fF
+C37 vco_vctrl MC 0.33fF
+C38 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C39 buffer_salida_0/a_678_n100# vdd 0.24fF
+C40 vco_vctrl freq_div_0/prescaler_23_0/nCLK_23 0.06fF
+C41 Up biasp 0.26fF
+C42 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# 0.34fF
+C43 n_out_by_2 clk_1 -0.10fF
+C44 nDown nUp -0.09fF
+C45 vdd nUp 0.05fF
+C46 nDown pswitch 0.53fF
+C47 vco_vctrl s_0 0.45fF
+C48 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD 1.23fF
+C49 vco_vctrl freq_div_0/div_by_5_0/Q1 0.10fF
+C50 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C51 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.15fF
+C52 vco_D0 vdd 0.03fF
+C53 vdd clk_0 0.13fF
+C54 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C55 nUp pswitch 0.93fF
+C56 n_out_by_2 s_0 0.14fF
+C57 vco_vctrl s_0_n 0.34fF
+C58 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD -0.42fF
+C59 s_1 out_div 0.37fF
+C60 nDown Down 2.55fF
+C61 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C62 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C63 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C64 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C65 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C66 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C67 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C68 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C69 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C70 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C71 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C72 QB vss 3.83fF
+C73 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C74 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C75 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C76 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C77 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C78 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C79 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C80 pfd_reset vss 1.87fF
+C81 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C82 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C83 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C84 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C85 QA vss 4.29fF
+C86 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C87 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C88 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C89 in_ref vss 0.84fF
+C90 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C91 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.66fF
+C92 nUp vss 0.30fF
+C93 Up vss 5.34fF
+C94 Down vss 0.91fF
+C95 nDown vss 1.94fF
+C96 out_to_buffer vss 1.92fF
+C97 out_to_div vss 8.72fF
+C98 out_first_buffer vss 2.15fF
+C99 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C100 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C101 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C102 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C103 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C104 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C105 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C106 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C107 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C108 vco_out vss 1.65fF
+C109 vco_D0 vss -4.72fF
+C110 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C111 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C112 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C113 out_to_pad vss 7.15fF
+C114 buffer_salida_0/a_3996_n100# vss 48.29fF
+C115 buffer_salida_0/a_678_n100# vss 13.38fF
+C116 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C117 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C118 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C119 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C120 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C121 freq_div_0/prescaler_23_0/Q2_d vss -0.69fF
+C122 freq_div_0/prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C123 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C124 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C125 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C126 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C127 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C128 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C129 freq_div_0/prescaler_23_0/Q2 vss 0.55fF
+C130 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C131 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C132 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C133 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C134 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C135 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C136 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C137 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C138 freq_div_0/prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C139 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C140 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C141 n_clk_0 vss -6.63fF
+C142 freq_div_0/prescaler_23_0/Q1 vss 0.07fF
+C143 freq_div_0/prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C144 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C145 clk_0 vss -0.36fF
+C146 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C147 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C148 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C149 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C150 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C151 freq_div_0/prescaler_23_0/nCLK_23 vss -1.02fF
+C152 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C153 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C154 MC vss -1.42fF
+C155 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C156 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C157 n_out_by_2 vss 4.53fF
+C158 out_by_2 vss 4.18fF
+C159 s_0_n vss -3.95fF
+C160 s_0 vss 5.61fF
+C161 freq_div_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C162 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C163 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C164 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C165 freq_div_0/div_by_5_0/Q1_shift vss -0.36fF
+C166 freq_div_0/div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C167 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C168 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C169 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C170 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C171 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C172 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C173 freq_div_0/div_by_5_0/Q1 vss 4.35fF
+C174 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C175 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C176 freq_div_0/div_by_5_0/Q0 vss 0.29fF
+C177 freq_div_0/div_by_5_0/nQ0 vss 0.99fF
+C178 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C179 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C180 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C181 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C182 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C183 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C184 freq_div_0/div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C185 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C186 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C187 freq_div_0/div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C188 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C189 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C190 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C191 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C192 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C193 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C194 freq_div_0/div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C195 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C196 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C197 n_clk_1 vss -0.57fF
+C198 freq_div_0/div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C199 freq_div_0/div_by_5_0/nQ2 vss 1.38fF
+C200 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C201 clk_1 vss -2.22fF
+C202 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C203 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C204 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C205 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C206 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C207 freq_div_0/div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C208 vdd vss 573.83fF
+C209 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C210 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C211 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C212 out_div vss 0.60fF
+C213 clk_d vss 1.26fF
+C214 s_1_n vss -2.01fF
+C215 s_1 vss 1.77fF
+C216 freq_div_0/inverter_min_x4_0/in vss 2.71fF
+C217 clk_5 vss -0.23fF
+C218 clk_out_mux21 vss 3.65fF
+C219 clk_pre vss 1.67fF
+C220 clk_2_f vss 3.29fF
+C221 freq_div_0/div_by_2_0/o1 vss 2.08fF
+C222 freq_div_0/div_by_2_0/nCLK_2 vss 1.04fF
+C223 freq_div_0/div_by_2_0/o2 vss 2.08fF
+C224 freq_div_0/div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C225 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C226 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C227 freq_div_0/div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C228 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C229 freq_div_0/div_by_2_0/out_div vss -0.82fF
+C230 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C231 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C232 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C233 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C234 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C235 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C236 freq_div_0/div_by_2_0/nout_div vss 2.62fF
+C237 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C238 out_buffer_div_2 vss 1.57fF
+C239 n_out_buffer_div_2 vss 1.57fF
+C240 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C241 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C242 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C243 div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C244 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C245 out_div_2 vss -0.70fF
+C246 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C247 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C248 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C249 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C250 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C251 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C252 n_out_div_2 vss 2.11fF
+C253 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C254 lf_vc vss -60.88fF
+C255 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C256 lf_D0 vss 0.01fF
+C257 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C258 nswitch vss 4.61fF
+C259 biasp vss 5.46fF
+C260 iref_cp vss 7.56fF
+C261 vco_vctrl vss -30.43fF
+C262 pswitch vss 2.72fF
+.ends
+
diff --git a/mag/freq_div.mag b/mag/freq_div.mag
new file mode 100644
index 0000000..3d6b5e9
--- /dev/null
+++ b/mag/freq_div.mag
@@ -0,0 +1,420 @@
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+rect -2780 3485 -2710 3566
+rect -1961 3151 -1753 3156
+rect -1961 3071 -1951 3151
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+rect -1961 3066 -1753 3071
+rect -1941 748 -1853 3066
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+rect -402 3696 -334 3769
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+rect -1425 669 -1203 674
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+rect -1307 511 -1297 630
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+rect -1298 509 -1210 511
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+rect 22968 678 22978 740
+rect 22817 673 22978 678
+rect 22373 667 22545 672
+rect 15562 240 15572 363
+rect 15660 240 15670 363
+<< via3 >>
+rect -2786 5185 -2701 5275
+rect -1517 3933 -1431 4023
+rect -1685 879 -1599 953
+rect -411 2115 -325 2189
+rect -1297 511 -1210 630
+rect 15074 508 15162 631
+rect -1952 237 -1845 373
+rect 15572 240 15660 363
+<< metal4 >>
+rect -2792 5275 2396 5276
+rect -2792 5185 -2786 5275
+rect -2701 5185 2396 5275
+rect -2792 5184 2396 5185
+rect -1522 4023 2450 4024
+rect -1522 3933 -1517 4023
+rect -1431 3933 2450 4023
+rect -1522 3932 2450 3933
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+rect -325 2185 -324 2189
+rect -325 2119 2959 2185
+rect -325 2115 -324 2119
+rect -412 2114 -324 2115
+rect -1686 953 -1598 954
+rect -1686 879 -1685 953
+rect -1599 949 -1598 953
+rect -1599 883 2950 949
+rect -1599 879 -1598 883
+rect -1686 878 -1598 879
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+rect -1298 630 15074 631
+rect -1298 511 -1297 630
+rect -1210 511 15074 630
+rect -1298 510 15074 511
+rect -1296 508 15074 510
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+rect -1953 237 -1952 373
+rect -1845 363 -1844 373
+rect 15571 363 15661 364
+rect -1845 240 15572 363
+rect 15660 240 15661 363
+rect -1845 237 -1844 240
+rect 15571 239 15661 240
+rect -1953 236 -1844 237
+use mux2to1 mux2to1_1
+timestamp 1624653480
+transform -1 0 23305 0 -1 2710
+box -11 -1360 1267 2
+use mux2to1 mux2to1_0
+timestamp 1624653480
+transform -1 0 15995 0 -1 2710
+box -11 -1360 1267 2
+use mux2to4 mux2to4_0
+timestamp 1624653480
+transform 1 0 -2821 0 -1 2556
+box -11 -1360 2541 2
+use div_by_5 div_by_5_0
+timestamp 1624885207
+transform 1 0 556 0 1 0
+box -556 0 13892 3068
+use inverter_min_x2 inverter_min_x2_2
+timestamp 1624049879
+transform 1 0 -1766 0 -1 655
+box -53 -615 473 655
+use inverter_min_x2 inverter_min_x2_1
+timestamp 1624049879
+transform -1 0 22879 0 -1 655
+box -53 -615 473 655
+use div_by_2 div_by_2_0
+timestamp 1624885207
+transform 1 0 17530 0 1 0
+box -1244 0 4228 3068
+use inverter_min_x4 inverter_min_x4_0
+timestamp 1624049879
+transform 1 0 18971 0 -1 4889
+box -53 -616 665 643
+use inverter_min_x2 inverter_min_x2_0
+timestamp 1624049879
+transform 1 0 18445 0 -1 4890
+box -53 -615 473 655
+use prescaler_23 prescaler_23_0
+timestamp 1624885207
+transform 1 0 0 0 -1 6136
+box 0 -316 11752 3068
+<< labels >>
+rlabel metal2 22635 2841 22727 3134 1 out
+rlabel metal4 -2701 5184 2396 5276 1 clk_0
+rlabel metal4 -1431 3932 2450 4024 1 n_clk_0
+rlabel metal4 -325 2119 2959 2185 1 n_clk_1
+rlabel metal4 -1599 883 2950 949 1 clk_1
+rlabel metal2 14531 2347 14765 2506 1 clk_5
+rlabel metal2 11841 5135 15870 5265 1 clk_pre
+rlabel metal2 19645 4885 23186 5013 1 clk_d
+rlabel metal2 21754 2231 22085 2348 1 clk_2
+rlabel metal3 16081 3098 16198 4886 1 clk_out_mux21
+rlabel metal3 22882 740 22970 3383 1 s_1
+rlabel metal3 22381 740 22469 3384 1 s_1_n
+rlabel metal3 -1941 373 -1853 673 1 s_0
+rlabel metal3 -1307 630 -1203 674 1 s_0_n
+rlabel metal1 14232 30 16473 164 1 vdd
+rlabel metal1 19149 5370 20937 5699 1 vss
+rlabel metal2 -972 2687 -876 2980 1 in_b
+rlabel metal2 -2235 2687 -2151 2980 1 in_a
+<< end >>
diff --git a/mag/mux2to1.mag b/mag/mux2to1.mag
new file mode 100644
index 0000000..2ed5b6a
--- /dev/null
+++ b/mag/mux2to1.mag
@@ -0,0 +1,37 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624653480
+<< poly >>
+rect 420 -552 654 -486
+rect 588 -670 654 -552
+rect 588 -736 833 -670
+<< metal1 >>
+rect -11 -76 1267 2
+rect 198 -670 290 -580
+rect 332 -760 424 -670
+rect -11 -1360 1267 -1282
+<< metal2 >>
+rect 586 -424 678 -131
+rect 616 -583 1041 -517
+rect 616 -679 682 -583
+rect 404 -745 682 -679
+rect 41 -1224 111 -929
+rect 1145 -1225 1215 -930
+use trans_gate_mux2to8 trans_gate_mux2to8_1
+timestamp 1624653480
+transform -1 0 1203 0 -1 -723
+box -64 -725 579 637
+use trans_gate_mux2to8 trans_gate_mux2to8_0
+timestamp 1624653480
+transform 1 0 53 0 -1 -723
+box -64 -725 579 637
+<< labels >>
+rlabel metal2 586 -424 678 -131 1 in_a
+rlabel metal1 -11 -76 1267 2 1 vss
+rlabel metal1 -11 -1360 1267 -1282 1 vdd
+rlabel metal2 41 -1224 111 -929 1 out_a_0
+rlabel metal2 1145 -1225 1215 -930 1 out_a_1
+rlabel metal1 198 -670 290 -580 1 select_0_neg
+rlabel metal1 332 -760 424 -670 1 select_0
+<< end >>
diff --git a/mag/mux2to4.mag b/mag/mux2to4.mag
new file mode 100644
index 0000000..0e9e249
--- /dev/null
+++ b/mag/mux2to4.mag
@@ -0,0 +1,63 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624653480
+<< poly >>
+rect 420 -552 654 -486
+rect 1659 -552 1929 -486
+rect 588 -670 654 -552
+rect 1056 -670 1421 -607
+rect 588 -736 833 -670
+rect 1358 -792 1421 -670
+rect 1863 -670 1929 -552
+rect 1863 -736 2108 -670
+rect 1358 -858 1509 -792
+<< metal1 >>
+rect -11 -76 2541 2
+rect 198 -670 290 -580
+rect 332 -760 424 -670
+rect -11 -1360 2541 -1282
+<< metal2 >>
+rect 586 -424 670 -131
+rect 1849 -424 1945 -131
+rect 616 -583 1041 -517
+rect 1891 -583 2316 -517
+rect 616 -679 682 -583
+rect 404 -745 682 -679
+rect 1211 -681 1544 -619
+rect 1891 -679 1957 -583
+rect 1211 -750 1273 -681
+rect 1633 -745 1957 -679
+rect 850 -812 1273 -750
+rect 41 -1224 111 -929
+rect 1145 -1225 1215 -930
+rect 1311 -1225 1381 -930
+rect 2417 -1223 2487 -928
+use trans_gate_mux2to8 trans_gate_mux2to8_3
+timestamp 1624653480
+transform -1 0 2477 0 -1 -723
+box -64 -725 579 637
+use trans_gate_mux2to8 trans_gate_mux2to8_2
+timestamp 1624653480
+transform 1 0 1323 0 -1 -723
+box -64 -725 579 637
+use trans_gate_mux2to8 trans_gate_mux2to8_1
+timestamp 1624653480
+transform -1 0 1203 0 -1 -723
+box -64 -725 579 637
+use trans_gate_mux2to8 trans_gate_mux2to8_0
+timestamp 1624653480
+transform 1 0 53 0 -1 -723
+box -64 -725 579 637
+<< labels >>
+rlabel metal2 586 -424 670 -131 1 in_a
+rlabel metal2 1849 -424 1945 -131 1 in_b
+rlabel metal1 -11 -76 2541 2 1 vss
+rlabel metal1 -11 -1360 2541 -1282 1 vdd
+rlabel metal2 41 -1224 111 -929 1 out_a_0
+rlabel metal2 1145 -1225 1215 -930 1 out_a_1
+rlabel metal2 1311 -1225 1381 -930 1 out_b_0
+rlabel metal2 2417 -1223 2487 -928 1 out_b_1
+rlabel metal1 198 -670 290 -580 1 select_0_neg
+rlabel metal1 332 -760 424 -670 1 select_0
+<< end >>
diff --git a/mag/pfd_cp_interface.mag b/mag/pfd_cp_interface.mag
index f157ae0..e7c9f1d 100644
--- a/mag/pfd_cp_interface.mag
+++ b/mag/pfd_cp_interface.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624049879
+timestamp 1624885207
<< metal1 >>
rect 983 2998 993 3026
rect 0 2944 993 2998
@@ -50,29 +50,29 @@
rect 1161 40 1171 152
rect 983 35 1171 40
use trans_gate trans_gate_0
-timestamp 1624049879
+timestamp 1624653480
transform 1 0 675 0 -1 723
box -53 -811 569 723
-use inverter_cp_x2 inverter_cp_x2_0
+use inverter_cp_x1 inverter_cp_x1_1
timestamp 1624049879
-transform 1 0 1244 0 -1 776
-box 0 -758 910 776
-use inverter_cp_x2 inverter_cp_x2_1
-timestamp 1624049879
-transform 1 0 1244 0 1 2292
-box 0 -758 910 776
-use inverter_cp_x1 inverter_cp_x1_0
-timestamp 1624049879
-transform 1 0 0 0 -1 776
+transform 1 0 0 0 1 2292
box 0 -758 622 776
use inverter_cp_x1 inverter_cp_x1_2
timestamp 1624049879
transform 1 0 622 0 1 2292
box 0 -758 622 776
-use inverter_cp_x1 inverter_cp_x1_1
+use inverter_cp_x1 inverter_cp_x1_0
timestamp 1624049879
-transform 1 0 0 0 1 2292
+transform 1 0 0 0 -1 776
box 0 -758 622 776
+use inverter_cp_x2 inverter_cp_x2_1
+timestamp 1624049879
+transform 1 0 1244 0 1 2292
+box 0 -758 910 776
+use inverter_cp_x2 inverter_cp_x2_0
+timestamp 1624049879
+transform 1 0 1244 0 -1 776
+box 0 -758 910 776
<< labels >>
rlabel metal1 0 1498 2143 1570 1 vss
rlabel metal1 0 2259 226 2325 1 QA
diff --git a/mag/prescaler_23.mag b/mag/prescaler_23.mag
new file mode 100644
index 0000000..7c01995
--- /dev/null
+++ b/mag/prescaler_23.mag
@@ -0,0 +1,401 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624885207
+<< nwell >>
+rect 2984 1980 4570 3060
+rect 10382 2725 10536 3068
+rect 10538 3058 10785 3068
+rect 10538 2297 11706 3058
+rect 10538 1971 11703 2297
+rect 2984 1080 4332 1086
+rect 2984 0 4570 1080
+rect 10538 -16 11752 1078
+<< viali >>
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+rect 3746 1919 3812 1981
+rect 3965 1900 4033 1999
+rect 11047 1885 11181 1959
+rect 11235 1919 11301 1985
+rect 11454 1882 11540 2005
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+rect 10931 1062 10993 1132
+rect 11207 1109 11273 1175
+rect 11330 1112 11373 1241
+rect 3921 910 4000 1023
+rect 11597 843 11677 1035
+<< metal1 >>
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+rect 7527 2904 9159 3038
+rect 10503 2904 11506 3038
+rect 3537 2359 4017 2904
+rect 11026 2361 11506 2904
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+rect 3537 164 4017 715
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+<< via1 >>
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+rect 6553 2128 6817 2185
+rect 9536 2126 9796 2180
+rect 3548 1893 3558 1929
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+rect 3663 1893 3675 1929
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+rect 6537 888 6850 941
+rect 9534 883 9798 937
+<< metal2 >>
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+rect 6548 2190 6820 2200
+rect 6548 2111 6820 2121
+rect 9528 2191 9800 2201
+rect 9528 2111 9800 2121
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+rect 3256 -196 11063 -184
+rect 3256 -306 10863 -196
+rect 11050 -306 11063 -196
+rect 3256 -311 11063 -306
+rect 10863 -316 11050 -311
+<< via2 >>
+rect 1989 2185 2256 2191
+rect 1989 2127 2252 2185
+rect 2252 2127 2256 2185
+rect 6548 2185 6820 2190
+rect 6548 2128 6553 2185
+rect 6553 2128 6817 2185
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+rect 10911 1046 10996 1132
+rect 10996 1046 11014 1132
+rect 10894 964 11014 1046
+rect 10863 -306 11050 -196
+<< metal3 >>
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+rect 1978 2123 1988 2199
+rect 2270 2123 2280 2199
+rect 6538 2190 6830 2195
+rect 1979 2122 2266 2123
+rect 6538 2121 6548 2190
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+rect 10884 964 10894 1140
+rect 11014 964 11024 1140
+rect 10884 959 11024 964
+rect 1951 861 1961 951
+rect 2267 861 2277 951
+rect 9513 946 9833 951
+rect 6513 940 6886 945
+rect 6513 869 6523 940
+rect 6876 869 6886 940
+rect 6513 864 6886 869
+rect 9513 869 9523 946
+rect 9823 869 9833 946
+rect 9513 864 9833 869
+rect 238 388 311 789
+rect 3549 393 3674 398
+rect 224 267 234 388
+rect 311 267 321 388
+rect 238 263 311 267
+rect 3549 234 3559 393
+rect 3664 234 3674 393
+rect 3549 229 3674 234
+rect 10893 -184 11020 959
+rect 10892 -191 11020 -184
+rect 10853 -196 11060 -191
+rect 10853 -306 10863 -196
+rect 11050 -306 11060 -196
+rect 10853 -311 11060 -306
+<< via3 >>
+rect 1988 2191 2270 2199
+rect 1988 2127 1989 2191
+rect 1989 2127 2256 2191
+rect 2256 2127 2270 2191
+rect 1988 2123 2270 2127
+rect 6548 2121 6820 2190
+rect 9496 2191 9810 2202
+rect 9496 2121 9528 2191
+rect 9528 2121 9800 2191
+rect 9800 2121 9810 2191
+rect 9496 2112 9810 2121
+rect 1961 943 2267 951
+rect 1961 871 1970 943
+rect 1970 871 2254 943
+rect 2254 871 2267 943
+rect 1961 861 2267 871
+rect 6523 869 6876 940
+rect 9523 869 9823 946
+rect 234 267 311 388
+rect 3559 234 3664 393
+<< metal4 >>
+rect 1983 2203 9735 2204
+rect 1983 2202 9811 2203
+rect 1983 2199 9496 2202
+rect 1983 2123 1988 2199
+rect 2270 2190 9496 2199
+rect 2270 2123 6548 2190
+rect 1983 2121 6548 2123
+rect 6820 2121 9496 2190
+rect 1983 2112 9496 2121
+rect 9810 2112 9811 2202
+rect 9495 2111 9811 2112
+rect 1960 951 9783 952
+rect 1960 861 1961 951
+rect 2267 947 9783 951
+rect 2267 946 9824 947
+rect 2267 940 9523 946
+rect 2267 869 6523 940
+rect 6876 869 9523 940
+rect 9823 869 9824 946
+rect 2267 868 9824 869
+rect 2267 861 9783 868
+rect 1960 860 9783 861
+rect 3558 393 3665 394
+rect 233 388 312 389
+rect 233 267 234 388
+rect 311 377 312 388
+rect 3558 377 3559 393
+rect 311 267 3559 377
+rect 233 266 312 267
+rect 3558 234 3559 267
+rect 3664 234 3665 393
+rect 3558 233 3665 234
+use sky130_fd_sc_hs__mux2_1 sky130_fd_sc_hs__mux2_1_0
+timestamp 1623986409
+transform 1 0 10830 0 -1 1419
+box -38 -49 902 715
+use sky130_fd_sc_hs__or2_1 sky130_fd_sc_hs__or2_1_0
+timestamp 1624049879
+transform 1 0 3537 0 1 1649
+box -38 -49 518 715
+use sky130_fd_sc_hs__or2_1 sky130_fd_sc_hs__or2_1_1
+timestamp 1624049879
+transform 1 0 11026 0 1 1649
+box -38 -49 518 715
+use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_0
+timestamp 1624049879
+transform 1 0 3537 0 -1 1419
+box -38 -49 518 715
+use DFlipFlop DFlipFlop_0
+timestamp 1624885207
+transform 1 0 1244 0 1 0
+box -1244 0 1740 3068
+use DFlipFlop DFlipFlop_1
+timestamp 1624885207
+transform 1 0 5814 0 1 0
+box -1244 0 1740 3068
+use DFlipFlop DFlipFlop_2
+timestamp 1624885207
+transform 1 0 8798 0 -1 3068
+box -1244 0 1740 3068
+<< labels >>
+rlabel metal4 2267 860 6523 952 1 CLK
+rlabel metal4 2270 2112 6548 2204 1 nCLK
+rlabel metal1 11677 843 11727 1038 1 CLK_23
+rlabel metal1 2980 2904 4612 3038 1 vdd
+rlabel metal1 2949 1370 4573 1698 1 vss
+rlabel metal4 311 267 3559 377 1 nCLK_23
+rlabel metal2 3256 -311 10863 -184 1 MC
+rlabel metal2 3060 1499 3126 2076 1 Q1
+rlabel metal3 7379 1504 7861 1564 1 Q2
+rlabel metal2 10651 1888 11047 1954 1 Q2_d
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_BHR94T.mag b/mag/sky130_fd_pr__nfet_01v8_BHR94T.mag
index 0f0e256..8e53291 100644
--- a/mag/sky130_fd_pr__nfet_01v8_BHR94T.mag
+++ b/mag/sky130_fd_pr__nfet_01v8_BHR94T.mag
@@ -1,9 +1,9 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624049879
+timestamp 1624062693
<< pwell >>
-rect -311 -335 311 335
+rect -311 -335 311 324
<< nmos >>
rect -111 -125 -81 125
rect -15 -125 15 125
@@ -31,15 +31,9 @@
rect 31 -113 65 113
rect 127 -113 161 113
<< psubdiff >>
-rect -275 203 -241 265
-rect 241 203 275 265
-rect -275 -265 -241 -203
-rect 241 -265 275 -203
-rect -275 -299 -179 -265
-rect 179 -299 275 -265
+rect -240 -299 -179 -265
+rect 179 -299 241 -265
<< psubdiffcont >>
-rect -275 -203 -241 203
-rect 241 -203 275 203
rect -179 -299 179 -265
<< poly >>
rect -111 125 -81 151
@@ -49,8 +43,6 @@
rect -15 -151 15 -125
rect 81 -151 111 -125
<< locali >>
-rect -275 203 -241 265
-rect 241 203 275 265
rect -161 113 -127 129
rect -161 -129 -127 -113
rect -65 113 -31 129
@@ -59,10 +51,8 @@
rect 31 -129 65 -113
rect 127 113 161 129
rect 127 -129 161 -113
-rect -275 -265 -241 -203
-rect 241 -265 275 -203
-rect -275 -299 -179 -265
-rect 179 -299 275 -265
+rect -240 -299 -179 -265
+rect 179 -299 241 -265
<< viali >>
rect -161 -113 -127 113
rect -65 -113 -31 113
diff --git a/mag/sky130_fd_pr__pfet_01v8_4798MH.mag b/mag/sky130_fd_pr__pfet_01v8_4798MH.mag
index a113890..9bad16a 100644
--- a/mag/sky130_fd_pr__pfet_01v8_4798MH.mag
+++ b/mag/sky130_fd_pr__pfet_01v8_4798MH.mag
@@ -1,9 +1,9 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624049879
+timestamp 1624062693
<< nwell >>
-rect -311 -344 311 344
+rect -311 -338 311 344
<< pmos >>
rect -111 -125 -81 125
rect -15 -125 15 125
@@ -31,16 +31,10 @@
rect 31 -113 65 113
rect 127 -113 161 113
<< nsubdiff >>
-rect -275 274 -179 308
-rect 179 274 275 308
-rect -275 212 -241 274
-rect 241 212 275 274
-rect -275 -274 -241 -212
-rect 241 -274 275 -212
+rect -240 274 -179 308
+rect 179 274 240 308
<< nsubdiffcont >>
rect -179 274 179 308
-rect -275 -212 -241 212
-rect 241 -212 275 212
<< poly >>
rect -111 125 -81 151
rect -15 125 15 151
@@ -49,10 +43,8 @@
rect -15 -156 15 -125
rect 81 -156 111 -125
<< locali >>
-rect -275 274 -179 308
-rect 179 274 275 308
-rect -275 212 -241 274
-rect 241 212 275 274
+rect -240 274 -179 308
+rect 179 274 240 308
rect -161 113 -127 129
rect -161 -129 -127 -113
rect -65 113 -31 129
@@ -61,8 +53,6 @@
rect 31 -129 65 -113
rect 127 113 161 129
rect 127 -129 161 -113
-rect -275 -274 -241 -212
-rect 241 -274 275 -212
<< viali >>
rect -161 -113 -127 113
rect -65 -113 -31 113
diff --git a/mag/sky130_fd_sc_hs__mux2_1.mag b/mag/sky130_fd_sc_hs__mux2_1.mag
new file mode 100644
index 0000000..45ef6de
--- /dev/null
+++ b/mag/sky130_fd_sc_hs__mux2_1.mag
@@ -0,0 +1,381 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623986409
+<< checkpaint >>
+rect -1298 -1309 2162 1975
+<< nwell >>
+rect -38 332 902 704
+<< pwell >>
+rect 1 49 861 248
+rect 0 0 864 49
+<< scpmos >>
+rect 86 368 116 536
+rect 193 368 223 568
+rect 386 368 416 568
+rect 494 368 524 568
+rect 608 368 638 568
+rect 732 368 762 592
+<< nmoslvt >>
+rect 84 112 114 222
+rect 196 74 226 222
+rect 274 74 304 222
+rect 413 74 443 222
+rect 605 74 635 222
+rect 748 74 778 222
+<< ndiff >>
+rect 27 184 84 222
+rect 27 150 39 184
+rect 73 150 84 184
+rect 27 112 84 150
+rect 114 210 196 222
+rect 114 176 128 210
+rect 162 176 196 210
+rect 114 120 196 176
+rect 114 112 146 120
+rect 129 86 146 112
+rect 180 86 196 120
+rect 129 74 196 86
+rect 226 74 274 222
+rect 304 128 413 222
+rect 304 94 341 128
+rect 375 94 413 128
+rect 304 74 413 94
+rect 443 74 605 222
+rect 635 146 748 222
+rect 635 112 675 146
+rect 709 112 748 146
+rect 635 74 748 112
+rect 778 210 835 222
+rect 778 176 789 210
+rect 823 176 835 210
+rect 778 120 835 176
+rect 778 86 789 120
+rect 823 86 835 120
+rect 778 74 835 86
+<< pdiff >>
+rect 663 580 732 592
+rect 663 568 675 580
+rect 134 536 193 568
+rect 27 524 86 536
+rect 27 490 39 524
+rect 73 490 86 524
+rect 27 429 86 490
+rect 27 395 39 429
+rect 73 395 86 429
+rect 27 368 86 395
+rect 116 519 193 536
+rect 116 485 146 519
+rect 180 485 193 519
+rect 116 368 193 485
+rect 223 368 386 568
+rect 416 531 494 568
+rect 416 497 429 531
+rect 463 497 494 531
+rect 416 414 494 497
+rect 416 380 429 414
+rect 463 380 494 414
+rect 416 368 494 380
+rect 524 368 608 568
+rect 638 546 675 568
+rect 709 546 732 580
+rect 638 497 732 546
+rect 638 463 675 497
+rect 709 463 732 497
+rect 638 414 732 463
+rect 638 380 675 414
+rect 709 380 732 414
+rect 638 368 732 380
+rect 762 580 821 592
+rect 762 546 775 580
+rect 809 546 821 580
+rect 762 497 821 546
+rect 762 463 775 497
+rect 809 463 821 497
+rect 762 414 821 463
+rect 762 380 775 414
+rect 809 380 821 414
+rect 762 368 821 380
+<< ndiffc >>
+rect 39 150 73 184
+rect 128 176 162 210
+rect 146 86 180 120
+rect 341 94 375 128
+rect 675 112 709 146
+rect 789 176 823 210
+rect 789 86 823 120
+<< pdiffc >>
+rect 39 490 73 524
+rect 39 395 73 429
+rect 146 485 180 519
+rect 429 497 463 531
+rect 429 380 463 414
+rect 675 546 709 580
+rect 675 463 709 497
+rect 675 380 709 414
+rect 775 546 809 580
+rect 775 463 809 497
+rect 775 380 809 414
+<< poly >>
+rect 193 568 223 594
+rect 386 568 416 594
+rect 494 568 524 594
+rect 608 568 638 594
+rect 732 592 762 618
+rect 86 536 116 562
+rect 86 353 116 368
+rect 193 353 223 368
+rect 386 353 416 368
+rect 494 353 524 368
+rect 608 353 638 368
+rect 732 353 762 368
+rect 83 336 119 353
+rect 190 336 226 353
+rect 83 320 226 336
+rect 83 286 117 320
+rect 151 286 226 320
+rect 383 310 419 353
+rect 491 310 527 353
+rect 605 330 641 353
+rect 605 314 671 330
+rect 729 326 765 353
+rect 83 270 226 286
+rect 84 222 114 270
+rect 196 222 226 270
+rect 269 294 335 310
+rect 269 260 285 294
+rect 319 260 335 294
+rect 269 244 335 260
+rect 377 294 443 310
+rect 377 260 393 294
+rect 427 260 443 294
+rect 377 244 443 260
+rect 491 294 557 310
+rect 491 260 507 294
+rect 541 260 557 294
+rect 491 244 557 260
+rect 605 280 621 314
+rect 655 280 671 314
+rect 605 264 671 280
+rect 713 310 779 326
+rect 713 276 729 310
+rect 763 276 779 310
+rect 274 222 304 244
+rect 413 222 443 244
+rect 605 222 635 264
+rect 713 260 779 276
+rect 748 222 778 260
+rect 84 86 114 112
+rect 196 48 226 74
+rect 274 48 304 74
+rect 413 48 443 74
+rect 605 48 635 74
+rect 748 48 778 74
+<< polycont >>
+rect 117 286 151 320
+rect 285 260 319 294
+rect 393 260 427 294
+rect 507 260 541 294
+rect 621 280 655 314
+rect 729 276 763 310
+<< locali >>
+rect 0 649 31 683
+rect 65 649 127 683
+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
+rect 449 649 511 683
+rect 545 649 607 683
+rect 641 649 703 683
+rect 737 649 799 683
+rect 833 649 864 683
+rect 23 524 89 540
+rect 23 490 39 524
+rect 73 490 89 524
+rect 23 446 89 490
+rect 130 519 196 649
+rect 130 485 146 519
+rect 180 485 196 519
+rect 130 480 196 485
+rect 230 581 625 615
+rect 230 446 264 581
+rect 23 429 264 446
+rect 23 395 39 429
+rect 73 412 264 429
+rect 413 531 479 547
+rect 413 497 429 531
+rect 463 497 479 531
+rect 413 414 479 497
+rect 73 395 89 412
+rect 23 390 89 395
+rect 23 226 57 390
+rect 413 380 429 414
+rect 463 380 479 414
+rect 413 378 479 380
+rect 101 320 167 356
+rect 101 286 117 320
+rect 151 286 167 320
+rect 101 270 167 286
+rect 201 344 479 378
+rect 23 184 89 226
+rect 23 150 39 184
+rect 73 150 89 184
+rect 23 108 89 150
+rect 125 210 167 226
+rect 125 176 128 210
+rect 162 176 167 210
+rect 125 136 167 176
+rect 201 204 235 344
+rect 591 330 625 581
+rect 659 580 725 649
+rect 659 546 675 580
+rect 709 546 725 580
+rect 659 497 725 546
+rect 659 463 675 497
+rect 709 463 725 497
+rect 659 414 725 463
+rect 659 380 675 414
+rect 709 380 725 414
+rect 659 364 725 380
+rect 759 580 847 596
+rect 759 546 775 580
+rect 809 546 847 580
+rect 759 497 847 546
+rect 759 463 775 497
+rect 809 463 847 497
+rect 759 414 847 463
+rect 759 380 775 414
+rect 809 380 847 414
+rect 759 364 847 380
+rect 591 314 671 330
+rect 269 294 337 310
+rect 269 260 285 294
+rect 319 260 337 294
+rect 269 244 337 260
+rect 201 170 269 204
+rect 125 120 201 136
+rect 125 86 146 120
+rect 180 86 201 120
+rect 125 17 201 86
+rect 235 128 269 170
+rect 303 196 337 244
+rect 377 294 455 310
+rect 377 260 393 294
+rect 427 260 455 294
+rect 377 236 455 260
+rect 491 294 557 310
+rect 491 260 507 294
+rect 541 260 557 294
+rect 591 280 621 314
+rect 655 280 671 314
+rect 591 264 671 280
+rect 705 310 779 326
+rect 705 276 729 310
+rect 763 276 779 310
+rect 491 196 557 260
+rect 705 260 779 276
+rect 705 230 739 260
+rect 303 162 557 196
+rect 591 196 739 230
+rect 813 226 847 364
+rect 773 210 847 226
+rect 591 128 625 196
+rect 773 176 789 210
+rect 823 176 847 210
+rect 235 94 341 128
+rect 375 94 625 128
+rect 235 78 625 94
+rect 659 146 725 162
+rect 659 112 675 146
+rect 709 112 725 146
+rect 659 17 725 112
+rect 773 120 847 176
+rect 773 86 789 120
+rect 823 86 847 120
+rect 773 70 847 86
+rect 0 -17 31 17
+rect 65 -17 127 17
+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 511 17
+rect 545 -17 607 17
+rect 641 -17 703 17
+rect 737 -17 799 17
+rect 833 -17 864 17
+<< viali >>
+rect 31 649 65 683
+rect 127 649 161 683
+rect 223 649 257 683
+rect 319 649 353 683
+rect 415 649 449 683
+rect 511 649 545 683
+rect 607 649 641 683
+rect 703 649 737 683
+rect 799 649 833 683
+rect 31 -17 65 17
+rect 127 -17 161 17
+rect 223 -17 257 17
+rect 319 -17 353 17
+rect 415 -17 449 17
+rect 511 -17 545 17
+rect 607 -17 641 17
+rect 703 -17 737 17
+rect 799 -17 833 17
+<< metal1 >>
+rect 0 683 864 715
+rect 0 649 31 683
+rect 65 649 127 683
+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
+rect 449 649 511 683
+rect 545 649 607 683
+rect 641 649 703 683
+rect 737 649 799 683
+rect 833 649 864 683
+rect 0 617 864 649
+rect 0 17 864 49
+rect 0 -17 31 17
+rect 65 -17 127 17
+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 511 17
+rect 545 -17 607 17
+rect 641 -17 703 17
+rect 737 -17 799 17
+rect 833 -17 864 17
+rect 0 -49 864 -17
+<< labels >>
+rlabel comment s 0 0 0 0 4 mux2_1
+flabel pwell s 0 0 864 49 0 FreeSans 200 0 0 0 VNB
+port 5 nsew ground bidirectional
+flabel nwell s 0 617 864 666 0 FreeSans 200 0 0 0 VPB
+port 6 nsew power bidirectional
+flabel metal1 s 0 617 864 666 0 FreeSans 340 0 0 0 VPWR
+port 7 nsew power bidirectional
+flabel metal1 s 0 0 864 49 0 FreeSans 340 0 0 0 VGND
+port 4 nsew ground bidirectional
+flabel locali s 799 390 833 424 0 FreeSans 340 0 0 0 X
+port 8 nsew signal output
+flabel locali s 799 464 833 498 0 FreeSans 340 0 0 0 X
+port 8 nsew signal output
+flabel locali s 799 538 833 572 0 FreeSans 340 0 0 0 X
+port 8 nsew signal output
+flabel locali s 127 316 161 350 0 FreeSans 340 0 0 0 S
+port 3 nsew signal input
+flabel locali s 415 242 449 276 0 FreeSans 340 0 0 0 A0
+port 1 nsew signal input
+flabel locali s 511 168 545 202 0 FreeSans 340 0 0 0 A1
+port 2 nsew signal input
+flabel locali s 511 242 545 276 0 FreeSans 340 0 0 0 A1
+port 2 nsew signal input
+<< properties >>
+string LEFsite unit
+string LEFclass CORE
+string FIXED_BBOX 0 0 864 666
+string LEFsymmetry X Y
+string GDS_END 1046316
+string GDS_START 1039454
+<< end >>
diff --git a/mag/top_pll_v3.mag b/mag/top_pll_v3.mag
new file mode 100644
index 0000000..8270648
--- /dev/null
+++ b/mag/top_pll_v3.mag
@@ -0,0 +1,630 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624886397
+<< nwell >>
+rect 0 2846 20536 2860
+rect 0 2838 6183 2846
+rect 0 2608 3909 2838
+rect 3790 2062 3909 2608
+rect 6063 2012 6183 2838
+rect 13905 2752 20536 2846
+rect 13905 1955 14025 2752
+rect 18329 1955 20536 2752
+rect 18510 1923 20536 1955
+rect 20472 1290 20536 1923
+rect 49317 1290 50180 2860
+rect -3 -230 3909 546
+rect -3 -400 6063 -230
+<< pwell >>
+rect 3790 706 3909 2062
+rect 2872 546 3909 706
+rect 13905 784 14901 854
+rect 18329 784 18510 1215
+rect 20472 1190 20593 1290
+rect 20456 1176 20593 1190
+rect 13905 653 18510 784
+rect 19367 653 20225 754
+rect 20472 653 20593 1176
+rect 13905 223 20593 653
+rect 13905 181 20796 223
+rect 27347 181 46785 1226
+rect 49317 769 50180 1290
+rect 49319 356 50180 769
+rect 13905 -238 20572 181
+rect 48562 -632 50180 356
+rect 49370 -3693 50180 -632
+<< psubdiff >>
+rect 20575 24 20599 114
+rect 49259 24 49283 114
+rect 48569 -453 50169 -429
+rect 48569 -4056 48570 -4032
+rect 48570 -7205 50169 -7181
+<< nsubdiff >>
+rect 43 -212 67 -124
+rect 416 -212 440 -124
+rect 1252 -220 1276 -132
+rect 1625 -220 1649 -132
+rect 2420 -214 2446 -126
+rect 2795 -214 2819 -126
+<< psubdiffcont >>
+rect 20599 24 49259 114
+rect 48569 -4032 50169 -453
+rect 48570 -7181 50169 -4032
+<< nsubdiffcont >>
+rect 67 -212 416 -124
+rect 1276 -220 1625 -132
+rect 2446 -214 2795 -126
+<< poly >>
+rect 10374 2156 10680 2179
+rect 10374 2078 10395 2156
+rect 10657 2078 10680 2156
+rect 10374 2055 10680 2078
+rect 10354 385 10697 405
+rect 10354 280 10372 385
+rect 10671 280 10697 385
+rect 10354 269 10697 280
+<< polycont >>
+rect 9420 2020 9699 2114
+rect 10395 2078 10657 2156
+rect 9434 325 9696 449
+rect 10372 280 10671 385
+<< locali >>
+rect 20583 24 20599 114
+rect 49259 24 49275 114
+rect 48569 -453 50169 -437
+rect 48569 -4048 48570 -4032
+rect 48570 -7197 50169 -7181
+<< viali >>
+rect 10374 2156 10680 2179
+rect 9399 2114 9723 2134
+rect 9399 2020 9420 2114
+rect 9420 2020 9699 2114
+rect 9699 2020 9723 2114
+rect 10374 2078 10395 2156
+rect 10395 2078 10657 2156
+rect 10657 2078 10680 2156
+rect 10374 2055 10680 2078
+rect 9399 1999 9723 2020
+rect 9405 449 9723 468
+rect 9405 325 9434 449
+rect 9434 325 9696 449
+rect 9696 325 9723 449
+rect 9405 306 9723 325
+rect 10354 385 10697 405
+rect 10354 280 10372 385
+rect 10372 280 10671 385
+rect 10671 280 10697 385
+rect 10354 269 10697 280
+rect 20599 24 49259 114
+rect 22 -124 2852 -112
+rect 22 -212 67 -124
+rect 67 -212 416 -124
+rect 416 -126 2852 -124
+rect 416 -132 2446 -126
+rect 416 -212 1276 -132
+rect 22 -220 1276 -212
+rect 1276 -220 1625 -132
+rect 1625 -214 2446 -132
+rect 2446 -214 2795 -126
+rect 2795 -214 2852 -126
+rect 1625 -220 2852 -214
+rect 22 -232 2852 -220
+rect 48569 -4032 50169 -453
+rect 48570 -7181 50169 -4032
+<< metal1 >>
+rect 0 2824 20536 2830
+rect 0 2816 20548 2824
+rect 0 2808 6183 2816
+rect 0 2674 6294 2808
+rect 13869 2687 20548 2816
+rect 13869 2674 20472 2687
+rect 0 2578 3504 2674
+rect 3150 2150 3504 2578
+rect 5909 2095 6099 2096
+rect 4963 2090 5581 2095
+rect 3909 2034 3919 2090
+rect 4143 2034 4153 2090
+rect 4963 2034 5180 2090
+rect 5404 2034 5581 2090
+rect 4963 2029 5581 2034
+rect 5873 2091 6099 2095
+rect 5873 2035 5955 2091
+rect 6089 2035 6099 2091
+rect 5873 2030 6099 2035
+rect 5873 2029 6063 2030
+rect 0 1956 210 2022
+rect 8859 2012 8963 2633
+rect 13835 2624 20472 2674
+rect 13835 2617 14025 2624
+rect 10362 2179 10692 2185
+rect 9387 2134 9735 2140
+rect 9387 1999 9399 2134
+rect 9723 1999 9735 2134
+rect 10362 2055 10374 2179
+rect 10680 2055 10692 2179
+rect 11133 2158 11217 2499
+rect 10362 2049 10692 2055
+rect 9387 1993 9735 1999
+rect 18308 1990 20472 2624
+rect 18329 1985 20472 1990
+rect 18510 1880 20472 1985
+rect 18510 1879 19087 1880
+rect 18863 1841 19087 1879
+rect 18863 1823 19020 1841
+rect 3857 1234 3909 1468
+rect 6052 1268 6259 1468
+rect 3857 870 3976 1234
+rect 3790 830 3976 870
+rect 3585 776 3976 830
+rect 3790 736 3976 776
+rect 6183 830 6259 1268
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+rect 23760 -534 32011 -498
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+rect 26744 -1290 26754 -1201
+rect 27038 -1284 27439 -1204
+rect 24577 -1672 24694 -1665
+rect 24554 -1708 26599 -1672
+rect 24564 -1712 26591 -1708
+rect 24516 -1767 26618 -1712
+rect 24534 -1770 26599 -1767
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+rect 48563 -453 50175 -441
+rect 24546 -2282 26688 -2277
+rect 24531 -2293 26688 -2282
+rect 24531 -2297 26599 -2293
+rect 24516 -2333 26599 -2297
+rect 26511 -2803 26521 -2707
+rect 26736 -2803 26746 -2707
+rect 27038 -2801 27439 -2721
+rect 27274 -3449 27526 -3417
+rect 26912 -4238 27526 -3449
+rect 25629 -4270 27526 -4238
+rect 24570 -4522 27526 -4270
+rect 48563 -4032 48569 -453
+rect 48563 -5101 48570 -4032
+rect -636 -6099 2871 -5770
+rect -636 -8501 976 -6099
+rect 48564 -7181 48570 -5101
+rect 50169 -7181 50175 -453
+rect 48564 -7193 50175 -7181
+rect 48563 -8501 50175 -7193
+rect 7710 -23526 8742 -23446
+<< via1 >>
+rect 3919 2034 4143 2090
+rect 5180 2034 5404 2090
+rect 5955 2035 6089 2091
+rect 9420 2020 9699 2114
+rect 10395 2078 10657 2156
+rect 18520 1190 18728 1242
+rect 19587 1172 19999 1256
+rect 20318 1169 20560 1253
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+rect 5919 518 6053 574
+rect 9434 325 9696 449
+rect 10372 280 10671 385
+rect 26552 -1290 26744 -1201
+rect 26521 -2803 26736 -2707
+<< metal2 >>
+rect 10395 2156 10657 2166
+rect 9420 2114 9699 2124
+rect 3919 2090 4143 2100
+rect 3919 2024 4143 2034
+rect 5180 2090 5404 2100
+rect 5180 2024 5404 2034
+rect 5955 2091 6089 2101
+rect 5955 2025 6089 2035
+rect 10395 2068 10657 2078
+rect 3988 1928 4074 2024
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+rect 5469 1609 10645 1611
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+rect 19587 1256 19999 1266
+rect 18520 1242 18728 1252
+rect 18091 1190 18520 1241
+rect 18091 1189 18728 1190
+rect 18520 1180 18728 1189
+rect 19587 1162 19999 1172
+rect 20318 1253 20560 1263
+rect 20318 1159 20560 1169
+rect 5232 1055 10645 1079
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+rect 5232 971 10645 997
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+rect 3988 584 4074 680
+rect -609 508 -513 518
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+rect 5180 508 5404 518
+rect 5919 574 6053 584
+rect 5919 508 6053 518
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+rect 10372 385 10671 395
+rect 13195 343 13711 353
+rect 10372 270 10671 280
+rect 13764 206 14377 369
+rect 14214 25 14377 206
+rect 25954 -1183 26057 -1173
+rect 26057 -1201 26762 -1188
+rect 26057 -1290 26552 -1201
+rect 26744 -1290 26762 -1201
+rect 26057 -1297 26762 -1290
+rect 26552 -1300 26744 -1297
+rect 25954 -1316 26057 -1306
+rect 25953 -2394 26054 -2384
+rect 23735 -2504 25953 -2397
+rect 23735 -2506 26054 -2504
+rect 790 -2748 1121 -2631
+rect 8110 -2906 8344 -2747
+rect -626 -3263 -496 -3253
+rect -496 -3521 216 -3266
+rect 23737 -3267 23847 -2506
+rect 25953 -2514 26054 -2506
+rect 26521 -2700 26736 -2697
+rect 25015 -2707 26740 -2700
+rect 25015 -2803 26521 -2707
+rect 26736 -2803 26740 -2707
+rect 25015 -2807 26740 -2803
+rect 23737 -3381 23846 -3267
+rect 25015 -3384 25122 -2807
+rect 26521 -2813 26736 -2807
+rect -626 -3535 -496 -3525
+rect -311 -5413 3230 -5285
+rect 7005 -5665 11034 -5535
+rect 12012 -6847 19619 -6720
+<< via2 >>
+rect 5180 2034 5404 2090
+rect 5955 2035 6089 2091
+rect 9491 2043 9625 2099
+rect 10412 2078 10636 2134
+rect 5955 1756 6089 1812
+rect 9499 1775 9633 1831
+rect 5245 1555 5469 1611
+rect 10410 1553 10634 1609
+rect 19587 1172 19999 1256
+rect 5245 997 5469 1053
+rect 10410 999 10634 1055
+rect 5919 797 6053 853
+rect 9497 797 9631 853
+rect -609 518 -513 715
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+rect 10412 306 10636 362
+rect 13195 353 13711 941
+rect 25954 -1306 26057 -1183
+rect 25953 -2504 26054 -2394
+rect -626 -3525 -496 -3263
+<< metal3 >>
+rect 10402 2134 10646 2139
+rect 9470 2099 9672 2114
+rect 5170 2090 5414 2095
+rect 5170 2034 5180 2090
+rect 5404 2034 5414 2090
+rect 5170 2029 5414 2034
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+rect 5945 2035 5955 2091
+rect 6089 2035 6099 2091
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+rect 9470 2043 9491 2099
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+rect 9525 1769 9585 1770
+rect 5945 1751 6099 1756
+rect 5992 1742 6052 1751
+rect 5235 1611 5479 1616
+rect 10494 1614 10554 2073
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+rect 5469 1555 5479 1611
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+rect 10400 1609 10644 1614
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+rect 19577 1256 20009 1261
+rect 19577 1172 19587 1256
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+rect 10400 1055 10644 1060
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+rect 10634 999 10644 1055
+rect 10400 994 10644 999
+rect -627 715 -495 725
+rect -627 518 -609 715
+rect -513 518 -495 715
+rect 5262 579 5322 992
+rect 5956 858 6016 867
+rect 5909 853 6063 858
+rect 5909 797 5919 853
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+rect 5909 792 6063 797
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+rect 9487 797 9497 853
+rect 9631 797 9641 853
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+rect 5956 579 6016 792
+rect -627 -3258 -495 518
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+rect 5909 513 6063 518
+rect 9534 420 9594 792
+rect 9487 415 9641 420
+rect 9487 359 9497 415
+rect 9631 359 9641 415
+rect 10494 367 10554 994
+rect 13185 941 13721 946
+rect 9487 354 9641 359
+rect 10402 362 10646 367
+rect 10402 306 10412 362
+rect 10636 306 10646 362
+rect 13185 353 13195 941
+rect 13711 353 13721 941
+rect 13185 348 13721 353
+rect 10402 301 10646 306
+rect 16756 -71 16812 -15
+rect 19758 -86 19952 1167
+rect 19749 -275 19759 -86
+rect 19949 -275 19959 -86
+rect 32202 -276 32212 -87
+rect 32435 -276 32444 -87
+rect 24078 -1074 24182 -1030
+rect 24728 -1073 24816 -773
+rect -636 -3263 -486 -3258
+rect -636 -3525 -626 -3263
+rect -496 -3525 -486 -3263
+rect -636 -3530 -486 -3525
+rect -627 -3537 -495 -3530
+rect -95 -3783 -7 -1140
+rect 406 -3784 494 -1140
+rect 25944 -1183 26067 -1178
+rect 25944 -1306 25954 -1183
+rect 26057 -1306 26067 -1183
+rect 27754 -1216 27814 -1004
+rect 25944 -1311 26067 -1306
+rect 25950 -2389 26059 -1311
+rect 32206 -1839 32440 -276
+rect 31744 -2048 32440 -1839
+rect 31744 -2090 32437 -2048
+rect 25943 -2394 26064 -2389
+rect 25943 -2504 25953 -2394
+rect 26054 -2504 26064 -2394
+rect 25943 -2509 26064 -2504
+rect 27797 -2793 28028 -2733
+rect 6677 -5289 6794 -3501
+<< via3 >>
+rect 13195 353 13711 941
+rect 19759 -275 19949 -86
+rect 32212 -276 32435 -87
+<< metal4 >>
+rect 13194 941 13712 942
+rect 13194 353 13195 941
+rect 13711 353 13712 941
+rect 13194 352 13712 353
+rect 19757 -86 32444 -83
+rect 19757 -275 19759 -86
+rect 19949 -87 32444 -86
+rect 19949 -275 32212 -87
+rect 19757 -276 32212 -275
+rect 32435 -276 32444 -87
+rect 19757 -278 32444 -276
+rect 19925 -1349 24474 -1283
+rect 19916 -2585 23200 -2519
+rect 20425 -4424 24306 -4332
+rect 20479 -5676 25576 -5584
+rect 19686 -7893 45045 -7093
+<< via4 >>
+rect 13195 353 13711 941
+rect 13169 -7854 13729 -7126
+<< metal5 >>
+rect 13136 941 13764 965
+rect 13136 353 13195 941
+rect 13711 353 13764 941
+rect 13136 -7126 13764 353
+rect 13136 -7854 13169 -7126
+rect 13729 -7854 13764 -7126
+rect 13136 -7886 13764 -7854
+use loop_filter_v2 loop_filter_v2_0
+timestamp 1624053471
+transform 1 0 15820 0 1 -12873
+box -16462 -24206 34360 5780
+use div_by_2 div_by_2_0
+timestamp 1624885207
+transform -1 0 30791 0 -1 -468
+box -1244 0 4228 3068
+use freq_div *freq_div_0
+timestamp 1624885207
+transform -1 0 22875 0 -1 -400
+box -2832 0 23316 6452
+use ring_osc_buffer ring_osc_buffer_0
+timestamp 1624402156
+transform 1 0 18509 0 1 653
+box 0 0 1963 1270
+use ring_osc ring_osc_0
+timestamp 1624049879
+transform 1 0 14447 0 1 -174
+box -422 0 3882 2956
+use PFD PFD_0
+timestamp 1624049879
+transform 1 0 0 0 1 1304
+box 0 -1304 3790 1304
+use pfd_cp_interface pfd_cp_interface_0
+timestamp 1624885207
+transform 1 0 3909 0 1 -230
+box 0 0 2154 3068
+use buffer_salida buffer_salida_0
+timestamp 1624049879
+transform 1 0 20599 0 1 1292
+box -63 -1119 28718 1568
+use charge_pump *charge_pump_0
+timestamp 1624049879
+transform 1 0 6183 0 1 -142
+box 0 -96 7722 2988
+<< labels >>
+rlabel metal2 2159 858 2211 1750 1 pfd_reset
+rlabel metal1 0 1956 210 2022 1 in_ref
+rlabel metal2 3988 1876 4074 2034 1 QA
+rlabel metal2 3988 574 4074 733 1 QB
+rlabel metal2 6053 755 9497 863 1 Down
+rlabel metal2 5469 971 10410 1079 1 nDown
+rlabel metal2 5469 1529 10410 1637 1 Up
+rlabel metal2 6089 1746 9499 1854 1 nUp
+rlabel metal1 8859 2012 8963 2633 1 biasp
+rlabel metal1 11133 2158 11217 2499 1 pswitch
+rlabel metal1 11118 80 11244 311 1 nswitch
+rlabel metal2 13764 206 14377 369 1 vco_vctrl
+rlabel metal2 18091 1189 18520 1241 1 vco_out
+rlabel metal1 18878 1176 19279 1256 1 out_first_buffer
+rlabel via1 19587 1172 19999 1256 1 out_to_div
+rlabel metal1 6405 304 8963 408 1 iref_cp
+rlabel metal1 0 2578 3504 2816 1 vdd
+rlabel metal1 20560 1182 20839 1241 1 out_to_buffer
+rlabel metal1 48286 1072 49317 1356 1 out_to_pad
+rlabel metal1 33402 -2166 33728 24 1 vss
+rlabel metal3 27754 -1216 27814 -1004 1 n_out_div_2
+rlabel metal3 27797 -2793 28028 -2733 1 out_div_2
+rlabel metal1 27038 -2801 27439 -2721 1 out_buffer_div_2
+rlabel metal1 27038 -1284 27439 -1204 1 n_out_buffer_div_2
+rlabel metal2 26057 -1297 26552 -1188 1 n_out_by_2
+rlabel metal2 25015 -2807 26521 -2700 1 out_by_2
+rlabel metal4 20479 -5676 25576 -5584 1 clk_0
+rlabel metal4 20425 -4424 24306 -4332 1 n_clk_0
+rlabel metal4 19916 -2585 23200 -2519 1 n_clk_1
+rlabel metal4 19925 -1349 24474 -1283 1 clk_1
+rlabel metal2 8110 -2906 8344 -2747 1 clk_5
+rlabel metal2 7005 -5665 11034 -5535 1 clk_pre
+rlabel metal3 6677 -5289 6794 -3501 1 clk_out_mux21
+rlabel metal2 -311 -5413 3230 -5285 1 clk_d
+rlabel metal2 790 -2748 1121 -2631 1 clk_2_f
+rlabel metal3 -627 -3263 -495 518 1 out_div
+rlabel metal3 -95 -3783 -7 -1140 1 s_1
+rlabel metal3 406 -3784 494 -1140 1 s_1_n
+rlabel metal3 24728 -1073 24816 -773 1 s_0
+rlabel metal3 24078 -1074 24182 -1030 1 s_0_n
+rlabel metal2 12012 -6847 19619 -6720 1 MC
+rlabel metal4 19686 -7893 45045 -7093 1 lf_vc
+rlabel metal1 7710 -23526 8742 -23446 1 lf_D0
+rlabel metal3 16756 -71 16812 -15 1 vco_D0
+<< end >>
diff --git a/mag/trans_gate.mag b/mag/trans_gate.mag
index 96c6ca1..1e14885 100644
--- a/mag/trans_gate.mag
+++ b/mag/trans_gate.mag
@@ -1,10 +1,12 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624049879
+timestamp 1624653480
<< nwell >>
rect -53 635 569 723
+rect -53 -53 569 -47
<< pwell >>
+rect -53 -64 569 -53
rect -53 -811 569 -723
<< psubdiff >>
rect 55 -775 79 -741
@@ -117,13 +119,13 @@
rect 291 -766 359 -757
rect 299 -767 351 -766
use sky130_fd_pr__pfet_01v8_4798MH sky130_fd_pr__pfet_01v8_4798MH_0
-timestamp 1624049879
+timestamp 1624062693
transform 1 0 258 0 1 291
-box -311 -344 311 344
+box -311 -338 311 344
use sky130_fd_pr__nfet_01v8_BHR94T sky130_fd_pr__nfet_01v8_BHR94T_0
-timestamp 1624049879
+timestamp 1624062693
transform 1 0 258 0 1 -388
-box -311 -335 311 335
+box -311 -335 311 324
<< labels >>
rlabel metal1 217 599 569 653 1 vdd
rlabel metal1 -53 -741 299 -687 1 vss
diff --git a/mag/trans_gate_mux2to8.mag b/mag/trans_gate_mux2to8.mag
new file mode 100644
index 0000000..bdcdc9b
--- /dev/null
+++ b/mag/trans_gate_mux2to8.mag
@@ -0,0 +1,127 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624653480
+<< nwell >>
+rect -64 618 579 637
+rect -64 599 -17 618
+rect -64 -47 -40 599
+rect 568 -47 579 618
+rect -64 -53 579 -47
+<< pwell >>
+rect -64 -725 579 -53
+<< poly >>
+rect 147 69 371 135
+rect 279 30 371 69
+rect 279 -34 301 30
+rect 347 -34 371 30
+rect 279 -53 371 -34
+rect 145 -66 237 -53
+rect 145 -130 168 -66
+rect 214 -130 237 -66
+rect 145 -171 237 -130
+rect 145 -237 369 -171
+<< polycont >>
+rect 301 -34 347 30
+rect 168 -130 214 -66
+<< locali >>
+rect 281 30 363 50
+rect 281 -34 301 30
+rect 347 -34 363 30
+rect 151 -66 231 -48
+rect 281 -57 363 -34
+rect 151 -130 168 -66
+rect 214 -130 231 -66
+rect 151 -147 231 -130
+<< viali >>
+rect 79 565 437 599
+rect 301 -34 347 30
+rect 168 -130 214 -66
+rect 79 -687 437 -653
+<< metal1 >>
+rect 67 599 449 605
+rect 67 565 79 599
+rect 437 565 449 599
+rect 67 559 449 565
+rect 45 490 329 508
+rect -20 217 -10 490
+rect 58 462 329 490
+rect 58 404 137 462
+rect 283 404 329 462
+rect 58 217 97 404
+rect 45 -171 97 217
+rect 425 183 477 416
+rect 187 120 233 178
+rect 419 120 477 183
+rect 187 74 477 120
+rect 295 30 353 42
+rect 285 -34 295 30
+rect 353 -34 363 30
+rect 295 -46 353 -34
+rect 162 -66 220 -54
+rect 152 -130 162 -66
+rect 220 -130 230 -66
+rect 162 -142 220 -130
+rect 45 -217 329 -171
+rect 45 -341 97 -217
+rect 283 -263 329 -217
+rect 419 -309 477 74
+rect 45 -513 91 -341
+rect 419 -343 465 -309
+rect 425 -455 465 -343
+rect 419 -501 465 -455
+rect 187 -559 233 -513
+rect 379 -559 465 -501
+rect 187 -582 465 -559
+rect 533 -582 543 -309
+rect 187 -605 477 -582
+rect 67 -653 449 -647
+rect 67 -687 79 -653
+rect 437 -687 449 -653
+rect 67 -693 449 -687
+<< via1 >>
+rect -10 217 58 490
+rect 295 -34 301 30
+rect 301 -34 347 30
+rect 347 -34 353 30
+rect 162 -130 168 -66
+rect 168 -130 214 -66
+rect 214 -130 220 -66
+rect 465 -582 533 -309
+<< metal2 >>
+rect -10 490 58 500
+rect -10 207 58 217
+rect 295 30 353 40
+rect 295 -44 353 -34
+rect 162 -66 220 -56
+rect 162 -140 220 -130
+rect 465 -309 533 -299
+rect 465 -592 533 -582
+<< via2 >>
+rect -10 217 58 490
+rect 465 -582 533 -309
+<< metal3 >>
+rect -20 490 68 495
+rect -20 217 -10 490
+rect 58 217 68 490
+rect -20 212 68 217
+rect 455 -309 543 -304
+rect 455 -582 465 -309
+rect 533 -582 543 -309
+rect 455 -587 543 -582
+use sky130_fd_pr__pfet_01v8_4798MH sky130_fd_pr__pfet_01v8_4798MH_0
+timestamp 1624062693
+transform 1 0 258 0 1 291
+box -311 -338 311 344
+use sky130_fd_pr__nfet_01v8_BHR94T sky130_fd_pr__nfet_01v8_BHR94T_0
+timestamp 1624062693
+transform 1 0 258 0 1 -388
+box -311 -335 311 324
+<< labels >>
+rlabel metal1 67 -653 449 -647 1 vss
+rlabel metal1 67 559 449 565 1 vdd
+rlabel poly 279 -53 371 135 1 en_neg
+rlabel poly 145 -237 237 -53 1 en_pos
+rlabel metal1 419 -309 477 183 1 in
+rlabel metal1 45 -341 97 217 1 out
+<< end >>
diff --git a/xschem/freq_div.sch b/xschem/freq_div.sch
new file mode 100644
index 0000000..9069388
--- /dev/null
+++ b/xschem/freq_div.sch
@@ -0,0 +1,171 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 0 -30 0 0 { lab=vdd}
+N 40 -30 40 0 { lab=vss}
+N -40 -30 -40 0 { lab=MC}
+N -20 330 -20 360 { lab=vdd}
+N 20 330 20 360 { lab=vss}
+N 620 330 620 360 { lab=vdd}
+N 660 330 660 360 { lab=vss}
+N -30 160 -30 190 { lab=#net1}
+N -10 160 -10 190 { lab=#net2}
+N 10 160 10 190 { lab=#net3}
+N 30 160 30 190 { lab=#net4}
+N 610 520 610 550 { lab=#net5}
+N 630 520 630 550 { lab=#net6}
+N 650 520 650 550 { lab=#net7}
+N 670 520 670 550 { lab=#net8}
+N -40 520 -40 550 { lab=#net9}
+N -20 520 -20 550 { lab=#net10}
+N 0 520 0 550 { lab=#net11}
+N 20 520 20 550 { lab=#net12}
+N 40 520 40 550 { lab=#net13}
+N -320 60 -70 60 { lab=clk_0}
+N -220 420 -80 420 { lab=clk_1}
+N 710 460 740 460 { lab=#net14}
+N -450 80 -450 110 { lab=vdd}
+N -410 80 -410 110 { lab=vss}
+N -190 -300 -190 -270 { lab=vdd}
+N -190 -170 -190 -140 { lab=vss}
+N -450 430 -450 520 { lab=s_0}
+N -320 -220 -230 -220 { lab=s_0}
+N -410 430 -410 520 { lab=s_0_n}
+N -100 -220 -30 -220 { lab=s_0_n}
+N -520 230 -500 230 { lab=in_a}
+N -530 230 -520 230 { lab=in_a}
+N -520 310 -500 310 { lab=in_b}
+N -530 310 -520 310 { lab=in_b}
+N -280 100 -70 100 { lab=n_clk_0}
+N -180 460 -80 460 { lab=n_clk_1}
+N 1020 200 1120 200 { lab=out}
+N -360 190 -320 190 { lab=clk_0}
+N -320 60 -320 190 { lab=clk_0}
+N -360 230 -280 230 { lab=n_clk_0}
+N -280 100 -280 230 { lab=n_clk_0}
+N -360 350 -320 350 { lab=n_clk_1}
+N -320 460 -180 460 { lab=n_clk_1}
+N -320 350 -320 460 { lab=n_clk_1}
+N -360 310 -280 310 { lab=clk_1}
+N -280 310 -280 420 { lab=clk_1}
+N -280 420 -220 420 { lab=clk_1}
+N 70 80 260 80 { lab=clk_pre}
+N 80 440 160 440 { lab=clk_5}
+N 160 200 160 440 { lab=clk_5}
+N 160 200 260 200 { lab=clk_5}
+N 800 260 880 260 { lab=clk_2}
+N 350 -50 350 -20 { lab=vdd}
+N 310 -50 310 -20 { lab=vss}
+N 970 10 970 40 { lab=vdd}
+N 930 10 930 40 { lab=vss}
+N 350 300 350 390 { lab=s_0}
+N 310 300 310 390 { lab=s_0_n}
+N 330 -300 330 -270 { lab=vdd}
+N 330 -170 330 -140 { lab=vss}
+N 200 -220 290 -220 { lab=s_1}
+N 420 -220 490 -220 { lab=s_1_n}
+N 970 360 970 450 { lab=s_1}
+N 930 360 930 450 { lab=s_1_n}
+N 710 420 720 420 { lab=clk_2}
+N 610 140 670 140 { lab=#net15}
+N 800 140 880 140 { lab=clk_d}
+N 400 140 480 140 { lab=clk_out_mux21}
+N 440 140 440 440 { lab=clk_out_mux21}
+N 440 440 570 440 { lab=clk_out_mux21}
+N 720 420 800 420 { lab=clk_2}
+N 800 260 800 420 { lab=clk_2}
+N 520 60 520 90 { lab=vdd}
+N 520 190 520 220 { lab=vss}
+N 710 60 710 90 { lab=vdd}
+N 710 190 710 220 { lab=vss}
+N -240 10 -240 60 { lab=clk_0}
+N -240 100 -240 150 { lab=n_clk_0}
+N -240 370 -240 420 { lab=clk_1}
+N -240 460 -240 510 { lab=n_clk_1}
+N 220 30 220 80 { lab=clk_pre}
+N 220 200 220 250 { lab=clk_5}
+N 430 90 430 140 { lab=clk_out_mux21}
+N 860 90 860 140 { lab=clk_d}
+N 860 260 860 310 { lab=clk_2}
+N -70 -270 -70 -220 { lab=s_0_n}
+N 460 -270 460 -220 { lab=s_1_n}
+C {prescaler_23.sym} 0 80 0 0 {name=x2}
+C {div_by_2.sym} 640 440 0 0 {name=x3}
+C {div_by_5.sym} 0 440 0 0 {name=x4}
+C {lab_pin.sym} 0 -30 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 40 -30 1 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -20 330 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 20 330 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 620 330 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 660 330 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {noconn.sym} -30 190 3 0 {name=l18}
+C {noconn.sym} -10 190 3 0 {name=l19}
+C {noconn.sym} 10 190 3 0 {name=l20}
+C {noconn.sym} 30 190 3 0 {name=l22}
+C {noconn.sym} 610 550 3 0 {name=l17}
+C {noconn.sym} 630 550 3 0 {name=l21}
+C {noconn.sym} 650 550 3 0 {name=l23}
+C {noconn.sym} 670 550 3 0 {name=l24}
+C {noconn.sym} -40 550 3 0 {name=l30}
+C {noconn.sym} -20 550 3 0 {name=l31}
+C {noconn.sym} 0 550 3 0 {name=l32}
+C {noconn.sym} 20 550 3 0 {name=l33}
+C {noconn.sym} 40 550 3 0 {name=l34}
+C {noconn.sym} 740 460 2 0 {name=l42}
+C {inverter_min_x2.sym} -170 -220 0 0 {name=x9}
+C {lab_pin.sym} -190 -300 1 0 {name=l45 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -190 -140 3 0 {name=l46 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -450 520 3 0 {name=l51 sig_type=std_logic lab=s_0}
+C {lab_pin.sym} -410 520 3 0 {name=l52 sig_type=std_logic lab=s_0_n}
+C {lab_pin.sym} -30 -220 2 0 {name=l53 sig_type=std_logic lab=s_0_n}
+C {ipin.sym} -320 -220 0 0 {name=p1 sig_type=std_logic lab=s_0}
+C {iopin.sym} -450 80 3 0 {name=p2 sig_type=std_logic lab=vdd}
+C {iopin.sym} -410 80 3 0 {name=p3 sig_type=std_logic lab=vss}
+C {ipin.sym} -530 230 0 0 {name=p4 sig_type=std_logic lab=in_a}
+C {ipin.sym} -530 310 0 0 {name=p5 sig_type=std_logic lab=in_b}
+C {opin.sym} 1120 200 0 0 {name=p6 sig_type=std_logic lab=out}
+C {lab_wire.sym} -170 60 0 1 {name=l57 sig_type=std_logic lab=clk_0}
+C {lab_wire.sym} -170 100 0 1 {name=l60 sig_type=std_logic lab=n_clk_0}
+C {lab_wire.sym} -160 420 0 1 {name=l61 sig_type=std_logic lab=clk_1}
+C {lab_wire.sym} -160 460 0 1 {name=l62 sig_type=std_logic lab=n_clk_1}
+C {mux2to4.sym} -430 270 0 0 {name=x1}
+C {mux2to1.sym} 330 140 0 1 {name=x6}
+C {mux2to1.sym} 950 200 0 1 {name=x5}
+C {ipin.sym} -40 -30 1 0 {name=p7 sig_type=std_logic lab=MC}
+C {lab_pin.sym} 350 -50 3 1 {name=l3 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 310 -50 3 1 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 970 10 3 1 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 930 10 3 1 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 390 3 0 {name=l9 sig_type=std_logic lab=s_0}
+C {lab_pin.sym} 310 390 3 0 {name=l12 sig_type=std_logic lab=s_0_n}
+C {inverter_min_x2.sym} 350 -220 0 0 {name=x7}
+C {lab_pin.sym} 330 -300 1 0 {name=l13 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 330 -140 3 0 {name=l14 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 490 -220 2 0 {name=l15 sig_type=std_logic lab=s_1_n}
+C {ipin.sym} 200 -220 0 0 {name=p8 sig_type=std_logic lab=s_1}
+C {lab_pin.sym} 970 450 3 0 {name=l16 sig_type=std_logic lab=s_1}
+C {lab_pin.sym} 930 450 3 0 {name=l25 sig_type=std_logic lab=s_1_n}
+C {lab_wire.sym} 150 80 0 1 {name=l26 sig_type=std_logic lab=clk_pre}
+C {lab_wire.sym} 180 200 0 1 {name=l27 sig_type=std_logic lab=clk_5}
+C {lab_wire.sym} 820 140 0 1 {name=l28 sig_type=std_logic lab=clk_d}
+C {lab_wire.sym} 810 260 0 1 {name=l29 sig_type=std_logic lab=clk_2}
+C {inverter_min_x2.sym} 540 140 0 0 {name=x8}
+C {inverter_min_x4.sym} 730 140 0 0 {name=x10}
+C {lab_pin.sym} 520 60 1 0 {name=l35 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 520 220 3 0 {name=l36 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 710 60 1 0 {name=l37 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 710 220 3 0 {name=l38 sig_type=std_logic lab=vss}
+C {iopin.sym} -240 10 3 0 {name=p9 sig_type=std_logic lab=clk_0}
+C {iopin.sym} -240 150 1 0 {name=p10 sig_type=std_logic lab=n_clk_0}
+C {iopin.sym} -240 370 3 0 {name=p11 sig_type=std_logic lab=clk_1}
+C {iopin.sym} -240 510 1 0 {name=p12 sig_type=std_logic lab=n_clk_1}
+C {iopin.sym} 220 30 3 0 {name=p13 sig_type=std_logic lab=clk_pre}
+C {iopin.sym} 220 250 1 0 {name=p14 sig_type=std_logic lab=clk_5}
+C {iopin.sym} 430 90 3 0 {name=p15 sig_type=std_logic lab=clk_out_mux21}
+C {iopin.sym} 860 90 3 0 {name=p16 sig_type=std_logic lab=clk_d}
+C {iopin.sym} 860 310 1 0 {name=p17 sig_type=std_logic lab=clk_2}
+C {iopin.sym} -70 -270 3 0 {name=p18 sig_type=std_logic lab=s_0_n}
+C {iopin.sym} 460 -270 3 0 {name=p19 sig_type=std_logic lab=s_1_n}
diff --git a/xschem/freq_div.sym b/xschem/freq_div.sym
new file mode 100644
index 0000000..9fc4af8
--- /dev/null
+++ b/xschem/freq_div.sym
@@ -0,0 +1,90 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -80 -50 -60 {}
+L 4 -70 -80 -70 -60 {}
+L 4 -30 -80 -30 -60 {}
+L 4 140 0 160 0 {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 -60 60 60 60 {}
+L 4 140 -60 140 60 {}
+L 4 -60 -60 60 -60 {}
+L 4 -100 -60 -100 60 {}
+L 4 -50 40 50 40 {}
+L 4 60 60 100 60 {}
+L 4 -100 60 -60 60 {}
+L 4 -90 40 -50 40 {}
+L 4 -90 40 -90 60 {}
+L 4 50 40 90 40 {}
+L 4 130 40 130 60 {}
+L 4 70 -60 100 -60 {}
+L 4 60 -60 70 -60 {}
+L 4 -100 -60 -60 -60 {}
+L 4 100 60 140 60 {}
+L 4 90 40 130 40 {}
+L 4 100 -60 140 -60 {}
+L 4 -80 -60 -80 -40 {}
+L 4 -80 -40 -20 -40 {}
+L 4 -20 -60 -20 -40 {}
+L 7 120 60 120 80 {}
+L 7 100 60 100 80 {}
+L 7 -80 60 -80 80 {}
+L 7 0 60 0 80 {}
+L 7 100 -80 100 -60 {}
+L 7 80 -80 80 -60 {}
+L 7 40 60 40 80 {}
+L 7 60 60 60 80 {}
+L 7 -60 60 -60 80 {}
+L 7 20 60 20 80 {}
+L 7 80 60 80 80 {}
+L 7 -40 60 -40 80 {}
+L 7 -20 60 -20 80 {}
+B 5 117.5 77.5 122.5 82.5 {name=s_1_n sig_type=std_logic dir=inout }
+B 5 97.5 77.5 102.5 82.5 {name=s_0_n sig_type=std_logic dir=inout }
+B 5 -52.5 -82.5 -47.5 -77.5 {name=s_0 sig_type=std_logic dir=in }
+B 5 -72.5 -82.5 -67.5 -77.5 {name=s_1 sig_type=std_logic dir=in }
+B 5 -32.5 -82.5 -27.5 -77.5 {name=MC sig_type=std_logic dir=in }
+B 5 -82.5 77.5 -77.5 82.5 {name=clk_0 sig_type=std_logic dir=inout }
+B 5 -2.5 77.5 2.5 82.5 {name=clk_pre sig_type=std_logic dir=inout }
+B 5 97.5 -82.5 102.5 -77.5 {name=vss sig_type=std_logic dir=inout }
+B 5 77.5 -82.5 82.5 -77.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 37.5 77.5 42.5 82.5 {name=clk_out_mux21 sig_type=std_logic dir=inout }
+B 5 57.5 77.5 62.5 82.5 {name=clk_d sig_type=std_logic dir=inout }
+B 5 -62.5 77.5 -57.5 82.5 {name=n_clk_0 sig_type=std_logic dir=inout }
+B 5 157.5 -2.5 162.5 2.5 {name=out sig_type=std_logic dir=out }
+B 5 -122.5 -22.5 -117.5 -17.5 {name=in_a sig_type=std_logic dir=in }
+B 5 17.5 77.5 22.5 82.5 {name=clk_5 sig_type=std_logic dir=inout }
+B 5 77.5 77.5 82.5 82.5 {name=clk_2 sig_type=std_logic dir=inout }
+B 5 -122.5 17.5 -117.5 22.5 {name=in_b sig_type=std_logic dir=in }
+B 5 -42.5 77.5 -37.5 82.5 {name=clk_1 sig_type=std_logic dir=inout }
+B 5 -22.5 77.5 -17.5 82.5 {name=n_clk_1 sig_type=std_logic dir=inout }
+T {@symname} 131 69 0 0 0.3 0.3 {}
+T {@name} 0 -47 0 0 0.2 0.2 {}
+T {s_1_n} 119 95 1 1 0.2 0.2 {}
+T {s_0_n} 99 95 1 1 0.2 0.2 {}
+T {s_0} -64 -85 3 1 0.2 0.2 {}
+T {s_1} -84 -85 3 1 0.2 0.2 {}
+T {MC} -44 -85 3 1 0.2 0.2 {}
+T {clk_0} -94 105 3 0 0.2 0.2 {}
+T {clk_pre} -1 105 1 1 0.2 0.2 {}
+T {vss} 99 -85 1 0 0.2 0.2 {}
+T {vdd} 79 -85 1 0 0.2 0.2 {}
+T {clk_out_mux21} 39 140 1 1 0.2 0.2 {}
+T {clk_d} 59 105 1 1 0.2 0.2 {}
+T {n_clk_0} -74 105 3 0 0.2 0.2 {}
+T {out} 135 -4 0 1 0.2 0.2 {}
+T {in_a} -95 -24 0 0 0.2 0.2 {}
+T {clk_5} 19 105 1 1 0.2 0.2 {}
+T {clk_2} 79 105 1 1 0.2 0.2 {}
+T {in_b} -95 16 0 0 0.2 0.2 {}
+T {clk_1} -54 105 3 0 0.2 0.2 {}
+T {n_clk_1} -34 105 3 0 0.2 0.2 {}
+T {Control} -70 -56.5 0 0 0.2 0.2 {}
+T {Debug} 0 43.5 0 0 0.2 0.2 {}
diff --git a/xschem/freq_div_pex_c.sym b/xschem/freq_div_pex_c.sym
new file mode 100644
index 0000000..7099642
--- /dev/null
+++ b/xschem/freq_div_pex_c.sym
@@ -0,0 +1,90 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -80 -50 -60 {}
+L 4 -70 -80 -70 -60 {}
+L 4 -30 -80 -30 -60 {}
+L 4 140 0 160 0 {}
+L 4 -120 -20 -100 -20 {}
+L 4 -120 20 -100 20 {}
+L 4 -60 60 60 60 {}
+L 4 140 -60 140 60 {}
+L 4 -60 -60 60 -60 {}
+L 4 -100 -60 -100 60 {}
+L 4 -50 40 50 40 {}
+L 4 60 60 100 60 {}
+L 4 -100 60 -60 60 {}
+L 4 -90 40 -50 40 {}
+L 4 -90 40 -90 60 {}
+L 4 50 40 90 40 {}
+L 4 130 40 130 60 {}
+L 4 70 -60 100 -60 {}
+L 4 60 -60 70 -60 {}
+L 4 -100 -60 -60 -60 {}
+L 4 100 60 140 60 {}
+L 4 90 40 130 40 {}
+L 4 100 -60 140 -60 {}
+L 4 -80 -60 -80 -40 {}
+L 4 -80 -40 -20 -40 {}
+L 4 -20 -60 -20 -40 {}
+L 7 120 60 120 80 {}
+L 7 100 60 100 80 {}
+L 7 -80 60 -80 80 {}
+L 7 0 60 0 80 {}
+L 7 100 -80 100 -60 {}
+L 7 80 -80 80 -60 {}
+L 7 40 60 40 80 {}
+L 7 60 60 60 80 {}
+L 7 -60 60 -60 80 {}
+L 7 20 60 20 80 {}
+L 7 80 60 80 80 {}
+L 7 -40 60 -40 80 {}
+L 7 -20 60 -20 80 {}
+B 5 117.5 77.5 122.5 82.5 {name=s_1_n sig_type=std_logic dir=inout }
+B 5 97.5 77.5 102.5 82.5 {name=s_0_n sig_type=std_logic dir=inout }
+B 5 -52.5 -82.5 -47.5 -77.5 {name=s_0 sig_type=std_logic dir=in }
+B 5 -72.5 -82.5 -67.5 -77.5 {name=s_1 sig_type=std_logic dir=in }
+B 5 -32.5 -82.5 -27.5 -77.5 {name=MC sig_type=std_logic dir=in }
+B 5 -82.5 77.5 -77.5 82.5 {name=clk_0 sig_type=std_logic dir=inout }
+B 5 -2.5 77.5 2.5 82.5 {name=clk_pre sig_type=std_logic dir=inout }
+B 5 97.5 -82.5 102.5 -77.5 {name=vss sig_type=std_logic dir=inout }
+B 5 77.5 -82.5 82.5 -77.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 37.5 77.5 42.5 82.5 {name=clk_out_mux21 sig_type=std_logic dir=inout }
+B 5 57.5 77.5 62.5 82.5 {name=clk_d sig_type=std_logic dir=inout }
+B 5 -62.5 77.5 -57.5 82.5 {name=n_clk_0 sig_type=std_logic dir=inout }
+B 5 157.5 -2.5 162.5 2.5 {name=out sig_type=std_logic dir=out }
+B 5 -122.5 -22.5 -117.5 -17.5 {name=in_a sig_type=std_logic dir=in }
+B 5 17.5 77.5 22.5 82.5 {name=clk_5 sig_type=std_logic dir=inout }
+B 5 77.5 77.5 82.5 82.5 {name=clk_2 sig_type=std_logic dir=inout }
+B 5 -122.5 17.5 -117.5 22.5 {name=in_b sig_type=std_logic dir=in }
+B 5 -42.5 77.5 -37.5 82.5 {name=clk_1 sig_type=std_logic dir=inout }
+B 5 -22.5 77.5 -17.5 82.5 {name=n_clk_1 sig_type=std_logic dir=inout }
+T {@symname} 131 69 0 0 0.3 0.3 {}
+T {@name} 0 -47 0 0 0.2 0.2 {}
+T {s_1_n} 119 95 1 1 0.2 0.2 {}
+T {s_0_n} 99 95 1 1 0.2 0.2 {}
+T {s_0} -64 -85 3 1 0.2 0.2 {}
+T {s_1} -84 -85 3 1 0.2 0.2 {}
+T {MC} -44 -85 3 1 0.2 0.2 {}
+T {clk_0} -94 105 3 0 0.2 0.2 {}
+T {clk_pre} -1 105 1 1 0.2 0.2 {}
+T {vss} 99 -85 1 0 0.2 0.2 {}
+T {vdd} 79 -85 1 0 0.2 0.2 {}
+T {clk_out_mux21} 39 140 1 1 0.2 0.2 {}
+T {clk_d} 59 105 1 1 0.2 0.2 {}
+T {n_clk_0} -74 105 3 0 0.2 0.2 {}
+T {out} 135 -4 0 1 0.2 0.2 {}
+T {in_a} -95 -24 0 0 0.2 0.2 {}
+T {clk_5} 19 105 1 1 0.2 0.2 {}
+T {clk_2} 79 105 1 1 0.2 0.2 {}
+T {in_b} -95 16 0 0 0.2 0.2 {}
+T {clk_1} -54 105 3 0 0.2 0.2 {}
+T {n_clk_1} -34 105 3 0 0.2 0.2 {}
+T {Control} -70 -56.5 0 0 0.2 0.2 {}
+T {Debug} 0 43.5 0 0 0.2 0.2 {}
diff --git a/xschem/loop_filter_v2_pex_c.sym b/xschem/loop_filter_v2_pex_c.sym
new file mode 100644
index 0000000..64d1857
--- /dev/null
+++ b/xschem/loop_filter_v2_pex_c.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 40 -50 40 50 {}
+L 4 -40 -50 -40 50 {}
+L 4 -40 -50 40 -50 {}
+L 4 -40 50 40 50 {}
+L 7 0 50 0 70 {}
+L 7 0 -70 0 -50 {}
+L 7 40 0 60 0 {}
+L 7 -60 0 -40 0 {}
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+B 5 -2.5 -72.5 2.5 -67.5 {name=in dir=inout }
+B 5 57.5 -2.5 62.5 2.5 {name=vc_pex dir=inout }
+B 5 -62.5 -2.5 -57.5 2.5 {name=D0_cap dir=inout }
+T {@symname} 52.5 34 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vss} -6 75 1 1 0.2 0.2 {}
+T {in} -14 -75 3 1 0.2 0.2 {}
+T {vc_pex} 75 -14 0 1 0.2 0.2 {}
+T {D0_cap} -85 -16 0 0 0.2 0.2 {}
diff --git a/xschem/mux2to1.sch b/xschem/mux2to1.sch
new file mode 100644
index 0000000..d3a4d9a
--- /dev/null
+++ b/xschem/mux2to1.sch
@@ -0,0 +1,38 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 470 -950 470 -910 { lab=in_a}
+N 340 -1040 380 -1040 { lab=selec_0}
+N 340 -1040 340 -820 { lab=selec_0}
+N 340 -820 370 -820 { lab=selec_0}
+N 570 -1040 600 -1040 { lab=selec_0_neg}
+N 600 -1040 600 -820 { lab=selec_0_neg}
+N 560 -820 600 -820 { lab=selec_0_neg}
+N 470 -1130 690 -1130 { lab=out_a_1}
+N 470 -730 690 -730 { lab=out_a_0}
+N 380 -930 470 -930 { lab=in_a}
+N 380 -1000 380 -960 { lab=vss}
+N 560 -900 560 -860 { lab=vss}
+N 570 -1000 570 -960 { lab=vdd}
+N 370 -900 370 -860 { lab=vdd}
+C {trans_gate_mux2to8.sym} 470 -1040 3 0 {name=x4}
+C {trans_gate_mux2to8.sym} 470 -820 1 0 {name=x5}
+C {lab_pin.sym} 430 -930 0 0 {name=l27 sig_type=std_logic lab=in_a}
+C {lab_pin.sym} 690 -1130 2 0 {name=l36 sig_type=std_logic lab=out_a_1}
+C {lab_pin.sym} 690 -730 2 0 {name=l37 sig_type=std_logic lab=out_a_0}
+C {lab_pin.sym} 340 -950 2 1 {name=l60 sig_type=std_logic lab=selec_0}
+C {lab_pin.sym} 600 -850 0 1 {name=l62 sig_type=std_logic lab=selec_0_neg}
+C {iopin.sym} 970 -1150 0 0 {name=p4 lab=in_a}
+C {ipin.sym} 920 -980 0 0 {name=p5 lab=selec_0_neg}
+C {ipin.sym} 920 -1020 0 0 {name=p6 lab=selec_0}
+C {iopin.sym} 970 -1040 0 0 {name=p13 lab=out_a_0}
+C {iopin.sym} 970 -990 0 0 {name=p14 lab=out_a_1}
+C {iopin.sym} 970 -1210 0 0 {name=p15 lab=vdd}
+C {iopin.sym} 970 -1190 0 0 {name=p16 lab=vss}
+C {lab_pin.sym} 380 -970 1 1 {name=l17 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 560 -890 3 1 {name=l18 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 570 -970 1 1 {name=l20 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 370 -890 3 1 {name=l21 sig_type=std_logic lab=vdd}
diff --git a/xschem/mux2to1.sym b/xschem/mux2to1.sym
new file mode 100644
index 0000000..125e6b0
--- /dev/null
+++ b/xschem/mux2to1.sym
@@ -0,0 +1,45 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -20 140 -20 160 {}
+L 4 20 140 20 160 {}
+L 4 -50 140 50 140 {}
+L 4 -50 -140 50 -140 {}
+L 4 -40 120 -40 140 {}
+L 4 -40 120 40 120 {}
+L 4 40 120 40 140 {}
+L 4 50 80 50 140 {}
+L 4 50 -140 50 -80 {}
+L 4 50 -60 50 -20 {}
+L 4 50 40 50 80 {}
+L 4 50 -20 50 60 {}
+L 4 -50 -140 -50 140 {}
+L 4 50 -80 50 -60 {}
+L 7 -20 -160 -20 -140 {}
+L 7 20 -160 20 -140 {}
+L 7 -70 0 -50 0 {}
+L 7 50 -60 70 -60 {}
+L 7 50 60 70 60 {}
+B 5 -22.5 -162.5 -17.5 -157.5 {name=vdd dir=inout }
+B 5 17.5 -162.5 22.5 -157.5 {name=vss dir=inout }
+B 5 -72.5 -2.5 -67.5 2.5 {name=in_a dir=inout }
+B 5 67.5 -62.5 72.5 -57.5 {name=out_a_0 dir=inout }
+B 5 -22.5 157.5 -17.5 162.5 {name=selec_0 dir=in }
+B 5 67.5 57.5 72.5 62.5 {name=out_a_1 dir=inout }
+B 5 17.5 157.5 22.5 162.5 {name=selec_0_neg dir=in }
+T {@symname} 30.5 144 0 0 0.3 0.3 {}
+T {@name} -25 -132 0 0 0.2 0.2 {}
+T {vdd} -34 -165 3 1 0.2 0.2 {}
+T {vss} 6 -165 3 1 0.2 0.2 {}
+T {in_a} -45 4 2 1 0.2 0.2 {}
+T {out_a_0} 45 -64 0 1 0.2 0.2 {}
+T {selec_0} -34 205 3 0 0.2 0.2 {}
+T {out_a_1} 45 56 0 1 0.2 0.2 {}
+T {selec_0_neg} 6 205 3 0 0.2 0.2 {}
+T {Select} 15 126 0 1 0.2 0.2 {}
diff --git a/xschem/mux2to4.sch b/xschem/mux2to4.sch
new file mode 100644
index 0000000..1c4564e
--- /dev/null
+++ b/xschem/mux2to4.sch
@@ -0,0 +1,66 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 470 -950 470 -910 { lab=in_a}
+N 340 -1040 380 -1040 { lab=selec_0}
+N 340 -1040 340 -820 { lab=selec_0}
+N 340 -820 370 -820 { lab=selec_0}
+N 570 -1040 600 -1040 { lab=selec_0_neg}
+N 600 -1040 600 -820 { lab=selec_0_neg}
+N 560 -820 600 -820 { lab=selec_0_neg}
+N 470 -1420 470 -1380 { lab=in_b}
+N 340 -1510 380 -1510 { lab=selec_0}
+N 340 -1510 340 -1290 { lab=selec_0}
+N 340 -1290 370 -1290 { lab=selec_0}
+N 570 -1510 600 -1510 { lab=selec_0_neg}
+N 600 -1510 600 -1290 { lab=selec_0_neg}
+N 560 -1290 600 -1290 { lab=selec_0_neg}
+N 470 -1600 690 -1600 { lab=out_b_1}
+N 470 -1200 690 -1200 { lab=out_b_0}
+N 470 -1130 690 -1130 { lab=out_a_1}
+N 470 -730 690 -730 { lab=out_a_0}
+N 380 -1400 470 -1400 { lab=in_b}
+N 380 -930 470 -930 { lab=in_a}
+N 380 -1470 380 -1430 { lab=vss}
+N 560 -1370 560 -1330 { lab=vss}
+N 570 -1470 570 -1430 { lab=vdd}
+N 370 -1370 370 -1330 { lab=vdd}
+N 380 -1000 380 -960 { lab=vss}
+N 560 -900 560 -860 { lab=vss}
+N 570 -1000 570 -960 { lab=vdd}
+N 370 -900 370 -860 { lab=vdd}
+C {trans_gate_mux2to8.sym} 470 -1040 3 0 {name=x4}
+C {trans_gate_mux2to8.sym} 470 -820 1 0 {name=x5}
+C {trans_gate_mux2to8.sym} 470 -1510 3 0 {name=x8}
+C {trans_gate_mux2to8.sym} 470 -1290 1 0 {name=x9}
+C {lab_pin.sym} 380 -1400 0 0 {name=l19 sig_type=std_logic lab=in_b}
+C {lab_pin.sym} 430 -930 0 0 {name=l27 sig_type=std_logic lab=in_a}
+C {lab_pin.sym} 690 -1600 2 0 {name=l28 sig_type=std_logic lab=out_b_1}
+C {lab_pin.sym} 690 -1200 2 0 {name=l31 sig_type=std_logic lab=out_b_0}
+C {lab_pin.sym} 690 -1130 2 0 {name=l36 sig_type=std_logic lab=out_a_1}
+C {lab_pin.sym} 690 -730 2 0 {name=l37 sig_type=std_logic lab=out_a_0}
+C {lab_pin.sym} 340 -1440 2 1 {name=l59 sig_type=std_logic lab=selec_0}
+C {lab_pin.sym} 340 -950 2 1 {name=l60 sig_type=std_logic lab=selec_0}
+C {lab_pin.sym} 600 -1350 0 1 {name=l61 sig_type=std_logic lab=selec_0_neg}
+C {lab_pin.sym} 600 -850 0 1 {name=l62 sig_type=std_logic lab=selec_0_neg}
+C {iopin.sym} 970 -1150 0 0 {name=p4 lab=in_a}
+C {iopin.sym} 970 -1110 0 0 {name=p1 lab=in_b}
+C {ipin.sym} 920 -980 0 0 {name=p5 lab=selec_0_neg}
+C {ipin.sym} 920 -1020 0 0 {name=p6 lab=selec_0}
+C {iopin.sym} 970 -1060 0 0 {name=p9 lab=out_b_0}
+C {iopin.sym} 970 -1010 0 0 {name=p10 lab=out_b_1}
+C {iopin.sym} 970 -1040 0 0 {name=p13 lab=out_a_0}
+C {iopin.sym} 970 -990 0 0 {name=p14 lab=out_a_1}
+C {iopin.sym} 970 -1210 0 0 {name=p15 lab=vdd}
+C {iopin.sym} 970 -1190 0 0 {name=p16 lab=vss}
+C {lab_pin.sym} 380 -1440 1 1 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 560 -1360 3 1 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 570 -1440 1 1 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 370 -1360 3 1 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 380 -970 1 1 {name=l17 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 560 -890 3 1 {name=l18 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 570 -970 1 1 {name=l20 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 370 -890 3 1 {name=l21 sig_type=std_logic lab=vdd}
diff --git a/xschem/mux2to4.sym b/xschem/mux2to4.sym
new file mode 100644
index 0000000..7f89850
--- /dev/null
+++ b/xschem/mux2to4.sym
@@ -0,0 +1,53 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -20 140 -20 160 {}
+L 4 20 140 20 160 {}
+L 4 -50 140 50 140 {}
+L 4 -50 -140 50 -140 {}
+L 4 -40 120 -40 140 {}
+L 4 -40 120 40 120 {}
+L 4 40 120 40 140 {}
+L 4 50 80 50 140 {}
+L 4 50 -140 50 -80 {}
+L 4 50 -80 50 -40 {}
+L 4 50 40 50 80 {}
+L 4 50 -40 50 40 {}
+L 4 -50 -140 -50 140 {}
+L 7 -20 -160 -20 -140 {}
+L 7 20 -160 20 -140 {}
+L 7 -70 -40 -50 -40 {}
+L 7 -70 40 -50 40 {}
+L 7 50 -40 70 -40 {}
+L 7 50 -80 70 -80 {}
+L 7 50 80 70 80 {}
+L 7 50 40 70 40 {}
+B 5 -22.5 -162.5 -17.5 -157.5 {name=vdd dir=inout }
+B 5 17.5 -162.5 22.5 -157.5 {name=vss dir=inout }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=in_a dir=inout }
+B 5 -72.5 37.5 -67.5 42.5 {name=in_b dir=inout }
+B 5 67.5 -42.5 72.5 -37.5 {name=out_b_0 dir=inout }
+B 5 67.5 -82.5 72.5 -77.5 {name=out_a_0 dir=inout }
+B 5 -22.5 157.5 -17.5 162.5 {name=selec_0 dir=in }
+B 5 67.5 77.5 72.5 82.5 {name=out_b_1 dir=inout }
+B 5 67.5 37.5 72.5 42.5 {name=out_a_1 dir=inout }
+B 5 17.5 157.5 22.5 162.5 {name=selec_0_neg dir=in }
+T {@symname} 30.5 144 0 0 0.3 0.3 {}
+T {@name} -25 -132 0 0 0.2 0.2 {}
+T {vdd} -34 -165 3 1 0.2 0.2 {}
+T {vss} 6 -165 3 1 0.2 0.2 {}
+T {in_a} -45 -36 2 1 0.2 0.2 {}
+T {in_b} -45 44 2 1 0.2 0.2 {}
+T {out_b_0} 45 -44 0 1 0.2 0.2 {}
+T {out_a_0} 45 -84 0 1 0.2 0.2 {}
+T {selec_0} -34 205 3 0 0.2 0.2 {}
+T {out_b_1} 45 76 0 1 0.2 0.2 {}
+T {out_a_1} 45 36 0 1 0.2 0.2 {}
+T {selec_0_neg} 6 205 3 0 0.2 0.2 {}
+T {Select} 15 126 0 1 0.2 0.2 {}
diff --git a/xschem/prescaler_23.sch b/xschem/prescaler_23.sch
new file mode 100644
index 0000000..b8d39d1
--- /dev/null
+++ b/xschem/prescaler_23.sch
@@ -0,0 +1,83 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 530 -0 600 -0 { lab=2}
+N 350 20 410 20 { lab=1}
+N 120 0 230 0 { lab=Q1}
+N 200 40 230 40 { lab=MC}
+N 200 40 200 170 { lab=MC}
+N -80 0 -20 0 { lab=nCLK_23}
+N 1610 0 1670 0 { lab=CLK_23}
+N -80 40 -20 40 { lab=CLK}
+N -80 80 -20 80 { lab=nCLK}
+N 540 80 610 80 { lab=nCLK}
+N 540 40 600 40 { lab=CLK}
+N 50 120 50 180 { lab=vss}
+N 50 -100 50 -40 { lab=vdd}
+N 670 -100 670 -40 { lab=vdd}
+N 670 120 670 180 { lab=vss}
+N 200 170 200 180 { lab=MC}
+N 380 -20 410 -20 { lab=nCLK_23}
+N 740 80 770 80 { lab=nCLK_23}
+N 770 80 800 80 { lab=nCLK_23}
+N 1010 40 1080 40 { lab=nCLK}
+N 1020 80 1080 80 { lab=CLK}
+N 1010 0 1080 -0 { lab=Q2}
+N 1150 -100 1150 -40 { lab=vdd}
+N 1150 120 1150 180 { lab=vss}
+N 1220 -0 1280 0 { lab=Q2_d}
+N 1040 -180 1040 0 { lab=Q2}
+N 1040 -180 1230 -180 { lab=Q2}
+N 1230 -180 1230 -40 { lab=Q2}
+N 1230 -40 1280 -40 { lab=Q2}
+N 1400 -20 1530 -20 { lab=3}
+N 1480 20 1530 20 { lab=nCLK_23}
+N 1480 60 1530 60 { lab=MC}
+N 740 -0 1010 0 { lab=Q2}
+N 120 80 140 80 { lab=#net1}
+N 1220 80 1250 80 { lab=#net2}
+N 200 -50 200 0 { lab=Q1}
+N 860 -50 860 0 { lab=Q2}
+N 1280 50 1330 50 { lab=Q2_d}
+N 1270 50 1280 50 { lab=Q2_d}
+N 1270 -0 1270 50 { lab=Q2_d}
+C {sky130_stdcells/and2_1.sym} 470 0 0 0 {name=x3 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {sky130_stdcells/or2_1.sym} 290 20 0 0 {name=x4 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {iopin.sym} 50 -100 3 0 {name=p1 lab=vdd}
+C {ipin.sym} -80 40 0 0 {name=p2 lab=CLK}
+C {ipin.sym} -80 80 0 0 {name=p3 lab=nCLK}
+C {ipin.sym} 200 180 3 0 {name=p4 lab=MC}
+C {iopin.sym} 50 180 1 0 {name=p5 lab=vss}
+C {opin.sym} 1670 0 0 0 {name=p6 lab=CLK_23}
+C {lab_wire.sym} 180 0 0 0 {name=l2 sig_type=std_logic lab=Q1}
+C {lab_pin.sym} 380 -20 0 0 {name=l3 sig_type=std_logic lab=nCLK_23}
+C {lab_pin.sym} 540 80 0 0 {name=l5 sig_type=std_logic lab=nCLK}
+C {lab_pin.sym} 540 40 0 0 {name=l6 sig_type=std_logic lab=CLK}
+C {lab_pin.sym} 670 180 3 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 670 -100 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 390 20 0 0 {name=l9 sig_type=std_logic lab=1}
+C {lab_wire.sym} 560 0 0 0 {name=l10 sig_type=std_logic lab=2}
+C {lab_pin.sym} 1010 40 2 1 {name=l4 sig_type=std_logic lab=nCLK}
+C {lab_pin.sym} 1020 80 2 1 {name=l11 sig_type=std_logic lab=CLK}
+C {lab_pin.sym} 1150 180 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1150 -100 1 0 {name=l14 sig_type=std_logic lab=vdd}
+C {sky130_stdcells/mux2_1.sym} 1570 0 0 0 {name=x6 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {sky130_stdcells/or2_1.sym} 1340 -20 0 0 {name=x7 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {lab_pin.sym} 1250 0 3 0 {name=l15 sig_type=std_logic lab=Q2_d}
+C {lab_pin.sym} 1480 20 0 0 {name=l16 sig_type=std_logic lab=nCLK_23}
+C {lab_pin.sym} 1480 60 0 0 {name=l17 sig_type=std_logic lab=MC}
+C {lab_pin.sym} 1040 -60 0 0 {name=l12 sig_type=std_logic lab=Q2}
+C {lab_wire.sym} 1470 -20 0 0 {name=l18 sig_type=std_logic lab=3}
+C {lab_pin.sym} -80 0 0 0 {name=l19 sig_type=std_logic lab=nCLK_23}
+C {DFlipFlop.sym} 50 40 0 0 {name=x1}
+C {DFlipFlop.sym} 670 40 0 0 {name=x2}
+C {DFlipFlop.sym} 1150 40 0 0 {name=x5}
+C {noconn.sym} 140 80 2 0 {name=l20}
+C {noconn.sym} 1250 80 2 0 {name=l21}
+C {iopin.sym} 800 80 0 0 {name=p8 lab=nCLK_23}
+C {iopin.sym} 200 -50 3 0 {name=p7 lab=Q1}
+C {iopin.sym} 860 -50 3 0 {name=p9 lab=Q2}
+C {iopin.sym} 1330 50 0 0 {name=p10 lab=Q2_d}
diff --git a/xschem/prescaler_23.sym b/xschem/prescaler_23.sym
new file mode 100644
index 0000000..1187db8
--- /dev/null
+++ b/xschem/prescaler_23.sym
@@ -0,0 +1,58 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -70 -20 -50 -20 {}
+L 4 -70 20 -50 20 {}
+L 4 -40 -80 -40 -60 {}
+L 4 -50 -40 -50 40 {}
+L 4 -50 -60 50 -60 {}
+L 4 50 -40 50 40 {}
+L 4 -50 60 50 60 {}
+L 4 -50 -30 -40 -20 {}
+L 4 -50 -10 -40 -20 {}
+L 4 -50 10 -40 20 {}
+L 4 -50 30 -40 20 {}
+L 4 -50 40 -50 60 {}
+L 4 50 40 50 60 {}
+L 4 -50 -60 -50 -40 {}
+L 4 50 -60 50 -40 {}
+L 4 40 50 40 60 {}
+L 4 40 40 40 50 {}
+L 4 -40 40 40 40 {}
+L 4 -40 40 -40 60 {}
+L 7 0 -80 0 -60 {}
+L 7 40 -80 40 -60 {}
+L 7 -10 60 -10 80 {}
+L 7 -30 60 -30 80 {}
+L 7 10 60 10 80 {}
+L 7 30 60 30 80 {}
+B 5 -2.5 -82.5 2.5 -77.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=CLK_23 dir=out }
+B 5 -72.5 -22.5 -67.5 -17.5 {name=CLK dir=in }
+B 5 -72.5 17.5 -67.5 22.5 {name=nCLK dir=in }
+B 5 37.5 -82.5 42.5 -77.5 {name=vss dir=inout }
+B 5 -42.5 -82.5 -37.5 -77.5 {name=MC dir=in }
+B 5 -12.5 77.5 -7.5 82.5 {name=Q1 dir=inout }
+B 5 -32.5 77.5 -27.5 82.5 {name=nCLK_23 dir=inout }
+B 5 7.5 77.5 12.5 82.5 {name=Q2 dir=inout }
+B 5 27.5 77.5 32.5 82.5 {name=Q2_d dir=inout }
+T {@symname} 58 64 0 0 0.3 0.3 {}
+T {@name} -15 -52 0 0 0.2 0.2 {}
+T {vdd} -14 -85 3 1 0.2 0.2 {}
+T {CLK_23} 45 -4 0 1 0.2 0.2 {}
+T {CLK} -35 -24 0 0 0.2 0.2 {}
+T {nCLK} -35 16 0 0 0.2 0.2 {}
+T {vss} 26 -85 3 1 0.2 0.2 {}
+T {MC} -56 -65 3 0 0.2 0.2 {}
+T {Q1} 4 95 1 1 0.2 0.2 {}
+T {nCLK_23} -16 115 1 1 0.2 0.2 {}
+T {Q2} 24 95 1 1 0.2 0.2 {}
+T {Q2_d} 44 95 1 1 0.2 0.2 {}
+T {Debug} -15 46 0 0 0.2 0.2 {}
diff --git a/xschem/prescaler_23_pex_c.sym b/xschem/prescaler_23_pex_c.sym
new file mode 100644
index 0000000..1a55b47
--- /dev/null
+++ b/xschem/prescaler_23_pex_c.sym
@@ -0,0 +1,58 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -70 -20 -50 -20 {}
+L 4 -70 20 -50 20 {}
+L 4 -40 -80 -40 -60 {}
+L 4 -50 -40 -50 40 {}
+L 4 -50 -60 50 -60 {}
+L 4 50 -40 50 40 {}
+L 4 -50 60 50 60 {}
+L 4 -50 -30 -40 -20 {}
+L 4 -50 -10 -40 -20 {}
+L 4 -50 10 -40 20 {}
+L 4 -50 30 -40 20 {}
+L 4 -50 40 -50 60 {}
+L 4 50 40 50 60 {}
+L 4 -50 -60 -50 -40 {}
+L 4 50 -60 50 -40 {}
+L 4 40 50 40 60 {}
+L 4 40 40 40 50 {}
+L 4 -40 40 40 40 {}
+L 4 -40 40 -40 60 {}
+L 7 0 -80 0 -60 {}
+L 7 40 -80 40 -60 {}
+L 7 -10 60 -10 80 {}
+L 7 -30 60 -30 80 {}
+L 7 10 60 10 80 {}
+L 7 30 60 30 80 {}
+B 5 -2.5 -82.5 2.5 -77.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=CLK_23 dir=out }
+B 5 -72.5 -22.5 -67.5 -17.5 {name=CLK dir=in }
+B 5 -72.5 17.5 -67.5 22.5 {name=nCLK dir=in }
+B 5 37.5 -82.5 42.5 -77.5 {name=vss dir=inout }
+B 5 -42.5 -82.5 -37.5 -77.5 {name=MC dir=in }
+B 5 -12.5 77.5 -7.5 82.5 {name=Q1 dir=inout }
+B 5 -32.5 77.5 -27.5 82.5 {name=nCLK_23 dir=inout }
+B 5 7.5 77.5 12.5 82.5 {name=Q2 dir=inout }
+B 5 27.5 77.5 32.5 82.5 {name=Q2_d dir=inout }
+T {@symname} 58 64 0 0 0.3 0.3 {}
+T {@name} -15 -52 0 0 0.2 0.2 {}
+T {vdd} -14 -85 3 1 0.2 0.2 {}
+T {CLK_23} 45 -4 0 1 0.2 0.2 {}
+T {CLK} -35 -24 0 0 0.2 0.2 {}
+T {nCLK} -35 16 0 0 0.2 0.2 {}
+T {vss} 26 -85 3 1 0.2 0.2 {}
+T {MC} -56 -65 3 0 0.2 0.2 {}
+T {Q1} 4 95 1 1 0.2 0.2 {}
+T {nCLK_23} -16 115 1 1 0.2 0.2 {}
+T {Q2} 24 95 1 1 0.2 0.2 {}
+T {Q2_d} 44 95 1 1 0.2 0.2 {}
+T {Debug} -15 46 0 0 0.2 0.2 {}
diff --git a/xschem/simulations/freq_div.spice b/xschem/simulations/freq_div.spice
new file mode 100644
index 0000000..d72e8fc
--- /dev/null
+++ b/xschem/simulations/freq_div.spice
@@ -0,0 +1,291 @@
+**.subckt freq_div s_0 vdd vss in_a in_b out MC s_1 clk_0 n_clk_0 clk_1 n_clk_1 clk_pre clk_5
+*+ clk_out_mux21 clk_d clk_2 s_0_n s_1_n
+*.ipin s_0
+*.iopin vdd
+*.iopin vss
+*.ipin in_a
+*.ipin in_b
+*.opin out
+*.ipin MC
+*.ipin s_1
+*.iopin clk_0
+*.iopin n_clk_0
+*.iopin clk_1
+*.iopin n_clk_1
+*.iopin clk_pre
+*.iopin clk_5
+*.iopin clk_out_mux21
+*.iopin clk_d
+*.iopin clk_2
+*.iopin s_0_n
+*.iopin s_1_n
+x2 vdd clk_pre clk_0 n_clk_0 vss MC net2 net1 net3 net4 prescaler_23
+x3 net14 vss clk_out_mux21 vdd clk_2 net5 net6 net7 net8 div_by_2
+x4 vdd clk_5 clk_1 vss n_clk_1 net9 net10 net12 net13 net11 div_by_5
+x9 vdd s_0_n s_0 vss inverter_min_x2
+x1 vdd vss in_a in_b n_clk_0 clk_0 s_0 n_clk_1 clk_1 s_0_n mux2to4
+x6 vdd vss clk_out_mux21 clk_pre s_0 clk_5 s_0_n mux2to1
+x5 vdd vss out clk_d s_1 clk_2 s_1_n mux2to1
+x7 vdd s_1_n s_1 vss inverter_min_x2
+x8 vdd net15 clk_out_mux21 vss inverter_min_x2
+x10 vdd clk_d net15 vss inverter_min_x4
+**.ends
+
+* expanding symbol: prescaler_23/sch/prescaler_23.sym # of pins=10
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/prescaler_23/sch/prescaler_23.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/prescaler_23/sch/prescaler_23.sch
+.subckt prescaler_23 vdd CLK_23 CLK nCLK vss MC Q1 nCLK_23 Q2 Q2_d
+*.iopin vdd
+*.ipin CLK
+*.ipin nCLK
+*.ipin MC
+*.iopin vss
+*.opin CLK_23
+*.iopin nCLK_23
+*.iopin Q1
+*.iopin Q2
+*.iopin Q2_d
+x3 nCLK_23 1 vss vss vdd vdd 2 sky130_fd_sc_hs__and2_1
+x4 Q1 MC vss vss vdd vdd 1 sky130_fd_sc_hs__or2_1
+x6 3 nCLK_23 MC vss vss vdd vdd CLK_23 sky130_fd_sc_hs__mux2_1
+x7 Q2 Q2_d vss vss vdd vdd 3 sky130_fd_sc_hs__or2_1
+x1 vdd Q1 net1 vss nCLK_23 CLK nCLK DFlipFlop
+x2 vdd Q2 nCLK_23 vss 2 CLK nCLK DFlipFlop
+x5 vdd Q2_d net2 vss Q2 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: div_by_2/sch/div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/div_by_2/sch/div_by_2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/div_by_2/sch/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: div_by_5/sch/div_by_5.sym # of pins=10
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/div_by_5/sch/div_by_5.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/div_by_5/sch/div_by_5.sch
+.subckt div_by_5 vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: inverter_min_x2/sch/inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: mux2to4/sch/mux2to4.sym # of pins=10
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/mux2to4/sch/mux2to4.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/mux2to4/sch/mux2to4.sch
+.subckt mux2to4 vdd vss in_a in_b out_b_0 out_a_0 selec_0 out_b_1 out_a_1 selec_0_neg
+*.iopin in_a
+*.iopin in_b
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_b_0
+*.iopin out_b_1
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+x8 selec_0 out_b_1 in_b selec_0_neg vss vdd trans_gate_mux2to8
+x9 selec_0_neg out_b_0 in_b selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
+* expanding symbol: mux2to1/sch/mux2to1.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/mux2to1/sch/mux2to1.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/mux2to1/sch/mux2to1.sch
+.subckt mux2to1 vdd vss in_a out_a_0 selec_0 out_a_1 selec_0_neg
+*.iopin in_a
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
+* expanding symbol: inverter_min_x4/sch/inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x4/sch/inverter_min_x4.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x4/sch/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: DFlipFlop/sch/DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/DFlipFlop/sch/DFlipFlop.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/DFlipFlop/sch/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter/sch/clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/clock_inverter/sch/clock_inverter.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/clock_inverter/sch/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: trans_gate_mux2to8/sch/trans_gate_mux2to8.sym # of pins=6
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate_mux2to8/sch/trans_gate_mux2to8.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate_mux2to8/sch/trans_gate_mux2to8.sch
+.subckt trans_gate_mux2to8 en_pos out in en_neg vss vdd
+*.iopin en_neg
+*.ipin in
+*.opin out
+*.iopin en_pos
+*.iopin vdd
+*.iopin vss
+XM2 out en_neg in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out en_pos in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: latch_diff/sch/latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/latch_diff/sch/latch_diff.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/latch_diff/sch/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate/sch/trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate/sch/trans_gate.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate/sch/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1/sch/inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_cp_x1/sch/inverter_cp_x1.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_cp_x1/sch/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/freq_div_pex_c.spice b/xschem/simulations/freq_div_pex_c.spice
new file mode 100644
index 0000000..2e62ee7
--- /dev/null
+++ b/xschem/simulations/freq_div_pex_c.spice
@@ -0,0 +1,1379 @@
+* NGSPICE file created from freq_div.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n81_n125# 0.13fF
+C1 a_15_n125# a_n81_n125# 0.36fF
+C2 w_n311_n344# a_n173_n125# 0.14fF
+C3 w_n311_n344# a_111_n125# 0.14fF
+C4 a_15_n125# w_n311_n344# 0.09fF
+C5 a_81_n156# a_n15_n156# 0.02fF
+C6 a_111_n125# a_n173_n125# 0.08fF
+C7 a_15_n125# a_n173_n125# 0.13fF
+C8 a_15_n125# a_111_n125# 0.36fF
+C9 w_n311_n344# a_n81_n125# 0.09fF
+C10 a_n15_n156# a_n111_n156# 0.02fF
+C11 a_n173_n125# a_n81_n125# 0.36fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.11fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_n81_n125# a_n173_n125# 0.36fF
+C2 a_n15_n151# a_n111_n151# 0.02fF
+C3 a_81_n151# a_n15_n151# 0.02fF
+C4 a_111_n125# a_n173_n125# 0.08fF
+C5 a_n81_n125# a_15_n125# 0.36fF
+C6 a_111_n125# a_15_n125# 0.36fF
+C7 a_111_n125# a_n81_n125# 0.13fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# vss m1_45_n513# vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_45_n513# vdd 0.69fF
+C1 m1_187_n605# vdd 0.55fF
+C2 m1_187_n605# m1_45_n513# 0.36fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_15_n125# 0.36fF
+C1 a_15_n125# w_n311_n344# 0.09fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 a_111_n125# w_n311_n344# 0.14fF
+C4 a_111_n125# a_n81_n125# 0.13fF
+C5 w_n311_n344# a_n81_n125# 0.09fF
+C6 a_n173_n125# a_15_n125# 0.13fF
+C7 a_111_n125# a_n173_n125# 0.08fF
+C8 a_n173_n125# w_n311_n344# 0.14fF
+C9 a_n173_n125# a_n81_n125# 0.36fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n81_n125# 0.36fF
+C1 a_111_n125# a_15_n125# 0.36fF
+C2 a_n173_n125# a_111_n125# 0.08fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_n81_n125# a_15_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vdd vss
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 in out 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d vss inverter_cp_x1_0/out vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vdd vss inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vdd vss inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vdd vss inverter_cp_x1
+C0 vdd CLK_d 0.03fF
+C1 inverter_cp_x1_2/in CLK_d 0.12fF
+C2 inverter_cp_x1_2/in vdd 0.21fF
+C3 CLK inverter_cp_x1_0/out 0.31fF
+C4 inverter_cp_x1_0/out nCLK_d 0.11fF
+C5 vdd inverter_cp_x1_0/out 0.28fF
+C6 CLK vdd 0.36fF
+C7 CLK inverter_cp_x1_2/in 0.31fF
+C8 vdd nCLK_d 0.03fF
+C9 inverter_cp_x1_2/in vss 2.01fF
+C10 CLK_d vss 0.96fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 vdd vss 16.35fF
+C14 nCLK_d vss 1.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n33_n95# 0.28fF
+C1 w_n263_n314# a_63_n95# 0.11fF
+C2 w_n263_n314# a_n33_n95# 0.08fF
+C3 w_n263_n314# a_n125_n95# 0.11fF
+C4 a_63_n95# a_n33_n95# 0.28fF
+C5 a_n125_n95# a_63_n95# 0.10fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_15_n125# 0.36fF
+C1 a_n129_n213# a_111_n125# 0.01fF
+C2 a_n173_n125# a_n81_n125# 0.36fF
+C3 a_n129_n213# a_15_n125# 0.10fF
+C4 a_n173_n125# a_n129_n213# 0.02fF
+C5 a_n129_n213# a_n81_n125# 0.10fF
+C6 a_111_n125# a_15_n125# 0.36fF
+C7 a_n173_n125# a_111_n125# 0.08fF
+C8 a_n81_n125# a_111_n125# 0.13fF
+C9 a_n173_n125# a_15_n125# 0.13fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n33_n95# 0.88fF
+C1 a_n125_n95# a_n81_n183# 0.16fF
+C2 a_n81_n183# a_n33_n95# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 D nQ 0.05fF
+C1 Q m1_657_280# 0.94fF
+C2 Q nQ 0.93fF
+C3 nD nQ 0.05fF
+C4 Q vdd 0.16fF
+C5 m1_657_280# nQ 1.41fF
+C6 Q D 0.05fF
+C7 m1_657_280# CLK 0.24fF
+C8 vdd nQ 0.16fF
+C9 Q nD 0.05fF
+C10 D vss 0.53fF
+C11 nD vss 0.16fF
+C12 m1_657_280# vss 1.88fF
+C13 CLK vss 0.87fF
+C14 Q vss -0.55fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vdd vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ latch_diff_0/nD Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D CLK
++ clock_inverter_0/inverter_cp_x1_0/out nCLK
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C1 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C2 nQ latch_diff_1/D 0.11fF
+C3 latch_diff_1/nD vdd 0.02fF
+C4 vdd latch_diff_0/nD 0.14fF
+C5 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C6 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C7 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C8 latch_diff_1/nD latch_diff_0/D 0.04fF
+C9 vdd latch_diff_0/D 0.09fF
+C10 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
+C11 latch_diff_1/nD nQ 0.08fF
+C12 latch_diff_1/nD Q 0.01fF
+C13 latch_diff_1/nD latch_diff_1/D 0.33fF
+C14 latch_diff_1/D latch_diff_0/nD 0.41fF
+C15 vdd latch_diff_1/D 0.03fF
+C16 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
+C17 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C18 latch_diff_0/D latch_diff_1/D 0.11fF
+C19 latch_diff_1/m1_657_280# vss 0.64fF
+C20 nCLK vss 0.83fF
+C21 Q vss -0.92fF
+C22 nQ vss 0.57fF
+C23 latch_diff_0/m1_657_280# vss 0.72fF
+C24 CLK vss 0.83fF
+C25 latch_diff_1/D vss -0.30fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C28 latch_diff_0/D vss 1.29fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 vdd vss 32.52fF
+C32 latch_diff_0/nD vss 1.74fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n33_n84# a_159_n84# 0.09fF
+C1 a_159_n84# w_n359_n303# 0.08fF
+C2 a_159_n84# a_n221_n84# 0.04fF
+C3 a_63_n84# a_n129_n84# 0.09fF
+C4 a_n33_n84# a_n129_n84# 0.24fF
+C5 a_n129_n84# w_n359_n303# 0.06fF
+C6 a_n129_n84# a_n221_n84# 0.24fF
+C7 a_63_n84# a_n33_n84# 0.24fF
+C8 a_63_n84# w_n359_n303# 0.06fF
+C9 a_n159_n110# a_n63_n110# 0.02fF
+C10 a_63_n84# a_n221_n84# 0.05fF
+C11 a_n33_n84# w_n359_n303# 0.05fF
+C12 a_n33_n84# a_n221_n84# 0.09fF
+C13 w_n359_n303# a_n221_n84# 0.08fF
+C14 a_33_n110# a_n63_n110# 0.02fF
+C15 a_33_n110# a_129_n110# 0.02fF
+C16 a_159_n84# a_n129_n84# 0.05fF
+C17 a_63_n84# a_159_n84# 0.24fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_33_n68# a_129_n68# 0.02fF
+C1 a_159_n42# a_63_n42# 0.12fF
+C2 a_n129_n42# a_n33_n42# 0.12fF
+C3 a_63_n42# a_n221_n42# 0.03fF
+C4 a_159_n42# a_n221_n42# 0.02fF
+C5 a_63_n42# a_n33_n42# 0.12fF
+C6 a_33_n68# a_n63_n68# 0.02fF
+C7 a_159_n42# a_n33_n42# 0.05fF
+C8 a_n221_n42# a_n33_n42# 0.05fF
+C9 a_63_n42# a_n129_n42# 0.05fF
+C10 a_n159_n68# a_n63_n68# 0.02fF
+C11 a_159_n42# a_n129_n42# 0.03fF
+C12 a_n221_n42# a_n129_n42# 0.12fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 out vdd 0.62fF
+C1 out in 0.67fF
+C2 vdd in 0.33fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_n33_n42# a_n125_n42# 0.12fF
+C2 a_n33_n42# a_63_n42# 0.12fF
+C3 a_63_n42# a_n125_n42# 0.05fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n63_n110# a_33_n110# 0.02fF
+C1 a_n125_n84# w_n263_n303# 0.10fF
+C2 a_n125_n84# a_63_n84# 0.09fF
+C3 a_63_n84# w_n263_n303# 0.10fF
+C4 a_n125_n84# a_n33_n84# 0.24fF
+C5 a_n33_n84# w_n263_n303# 0.07fF
+C6 a_63_n84# a_n33_n84# 0.24fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 vdd out 0.15fF
+C1 in out 0.30fF
+C2 vdd in 0.01fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 CLK_2 vss vdd o1 CLK
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/latch_diff_0/nD
++ out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_1 o2 nCLK_2 vss vdd inverter_min_x4
+Xinverter_min_x4_0 o1 CLK_2 vss vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 nout_div DFlipFlop_0/latch_diff_1/m1_657_280# 0.21fF
+C1 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C2 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
+C3 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C4 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C5 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C6 o2 vdd 0.14fF
+C7 DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.29fF
+C8 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
+C9 o1 vdd 0.14fF
+C10 vdd nout_div 0.16fF
+C11 DFlipFlop_0/latch_diff_0/D DFlipFlop_0/nCLK 0.13fF
+C12 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/nD 0.12fF
+C13 o1 out_div 0.01fF
+C14 nout_div out_div 0.22fF
+C15 o2 nCLK_2 0.11fF
+C16 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C17 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
+C18 vdd out_div 0.03fF
+C19 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C20 nout_div DFlipFlop_0/CLK 0.42fF
+C21 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C22 vdd nCLK_2 0.08fF
+C23 vdd DFlipFlop_0/CLK 0.40fF
+C24 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
+C25 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C26 o1 CLK_2 0.11fF
+C27 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C28 nout_div DFlipFlop_0/nCLK 0.43fF
+C29 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C30 vdd CLK_2 0.08fF
+C31 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C32 vdd DFlipFlop_0/nCLK 0.30fF
+C33 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C34 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C35 CLK_2 vss 1.08fF
+C36 o1 vss 2.21fF
+C37 nCLK_2 vss 1.08fF
+C38 o2 vss 2.21fF
+C39 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C40 DFlipFlop_0/CLK vss 1.03fF
+C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C42 CLK vss 3.27fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C45 out_div vss -0.77fF
+C46 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C50 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 vdd vss 64.24fF
+C54 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+.ends
+
+.subckt trans_gate_mux2to8 in vss out en_pos en_neg vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss en_neg in out out vdd en_neg en_neg in sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 en_pos vss en_pos in out out en_pos in sky130_fd_pr__nfet_01v8_BHR94T
+C0 vdd in 0.05fF
+C1 en_neg en_pos 0.04fF
+C2 en_neg out 0.07fF
+C3 en_pos out 0.27fF
+C4 vdd out 0.68fF
+C5 en_neg in 0.28fF
+C6 en_pos in 0.07fF
+C7 out in 0.36fF
+C8 vdd vss 2.63fF
+C9 in vss 1.53fF
+C10 out vss 0.88fF
+C11 en_pos vss 0.29fF
+C12 en_neg vss 0.31fF
+.ends
+
+.subckt mux2to1 vss select_0_neg out_a_0 out_a_1 select_0 vdd in_a
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 out_a_1 vdd 0.09fF
+C1 select_0 in_a 0.31fF
+C2 select_0_neg select_0 0.17fF
+C3 select_0_neg in_a 0.11fF
+C4 in_a vdd 0.14fF
+C5 out_a_1 select_0 0.14fF
+C6 out_a_0 in_a 0.08fF
+C7 out_a_0 select_0_neg 0.05fF
+C8 out_a_1 in_a 0.08fF
+C9 out_a_0 vdd 0.09fF
+C10 out_a_1 vss 1.03fF
+C11 vdd vss 5.88fF
+C12 in_a vss 2.43fF
+C13 out_a_0 vss 1.03fF
+C14 select_0_neg vss 1.15fF
+C15 select_0 vss 0.97fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_194_125# VPWR 0.33fF
+C1 a_355_368# A 0.02fF
+C2 a_194_125# X 0.29fF
+C3 B VGND 0.10fF
+C4 a_194_125# a_355_368# 0.51fF
+C5 X VPWR 0.07fF
+C6 VGND A 0.31fF
+C7 a_355_368# VPWR 0.37fF
+C8 a_194_125# VGND 0.25fF
+C9 B A 0.28fF
+C10 a_355_368# X 0.17fF
+C11 a_194_125# B 0.57fF
+C12 VPB VPWR 0.06fF
+C13 VGND VPWR 0.01fF
+C14 B VPWR 0.09fF
+C15 a_194_125# A 0.18fF
+C16 X VGND 0.28fF
+C17 a_194_125# a_158_392# 0.06fF
+C18 X B 0.13fF
+C19 VPWR A 0.15fF
+C20 a_355_368# B 0.08fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 VPWR a_56_136# 0.57fF
+C1 VGND X 0.15fF
+C2 X VPWR 0.20fF
+C3 X a_56_136# 0.26fF
+C4 A B 0.08fF
+C5 VGND A 0.21fF
+C6 A VPWR 0.07fF
+C7 VGND B 0.03fF
+C8 A a_56_136# 0.17fF
+C9 VPWR B 0.02fF
+C10 a_56_136# B 0.30fF
+C11 VPB VPWR 0.04fF
+C12 X B 0.02fF
+C13 VGND a_56_136# 0.06fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 a_63_368# B 0.14fF
+C1 VPWR VPB 0.04fF
+C2 VGND X 0.16fF
+C3 A X 0.02fF
+C4 VPWR X 0.18fF
+C5 a_63_368# X 0.33fF
+C6 a_63_368# a_152_368# 0.03fF
+C7 VPWR A 0.05fF
+C8 a_63_368# VGND 0.27fF
+C9 a_63_368# A 0.28fF
+C10 a_63_368# VPWR 0.29fF
+C11 VGND B 0.11fF
+C12 A B 0.10fF
+C13 VPWR B 0.01fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 nCLK DFlipFlop_0/D DFlipFlop_0/latch_diff_1/nD vss Q1 CLK DFlipFlop_0/Q
++ vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_0/D DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/nD CLK_5 Q1_shift nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_1/latch_diff_1/D nQ0
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in Q0 DFlipFlop_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/nQ DFlipFlop_2/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_152_368# sky130_fd_sc_hs__and2_1_1/a_56_136#
++ DFlipFlop_3/nQ sky130_fd_sc_hs__and2_1_0/a_143_136# DFlipFlop_2/latch_diff_0/nD
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vdd vss DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out CLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C1 DFlipFlop_2/D Q0 0.25fF
+C2 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C3 Q1 vdd 9.49fF
+C4 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q0 0.42fF
+C5 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C6 DFlipFlop_0/Q nQ2 0.09fF
+C7 nCLK DFlipFlop_1/latch_diff_1/D 0.08fF
+C8 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C9 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C10 CLK Q1 -0.10fF
+C11 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C12 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C13 nCLK DFlipFlop_2/nQ 0.09fF
+C14 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C15 nCLK DFlipFlop_0/Q 0.11fF
+C16 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C17 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C18 nCLK nQ2 0.10fF
+C19 Q1 Q0 9.65fF
+C20 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C21 DFlipFlop_1/D nCLK 0.14fF
+C22 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C23 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C24 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C25 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C26 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
+C27 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C28 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C29 Q1 Q1_shift 0.36fF
+C30 Q1 DFlipFlop_3/latch_diff_1/m1_657_280# 0.28fF
+C31 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
+C32 DFlipFlop_2/latch_diff_0/D nCLK 0.11fF
+C33 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C34 nQ0 Q1 0.06fF
+C35 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
+C36 DFlipFlop_3/nQ nCLK 0.02fF
+C37 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C38 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C39 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C40 vdd DFlipFlop_2/nQ 0.02fF
+C41 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C42 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C43 Q1 DFlipFlop_0/D 0.13fF
+C44 nQ2 vdd 0.04fF
+C45 CLK DFlipFlop_2/nQ 0.13fF
+C46 DFlipFlop_1/latch_diff_0/nD CLK 0.08fF
+C47 DFlipFlop_1/D vdd 0.25fF
+C48 sky130_fd_sc_hs__xor2_1_0/a_355_368# Q0 0.03fF
+C49 CLK DFlipFlop_0/Q 0.08fF
+C50 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C51 CLK nQ2 0.17fF
+C52 nCLK vdd 0.34fF
+C53 DFlipFlop_1/D CLK 0.21fF
+C54 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C55 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C56 Q1_shift sky130_fd_sc_hs__or2_1_0/a_63_368# -0.27fF
+C57 DFlipFlop_0/Q Q0 0.21fF
+C58 nQ2 Q0 0.23fF
+C59 vdd CLK_5 0.15fF
+C60 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C61 DFlipFlop_3/nQ vdd 0.02fF
+C62 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C63 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C64 DFlipFlop_1/D Q0 0.07fF
+C65 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C66 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C67 DFlipFlop_3/nQ CLK 0.01fF
+C68 nCLK Q0 0.20fF
+C69 DFlipFlop_2/latch_diff_1/nD CLK 0.09fF
+C70 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C71 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C72 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C73 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C74 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C75 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
+C76 nQ0 nQ2 0.03fF
+C77 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C78 nQ0 DFlipFlop_1/D 0.12fF
+C79 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C80 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C81 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C82 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C83 Q1 DFlipFlop_2/D 0.10fF
+C84 nQ0 nCLK 0.09fF
+C85 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C86 CLK vdd 0.41fF
+C87 DFlipFlop_3/nQ Q1_shift 0.04fF
+C88 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C89 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C90 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C91 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C92 vdd Q0 5.33fF
+C93 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
+C94 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C95 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C96 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C97 CLK Q0 0.08fF
+C98 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C99 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
+C100 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C101 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C102 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C103 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C104 Q1_shift vdd 0.10fF
+C105 Q1 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C106 nQ0 vdd 0.11fF
+C107 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C108 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C109 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C110 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C111 nQ0 CLK 0.19fF
+C112 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C113 Q1 DFlipFlop_3/latch_diff_1/D 0.79fF
+C114 DFlipFlop_0/latch_diff_0/D Q0 0.42fF
+C115 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C116 DFlipFlop_0/D vdd 0.19fF
+C117 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C118 nQ0 Q0 0.33fF
+C119 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C120 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C121 nQ0 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.04fF
+C122 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C123 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C124 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C125 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
+C126 nCLK DFlipFlop_2/D 0.41fF
+C127 DFlipFlop_0/D Q0 0.39fF
+C128 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C129 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C130 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C131 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C132 Q1 DFlipFlop_2/nQ 0.31fF
+C133 Q1 DFlipFlop_0/Q 0.13fF
+C134 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C135 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.28fF
+C136 Q1 nQ2 0.07fF
+C137 DFlipFlop_1/D Q1 0.03fF
+C138 nQ0 DFlipFlop_1/latch_diff_0/m1_657_280# 0.25fF
+C139 nCLK DFlipFlop_1/latch_diff_1/nD 0.16fF
+C140 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C141 Q1 nCLK -0.01fF
+C142 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C143 DFlipFlop_2/D vdd 0.07fF
+C144 nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
+C145 DFlipFlop_2/latch_diff_0/D Q1 0.42fF
+C146 Q1 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C147 sky130_fd_sc_hs__and2_1_1/a_56_136# vdd 0.04fF
+C148 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C149 DFlipFlop_3/nQ Q1 0.10fF
+C150 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C151 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
+C152 CLK DFlipFlop_2/D 0.14fF
+C153 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C154 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C155 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C156 nCLK DFlipFlop_3/latch_diff_1/D 0.14fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/nQ vss 0.52fF
+C164 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C168 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 Q1 vss 8.55fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C172 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C173 DFlipFlop_2/nQ vss 0.50fF
+C174 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C177 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C178 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C183 Q0 vss 0.53fF
+C184 nQ0 vss 3.42fF
+C185 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C188 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C194 nCLK vss 0.89fF
+C195 DFlipFlop_0/Q vss -0.94fF
+C196 nQ2 vss 2.05fF
+C197 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C198 CLK vss 0.07fF
+C199 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C200 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C202 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 vdd vss 146.47fF
+C206 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt mux2to4 vss out_b_1 out_b_0 select_0 out_a_0 select_0_neg out_a_1 vdd in_a
++ in_b
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_11 in_b vss out_b_1 select_0 select_0_neg vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_10 in_b vss out_b_0 select_0_neg select_0 vdd trans_gate_mux2to8
+C0 out_b_1 vdd 0.09fF
+C1 in_b select_0 0.24fF
+C2 in_a out_b_0 0.11fF
+C3 select_0 out_b_0 0.03fF
+C4 in_b vdd 0.17fF
+C5 out_b_0 vdd 0.15fF
+C6 in_b select_0_neg 0.10fF
+C7 select_0_neg out_b_0 -0.13fF
+C8 in_a select_0 0.31fF
+C9 in_a vdd 0.17fF
+C10 select_0 vdd 0.02fF
+C11 in_a select_0_neg 0.22fF
+C12 select_0_neg select_0 0.49fF
+C13 out_a_1 in_b 0.08fF
+C14 select_0_neg vdd 0.02fF
+C15 out_a_1 out_b_0 0.88fF
+C16 out_a_1 in_a 0.08fF
+C17 out_a_1 select_0 0.18fF
+C18 out_a_1 vdd 0.16fF
+C19 out_a_0 in_a 0.08fF
+C20 in_b out_b_1 0.08fF
+C21 out_a_1 select_0_neg 0.12fF
+C22 out_a_0 vdd 0.09fF
+C23 out_a_0 select_0_neg 0.05fF
+C24 in_b out_b_0 0.08fF
+C25 out_b_1 select_0 0.14fF
+C26 in_b vss 2.46fF
+C27 out_b_0 vss 0.84fF
+C28 out_b_1 vss 1.03fF
+C29 out_a_1 vss 0.32fF
+C30 vdd vss 11.72fF
+C31 in_a vss 2.46fF
+C32 out_a_0 vss 1.03fF
+C33 select_0_neg vss 2.57fF
+C34 select_0 vss 2.23fF
+.ends
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X a_304_74# a_443_74# a_524_368#
++ a_27_112#
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VPB VPWR 0.06fF
+C1 a_304_74# VGND 0.58fF
+C2 a_524_368# a_27_112# 0.06fF
+C3 a_27_112# a_223_368# 0.09fF
+C4 a_304_74# a_226_74# 0.08fF
+C5 a_304_74# a_27_112# 0.58fF
+C6 a_304_74# A0 0.23fF
+C7 a_304_74# A1 0.69fF
+C8 S VPWR 0.05fF
+C9 a_304_74# X 0.29fF
+C10 a_443_74# A1 0.07fF
+C11 a_27_112# VGND 0.18fF
+C12 VGND A0 0.02fF
+C13 VGND A1 0.09fF
+C14 VGND X 0.11fF
+C15 a_27_112# A0 0.07fF
+C16 a_27_112# A1 0.18fF
+C17 a_304_74# VPWR 0.13fF
+C18 A0 A1 0.31fF
+C19 a_27_112# X 0.08fF
+C20 A1 X 0.02fF
+C21 a_304_74# S 0.18fF
+C22 VGND VPWR 0.02fF
+C23 a_27_112# VPB 0.01fF
+C24 S VGND 0.07fF
+C25 a_304_74# a_223_368# 0.05fF
+C26 a_27_112# VPWR 0.99fF
+C27 A1 VPWR 0.01fF
+C28 VPWR X 0.28fF
+C29 a_27_112# S 0.22fF
+C30 S A0 0.04fF
+C31 S A1 0.10fF
+C32 a_304_74# a_443_74# 0.12fF
+C33 VGND VNB 0.88fF
+C34 X VNB 0.25fF
+C35 VPWR VNB 0.89fF
+C36 A1 VNB 0.37fF
+C37 A0 VNB 0.23fF
+C38 S VNB 0.34fF
+C39 VPB VNB 0.87fF
+C40 a_304_74# VNB 0.36fF
+C41 a_27_112# VNB 0.65fF
+.ends
+
+.subckt prescaler_23 nCLK vss DFlipFlop_0/latch_diff_1/nD nCLK_23 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ CLK_23 DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/latch_diff_1/D DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1_0/a_304_74# sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__mux2_1_0/a_524_368#
++ sky130_fd_sc_hs__mux2_1_0/a_27_112# sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ DFlipFlop_0/latch_diff_0/nD
++ Q1 DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_0/D
++ CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out nCLK DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ Q2_d DFlipFlop_2/latch_diff_1/nD Q2 DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/latch_diff_0/D
++ nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK_23 DFlipFlop_1/latch_diff_0/nD
++ Q2 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1_0/a_143_136# sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1_1/a_152_368#
++ sky130_fd_sc_hs__or2_1_1/a_63_368# sky130_fd_sc_hs__or2_1
+C0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 0.26fF
+C1 vdd CLK_23 0.16fF
+C2 Q2 sky130_fd_sc_hs__or2_1_1/X 0.24fF
+C3 Q1 sky130_fd_sc_hs__or2_1_0/X 0.06fF
+C4 sky130_fd_sc_hs__mux2_1_0/a_27_112# nCLK_23 0.07fF
+C5 DFlipFlop_1/D sky130_fd_sc_hs__or2_1_0/X 0.35fF
+C6 MC Q1 0.29fF
+C7 DFlipFlop_1/latch_diff_1/nD nCLK 0.18fF
+C8 sky130_fd_sc_hs__or2_1_0/X nCLK_23 0.07fF
+C9 CLK DFlipFlop_2/nQ 0.02fF
+C10 MC nCLK_23 4.46fF
+C11 Q2 DFlipFlop_2/latch_diff_1/D 0.13fF
+C12 DFlipFlop_2/latch_diff_0/nD nCLK 0.09fF
+C13 MC Q2 0.18fF
+C14 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C15 sky130_fd_sc_hs__and2_1_0/a_56_136# nCLK_23 0.14fF
+C16 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C17 CLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.05fF
+C18 CLK DFlipFlop_1/latch_diff_1/D 0.18fF
+C19 DFlipFlop_0/latch_diff_0/nD nCLK_23 0.12fF
+C20 DFlipFlop_2/latch_diff_1/nD CLK 0.19fF
+C21 sky130_fd_sc_hs__and2_1_0/a_143_136# nCLK_23 0.02fF
+C22 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.16fF
+C23 DFlipFlop_2/nQ nCLK 0.02fF
+C24 vdd CLK 0.34fF
+C25 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.06fF
+C26 DFlipFlop_2/latch_diff_0/D CLK 0.13fF
+C27 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C28 DFlipFlop_1/latch_diff_1/D nCLK 0.09fF
+C29 MC sky130_fd_sc_hs__or2_1_1/X 0.02fF
+C30 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.10fF
+C31 DFlipFlop_2/latch_diff_1/nD nCLK 0.12fF
+C32 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C33 MC sky130_fd_sc_hs__mux2_1_0/a_27_112# 0.24fF
+C34 MC sky130_fd_sc_hs__or2_1_0/X 0.09fF
+C35 Q1 DFlipFlop_0/latch_diff_1/nD 0.03fF
+C36 vdd nCLK -0.55fF
+C37 Q2 DFlipFlop_2/nQ 0.13fF
+C38 sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C39 DFlipFlop_0/latch_diff_1/nD nCLK_23 0.02fF
+C40 vdd Q2_d 0.02fF
+C41 sky130_fd_sc_hs__mux2_1_0/a_443_74# nCLK_23 0.09fF
+C42 Q2 sky130_fd_sc_hs__or2_1_1/a_63_368# 0.09fF
+C43 Q1 CLK -0.07fF
+C44 DFlipFlop_1/latch_diff_0/D nCLK 0.02fF
+C45 CLK DFlipFlop_1/D 0.40fF
+C46 CLK nCLK_23 0.22fF
+C47 vdd Q1 0.07fF
+C48 Q2 DFlipFlop_2/latch_diff_1/nD 0.17fF
+C49 Q2 CLK 0.29fF
+C50 CLK DFlipFlop_0/latch_diff_1/D 0.04fF
+C51 vdd DFlipFlop_1/D 0.07fF
+C52 vdd nCLK_23 3.35fF
+C53 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.02fF
+C54 vdd Q2 1.63fF
+C55 DFlipFlop_2/latch_diff_0/D Q2 0.30fF
+C56 sky130_fd_sc_hs__or2_1_0/a_63_368# nCLK 0.05fF
+C57 Q1 nCLK -0.02fF
+C58 Q2 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.38fF
+C59 CLK DFlipFlop_0/nQ 0.15fF
+C60 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.29fF
+C61 DFlipFlop_1/D nCLK 0.16fF
+C62 nCLK nCLK_23 0.11fF
+C63 sky130_fd_sc_hs__mux2_1_0/a_304_74# nCLK_23 0.04fF
+C64 sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__or2_1_1/X 0.03fF
+C65 Q2 nCLK 0.29fF
+C66 sky130_fd_sc_hs__or2_1_0/a_152_368# nCLK 0.01fF
+C67 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C68 DFlipFlop_2/latch_diff_0/m1_657_280# nCLK 0.31fF
+C69 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.09fF
+C70 Q2 Q2_d 0.66fF
+C71 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out nCLK_23 0.49fF
+C72 vdd sky130_fd_sc_hs__or2_1_1/X 0.03fF
+C73 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.31fF
+C74 Q1 nCLK_23 0.02fF
+C75 CLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.33fF
+C76 CLK sky130_fd_sc_hs__or2_1_0/X 0.01fF
+C77 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1 0.01fF
+C78 DFlipFlop_0/nQ nCLK 0.11fF
+C79 Q1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.06fF
+C80 DFlipFlop_1/D nCLK_23 0.02fF
+C81 CLK DFlipFlop_2/latch_diff_1/D 0.09fF
+C82 MC CLK 0.08fF
+C83 Q2 nCLK_23 0.03fF
+C84 vdd sky130_fd_sc_hs__or2_1_0/X 0.03fF
+C85 DFlipFlop_0/latch_diff_1/D nCLK_23 0.05fF
+C86 sky130_fd_sc_hs__and2_1_0/a_56_136# CLK 0.08fF
+C87 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.31fF
+C88 MC vdd 0.88fF
+C89 sky130_fd_sc_hs__mux2_1_0/a_304_74# sky130_fd_sc_hs__or2_1_1/X 0.08fF
+C90 Q2_d sky130_fd_sc_hs__or2_1_1/X 0.03fF
+C91 Q1 DFlipFlop_0/nQ -0.02fF
+C92 DFlipFlop_1/latch_diff_1/nD CLK 0.11fF
+C93 DFlipFlop_0/nQ nCLK_23 0.05fF
+C94 sky130_fd_sc_hs__or2_1_0/X nCLK 0.06fF
+C95 DFlipFlop_2/latch_diff_1/D nCLK 0.16fF
+C96 DFlipFlop_2/latch_diff_1/m1_657_280# Q2_d 0.03fF
+C97 MC nCLK 0.01fF
+C98 sky130_fd_sc_hs__mux2_1_0/a_524_368# nCLK_23 0.04fF
+C99 DFlipFlop_1/latch_diff_0/nD CLK 0.09fF
+C100 DFlipFlop_2/latch_diff_1/D Q2_d 0.03fF
+C101 sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C102 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C103 sky130_fd_sc_hs__or2_1_0/X vss 0.92fF
+C104 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.39fF
+C105 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.72fF
+C106 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C107 DFlipFlop_1/latch_diff_1/D vss -1.72fF
+C108 DFlipFlop_1/latch_diff_1/nD vss 0.58fF
+C109 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C110 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C111 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C112 DFlipFlop_1/D vss 2.98fF
+C113 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C114 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C115 Q2_d vss -0.22fF
+C116 DFlipFlop_2/nQ vss 0.48fF
+C117 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C118 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C119 DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C120 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C121 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C122 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C123 Q2 vss 1.35fF
+C124 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C125 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C126 nCLK vss -1.56fF
+C127 Q1 vss 0.50fF
+C128 DFlipFlop_0/nQ vss 0.48fF
+C129 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C130 CLK vss -0.69fF
+C131 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C132 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C133 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C134 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C135 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C136 nCLK_23 vss -0.65fF
+C137 vdd vss 115.65fF
+C138 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C139 CLK_23 vss -0.57fF
+C140 sky130_fd_sc_hs__or2_1_1/X vss -0.35fF
+C141 MC vss 2.09fF
+C142 sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.41fF
+C143 sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.69fF
+.ends
+
+.subckt freq_div_pex_c s_1_n s_0_n s_0 s_1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 out in_a
++ clk_5 clk_2 in_b clk_1 n_clk_1
+Xdiv_by_2_0 clk_2 vss vdd div_by_2_0/o1 clk_out_mux21 div_by_2
+Xmux2to1_0 vss s_0_n clk_pre clk_5 s_0 vdd clk_out_mux21 mux2to1
+Xinverter_min_x4_0 inverter_min_x4_0/in clk_d vss vdd inverter_min_x4
+Xmux2to1_1 vss s_1_n clk_d clk_2 s_1 vdd out mux2to1
+Xinverter_min_x2_0 clk_out_mux21 inverter_min_x4_0/in vss vdd inverter_min_x2
+Xinverter_min_x2_1 s_1 s_1_n vss vdd inverter_min_x2
+Xinverter_min_x2_2 s_0 s_0_n vss vdd inverter_min_x2
+Xdiv_by_5_0 n_clk_1 div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_0/latch_diff_1/nD
++ vss div_by_5_0/Q1 clk_1 div_by_5_0/DFlipFlop_0/Q vdd div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_3/latch_diff_0/D div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD
++ clk_5 div_by_5_0/Q1_shift div_by_5_0/nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/DFlipFlop_2/D
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
++ div_by_5_0/nQ0 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/Q0
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_by_5
+Xmux2to4_0 vss n_clk_1 n_clk_0 s_0 clk_0 s_0_n clk_1 vdd in_a in_b mux2to4
+Xprescaler_23_0 n_clk_0 vss prescaler_23_0/DFlipFlop_0/latch_diff_1/nD prescaler_23_0/nCLK_23
++ vdd prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_pre prescaler_23_0/DFlipFlop_0/latch_diff_0/D
++ clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/D prescaler_23_0/DFlipFlop_0/latch_diff_0/nD
++ prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in prescaler_23
+C0 s_0 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.36fF
+C1 s_0_n div_by_5_0/Q0 0.24fF
+C2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0 0.02fF
+C3 s_0_n div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.31fF
+C4 s_0 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.10fF
+C5 s_1_n out 0.33fF
+C6 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.02fF
+C7 s_0 in_a 0.30fF
+C8 s_0_n div_by_5_0/nQ0 0.05fF
+C9 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD 0.09fF
+C10 s_0_n n_clk_0 0.31fF
+C11 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_clk_0 0.14fF
+C12 vdd clk_d 0.23fF
+C13 s_1 clk_d 0.22fF
+C14 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_clk_1 0.11fF
+C15 s_0 div_by_5_0/Q1_shift 0.05fF
+C16 s_0_n div_by_5_0/Q1 0.21fF
+C17 s_0_n div_by_5_0/DFlipFlop_1/D 0.19fF
+C18 s_0_n div_by_5_0/DFlipFlop_0/Q 0.24fF
+C19 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/D 0.13fF
+C20 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C21 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out s_0 -0.13fF
+C22 n_clk_1 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.06fF
+C23 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_clk_1 0.14fF
+C24 s_0_n div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C25 s_0_n div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.37fF
+C26 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.17fF
+C27 clk_0 prescaler_23_0/nCLK_23 0.16fF
+C28 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.24fF
+C29 s_1_n s_1 0.39fF
+C30 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.08fF
+C31 vdd clk_1 0.17fF
+C32 s_0 clk_1 1.36fF
+C33 div_by_5_0/DFlipFlop_2/nQ s_0 0.05fF
+C34 div_by_5_0/DFlipFlop_0/latch_diff_1/D clk_1 0.11fF
+C35 s_0_n div_by_5_0/Q1_shift 0.04fF
+C36 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD 0.09fF
+C37 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0 0.05fF
+C38 s_0 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.05fF
+C39 s_0_n div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out -0.01fF
+C40 div_by_5_0/DFlipFlop_2/latch_diff_0/nD s_0 0.12fF
+C41 s_1 out 0.39fF
+C42 clk_d inverter_min_x4_0/in 0.11fF
+C43 vdd clk_5 0.05fF
+C44 div_by_5_0/DFlipFlop_0/D clk_1 0.14fF
+C45 s_0_n clk_1 4.82fF
+C46 clk_5 clk_out_mux21 0.05fF
+C47 vdd clk_0 0.63fF
+C48 s_0_n div_by_5_0/DFlipFlop_2/nQ 0.04fF
+C49 s_1_n clk_2 0.59fF
+C50 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/D 0.09fF
+C51 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out s_0 -0.19fF
+C52 s_0_n div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.04fF
+C53 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.04fF
+C54 s_0_n div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.20fF
+C55 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# div_by_5_0/Q1_shift -0.02fF
+C56 s_0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.02fF
+C57 s_0 div_by_5_0/DFlipFlop_3/nQ 0.02fF
+C58 div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in -0.03fF
+C59 s_0 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.12fF
+C60 vdd s_0 3.90fF
+C61 s_0 clk_out_mux21 0.68fF
+C62 vdd clk_out_mux21 0.14fF
+C63 div_by_5_0/DFlipFlop_0/latch_diff_1/D s_0 0.05fF
+C64 s_0 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.05fF
+C65 s_0_n clk_5 0.56fF
+C66 clk_2 out 0.05fF
+C67 vdd n_clk_1 0.14fF
+C68 clk_1 n_clk_0 -0.03fF
+C69 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_clk_1 0.08fF
+C70 s_0_n div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.29fF
+C71 s_0_n div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.05fF
+C72 div_by_5_0/DFlipFlop_2/D s_0 0.03fF
+C73 n_clk_0 prescaler_23_0/nCLK_23 0.16fF
+C74 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C75 s_0_n div_by_5_0/DFlipFlop_3/nQ 0.24fF
+C76 div_by_5_0/nQ2 s_0 0.05fF
+C77 div_by_5_0/DFlipFlop_0/D s_0 0.03fF
+C78 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.20fF
+C79 s_0_n vdd 2.68fF
+C80 s_0_n s_0 7.76fF
+C81 s_0_n clk_out_mux21 0.45fF
+C82 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.04fF
+C83 div_by_5_0/DFlipFlop_0/latch_diff_1/nD clk_1 0.08fF
+C84 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.04fF
+C85 clk_pre prescaler_23_0/nCLK_23 0.03fF
+C86 clk_1 in_a 0.05fF
+C87 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD 0.13fF
+C88 div_by_5_0/DFlipFlop_0/D n_clk_1 0.21fF
+C89 in_b n_clk_1 0.05fF
+C90 vdd clk_2 0.05fF
+C91 s_0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.12fF
+C92 n_clk_1 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C93 s_0_n div_by_5_0/DFlipFlop_2/D 0.05fF
+C94 clk_0 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C95 s_0 div_by_5_0/Q0 0.02fF
+C96 vdd div_by_5_0/Q0 0.05fF
+C97 s_0 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.30fF
+C98 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_1 0.05fF
+C99 vdd inverter_min_x4_0/in 0.09fF
+C100 s_0_n div_by_5_0/nQ2 0.05fF
+C101 s_0_n div_by_5_0/DFlipFlop_0/D 0.05fF
+C102 s_0_n in_b 0.48fF
+C103 s_0 div_by_5_0/nQ0 0.05fF
+C104 div_by_5_0/Q0 n_clk_1 0.01fF
+C105 vdd n_clk_0 0.25fF
+C106 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_clk_1 0.11fF
+C107 vdd div_by_5_0/Q1 0.04fF
+C108 s_0 div_by_5_0/Q1 0.04fF
+C109 s_0 div_by_5_0/DFlipFlop_1/D 0.03fF
+C110 clk_5 div_by_5_0/Q1_shift 0.04fF
+C111 s_0 clk_pre 0.21fF
+C112 vdd clk_pre 0.17fF
+C113 s_0 div_by_5_0/DFlipFlop_0/Q 0.02fF
+C114 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/D 0.13fF
+C115 clk_pre clk_out_mux21 1.19fF
+C116 div_by_5_0/DFlipFlop_3/latch_diff_1/D s_0 0.02fF
+C117 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.20fF
+C118 div_by_5_0/Q1 n_clk_1 0.15fF
+C119 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C120 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C121 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C122 prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C123 prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C124 prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C125 prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C126 prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C127 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C128 prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C129 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C130 prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C131 prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C132 prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C133 prescaler_23_0/Q2_d vss -0.69fF
+C134 prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C135 prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C136 prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C137 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C138 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C139 prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C140 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C141 prescaler_23_0/Q2 vss 0.55fF
+C142 prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C143 prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C144 n_clk_0 vss -5.72fF
+C145 prescaler_23_0/Q1 vss 0.07fF
+C146 prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C147 prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C148 clk_0 vss 0.67fF
+C149 prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C150 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C151 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C152 prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C153 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C154 prescaler_23_0/nCLK_23 vss -1.02fF
+C155 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C156 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C157 prescaler_23_0/MC vss 1.07fF
+C158 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C159 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C160 in_b vss 2.26fF
+C161 in_a vss 2.25fF
+C162 s_0_n vss -2.50fF
+C163 s_0 vss 5.84fF
+C164 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C165 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C166 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C167 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C168 div_by_5_0/Q1_shift vss -0.36fF
+C169 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C170 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C172 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C173 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C174 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C176 div_by_5_0/Q1 vss 4.35fF
+C177 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C178 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C179 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C180 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C181 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C182 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C183 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C184 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C185 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C186 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C187 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C188 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C189 div_by_5_0/Q0 vss 0.29fF
+C190 div_by_5_0/nQ0 vss 0.99fF
+C191 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C192 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C193 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C194 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C195 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C196 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C197 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C198 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C199 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C200 n_clk_1 vss -0.46fF
+C201 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C202 div_by_5_0/nQ2 vss 1.38fF
+C203 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C204 clk_1 vss -1.26fF
+C205 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C206 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C207 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C208 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C209 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C210 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C211 vdd vss 354.24fF
+C212 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C213 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C214 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C215 out vss 1.17fF
+C216 clk_d vss 0.79fF
+C217 s_1_n vss 1.22fF
+C218 s_1 vss 2.97fF
+C219 inverter_min_x4_0/in vss 2.77fF
+C220 clk_5 vss 1.61fF
+C221 clk_out_mux21 vss 6.10fF
+C222 clk_pre vss 1.31fF
+C223 clk_2 vss 3.54fF
+C224 div_by_2_0/o1 vss 2.20fF
+C225 div_by_2_0/nCLK_2 vss 1.04fF
+C226 div_by_2_0/o2 vss 2.08fF
+C227 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C228 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C229 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C230 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C231 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C232 div_by_2_0/out_div vss -0.80fF
+C233 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C234 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C235 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C236 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C237 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C238 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C239 div_by_2_0/nout_div vss 2.62fF
+C240 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+.ends
+
diff --git a/xschem/simulations/loop_filter_v2_pex_c.spice b/xschem/simulations/loop_filter_v2_pex_c.spice
new file mode 100644
index 0000000..32b0869
--- /dev/null
+++ b/xschem/simulations/loop_filter_v2_pex_c.spice
@@ -0,0 +1,249 @@
+* NGSPICE file created from loop_filter_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_2669_n2600# m3_2669_2700# 3.28fF
+C1 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C2 m3_2669_n13200# m3_n2650_n13200# 2.73fF
+C3 m3_2669_2700# m3_7988_2700# 2.73fF
+C4 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C5 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C6 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C7 m3_2669_2700# m3_n2650_2700# 2.73fF
+C8 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C9 m3_7988_n2600# m3_7988_n7900# 3.39fF
+C10 m3_2669_n2600# c1_n13188_n13100# 58.86fF
+C11 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C12 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C13 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C14 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C15 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C16 m3_n7969_2700# c1_n13188_n13100# 58.86fF
+C17 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C18 m3_7988_8000# m3_7988_2700# 3.39fF
+C19 m3_n2650_8000# m3_2669_8000# 2.73fF
+C20 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
+C21 m3_2669_2700# m3_2669_8000# 3.28fF
+C22 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C23 m3_7988_n13200# m3_7988_n7900# 3.39fF
+C24 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C25 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C26 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C27 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C28 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C29 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C30 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C31 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C32 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C33 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C34 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C35 m3_7988_8000# m3_2669_8000# 2.73fF
+C36 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C37 m3_n13288_2700# c1_n13188_n13100# 58.61fF
+C38 m3_2669_n2600# m3_n2650_n2600# 2.73fF
+C39 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C40 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C41 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C42 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C43 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C44 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C45 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C46 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C47 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C48 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C49 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C50 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C51 m3_n7969_2700# m3_n7969_8000# 3.28fF
+C52 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C53 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C54 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C55 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C56 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C57 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C58 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C59 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C60 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C61 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C62 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C63 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C64 m3_7988_n2600# m3_7988_2700# 3.39fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C1 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C2 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C3 c1_110_n4150# m3_10_n4250# 81.11fF
+C4 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
+C5 m3_n4309_50# m3_10_n4250# 1.75fF
+C6 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 out in 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C1 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C2 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
+C3 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C4 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C5 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C6 m3_n2150_2200# m3_n2150_n2100# 2.63fF
+C7 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C8 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C9 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C10 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C11 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C12 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C13 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C14 m3_n2150_2200# m3_n6469_2200# 1.75fF
+C15 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C16 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C17 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C18 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_n88_n300# a_30_n300# 0.61fF
+C1 a_n88_n300# a_n118_n388# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2_pex_c vss in vc_pex D0_cap
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in D0_cap 0.07fF
+C1 in vc_pex 0.18fF
+C2 in cap3_loop_filter_0/in 0.79fF
+C3 vc_pex vss -2.18fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -35.63fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
diff --git a/xschem/simulations/mux2to1.spice b/xschem/simulations/mux2to1.spice
new file mode 100644
index 0000000..d7cd0c7
--- /dev/null
+++ b/xschem/simulations/mux2to1.spice
@@ -0,0 +1,32 @@
+**.subckt mux2to1 in_a selec_0_neg selec_0 out_a_0 out_a_1 vdd vss
+*.iopin in_a
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+**.ends
+
+* expanding symbol: trans_gate_mux2to8/sch/trans_gate_mux2to8.sym # of pins=6
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate_mux2to8/sch/trans_gate_mux2to8.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate_mux2to8/sch/trans_gate_mux2to8.sch
+.subckt trans_gate_mux2to8 en_pos out in en_neg vss vdd
+*.iopin en_neg
+*.ipin in
+*.opin out
+*.iopin en_pos
+*.iopin vdd
+*.iopin vss
+XM2 out en_neg in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out en_pos in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/mux2to4.spice b/xschem/simulations/mux2to4.spice
new file mode 100644
index 0000000..1421501
--- /dev/null
+++ b/xschem/simulations/mux2to4.spice
@@ -0,0 +1,37 @@
+**.subckt mux2to4 in_a in_b selec_0_neg selec_0 out_b_0 out_b_1 out_a_0 out_a_1 vdd vss
+*.iopin in_a
+*.iopin in_b
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_b_0
+*.iopin out_b_1
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+x8 selec_0 out_b_1 in_b selec_0_neg vss vdd trans_gate_mux2to8
+x9 selec_0_neg out_b_0 in_b selec_0 vss vdd trans_gate_mux2to8
+**.ends
+
+* expanding symbol: trans_gate_mux2to8.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate_mux2to8.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate_mux2to8.sch
+.subckt trans_gate_mux2to8 en_pos out in en_neg vss vdd
+*.iopin en_neg
+*.ipin in
+*.opin out
+*.iopin en_pos
+*.iopin vdd
+*.iopin vss
+XM2 out en_neg in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out en_pos in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/prescaler_23.spice b/xschem/simulations/prescaler_23.spice
new file mode 100644
index 0000000..f3a00af
--- /dev/null
+++ b/xschem/simulations/prescaler_23.spice
@@ -0,0 +1,117 @@
+**.subckt prescaler_23 vdd CLK nCLK MC vss CLK_23 nCLK_23 Q1 Q2 Q2_d
+*.iopin vdd
+*.ipin CLK
+*.ipin nCLK
+*.ipin MC
+*.iopin vss
+*.opin CLK_23
+*.iopin nCLK_23
+*.iopin Q1
+*.iopin Q2
+*.iopin Q2_d
+x3 nCLK_23 1 vss vss vdd vdd 2 sky130_fd_sc_hs__and2_1
+x4 Q1 MC vss vss vdd vdd 1 sky130_fd_sc_hs__or2_1
+x6 3 nCLK_23 MC vss vss vdd vdd CLK_23 sky130_fd_sc_hs__mux2_1
+x7 Q2 Q2_d vss vss vdd vdd 3 sky130_fd_sc_hs__or2_1
+x1 vdd Q1 net1 vss nCLK_23 CLK nCLK DFlipFlop
+x2 vdd Q2 nCLK_23 vss 2 CLK nCLK DFlipFlop
+x5 vdd Q2_d net2 vss Q2 nCLK CLK DFlipFlop
+**.ends
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/prescaler_23_pex_c.spice b/xschem/simulations/prescaler_23_pex_c.spice
new file mode 100644
index 0000000..99ec933
--- /dev/null
+++ b/xschem/simulations/prescaler_23_pex_c.spice
@@ -0,0 +1,544 @@
+* NGSPICE file created from prescaler_23.ext - technology: sky130A
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X a_304_74# a_443_74# a_524_368#
++ a_27_112#
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 A1 a_304_74# 0.69fF
+C1 a_27_112# VGND 0.18fF
+C2 a_226_74# a_304_74# 0.08fF
+C3 a_27_112# a_304_74# 0.58fF
+C4 S VPWR 0.05fF
+C5 a_524_368# a_27_112# 0.06fF
+C6 VGND A0 0.02fF
+C7 A1 a_27_112# 0.18fF
+C8 a_304_74# A0 0.23fF
+C9 X VPWR 0.28fF
+C10 VGND VPWR 0.02fF
+C11 A1 A0 0.31fF
+C12 a_304_74# VPWR 0.13fF
+C13 a_304_74# a_223_368# 0.05fF
+C14 a_27_112# A0 0.07fF
+C15 A1 VPWR 0.01fF
+C16 VGND S 0.07fF
+C17 a_27_112# VPWR 0.99fF
+C18 a_304_74# S 0.18fF
+C19 a_27_112# a_223_368# 0.09fF
+C20 a_27_112# VPB 0.01fF
+C21 X VGND 0.11fF
+C22 A1 S 0.10fF
+C23 a_304_74# a_443_74# 0.12fF
+C24 X a_304_74# 0.29fF
+C25 a_27_112# S 0.22fF
+C26 a_304_74# VGND 0.58fF
+C27 A1 a_443_74# 0.07fF
+C28 A1 X 0.02fF
+C29 X a_27_112# 0.08fF
+C30 A0 S 0.04fF
+C31 A1 VGND 0.09fF
+C32 VPB VPWR 0.06fF
+C33 VGND VNB 0.88fF
+C34 X VNB 0.25fF
+C35 VPWR VNB 0.89fF
+C36 A1 VNB 0.37fF
+C37 A0 VNB 0.23fF
+C38 S VNB 0.34fF
+C39 VPB VNB 0.87fF
+C40 a_304_74# VNB 0.36fF
+C41 a_27_112# VNB 0.65fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n81_n125# 0.13fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_n81_n125# a_15_n125# 0.36fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n15_n156# a_n111_n156# 0.02fF
+C5 a_n173_n125# w_n311_n344# 0.14fF
+C6 a_n15_n156# a_81_n156# 0.02fF
+C7 a_n81_n125# w_n311_n344# 0.09fF
+C8 a_n173_n125# a_n81_n125# 0.36fF
+C9 a_111_n125# w_n311_n344# 0.14fF
+C10 a_15_n125# w_n311_n344# 0.09fF
+C11 a_n173_n125# a_111_n125# 0.08fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n111_n151# a_n15_n151# 0.02fF
+C1 a_n173_n125# a_n81_n125# 0.36fF
+C2 a_n15_n151# a_81_n151# 0.02fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_n173_n125# a_111_n125# 0.08fF
+C6 a_n81_n125# a_15_n125# 0.36fF
+C7 a_n81_n125# a_111_n125# 0.13fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_187_n605# m1_45_n513# 0.36fF
+C1 m1_187_n605# vdd 0.55fF
+C2 vdd m1_45_n513# 0.69fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n311_n344# a_111_n125# 0.14fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 a_n173_n125# a_111_n125# 0.08fF
+C3 w_n311_n344# a_n81_n125# 0.09fF
+C4 a_15_n125# a_n81_n125# 0.36fF
+C5 a_n173_n125# a_n81_n125# 0.36fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_15_n125# w_n311_n344# 0.09fF
+C8 a_n173_n125# w_n311_n344# 0.14fF
+C9 a_n173_n125# a_15_n125# 0.13fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n81_n125# a_n173_n125# 0.36fF
+C2 a_111_n125# a_15_n125# 0.36fF
+C3 a_n81_n125# a_15_n125# 0.36fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_n81_n125# a_111_n125# 0.13fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 in out 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
+Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
+C0 vdd inverter_cp_x1_0/out 0.28fF
+C1 vdd CLK_d 0.03fF
+C2 inverter_cp_x1_2/in vdd 0.21fF
+C3 inverter_cp_x1_2/in CLK_d 0.12fF
+C4 vdd CLK 0.36fF
+C5 inverter_cp_x1_0/out CLK 0.31fF
+C6 inverter_cp_x1_2/in CLK 0.31fF
+C7 vdd nCLK_d 0.03fF
+C8 nCLK_d inverter_cp_x1_0/out 0.11fF
+C9 inverter_cp_x1_2/in vss 2.01fF
+C10 CLK_d vss 0.96fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 vdd vss 16.51fF
+C14 nCLK_d vss 1.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_63_n95# 0.28fF
+C1 a_n125_n95# w_n263_n314# 0.11fF
+C2 a_n125_n95# a_63_n95# 0.10fF
+C3 a_n125_n95# a_n33_n95# 0.28fF
+C4 w_n263_n314# a_63_n95# 0.11fF
+C5 a_n33_n95# w_n263_n314# 0.08fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n129_n213# 0.02fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 a_n173_n125# a_111_n125# 0.08fF
+C3 a_n173_n125# a_15_n125# 0.13fF
+C4 a_n81_n125# a_n129_n213# 0.10fF
+C5 a_n81_n125# a_111_n125# 0.13fF
+C6 a_n81_n125# a_15_n125# 0.36fF
+C7 a_n81_n125# a_n173_n125# 0.36fF
+C8 a_n129_n213# a_111_n125# 0.01fF
+C9 a_15_n125# a_n129_n213# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n81_n183# 0.16fF
+C1 a_n33_n95# a_n81_n183# 0.10fF
+C2 a_n33_n95# a_n125_n95# 0.88fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 Q D 0.05fF
+C1 m1_657_280# nQ 1.41fF
+C2 Q nD 0.05fF
+C3 Q vdd 0.16fF
+C4 CLK m1_657_280# 0.24fF
+C5 Q nQ 0.93fF
+C6 nQ D 0.05fF
+C7 Q m1_657_280# 0.94fF
+C8 nD nQ 0.05fF
+C9 vdd nQ 0.16fF
+C10 D vss 0.53fF
+C11 nD vss 0.16fF
+C12 m1_657_280# vss 1.88fF
+C13 CLK vss 0.87fF
+C14 Q vss -0.55fF
+C15 vdd vss 5.98fF
+C16 nQ vss 1.16fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vdd vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ latch_diff_0/nD Q latch_diff_1/nD latch_diff_1/m1_657_280# D clock_inverter_0/inverter_cp_x1_0/out
++ CLK latch_diff_0/D nCLK
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_1/D nQ 0.11fF
+C1 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C2 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C3 latch_diff_1/nD latch_diff_0/D 0.04fF
+C4 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C5 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C6 Q latch_diff_1/nD 0.01fF
+C7 vdd latch_diff_0/D 0.09fF
+C8 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C9 vdd latch_diff_1/nD 0.02fF
+C10 latch_diff_1/D latch_diff_0/D 0.11fF
+C11 nQ latch_diff_1/nD 0.08fF
+C12 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C13 latch_diff_1/D latch_diff_1/nD 0.33fF
+C14 latch_diff_0/nD vdd 0.14fF
+C15 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C16 latch_diff_0/nD latch_diff_1/D 0.41fF
+C17 latch_diff_1/D vdd 0.03fF
+C18 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C19 latch_diff_1/m1_657_280# vss 0.64fF
+C20 nCLK vss 0.83fF
+C21 Q vss -0.92fF
+C22 nQ vss 0.57fF
+C23 latch_diff_0/m1_657_280# vss 0.72fF
+C24 CLK vss 0.83fF
+C25 latch_diff_1/D vss -0.30fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C28 latch_diff_0/D vss 1.29fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 vdd vss 32.62fF
+C32 latch_diff_0/nD vss 1.74fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 X B 0.02fF
+C1 A a_56_136# 0.17fF
+C2 VPWR VPB 0.04fF
+C3 a_56_136# X 0.26fF
+C4 VPWR B 0.02fF
+C5 VGND B 0.03fF
+C6 A VPWR 0.07fF
+C7 A VGND 0.21fF
+C8 A B 0.08fF
+C9 VPWR a_56_136# 0.57fF
+C10 a_56_136# VGND 0.06fF
+C11 VPWR X 0.20fF
+C12 VGND X 0.15fF
+C13 a_56_136# B 0.30fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 B VPWR 0.01fF
+C1 A X 0.02fF
+C2 VGND a_63_368# 0.27fF
+C3 A B 0.10fF
+C4 VGND X 0.16fF
+C5 A VPWR 0.05fF
+C6 VGND B 0.11fF
+C7 a_63_368# X 0.33fF
+C8 B a_63_368# 0.14fF
+C9 a_63_368# VPWR 0.29fF
+C10 VPB VPWR 0.04fF
+C11 A a_63_368# 0.28fF
+C12 X VPWR 0.18fF
+C13 a_152_368# a_63_368# 0.03fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt prescaler_23_pex_c vdd CLK_23 CLK nCLK vss MC Q1 nCLK_23 Q2 Q2_d
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1_0/a_304_74# sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__mux2_1_0/a_524_368#
++ sky130_fd_sc_hs__mux2_1_0/a_27_112# sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ DFlipFlop_0/latch_diff_0/nD
++ Q1 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# nCLK_23 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_0/latch_diff_0/D nCLK DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK_23 DFlipFlop_1/latch_diff_0/nD
++ Q2 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ Q2_d DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# Q2 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/D CLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1_0/a_143_136# sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1_1/a_152_368#
++ sky130_fd_sc_hs__or2_1_1/a_63_368# sky130_fd_sc_hs__or2_1
+C0 DFlipFlop_0/nQ nCLK 0.11fF
+C1 DFlipFlop_1/latch_diff_1/D CLK 0.18fF
+C2 DFlipFlop_0/latch_diff_1/m1_657_280# Q1 0.06fF
+C3 sky130_fd_sc_hs__or2_1_1/a_63_368# Q2 0.09fF
+C4 Q2 vdd 1.63fF
+C5 sky130_fd_sc_hs__mux2_1_0/a_304_74# sky130_fd_sc_hs__or2_1_1/X 0.08fF
+C6 DFlipFlop_2/latch_diff_1/nD CLK 0.19fF
+C7 sky130_fd_sc_hs__or2_1_0/X CLK 0.01fF
+C8 nCLK_23 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.49fF
+C9 DFlipFlop_2/latch_diff_0/D Q2 0.30fF
+C10 sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__and2_1_0/a_56_136# 0.07fF
+C11 sky130_fd_sc_hs__and2_1_0/a_143_136# nCLK_23 0.02fF
+C12 Q2_d vdd 0.02fF
+C13 Q2 Q2_d 0.66fF
+C14 nCLK DFlipFlop_1/D 0.16fF
+C15 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C16 DFlipFlop_2/latch_diff_1/nD Q2 0.17fF
+C17 sky130_fd_sc_hs__or2_1_1/X nCLK_23 0.26fF
+C18 sky130_fd_sc_hs__or2_1_0/X vdd 0.03fF
+C19 sky130_fd_sc_hs__mux2_1_0/a_27_112# nCLK_23 0.07fF
+C20 nCLK_23 Q1 0.02fF
+C21 DFlipFlop_2/nQ CLK 0.02fF
+C22 DFlipFlop_0/nQ nCLK_23 0.05fF
+C23 DFlipFlop_2/latch_diff_0/m1_657_280# nCLK 0.31fF
+C24 DFlipFlop_2/latch_diff_0/nD nCLK 0.09fF
+C25 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C26 DFlipFlop_2/nQ Q2 0.13fF
+C27 nCLK nCLK_23 0.11fF
+C28 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.29fF
+C29 MC CLK 0.08fF
+C30 nCLK_23 DFlipFlop_1/D 0.02fF
+C31 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.06fF
+C32 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_443_74# 0.03fF
+C33 DFlipFlop_2/latch_diff_1/D CLK 0.09fF
+C34 sky130_fd_sc_hs__mux2_1_0/a_304_74# nCLK_23 0.04fF
+C35 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.02fF
+C36 MC vdd 0.88fF
+C37 Q2 MC 0.18fF
+C38 DFlipFlop_2/latch_diff_1/D Q2 0.13fF
+C39 CLK_23 vdd 0.16fF
+C40 DFlipFlop_0/latch_diff_1/D nCLK_23 0.05fF
+C41 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in CLK -0.10fF
+C42 DFlipFlop_2/latch_diff_1/D Q2_d 0.03fF
+C43 sky130_fd_sc_hs__or2_1_0/X MC 0.09fF
+C44 Q1 CLK -0.07fF
+C45 DFlipFlop_0/nQ CLK 0.15fF
+C46 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C47 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q2 0.38fF
+C48 sky130_fd_sc_hs__or2_1_1/X vdd 0.03fF
+C49 sky130_fd_sc_hs__or2_1_1/X Q2 0.24fF
+C50 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.09fF
+C51 Q1 vdd 0.07fF
+C52 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_443_74# 0.09fF
+C53 DFlipFlop_1/latch_diff_1/nD nCLK 0.18fF
+C54 DFlipFlop_1/D CLK 0.40fF
+C55 sky130_fd_sc_hs__or2_1_1/X Q2_d 0.03fF
+C56 nCLK sky130_fd_sc_hs__or2_1_0/a_63_368# 0.05fF
+C57 nCLK vdd -0.55fF
+C58 nCLK Q2 0.29fF
+C59 sky130_fd_sc_hs__or2_1_0/X Q1 0.06fF
+C60 vdd DFlipFlop_1/D 0.07fF
+C61 nCLK DFlipFlop_1/latch_diff_1/D 0.09fF
+C62 nCLK_23 CLK 0.22fF
+C63 nCLK_23 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C64 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_524_368# 0.04fF
+C65 DFlipFlop_2/latch_diff_1/nD nCLK 0.12fF
+C66 DFlipFlop_0/latch_diff_1/D CLK 0.04fF
+C67 sky130_fd_sc_hs__or2_1_0/X nCLK 0.06fF
+C68 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1 0.01fF
+C69 DFlipFlop_1/latch_diff_0/nD CLK 0.09fF
+C70 DFlipFlop_2/latch_diff_1/m1_657_280# CLK 0.33fF
+C71 sky130_fd_sc_hs__or2_1_0/X DFlipFlop_1/D 0.35fF
+C72 nCLK_23 vdd 3.35fF
+C73 nCLK_23 Q2 0.03fF
+C74 DFlipFlop_1/latch_diff_0/D nCLK 0.02fF
+C75 DFlipFlop_0/latch_diff_1/nD Q1 0.03fF
+C76 nCLK_23 DFlipFlop_0/latch_diff_0/nD 0.12fF
+C77 sky130_fd_sc_hs__or2_1_0/a_152_368# nCLK 0.01fF
+C78 nCLK DFlipFlop_2/nQ 0.02fF
+C79 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C80 sky130_fd_sc_hs__or2_1_1/X MC 0.02fF
+C81 sky130_fd_sc_hs__mux2_1_0/a_27_112# MC 0.24fF
+C82 Q1 MC 0.29fF
+C83 sky130_fd_sc_hs__or2_1_0/X nCLK_23 0.07fF
+C84 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C85 DFlipFlop_2/latch_diff_1/m1_657_280# Q2_d 0.03fF
+C86 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.31fF
+C87 nCLK MC 0.01fF
+C88 DFlipFlop_2/latch_diff_1/D nCLK 0.16fF
+C89 DFlipFlop_1/latch_diff_1/nD CLK 0.11fF
+C90 sky130_fd_sc_hs__and2_1_0/a_56_136# CLK 0.08fF
+C91 DFlipFlop_0/latch_diff_1/nD nCLK_23 0.02fF
+C92 DFlipFlop_0/nQ Q1 -0.02fF
+C93 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.16fF
+C94 sky130_fd_sc_hs__mux2_1_0/a_304_74# CLK_23 0.05fF
+C95 nCLK_23 MC 4.46fF
+C96 vdd CLK 0.34fF
+C97 Q2 CLK 0.29fF
+C98 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.31fF
+C99 DFlipFlop_2/latch_diff_0/D CLK 0.13fF
+C100 nCLK Q1 -0.02fF
+C101 sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C102 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C103 sky130_fd_sc_hs__or2_1_0/X vss 0.92fF
+C104 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.39fF
+C105 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C106 Q2_d vss 0.57fF
+C107 DFlipFlop_2/nQ vss 0.48fF
+C108 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C109 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C110 DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C111 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C112 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C113 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C114 Q2 vss 1.35fF
+C115 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C116 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.72fF
+C117 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C118 DFlipFlop_1/latch_diff_1/D vss -1.72fF
+C119 DFlipFlop_1/latch_diff_1/nD vss 0.58fF
+C120 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C121 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C122 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C123 DFlipFlop_1/D vss 2.98fF
+C124 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C125 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C126 nCLK vss -1.49fF
+C127 Q1 vss -0.09fF
+C128 DFlipFlop_0/nQ vss 0.48fF
+C129 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C130 CLK vss -0.61fF
+C131 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C132 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C133 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C134 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C135 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C136 nCLK_23 vss 5.43fF
+C137 vdd vss 115.92fF
+C138 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C139 CLK_23 vss 0.05fF
+C140 sky130_fd_sc_hs__or2_1_1/X vss -0.35fF
+C141 MC vss 2.59fF
+C142 sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.41fF
+C143 sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.69fF
+.ends
+
diff --git a/xschem/simulations/tb_freq_div.spice b/xschem/simulations/tb_freq_div.spice
new file mode 100644
index 0000000..74d76ee
--- /dev/null
+++ b/xschem/simulations/tb_freq_div.spice
@@ -0,0 +1,478 @@
+**.subckt tb_freq_div
+x1 s1n s0n S0 S1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 f_div clk_2 clk_5 clk_2_f
++ nclk_2 clk_1 n_clk_1 freq_div
+x2 nclk_2 vss CLK vdd clk_2 net1 net2 net3 net4 div_by_2
+x3 vss vdd net7 net6 f_div net8 net5 PFD
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref net9 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+VMC S1 vss PULSE(0 {vin} 0 1p 1p 400n 800n) DC {vin} AC 0
+x4 vdd net10 net9 vss inverter_min_x2_pex_c
+x5 vdd CLK net10 vss inverter_min_x4_pex_c
+VMC1 S0 vss PULSE(0 {vin} 0 1p 1p 200n 400n) DC {vin} AC 0
+VMC2 MC vss PULSE(0 {vin} 0 1p 1p 100n 200n) DC {vin} AC 0
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+.options GMIN = 1e-10
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+
+* Data to save
+.save all
+.ic v(CLK) = 0.0
+.ic v(MC) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(f_div) = 0.0
+.ic v(S0) = 0.0
+.ic v(S1) = 0.0
+.ic v(clk_0) = 0.0
+.ic v(n_clk_0) = 0.0
+.ic v(clk_1) = 0.0
+.ic v(n_clk_1) = 0.0
+.ic v(clk_pre) = 0.0
+.ic v(clk_5) = 0.0
+.ic v(clk_d) = 0.0
+.ic v(clk_2_f) = 0.0
+.ic v(s1n) = 0.0
+.ic v(s0n) = 0.0
+.ic v(x1.x4.q2) = 0.0
+.ic v(x1.x4.q1) = 0.0
+.ic v(x1.x4.q1_shift) = 0.0
+.ic v(x1.x4.q0) = 0.0
+.ic v(x1.x4.x1.a) = 0.0
+.ic v(x1.x4.x1.D_d) = 0.0
+.ic v(x1.x4.x1.nD_d) = 0.0
+
+* Simulation
+.control
+ save v(CLK) v(clk_2) v(S1) v(S0) v(MC) v(clk_0) v(clk_1) v(clk_pre) v(clk_5) v(clk_d) v(clk_2_f)
++ v(f_div)
+ tran 0.01ns 800ns
+ write tb_freq_div_tran.raw
+ plot v(CLK) v(clk_2)+2 v(S1)+4 v(S0)+6 v(MC)+8 v(clk_0)+10 v(clk_1)+12 v(clk_pre)+14 v(clk_5)+16
++ v(clk_d)+18 v(clk_2_f)+20 v(f_div)+22
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: freq_div.sym # of pins=19
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/freq_div.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/freq_div.sch
+.subckt freq_div s_1_n s_0_n s_0 s_1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 out in_a
++ clk_5 clk_2 in_b clk_1 n_clk_1
+*.ipin s_0
+*.iopin vdd
+*.iopin vss
+*.ipin in_a
+*.ipin in_b
+*.opin out
+*.ipin MC
+*.ipin s_1
+*.iopin clk_0
+*.iopin n_clk_0
+*.iopin clk_1
+*.iopin n_clk_1
+*.iopin clk_pre
+*.iopin clk_5
+*.iopin clk_out_mux21
+*.iopin clk_d
+*.iopin clk_2
+*.iopin s_0_n
+*.iopin s_1_n
+x2 vdd clk_pre clk_0 n_clk_0 vss MC net2 net1 net3 net4 prescaler_23
+x3 net14 vss clk_out_mux21 vdd clk_2 net5 net6 net7 net8 div_by_2
+x4 vdd clk_5 clk_1 vss n_clk_1 net9 net10 net12 net13 net11 div_by_5
+x9 vdd s_0_n s_0 vss inverter_min_x2
+x1 vdd vss in_a in_b n_clk_0 clk_0 s_0 n_clk_1 clk_1 s_0_n mux2to4
+x6 vdd vss clk_out_mux21 clk_pre s_0 clk_5 s_0_n mux2to1
+x5 vdd vss out clk_d s_1 clk_2 s_1_n mux2to1
+x7 vdd s_1_n s_1 vss inverter_min_x2
+x8 vdd net15 clk_out_mux21 vss inverter_min_x2
+x10 vdd clk_d net15 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding symbol: prescaler_23.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/prescaler_23.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/prescaler_23.sch
+.subckt prescaler_23 vdd CLK_23 CLK nCLK vss MC Q1 nCLK_23 Q2 Q2_d
+*.iopin vdd
+*.ipin CLK
+*.ipin nCLK
+*.ipin MC
+*.iopin vss
+*.opin CLK_23
+*.iopin nCLK_23
+*.iopin Q1
+*.iopin Q2
+*.iopin Q2_d
+x3 nCLK_23 1 vss vss vdd vdd 2 sky130_fd_sc_hs__and2_1
+x4 Q1 MC vss vss vdd vdd 1 sky130_fd_sc_hs__or2_1
+x6 3 nCLK_23 MC vss vss vdd vdd CLK_23 sky130_fd_sc_hs__mux2_1
+x7 Q2 Q2_d vss vss vdd vdd 3 sky130_fd_sc_hs__or2_1
+x1 vdd Q1 net1 vss nCLK_23 CLK nCLK DFlipFlop
+x2 vdd Q2 nCLK_23 vss 2 CLK nCLK DFlipFlop
+x5 vdd Q2_d net2 vss Q2 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: div_by_5.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
+.subckt div_by_5 vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: mux2to4.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to4.sch
+.subckt mux2to4 vdd vss in_a in_b out_b_0 out_a_0 selec_0 out_b_1 out_a_1 selec_0_neg
+*.iopin in_a
+*.iopin in_b
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_b_0
+*.iopin out_b_1
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+x8 selec_0 out_b_1 in_b selec_0_neg vss vdd trans_gate_mux2to8
+x9 selec_0_neg out_b_0 in_b selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
+* expanding symbol: mux2to1.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to1.sch
+.subckt mux2to1 vdd vss in_a out_a_0 selec_0 out_a_1 selec_0_neg
+*.iopin in_a
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding symbol: and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: trans_gate_mux2to8.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate_mux2to8.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate_mux2to8.sch
+.subckt trans_gate_mux2to8 en_pos out in en_neg vss vdd
+*.iopin en_neg
+*.ipin in
+*.opin out
+*.iopin en_pos
+*.iopin vdd
+*.iopin vss
+XM2 out en_neg in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out en_pos in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+**** begin user architecture code
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/and2/sky130_fd_sc_hs__and2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/or2/sky130_fd_sc_hs__or2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/mux2/sky130_fd_sc_hs__mux2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/xor2/sky130_fd_sc_hs__xor2_1.spice
+
+**** end user architecture code
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_freq_div_pex_c.spice b/xschem/simulations/tb_freq_div_pex_c.spice
new file mode 100644
index 0000000..276f009
--- /dev/null
+++ b/xschem/simulations/tb_freq_div_pex_c.spice
@@ -0,0 +1,77 @@
+**.subckt tb_freq_div_pex_c
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref net9 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+VMC S1 vss PULSE(0 {vin} 0 1p 1p 400n 800n) DC {vin} AC 0
+x4 vdd net10 net9 vss inverter_min_x2_pex_c
+x5 vdd CLK net10 vss inverter_min_x4_pex_c
+VMC1 S0 vss PULSE(0 {vin} 0 1p 1p 200n 400n) DC {vin} AC 0
+VMC2 MC vss PULSE(0 {vin} 0 1p 1p 100n 200n) DC {vin} AC 0
+x1 s1n s0n S0 S1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 f_div clk_2 clk_5 clk_2_f
++ nclk_2 clk_1 n_clk_1 freq_div_pex_c
+x2 nclk_2 vss CLK vdd clk_2 net1 net2 net3 net4 div_by_2_pex_c
+x3 vss vdd net7 net6 f_div net8 net5 PFD_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+.options GMIN = 1e-10
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/freq_div_pex_c.spice
+
+* Data to save
+.save all
+.ic v(CLK) = 0.0
+.ic v(MC) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(f_div) = 0.0
+.ic v(S0) = 0.0
+.ic v(S1) = 0.0
+.ic v(clk_0) = 0.0
+.ic v(n_clk_0) = 0.0
+.ic v(clk_1) = 0.0
+.ic v(n_clk_1) = 0.0
+.ic v(clk_pre) = 0.0
+.ic v(clk_5) = 0.0
+.ic v(clk_d) = 0.0
+.ic v(clk_2_f) = 0.0
+.ic v(s1n) = 0.0
+.ic v(s0n) = 0.0
+
+* Simulation
+.control
+ save v(CLK) v(clk_2) v(S1) v(S0) v(MC) v(clk_0) v(clk_1) v(clk_pre) v(clk_5) v(clk_d) v(clk_2_f)
++ v(f_div)
+ tran 0.01ns 800ns
+ write tb_freq_div_tran.raw
+ plot v(CLK) v(clk_2)+2 v(S1)+4 v(S0)+6 v(MC)+8 v(clk_0)+10 v(clk_1)+12 v(clk_pre)+14 v(clk_5)+16
++ v(clk_d)+18 v(clk_2_f)+20 v(f_div)+22
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+**** begin user architecture code
+
+**** end user architecture code
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_mux2to1.spice b/xschem/simulations/tb_mux2to1.spice
new file mode 100644
index 0000000..3875f14
--- /dev/null
+++ b/xschem/simulations/tb_mux2to1.spice
@@ -0,0 +1,249 @@
+**.subckt tb_mux2to1
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref net1 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+x1 in_a vss A vdd in_b out_div net3 net4 net5 div_by_2
+x2 vdd net2 net1 vss inverter_min_x2_pex_c
+x3 vdd A net2 vss inverter_min_x4_pex_c
+Vref1 selec_0 vss PULSE(0 {vin} 0 1p 1p {12.5n} {25n}) DC {vin} AC 0
+x7 vdd selec_0_neg selec_0 vss inverter_min_x4_pex_c
+C8 out_b_0_1 vss 10f m=1
+x4 vdd vss out_b_0_1 in_a selec_0_neg in_b selec_0 mux2to1
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/sky130-mpw2-fulgor/inverter_min_x2/sch/simulations/inverter_min_x2_pex_c.spice
+.include ~/sky130-mpw2-fulgor/inverter_min_x4/sch/simulations/inverter_min_x4_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 50ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ *write tb_div_by_2_tran.raw
+ plot v(selec_0) v(out_b_0_1)+8
+ *plot v(out_div) v(out)
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: div_by_2/sch/div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/div_by_2/sch/div_by_2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/div_by_2/sch/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: mux2to1/sch/mux2to1.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/mux2to1/sch/mux2to1.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/mux2to1/sch/mux2to1.sch
+.subckt mux2to1 vdd vss in_a out_a_0 selec_0 out_a_1 selec_0_neg
+*.iopin in_a
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
+* expanding symbol: DFlipFlop/sch/DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/DFlipFlop/sch/DFlipFlop.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/DFlipFlop/sch/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter/sch/clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/clock_inverter/sch/clock_inverter.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/clock_inverter/sch/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: inverter_min_x2/sch/inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4/sch/inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x4/sch/inverter_min_x4.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x4/sch/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: trans_gate_mux2to8/sch/trans_gate_mux2to8.sym # of pins=6
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate_mux2to8/sch/trans_gate_mux2to8.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate_mux2to8/sch/trans_gate_mux2to8.sch
+.subckt trans_gate_mux2to8 en_pos out in en_neg vss vdd
+*.iopin en_neg
+*.ipin in
+*.opin out
+*.iopin en_pos
+*.iopin vdd
+*.iopin vss
+XM2 out en_neg in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out en_pos in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: latch_diff/sch/latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/latch_diff/sch/latch_diff.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/latch_diff/sch/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate/sch/trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate/sch/trans_gate.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate/sch/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1/sch/inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_cp_x1/sch/inverter_cp_x1.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_cp_x1/sch/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_mux2to4.spice b/xschem/simulations/tb_mux2to4.spice
new file mode 100644
index 0000000..da3cbfd
--- /dev/null
+++ b/xschem/simulations/tb_mux2to4.spice
@@ -0,0 +1,257 @@
+**.subckt tb_mux2to4
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref net1 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+x1 in_a vss A vdd in_b out_div net3 net4 net5 div_by_2
+x2 vdd net2 net1 vss inverter_min_x2_pex_c
+x3 vdd A net2 vss inverter_min_x4_pex_c
+Vref1 selec_0 vss PULSE(0 {vin} 0 1p 1p {12.5n} {25n}) DC {vin} AC 0
+x7 vdd selec_0_neg selec_0 vss inverter_min_x4_pex_c
+C5 out_a_0_0 vss 10f m=1
+C6 out_b_0_0 vss 10f m=1
+C7 out_a_0_1 vss 10f m=1
+C8 out_b_0_1 vss 10f m=1
+x4 vdd vss in_a in_b out_b_0_0 out_a_0_0 selec_0 out_b_0_1 out_a_0_1 selec_0_neg mux2to4
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/sky130-mpw2-fulgor/inverter_min_x2/sch/simulations/inverter_min_x2_pex_c.spice
+.include ~/sky130-mpw2-fulgor/inverter_min_x4/sch/simulations/inverter_min_x4_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 50ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ *write tb_div_by_2_tran.raw
+ plot v(selec_0) v(out_b_0_0)+4 v(out_a_0_0)+6 v(out_b_0_1)+8 v(out_a_0_1)+10
+ *plot v(out_div) v(out)
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: div_by_2/sch/div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/div_by_2/sch/div_by_2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/div_by_2/sch/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: mux2to4/sch/mux2to4.sym # of pins=10
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/mux2to4/sch/mux2to4.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/mux2to4/sch/mux2to4.sch
+.subckt mux2to4 vdd vss in_a in_b out_b_0 out_a_0 selec_0 out_b_1 out_a_1 selec_0_neg
+*.iopin in_a
+*.iopin in_b
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_b_0
+*.iopin out_b_1
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+x8 selec_0 out_b_1 in_b selec_0_neg vss vdd trans_gate_mux2to8
+x9 selec_0_neg out_b_0 in_b selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
+* expanding symbol: DFlipFlop/sch/DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/DFlipFlop/sch/DFlipFlop.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/DFlipFlop/sch/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter/sch/clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/clock_inverter/sch/clock_inverter.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/clock_inverter/sch/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: inverter_min_x2/sch/inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4/sch/inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x4/sch/inverter_min_x4.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x4/sch/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: trans_gate_mux2to8/sch/trans_gate_mux2to8.sym # of pins=6
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate_mux2to8/sch/trans_gate_mux2to8.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate_mux2to8/sch/trans_gate_mux2to8.sch
+.subckt trans_gate_mux2to8 en_pos out in en_neg vss vdd
+*.iopin en_neg
+*.ipin in
+*.opin out
+*.iopin en_pos
+*.iopin vdd
+*.iopin vss
+XM2 out en_neg in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out en_pos in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: latch_diff/sch/latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/latch_diff/sch/latch_diff.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/latch_diff/sch/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate/sch/trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate/sch/trans_gate.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate/sch/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1/sch/inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_cp_x1/sch/inverter_cp_x1.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_cp_x1/sch/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_prescaler_23.spice b/xschem/simulations/tb_prescaler_23.spice
new file mode 100644
index 0000000..46aa9e6
--- /dev/null
+++ b/xschem/simulations/tb_prescaler_23.spice
@@ -0,0 +1,233 @@
+**.subckt tb_prescaler_23
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref CLK vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+C2 clk_23 vss 10f m=1
+x2 nclk_2 vss CLK vdd clk_2 net1 net2 net3 net4 div_by_2
+x1 vdd clk_23 clk_2 nclk_2 vss MC net6 net5 net7 net8 prescaler_23
+VMC MC vss PULSE(0 {vin} 0 1p 1p 400n 800n) DC {vin} AC 0
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+.ic v(CLK) = 0.0
+.ic v(MC) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(clk_23) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 800ns
+ write tb_div_by_5_tran.raw
+ plot v(clk_23) v(clk) v(clk_2) v(clk_23)+3 v(clk_2)+6 v(clk)+9
+
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: div_by_2/sch/div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/div_by_2/sch/div_by_2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/div_by_2/sch/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: prescaler_23/sch/prescaler_23.sym # of pins=10
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/prescaler_23/sch/prescaler_23.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/prescaler_23/sch/prescaler_23.sch
+.subckt prescaler_23 vdd CLK_23 CLK nCLK vss MC Q1 nCLK_23 Q2 Q2_d
+*.iopin vdd
+*.ipin CLK
+*.ipin nCLK
+*.ipin MC
+*.iopin vss
+*.opin CLK_23
+*.iopin nCLK_23
+*.iopin Q1
+*.iopin Q2
+*.iopin Q2_d
+x3 nCLK_23 1 vss vss vdd vdd 2 sky130_fd_sc_hs__and2_1
+x4 Q1 MC vss vss vdd vdd 1 sky130_fd_sc_hs__or2_1
+x6 3 nCLK_23 MC vss vss vdd vdd CLK_23 sky130_fd_sc_hs__mux2_1
+x7 Q2 Q2_d vss vss vdd vdd 3 sky130_fd_sc_hs__or2_1
+x1 vdd Q1 net1 vss nCLK_23 CLK nCLK DFlipFlop
+x2 vdd Q2 nCLK_23 vss 2 CLK nCLK DFlipFlop
+x5 vdd Q2_d net2 vss Q2 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: DFlipFlop/sch/DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/DFlipFlop/sch/DFlipFlop.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/DFlipFlop/sch/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter/sch/clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/clock_inverter/sch/clock_inverter.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/clock_inverter/sch/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: inverter_min_x2/sch/inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4/sch/inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x4/sch/inverter_min_x4.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x4/sch/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: latch_diff/sch/latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/latch_diff/sch/latch_diff.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/latch_diff/sch/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate/sch/trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate/sch/trans_gate.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/trans_gate/sch/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1/sch/inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_cp_x1/sch/inverter_cp_x1.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_cp_x1/sch/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+.GLOBAL GND
+**** begin user architecture code
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/and2/sky130_fd_sc_hs__and2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/or2/sky130_fd_sc_hs__or2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/mux2/sky130_fd_sc_hs__mux2_1.spice
+
+**** end user architecture code
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_prescaler_23_pex_c.spice b/xschem/simulations/tb_prescaler_23_pex_c.spice
new file mode 100644
index 0000000..b350049
--- /dev/null
+++ b/xschem/simulations/tb_prescaler_23_pex_c.spice
@@ -0,0 +1,57 @@
+**.subckt tb_prescaler_23_pex_c
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref CLK vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+C2 clk_23 vss 10f m=1
+Vmc MC vss PULSE({vin} 0 0 1p 1p 400n 800n) DC {vin} AC 0
+x1 vdd clk_23 clk_2 nclk_2 vss MC net6 net5 net7 net8 prescaler_23_pex_c
+x2 nclk_2 vss CLK vdd clk_2 net1 net2 net3 net4 div_by_2_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/sky130-mpw2-fulgor/div_by_2/sch/simulations/div_by_2_pex_c.spice
+.include ~/sky130-mpw2-fulgor/prescaler_23/sch/simulations/prescaler_23_pex_c.spice
+
+* Data to save
+
+.ic v(CLK) = 0.0
+.ic v(MC) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(clk_23) = 0.0
+
+* Simulation
+.control
+ save v(MC) v(CLK) v(clk_2) v(nclk_2) v(clk_23)
+ tran 0.01ns 800ns
+ write tb_div_by_5_tran.raw
+ plot v(clk_23) v(clk) v(clk_2) v(MC)+3 v(clk_23)+6 v(clk_2)+9 v(clk)+12
+
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+**** begin user architecture code
+
+**** end user architecture code
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_top_pll_v3.spice b/xschem/simulations/tb_top_pll_v3.spice
new file mode 100644
index 0000000..276828a
--- /dev/null
+++ b/xschem/simulations/tb_top_pll_v3.spice
@@ -0,0 +1,891 @@
+**.subckt tb_top_pll_v3
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+VD0 D0 vss {vd0}
+I0 net1 vss {iref}
+x2 vdd net1 iref_cp net2 net3 net4 net5 net6 net7 net8 net9 net10 bias
+C1 out_to_pad vss 20p m=1
+x1 iref_cp vss vdd vco_out vctrl Up QA out_to_buffer A nUp out_to_pad Down nDown QB D0 lf_vc
++ vco_buffer_out biasp pswitch nswitch pfd_reset S0 MC S1 out_by_2 out_to_div out_div n_out_by_2 n_out_div_2
++ out_div_2 out_buffer_div_2 n_out_buffer_div_2 n_clk_0 s1n s0n clk_2_f clk_d clk_out_div clk_5 clk_pre n_clk_1
++ clk_1 clk_0 D1 top_pll_v3
+VD1 D1 vss {vd1}
+VMC S1 vss {vin}
+VMC1 S0 vss {vin}
+VMC2 MC vss {vin}
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param vd1 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+.options GMIN = 1e-10
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(clk_0) = 0.0
+.ic v(n_clk_0) = 0.0
+.ic v(clk_1) = 0.0
+.ic v(n_clk_1) = 0.0
+.ic v(clk_pre) = 0.0
+.ic v(clk_5) = 0.0
+.ic v(clk_d) = 0.0
+.ic v(clk_2_f) = 0.0
+.ic v(s1n) = 0.0
+.ic v(s0n) = 0.0
+.ic v(out_div) = 0.0
+
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+ let T = wTosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14
++ v(out_div)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_div)
+ plot v(out_div) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: bias.sym # of pins=12
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sch
+.subckt bias vdd iref iref_0 iref_1 iref_2 iref_3 iref_4 iref_5 iref_6 iref_7 iref_8 iref_9
+*.iopin iref
+*.iopin vdd
+*.opin iref_0
+*.opin iref_1
+*.opin iref_2
+*.opin iref_3
+*.opin iref_4
+*.opin iref_5
+*.opin iref_6
+*.opin iref_7
+*.opin iref_8
+*.opin iref_9
+XM1 iref iref vbp1 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM2 vbp1 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM3 net1 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM4 iref_0 iref net1 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM5 net2 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM6 iref_1 iref net2 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM7 net3 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM8 iref_2 iref net3 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM9 net4 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM10 iref_3 iref net4 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM11 net5 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM12 iref_4 iref net5 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM13 net6 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM14 iref_5 iref net6 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM15 net7 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM16 iref_6 iref net7 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM17 net8 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM18 iref_7 iref net8 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM19 net9 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM20 iref_8 iref net9 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM21 net10 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM22 iref_9 iref net10 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+.ends
+
+
+* expanding symbol: top_pll_v3.sym # of pins=44
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v3.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v3.sch
+.subckt top_pll_v3 iref_cp vss vdd vco_out vco_vctrl Up pfd_QA out_to_buffer in_ref nUp out_to_pad
++ Down nDown pfd_QB lf_D0 lf_vc out_first_buffer cp_biasp cp_pswitch cp_nswitch pfd_reset s_0 MC s_1
++ out_by_2 out_to_div out_div n_out_by_2 n_out_div_2 out_div_2 n_out_buffer_div_2 out_buffer_div_2 n_clk_0 s1n
++ s0n clk_2_f clk_d clk_out_mux21 clk_5 clk_pre n_clk_1 clk_1 clk_0 lf_D0
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.ipin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.iopin out_to_buffer
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin out_div
+*.opin out_to_pad
+*.iopin clk_0
+*.iopin n_clk_0
+*.iopin clk_1
+*.iopin n_clk_1
+*.iopin clk_pre
+*.iopin clk_5
+*.iopin clk_out_mux21
+*.iopin clk_d
+*.iopin clk_2_f
+*.iopin s0n
+*.iopin s1n
+*.ipin MC
+*.ipin s_0
+*.ipin s_1
+x1 vss vdd pfd_QA in_ref out_div pfd_QB pfd_reset PFD
+x2 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface
+x3 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump
+x5 vdd vco_out vco_D0 vco_vctrl vss csvco
+x6 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer
+x7 vdd out_to_pad out_to_buffer vss buffer_salida
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2
+x9 s1n s0n s_0 s_1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 out_div out_by_2 clk_5
++ clk_2_f n_out_by_2 clk_1 n_clk_1 freq_div
+x4 vss vco_vctrl lf_vc loop_filter
+.ends
+
+
+* expanding symbol: PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding symbol: pfd_cp_interface.sym # of pins=8
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
+.subckt pfd_cp_interface Up vdd QA nUp Down QB vss nDown
+*.iopin vdd
+*.iopin vss
+*.ipin QA
+*.ipin QB
+*.opin nDown
+*.opin Down
+*.opin nUp
+*.opin Up
+x5 vdd nDown nQB vss trans_gate
+x3 vdd Up nQA vss inverter_cp_x1
+x1 vdd nQB QB vss inverter_cp_x1
+x2 vdd nQA QA vss inverter_cp_x1
+x4 vdd nUp Up vss inverter_cp_x2
+x6 vdd Down nDown vss inverter_cp_x2
+.ends
+
+
+* expanding symbol: charge_pump.sym # of pins=11
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sch
+.subckt charge_pump vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
+*.iopin vss
+*.iopin vdd
+*.ipin Down
+*.ipin nUp
+*.ipin Up
+*.ipin nDown
+*.opin out
+*.iopin nswitch
+*.iopin pswitch
+*.ipin iref
+*.iopin biasp
+XM1 out pswitch vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM2 out nswitch vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM3 pswitch nUp biasp vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 pswitch Up vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM5 nswitch Down iref vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM6 nswitch nDown vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM7 pswitch nUp pswitch vdd sky130_fd_pr__pfet_01v8 L=2 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM8 nswitch Down nswitch vss sky130_fd_pr__nfet_01v8 L=1.5 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM9 iref iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM10 biasp iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM11 biasp biasp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+.ends
+
+
+* expanding symbol: csvco.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sch
+.subckt csvco vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd vbp out out1 vctrl vss D0 csvco_branch
+x2 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x3 vdd vbp out2 out vctrl vss D0 csvco_branch
+.ends
+
+
+* expanding symbol: ring_osc_buffer.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
+.subckt ring_osc_buffer vdd in_vco out_pad out_div vss o1
+*.iopin vdd
+*.iopin vss
+*.ipin in_vco
+*.opin out_pad
+*.opin out_div
+*.iopin o1
+x1 vdd o1 in_vco vss inverter_min_x2
+x2 vdd out_div o1 vss inverter_min_x4
+x3 vdd out_pad out_div vss inverter_min_x4
+.ends
+
+
+* expanding symbol: buffer_salida.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sch
+.subckt buffer_salida vdd out in vss
+*.iopin vss
+*.ipin in
+*.iopin vdd
+*.opin out
+XM2 net1 in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 net1 in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM3 net2 net1 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM4 net2 net1 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM5 out net2 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+XM6 out net2 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+.ends
+
+
+* expanding symbol: div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: freq_div.sym # of pins=19
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/freq_div.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/freq_div.sch
+.subckt freq_div s_1_n s_0_n s_0 s_1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 out in_a
++ clk_5 clk_2 in_b clk_1 n_clk_1
+*.ipin s_0
+*.iopin vdd
+*.iopin vss
+*.ipin in_a
+*.ipin in_b
+*.opin out
+*.ipin MC
+*.ipin s_1
+*.iopin clk_0
+*.iopin n_clk_0
+*.iopin clk_1
+*.iopin n_clk_1
+*.iopin clk_pre
+*.iopin clk_5
+*.iopin clk_out_mux21
+*.iopin clk_d
+*.iopin clk_2
+*.iopin s_0_n
+*.iopin s_1_n
+x2 vdd clk_pre clk_0 n_clk_0 vss MC net2 net1 net3 net4 prescaler_23
+x3 net14 vss clk_out_mux21 vdd clk_2 net5 net6 net7 net8 div_by_2
+x4 vdd clk_5 clk_1 vss n_clk_1 net9 net10 net12 net13 net11 div_by_5
+x9 vdd s_0_n s_0 vss inverter_min_x2
+x1 vdd vss in_a in_b n_clk_0 clk_0 s_0 n_clk_1 clk_1 s_0_n mux2to4
+x6 vdd vss clk_out_mux21 clk_pre s_0 clk_5 s_0_n mux2to1
+x5 vdd vss out clk_d s_1 clk_2 s_1_n mux2to1
+x7 vdd s_1_n s_1 vss inverter_min_x2
+x8 vdd net15 clk_out_mux21 vss inverter_min_x2
+x10 vdd clk_d net15 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sch
+.subckt loop_filter vss in vc_pex
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+x1 in net1 vss res_loop_filter
+x2 vc_pex net1 vss res_loop_filter
+x3 vc_pex net1 vss res_loop_filter
+x4 vc_pex vss cap1_loop_filter
+x5 in vss cap2_loop_filter
+.ends
+
+
+* expanding symbol: DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding symbol: and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+
+* expanding symbol: csvco_branch.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sch
+.subckt csvco_branch vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: prescaler_23.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/prescaler_23.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/prescaler_23.sch
+.subckt prescaler_23 vdd CLK_23 CLK nCLK vss MC Q1 nCLK_23 Q2 Q2_d
+*.iopin vdd
+*.ipin CLK
+*.ipin nCLK
+*.ipin MC
+*.iopin vss
+*.opin CLK_23
+*.iopin nCLK_23
+*.iopin Q1
+*.iopin Q2
+*.iopin Q2_d
+x3 nCLK_23 1 vss vss vdd vdd 2 sky130_fd_sc_hs__and2_1
+x4 Q1 MC vss vss vdd vdd 1 sky130_fd_sc_hs__or2_1
+x6 3 nCLK_23 MC vss vss vdd vdd CLK_23 sky130_fd_sc_hs__mux2_1
+x7 Q2 Q2_d vss vss vdd vdd 3 sky130_fd_sc_hs__or2_1
+x1 vdd Q1 net1 vss nCLK_23 CLK nCLK DFlipFlop
+x2 vdd Q2 nCLK_23 vss 2 CLK nCLK DFlipFlop
+x5 vdd Q2_d net2 vss Q2 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: div_by_5.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
+.subckt div_by_5 vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: mux2to4.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to4.sch
+.subckt mux2to4 vdd vss in_a in_b out_b_0 out_a_0 selec_0 out_b_1 out_a_1 selec_0_neg
+*.iopin in_a
+*.iopin in_b
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_b_0
+*.iopin out_b_1
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+x8 selec_0 out_b_1 in_b selec_0_neg vss vdd trans_gate_mux2to8
+x9 selec_0_neg out_b_0 in_b selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
+* expanding symbol: mux2to1.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to1.sch
+.subckt mux2to1 vdd vss in_a out_a_0 selec_0 out_a_1 selec_0_neg
+*.iopin in_a
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
+* expanding symbol: res_loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sch
+.subckt res_loop_filter in out vss
+*.iopin in
+*.iopin vss
+*.iopin out
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 L=22.92 mult=1 m=1
+.ends
+
+
+* expanding symbol: cap1_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
+.subckt cap1_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+.ends
+
+
+* expanding symbol: cap2_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
+.subckt cap2_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+.ends
+
+
+* expanding symbol: nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate_mux2to8.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate_mux2to8.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate_mux2to8.sch
+.subckt trans_gate_mux2to8 en_pos out in en_neg vss vdd
+*.iopin en_neg
+*.ipin in
+*.opin out
+*.iopin en_pos
+*.iopin vdd
+*.iopin vss
+XM2 out en_neg in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out en_pos in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+.GLOBAL GND
+**** begin user architecture code
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/and2/sky130_fd_sc_hs__and2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/or2/sky130_fd_sc_hs__or2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/mux2/sky130_fd_sc_hs__mux2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/xor2/sky130_fd_sc_hs__xor2_1.spice
+
+**** end user architecture code
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_top_pll_v3_pex_c.spice b/xschem/simulations/tb_top_pll_v3_pex_c.spice
new file mode 100644
index 0000000..9175dd1
--- /dev/null
+++ b/xschem/simulations/tb_top_pll_v3_pex_c.spice
@@ -0,0 +1,99 @@
+**.subckt tb_top_pll_v3_pex_c
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+VD0 D0 vss {vd0}
+I0 net1 vss {iref}
+C1 out_to_pad vss 20p m=1
+VD1 D1 vss {vd1}
+VMC S1 vss {vin}
+VMC1 S0 vss {vin}
+VMC2 MC vss {vin}
+x1 vdd net1 vss iref_cp net2 net3 net4 net5 net6 net7 net8 net9 net10 bias_pex_c
+x2 iref_cp vss vdd vco_out vctrl Up QA out_to_buffer A nUp out_to_pad Down nDown QB D0 lf_vc
++ vco_buffer_out biasp pswitch nswitch pfd_reset S0 MC S1 out_by_2 out_to_div out_div n_out_by_2 n_out_div_2
++ out_div_2 out_buffer_div_2 n_out_buffer_div_2 n_clk_0 s1n s0n clk_2_f clk_d clk_out_div clk_5 clk_pre n_clk_1
++ clk_1 clk_0 D1 top_pll_v3_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param vd1 = 0.0
+
+.options TEMP = 0.0
+.options RSHUNT = 1e20
+.options GMIN = 1e-10
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/top_pll_v3_pex_c.spice
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(clk_0) = 0.0
+.ic v(n_clk_0) = 0.0
+.ic v(clk_1) = 0.0
+.ic v(n_clk_1) = 0.0
+.ic v(clk_pre) = 0.0
+.ic v(clk_5) = 0.0
+.ic v(clk_d) = 0.0
+.ic v(clk_2_f) = 0.0
+.ic v(s1n) = 0.0
+.ic v(s0n) = 0.0
+.ic v(out_div) = 0.0
+
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+ let T = wTosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14
++ v(out_div)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_div)
+ plot v(out_div) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_top_pll_v3_pex_no_integration.spice b/xschem/simulations/tb_top_pll_v3_pex_no_integration.spice
new file mode 100644
index 0000000..559cc18
--- /dev/null
+++ b/xschem/simulations/tb_top_pll_v3_pex_no_integration.spice
@@ -0,0 +1,260 @@
+**.subckt tb_top_pll_v3_pex_no_integration
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+VD0 D0 vss {vd0}
+I0 net1 vss {iref}
+x2 vdd net1 iref_cp net2 net3 net4 net5 net6 net7 net8 net9 net10 bias
+C1 out_to_pad vss 20p m=1
+VD1 D1 vss {vd1}
+VMC S1 vss PULSE(0.0 0.0 0 1p 1p 400n 800n) DC {vin} AC 0
+VMC1 S0 vss PULSE({vin} {vin} 0 1p 1p 200n 400n) DC {vin} AC 0
+VMC2 MC vss PULSE({vin} {vin} 0 1p 1p 100n 200n) DC {vin} AC 0
+x1 iref_cp vss vdd vco_out vctrl Up QA out_to_buffer A nUp out_to_pad Down nDown QB D0 lf_vc
++ vco_buffer_out biasp pswitch nswitch pfd_reset S0 MC S1 out_by_2 out_to_div out_div n_out_by_2 n_out_div_2
++ out_div_2 out_buffer_div_2 n_out_buffer_div_2 n_clk_0 s1n s0n clk_2_f clk_d clk_out_div clk_5 clk_pre n_clk_1
++ clk_1 clk_0 D1 top_pll_v3_pex_no_integration
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param vd1 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+.options GMIN = 1e-10
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/charge_pump_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/loop_filter_v2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/ring_osc_buffer_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/buffer_salida_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/freq_div_pex_c.spice
+
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(clk_0) = 0.0
+.ic v(n_clk_0) = 0.0
+.ic v(clk_1) = 0.0
+.ic v(n_clk_1) = 0.0
+.ic v(clk_pre) = 0.0
+.ic v(clk_5) = 0.0
+.ic v(clk_d) = 0.0
+.ic v(clk_2_f) = 0.0
+.ic v(s1n) = 0.0
+.ic v(s0n) = 0.0
+.ic v(out_div) = 0.0
+
+
+* Simulation
+.control
+ tran 0.01ns 2us
+ meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+ let T = Tosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14
++ v(out_div)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_div)
+ plot v(out_div) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: bias.sym # of pins=12
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sch
+.subckt bias vdd iref iref_0 iref_1 iref_2 iref_3 iref_4 iref_5 iref_6 iref_7 iref_8 iref_9
+*.iopin iref
+*.iopin vdd
+*.opin iref_0
+*.opin iref_1
+*.opin iref_2
+*.opin iref_3
+*.opin iref_4
+*.opin iref_5
+*.opin iref_6
+*.opin iref_7
+*.opin iref_8
+*.opin iref_9
+XM1 iref iref vbp1 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM2 vbp1 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM3 net1 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM4 iref_0 iref net1 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM5 net2 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM6 iref_1 iref net2 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM7 net3 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM8 iref_2 iref net3 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM9 net4 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM10 iref_3 iref net4 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM11 net5 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM12 iref_4 iref net5 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM13 net6 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM14 iref_5 iref net6 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM15 net7 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM16 iref_6 iref net7 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM17 net8 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM18 iref_7 iref net8 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM19 net9 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM20 iref_8 iref net9 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM21 net10 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM22 iref_9 iref net10 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+.ends
+
+
+* expanding symbol: top_pll_v3_pex_no_integration.sym # of pins=44
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v3_pex_no_integration.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v3_pex_no_integration.sch
+.subckt top_pll_v3_pex_no_integration iref_cp vss vdd vco_out vco_vctrl Up pfd_QA out_to_buffer
++ in_ref nUp out_to_pad Down nDown pfd_QB lf_D0 lf_vc out_first_buffer cp_biasp cp_pswitch cp_nswitch
++ pfd_reset s_0 MC s_1 out_by_2 out_to_div out_div n_out_by_2 n_out_div_2 out_div_2 n_out_buffer_div_2
++ out_buffer_div_2 n_clk_0 s1n s0n clk_2_f clk_d clk_out_mux21 clk_5 clk_pre n_clk_1 clk_1 clk_0 lf_D0
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.ipin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.iopin out_to_buffer
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin out_div
+*.opin out_to_pad
+*.iopin clk_0
+*.iopin n_clk_0
+*.iopin clk_1
+*.iopin n_clk_1
+*.iopin clk_pre
+*.iopin clk_5
+*.iopin clk_out_mux21
+*.iopin clk_d
+*.iopin clk_2_f
+*.iopin s0n
+*.iopin s1n
+*.ipin MC
+*.ipin s_0
+*.ipin s_1
+*.ipin lf_D0
+x1 vss vdd pfd_QA in_ref out_div pfd_QB pfd_reset PFD_pex_c
+x2 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface_pex_c
+x4 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump_pex_c
+x5 vss vco_vctrl lf_vc lf_D0 loop_filter_v2_pex_c
+x6 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer_pex_c
+x7 vdd out_to_pad out_to_buffer vss buffer_salida_pex_c
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2_pex_c
+x9 s1n s0n s_0 s_1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 out_div out_by_2 clk_5
++ clk_2_f n_out_by_2 clk_1 n_clk_1 freq_div_pex_c
+x3 vdd vco_out vco_vctrl vss vco_D0 csvco_pex_c
+.ends
+
+.GLOBAL GND
+**** begin user architecture code
+
+**** end user architecture code
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/top_pll_v3.spice b/xschem/simulations/top_pll_v3.spice
new file mode 100644
index 0000000..fb4daed
--- /dev/null
+++ b/xschem/simulations/top_pll_v3.spice
@@ -0,0 +1,715 @@
+**.subckt top_pll_v3 vdd vss in_ref pfd_QA pfd_QB Up nUp Down nDown pfd_reset cp_nswitch cp_pswitch
+*+ cp_biasp iref_cp lf_vc vco_D0 vco_vctrl vco_out out_first_buffer out_to_buffer out_to_div out_by_2
+*+ n_out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2 out_div out_to_pad clk_0 n_clk_0 clk_1
+*+ n_clk_1 clk_pre clk_5 clk_out_mux21 clk_d clk_2_f s0n s1n MC s_0 s_1 lf_D0
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.ipin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.iopin out_to_buffer
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin out_div
+*.opin out_to_pad
+*.iopin clk_0
+*.iopin n_clk_0
+*.iopin clk_1
+*.iopin n_clk_1
+*.iopin clk_pre
+*.iopin clk_5
+*.iopin clk_out_mux21
+*.iopin clk_d
+*.iopin clk_2_f
+*.iopin s0n
+*.iopin s1n
+*.ipin MC
+*.ipin s_0
+*.ipin s_1
+*.ipin lf_D0
+x1 vss vdd pfd_QA in_ref out_div pfd_QB pfd_reset PFD
+x2 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface
+x3 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump
+x5 vdd vco_out vco_D0 vco_vctrl vss csvco
+x6 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer
+x7 vdd out_to_pad out_to_buffer vss buffer_salida
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2
+x9 s1n s0n s_0 s_1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 out_div out_by_2 clk_5
++ clk_2_f n_out_by_2 clk_1 n_clk_1 freq_div
+x4 vss vco_vctrl lf_vc lf_D0 loop_filter_v2
+**.ends
+
+* expanding symbol: PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding symbol: pfd_cp_interface.sym # of pins=8
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
+.subckt pfd_cp_interface Up vdd QA nUp Down QB vss nDown
+*.iopin vdd
+*.iopin vss
+*.ipin QA
+*.ipin QB
+*.opin nDown
+*.opin Down
+*.opin nUp
+*.opin Up
+x5 vdd nDown nQB vss trans_gate
+x3 vdd Up nQA vss inverter_cp_x1
+x1 vdd nQB QB vss inverter_cp_x1
+x2 vdd nQA QA vss inverter_cp_x1
+x4 vdd nUp Up vss inverter_cp_x2
+x6 vdd Down nDown vss inverter_cp_x2
+.ends
+
+
+* expanding symbol: charge_pump.sym # of pins=11
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sch
+.subckt charge_pump vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
+*.iopin vss
+*.iopin vdd
+*.ipin Down
+*.ipin nUp
+*.ipin Up
+*.ipin nDown
+*.opin out
+*.iopin nswitch
+*.iopin pswitch
+*.ipin iref
+*.iopin biasp
+XM1 out pswitch vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM2 out nswitch vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM3 pswitch nUp biasp vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 pswitch Up vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM5 nswitch Down iref vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM6 nswitch nDown vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM7 pswitch nUp pswitch vdd sky130_fd_pr__pfet_01v8 L=2 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM8 nswitch Down nswitch vss sky130_fd_pr__nfet_01v8 L=1.5 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM9 iref iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM10 biasp iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM11 biasp biasp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+.ends
+
+
+* expanding symbol: csvco.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sch
+.subckt csvco vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd vbp out out1 vctrl vss D0 csvco_branch
+x2 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x3 vdd vbp out2 out vctrl vss D0 csvco_branch
+.ends
+
+
+* expanding symbol: ring_osc_buffer.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
+.subckt ring_osc_buffer vdd in_vco out_pad out_div vss o1
+*.iopin vdd
+*.iopin vss
+*.ipin in_vco
+*.opin out_pad
+*.opin out_div
+*.iopin o1
+x1 vdd o1 in_vco vss inverter_min_x2
+x2 vdd out_div o1 vss inverter_min_x4
+x3 vdd out_pad out_div vss inverter_min_x4
+.ends
+
+
+* expanding symbol: buffer_salida.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sch
+.subckt buffer_salida vdd out in vss
+*.iopin vss
+*.ipin in
+*.iopin vdd
+*.opin out
+XM2 net1 in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 net1 in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM3 net2 net1 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM4 net2 net1 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM5 out net2 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+XM6 out net2 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+.ends
+
+
+* expanding symbol: div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: freq_div.sym # of pins=19
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/freq_div.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/freq_div.sch
+.subckt freq_div s_1_n s_0_n s_0 s_1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 out in_a
++ clk_5 clk_2 in_b clk_1 n_clk_1
+*.ipin s_0
+*.iopin vdd
+*.iopin vss
+*.ipin in_a
+*.ipin in_b
+*.opin out
+*.ipin MC
+*.ipin s_1
+*.iopin clk_0
+*.iopin n_clk_0
+*.iopin clk_1
+*.iopin n_clk_1
+*.iopin clk_pre
+*.iopin clk_5
+*.iopin clk_out_mux21
+*.iopin clk_d
+*.iopin clk_2
+*.iopin s_0_n
+*.iopin s_1_n
+x2 vdd clk_pre clk_0 n_clk_0 vss MC net2 net1 net3 net4 prescaler_23
+x3 net14 vss clk_out_mux21 vdd clk_2 net5 net6 net7 net8 div_by_2
+x4 vdd clk_5 clk_1 vss n_clk_1 net9 net10 net12 net13 net11 div_by_5
+x9 vdd s_0_n s_0 vss inverter_min_x2
+x1 vdd vss in_a in_b n_clk_0 clk_0 s_0 n_clk_1 clk_1 s_0_n mux2to4
+x6 vdd vss clk_out_mux21 clk_pre s_0 clk_5 s_0_n mux2to1
+x5 vdd vss out clk_d s_1 clk_2 s_1_n mux2to1
+x7 vdd s_1_n s_1 vss inverter_min_x2
+x8 vdd net15 clk_out_mux21 vss inverter_min_x2
+x10 vdd clk_d net15 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: loop_filter_v2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter_v2.sch
+.subckt loop_filter_v2 vss in vc_pex D0_cap
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+*.iopin D0_cap
+x1 in net1 vss res_loop_filter
+x2 vc_pex net1 vss res_loop_filter
+x3 vc_pex net1 vss res_loop_filter
+x4 vc_pex vss cap1_loop_filter
+x5 in vss cap2_loop_filter
+XM1 in D0_cap net2 vss sky130_fd_pr__nfet_01v8 L=0.3 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x6 net2 vss cap3_loop_filter
+.ends
+
+
+* expanding symbol: DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding symbol: and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+
+* expanding symbol: csvco_branch.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sch
+.subckt csvco_branch vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: prescaler_23.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/prescaler_23.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/prescaler_23.sch
+.subckt prescaler_23 vdd CLK_23 CLK nCLK vss MC Q1 nCLK_23 Q2 Q2_d
+*.iopin vdd
+*.ipin CLK
+*.ipin nCLK
+*.ipin MC
+*.iopin vss
+*.opin CLK_23
+*.iopin nCLK_23
+*.iopin Q1
+*.iopin Q2
+*.iopin Q2_d
+x3 nCLK_23 1 vss vss vdd vdd 2 sky130_fd_sc_hs__and2_1
+x4 Q1 MC vss vss vdd vdd 1 sky130_fd_sc_hs__or2_1
+x6 3 nCLK_23 MC vss vss vdd vdd CLK_23 sky130_fd_sc_hs__mux2_1
+x7 Q2 Q2_d vss vss vdd vdd 3 sky130_fd_sc_hs__or2_1
+x1 vdd Q1 net1 vss nCLK_23 CLK nCLK DFlipFlop
+x2 vdd Q2 nCLK_23 vss 2 CLK nCLK DFlipFlop
+x5 vdd Q2_d net2 vss Q2 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: div_by_5.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
+.subckt div_by_5 vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: mux2to4.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to4.sch
+.subckt mux2to4 vdd vss in_a in_b out_b_0 out_a_0 selec_0 out_b_1 out_a_1 selec_0_neg
+*.iopin in_a
+*.iopin in_b
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_b_0
+*.iopin out_b_1
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+x8 selec_0 out_b_1 in_b selec_0_neg vss vdd trans_gate_mux2to8
+x9 selec_0_neg out_b_0 in_b selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
+* expanding symbol: mux2to1.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to1.sch
+.subckt mux2to1 vdd vss in_a out_a_0 selec_0 out_a_1 selec_0_neg
+*.iopin in_a
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
+* expanding symbol: res_loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sch
+.subckt res_loop_filter in out vss
+*.iopin in
+*.iopin vss
+*.iopin out
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 L=22.92 mult=1 m=1
+.ends
+
+
+* expanding symbol: cap1_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
+.subckt cap1_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+.ends
+
+
+* expanding symbol: cap2_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
+.subckt cap2_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+.ends
+
+
+* expanding symbol: cap3_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sch
+.subckt cap3_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=4 m=4
+.ends
+
+
+* expanding symbol: nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate_mux2to8.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate_mux2to8.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate_mux2to8.sch
+.subckt trans_gate_mux2to8 en_pos out in en_neg vss vdd
+*.iopin en_neg
+*.ipin in
+*.opin out
+*.iopin en_pos
+*.iopin vdd
+*.iopin vss
+XM2 out en_neg in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out en_pos in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/top_pll_v3_no_integration.spice b/xschem/simulations/top_pll_v3_no_integration.spice
new file mode 100644
index 0000000..5da8ddc
--- /dev/null
+++ b/xschem/simulations/top_pll_v3_no_integration.spice
@@ -0,0 +1,62 @@
+**.subckt top_pll_v3_no_integration vdd vss in_ref pfd_QA pfd_QB Up nUp Down nDown pfd_reset
+*+ cp_nswitch cp_pswitch cp_biasp iref_cp lf_vc vco_D0 vco_vctrl vco_out out_first_buffer out_to_buffer
+*+ out_to_div out_by_2 n_out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2 out_div out_to_pad
+*+ clk_0 n_clk_0 clk_1 n_clk_1 clk_pre clk_5 clk_out_mux21 clk_d clk_2_f s0n s1n MC s_0 s_1 lf_D0
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.ipin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.iopin out_to_buffer
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin out_div
+*.opin out_to_pad
+*.iopin clk_0
+*.iopin n_clk_0
+*.iopin clk_1
+*.iopin n_clk_1
+*.iopin clk_pre
+*.iopin clk_5
+*.iopin clk_out_mux21
+*.iopin clk_d
+*.iopin clk_2_f
+*.iopin s0n
+*.iopin s1n
+*.ipin MC
+*.ipin s_0
+*.ipin s_1
+*.ipin lf_D0
+x1 vss vdd pfd_QA in_ref out_div pfd_QB pfd_reset PFD_pex_c
+x2 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface_pex_c
+x3 vdd vco_out vco_vctrl vss vco_D0 csvco_v2_pex_c
+x4 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump_pex_c
+x5 vss vco_vctrl lf_vc lf_D0 loop_filter_v2_pex_c
+x6 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer_pex_c
+x7 vdd out_to_pad out_to_buffer vss buffer_salida_pex_c
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2_pex_c
+x9 s1n s0n s_0 s_1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 out_div out_by_2 clk_5
++ clk_2_f n_out_by_2 clk_1 n_clk_1 freq_div_pex_c
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/top_pll_v3_pex_c.spice b/xschem/simulations/top_pll_v3_pex_c.spice
new file mode 100644
index 0000000..8f22a11
--- /dev/null
+++ b/xschem/simulations/top_pll_v3_pex_c.spice
@@ -0,0 +1,3528 @@
+* NGSPICE file created from top_pll_v3.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_n29_n486# w_n2457_n634# 0.02fF
+C1 a_n1861_n486# w_n2457_n634# 0.02fF
+C2 a_429_n486# w_n2457_n634# 0.02fF
+C3 a_n945_n486# w_n2457_n634# 0.02fF
+C4 a_887_n486# w_n2457_n634# 0.02fF
+C5 a_1345_n486# w_n2457_n634# 0.02fF
+C6 w_n2457_n634# a_2261_n486# 0.02fF
+C7 a_n1403_n486# w_n2457_n634# 0.02fF
+C8 a_n487_n486# w_n2457_n634# 0.02fF
+C9 w_n2457_n634# a_n2319_n486# 0.02fF
+C10 a_1803_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n1041_n75# a_n849_n75# 0.08fF
+C1 a_n561_n75# a_n657_n75# 0.22fF
+C2 a_n81_n75# a_n465_n75# 0.03fF
+C3 a_n369_n75# a_15_n75# 0.03fF
+C4 a_207_n75# a_399_n75# 0.08fF
+C5 a_591_n75# a_495_n75# 0.22fF
+C6 a_1071_n75# a_879_n75# 0.08fF
+C7 a_n657_n75# a_n369_n75# 0.05fF
+C8 a_n753_n75# a_n657_n75# 0.22fF
+C9 a_111_n75# a_207_n75# 0.22fF
+C10 a_303_n75# a_399_n75# 0.22fF
+C11 a_207_n75# a_495_n75# 0.05fF
+C12 a_207_n75# a_n81_n75# 0.05fF
+C13 a_n657_n75# a_n465_n75# 0.08fF
+C14 a_1071_n75# a_975_n75# 0.22fF
+C15 a_111_n75# a_303_n75# 0.08fF
+C16 a_n945_n75# a_n561_n75# 0.03fF
+C17 a_207_n75# a_15_n75# 0.08fF
+C18 a_303_n75# a_495_n75# 0.08fF
+C19 a_303_n75# a_n81_n75# 0.03fF
+C20 a_111_n75# a_n273_n75# 0.03fF
+C21 a_n945_n75# a_n753_n75# 0.08fF
+C22 a_n177_n75# a_n561_n75# 0.03fF
+C23 a_111_n75# a_399_n75# 0.05fF
+C24 a_n273_n75# a_n81_n75# 0.08fF
+C25 a_303_n75# a_15_n75# 0.05fF
+C26 a_687_n75# a_783_n75# 0.22fF
+C27 a_399_n75# a_495_n75# 0.22fF
+C28 a_n1229_n75# a_n945_n75# 0.05fF
+C29 a_n1041_n75# a_n657_n75# 0.03fF
+C30 a_1071_n75# a_1167_n75# 0.22fF
+C31 a_n177_n75# a_n369_n75# 0.08fF
+C32 a_n273_n75# a_15_n75# 0.05fF
+C33 a_n657_n75# a_n849_n75# 0.08fF
+C34 a_111_n75# a_495_n75# 0.03fF
+C35 a_111_n75# a_n81_n75# 0.08fF
+C36 a_687_n75# a_879_n75# 0.08fF
+C37 a_399_n75# a_15_n75# 0.03fF
+C38 a_n273_n75# a_n657_n75# 0.03fF
+C39 a_n1137_n75# a_n945_n75# 0.08fF
+C40 a_n561_n75# a_n369_n75# 0.08fF
+C41 a_n177_n75# a_n465_n75# 0.05fF
+C42 a_n753_n75# a_n561_n75# 0.08fF
+C43 a_591_n75# a_687_n75# 0.22fF
+C44 a_111_n75# a_15_n75# 0.22fF
+C45 a_783_n75# a_879_n75# 0.22fF
+C46 a_687_n75# a_975_n75# 0.05fF
+C47 a_n561_n75# a_n465_n75# 0.22fF
+C48 a_n81_n75# a_15_n75# 0.22fF
+C49 a_n753_n75# a_n369_n75# 0.03fF
+C50 a_n1041_n75# a_n945_n75# 0.22fF
+C51 a_207_n75# a_n177_n75# 0.03fF
+C52 a_591_n75# a_783_n75# 0.08fF
+C53 a_n945_n75# a_n849_n75# 0.22fF
+C54 a_n369_n75# a_n465_n75# 0.22fF
+C55 a_n753_n75# a_n465_n75# 0.05fF
+C56 a_783_n75# a_975_n75# 0.08fF
+C57 a_687_n75# a_303_n75# 0.03fF
+C58 a_591_n75# a_879_n75# 0.05fF
+C59 a_n1137_n75# a_n753_n75# 0.03fF
+C60 a_879_n75# a_975_n75# 0.22fF
+C61 a_n273_n75# a_n177_n75# 0.22fF
+C62 a_n561_n75# a_n849_n75# 0.05fF
+C63 a_n1229_n75# a_n1137_n75# 0.22fF
+C64 a_687_n75# a_399_n75# 0.05fF
+C65 a_591_n75# a_975_n75# 0.03fF
+C66 a_n1041_n75# a_n753_n75# 0.05fF
+C67 a_n273_n75# a_n561_n75# 0.05fF
+C68 a_1167_n75# a_783_n75# 0.03fF
+C69 a_111_n75# a_n177_n75# 0.05fF
+C70 a_n753_n75# a_n849_n75# 0.22fF
+C71 a_591_n75# a_207_n75# 0.03fF
+C72 a_n1229_n75# a_n1041_n75# 0.08fF
+C73 a_783_n75# a_399_n75# 0.03fF
+C74 a_687_n75# a_495_n75# 0.08fF
+C75 a_n273_n75# a_n369_n75# 0.22fF
+C76 a_n177_n75# a_n81_n75# 0.22fF
+C77 a_n1229_n75# a_n849_n75# 0.03fF
+C78 a_n465_n75# a_n849_n75# 0.03fF
+C79 a_1167_n75# a_879_n75# 0.05fF
+C80 a_n945_n75# a_n657_n75# 0.05fF
+C81 a_591_n75# a_303_n75# 0.05fF
+C82 a_n1137_n75# a_n1041_n75# 0.22fF
+C83 a_n273_n75# a_n465_n75# 0.08fF
+C84 a_n177_n75# a_15_n75# 0.08fF
+C85 a_1071_n75# a_687_n75# 0.03fF
+C86 a_783_n75# a_495_n75# 0.05fF
+C87 a_n1137_n75# a_n849_n75# 0.05fF
+C88 a_1167_n75# a_975_n75# 0.08fF
+C89 a_207_n75# a_303_n75# 0.22fF
+C90 a_591_n75# a_399_n75# 0.08fF
+C91 a_n81_n75# a_n369_n75# 0.05fF
+C92 a_1071_n75# a_783_n75# 0.05fF
+C93 a_879_n75# a_495_n75# 0.03fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_543_n75# a_831_n75# 0.05fF
+C1 a_n321_n75# a_63_n75# 0.03fF
+C2 a_n33_n75# a_n417_n75# 0.03fF
+C3 a_735_n75# a_927_n75# 0.08fF
+C4 a_447_n75# a_63_n75# 0.03fF
+C5 a_n897_n75# a_n609_n75# 0.05fF
+C6 a_255_n75# a_159_n75# 0.22fF
+C7 a_n801_n75# a_n989_n75# 0.08fF
+C8 a_447_n75# a_159_n75# 0.05fF
+C9 a_n801_n75# a_n417_n75# 0.03fF
+C10 a_351_n75# a_n33_n75# 0.03fF
+C11 a_831_n75# a_927_n75# 0.22fF
+C12 a_n801_n75# a_n897_n75# 0.22fF
+C13 a_351_n75# a_63_n75# 0.05fF
+C14 a_543_n75# a_927_n75# 0.03fF
+C15 a_n705_n75# a_n609_n75# 0.22fF
+C16 a_351_n75# a_159_n75# 0.08fF
+C17 a_n609_n75# a_n225_n75# 0.03fF
+C18 a_n129_n75# a_n513_n75# 0.03fF
+C19 a_n225_n75# a_n33_n75# 0.08fF
+C20 a_n927_n101# a_33_n101# 0.08fF
+C21 a_255_n75# a_n129_n75# 0.03fF
+C22 a_n801_n75# a_n705_n75# 0.22fF
+C23 a_n129_n75# a_n321_n75# 0.08fF
+C24 a_n225_n75# a_63_n75# 0.05fF
+C25 a_255_n75# a_639_n75# 0.03fF
+C26 a_543_n75# a_159_n75# 0.03fF
+C27 a_n225_n75# a_159_n75# 0.03fF
+C28 a_639_n75# a_447_n75# 0.08fF
+C29 a_n129_n75# a_n417_n75# 0.05fF
+C30 a_n513_n75# a_n321_n75# 0.08fF
+C31 a_n801_n75# a_n609_n75# 0.08fF
+C32 a_255_n75# a_447_n75# 0.08fF
+C33 a_n513_n75# a_n417_n75# 0.22fF
+C34 a_n33_n75# a_63_n75# 0.22fF
+C35 a_639_n75# a_735_n75# 0.22fF
+C36 a_159_n75# a_n33_n75# 0.08fF
+C37 a_351_n75# a_639_n75# 0.05fF
+C38 a_n897_n75# a_n513_n75# 0.03fF
+C39 a_n321_n75# a_n417_n75# 0.22fF
+C40 a_255_n75# a_351_n75# 0.22fF
+C41 a_159_n75# a_63_n75# 0.22fF
+C42 a_639_n75# a_831_n75# 0.08fF
+C43 a_735_n75# a_447_n75# 0.05fF
+C44 a_351_n75# a_447_n75# 0.22fF
+C45 a_n989_n75# a_n897_n75# 0.22fF
+C46 a_n225_n75# a_n129_n75# 0.22fF
+C47 a_639_n75# a_543_n75# 0.22fF
+C48 a_n705_n75# a_n513_n75# 0.08fF
+C49 a_831_n75# a_447_n75# 0.03fF
+C50 a_n225_n75# a_n513_n75# 0.05fF
+C51 a_255_n75# a_543_n75# 0.05fF
+C52 a_351_n75# a_735_n75# 0.03fF
+C53 a_543_n75# a_447_n75# 0.22fF
+C54 a_639_n75# a_927_n75# 0.05fF
+C55 a_n705_n75# a_n321_n75# 0.03fF
+C56 a_n129_n75# a_n33_n75# 0.22fF
+C57 a_n225_n75# a_n321_n75# 0.22fF
+C58 a_n705_n75# a_n989_n75# 0.05fF
+C59 a_n609_n75# a_n513_n75# 0.22fF
+C60 a_n705_n75# a_n417_n75# 0.05fF
+C61 a_735_n75# a_831_n75# 0.22fF
+C62 a_n225_n75# a_n417_n75# 0.08fF
+C63 a_n129_n75# a_63_n75# 0.08fF
+C64 a_n609_n75# a_n321_n75# 0.05fF
+C65 a_255_n75# a_n33_n75# 0.05fF
+C66 a_n705_n75# a_n897_n75# 0.08fF
+C67 a_543_n75# a_735_n75# 0.08fF
+C68 a_351_n75# a_543_n75# 0.08fF
+C69 a_n129_n75# a_159_n75# 0.05fF
+C70 a_n989_n75# a_n609_n75# 0.03fF
+C71 a_n33_n75# a_n321_n75# 0.05fF
+C72 a_n801_n75# a_n513_n75# 0.05fF
+C73 a_n609_n75# a_n417_n75# 0.08fF
+C74 a_255_n75# a_63_n75# 0.08fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_255_n150# a_543_n150# 0.10fF
+C1 a_63_n150# a_n33_n150# 0.43fF
+C2 a_159_n150# a_447_n150# 0.10fF
+C3 a_639_n150# a_543_n150# 0.43fF
+C4 a_n513_n150# a_n129_n150# 0.07fF
+C5 a_n225_n150# a_n609_n150# 0.07fF
+C6 a_n989_n150# a_n801_n150# 0.16fF
+C7 a_159_n150# a_n225_n150# 0.07fF
+C8 a_639_n150# a_831_n150# 0.16fF
+C9 a_n897_n150# a_n801_n150# 0.43fF
+C10 a_159_n150# a_n129_n150# 0.10fF
+C11 a_255_n150# a_159_n150# 0.43fF
+C12 a_159_n150# a_n33_n150# 0.16fF
+C13 a_n417_n150# a_n801_n150# 0.07fF
+C14 a_351_n150# a_447_n150# 0.43fF
+C15 a_735_n150# a_927_n150# 0.16fF
+C16 a_n321_n150# a_63_n150# 0.07fF
+C17 a_n417_n150# a_n225_n150# 0.16fF
+C18 a_735_n150# a_543_n150# 0.16fF
+C19 a_n705_n150# a_n321_n150# 0.07fF
+C20 a_255_n150# a_351_n150# 0.43fF
+C21 a_n417_n150# a_n129_n150# 0.10fF
+C22 a_n321_n150# a_n513_n150# 0.16fF
+C23 a_639_n150# a_351_n150# 0.10fF
+C24 a_543_n150# a_927_n150# 0.07fF
+C25 a_735_n150# a_831_n150# 0.43fF
+C26 a_351_n150# a_n33_n150# 0.07fF
+C27 a_n417_n150# a_n33_n150# 0.07fF
+C28 a_n321_n150# a_n609_n150# 0.10fF
+C29 a_255_n150# a_447_n150# 0.16fF
+C30 a_n705_n150# a_n513_n150# 0.16fF
+C31 a_927_n150# a_831_n150# 0.43fF
+C32 a_639_n150# a_447_n150# 0.16fF
+C33 a_n225_n150# a_n129_n150# 0.43fF
+C34 a_159_n150# a_63_n150# 0.43fF
+C35 a_543_n150# a_831_n150# 0.10fF
+C36 a_n705_n150# a_n609_n150# 0.43fF
+C37 a_n33_n150# a_n225_n150# 0.16fF
+C38 a_159_n150# a_543_n150# 0.07fF
+C39 a_n513_n150# a_n609_n150# 0.43fF
+C40 a_255_n150# a_n129_n150# 0.07fF
+C41 a_639_n150# a_255_n150# 0.07fF
+C42 a_n705_n150# a_n989_n150# 0.10fF
+C43 a_n33_n150# a_n129_n150# 0.43fF
+C44 a_255_n150# a_n33_n150# 0.10fF
+C45 a_735_n150# a_351_n150# 0.07fF
+C46 a_n417_n150# a_n321_n150# 0.43fF
+C47 a_33_n247# a_n927_n247# 0.09fF
+C48 a_n705_n150# a_n897_n150# 0.16fF
+C49 a_n989_n150# a_n609_n150# 0.07fF
+C50 a_351_n150# a_63_n150# 0.10fF
+C51 a_n897_n150# a_n513_n150# 0.07fF
+C52 a_735_n150# a_447_n150# 0.10fF
+C53 a_351_n150# a_543_n150# 0.16fF
+C54 a_n705_n150# a_n417_n150# 0.10fF
+C55 a_n897_n150# a_n609_n150# 0.10fF
+C56 a_n417_n150# a_n513_n150# 0.43fF
+C57 a_n321_n150# a_n225_n150# 0.43fF
+C58 a_447_n150# a_63_n150# 0.07fF
+C59 a_n705_n150# a_n801_n150# 0.43fF
+C60 a_n989_n150# a_n897_n150# 0.43fF
+C61 a_n801_n150# a_n513_n150# 0.10fF
+C62 a_n321_n150# a_n129_n150# 0.16fF
+C63 a_543_n150# a_447_n150# 0.43fF
+C64 a_n417_n150# a_n609_n150# 0.16fF
+C65 a_63_n150# a_n225_n150# 0.10fF
+C66 a_735_n150# a_639_n150# 0.43fF
+C67 a_351_n150# a_159_n150# 0.16fF
+C68 a_n321_n150# a_n33_n150# 0.10fF
+C69 a_n801_n150# a_n609_n150# 0.16fF
+C70 a_63_n150# a_n129_n150# 0.16fF
+C71 a_n225_n150# a_n513_n150# 0.10fF
+C72 a_255_n150# a_63_n150# 0.16fF
+C73 a_639_n150# a_927_n150# 0.10fF
+C74 a_447_n150# a_831_n150# 0.07fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n1461_n44# a_n1819_n44# 0.04fF
+C1 a_n29_n44# a_329_n44# 0.04fF
+C2 a_n1103_n44# a_n745_n44# 0.04fF
+C3 a_n387_n44# a_n745_n44# 0.04fF
+C4 a_1045_n44# a_1403_n44# 0.04fF
+C5 a_1761_n44# a_1403_n44# 0.04fF
+C6 a_329_n44# a_687_n44# 0.04fF
+C7 a_687_n44# a_1045_n44# 0.04fF
+C8 a_n1103_n44# a_n1461_n44# 0.04fF
+C9 a_n29_n44# a_n387_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_879_n150# a_1167_n150# 0.10fF
+C1 a_n1041_n150# a_n1137_n150# 0.43fF
+C2 a_n273_n150# a_111_n150# 0.07fF
+C3 a_111_n150# a_15_n150# 0.43fF
+C4 a_n753_n150# a_n465_n150# 0.10fF
+C5 a_n849_n150# a_n1229_n150# 0.07fF
+C6 a_n561_n150# a_n369_n150# 0.16fF
+C7 w_n1367_n369# a_1167_n150# 0.14fF
+C8 a_975_n150# a_879_n150# 0.43fF
+C9 a_111_n150# a_n81_n150# 0.16fF
+C10 a_591_n150# a_687_n150# 0.43fF
+C11 a_783_n150# a_1071_n150# 0.10fF
+C12 a_975_n150# w_n1367_n369# 0.05fF
+C13 a_n1137_n150# a_n849_n150# 0.10fF
+C14 a_495_n150# a_303_n150# 0.16fF
+C15 a_111_n150# a_303_n150# 0.16fF
+C16 a_111_n150# a_n177_n150# 0.10fF
+C17 a_n465_n150# a_n369_n150# 0.43fF
+C18 a_n945_n150# a_n1229_n150# 0.10fF
+C19 a_879_n150# w_n1367_n369# 0.04fF
+C20 a_n753_n150# a_n369_n150# 0.07fF
+C21 a_n945_n150# a_n1137_n150# 0.16fF
+C22 a_591_n150# a_495_n150# 0.43fF
+C23 a_687_n150# a_1071_n150# 0.07fF
+C24 a_783_n150# a_687_n150# 0.43fF
+C25 a_207_n150# a_399_n150# 0.16fF
+C26 a_207_n150# a_15_n150# 0.16fF
+C27 a_n657_n150# a_n1041_n150# 0.07fF
+C28 a_207_n150# a_n81_n150# 0.10fF
+C29 a_495_n150# a_783_n150# 0.10fF
+C30 a_n273_n150# a_n657_n150# 0.07fF
+C31 a_591_n150# a_975_n150# 0.07fF
+C32 a_15_n150# a_399_n150# 0.07fF
+C33 a_n753_n150# a_n1137_n150# 0.07fF
+C34 a_207_n150# a_303_n150# 0.43fF
+C35 a_n657_n150# a_n849_n150# 0.16fF
+C36 a_207_n150# a_n177_n150# 0.07fF
+C37 a_n1041_n150# a_n849_n150# 0.16fF
+C38 a_n273_n150# a_15_n150# 0.10fF
+C39 a_495_n150# a_687_n150# 0.16fF
+C40 a_1071_n150# a_1167_n150# 0.43fF
+C41 a_399_n150# a_303_n150# 0.43fF
+C42 a_n273_n150# a_n81_n150# 0.16fF
+C43 a_591_n150# a_879_n150# 0.10fF
+C44 a_15_n150# a_n81_n150# 0.43fF
+C45 a_207_n150# a_591_n150# 0.07fF
+C46 a_783_n150# a_1167_n150# 0.07fF
+C47 a_975_n150# a_1071_n150# 0.43fF
+C48 a_n657_n150# a_n945_n150# 0.10fF
+C49 a_n945_n150# a_n1041_n150# 0.43fF
+C50 a_15_n150# a_303_n150# 0.10fF
+C51 a_783_n150# a_975_n150# 0.16fF
+C52 a_n273_n150# a_n177_n150# 0.43fF
+C53 a_15_n150# a_n177_n150# 0.16fF
+C54 a_n657_n150# a_n561_n150# 0.43fF
+C55 a_303_n150# a_n81_n150# 0.07fF
+C56 a_591_n150# a_399_n150# 0.16fF
+C57 a_n81_n150# a_n177_n150# 0.43fF
+C58 a_879_n150# a_1071_n150# 0.16fF
+C59 a_n945_n150# a_n849_n150# 0.43fF
+C60 a_111_n150# a_495_n150# 0.07fF
+C61 a_n273_n150# a_n561_n150# 0.10fF
+C62 a_783_n150# a_879_n150# 0.43fF
+C63 a_n1137_n150# a_n1229_n150# 0.43fF
+C64 w_n1367_n369# a_1071_n150# 0.07fF
+C65 a_n657_n150# a_n465_n150# 0.16fF
+C66 a_n561_n150# a_n849_n150# 0.10fF
+C67 a_975_n150# a_687_n150# 0.10fF
+C68 a_n657_n150# a_n753_n150# 0.43fF
+C69 a_591_n150# a_303_n150# 0.10fF
+C70 a_n273_n150# a_n465_n150# 0.16fF
+C71 a_n561_n150# a_n177_n150# 0.07fF
+C72 a_783_n150# a_399_n150# 0.07fF
+C73 a_n753_n150# a_n1041_n150# 0.10fF
+C74 a_n465_n150# a_n849_n150# 0.07fF
+C75 a_n465_n150# a_n81_n150# 0.07fF
+C76 a_n945_n150# a_n561_n150# 0.07fF
+C77 a_879_n150# a_687_n150# 0.16fF
+C78 a_n753_n150# a_n849_n150# 0.43fF
+C79 a_n657_n150# a_n369_n150# 0.10fF
+C80 a_n465_n150# a_n177_n150# 0.10fF
+C81 a_399_n150# a_687_n150# 0.10fF
+C82 a_n273_n150# a_n369_n150# 0.43fF
+C83 a_15_n150# a_n369_n150# 0.07fF
+C84 a_495_n150# a_879_n150# 0.07fF
+C85 a_207_n150# a_495_n150# 0.10fF
+C86 a_n561_n150# a_n465_n150# 0.43fF
+C87 a_n945_n150# a_n753_n150# 0.16fF
+C88 a_n81_n150# a_n369_n150# 0.10fF
+C89 a_207_n150# a_111_n150# 0.43fF
+C90 a_975_n150# a_1167_n150# 0.16fF
+C91 a_n753_n150# a_n561_n150# 0.16fF
+C92 a_591_n150# a_783_n150# 0.16fF
+C93 a_495_n150# a_399_n150# 0.43fF
+C94 a_n369_n150# a_n177_n150# 0.16fF
+C95 a_n1041_n150# a_n1229_n150# 0.16fF
+C96 a_111_n150# a_399_n150# 0.10fF
+C97 a_687_n150# a_303_n150# 0.07fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vss vdd nUp Down w_2544_775# out pswitch iref nDown biasp
++ Up w_6648_570#
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 nUp Up 0.15fF
+C1 biasp iref 0.80fF
+C2 vdd out 6.66fF
+C3 nDown nswitch 0.31fF
+C4 vdd nswitch 0.07fF
+C5 biasp nswitch 0.03fF
+C6 pswitch out 4.91fF
+C7 Down nswitch 2.27fF
+C8 pswitch nswitch 0.06fF
+C9 nUp Down 0.25fF
+C10 Up pswitch 0.70fF
+C11 nUp pswitch 5.66fF
+C12 iref nswitch 1.91fF
+C13 Down nDown 0.13fF
+C14 out nswitch 1.28fF
+C15 vdd biasp 2.64fF
+C16 nUp out 0.31fF
+C17 vdd pswitch 3.98fF
+C18 biasp pswitch 3.11fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C1 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C2 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C3 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C4 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C5 m3_n2650_n2600# m3_n2650_n7900# 3.28fF
+C6 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C7 m3_7988_8000# m3_7988_2700# 3.39fF
+C8 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C9 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C10 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C11 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C12 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C13 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C14 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C15 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C16 m3_2669_2700# m3_2669_8000# 3.28fF
+C17 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C18 m3_2669_2700# m3_n2650_2700# 2.73fF
+C19 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C20 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C21 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C22 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C23 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C24 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C25 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
+C26 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C27 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C28 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C29 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C30 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C31 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C32 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C33 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C34 m3_2669_8000# m3_7988_8000# 2.73fF
+C35 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C36 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C37 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C38 m3_2669_8000# m3_n2650_8000# 2.73fF
+C39 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C40 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C41 m3_2669_n13200# m3_7988_n13200# 2.73fF
+C42 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C43 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C44 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C45 m3_2669_n2600# m3_n2650_n2600# 2.73fF
+C46 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C47 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C48 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C49 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C50 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C51 m3_2669_2700# m3_7988_2700# 2.73fF
+C52 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C53 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C54 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C55 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C56 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
+C57 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C58 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C59 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C60 m3_n2650_n2600# m3_n2650_2700# 3.28fF
+C61 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C62 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C63 m3_2669_2700# m3_2669_n2600# 3.28fF
+C64 m3_7988_n2600# m3_7988_2700# 3.39fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_10_n4250# m3_n4309_50# 1.75fF
+C1 c1_n4209_n4150# m3_n4309_50# 38.10fF
+C2 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C3 m3_10_n4250# c1_110_n4150# 81.11fF
+C4 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C5 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C6 c1_n4209_n4150# c1_110_n4150# 1.32fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 in out 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C1 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C2 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C3 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C4 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C5 m3_n2150_2200# m3_n6469_2200# 1.75fF
+C6 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C7 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C8 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C9 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C10 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C11 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C12 m3_n2150_2200# m3_n2150_n2100# 2.63fF
+C13 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C14 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C15 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C16 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C17 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C18 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_30_n300# a_n88_n300# 0.61fF
+C1 a_n118_n388# a_n88_n300# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in cap3_loop_filter_0/in 0.79fF
+C1 in D0_cap 0.07fF
+C2 in vc_pex 0.18fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS w_n311_n338# a_81_n156# a_111_n125# a_15_n125#
++ a_n173_n125# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n338# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_81_n156# a_n15_n156# 0.02fF
+C1 a_15_n125# a_n81_n125# 0.36fF
+C2 a_111_n125# a_15_n125# 0.36fF
+C3 a_n173_n125# a_15_n125# 0.13fF
+C4 a_111_n125# a_n81_n125# 0.13fF
+C5 a_n111_n156# a_n15_n156# 0.02fF
+C6 a_n173_n125# a_n81_n125# 0.36fF
+C7 a_111_n125# a_n173_n125# 0.08fF
+C8 a_111_n125# VSUBS 0.03fF
+C9 a_15_n125# VSUBS 0.03fF
+C10 a_n81_n125# VSUBS 0.03fF
+C11 a_n173_n125# VSUBS 0.03fF
+C12 a_81_n156# VSUBS 0.05fF
+C13 a_n15_n156# VSUBS 0.05fF
+C14 a_n111_n156# VSUBS 0.05fF
+C15 w_n311_n338# VSUBS 1.56fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n15_n151# a_n111_n151# 0.02fF
+C1 a_n173_n125# a_n81_n125# 0.36fF
+C2 a_n15_n151# a_81_n151# 0.02fF
+C3 a_111_n125# a_n173_n125# 0.08fF
+C4 a_111_n125# a_n81_n125# 0.13fF
+C5 a_n173_n125# a_15_n125# 0.13fF
+C6 a_n81_n125# a_15_n125# 0.36fF
+C7 a_111_n125# a_15_n125# 0.36fF
+C8 a_111_n125# w_n311_n335# 0.04fF
+C9 a_15_n125# w_n311_n335# 0.04fF
+C10 a_n81_n125# w_n311_n335# 0.04fF
+C11 a_n173_n125# w_n311_n335# 0.04fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# vss m1_45_n513# vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd vss m1_187_n605# m1_45_n513# m1_45_n513#
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_187_n605# vdd 0.55fF
+C1 m1_187_n605# m1_45_n513# 0.36fF
+C2 m1_45_n513# vdd 0.69fF
+C3 m1_187_n605# vss 0.73fF
+C4 m1_45_n513# vss 1.10fF
+C5 vdd vss 2.55fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n311_n344# a_n173_n125# 0.14fF
+C1 a_n81_n125# a_111_n125# 0.13fF
+C2 a_15_n125# a_n173_n125# 0.13fF
+C3 a_15_n125# w_n311_n344# 0.09fF
+C4 a_n173_n125# a_111_n125# 0.08fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 w_n311_n344# a_111_n125# 0.14fF
+C7 w_n311_n344# a_n81_n125# 0.09fF
+C8 a_15_n125# a_111_n125# 0.36fF
+C9 a_15_n125# a_n81_n125# 0.36fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n173_n125# 0.08fF
+C1 a_111_n125# a_n81_n125# 0.13fF
+C2 a_15_n125# a_n173_n125# 0.13fF
+C3 a_15_n125# a_n81_n125# 0.36fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 in out 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d vss inverter_cp_x1_0/out vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd CLK_d 0.03fF
+C1 inverter_cp_x1_0/out vdd 0.21fF
+C2 CLK inverter_cp_x1_2/in 0.31fF
+C3 nCLK_d inverter_cp_x1_0/out 0.11fF
+C4 inverter_cp_x1_2/in CLK_d 0.12fF
+C5 inverter_cp_x1_0/out CLK 0.31fF
+C6 nCLK_d vdd 0.03fF
+C7 CLK vdd 0.36fF
+C8 vdd inverter_cp_x1_2/in 0.21fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.69fF
+C12 CLK vss 3.03fF
+C13 vdd vss 15.46fF
+C14 nCLK_d vss 1.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_63_n95# 0.11fF
+C1 a_n125_n95# a_63_n95# 0.10fF
+C2 w_n263_n314# a_n33_n95# 0.08fF
+C3 a_n33_n95# a_n125_n95# 0.28fF
+C4 w_n263_n314# a_n125_n95# 0.11fF
+C5 a_n33_n95# a_63_n95# 0.28fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n129_n213# a_111_n125# 0.01fF
+C1 a_15_n125# a_n173_n125# 0.13fF
+C2 a_n129_n213# a_n173_n125# 0.02fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_n129_n213# a_15_n125# 0.10fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 a_n173_n125# a_111_n125# 0.08fF
+C8 a_n129_n213# a_n81_n125# 0.10fF
+C9 a_15_n125# a_111_n125# 0.36fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n81_n183# a_n125_n95# 0.16fF
+C1 a_n33_n95# a_n125_n95# 0.88fF
+C2 a_n81_n183# a_n33_n95# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 D Q 0.05fF
+C1 Q nD 0.05fF
+C2 vdd nQ 0.16fF
+C3 nQ m1_657_280# 1.41fF
+C4 D nQ 0.05fF
+C5 nQ Q 0.93fF
+C6 nQ nD 0.05fF
+C7 m1_657_280# CLK 0.24fF
+C8 vdd Q 0.16fF
+C9 Q m1_657_280# 0.94fF
+C10 D vss 0.53fF
+C11 m1_657_280# vss 1.88fF
+C12 nD vss 0.16fF
+C13 CLK vss 0.87fF
+C14 Q vss -0.55fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vdd vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ nCLK latch_diff_0/nD Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D
++ CLK clock_inverter_0/inverter_cp_x1_0/out
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C1 latch_diff_1/D vdd 0.01fF
+C2 latch_diff_1/nD nQ 0.08fF
+C3 latch_diff_0/nD vdd 0.14fF
+C4 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
+C5 latch_diff_0/D latch_diff_0/m1_657_280# 0.37fF
+C6 latch_diff_0/nD latch_diff_1/D 0.41fF
+C7 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
+C8 latch_diff_0/D vdd 0.09fF
+C9 latch_diff_0/D latch_diff_1/D 0.11fF
+C10 latch_diff_1/nD vdd 0.02fF
+C11 latch_diff_1/nD latch_diff_1/D 0.33fF
+C12 latch_diff_1/nD Q 0.01fF
+C13 latch_diff_0/D latch_diff_1/nD 0.04fF
+C14 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C15 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C16 latch_diff_1/D nQ 0.11fF
+C17 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C18 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C19 latch_diff_1/m1_657_280# vss 0.64fF
+C20 nCLK vss 0.83fF
+C21 Q vss -0.92fF
+C22 nQ vss 0.57fF
+C23 latch_diff_0/m1_657_280# vss 0.69fF
+C24 CLK vss 0.83fF
+C25 latch_diff_1/D vss -0.33fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.63fF
+C30 D vss 3.27fF
+C31 vdd vss 31.85fF
+C32 latch_diff_0/nD vss 1.53fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_159_n84# w_n359_n303# 0.08fF
+C1 a_159_n84# a_n33_n84# 0.09fF
+C2 a_159_n84# a_n129_n84# 0.05fF
+C3 a_63_n84# w_n359_n303# 0.06fF
+C4 a_63_n84# a_n33_n84# 0.24fF
+C5 a_63_n84# a_n129_n84# 0.09fF
+C6 a_159_n84# a_n221_n84# 0.04fF
+C7 a_63_n84# a_n221_n84# 0.05fF
+C8 a_159_n84# a_63_n84# 0.24fF
+C9 a_n159_n110# a_n63_n110# 0.02fF
+C10 a_n33_n84# w_n359_n303# 0.05fF
+C11 a_n129_n84# w_n359_n303# 0.06fF
+C12 a_n33_n84# a_n129_n84# 0.24fF
+C13 a_33_n110# a_n63_n110# 0.02fF
+C14 a_n221_n84# w_n359_n303# 0.08fF
+C15 a_n33_n84# a_n221_n84# 0.09fF
+C16 a_n129_n84# a_n221_n84# 0.24fF
+C17 a_129_n110# a_33_n110# 0.02fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_63_n42# a_159_n42# 0.12fF
+C2 a_n129_n42# a_159_n42# 0.03fF
+C3 a_n221_n42# a_n33_n42# 0.05fF
+C4 a_n63_n68# a_n159_n68# 0.02fF
+C5 a_33_n68# a_129_n68# 0.02fF
+C6 a_63_n42# a_n33_n42# 0.12fF
+C7 a_n221_n42# a_63_n42# 0.03fF
+C8 a_n33_n42# a_n129_n42# 0.12fF
+C9 a_n221_n42# a_n129_n42# 0.12fF
+C10 a_n33_n42# a_159_n42# 0.05fF
+C11 a_n221_n42# a_159_n42# 0.02fF
+C12 a_63_n42# a_n129_n42# 0.05fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 in vdd 0.33fF
+C1 vdd out 0.62fF
+C2 in out 0.67fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n42# a_63_n42# 0.12fF
+C1 a_n125_n42# a_63_n42# 0.05fF
+C2 a_n63_n68# a_33_n68# 0.02fF
+C3 a_n33_n42# a_n125_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n125_n84# a_n33_n84# 0.24fF
+C1 a_63_n84# a_n33_n84# 0.24fF
+C2 a_n125_n84# a_63_n84# 0.09fF
+C3 w_n263_n303# a_n33_n84# 0.07fF
+C4 a_n125_n84# w_n263_n303# 0.10fF
+C5 a_33_n110# a_n63_n110# 0.02fF
+C6 w_n263_n303# a_63_n84# 0.10fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 in vdd 0.01fF
+C1 vdd out 0.15fF
+C2 in out 0.30fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vdd vss nout_div CLK_2 nCLK_2 o1 o2 CLK out_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD
++ out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 o1 CLK_2 0.11fF
+C1 vdd DFlipFlop_0/CLK 0.40fF
+C2 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C3 nout_div out_div 0.22fF
+C4 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C5 vdd DFlipFlop_0/nCLK 0.30fF
+C6 vdd nCLK_2 0.08fF
+C7 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C8 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C9 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C10 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
+C11 o1 vdd 0.14fF
+C12 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C13 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C14 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C15 vdd out_div 0.03fF
+C16 DFlipFlop_0/latch_diff_0/D DFlipFlop_0/nCLK 0.13fF
+C17 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C18 o2 vdd 0.14fF
+C19 vdd CLK_2 0.08fF
+C20 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C21 vdd nout_div 0.16fF
+C22 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C23 nout_div DFlipFlop_0/CLK 0.42fF
+C24 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/CLK -0.48fF
+C25 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C26 DFlipFlop_0/latch_diff_0/nD nout_div 0.07fF
+C27 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C28 o2 nCLK_2 0.11fF
+C29 nout_div DFlipFlop_0/nCLK 0.43fF
+C30 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
+C31 o1 out_div 0.01fF
+C32 DFlipFlop_0/latch_diff_0/D nout_div 0.09fF
+C33 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C34 CLK_2 vss 1.08fF
+C35 o1 vss 2.21fF
+C36 nCLK_2 vss 1.08fF
+C37 o2 vss 2.21fF
+C38 DFlipFlop_0/CLK vss 1.03fF
+C39 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C40 clock_inverter_0/inverter_cp_x1_0/out vss 1.64fF
+C41 CLK vss 3.27fF
+C42 DFlipFlop_0/nCLK vss 1.55fF
+C43 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C46 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C47 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C48 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.59fF
+C51 nout_div vss 4.41fF
+C52 vdd vss 62.89fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+.ends
+
+.subckt trans_gate_mux2to8 in vss out en_pos en_neg vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vdd en_neg in out out en_neg en_neg in sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 en_pos vss en_pos in out out en_pos in sky130_fd_pr__nfet_01v8_BHR94T
+C0 in en_neg 0.28fF
+C1 out en_neg 0.07fF
+C2 en_pos en_neg 0.04fF
+C3 out in 0.36fF
+C4 en_pos in 0.07fF
+C5 out en_pos 0.27fF
+C6 vdd in 0.05fF
+C7 out vdd 0.27fF
+C8 vdd vss 2.08fF
+C9 in vss 1.12fF
+C10 out vss 0.87fF
+C11 en_pos vss 0.29fF
+C12 en_neg vss 0.31fF
+.ends
+
+.subckt mux2to1 vss select_0_neg out_a_0 out_a_1 select_0 vdd in_a
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 select_0_neg select_0 0.17fF
+C1 select_0_neg in_a 0.11fF
+C2 vdd out_a_0 0.06fF
+C3 vdd out_a_1 0.06fF
+C4 select_0_neg out_a_0 0.05fF
+C5 in_a select_0 0.31fF
+C6 out_a_1 select_0 0.14fF
+C7 in_a out_a_0 0.08fF
+C8 in_a out_a_1 0.08fF
+C9 vdd in_a 0.02fF
+C10 out_a_1 vss 0.99fF
+C11 vdd vss 4.78fF
+C12 in_a vss 2.00fF
+C13 out_a_0 vss 0.99fF
+C14 select_0_neg vss 1.15fF
+C15 select_0 vss 0.97fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 B a_194_125# 0.57fF
+C1 VPWR a_355_368# 0.37fF
+C2 VPWR X 0.07fF
+C3 VPWR VGND 0.01fF
+C4 A a_355_368# 0.02fF
+C5 A VGND 0.31fF
+C6 VPWR a_194_125# 0.33fF
+C7 X a_355_368# 0.17fF
+C8 a_158_392# a_194_125# 0.06fF
+C9 VGND X 0.28fF
+C10 B VPWR 0.09fF
+C11 A a_194_125# 0.18fF
+C12 VPWR VPB 0.06fF
+C13 a_194_125# a_355_368# 0.51fF
+C14 a_194_125# X 0.29fF
+C15 B A 0.28fF
+C16 VGND a_194_125# 0.25fF
+C17 B a_355_368# 0.08fF
+C18 B X 0.13fF
+C19 B VGND 0.10fF
+C20 VPWR A 0.15fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 VPWR VPB 0.04fF
+C1 B a_56_136# 0.30fF
+C2 A a_56_136# 0.17fF
+C3 VGND a_56_136# 0.06fF
+C4 a_56_136# X 0.26fF
+C5 B VPWR 0.02fF
+C6 A VPWR 0.07fF
+C7 VPWR X 0.20fF
+C8 B A 0.08fF
+C9 VGND B 0.03fF
+C10 VGND A 0.21fF
+C11 B X 0.02fF
+C12 VGND X 0.15fF
+C13 VPWR a_56_136# 0.57fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VPWR VPB 0.04fF
+C1 a_63_368# a_152_368# 0.03fF
+C2 VPWR A 0.05fF
+C3 X VGND 0.16fF
+C4 B VGND 0.11fF
+C5 X VPWR 0.18fF
+C6 B VPWR 0.01fF
+C7 a_63_368# VGND 0.27fF
+C8 X A 0.02fF
+C9 a_63_368# VPWR 0.29fF
+C10 B A 0.10fF
+C11 a_63_368# A 0.28fF
+C12 a_63_368# X 0.33fF
+C13 a_63_368# B 0.14fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_2/latch_diff_0/nD vss
++ Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in CLK DFlipFlop_0/Q vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ DFlipFlop_3/latch_diff_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/nD DFlipFlop_2/latch_diff_0/m1_657_280# CLK_5 Q1_shift
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D DFlipFlop_1/D nQ0 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/latch_diff_1/nD Q0 DFlipFlop_0/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_0/latch_diff_0/nD DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/D
++ DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_152_368# sky130_fd_sc_hs__and2_1_1/a_56_136#
++ DFlipFlop_3/nQ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 nCLK DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ nCLK DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vdd vss DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ CLK DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C1 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C2 vdd CLK_5 0.15fF
+C3 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C4 DFlipFlop_3/nQ CLK 0.01fF
+C5 CLK Q0 0.08fF
+C6 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
+C7 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C8 Q1 nCLK -0.01fF
+C9 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C10 Q1 DFlipFlop_3/nQ 0.10fF
+C11 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
+C12 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
+C13 Q1 Q0 9.65fF
+C14 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C15 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C16 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C17 CLK nQ0 0.19fF
+C18 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C19 sky130_fd_sc_hs__and2_1_1/a_56_136# CLK 0.06fF
+C20 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C21 Q1 nQ0 0.06fF
+C22 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C23 nCLK DFlipFlop_1/latch_diff_1/nD 0.16fF
+C24 vdd DFlipFlop_1/D 0.25fF
+C25 Q1 DFlipFlop_0/D 0.13fF
+C26 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C27 DFlipFlop_3/nQ nCLK 0.02fF
+C28 nCLK Q0 0.20fF
+C29 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C30 CLK nQ2 0.17fF
+C31 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C32 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C33 DFlipFlop_0/latch_diff_0/D Q0 0.42fF
+C34 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C35 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C36 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C37 Q1 nQ2 0.07fF
+C38 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C39 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C40 nCLK nQ0 0.09fF
+C41 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C42 nQ0 Q0 0.33fF
+C43 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C44 DFlipFlop_0/Q CLK 0.08fF
+C45 DFlipFlop_2/D CLK 0.14fF
+C46 DFlipFlop_0/D Q0 0.39fF
+C47 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C48 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C49 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C50 Q1 DFlipFlop_0/Q 0.13fF
+C51 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C52 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C53 Q1 DFlipFlop_2/D 0.10fF
+C54 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C55 nCLK nQ2 0.10fF
+C56 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C57 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C58 nQ2 Q0 0.23fF
+C59 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C60 DFlipFlop_1/latch_diff_0/nD CLK 0.08fF
+C61 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_1/D 0.03fF
+C62 DFlipFlop_2/nQ CLK 0.13fF
+C63 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
+C64 Q1_shift vdd 0.10fF
+C65 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C66 Q1 DFlipFlop_2/nQ 0.31fF
+C67 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C68 DFlipFlop_0/Q nCLK 0.11fF
+C69 nQ2 nQ0 0.03fF
+C70 DFlipFlop_2/D nCLK 0.41fF
+C71 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C72 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C73 DFlipFlop_0/Q Q0 0.21fF
+C74 DFlipFlop_2/D Q0 0.25fF
+C75 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C76 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C77 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C78 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C79 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C80 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C81 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C82 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C83 DFlipFlop_2/nQ nCLK 0.09fF
+C84 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C85 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C86 vdd CLK 0.41fF
+C87 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
+C88 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
+C89 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C90 Q1 vdd 9.49fF
+C91 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C92 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C93 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C94 DFlipFlop_0/Q nQ2 0.09fF
+C95 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C96 DFlipFlop_1/D CLK 0.21fF
+C97 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C98 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C99 Q1 DFlipFlop_1/D 0.03fF
+C100 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C101 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C102 nCLK sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.11fF
+C103 nCLK vdd 0.34fF
+C104 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C105 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C106 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C107 DFlipFlop_3/nQ vdd 0.02fF
+C108 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C109 vdd Q0 5.33fF
+C110 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C111 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C112 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C113 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C114 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q0 0.42fF
+C115 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C116 nCLK DFlipFlop_1/D 0.14fF
+C117 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
+C118 vdd nQ0 0.11fF
+C119 DFlipFlop_1/D Q0 0.07fF
+C120 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C121 sky130_fd_sc_hs__and2_1_1/a_56_136# vdd 0.04fF
+C122 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C123 vdd DFlipFlop_0/D 0.19fF
+C124 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C125 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C126 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C127 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C128 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C129 DFlipFlop_1/D nQ0 0.12fF
+C130 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C131 vdd nQ2 0.04fF
+C132 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C133 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C134 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C135 Q1 Q1_shift 0.36fF
+C136 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C137 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C138 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C139 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
+C140 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C141 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C142 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.08fF
+C143 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C144 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
+C145 DFlipFlop_2/D vdd 0.07fF
+C146 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C147 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
+C148 DFlipFlop_1/latch_diff_1/m1_657_280# nQ0 0.21fF
+C149 DFlipFlop_3/nQ Q1_shift 0.04fF
+C150 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C151 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C152 Q1 CLK -0.10fF
+C153 DFlipFlop_2/nQ vdd 0.02fF
+C154 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C155 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C156 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/nQ vss 0.52fF
+C164 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.64fF
+C170 Q1 vss 8.55fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C172 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C173 Q0 vss 0.53fF
+C174 nQ0 vss 3.42fF
+C175 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C176 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C177 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C178 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C179 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C180 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.58fF
+C181 DFlipFlop_1/D vss 3.72fF
+C182 DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C183 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C184 DFlipFlop_2/nQ vss 0.50fF
+C185 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C186 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C187 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C188 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C190 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C191 DFlipFlop_2/D vss 5.34fF
+C192 DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C193 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C194 nCLK vss 0.89fF
+C195 DFlipFlop_0/Q vss -0.94fF
+C196 nQ2 vss 2.05fF
+C197 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C198 CLK vss 0.07fF
+C199 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C200 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 vdd vss 144.09fF
+C206 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt mux2to4 vss out_b_1 vdd select_0 select_0_neg out_a_0 out_a_1 out_b_0 in_a
++ in_b
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_b vss out_b_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_3 in_b vss out_b_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 out_a_0 in_a 0.08fF
+C1 out_b_0 in_a 0.11fF
+C2 out_b_1 in_b 0.08fF
+C3 out_b_0 select_0 0.03fF
+C4 out_b_0 out_a_1 0.88fF
+C5 out_b_0 in_b 0.08fF
+C6 in_a vdd 0.02fF
+C7 select_0 vdd 0.02fF
+C8 out_a_1 vdd 0.06fF
+C9 select_0_neg out_a_0 0.05fF
+C10 select_0_neg out_b_0 -0.13fF
+C11 in_b vdd 0.02fF
+C12 select_0 in_a 0.31fF
+C13 out_a_1 in_a 0.08fF
+C14 out_a_1 select_0 0.18fF
+C15 in_b select_0 0.24fF
+C16 out_a_1 in_b 0.08fF
+C17 select_0_neg vdd 0.02fF
+C18 select_0_neg in_a 0.22fF
+C19 out_b_1 vdd 0.06fF
+C20 select_0_neg select_0 0.49fF
+C21 select_0_neg out_a_1 0.12fF
+C22 out_a_0 vdd 0.06fF
+C23 out_b_0 vdd 0.06fF
+C24 select_0_neg in_b 0.10fF
+C25 out_b_1 select_0 0.14fF
+C26 out_b_1 vss 0.99fF
+C27 in_b vss 2.00fF
+C28 out_b_0 vss 0.93fF
+C29 out_a_1 vss 0.22fF
+C30 vdd vss 9.53fF
+C31 in_a vss 2.00fF
+C32 out_a_0 vss 0.99fF
+C33 select_0_neg vss 2.56fF
+C34 select_0 vss 2.23fF
+.ends
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X a_304_74# a_443_74# a_524_368#
++ a_27_112#
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 A0 S 0.04fF
+C1 VGND VPWR 0.02fF
+C2 X VPWR 0.28fF
+C3 a_304_74# a_443_74# 0.12fF
+C4 A1 A0 0.31fF
+C5 A0 a_27_112# 0.07fF
+C6 A1 S 0.10fF
+C7 a_304_74# VPWR 0.13fF
+C8 X VGND 0.11fF
+C9 S a_27_112# 0.22fF
+C10 a_304_74# VGND 0.58fF
+C11 a_304_74# a_223_368# 0.05fF
+C12 X a_304_74# 0.29fF
+C13 a_524_368# a_27_112# 0.06fF
+C14 a_304_74# a_226_74# 0.08fF
+C15 A1 a_27_112# 0.18fF
+C16 S VPWR 0.05fF
+C17 VPB a_27_112# 0.01fF
+C18 VGND A0 0.02fF
+C19 VGND S 0.07fF
+C20 a_304_74# A0 0.23fF
+C21 a_304_74# S 0.18fF
+C22 A1 a_443_74# 0.07fF
+C23 A1 VPWR 0.01fF
+C24 VPWR a_27_112# 0.99fF
+C25 A1 VGND 0.09fF
+C26 VGND a_27_112# 0.18fF
+C27 X A1 0.02fF
+C28 a_27_112# a_223_368# 0.09fF
+C29 X a_27_112# 0.08fF
+C30 A1 a_304_74# 0.69fF
+C31 a_304_74# a_27_112# 0.58fF
+C32 VPB VPWR 0.06fF
+C33 VGND VNB 0.88fF
+C34 X VNB 0.25fF
+C35 VPWR VNB 0.89fF
+C36 A1 VNB 0.37fF
+C37 A0 VNB 0.23fF
+C38 S VNB 0.34fF
+C39 VPB VNB 0.87fF
+C40 a_304_74# VNB 0.36fF
+C41 a_27_112# VNB 0.65fF
+.ends
+
+.subckt prescaler_23 nCLK vss DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_2/latch_diff_0/nD
++ vdd DFlipFlop_2/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out CLK_23 DFlipFlop_2/latch_diff_0/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_0/latch_diff_0/nD MC DFlipFlop_2/latch_diff_0/D
++ Q2
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1_0/a_304_74# sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__mux2_1_0/a_524_368#
++ sky130_fd_sc_hs__mux2_1_0/a_27_112# sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vdd vss DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ nCLK DFlipFlop_0/latch_diff_0/nD
++ Q1 DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_0/D
++ CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vdd vss DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK_23 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q2 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vdd vss DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ CLK DFlipFlop_2/latch_diff_0/nD
++ Q2_d DFlipFlop_2/latch_diff_1/nD Q2 DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/latch_diff_0/D
++ nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1_0/a_143_136# sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1_1/a_152_368#
++ sky130_fd_sc_hs__or2_1_1/a_63_368# sky130_fd_sc_hs__or2_1
+C0 CLK sky130_fd_sc_hs__or2_1_0/X 0.01fF
+C1 MC sky130_fd_sc_hs__or2_1_0/X 0.09fF
+C2 nCLK_23 DFlipFlop_0/nQ 0.05fF
+C3 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q2 0.38fF
+C4 nCLK DFlipFlop_1/D 0.16fF
+C5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C6 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_524_368# 0.04fF
+C7 CLK Q1 -0.07fF
+C8 nCLK_23 vdd 3.27fF
+C9 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.06fF
+C10 MC Q1 0.29fF
+C11 nCLK DFlipFlop_0/nQ 0.11fF
+C12 CLK_23 vdd 0.16fF
+C13 MC sky130_fd_sc_hs__mux2_1_0/a_27_112# 0.24fF
+C14 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_443_74# 0.09fF
+C15 CLK sky130_fd_sc_hs__and2_1_0/a_56_136# 0.08fF
+C16 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.31fF
+C17 nCLK_23 nCLK 0.11fF
+C18 nCLK_23 Q2 0.03fF
+C19 nCLK DFlipFlop_1/latch_diff_1/D 0.09fF
+C20 MC CLK 0.08fF
+C21 nCLK vdd -0.55fF
+C22 nCLK_23 sky130_fd_sc_hs__or2_1_1/X 0.26fF
+C23 vdd Q2 1.63fF
+C24 sky130_fd_sc_hs__or2_1_1/X vdd 0.03fF
+C25 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C26 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_443_74# 0.03fF
+C27 nCLK Q2 0.29fF
+C28 nCLK_23 DFlipFlop_0/latch_diff_1/D 0.05fF
+C29 sky130_fd_sc_hs__or2_1_1/a_63_368# Q2 0.09fF
+C30 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.31fF
+C31 sky130_fd_sc_hs__or2_1_1/X Q2 0.24fF
+C32 DFlipFlop_1/D sky130_fd_sc_hs__or2_1_0/X 0.35fF
+C33 nCLK DFlipFlop_2/latch_diff_0/nD 0.09fF
+C34 nCLK DFlipFlop_2/latch_diff_1/D 0.16fF
+C35 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.29fF
+C36 nCLK sky130_fd_sc_hs__or2_1_0/a_63_368# 0.05fF
+C37 DFlipFlop_2/latch_diff_1/D Q2 0.13fF
+C38 nCLK_23 DFlipFlop_0/latch_diff_0/nD 0.12fF
+C39 CLK DFlipFlop_1/latch_diff_1/nD 0.11fF
+C40 nCLK_23 DFlipFlop_0/latch_diff_1/nD 0.02fF
+C41 nCLK DFlipFlop_2/nQ 0.02fF
+C42 nCLK_23 sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C43 DFlipFlop_2/nQ Q2 0.13fF
+C44 nCLK DFlipFlop_2/latch_diff_1/nD 0.12fF
+C45 vdd sky130_fd_sc_hs__or2_1_0/X 0.03fF
+C46 DFlipFlop_2/latch_diff_0/D Q2 0.30fF
+C47 DFlipFlop_2/latch_diff_1/nD Q2 0.17fF
+C48 nCLK_23 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.49fF
+C49 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.10fF
+C50 nCLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.31fF
+C51 CLK DFlipFlop_1/D 0.40fF
+C52 DFlipFlop_0/nQ Q1 -0.02fF
+C53 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C54 nCLK sky130_fd_sc_hs__or2_1_0/a_152_368# 0.01fF
+C55 nCLK sky130_fd_sc_hs__or2_1_0/X 0.06fF
+C56 DFlipFlop_1/latch_diff_0/D nCLK 0.02fF
+C57 Q2_d vdd 0.02fF
+C58 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.04fF
+C59 nCLK_23 Q1 0.02fF
+C60 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_27_112# 0.07fF
+C61 CLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.05fF
+C62 vdd Q1 0.07fF
+C63 CLK DFlipFlop_0/nQ 0.15fF
+C64 nCLK_23 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C65 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C66 Q2_d Q2 0.66fF
+C67 DFlipFlop_0/latch_diff_1/m1_657_280# Q1 0.06fF
+C68 nCLK_23 CLK 0.22fF
+C69 sky130_fd_sc_hs__or2_1_1/X Q2_d 0.03fF
+C70 MC nCLK_23 4.46fF
+C71 nCLK Q1 -0.02fF
+C72 CLK DFlipFlop_1/latch_diff_1/D 0.18fF
+C73 CLK vdd 0.34fF
+C74 MC vdd 0.88fF
+C75 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.08fF
+C76 Q2_d DFlipFlop_2/latch_diff_1/D 0.03fF
+C77 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.09fF
+C78 MC nCLK 0.01fF
+C79 CLK Q2 0.29fF
+C80 MC Q2 0.18fF
+C81 MC sky130_fd_sc_hs__or2_1_1/X 0.02fF
+C82 DFlipFlop_2/latch_diff_1/m1_657_280# Q2_d 0.03fF
+C83 CLK DFlipFlop_2/latch_diff_1/D 0.09fF
+C84 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.02fF
+C85 CLK DFlipFlop_1/latch_diff_0/nD 0.09fF
+C86 CLK DFlipFlop_0/latch_diff_1/D 0.04fF
+C87 DFlipFlop_2/latch_diff_1/m1_657_280# CLK 0.33fF
+C88 DFlipFlop_0/latch_diff_1/nD Q1 0.03fF
+C89 CLK DFlipFlop_2/nQ 0.02fF
+C90 nCLK DFlipFlop_1/latch_diff_1/nD 0.18fF
+C91 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1 0.01fF
+C92 sky130_fd_sc_hs__or2_1_0/X Q1 0.06fF
+C93 CLK DFlipFlop_2/latch_diff_0/D 0.13fF
+C94 CLK DFlipFlop_2/latch_diff_1/nD 0.19fF
+C95 nCLK_23 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C96 nCLK_23 DFlipFlop_1/D 0.02fF
+C97 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C98 sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C99 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C100 DFlipFlop_1/D vdd 0.07fF
+C101 sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C102 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C103 sky130_fd_sc_hs__or2_1_0/X vss 0.92fF
+C104 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.39fF
+C105 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C106 Q2_d vss -0.22fF
+C107 DFlipFlop_2/nQ vss 0.48fF
+C108 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C109 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C110 DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C111 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C112 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C113 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.63fF
+C114 Q2 vss 1.35fF
+C115 DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C116 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.72fF
+C117 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C118 DFlipFlop_1/latch_diff_1/D vss -1.72fF
+C119 DFlipFlop_1/latch_diff_1/nD vss 0.58fF
+C120 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C121 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C122 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C123 DFlipFlop_1/D vss 2.98fF
+C124 DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C125 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C126 nCLK vss -1.56fF
+C127 Q1 vss 0.50fF
+C128 DFlipFlop_0/nQ vss 0.48fF
+C129 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C130 CLK vss -0.69fF
+C131 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C132 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C133 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C134 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C135 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C136 nCLK_23 vss -0.65fF
+C137 vdd vss 113.67fF
+C138 DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C139 CLK_23 vss -0.57fF
+C140 sky130_fd_sc_hs__or2_1_1/X vss -0.35fF
+C141 MC vss 2.09fF
+C142 sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.41fF
+C143 sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.69fF
+.ends
+
+.subckt freq_div clk_0 vss n_clk_0 vdd s_0 prescaler_23_0/Q2 s_1_n s_1 prescaler_23_0/nCLK_23
++ prescaler_23_0/MC clk_d prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n
++ clk_pre div_by_5_0/DFlipFlop_2/latch_diff_0/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out div_by_5_0/Q1 div_by_5_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD clk_2 in_a in_b clk_5 prescaler_23_0/DFlipFlop_2/latch_diff_0/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD div_by_5_0/DFlipFlop_2/latch_diff_1/D
+Xdiv_by_2_0 vdd vss div_by_2_0/nout_div clk_2 div_by_2_0/nCLK_2 div_by_2_0/o1 div_by_2_0/o2
++ clk_out_mux21 div_by_2_0/out_div div_by_2
+Xmux2to1_0 vss s_0_n clk_pre clk_5 s_0 vdd clk_out_mux21 mux2to1
+Xinverter_min_x4_0 inverter_min_x4_0/in vss clk_d vdd inverter_min_x4
+Xmux2to1_1 vss s_1_n clk_d clk_2 s_1 vdd out mux2to1
+Xinverter_min_x2_0 clk_out_mux21 inverter_min_x4_0/in vss vdd inverter_min_x2
+Xinverter_min_x2_1 s_1 s_1_n vss vdd inverter_min_x2
+Xinverter_min_x2_2 s_0 s_0_n vss vdd inverter_min_x2
+Xdiv_by_5_0 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ vss div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in clk_1
++ div_by_5_0/DFlipFlop_0/Q vdd div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# clk_5 div_by_5_0/Q1_shift div_by_5_0/nQ2
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_by_5_0/DFlipFlop_1/D div_by_5_0/nQ0 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/Q0 div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xmux2to4_0 vss n_clk_1 vdd s_0 s_0_n clk_0 clk_1 n_clk_0 in_a in_b mux2to4
+Xprescaler_23_0 n_clk_0 vss prescaler_23_0/DFlipFlop_0/latch_diff_1/nD prescaler_23_0/nCLK_23
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vdd prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ clk_pre prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# prescaler_23_0/DFlipFlop_0/latch_diff_0/D
++ clk_0 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280#
++ prescaler_23_0/DFlipFlop_0/latch_diff_1/D prescaler_23_0/DFlipFlop_0/latch_diff_0/nD
++ prescaler_23_0/MC prescaler_23_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/Q2 prescaler_23
+C0 clk_1 s_0 1.36fF
+C1 n_clk_1 vdd 0.13fF
+C2 clk_5 vdd 0.04fF
+C3 div_by_5_0/Q0 s_0 0.02fF
+C4 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.02fF
+C5 clk_1 n_clk_0 -0.03fF
+C6 s_0_n div_by_5_0/DFlipFlop_1/D 0.19fF
+C7 n_clk_1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C8 div_by_5_0/DFlipFlop_2/D s_0 0.03fF
+C9 div_by_5_0/Q1_shift div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# -0.02fF
+C10 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out s_0_n -0.29fF
+C11 s_0_n div_by_5_0/nQ2 0.05fF
+C12 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.08fF
+C13 s_0 div_by_5_0/DFlipFlop_2/nQ 0.05fF
+C14 s_0 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.36fF
+C15 s_1_n clk_2 0.59fF
+C16 s_0_n div_by_5_0/nQ0 0.05fF
+C17 div_by_5_0/DFlipFlop_1/latch_diff_1/D s_0_n 0.04fF
+C18 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.04fF
+C19 n_clk_1 in_b 0.05fF
+C20 s_0 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.05fF
+C21 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0_n 0.04fF
+C22 clk_pre clk_out_mux21 1.19fF
+C23 s_0_n div_by_5_0/DFlipFlop_0/Q 0.24fF
+C24 vdd clk_d 0.23fF
+C25 s_0_n div_by_5_0/DFlipFlop_0/D 0.05fF
+C26 s_0 div_by_5_0/Q1 0.04fF
+C27 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_1 0.05fF
+C28 s_0_n clk_out_mux21 0.45fF
+C29 div_by_5_0/DFlipFlop_3/latch_diff_0/D s_0 0.10fF
+C30 s_0 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.12fF
+C31 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_0 0.16fF
+C32 div_by_5_0/Q1_shift s_0_n 0.04fF
+C33 s_0 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.12fF
+C34 div_by_5_0/Q0 n_clk_1 0.01fF
+C35 div_by_5_0/DFlipFlop_1/latch_diff_1/nD s_0 0.02fF
+C36 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.11fF
+C37 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0 0.02fF
+C38 clk_2 vdd 0.02fF
+C39 clk_0 vdd 0.63fF
+C40 clk_pre vdd 0.17fF
+C41 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.11fF
+C42 clk_out_mux21 vdd 0.14fF
+C43 s_1_n out 0.33fF
+C44 s_0_n vdd 2.53fF
+C45 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out s_0 -0.13fF
+C46 s_0_n div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.31fF
+C47 div_by_5_0/DFlipFlop_3/nQ s_0 0.02fF
+C48 clk_0 prescaler_23_0/nCLK_23 0.16fF
+C49 clk_pre prescaler_23_0/nCLK_23 0.03fF
+C50 inverter_min_x4_0/in clk_d 0.11fF
+C51 s_0 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.02fF
+C52 clk_2 out 0.05fF
+C53 s_0_n div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.05fF
+C54 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/D 0.13fF
+C55 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.20fF
+C56 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD clk_0 0.09fF
+C57 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD 0.09fF
+C58 prescaler_23_0/DFlipFlop_0/latch_diff_1/D clk_0 0.13fF
+C59 n_clk_1 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.06fF
+C60 n_clk_1 div_by_5_0/Q1 0.15fF
+C61 s_0 div_by_5_0/DFlipFlop_1/D 0.03fF
+C62 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.11fF
+C63 s_0_n in_b 0.48fF
+C64 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out s_0 -0.19fF
+C65 clk_1 div_by_5_0/DFlipFlop_0/D 0.14fF
+C66 s_0 div_by_5_0/nQ2 0.05fF
+C67 clk_1 s_0_n 4.82fF
+C68 div_by_5_0/nQ0 s_0 0.05fF
+C69 div_by_5_0/Q0 s_0_n 0.24fF
+C70 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.24fF
+C71 clk_1 in_a 0.05fF
+C72 s_1 clk_d 0.22fF
+C73 s_0_n div_by_5_0/DFlipFlop_2/D 0.05fF
+C74 inverter_min_x4_0/in vdd 0.09fF
+C75 div_by_5_0/DFlipFlop_1/latch_diff_1/D s_0 0.05fF
+C76 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.05fF
+C77 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0 0.05fF
+C78 s_1 s_1_n 0.39fF
+C79 s_0 div_by_5_0/DFlipFlop_0/Q 0.02fF
+C80 clk_1 vdd 0.16fF
+C81 s_0 div_by_5_0/DFlipFlop_0/D 0.03fF
+C82 clk_pre s_0 0.21fF
+C83 clk_out_mux21 s_0 0.68fF
+C84 s_0_n div_by_5_0/DFlipFlop_2/nQ 0.04fF
+C85 s_0_n div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.37fF
+C86 s_0_n s_0 7.76fF
+C87 div_by_5_0/Q1_shift s_0 0.05fF
+C88 div_by_5_0/Q0 vdd 0.05fF
+C89 n_clk_0 s_0_n 0.31fF
+C90 n_clk_1 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C91 s_0 in_a 0.30fF
+C92 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.04fF
+C93 div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/D -0.02fF
+C94 s_0_n div_by_5_0/Q1 0.21fF
+C95 s_0 vdd 3.67fF
+C96 div_by_5_0/DFlipFlop_3/latch_diff_0/D s_0_n 0.17fF
+C97 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.20fF
+C98 s_0 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.30fF
+C99 s_0_n div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.20fF
+C100 div_by_5_0/DFlipFlop_1/latch_diff_1/nD s_0_n 0.24fF
+C101 n_clk_0 vdd 0.25fF
+C102 n_clk_0 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C103 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0_n 0.24fF
+C104 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.08fF
+C105 s_0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.12fF
+C106 div_by_5_0/Q1 vdd -0.02fF
+C107 n_clk_1 div_by_5_0/DFlipFlop_0/D 0.21fF
+C108 n_clk_0 prescaler_23_0/nCLK_23 0.16fF
+C109 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.08fF
+C110 clk_5 clk_out_mux21 0.05fF
+C111 div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in -0.06fF
+C112 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out s_0_n -0.01fF
+C113 clk_5 s_0_n 0.56fF
+C114 s_1 out 0.39fF
+C115 div_by_5_0/DFlipFlop_3/nQ s_0_n 0.24fF
+C116 clk_5 div_by_5_0/Q1_shift 0.04fF
+C117 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C118 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD 0.13fF
+C119 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/D 0.09fF
+C120 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C121 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C122 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C123 prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C124 prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C125 prescaler_23_0/Q2_d vss -0.69fF
+C126 prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C127 prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C128 prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C129 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C130 prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C131 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C132 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C133 prescaler_23_0/Q2 vss 0.55fF
+C134 prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C135 prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C136 prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C137 prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C138 prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C139 prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C140 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C141 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C142 prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C143 prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C144 prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C145 n_clk_0 vss -5.35fF
+C146 prescaler_23_0/Q1 vss 0.07fF
+C147 prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C148 prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C149 clk_0 vss 0.66fF
+C150 prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C151 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C152 prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C153 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C155 prescaler_23_0/nCLK_23 vss -1.02fF
+C156 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C157 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C158 prescaler_23_0/MC vss 1.07fF
+C159 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C160 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C161 in_b vss 2.02fF
+C162 in_a vss 2.01fF
+C163 s_0_n vss -2.51fF
+C164 s_0 vss 5.84fF
+C165 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C166 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C167 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C168 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C169 div_by_5_0/Q1_shift vss -0.36fF
+C170 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C171 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C172 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C174 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C177 div_by_5_0/Q1 vss 4.35fF
+C178 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C179 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C180 div_by_5_0/Q0 vss 0.29fF
+C181 div_by_5_0/nQ0 vss 0.99fF
+C182 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C183 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C184 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C185 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C186 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C187 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C188 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C189 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C190 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C191 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C192 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C193 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C194 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C195 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C196 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C197 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C198 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C199 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C200 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C201 n_clk_1 vss -0.55fF
+C202 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C203 div_by_5_0/nQ2 vss 1.38fF
+C204 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C205 clk_1 vss -1.34fF
+C206 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C207 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C208 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C209 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C210 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C211 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C212 vdd vss 344.01fF
+C213 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C214 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C215 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C216 out vss 0.93fF
+C217 clk_d vss 0.78fF
+C218 s_1_n vss 1.22fF
+C219 s_1 vss 2.97fF
+C220 inverter_min_x4_0/in vss 2.77fF
+C221 clk_out_mux21 vss 5.29fF
+C222 clk_pre vss 1.30fF
+C223 clk_2 vss 3.46fF
+C224 div_by_2_0/o1 vss 2.20fF
+C225 div_by_2_0/nCLK_2 vss 1.04fF
+C226 div_by_2_0/o2 vss 2.08fF
+C227 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C228 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C229 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C230 div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C231 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C232 div_by_2_0/out_div vss -0.80fF
+C233 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C234 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C235 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C236 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C237 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C238 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C239 div_by_2_0/nout_div vss 2.62fF
+C240 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n129_n600# a_n257_n777# 0.29fF
+C1 a_n221_n600# a_n257_n777# 0.25fF
+C2 a_n129_n600# a_n221_n600# 7.87fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n129_n300# a_n221_n300# 4.05fF
+C1 a_n257_n404# a_n221_n300# 0.21fF
+C2 a_n257_n404# a_n129_n300# 0.30fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out vdd in vss
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 a_3996_n100# vdd 3.68fF
+C1 in vdd 0.02fF
+C2 vdd a_678_n100# 0.08fF
+C3 a_3996_n100# a_678_n100# 6.52fF
+C4 in a_678_n100# 0.81fF
+C5 vdd out 47.17fF
+C6 a_3996_n100# out 55.19fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n238# a_15_n150# 0.02fF
+C1 a_n33_n238# a_n73_n150# 0.02fF
+C2 a_n73_n150# a_15_n150# 0.51fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n369# a_n73_n150# 0.20fF
+C1 a_n33_181# a_15_n150# 0.01fF
+C2 w_n211_n369# a_n33_181# 0.05fF
+C3 w_n211_n369# a_15_n150# 0.20fF
+C4 a_n33_181# a_n73_n150# 0.01fF
+C5 a_15_n150# a_n73_n150# 0.51fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n465_172# a_n417_n150# 0.10fF
+C1 a_159_n150# a_n465_172# 0.10fF
+C2 a_n465_172# a_63_n150# 0.10fF
+C3 a_n509_n150# a_n321_n150# 0.16fF
+C4 a_n129_n150# a_n321_n150# 0.16fF
+C5 a_n33_n150# a_351_n150# 0.07fF
+C6 a_n465_172# a_447_n150# 0.01fF
+C7 a_255_n150# a_n33_n150# 0.10fF
+C8 a_n225_n150# a_n33_n150# 0.16fF
+C9 a_255_n150# a_351_n150# 0.43fF
+C10 a_n465_172# a_n509_n150# 0.01fF
+C11 a_n33_n150# a_n417_n150# 0.07fF
+C12 a_159_n150# a_n33_n150# 0.16fF
+C13 a_n465_172# a_n129_n150# 0.10fF
+C14 a_159_n150# a_351_n150# 0.16fF
+C15 a_n225_n150# a_n417_n150# 0.16fF
+C16 a_159_n150# a_255_n150# 0.43fF
+C17 a_159_n150# a_n225_n150# 0.07fF
+C18 a_63_n150# a_n33_n150# 0.43fF
+C19 a_63_n150# a_351_n150# 0.10fF
+C20 a_255_n150# a_63_n150# 0.16fF
+C21 a_63_n150# a_n225_n150# 0.10fF
+C22 a_447_n150# a_351_n150# 0.43fF
+C23 a_255_n150# a_447_n150# 0.16fF
+C24 a_n465_172# a_n321_n150# 0.10fF
+C25 a_159_n150# a_63_n150# 0.43fF
+C26 a_n129_n150# a_n33_n150# 0.43fF
+C27 a_159_n150# a_447_n150# 0.10fF
+C28 a_n225_n150# a_n509_n150# 0.10fF
+C29 a_255_n150# a_n129_n150# 0.07fF
+C30 a_n129_n150# a_n225_n150# 0.43fF
+C31 a_63_n150# a_447_n150# 0.07fF
+C32 a_n509_n150# a_n417_n150# 0.43fF
+C33 a_n129_n150# a_n417_n150# 0.10fF
+C34 a_159_n150# a_n129_n150# 0.10fF
+C35 a_n33_n150# a_n321_n150# 0.10fF
+C36 a_n225_n150# a_n321_n150# 0.43fF
+C37 a_n129_n150# a_63_n150# 0.16fF
+C38 a_n321_n150# a_n417_n150# 0.43fF
+C39 a_n465_172# a_n33_n150# 0.10fF
+C40 a_n465_172# a_351_n150# 0.10fF
+C41 a_n465_172# a_255_n150# 0.10fF
+C42 a_n465_172# a_n225_n150# 0.10fF
+C43 a_63_n150# a_n321_n150# 0.07fF
+C44 a_n129_n150# a_n509_n150# 0.07fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n465_n247# a_63_n150# 0.08fF
+C1 a_n321_n150# a_n417_n150# 0.43fF
+C2 a_255_n150# a_n33_n150# 0.10fF
+C3 a_351_n150# a_159_n150# 0.16fF
+C4 w_n647_n369# a_n129_n150# 0.02fF
+C5 w_n647_n369# a_63_n150# 0.02fF
+C6 a_159_n150# a_447_n150# 0.10fF
+C7 a_n129_n150# a_n33_n150# 0.43fF
+C8 a_n321_n150# a_n225_n150# 0.43fF
+C9 a_351_n150# a_447_n150# 0.43fF
+C10 a_n417_n150# a_n129_n150# 0.10fF
+C11 a_n33_n150# a_63_n150# 0.43fF
+C12 a_255_n150# a_159_n150# 0.43fF
+C13 a_255_n150# a_351_n150# 0.43fF
+C14 a_n225_n150# a_n129_n150# 0.43fF
+C15 a_159_n150# a_n129_n150# 0.10fF
+C16 w_n647_n369# a_n509_n150# 0.14fF
+C17 a_n225_n150# a_63_n150# 0.10fF
+C18 a_255_n150# a_447_n150# 0.16fF
+C19 a_159_n150# a_63_n150# 0.43fF
+C20 w_n647_n369# a_n465_n247# 0.47fF
+C21 a_351_n150# a_63_n150# 0.10fF
+C22 a_n465_n247# a_n33_n150# 0.08fF
+C23 a_n417_n150# a_n509_n150# 0.43fF
+C24 a_n465_n247# a_n417_n150# 0.08fF
+C25 a_63_n150# a_447_n150# 0.07fF
+C26 a_n321_n150# a_n129_n150# 0.16fF
+C27 a_n321_n150# a_63_n150# 0.07fF
+C28 a_255_n150# a_n129_n150# 0.07fF
+C29 w_n647_n369# a_n33_n150# 0.02fF
+C30 a_n225_n150# a_n509_n150# 0.10fF
+C31 a_255_n150# a_63_n150# 0.16fF
+C32 w_n647_n369# a_n417_n150# 0.07fF
+C33 a_n465_n247# a_n225_n150# 0.08fF
+C34 a_n465_n247# a_159_n150# 0.08fF
+C35 a_n417_n150# a_n33_n150# 0.07fF
+C36 a_351_n150# a_n465_n247# 0.08fF
+C37 a_n129_n150# a_63_n150# 0.16fF
+C38 w_n647_n369# a_n225_n150# 0.04fF
+C39 w_n647_n369# a_159_n150# 0.04fF
+C40 a_n321_n150# a_n509_n150# 0.16fF
+C41 a_351_n150# w_n647_n369# 0.07fF
+C42 a_n225_n150# a_n33_n150# 0.16fF
+C43 a_n321_n150# a_n465_n247# 0.08fF
+C44 a_159_n150# a_n33_n150# 0.16fF
+C45 a_n225_n150# a_n417_n150# 0.16fF
+C46 a_255_n150# a_n465_n247# 0.08fF
+C47 a_351_n150# a_n33_n150# 0.07fF
+C48 w_n647_n369# a_447_n150# 0.14fF
+C49 a_n321_n150# w_n647_n369# 0.05fF
+C50 a_n129_n150# a_n509_n150# 0.07fF
+C51 a_n465_n247# a_n129_n150# 0.08fF
+C52 a_255_n150# w_n647_n369# 0.05fF
+C53 a_159_n150# a_n225_n150# 0.07fF
+C54 a_n321_n150# a_n33_n150# 0.10fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n73_n11# 0.15fF
+C1 a_n73_n11# a_n33_n99# 0.02fF
+C2 a_15_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# a_20_n114# 0.42fF
+C1 a_20_n114# w_n216_n334# 0.20fF
+C2 a_n78_n114# w_n216_n334# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vdd 0.01fF
+C1 in out 0.11fF
+C2 vbulkp vdd 0.04fF
+C3 in vss 0.01fF
+C4 out vbulkp 0.08fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 vss out vdd inverter_csvco_0/vss
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 inverter_csvco_0/vss in 0.01fF
+C1 in out 0.06fF
+C2 inverter_csvco_0/vss vctrl 0.87fF
+C3 D0 inverter_csvco_0/vss 0.02fF
+C4 in inverter_csvco_0/vdd 0.01fF
+C5 D0 out 0.09fF
+C6 inverter_csvco_0/vss out 0.03fF
+C7 inverter_csvco_0/vdd vbp 0.75fF
+C8 cap_vco_0/t out 0.70fF
+C9 inverter_csvco_0/vdd out 0.02fF
+C10 vdd vbp 1.21fF
+C11 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C12 vdd cap_vco_0/t 0.04fF
+C13 vdd inverter_csvco_0/vdd 1.89fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vss vdd csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 vss
++ csvco_branch_1/in vdd csvco_branch_0/inverter_csvco_0/vss csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 vss out_vco vdd csvco_branch_2/inverter_csvco_0/vss csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 vss csvco_branch_2/in vdd csvco_branch_1/inverter_csvco_0/vss csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C1 vdd csvco_branch_2/vbp 1.49fF
+C2 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C3 out_vco csvco_branch_1/in 0.76fF
+C4 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C5 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
+C6 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C7 vctrl csvco_branch_2/vbp 0.06fF
+C8 out_vco csvco_branch_2/in 0.58fF
+C9 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
+C10 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C11 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C12 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C13 vctrl D0 4.41fF
+C14 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 out_pad out_div 0.15fF
+C1 vdd out_div 0.17fF
+C2 o1 vdd 0.09fF
+C3 out_pad vdd 0.10fF
+C4 o1 out_div 0.11fF
+C5 vdd vss 14.54fF
+C6 in_vco vss 0.83fF
+C7 out_pad vss 0.70fF
+C8 out_div vss 3.00fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n33_n125# a_n225_n125# 0.13fF
+C1 a_n225_n125# a_n129_n125# 0.36fF
+C2 a_n317_n125# a_63_n125# 0.06fF
+C3 a_63_n125# a_159_n125# 0.36fF
+C4 a_225_n151# a_129_n151# 0.02fF
+C5 a_33_n151# a_129_n151# 0.02fF
+C6 a_n33_n125# a_255_n125# 0.08fF
+C7 a_255_n125# a_n129_n125# 0.06fF
+C8 a_n317_n125# a_n225_n125# 0.36fF
+C9 a_63_n125# a_n225_n125# 0.08fF
+C10 a_n33_n125# a_n129_n125# 0.36fF
+C11 a_n225_n125# a_159_n125# 0.06fF
+C12 a_n63_n151# a_n159_n151# 0.02fF
+C13 a_63_n125# a_255_n125# 0.13fF
+C14 a_255_n125# a_159_n125# 0.36fF
+C15 a_n317_n125# a_n33_n125# 0.08fF
+C16 a_63_n125# a_n33_n125# 0.36fF
+C17 a_n317_n125# a_n129_n125# 0.13fF
+C18 a_n33_n125# a_159_n125# 0.13fF
+C19 a_63_n125# a_n129_n125# 0.13fF
+C20 a_n129_n125# a_159_n125# 0.08fF
+C21 a_n63_n151# a_33_n151# 0.02fF
+C22 a_n255_n151# a_n159_n151# 0.02fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n455_n344# a_n33_n125# 0.05fF
+C1 a_n129_n125# a_n317_n125# 0.13fF
+C2 w_n455_n344# a_n317_n125# 0.11fF
+C3 a_33_n154# a_129_n154# 0.02fF
+C4 a_n225_n125# a_63_n125# 0.08fF
+C5 a_n159_n154# a_n63_n154# 0.02fF
+C6 a_225_n154# a_129_n154# 0.02fF
+C7 a_255_n125# a_63_n125# 0.13fF
+C8 a_n129_n125# a_63_n125# 0.13fF
+C9 a_63_n125# w_n455_n344# 0.04fF
+C10 a_159_n125# a_n33_n125# 0.13fF
+C11 a_n225_n125# a_n129_n125# 0.36fF
+C12 a_n225_n125# w_n455_n344# 0.06fF
+C13 a_255_n125# a_n129_n125# 0.06fF
+C14 a_255_n125# w_n455_n344# 0.11fF
+C15 a_n129_n125# w_n455_n344# 0.04fF
+C16 a_n33_n125# a_n317_n125# 0.08fF
+C17 a_159_n125# a_63_n125# 0.36fF
+C18 a_63_n125# a_n33_n125# 0.36fF
+C19 a_33_n154# a_n63_n154# 0.02fF
+C20 a_159_n125# a_n225_n125# 0.06fF
+C21 a_63_n125# a_n317_n125# 0.06fF
+C22 a_n159_n154# a_n255_n154# 0.02fF
+C23 a_255_n125# a_159_n125# 0.36fF
+C24 a_159_n125# a_n129_n125# 0.08fF
+C25 a_159_n125# w_n455_n344# 0.06fF
+C26 a_n225_n125# a_n33_n125# 0.13fF
+C27 a_255_n125# a_n33_n125# 0.08fF
+C28 a_n129_n125# a_n33_n125# 0.36fF
+C29 a_n225_n125# a_n317_n125# 0.36fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 in vdd 0.04fF
+C1 in out 0.85fF
+C2 vdd out 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss vdd inverter_cp_x1_0/out inverter_cp_x1_2/in Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown vss inverter_cp_x1_0/out vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd nUp 0.14fF
+C1 Down nDown 0.23fF
+C2 Down inverter_cp_x1_0/out 0.12fF
+C3 Up inverter_cp_x1_2/in 0.12fF
+C4 inverter_cp_x1_2/in vdd 0.42fF
+C5 QA vdd 0.02fF
+C6 inverter_cp_x1_0/out nDown 0.11fF
+C7 QB vdd 0.02fF
+C8 vdd nDown 0.80fF
+C9 inverter_cp_x1_0/out vdd 0.18fF
+C10 Up vdd 0.60fF
+C11 Up nUp 0.20fF
+C12 inverter_cp_x1_2/in vss 2.01fF
+C13 QA vss 1.09fF
+C14 inverter_cp_x1_0/out vss 1.72fF
+C15 QB vss 1.09fF
+C16 vdd vss 28.20fF
+C17 nUp vss 1.32fF
+C18 Up vss 2.53fF
+C19 Down vss 1.17fF
+C20 nDown vss 2.77fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 w_n359_n309# a_63_n90# 0.06fF
+C1 a_n33_n90# a_n221_n90# 0.09fF
+C2 a_n159_n207# a_n63_n116# 0.12fF
+C3 a_159_n90# a_63_n90# 0.26fF
+C4 w_n359_n309# a_159_n90# 0.09fF
+C5 a_n221_n90# a_63_n90# 0.06fF
+C6 a_n129_n90# a_n33_n90# 0.26fF
+C7 w_n359_n309# a_n221_n90# 0.09fF
+C8 a_159_n90# a_n221_n90# 0.04fF
+C9 a_n129_n90# a_63_n90# 0.09fF
+C10 a_n129_n90# w_n359_n309# 0.06fF
+C11 a_n129_n90# a_159_n90# 0.06fF
+C12 a_n129_n90# a_n221_n90# 0.26fF
+C13 a_n33_n90# a_63_n90# 0.26fF
+C14 w_n359_n309# a_n33_n90# 0.05fF
+C15 a_n33_n90# a_159_n90# 0.09fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_71# a_33_n71# 0.04fF
+C1 a_n125_n45# a_63_n45# 0.05fF
+C2 a_n33_n45# a_63_n45# 0.13fF
+C3 a_n33_n45# a_n125_n45# 0.13fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 out vdd 0.11fF
+C1 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
+C2 A vdd 0.09fF
+C3 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
+C4 out A 0.06fF
+C5 out B 0.40fF
+C6 A B 0.24fF
+C7 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A Reset nor_pfd_2/B
+Xnor_pfd_0 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss CLK Q nor_pfd
+Xnor_pfd_1 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_3/A Reset nor_pfd
+C0 nor_pfd_2/B vdd 0.02fF
+C1 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C2 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C3 Reset nor_pfd_2/B 0.43fF
+C4 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C5 vdd nor_pfd_3/A 0.09fF
+C6 nor_pfd_2/B Q 2.22fF
+C7 Reset nor_pfd_3/A 0.12fF
+C8 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C9 nor_pfd_3/A Q 0.98fF
+C10 vdd nor_pfd_2/A -0.01fF
+C11 nor_pfd_2/B nor_pfd_3/A 0.58fF
+C12 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C13 nor_pfd_2/A Q 1.38fF
+C14 CLK Q 0.04fF
+C15 vdd Q 0.08fF
+C16 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C17 Reset Q 0.14fF
+C18 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C19 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_n45# a_159_n45# 0.03fF
+C1 a_n129_n45# a_63_n45# 0.05fF
+C2 a_n221_n45# a_159_n45# 0.02fF
+C3 a_n221_n45# a_63_n45# 0.03fF
+C4 a_n129_n45# a_n221_n45# 0.13fF
+C5 a_n63_n71# a_n159_n173# 0.10fF
+C6 a_159_n45# a_n33_n45# 0.05fF
+C7 a_63_n45# a_n33_n45# 0.13fF
+C8 a_n129_n45# a_n33_n45# 0.13fF
+C9 a_n221_n45# a_n33_n45# 0.05fF
+C10 a_63_n45# a_159_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n33_n90# a_63_n90# 0.26fF
+C1 a_n125_n90# a_n33_n90# 0.26fF
+C2 a_n125_n90# a_63_n90# 0.09fF
+C3 a_33_n187# a_n99_n187# 0.04fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_15_n45# a_n73_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n73_n90# w_n211_n309# 0.04fF
+C1 a_15_n90# w_n211_n309# 0.09fF
+C2 a_n73_n90# a_15_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# out vss vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 a_656_410# B 0.30fF
+C1 vdd out 0.10fF
+C2 vdd A 0.05fF
+C3 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C4 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C5 a_656_410# out 0.20fF
+C6 A B 0.33fF
+C7 a_656_410# A 0.04fF
+C8 vdd a_656_410# 0.20fF
+C9 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Reset Down Up A B
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A Reset dff_pfd_0/nor_pfd_2/B
++ dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A Reset dff_pfd_1/nor_pfd_2/B
++ dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# Reset vss vdd Up Down and_pfd
+C0 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C1 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C2 dff_pfd_1/nor_pfd_2/B vdd 0.04fF
+C3 vdd Reset 0.02fF
+C4 Down Up 0.06fF
+C5 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C6 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C7 Down vdd 0.08fF
+C8 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C9 vdd Up 1.62fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v3_pex_c iref_cp vss vdd vco_out vco_vctrl Up pfd_QA out_to_buffer
++ in_ref nUp out_to_pad Down nDown pfd_QB lf_D0 lf_vc out_first_buffer cp_biasp cp_pswitch cp_nswitch
++ pfd_reset s_0 MC s_1 out_by_2 out_to_div out_div n_out_by_2 n_out_div_2 out_div_2 n_out_buffer_div_2
++ out_buffer_div_2 n_clk_0 s1n s0n clk_2_f clk_d clk_out_mux21 clk_5 clk_pre n_clk_1 clk_1 clk_0 lf_D0
+Xcharge_pump_0 nswitch vss vdd nUp Down charge_pump_0/w_2544_775# vco_vctrl pswitch
++ iref_cp nDown biasp Up vss charge_pump
+Xloop_filter_v2_0 lf_vc lf_D0 vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vdd vss n_out_div_2 out_by_2 n_out_by_2 out_buffer_div_2 n_out_buffer_div_2
++ out_to_div out_div_2 div_by_2
+Xfreq_div_0 clk_0 vss n_clk_0 vdd s_0 freq_div_0/prescaler_23_0/Q2 s_1_n s_1 freq_div_0/prescaler_23_0/nCLK_23
++ MC clk_d freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n clk_pre
++ freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out_div freq_div_0/div_by_5_0/Q1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ clk_2_f out_by_2 n_out_by_2 clk_5 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D
++ freq_div
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad vdd out_to_buffer vss buffer_salida
+Xring_osc_0 vco_vctrl vss vdd ring_osc_0/csvco_branch_0/inverter_csvco_0/vss ring_osc_0/csvco_branch_2/vbp
++ vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div PFD
+C0 vco_vctrl n_clk_1 0.23fF
+C1 pswitch nUp 0.93fF
+C2 Up nUp 2.72fF
+C3 vdd nUp 0.05fF
+C4 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D 0.53fF
+C5 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C6 clk_0 vco_vctrl -0.26fF
+C7 nDown Down 2.55fF
+C8 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C9 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# 0.34fF
+C10 Up biasp 0.26fF
+C11 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vco_vctrl 0.15fF
+C12 out_by_2 n_out_by_2 0.27fF
+C13 nswitch nDown 0.76fF
+C14 nDown nUp -0.09fF
+C15 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C16 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C17 vco_vctrl freq_div_0/prescaler_23_0/nCLK_23 0.06fF
+C18 nswitch Down 0.54fF
+C19 buffer_salida_0/a_678_n100# out_to_buffer 0.21fF
+C20 charge_pump_0/w_2544_775# nDown 0.05fF
+C21 s_0_n n_out_by_2 0.14fF
+C22 clk_0 vdd 0.13fF
+C23 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.65fF
+C24 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C25 vdd vco_D0 0.03fF
+C26 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD 1.23fF
+C27 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD -0.42fF
+C28 vco_vctrl clk_1 -0.04fF
+C29 nDown biasp 0.26fF
+C30 vco_vctrl s_0 0.45fF
+C31 vco_vctrl vdd 0.58fF
+C32 charge_pump_0/w_2544_775# Down -0.23fF
+C33 s_1_n out_div 0.09fF
+C34 vdd buffer_salida_0/a_678_n100# 0.24fF
+C35 lf_vc MC 0.20fF
+C36 QA vdd -0.04fF
+C37 biasp Down 1.24fF
+C38 vdd out_to_buffer 0.07fF
+C39 vco_vctrl freq_div_0/div_by_5_0/Q1 0.10fF
+C40 MC vco_vctrl 0.33fF
+C41 pswitch Up 1.98fF
+C42 iref_cp Down 0.09fF
+C43 Up vdd 0.28fF
+C44 out_to_div out_to_buffer 0.13fF
+C45 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D 0.09fF
+C46 biasp nUp -0.16fF
+C47 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C48 out_to_div s_0 0.94fF
+C49 vco_vctrl freq_div_0/prescaler_23_0/Q2 0.06fF
+C50 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vco_vctrl 0.09fF
+C51 s_1 out_div 0.37fF
+C52 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vco_vctrl 0.17fF
+C53 pswitch nDown 0.53fF
+C54 vco_vctrl s_0_n 0.34fF
+C55 clk_d out_div 0.60fF
+C56 vdd nDown 0.22fF
+C57 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vco_vctrl -0.42fF
+C58 clk_1 n_out_by_2 -0.10fF
+C59 s_0 n_out_by_2 0.14fF
+C60 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vco_vctrl 0.82fF
+C61 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C62 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C63 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C64 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C65 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C66 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C67 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C68 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C69 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C70 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C71 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C72 QB vss 3.83fF
+C73 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C74 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C75 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C76 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C77 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C78 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C79 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C80 pfd_reset vss 1.87fF
+C81 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C82 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C83 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C84 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C85 QA vss 4.29fF
+C86 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C87 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C88 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C89 in_ref vss 0.84fF
+C90 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C91 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.66fF
+C92 nUp vss 0.30fF
+C93 Up vss 5.34fF
+C94 Down vss 0.91fF
+C95 nDown vss 1.94fF
+C96 out_to_buffer vss 1.92fF
+C97 out_to_div vss 8.72fF
+C98 out_first_buffer vss 2.15fF
+C99 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C100 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C101 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C102 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C103 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C104 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C105 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C106 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C107 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C108 vco_out vss 1.65fF
+C109 vco_D0 vss -4.72fF
+C110 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C111 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C112 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C113 out_to_pad vss 7.15fF
+C114 buffer_salida_0/a_3996_n100# vss 48.29fF
+C115 buffer_salida_0/a_678_n100# vss 13.38fF
+C116 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C117 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C118 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C119 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C120 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C121 freq_div_0/prescaler_23_0/Q2_d vss -0.69fF
+C122 freq_div_0/prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C123 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C124 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C125 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C126 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C127 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C128 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C129 freq_div_0/prescaler_23_0/Q2 vss 0.55fF
+C130 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C131 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C132 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C133 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C134 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C135 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C136 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C137 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C138 freq_div_0/prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C139 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C140 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C141 n_clk_0 vss -6.63fF
+C142 freq_div_0/prescaler_23_0/Q1 vss 0.07fF
+C143 freq_div_0/prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C144 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C145 clk_0 vss -0.36fF
+C146 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C147 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C148 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C149 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C150 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C151 freq_div_0/prescaler_23_0/nCLK_23 vss -1.02fF
+C152 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C153 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C154 MC vss -1.42fF
+C155 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C156 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C157 n_out_by_2 vss 4.53fF
+C158 out_by_2 vss 4.18fF
+C159 s_0_n vss -3.95fF
+C160 s_0 vss 5.61fF
+C161 freq_div_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C162 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C163 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C164 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C165 freq_div_0/div_by_5_0/Q1_shift vss -0.36fF
+C166 freq_div_0/div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C167 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C168 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C169 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C170 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C171 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C172 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C173 freq_div_0/div_by_5_0/Q1 vss 4.35fF
+C174 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 0.94fF
+C175 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C176 freq_div_0/div_by_5_0/Q0 vss 0.29fF
+C177 freq_div_0/div_by_5_0/nQ0 vss 0.99fF
+C178 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C179 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C180 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C181 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C182 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C183 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C184 freq_div_0/div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C185 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 0.94fF
+C186 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C187 freq_div_0/div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C188 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C189 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C190 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C191 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C192 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C193 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C194 freq_div_0/div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C195 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 0.94fF
+C196 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C197 n_clk_1 vss -0.57fF
+C198 freq_div_0/div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C199 freq_div_0/div_by_5_0/nQ2 vss 1.38fF
+C200 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C201 clk_1 vss -2.22fF
+C202 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C203 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C204 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C205 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C206 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C207 freq_div_0/div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C208 vdd vss 573.83fF
+C209 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C210 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C211 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C212 out_div vss 0.60fF
+C213 clk_d vss 1.26fF
+C214 s_1_n vss -2.01fF
+C215 s_1 vss 1.77fF
+C216 freq_div_0/inverter_min_x4_0/in vss 2.71fF
+C217 clk_5 vss -0.23fF
+C218 clk_out_mux21 vss 3.65fF
+C219 clk_pre vss 1.67fF
+C220 clk_2_f vss 3.29fF
+C221 freq_div_0/div_by_2_0/o1 vss 2.08fF
+C222 freq_div_0/div_by_2_0/nCLK_2 vss 1.04fF
+C223 freq_div_0/div_by_2_0/o2 vss 2.08fF
+C224 freq_div_0/div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C225 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C226 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C227 freq_div_0/div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C228 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C229 freq_div_0/div_by_2_0/out_div vss -0.82fF
+C230 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C231 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C232 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C233 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C234 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C235 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C236 freq_div_0/div_by_2_0/nout_div vss 2.62fF
+C237 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C238 out_buffer_div_2 vss 1.57fF
+C239 n_out_buffer_div_2 vss 1.57fF
+C240 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C241 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C242 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C243 div_by_2_0/DFlipFlop_0/nCLK vss 0.82fF
+C244 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C245 out_div_2 vss -0.70fF
+C246 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C247 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C248 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C249 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C250 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C251 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.56fF
+C252 n_out_div_2 vss 2.11fF
+C253 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 0.94fF
+C254 lf_vc vss -60.88fF
+C255 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C256 lf_D0 vss 0.01fF
+C257 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C258 nswitch vss 4.61fF
+C259 biasp vss 5.46fF
+C260 iref_cp vss 7.56fF
+C261 vco_vctrl vss -30.43fF
+C262 pswitch vss 2.72fF
+.ends
+
diff --git a/xschem/simulations/top_pll_v3_pex_no_integration.spice b/xschem/simulations/top_pll_v3_pex_no_integration.spice
new file mode 100644
index 0000000..3291b79
--- /dev/null
+++ b/xschem/simulations/top_pll_v3_pex_no_integration.spice
@@ -0,0 +1,62 @@
+**.subckt top_pll_v3_pex_no_integration vdd vss in_ref pfd_QA pfd_QB Up nUp Down nDown pfd_reset
+*+ cp_nswitch cp_pswitch cp_biasp iref_cp lf_vc vco_D0 vco_vctrl vco_out out_first_buffer out_to_buffer
+*+ out_to_div out_by_2 n_out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2 out_div out_to_pad
+*+ clk_0 n_clk_0 clk_1 n_clk_1 clk_pre clk_5 clk_out_mux21 clk_d clk_2_f s0n s1n MC s_0 s_1 lf_D0
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.ipin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.iopin out_to_buffer
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin out_div
+*.opin out_to_pad
+*.iopin clk_0
+*.iopin n_clk_0
+*.iopin clk_1
+*.iopin n_clk_1
+*.iopin clk_pre
+*.iopin clk_5
+*.iopin clk_out_mux21
+*.iopin clk_d
+*.iopin clk_2_f
+*.iopin s0n
+*.iopin s1n
+*.ipin MC
+*.ipin s_0
+*.ipin s_1
+*.ipin lf_D0
+x1 vss vdd pfd_QA in_ref out_div pfd_QB pfd_reset PFD_pex_c
+x2 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface_pex_c
+x4 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump_pex_c
+x5 vss vco_vctrl lf_vc lf_D0 loop_filter_v2_pex_c
+x6 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer_pex_c
+x7 vdd out_to_pad out_to_buffer vss buffer_salida_pex_c
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2_pex_c
+x9 s1n s0n s_0 s_1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 out_div out_by_2 clk_5
++ clk_2_f n_out_by_2 clk_1 n_clk_1 freq_div_pex_c
+x3 vdd vco_out vco_vctrl vss vco_D0 csvco_pex_c
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/trans_gate_mux2to8.spice b/xschem/simulations/trans_gate_mux2to8.spice
new file mode 100644
index 0000000..aa3023a
--- /dev/null
+++ b/xschem/simulations/trans_gate_mux2to8.spice
@@ -0,0 +1,16 @@
+**.subckt trans_gate_mux2to8 en_neg in out en_pos vdd vss
+*.iopin en_neg
+*.ipin in
+*.opin out
+*.iopin en_pos
+*.iopin vdd
+*.iopin vss
+XM2 out en_neg in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out en_pos in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/tb_freq_div.sch b/xschem/tb_freq_div.sch
new file mode 100644
index 0000000..4835a42
--- /dev/null
+++ b/xschem/tb_freq_div.sch
@@ -0,0 +1,202 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -310 0 -280 0 { lab=CLK}
+N -230 -110 -230 -80 { lab=vdd}
+N -240 80 -240 110 { lab=#net1}
+N -190 -110 -190 -80 { lab=vss}
+N -220 80 -220 110 { lab=#net2}
+N -200 80 -200 110 { lab=#net3}
+N -180 80 -180 110 { lab=#net4}
+N -140 20 -70 20 { lab=nclk_2}
+N -140 -20 -70 -20 { lab=clk_2}
+N 130 -110 130 -80 { lab=vdd}
+N 150 -110 150 -80 { lab=vss}
+N 210 0 320 0 { lab=f_div}
+N 370 -170 370 -140 { lab=vdd}
+N 410 -170 410 -140 { lab=vss}
+N 390 60 390 90 { lab=#net5}
+N 290 -80 320 -80 { lab=#net6}
+N 460 -80 490 -80 { lab=#net7}
+N 460 0 490 0 { lab=#net8}
+N -930 -270 -930 -240 { lab=GND}
+N -1020 110 -1020 140 { lab=vss}
+N -860 -270 -860 -240 { lab=vss}
+N -930 -360 -930 -330 { lab=vss}
+N -1020 20 -1020 50 { lab=#net9}
+N -860 -360 -860 -330 { lab=vdd}
+N -400 -290 -400 -260 { lab=vss}
+N -400 -380 -400 -350 { lab=S1}
+N -690 50 -690 80 { lab=vss}
+N -690 -80 -690 -50 { lab=vdd}
+N -600 0 -520 0 { lab=#net10}
+N -480 50 -480 80 { lab=vss}
+N -480 -80 -480 -50 { lab=vdd}
+N -1020 -0 -1020 20 { lab=#net9}
+N -1020 -0 -730 -0 { lab=#net9}
+N -390 -0 -310 -0 { lab=CLK}
+N -20 -110 -20 -80 { lab=S1}
+N 0 -110 0 -80 { lab=S0}
+N 20 -110 20 -80 { lab=MC}
+N -70 -290 -70 -260 { lab=vss}
+N -70 -380 -70 -350 { lab=S0}
+N 270 -290 270 -260 { lab=vss}
+N 270 -380 270 -350 { lab=MC}
+N -30 130 -30 160 { lab=clk_0}
+N -10 130 -10 160 { lab=n_clk_0}
+N 10 130 10 160 { lab=clk_1}
+N 30 130 30 160 { lab=n_clk_1}
+N -30 90 -30 130 { lab=clk_0}
+N -10 80 -10 130 { lab=n_clk_0}
+N 10 80 10 130 { lab=clk_1}
+N 30 80 30 130 { lab=n_clk_1}
+N -30 80 -30 90 { lab=clk_0}
+N 50 130 50 160 { lab=clk_pre}
+N 70 130 70 160 { lab=clk_5}
+N 90 130 90 160 { lab=clk_out_mux21}
+N 110 130 110 160 { lab=clk_d}
+N 50 90 50 130 { lab=clk_pre}
+N 70 80 70 130 { lab=clk_5}
+N 90 80 90 130 { lab=clk_out_mux21}
+N 110 80 110 130 { lab=clk_d}
+N 50 80 50 90 { lab=clk_pre}
+N 130 130 130 160 { lab=clk_2_f}
+N 150 130 150 160 { lab=s0n}
+N 170 130 170 160 { lab=s1n}
+N 130 80 130 130 { lab=clk_2_f}
+N 150 80 150 130 { lab=s0n}
+N 170 80 170 130 { lab=s1n}
+C {freq_div.sym} 50 0 0 0 {name=x1}
+C {lab_wire.sym} -330 0 0 1 {name=l7 sig_type=std_logic lab=CLK}
+C {lab_pin.sym} -230 -110 1 0 {name=l21 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} -130 -20 0 1 {name=l5 sig_type=std_logic lab=clk_2}
+C {lab_wire.sym} -130 20 0 1 {name=l12 sig_type=std_logic lab=nclk_2}
+C {div_by_2.sym} -210 0 0 0 {name=x2}
+C {lab_pin.sym} -190 -110 1 0 {name=l17 sig_type=std_logic lab=vss}
+C {noconn.sym} -240 110 3 0 {name=l18}
+C {noconn.sym} -220 110 3 0 {name=l19}
+C {noconn.sym} -200 110 3 0 {name=l20}
+C {noconn.sym} -180 110 3 0 {name=l22}
+C {lab_pin.sym} 130 -110 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 -110 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {PFD.sym} 390 -40 0 0 {name=x3}
+C {lab_pin.sym} 370 -170 1 0 {name=l3 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -170 1 0 {name=l4 sig_type=std_logic lab=vss}
+C {noconn.sym} 390 90 3 0 {name=l6}
+C {noconn.sym} 290 -80 0 0 {name=l8}
+C {noconn.sym} 490 -80 2 0 {name=l9}
+C {noconn.sym} 490 0 2 0 {name=l10}
+C {vsource.sym} -930 -300 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -860 -300 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -1020 80 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -930 -240 0 0 {name=l11 lab=GND}
+C {lab_pin.sym} -930 -360 1 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -860 -240 3 0 {name=l14 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -1020 140 3 0 {name=l15 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -860 -360 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {netlist_not_shown.sym} -760 -360 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+.options GMIN = 1e-10
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+
+* Data to save
+.save all
+.ic v(CLK) = 0.0
+.ic v(MC) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(f_div) = 0.0
+.ic v(S0) = 0.0
+.ic v(S1) = 0.0
+.ic v(clk_0) = 0.0
+.ic v(n_clk_0) = 0.0
+.ic v(clk_1) = 0.0
+.ic v(n_clk_1) = 0.0
+.ic v(clk_pre) = 0.0
+.ic v(clk_5) = 0.0
+.ic v(clk_d) = 0.0
+.ic v(clk_2_f) = 0.0
+.ic v(s1n) = 0.0
+.ic v(s0n) = 0.0
+.ic v(x1.x4.q2) = 0.0
+.ic v(x1.x4.q1) = 0.0
+.ic v(x1.x4.q1_shift) = 0.0
+.ic v(x1.x4.q0) = 0.0
+.ic v(x1.x4.x1.a) = 0.0
+.ic v(x1.x4.x1.D_d) = 0.0
+.ic v(x1.x4.x1.nD_d) = 0.0
+
+* Simulation
+.control
+ save v(CLK) v(clk_2) v(S1) v(S0) v(MC) v(clk_0) v(clk_1) v(clk_pre) v(clk_5) v(clk_d) v(clk_2_f) v(f_div)
+ tran 0.01ns 800ns
+ write tb_freq_div_tran.raw
+ plot v(CLK) v(clk_2)+2 v(S1)+4 v(S0)+6 v(MC)+8 v(clk_0)+10 v(clk_1)+12 v(clk_pre)+14 v(clk_5)+16 v(clk_d)+18 v(clk_2_f)+20 v(f_div)+22
+.endc
+
+.end
+"}
+C {netlist_not_shown.sym} -600 -360 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {lab_pin.sym} -400 -260 3 0 {name=l24 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -400 -380 1 0 {name=l25 sig_type=std_logic lab=S1}
+C {vsource.sym} -400 -320 0 0 {name=VMC value="PULSE(0 \{vin\} 0 1p 1p 400n 800n) DC \{vin\} AC 0"}
+C {lab_pin.sym} -690 80 3 0 {name=l26 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -690 -80 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {inverter_min_x2_pex_c.sym} -670 0 0 0 {name=x4}
+C {inverter_min_x4_pex_c.sym} -460 0 0 0 {name=x5}
+C {lab_pin.sym} -480 80 3 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -480 -80 1 0 {name=l29 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 240 0 0 1 {name=l23 sig_type=std_logic lab=f_div}
+C {lab_pin.sym} 20 -110 3 1 {name=l30 sig_type=std_logic lab=MC}
+C {lab_pin.sym} 0 -110 3 1 {name=l31 sig_type=std_logic lab=S0}
+C {lab_pin.sym} -20 -110 3 1 {name=l32 sig_type=std_logic lab=S1}
+C {lab_pin.sym} -70 -260 3 0 {name=l33 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -70 -380 1 0 {name=l34 sig_type=std_logic lab=S0}
+C {vsource.sym} -70 -320 0 0 {name=VMC1 value="PULSE(0 \{vin\} 0 1p 1p 200n 400n) DC \{vin\} AC 0"}
+C {lab_pin.sym} 270 -260 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 270 -380 1 0 {name=l36 sig_type=std_logic lab=MC}
+C {vsource.sym} 270 -320 0 0 {name=VMC2 value="PULSE(0 \{vin\} 0 1p 1p 100n 200n) DC \{vin\} AC 0"}
+C {noconn.sym} -30 160 3 0 {name=l37}
+C {noconn.sym} -10 160 3 0 {name=l38}
+C {noconn.sym} 10 160 3 0 {name=l39}
+C {noconn.sym} 30 160 3 0 {name=l40}
+C {noconn.sym} 50 160 3 0 {name=l41}
+C {noconn.sym} 70 160 3 0 {name=l42}
+C {noconn.sym} 90 160 3 0 {name=l43}
+C {noconn.sym} 110 160 3 0 {name=l44}
+C {noconn.sym} 130 160 3 0 {name=l45}
+C {noconn.sym} 150 160 3 0 {name=l46}
+C {noconn.sym} 170 160 3 0 {name=l47}
+C {lab_wire.sym} -30 150 3 1 {name=l48 sig_type=std_logic lab=clk_0}
+C {lab_wire.sym} -10 150 3 1 {name=l49 sig_type=std_logic lab=n_clk_0}
+C {lab_wire.sym} 10 150 3 1 {name=l50 sig_type=std_logic lab=clk_1}
+C {lab_wire.sym} 30 150 3 1 {name=l51 sig_type=std_logic lab=n_clk_1}
+C {lab_wire.sym} 50 150 3 1 {name=l52 sig_type=std_logic lab=clk_pre}
+C {lab_wire.sym} 70 150 3 1 {name=l53 sig_type=std_logic lab=clk_5}
+C {lab_wire.sym} 90 90 3 0 {name=l54 sig_type=std_logic lab=clk_out_mux21}
+C {lab_wire.sym} 110 150 3 1 {name=l55 sig_type=std_logic lab=clk_d}
+C {lab_wire.sym} 130 150 3 1 {name=l56 sig_type=std_logic lab=clk_2_f}
+C {lab_wire.sym} 150 150 3 1 {name=l57 sig_type=std_logic lab=s0n}
+C {lab_wire.sym} 170 150 3 1 {name=l58 sig_type=std_logic lab=s1n}
diff --git a/xschem/tb_freq_div_pex_c.sch b/xschem/tb_freq_div_pex_c.sch
new file mode 100644
index 0000000..bfd7ee1
--- /dev/null
+++ b/xschem/tb_freq_div_pex_c.sch
@@ -0,0 +1,198 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -310 0 -280 0 { lab=CLK}
+N -230 -110 -230 -80 { lab=vdd}
+N -240 80 -240 110 { lab=#net1}
+N -190 -110 -190 -80 { lab=vss}
+N -220 80 -220 110 { lab=#net2}
+N -200 80 -200 110 { lab=#net3}
+N -180 80 -180 110 { lab=#net4}
+N -140 20 -70 20 { lab=nclk_2}
+N -140 -20 -70 -20 { lab=clk_2}
+N 130 -110 130 -80 { lab=vdd}
+N 150 -110 150 -80 { lab=vss}
+N 210 0 320 0 { lab=f_div}
+N 370 -170 370 -140 { lab=vdd}
+N 410 -170 410 -140 { lab=vss}
+N 390 60 390 90 { lab=#net5}
+N 290 -80 320 -80 { lab=#net6}
+N 460 -80 490 -80 { lab=#net7}
+N 460 0 490 0 { lab=#net8}
+N -930 -270 -930 -240 { lab=GND}
+N -1020 110 -1020 140 { lab=vss}
+N -860 -270 -860 -240 { lab=vss}
+N -930 -360 -930 -330 { lab=vss}
+N -1020 20 -1020 50 { lab=#net9}
+N -860 -360 -860 -330 { lab=vdd}
+N -400 -290 -400 -260 { lab=vss}
+N -400 -380 -400 -350 { lab=S1}
+N -690 50 -690 80 { lab=vss}
+N -690 -80 -690 -50 { lab=vdd}
+N -600 0 -520 0 { lab=#net10}
+N -480 50 -480 80 { lab=vss}
+N -480 -80 -480 -50 { lab=vdd}
+N -1020 -0 -1020 20 { lab=#net9}
+N -1020 -0 -730 -0 { lab=#net9}
+N -390 -0 -310 -0 { lab=CLK}
+N -20 -110 -20 -80 { lab=S1}
+N 0 -110 0 -80 { lab=S0}
+N 20 -110 20 -80 { lab=MC}
+N -70 -290 -70 -260 { lab=vss}
+N -70 -380 -70 -350 { lab=S0}
+N 270 -290 270 -260 { lab=vss}
+N 270 -380 270 -350 { lab=MC}
+N -30 130 -30 160 { lab=clk_0}
+N -10 130 -10 160 { lab=n_clk_0}
+N 10 130 10 160 { lab=clk_1}
+N 30 130 30 160 { lab=n_clk_1}
+N -30 90 -30 130 { lab=clk_0}
+N -10 80 -10 130 { lab=n_clk_0}
+N 10 80 10 130 { lab=clk_1}
+N 30 80 30 130 { lab=n_clk_1}
+N -30 80 -30 90 { lab=clk_0}
+N 50 130 50 160 { lab=clk_pre}
+N 70 130 70 160 { lab=clk_5}
+N 90 130 90 160 { lab=clk_out_mux21}
+N 110 130 110 160 { lab=clk_d}
+N 50 90 50 130 { lab=clk_pre}
+N 70 80 70 130 { lab=clk_5}
+N 90 80 90 130 { lab=clk_out_mux21}
+N 110 80 110 130 { lab=clk_d}
+N 50 80 50 90 { lab=clk_pre}
+N 130 130 130 160 { lab=clk_2_f}
+N 150 130 150 160 { lab=s0n}
+N 170 130 170 160 { lab=s1n}
+N 130 80 130 130 { lab=clk_2_f}
+N 150 80 150 130 { lab=s0n}
+N 170 80 170 130 { lab=s1n}
+C {lab_wire.sym} -330 0 0 1 {name=l7 sig_type=std_logic lab=CLK}
+C {lab_pin.sym} -230 -110 1 0 {name=l21 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} -130 -20 0 1 {name=l5 sig_type=std_logic lab=clk_2}
+C {lab_wire.sym} -130 20 0 1 {name=l12 sig_type=std_logic lab=nclk_2}
+C {lab_pin.sym} -190 -110 1 0 {name=l17 sig_type=std_logic lab=vss}
+C {noconn.sym} -240 110 3 0 {name=l18}
+C {noconn.sym} -220 110 3 0 {name=l19}
+C {noconn.sym} -200 110 3 0 {name=l20}
+C {noconn.sym} -180 110 3 0 {name=l22}
+C {lab_pin.sym} 130 -110 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 -110 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 370 -170 1 0 {name=l3 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -170 1 0 {name=l4 sig_type=std_logic lab=vss}
+C {noconn.sym} 390 90 3 0 {name=l6}
+C {noconn.sym} 290 -80 0 0 {name=l8}
+C {noconn.sym} 490 -80 2 0 {name=l9}
+C {noconn.sym} 490 0 2 0 {name=l10}
+C {vsource.sym} -930 -300 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -860 -300 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -1020 80 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -930 -240 0 0 {name=l11 lab=GND}
+C {lab_pin.sym} -930 -360 1 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -860 -240 3 0 {name=l14 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -1020 140 3 0 {name=l15 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -860 -360 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {netlist_not_shown.sym} -760 -360 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+.options GMIN = 1e-10
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/freq_div_pex_c.spice
+
+* Data to save
+.save all
+.ic v(CLK) = 0.0
+.ic v(MC) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(f_div) = 0.0
+.ic v(S0) = 0.0
+.ic v(S1) = 0.0
+.ic v(clk_0) = 0.0
+.ic v(n_clk_0) = 0.0
+.ic v(clk_1) = 0.0
+.ic v(n_clk_1) = 0.0
+.ic v(clk_pre) = 0.0
+.ic v(clk_5) = 0.0
+.ic v(clk_d) = 0.0
+.ic v(clk_2_f) = 0.0
+.ic v(s1n) = 0.0
+.ic v(s0n) = 0.0
+
+* Simulation
+.control
+ save v(CLK) v(clk_2) v(S1) v(S0) v(MC) v(clk_0) v(clk_1) v(clk_pre) v(clk_5) v(clk_d) v(clk_2_f) v(f_div)
+ tran 0.01ns 800ns
+ write tb_freq_div_tran.raw
+ plot v(CLK) v(clk_2)+2 v(S1)+4 v(S0)+6 v(MC)+8 v(clk_0)+10 v(clk_1)+12 v(clk_pre)+14 v(clk_5)+16 v(clk_d)+18 v(clk_2_f)+20 v(f_div)+22
+.endc
+
+.end
+"}
+C {netlist_not_shown.sym} -600 -360 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {lab_pin.sym} -400 -260 3 0 {name=l24 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -400 -380 1 0 {name=l25 sig_type=std_logic lab=S1}
+C {vsource.sym} -400 -320 0 0 {name=VMC value="PULSE(0 \{vin\} 0 1p 1p 400n 800n) DC \{vin\} AC 0"}
+C {lab_pin.sym} -690 80 3 0 {name=l26 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -690 -80 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {inverter_min_x2_pex_c.sym} -670 0 0 0 {name=x4}
+C {inverter_min_x4_pex_c.sym} -460 0 0 0 {name=x5}
+C {lab_pin.sym} -480 80 3 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -480 -80 1 0 {name=l29 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 240 0 0 1 {name=l23 sig_type=std_logic lab=f_div}
+C {lab_pin.sym} 20 -110 3 1 {name=l30 sig_type=std_logic lab=MC}
+C {lab_pin.sym} 0 -110 3 1 {name=l31 sig_type=std_logic lab=S0}
+C {lab_pin.sym} -20 -110 3 1 {name=l32 sig_type=std_logic lab=S1}
+C {lab_pin.sym} -70 -260 3 0 {name=l33 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -70 -380 1 0 {name=l34 sig_type=std_logic lab=S0}
+C {vsource.sym} -70 -320 0 0 {name=VMC1 value="PULSE(0 \{vin\} 0 1p 1p 200n 400n) DC \{vin\} AC 0"}
+C {lab_pin.sym} 270 -260 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 270 -380 1 0 {name=l36 sig_type=std_logic lab=MC}
+C {vsource.sym} 270 -320 0 0 {name=VMC2 value="PULSE(0 \{vin\} 0 1p 1p 100n 200n) DC \{vin\} AC 0"}
+C {noconn.sym} -30 160 3 0 {name=l37}
+C {noconn.sym} -10 160 3 0 {name=l38}
+C {noconn.sym} 10 160 3 0 {name=l39}
+C {noconn.sym} 30 160 3 0 {name=l40}
+C {noconn.sym} 50 160 3 0 {name=l41}
+C {noconn.sym} 70 160 3 0 {name=l42}
+C {noconn.sym} 90 160 3 0 {name=l43}
+C {noconn.sym} 110 160 3 0 {name=l44}
+C {noconn.sym} 130 160 3 0 {name=l45}
+C {noconn.sym} 150 160 3 0 {name=l46}
+C {noconn.sym} 170 160 3 0 {name=l47}
+C {lab_wire.sym} -30 150 3 1 {name=l48 sig_type=std_logic lab=clk_0}
+C {lab_wire.sym} -10 150 3 1 {name=l49 sig_type=std_logic lab=n_clk_0}
+C {lab_wire.sym} 10 150 3 1 {name=l50 sig_type=std_logic lab=clk_1}
+C {lab_wire.sym} 30 150 3 1 {name=l51 sig_type=std_logic lab=n_clk_1}
+C {lab_wire.sym} 50 150 3 1 {name=l52 sig_type=std_logic lab=clk_pre}
+C {lab_wire.sym} 70 150 3 1 {name=l53 sig_type=std_logic lab=clk_5}
+C {lab_wire.sym} 90 90 3 0 {name=l54 sig_type=std_logic lab=clk_out_mux21}
+C {lab_wire.sym} 110 150 3 1 {name=l55 sig_type=std_logic lab=clk_d}
+C {lab_wire.sym} 130 150 3 1 {name=l56 sig_type=std_logic lab=clk_2_f}
+C {lab_wire.sym} 150 150 3 1 {name=l57 sig_type=std_logic lab=s0n}
+C {lab_wire.sym} 170 150 3 1 {name=l58 sig_type=std_logic lab=s1n}
+C {freq_div_pex_c.sym} 50 0 0 0 {name=x1}
+C {div_by_2_pex_c.sym} -210 0 0 0 {name=x2}
+C {PFD_pex_c.sym} 390 -40 0 0 {name=x3}
diff --git a/xschem/tb_mux2to1.sch b/xschem/tb_mux2to1.sch
new file mode 100644
index 0000000..95482d2
--- /dev/null
+++ b/xschem/tb_mux2to1.sch
@@ -0,0 +1,136 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -320 -790 -320 -760 { lab=GND}
+N -140 -540 -140 -510 { lab=vss}
+N -250 -790 -250 -760 { lab=vss}
+N -320 -880 -320 -850 { lab=vss}
+N -140 -630 -140 -600 { lab=#net1}
+N -250 -880 -250 -850 { lab=vdd}
+N 540 -630 570 -630 { lab=A}
+N 190 -580 190 -550 { lab=vss}
+N 190 -710 190 -680 { lab=vdd}
+N 280 -630 360 -630 { lab=#net2}
+N 400 -580 400 -550 { lab=vss}
+N 400 -710 400 -680 { lab=vdd}
+N -140 -630 150 -630 { lab=#net1}
+N 490 -630 540 -630 { lab=A}
+N 660 -740 660 -710 { lab=vss}
+N 620 -740 620 -710 { lab=vdd}
+N 610 -550 610 -500 { lab=out_div}
+N 630 -550 630 -500 { lab=#net3}
+N 650 -550 650 -500 { lab=#net4}
+N 670 -550 670 -500 { lab=#net5}
+N 450 -770 450 -740 { lab=vss}
+N 450 -860 450 -830 { lab=selec_0}
+N 790 -810 790 -780 { lab=vss}
+N 790 -940 790 -910 { lab=vdd}
+N 450 -860 750 -860 { lab=selec_0}
+N 880 -860 910 -860 { lab=selec_0_neg}
+N 1050 -570 1050 -350 { lab=selec_0}
+N 1090 -570 1090 -350 { lab=selec_0_neg}
+N 910 -670 1000 -670 { lab=in_b}
+N 910 -790 1000 -790 { lab=in_a}
+N 1310 -730 1530 -730 { lab=out_b_0_1}
+N 1530 -570 1530 -540 { lab=vss}
+N 1530 -730 1530 -630 { lab=out_b_0_1}
+N 710 -650 800 -650 { lab=in_b}
+N 710 -610 800 -610 { lab=in_a}
+N 1050 -920 1050 -890 { lab=vss}
+N 1090 -920 1090 -890 { lab=vdd}
+N 1140 -730 1220 -730 { lab=out_b_0_1}
+N 1220 -730 1310 -730 { lab=out_b_0_1}
+C {vsource.sym} -320 -820 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -250 -820 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -140 -570 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -320 -760 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -320 -880 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -250 -760 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -140 -510 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -250 -880 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 530 -630 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} -330 -640 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/sky130-mpw2-fulgor/inverter_min_x2/sch/simulations/inverter_min_x2_pex_c.spice
+.include ~/sky130-mpw2-fulgor/inverter_min_x4/sch/simulations/inverter_min_x4_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 50ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ *write tb_div_by_2_tran.raw
+ plot v(selec_0) v(out_b_0_1)+8
+ *plot v(out_div) v(out)
+.endc
+
+.end
+"}
+C {lab_pin.sym} 190 -550 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 190 -710 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {div_by_2/sch/div_by_2.sym} 640 -630 0 0 {name=x1}
+C {inverter_min_x2/sch/inverter_min_x2_pex_c.sym} 210 -630 0 0 {name=x2}
+C {inverter_min_x4/sch/inverter_min_x4_pex_c.sym} 420 -630 0 0 {name=x3}
+C {lab_pin.sym} 400 -550 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 400 -710 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 660 -740 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 620 -740 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {noconn.sym} 610 -500 1 1 {name=l20}
+C {noconn.sym} 630 -500 1 1 {name=l21}
+C {noconn.sym} 650 -500 1 1 {name=l22}
+C {noconn.sym} 670 -500 1 1 {name=l23}
+C {lab_pin.sym} 610 -520 2 1 {name=l26 sig_type=std_logic lab=out_div}
+C {vsource.sym} 450 -800 0 0 {name=Vref1 value="PULSE(0 \{vin\} 0 1p 1p \{12.5n\} \{25n\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} 450 -740 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 450 -850 0 1 {name=l13 sig_type=std_logic lab=selec_0}
+C {inverter_min_x4/sch/inverter_min_x4_pex_c.sym} 810 -860 0 0 {name=x7}
+C {lab_pin.sym} 790 -780 3 0 {name=l34 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 790 -940 1 0 {name=l35 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 900 -860 3 1 {name=l8 sig_type=std_logic lab=selec_0_neg}
+C {lab_pin.sym} 910 -670 0 0 {name=l19 sig_type=std_logic lab=in_b}
+C {lab_pin.sym} 910 -790 0 0 {name=l27 sig_type=std_logic lab=in_a}
+C {lab_pin.sym} 1050 -350 1 1 {name=l54 sig_type=std_logic lab=selec_0}
+C {lab_pin.sym} 1090 -350 1 1 {name=l58 sig_type=std_logic lab=selec_0_neg}
+C {lab_pin.sym} 1530 -730 0 1 {name=l38 sig_type=std_logic lab=out_b_0_1}
+C {capa.sym} 1530 -600 0 1 {name=C8
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1530 -540 1 1 {name=l56 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 800 -650 2 0 {name=l24 sig_type=std_logic lab=in_b}
+C {lab_pin.sym} 800 -610 2 0 {name=l25 sig_type=std_logic lab=in_a}
+C {lab_pin.sym} 1050 -920 3 1 {name=l76 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1090 -920 3 1 {name=l77 sig_type=std_logic lab=vdd}
+C {mux2to1/sch/mux2to1.sym} 1070 -730 0 1 {name=x4}
diff --git a/xschem/tb_mux2to4.sch b/xschem/tb_mux2to4.sch
new file mode 100644
index 0000000..f40b892
--- /dev/null
+++ b/xschem/tb_mux2to4.sch
@@ -0,0 +1,177 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -320 -790 -320 -760 { lab=GND}
+N -140 -540 -140 -510 { lab=vss}
+N -250 -790 -250 -760 { lab=vss}
+N -320 -880 -320 -850 { lab=vss}
+N -140 -630 -140 -600 { lab=#net1}
+N -250 -880 -250 -850 { lab=vdd}
+N 540 -630 570 -630 { lab=A}
+N 190 -580 190 -550 { lab=vss}
+N 190 -710 190 -680 { lab=vdd}
+N 280 -630 360 -630 { lab=#net2}
+N 400 -580 400 -550 { lab=vss}
+N 400 -710 400 -680 { lab=vdd}
+N -140 -630 150 -630 { lab=#net1}
+N 490 -630 540 -630 { lab=A}
+N 660 -740 660 -710 { lab=vss}
+N 620 -740 620 -710 { lab=vdd}
+N 610 -550 610 -500 { lab=out_div}
+N 630 -550 630 -500 { lab=#net3}
+N 650 -550 650 -500 { lab=#net4}
+N 670 -550 670 -500 { lab=#net5}
+N 450 -770 450 -740 { lab=vss}
+N 450 -860 450 -830 { lab=selec_0}
+N 790 -810 790 -780 { lab=vss}
+N 790 -940 790 -910 { lab=vdd}
+N 450 -860 750 -860 { lab=selec_0}
+N 880 -860 910 -860 { lab=selec_0_neg}
+N 1050 -570 1050 -350 { lab=selec_0}
+N 1090 -570 1090 -350 { lab=selec_0_neg}
+N 910 -690 1000 -690 { lab=in_b}
+N 910 -770 1000 -770 { lab=in_a}
+N 1370 -810 1590 -810 { lab=out_a_0_0}
+N 1390 -690 1610 -690 { lab=out_a_0_1}
+N 1310 -650 1530 -650 { lab=out_b_0_1}
+N 1730 -490 1730 -460 { lab=vss}
+N 1670 -490 1670 -460 { lab=vss}
+N 1610 -490 1610 -460 { lab=vss}
+N 1730 -780 1730 -590 { lab=out_a_0_0}
+N 1670 -710 1670 -550 { lab=out_b_0_0}
+N 1610 -690 1610 -560 { lab=out_a_0_1}
+N 1530 -490 1530 -460 { lab=vss}
+N 1530 -650 1530 -550 { lab=out_b_0_1}
+N 710 -650 800 -650 { lab=in_b}
+N 710 -610 800 -610 { lab=in_a}
+N 1090 -920 1090 -890 { lab=vss}
+N 1050 -920 1050 -890 { lab=vdd}
+N 1140 -810 1220 -810 { lab=out_a_0_0}
+N 1140 -770 1220 -770 { lab=out_b_0_0}
+N 1140 -690 1220 -690 { lab=out_a_0_1}
+N 1140 -650 1220 -650 { lab=out_b_0_1}
+N 1220 -650 1310 -650 { lab=out_b_0_1}
+N 1220 -690 1390 -690 { lab=out_a_0_1}
+N 1220 -770 1320 -770 { lab=out_b_0_0}
+N 1220 -810 1370 -810 { lab=out_a_0_0}
+N 1320 -770 1670 -770 { lab=out_b_0_0}
+N 1590 -810 1730 -810 { lab=out_a_0_0}
+N 1670 -770 1670 -710 { lab=out_b_0_0}
+N 1730 -810 1730 -780 { lab=out_a_0_0}
+N 1730 -590 1730 -550 { lab=out_a_0_0}
+N 1610 -560 1610 -550 { lab=out_a_0_1}
+C {vsource.sym} -320 -820 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -250 -820 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -140 -570 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -320 -760 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -320 -880 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -250 -760 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -140 -510 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -250 -880 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 530 -630 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} -330 -640 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/sky130-mpw2-fulgor/inverter_min_x2/sch/simulations/inverter_min_x2_pex_c.spice
+.include ~/sky130-mpw2-fulgor/inverter_min_x4/sch/simulations/inverter_min_x4_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 50ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ *write tb_div_by_2_tran.raw
+ plot v(selec_0) v(out_b_0_0)+4 v(out_a_0_0)+6 v(out_b_0_1)+8 v(out_a_0_1)+10
+ *plot v(out_div) v(out)
+.endc
+
+.end
+"}
+C {lab_pin.sym} 190 -550 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 190 -710 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {div_by_2/sch/div_by_2.sym} 640 -630 0 0 {name=x1}
+C {inverter_min_x2/sch/inverter_min_x2_pex_c.sym} 210 -630 0 0 {name=x2}
+C {inverter_min_x4/sch/inverter_min_x4_pex_c.sym} 420 -630 0 0 {name=x3}
+C {lab_pin.sym} 400 -550 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 400 -710 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 660 -740 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 620 -740 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {noconn.sym} 610 -500 1 1 {name=l20}
+C {noconn.sym} 630 -500 1 1 {name=l21}
+C {noconn.sym} 650 -500 1 1 {name=l22}
+C {noconn.sym} 670 -500 1 1 {name=l23}
+C {lab_pin.sym} 610 -520 2 1 {name=l26 sig_type=std_logic lab=out_div}
+C {vsource.sym} 450 -800 0 0 {name=Vref1 value="PULSE(0 \{vin\} 0 1p 1p \{12.5n\} \{25n\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} 450 -740 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 450 -850 0 1 {name=l13 sig_type=std_logic lab=selec_0}
+C {inverter_min_x4/sch/inverter_min_x4_pex_c.sym} 810 -860 0 0 {name=x7}
+C {lab_pin.sym} 790 -780 3 0 {name=l34 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 790 -940 1 0 {name=l35 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 900 -860 3 1 {name=l8 sig_type=std_logic lab=selec_0_neg}
+C {lab_pin.sym} 910 -690 0 0 {name=l19 sig_type=std_logic lab=in_b}
+C {lab_pin.sym} 910 -770 0 0 {name=l27 sig_type=std_logic lab=in_a}
+C {lab_pin.sym} 1050 -350 1 1 {name=l54 sig_type=std_logic lab=selec_0}
+C {lab_pin.sym} 1090 -350 1 1 {name=l58 sig_type=std_logic lab=selec_0_neg}
+C {lab_pin.sym} 1530 -650 0 1 {name=l38 sig_type=std_logic lab=out_b_0_1}
+C {lab_pin.sym} 1610 -690 0 1 {name=l39 sig_type=std_logic lab=out_a_0_1}
+C {lab_pin.sym} 1670 -770 0 1 {name=l40 sig_type=std_logic lab=out_b_0_0}
+C {lab_pin.sym} 1730 -810 0 1 {name=l41 sig_type=std_logic lab=out_a_0_0}
+C {capa.sym} 1730 -520 0 1 {name=C5
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1730 -460 1 1 {name=l52 sig_type=std_logic lab=vss}
+C {capa.sym} 1670 -520 0 1 {name=C6
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1670 -460 1 1 {name=l53 sig_type=std_logic lab=vss}
+C {capa.sym} 1610 -520 0 1 {name=C7
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1610 -460 1 1 {name=l55 sig_type=std_logic lab=vss}
+C {capa.sym} 1530 -520 0 1 {name=C8
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1530 -460 1 1 {name=l56 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 800 -650 2 0 {name=l24 sig_type=std_logic lab=in_b}
+C {lab_pin.sym} 800 -610 2 0 {name=l25 sig_type=std_logic lab=in_a}
+C {lab_pin.sym} 1090 -920 3 1 {name=l76 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1050 -920 3 1 {name=l77 sig_type=std_logic lab=vdd}
+C {mux2to4/sch/mux2to4.sym} 1070 -730 0 0 {name=x4}
diff --git a/xschem/tb_prescaler_23.sch b/xschem/tb_prescaler_23.sch
new file mode 100644
index 0000000..6d96637
--- /dev/null
+++ b/xschem/tb_prescaler_23.sch
@@ -0,0 +1,112 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -290 -350 -290 -320 { lab=GND}
+N -260 -120 -260 -90 { lab=vss}
+N -220 -350 -220 -320 { lab=vss}
+N -290 -440 -290 -410 { lab=vss}
+N -260 -210 -260 -180 { lab=CLK}
+N -220 -440 -220 -410 { lab=vdd}
+N 100 -240 130 -240 { lab=CLK}
+N 400 -350 400 -320 { lab=vdd}
+N 510 -170 510 -140 { lab=vss}
+N 180 -350 180 -320 { lab=vdd}
+N 170 -160 170 -130 { lab=#net1}
+N 270 -260 330 -260 { lab=clk_2}
+N 510 -240 510 -230 { lab=clk_23}
+N 470 -240 510 -240 { lab=clk_23}
+N 440 -350 440 -320 { lab=vss}
+N 270 -220 330 -220 { lab=nclk_2}
+N 80 -490 80 -460 { lab=vss}
+N 80 -580 80 -550 { lab=MC}
+N 360 -350 360 -320 { lab=MC}
+N 220 -350 220 -320 { lab=vss}
+N 190 -160 190 -130 { lab=#net2}
+N 210 -160 210 -130 { lab=#net3}
+N 230 -160 230 -130 { lab=#net4}
+N 370 -160 370 -130 { lab=#net5}
+N 390 -160 390 -130 { lab=#net6}
+N 410 -160 410 -130 { lab=#net7}
+N 430 -160 430 -130 { lab=#net8}
+C {vsource.sym} -290 -380 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -220 -380 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -260 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -290 -320 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -290 -440 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -220 -320 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -260 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -220 -440 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -260 -210 3 1 {name=l14 sig_type=std_logic lab=CLK}
+C {netlist_not_shown.sym} -120 -540 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+.ic v(CLK) = 0.0
+.ic v(MC) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(clk_23) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 800ns
+ write tb_div_by_5_tran.raw
+ plot v(clk_23) v(clk) v(clk_2) v(clk_23)+3 v(clk_2)+6 v(clk)+9
+
+.endc
+
+.end
+"}
+C {lab_pin.sym} 100 -240 2 1 {name=l7 sig_type=std_logic lab=CLK}
+C {lab_pin.sym} 400 -350 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {capa.sym} 510 -200 0 0 {name=C2
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 510 -140 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 510 -240 0 1 {name=l15 sig_type=std_logic lab=clk_23}
+C {lab_pin.sym} 180 -350 1 0 {name=l21 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 440 -350 1 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 280 -260 0 1 {name=l5 sig_type=std_logic lab=clk_2}
+C {lab_wire.sym} 280 -220 0 1 {name=l12 sig_type=std_logic lab=nclk_2}
+C {netlist_not_shown.sym} -120 -360 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {div_by_2/sch/div_by_2.sym} 200 -240 0 0 {name=x2}
+C {prescaler_23/sch/prescaler_23.sym} 400 -240 0 0 {name=x1}
+C {lab_pin.sym} 80 -460 3 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 80 -580 1 0 {name=l9 sig_type=std_logic lab=MC}
+C {lab_pin.sym} 360 -350 1 0 {name=l16 sig_type=std_logic lab=MC}
+C {vsource.sym} 80 -520 0 0 {name=VMC value="PULSE(0 \{vin\} 0 1p 1p 400n 800n) DC \{vin\} AC 0"}
+C {lab_pin.sym} 220 -350 1 0 {name=l17 sig_type=std_logic lab=vss}
+C {noconn.sym} 170 -130 3 0 {name=l18}
+C {noconn.sym} 190 -130 3 0 {name=l19}
+C {noconn.sym} 210 -130 3 0 {name=l20}
+C {noconn.sym} 230 -130 3 0 {name=l22}
+C {noconn.sym} 370 -130 3 0 {name=l23}
+C {noconn.sym} 390 -130 3 0 {name=l24}
+C {noconn.sym} 410 -130 3 0 {name=l25}
+C {noconn.sym} 430 -130 3 0 {name=l26}
diff --git a/xschem/tb_prescaler_23_pex_c.sch b/xschem/tb_prescaler_23_pex_c.sch
new file mode 100644
index 0000000..9b79c34
--- /dev/null
+++ b/xschem/tb_prescaler_23_pex_c.sch
@@ -0,0 +1,115 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -290 -350 -290 -320 { lab=GND}
+N -260 -120 -260 -90 { lab=vss}
+N -220 -350 -220 -320 { lab=vss}
+N -290 -440 -290 -410 { lab=vss}
+N -260 -210 -260 -180 { lab=CLK}
+N -220 -440 -220 -410 { lab=vdd}
+N 100 -240 130 -240 { lab=CLK}
+N 400 -350 400 -320 { lab=vdd}
+N 510 -170 510 -140 { lab=vss}
+N 180 -350 180 -320 { lab=vdd}
+N 170 -160 170 -130 { lab=#net1}
+N 270 -260 330 -260 { lab=clk_2}
+N 510 -240 510 -230 { lab=clk_23}
+N 470 -240 510 -240 { lab=clk_23}
+N 440 -350 440 -320 { lab=vss}
+N 270 -220 330 -220 { lab=nclk_2}
+N 80 -490 80 -460 { lab=vss}
+N 80 -580 80 -550 { lab=MC}
+N 360 -350 360 -320 { lab=MC}
+N 220 -350 220 -320 { lab=vss}
+N 190 -160 190 -130 { lab=#net2}
+N 210 -160 210 -130 { lab=#net3}
+N 230 -160 230 -130 { lab=#net4}
+N 370 -160 370 -130 { lab=#net5}
+N 390 -160 390 -130 { lab=#net6}
+N 410 -160 410 -130 { lab=#net7}
+N 430 -160 430 -130 { lab=#net8}
+C {vsource.sym} -290 -380 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -220 -380 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -260 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -290 -320 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -290 -440 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -220 -320 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -260 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -220 -440 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -260 -210 3 1 {name=l14 sig_type=std_logic lab=CLK}
+C {netlist_not_shown.sym} -120 -540 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/sky130-mpw2-fulgor/div_by_2/sch/simulations/div_by_2_pex_c.spice
+.include ~/sky130-mpw2-fulgor/prescaler_23/sch/simulations/prescaler_23_pex_c.spice
+
+* Data to save
+
+.ic v(CLK) = 0.0
+.ic v(MC) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(clk_23) = 0.0
+
+* Simulation
+.control
+ save v(MC) v(CLK) v(clk_2) v(nclk_2) v(clk_23)
+ tran 0.01ns 800ns
+ write tb_div_by_5_tran.raw
+ plot v(clk_23) v(clk) v(clk_2) v(MC)+3 v(clk_23)+6 v(clk_2)+9 v(clk)+12
+
+.endc
+
+.end
+"}
+C {lab_pin.sym} 100 -240 2 1 {name=l7 sig_type=std_logic lab=CLK}
+C {lab_pin.sym} 400 -350 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {capa.sym} 510 -200 0 0 {name=C2
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 510 -140 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 510 -240 0 1 {name=l15 sig_type=std_logic lab=clk_23}
+C {lab_pin.sym} 180 -350 1 0 {name=l21 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 440 -350 1 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 280 -260 0 1 {name=l5 sig_type=std_logic lab=clk_2}
+C {lab_wire.sym} 280 -220 0 1 {name=l12 sig_type=std_logic lab=nclk_2}
+C {netlist_not_shown.sym} -120 -360 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {lab_pin.sym} 80 -460 3 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 80 -580 1 0 {name=l9 sig_type=std_logic lab=MC}
+C {lab_pin.sym} 360 -350 1 0 {name=l16 sig_type=std_logic lab=MC}
+C {vsource.sym} 80 -520 0 0 {name=Vmc value="PULSE(\{vin\} 0 0 1p 1p 400n 800n) DC \{vin\} AC 0"}
+C {lab_pin.sym} 220 -350 1 0 {name=l17 sig_type=std_logic lab=vss}
+C {noconn.sym} 170 -130 3 0 {name=l18}
+C {noconn.sym} 190 -130 3 0 {name=l19}
+C {noconn.sym} 210 -130 3 0 {name=l20}
+C {noconn.sym} 230 -130 3 0 {name=l22}
+C {prescaler_23/sch/prescaler_23_pex_c.sym} 400 -240 0 0 {name=x1}
+C {div_by_2/sch/div_by_2_pex_c.sym} 200 -240 0 0 {name=x2}
+C {noconn.sym} 370 -130 3 0 {name=l23}
+C {noconn.sym} 390 -130 3 0 {name=l24}
+C {noconn.sym} 410 -130 3 0 {name=l25}
+C {noconn.sym} 430 -130 3 0 {name=l26}
diff --git a/xschem/tb_top_pll_v3.sch b/xschem/tb_top_pll_v3.sch
new file mode 100644
index 0000000..8a276de
--- /dev/null
+++ b/xschem/tb_top_pll_v3.sch
@@ -0,0 +1,305 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -620 -120 -620 -90 { lab=GND}
+N -470 -120 -470 -90 { lab=vss}
+N -550 -120 -550 -90 { lab=vss}
+N -620 -210 -620 -180 { lab=vss}
+N -470 -210 -470 -180 { lab=A}
+N -550 -210 -550 -180 { lab=vdd}
+N -100 -110 -100 -80 { lab=vss}
+N -100 -200 -100 -170 { lab=D0}
+N -590 50 -590 80 { lab=vdd}
+N -590 440 -590 470 { lab=vss}
+N -530 120 -490 120 { lab=iref_cp}
+N -590 350 -590 380 { lab=#net1}
+N -590 340 -590 350 { lab=#net1}
+N -530 140 -490 140 { lab=#net2}
+N -530 160 -490 160 { lab=#net3}
+N -530 180 -490 180 { lab=#net4}
+N -530 200 -490 200 { lab=#net5}
+N -530 220 -490 220 { lab=#net6}
+N -530 240 -490 240 { lab=#net7}
+N -530 260 -490 260 { lab=#net8}
+N -530 280 -490 280 { lab=#net9}
+N -530 300 -490 300 { lab=#net10}
+N 400 90 400 120 { lab=vdd}
+N 440 90 440 120 { lab=vss}
+N -260 80 -260 120 { lab=iref_cp}
+N -200 90 -200 120 { lab=D0}
+N -360 250 -330 250 { lab=A}
+N 570 250 610 250 { lab=out_to_pad}
+N 610 250 660 250 { lab=out_to_pad}
+N 340 380 340 430 { lab=clk_pre}
+N 320 380 320 430 { lab=n_clk_1}
+N 300 380 300 430 { lab=clk_1}
+N 280 380 280 430 { lab=n_clk_0}
+N 260 380 260 430 { lab=clk_0}
+N 180 380 180 430 { lab=n_out_buffer_div_2}
+N 160 380 160 430 { lab=out_buffer_div_2}
+N 140 380 140 430 { lab=n_out_div_2}
+N 120 380 120 430 { lab=out_div_2}
+N -100 430 -100 480 { lab=nswitch}
+N -80 430 -80 480 { lab=pswitch}
+N -60 430 -60 480 { lab=biasp}
+N -60 380 -60 430 { lab=biasp}
+N -80 380 -80 430 { lab=pswitch}
+N -100 380 -100 430 { lab=nswitch}
+N -280 430 -280 480 { lab=pfd_reset}
+N -280 380 -280 430 { lab=pfd_reset}
+N -260 430 -260 480 { lab=QA}
+N -260 380 -260 430 { lab=QA}
+N -240 430 -240 480 { lab=QB}
+N -240 380 -240 430 { lab=QB}
+N -200 430 -200 480 { lab=Up}
+N -200 380 -200 430 { lab=Up}
+N -180 430 -180 480 { lab=nUp}
+N -180 380 -180 430 { lab=nUp}
+N -160 430 -160 480 { lab=Down}
+N -160 380 -160 430 { lab=Down}
+N -140 430 -140 480 { lab=nDown}
+N -140 380 -140 430 { lab=nDown}
+N -20 380 -20 430 { lab=lf_vc}
+N 20 430 20 480 { lab=vctrl}
+N 20 380 20 430 { lab=vctrl}
+N 40 430 40 480 { lab=vco_out}
+N 40 380 40 430 { lab=vco_out}
+N 60 430 60 480 { lab=vco_buffer_out}
+N 60 380 60 430 { lab=vco_buffer_out}
+N 80 430 80 480 { lab=out_to_div}
+N 80 380 80 430 { lab=out_to_div}
+N 200 430 200 480 { lab=out_by_2}
+N 200 380 200 430 { lab=out_by_2}
+N 220 430 220 480 { lab=n_out_by_2}
+N 220 380 220 430 { lab=n_out_by_2}
+N 360 430 360 480 { lab=clk_5}
+N 360 380 360 430 { lab=clk_5}
+N 660 250 660 280 { lab=out_to_pad}
+N 660 340 660 370 { lab=vss}
+N 520 380 520 430 { lab=out_to_buffer}
+N 380 380 380 430 { lab=clk_out_div}
+N 400 380 400 430 { lab=clk_d}
+N 420 380 420 430 { lab=clk_2_f}
+N 440 380 440 430 { lab=s0n}
+N 460 380 460 430 { lab=s1n}
+N 480 380 480 430 { lab=out_div}
+N -160 90 -160 120 { lab=D1}
+N -110 90 -110 120 { lab=S1}
+N -80 90 -80 120 { lab=S0}
+N -50 90 -50 120 { lab=MC}
+N -20 -110 -20 -80 { lab=vss}
+N -20 -200 -20 -170 { lab=D1}
+N -390 -320 -390 -290 { lab=vss}
+N -390 -410 -390 -380 { lab=S1}
+N -60 -320 -60 -290 { lab=vss}
+N -60 -410 -60 -380 { lab=S0}
+N 280 -320 280 -290 { lab=vss}
+N 280 -410 280 -380 { lab=MC}
+C {vsource.sym} -620 -150 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -550 -150 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -470 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -620 -90 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -620 -210 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -90 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -470 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -210 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -470 -210 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 290 -180 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param vd1 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+.options GMIN = 1e-10
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(clk_0) = 0.0
+.ic v(n_clk_0) = 0.0
+.ic v(clk_1) = 0.0
+.ic v(n_clk_1) = 0.0
+.ic v(clk_pre) = 0.0
+.ic v(clk_5) = 0.0
+.ic v(clk_d) = 0.0
+.ic v(clk_2_f) = 0.0
+.ic v(s1n) = 0.0
+.ic v(s0n) = 0.0
+.ic v(out_div) = 0.0
+
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+ let T = wTosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14 v(out_div)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_div)
+ plot v(out_div) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+.end
+"}
+C {vsource.sym} -100 -140 0 0 {name=VD0 value=\{vd0\}}
+C {lab_pin.sym} -100 -80 3 0 {name=l52 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -100 -200 1 0 {name=l53 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -590 50 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -590 470 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -490 120 2 0 {name=l23 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -590 410 0 0 {name=I0 value=\{iref\}}
+C {noconn.sym} -490 140 2 0 {name=l75}
+C {noconn.sym} -490 160 2 0 {name=l76}
+C {noconn.sym} -490 180 2 0 {name=l77}
+C {noconn.sym} -490 200 2 0 {name=l78}
+C {noconn.sym} -490 220 2 0 {name=l79}
+C {noconn.sym} -490 240 2 0 {name=l80}
+C {noconn.sym} -490 260 2 0 {name=l81}
+C {noconn.sym} -490 280 2 0 {name=l82}
+C {noconn.sym} -490 300 2 0 {name=l83}
+C {lab_pin.sym} 400 90 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 440 90 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -260 80 1 0 {name=l9 sig_type=std_logic lab=iref_cp}
+C {lab_pin.sym} -200 90 1 0 {name=l10 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -360 250 2 1 {name=l11 sig_type=std_logic lab=A}
+C {lab_wire.sym} 620 250 0 1 {name=l61 sig_type=std_logic lab=out_to_pad}
+C {noconn.sym} 340 430 1 1 {name=l66}
+C {noconn.sym} 320 430 1 1 {name=l67}
+C {noconn.sym} 300 430 1 1 {name=l68}
+C {noconn.sym} 280 430 1 1 {name=l69}
+C {noconn.sym} 260 430 1 1 {name=l70}
+C {noconn.sym} 180 430 1 1 {name=l24}
+C {noconn.sym} 160 430 1 1 {name=l42}
+C {noconn.sym} 140 430 1 1 {name=l43}
+C {noconn.sym} 120 430 1 1 {name=l44}
+C {noconn.sym} -100 480 3 0 {name=l33}
+C {noconn.sym} -80 480 3 0 {name=l34}
+C {lab_wire.sym} -100 440 3 0 {name=l50 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} -80 440 3 0 {name=l51 sig_type=std_logic lab=pswitch}
+C {noconn.sym} -60 480 3 0 {name=l56}
+C {lab_wire.sym} -60 440 3 0 {name=l57 sig_type=std_logic lab=biasp}
+C {noconn.sym} -280 480 3 0 {name=l54}
+C {lab_wire.sym} -280 440 3 0 {name=l55 sig_type=std_logic lab=pfd_reset}
+C {noconn.sym} -260 480 3 0 {name=l12}
+C {lab_wire.sym} -260 440 3 0 {name=l13 sig_type=std_logic lab=QA}
+C {noconn.sym} -240 480 3 0 {name=l15}
+C {lab_wire.sym} -240 440 3 0 {name=l16 sig_type=std_logic lab=QB}
+C {noconn.sym} -200 480 3 0 {name=l17}
+C {lab_wire.sym} -200 440 3 0 {name=l18 sig_type=std_logic lab=Up}
+C {noconn.sym} -180 480 3 0 {name=l20}
+C {lab_wire.sym} -180 440 3 0 {name=l21 sig_type=std_logic lab=nUp}
+C {noconn.sym} -160 480 3 0 {name=l22}
+C {lab_wire.sym} -160 440 3 0 {name=l25 sig_type=std_logic lab=Down}
+C {noconn.sym} -140 480 3 0 {name=l26}
+C {lab_wire.sym} -140 440 3 0 {name=l27 sig_type=std_logic lab=nDown}
+C {noconn.sym} -20 430 1 1 {name=l28}
+C {noconn.sym} 20 480 3 0 {name=l29}
+C {lab_wire.sym} 20 440 3 0 {name=l30 sig_type=std_logic lab=vctrl}
+C {noconn.sym} 40 480 3 0 {name=l31}
+C {lab_wire.sym} 40 440 3 0 {name=l32 sig_type=std_logic lab=vco_out}
+C {noconn.sym} 60 480 3 0 {name=l35}
+C {lab_wire.sym} 60 440 3 0 {name=l37 sig_type=std_logic lab=vco_buffer_out}
+C {noconn.sym} 80 480 3 0 {name=l38}
+C {lab_wire.sym} 80 440 3 0 {name=l39 sig_type=std_logic lab=out_to_div}
+C {noconn.sym} 200 480 3 0 {name=l40}
+C {lab_wire.sym} 200 440 3 0 {name=l41 sig_type=std_logic lab=out_by_2}
+C {noconn.sym} 220 480 3 0 {name=l45}
+C {lab_wire.sym} 220 440 3 0 {name=l46 sig_type=std_logic lab=n_out_by_2}
+C {noconn.sym} 360 480 3 0 {name=l47}
+C {lab_wire.sym} 360 440 3 0 {name=l49 sig_type=std_logic lab=clk_5}
+C {lab_wire.sym} -20 390 3 0 {name=l58 sig_type=std_logic lab=lf_vc}
+C {lab_wire.sym} 120 420 3 0 {name=l59 sig_type=std_logic lab=out_div_2}
+C {lab_wire.sym} 140 420 3 0 {name=l60 sig_type=std_logic lab=n_out_div_2}
+C {lab_wire.sym} 160 420 3 0 {name=l62 sig_type=std_logic lab=out_buffer_div_2}
+C {lab_wire.sym} 180 420 3 0 {name=l63 sig_type=std_logic lab=n_out_buffer_div_2}
+C {lab_wire.sym} 260 420 3 0 {name=l64 sig_type=std_logic lab=clk_0}
+C {lab_wire.sym} 280 420 3 0 {name=l65 sig_type=std_logic lab=n_clk_0}
+C {lab_wire.sym} 300 420 3 0 {name=l71 sig_type=std_logic lab=clk_1}
+C {lab_wire.sym} 320 420 3 0 {name=l72 sig_type=std_logic lab=n_clk_1}
+C {lab_wire.sym} 340 420 3 0 {name=l73 sig_type=std_logic lab=clk_pre}
+C {bias.sym} -590 210 0 0 {name=x2}
+C {netlist_not_shown.sym} 460 -180 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {capa.sym} 660 310 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 660 370 3 0 {name=l48 sig_type=std_logic lab=vss}
+C {noconn.sym} 520 430 3 0 {name=l74}
+C {lab_wire.sym} 520 390 3 0 {name=l84 sig_type=std_logic lab=out_to_buffer}
+C {top_pll_v3.sym} 80 250 0 0 {name=x1}
+C {noconn.sym} 380 430 1 1 {name=l85}
+C {lab_wire.sym} 380 420 3 0 {name=l86 sig_type=std_logic lab=clk_out_div}
+C {noconn.sym} 400 430 1 1 {name=l87}
+C {lab_wire.sym} 400 420 3 0 {name=l88 sig_type=std_logic lab=clk_d}
+C {noconn.sym} 420 430 1 1 {name=l89}
+C {lab_wire.sym} 420 420 3 0 {name=l90 sig_type=std_logic lab=clk_2_f}
+C {noconn.sym} 440 430 1 1 {name=l91}
+C {lab_wire.sym} 440 420 3 0 {name=l92 sig_type=std_logic lab=s0n}
+C {noconn.sym} 460 430 1 1 {name=l93}
+C {lab_wire.sym} 460 420 3 0 {name=l94 sig_type=std_logic lab=s1n}
+C {noconn.sym} 480 430 1 1 {name=l95}
+C {lab_wire.sym} 480 420 3 0 {name=l96 sig_type=std_logic lab=out_div}
+C {lab_pin.sym} -160 90 1 0 {name=l97 sig_type=std_logic lab=D1}
+C {lab_pin.sym} -110 90 1 0 {name=l98 sig_type=std_logic lab=S1}
+C {lab_pin.sym} -80 90 1 0 {name=l99 sig_type=std_logic lab=S0}
+C {lab_pin.sym} -50 90 1 0 {name=l100 sig_type=std_logic lab=MC}
+C {vsource.sym} -20 -140 0 0 {name=VD1 value=\{vd1\}}
+C {lab_pin.sym} -20 -80 3 0 {name=l101 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -20 -200 1 0 {name=l102 sig_type=std_logic lab=D1}
+C {lab_pin.sym} -390 -290 3 0 {name=l103 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -390 -410 1 0 {name=l104 sig_type=std_logic lab=S1}
+C {vsource.sym} -390 -350 0 0 {name=VMC value=\{vin\}
+*value="PULSE(\{vin\} \{vin\} 0 1p 1p 400n 800n) DC \{vin\} AC 0"}
+C {lab_pin.sym} -60 -290 3 0 {name=l105 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -60 -410 1 0 {name=l106 sig_type=std_logic lab=S0}
+C {vsource.sym} -60 -350 0 0 {name=VMC1 value=\{vin\}
+*value="PULSE(\{vin\} \{vin\} 0 1p 1p 200n 400n) DC \{vin\} AC 0"}
+C {lab_pin.sym} 280 -290 3 0 {name=l107 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 280 -410 1 0 {name=l108 sig_type=std_logic lab=MC}
+C {vsource.sym} 280 -350 0 0 {name=VMC2 value=\{vin\}
+*value="PULSE(0 \{vin\} 0 1p 1p 100n 200n) DC \{vin\} AC 0"}
diff --git a/xschem/tb_top_pll_v3_pex_c.sch b/xschem/tb_top_pll_v3_pex_c.sch
new file mode 100644
index 0000000..6b3f76e
--- /dev/null
+++ b/xschem/tb_top_pll_v3_pex_c.sch
@@ -0,0 +1,304 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -620 -120 -620 -90 { lab=GND}
+N -470 -120 -470 -90 { lab=vss}
+N -550 -120 -550 -90 { lab=vss}
+N -620 -210 -620 -180 { lab=vss}
+N -470 -210 -470 -180 { lab=A}
+N -550 -210 -550 -180 { lab=vdd}
+N -100 -110 -100 -80 { lab=vss}
+N -100 -200 -100 -170 { lab=D0}
+N -590 50 -590 80 { lab=vdd}
+N -610 440 -610 470 { lab=vss}
+N -530 120 -490 120 { lab=iref_cp}
+N -610 350 -610 380 { lab=#net1}
+N -610 340 -610 350 { lab=#net1}
+N -530 140 -490 140 { lab=#net2}
+N -530 160 -490 160 { lab=#net3}
+N -530 180 -490 180 { lab=#net4}
+N -530 200 -490 200 { lab=#net5}
+N -530 220 -490 220 { lab=#net6}
+N -530 240 -490 240 { lab=#net7}
+N -530 260 -490 260 { lab=#net8}
+N -530 280 -490 280 { lab=#net9}
+N -530 300 -490 300 { lab=#net10}
+N 400 90 400 120 { lab=vdd}
+N 440 90 440 120 { lab=vss}
+N -260 80 -260 120 { lab=iref_cp}
+N -200 90 -200 120 { lab=D0}
+N -360 250 -330 250 { lab=A}
+N 570 250 610 250 { lab=out_to_pad}
+N 610 250 660 250 { lab=out_to_pad}
+N 340 380 340 430 { lab=clk_pre}
+N 320 380 320 430 { lab=n_clk_1}
+N 300 380 300 430 { lab=clk_1}
+N 280 380 280 430 { lab=n_clk_0}
+N 260 380 260 430 { lab=clk_0}
+N 180 380 180 430 { lab=n_out_buffer_div_2}
+N 160 380 160 430 { lab=out_buffer_div_2}
+N 140 380 140 430 { lab=n_out_div_2}
+N 120 380 120 430 { lab=out_div_2}
+N -100 430 -100 480 { lab=nswitch}
+N -80 430 -80 480 { lab=pswitch}
+N -60 430 -60 480 { lab=biasp}
+N -60 380 -60 430 { lab=biasp}
+N -80 380 -80 430 { lab=pswitch}
+N -100 380 -100 430 { lab=nswitch}
+N -280 430 -280 480 { lab=pfd_reset}
+N -280 380 -280 430 { lab=pfd_reset}
+N -260 430 -260 480 { lab=QA}
+N -260 380 -260 430 { lab=QA}
+N -240 430 -240 480 { lab=QB}
+N -240 380 -240 430 { lab=QB}
+N -200 430 -200 480 { lab=Up}
+N -200 380 -200 430 { lab=Up}
+N -180 430 -180 480 { lab=nUp}
+N -180 380 -180 430 { lab=nUp}
+N -160 430 -160 480 { lab=Down}
+N -160 380 -160 430 { lab=Down}
+N -140 430 -140 480 { lab=nDown}
+N -140 380 -140 430 { lab=nDown}
+N -20 380 -20 430 { lab=lf_vc}
+N 20 430 20 480 { lab=vctrl}
+N 20 380 20 430 { lab=vctrl}
+N 40 430 40 480 { lab=vco_out}
+N 40 380 40 430 { lab=vco_out}
+N 60 430 60 480 { lab=vco_buffer_out}
+N 60 380 60 430 { lab=vco_buffer_out}
+N 80 430 80 480 { lab=out_to_div}
+N 80 380 80 430 { lab=out_to_div}
+N 200 430 200 480 { lab=out_by_2}
+N 200 380 200 430 { lab=out_by_2}
+N 220 430 220 480 { lab=n_out_by_2}
+N 220 380 220 430 { lab=n_out_by_2}
+N 360 430 360 480 { lab=clk_5}
+N 360 380 360 430 { lab=clk_5}
+N 660 250 660 280 { lab=out_to_pad}
+N 660 340 660 370 { lab=vss}
+N 520 380 520 430 { lab=out_to_buffer}
+N 380 380 380 430 { lab=clk_out_div}
+N 400 380 400 430 { lab=clk_d}
+N 420 380 420 430 { lab=clk_2_f}
+N 440 380 440 430 { lab=s0n}
+N 460 380 460 430 { lab=s1n}
+N 480 380 480 430 { lab=out_div}
+N -160 90 -160 120 { lab=D1}
+N -110 90 -110 120 { lab=S1}
+N -80 90 -80 120 { lab=S0}
+N -50 90 -50 120 { lab=MC}
+N -20 -110 -20 -80 { lab=vss}
+N -20 -200 -20 -170 { lab=D1}
+N -390 -320 -390 -290 { lab=vss}
+N -390 -410 -390 -380 { lab=S1}
+N -60 -320 -60 -290 { lab=vss}
+N -60 -410 -60 -380 { lab=S0}
+N 280 -320 280 -290 { lab=vss}
+N 280 -410 280 -380 { lab=MC}
+N -570 340 -570 370 { lab=vss}
+C {vsource.sym} -620 -150 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -550 -150 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -470 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -620 -90 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -620 -210 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -90 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -470 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -210 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -470 -210 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 290 -180 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param vd1 = 0.0
+
+.options TEMP = 0.0
+.options RSHUNT = 1e20
+.options GMIN = 1e-10
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/top_pll_v3_pex_c.spice
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(clk_0) = 0.0
+.ic v(n_clk_0) = 0.0
+.ic v(clk_1) = 0.0
+.ic v(n_clk_1) = 0.0
+.ic v(clk_pre) = 0.0
+.ic v(clk_5) = 0.0
+.ic v(clk_d) = 0.0
+.ic v(clk_2_f) = 0.0
+.ic v(s1n) = 0.0
+.ic v(s0n) = 0.0
+.ic v(out_div) = 0.0
+
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+ let T = wTosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14 v(out_div)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_div)
+ plot v(out_div) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+.end
+"}
+C {vsource.sym} -100 -140 0 0 {name=VD0 value=\{vd0\}}
+C {lab_pin.sym} -100 -80 3 0 {name=l52 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -100 -200 1 0 {name=l53 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -590 50 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -610 470 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -490 120 2 0 {name=l23 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -610 410 0 0 {name=I0 value=\{iref\}}
+C {noconn.sym} -490 140 2 0 {name=l75}
+C {noconn.sym} -490 160 2 0 {name=l76}
+C {noconn.sym} -490 180 2 0 {name=l77}
+C {noconn.sym} -490 200 2 0 {name=l78}
+C {noconn.sym} -490 220 2 0 {name=l79}
+C {noconn.sym} -490 240 2 0 {name=l80}
+C {noconn.sym} -490 260 2 0 {name=l81}
+C {noconn.sym} -490 280 2 0 {name=l82}
+C {noconn.sym} -490 300 2 0 {name=l83}
+C {lab_pin.sym} 400 90 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 440 90 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -260 80 1 0 {name=l9 sig_type=std_logic lab=iref_cp}
+C {lab_pin.sym} -200 90 1 0 {name=l10 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -360 250 2 1 {name=l11 sig_type=std_logic lab=A}
+C {lab_wire.sym} 620 250 0 1 {name=l61 sig_type=std_logic lab=out_to_pad}
+C {noconn.sym} 340 430 1 1 {name=l66}
+C {noconn.sym} 320 430 1 1 {name=l67}
+C {noconn.sym} 300 430 1 1 {name=l68}
+C {noconn.sym} 280 430 1 1 {name=l69}
+C {noconn.sym} 260 430 1 1 {name=l70}
+C {noconn.sym} 180 430 1 1 {name=l24}
+C {noconn.sym} 160 430 1 1 {name=l42}
+C {noconn.sym} 140 430 1 1 {name=l43}
+C {noconn.sym} 120 430 1 1 {name=l44}
+C {noconn.sym} -100 480 3 0 {name=l33}
+C {noconn.sym} -80 480 3 0 {name=l34}
+C {lab_wire.sym} -100 440 3 0 {name=l50 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} -80 440 3 0 {name=l51 sig_type=std_logic lab=pswitch}
+C {noconn.sym} -60 480 3 0 {name=l56}
+C {lab_wire.sym} -60 440 3 0 {name=l57 sig_type=std_logic lab=biasp}
+C {noconn.sym} -280 480 3 0 {name=l54}
+C {lab_wire.sym} -280 440 3 0 {name=l55 sig_type=std_logic lab=pfd_reset}
+C {noconn.sym} -260 480 3 0 {name=l12}
+C {lab_wire.sym} -260 440 3 0 {name=l13 sig_type=std_logic lab=QA}
+C {noconn.sym} -240 480 3 0 {name=l15}
+C {lab_wire.sym} -240 440 3 0 {name=l16 sig_type=std_logic lab=QB}
+C {noconn.sym} -200 480 3 0 {name=l17}
+C {lab_wire.sym} -200 440 3 0 {name=l18 sig_type=std_logic lab=Up}
+C {noconn.sym} -180 480 3 0 {name=l20}
+C {lab_wire.sym} -180 440 3 0 {name=l21 sig_type=std_logic lab=nUp}
+C {noconn.sym} -160 480 3 0 {name=l22}
+C {lab_wire.sym} -160 440 3 0 {name=l25 sig_type=std_logic lab=Down}
+C {noconn.sym} -140 480 3 0 {name=l26}
+C {lab_wire.sym} -140 440 3 0 {name=l27 sig_type=std_logic lab=nDown}
+C {noconn.sym} -20 430 1 1 {name=l28}
+C {noconn.sym} 20 480 3 0 {name=l29}
+C {lab_wire.sym} 20 440 3 0 {name=l30 sig_type=std_logic lab=vctrl}
+C {noconn.sym} 40 480 3 0 {name=l31}
+C {lab_wire.sym} 40 440 3 0 {name=l32 sig_type=std_logic lab=vco_out}
+C {noconn.sym} 60 480 3 0 {name=l35}
+C {lab_wire.sym} 60 440 3 0 {name=l37 sig_type=std_logic lab=vco_buffer_out}
+C {noconn.sym} 80 480 3 0 {name=l38}
+C {lab_wire.sym} 80 440 3 0 {name=l39 sig_type=std_logic lab=out_to_div}
+C {noconn.sym} 200 480 3 0 {name=l40}
+C {lab_wire.sym} 200 440 3 0 {name=l41 sig_type=std_logic lab=out_by_2}
+C {noconn.sym} 220 480 3 0 {name=l45}
+C {lab_wire.sym} 220 440 3 0 {name=l46 sig_type=std_logic lab=n_out_by_2}
+C {noconn.sym} 360 480 3 0 {name=l47}
+C {lab_wire.sym} 360 440 3 0 {name=l49 sig_type=std_logic lab=clk_5}
+C {lab_wire.sym} -20 390 3 0 {name=l58 sig_type=std_logic lab=lf_vc}
+C {lab_wire.sym} 120 420 3 0 {name=l59 sig_type=std_logic lab=out_div_2}
+C {lab_wire.sym} 140 420 3 0 {name=l60 sig_type=std_logic lab=n_out_div_2}
+C {lab_wire.sym} 160 420 3 0 {name=l62 sig_type=std_logic lab=out_buffer_div_2}
+C {lab_wire.sym} 180 420 3 0 {name=l63 sig_type=std_logic lab=n_out_buffer_div_2}
+C {lab_wire.sym} 260 420 3 0 {name=l64 sig_type=std_logic lab=clk_0}
+C {lab_wire.sym} 280 420 3 0 {name=l65 sig_type=std_logic lab=n_clk_0}
+C {lab_wire.sym} 300 420 3 0 {name=l71 sig_type=std_logic lab=clk_1}
+C {lab_wire.sym} 320 420 3 0 {name=l72 sig_type=std_logic lab=n_clk_1}
+C {lab_wire.sym} 340 420 3 0 {name=l73 sig_type=std_logic lab=clk_pre}
+C {capa.sym} 660 310 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 660 370 3 0 {name=l48 sig_type=std_logic lab=vss}
+C {noconn.sym} 520 430 3 0 {name=l74}
+C {lab_wire.sym} 520 390 3 0 {name=l84 sig_type=std_logic lab=out_to_buffer}
+C {noconn.sym} 380 430 1 1 {name=l85}
+C {lab_wire.sym} 380 420 3 0 {name=l86 sig_type=std_logic lab=clk_out_div}
+C {noconn.sym} 400 430 1 1 {name=l87}
+C {lab_wire.sym} 400 420 3 0 {name=l88 sig_type=std_logic lab=clk_d}
+C {noconn.sym} 420 430 1 1 {name=l89}
+C {lab_wire.sym} 420 420 3 0 {name=l90 sig_type=std_logic lab=clk_2_f}
+C {noconn.sym} 440 430 1 1 {name=l91}
+C {lab_wire.sym} 440 420 3 0 {name=l92 sig_type=std_logic lab=s0n}
+C {noconn.sym} 460 430 1 1 {name=l93}
+C {lab_wire.sym} 460 420 3 0 {name=l94 sig_type=std_logic lab=s1n}
+C {noconn.sym} 480 430 1 1 {name=l95}
+C {lab_wire.sym} 480 420 3 0 {name=l96 sig_type=std_logic lab=out_div}
+C {lab_pin.sym} -160 90 1 0 {name=l97 sig_type=std_logic lab=D1}
+C {lab_pin.sym} -110 90 1 0 {name=l98 sig_type=std_logic lab=S1}
+C {lab_pin.sym} -80 90 1 0 {name=l99 sig_type=std_logic lab=S0}
+C {lab_pin.sym} -50 90 1 0 {name=l100 sig_type=std_logic lab=MC}
+C {vsource.sym} -20 -140 0 0 {name=VD1 value=\{vd1\}}
+C {lab_pin.sym} -20 -80 3 0 {name=l101 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -20 -200 1 0 {name=l102 sig_type=std_logic lab=D1}
+C {lab_pin.sym} -390 -290 3 0 {name=l103 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -390 -410 1 0 {name=l104 sig_type=std_logic lab=S1}
+C {vsource.sym} -390 -350 0 0 {name=VMC value=\{vin\}
+*value="PULSE(\{vin\} \{vin\} 0 1p 1p 400n 800n) DC \{vin\} AC 0"}
+C {lab_pin.sym} -60 -290 3 0 {name=l105 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -60 -410 1 0 {name=l106 sig_type=std_logic lab=S0}
+C {vsource.sym} -60 -350 0 0 {name=VMC1 value=\{vin\}
+*value="PULSE(\{vin\} \{vin\} 0 1p 1p 200n 400n) DC \{vin\} AC 0"}
+C {lab_pin.sym} 280 -290 3 0 {name=l107 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 280 -410 1 0 {name=l108 sig_type=std_logic lab=MC}
+C {vsource.sym} 280 -350 0 0 {name=VMC2 value=\{vin\}
+*value="PULSE(0 \{vin\} 0 1p 1p 100n 200n) DC \{vin\} AC 0"}
+C {bias_pex_c.sym} -590 210 0 0 {name=x1}
+C {lab_pin.sym} -570 370 3 0 {name=l36 sig_type=std_logic lab=vss}
+C {top_pll_v3_pex_c.sym} 80 250 0 0 {name=x2}
diff --git a/xschem/tb_top_pll_v3_pex_no_integration.sch b/xschem/tb_top_pll_v3_pex_no_integration.sch
new file mode 100644
index 0000000..e292a08
--- /dev/null
+++ b/xschem/tb_top_pll_v3_pex_no_integration.sch
@@ -0,0 +1,312 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -620 -120 -620 -90 { lab=GND}
+N -470 -120 -470 -90 { lab=vss}
+N -550 -120 -550 -90 { lab=vss}
+N -620 -210 -620 -180 { lab=vss}
+N -470 -210 -470 -180 { lab=A}
+N -550 -210 -550 -180 { lab=vdd}
+N -100 -110 -100 -80 { lab=vss}
+N -100 -200 -100 -170 { lab=D0}
+N -590 50 -590 80 { lab=vdd}
+N -590 440 -590 470 { lab=vss}
+N -530 120 -490 120 { lab=iref_cp}
+N -590 350 -590 380 { lab=#net1}
+N -590 340 -590 350 { lab=#net1}
+N -530 140 -490 140 { lab=#net2}
+N -530 160 -490 160 { lab=#net3}
+N -530 180 -490 180 { lab=#net4}
+N -530 200 -490 200 { lab=#net5}
+N -530 220 -490 220 { lab=#net6}
+N -530 240 -490 240 { lab=#net7}
+N -530 260 -490 260 { lab=#net8}
+N -530 280 -490 280 { lab=#net9}
+N -530 300 -490 300 { lab=#net10}
+N 400 90 400 120 { lab=vdd}
+N 440 90 440 120 { lab=vss}
+N -260 80 -260 120 { lab=iref_cp}
+N -200 90 -200 120 { lab=D0}
+N -360 250 -330 250 { lab=A}
+N 570 250 610 250 { lab=out_to_pad}
+N 610 250 660 250 { lab=out_to_pad}
+N 340 380 340 430 { lab=clk_pre}
+N 320 380 320 430 { lab=n_clk_1}
+N 300 380 300 430 { lab=clk_1}
+N 280 380 280 430 { lab=n_clk_0}
+N 260 380 260 430 { lab=clk_0}
+N 180 380 180 430 { lab=n_out_buffer_div_2}
+N 160 380 160 430 { lab=out_buffer_div_2}
+N 140 380 140 430 { lab=n_out_div_2}
+N 120 380 120 430 { lab=out_div_2}
+N -100 430 -100 480 { lab=nswitch}
+N -80 430 -80 480 { lab=pswitch}
+N -60 430 -60 480 { lab=biasp}
+N -60 380 -60 430 { lab=biasp}
+N -80 380 -80 430 { lab=pswitch}
+N -100 380 -100 430 { lab=nswitch}
+N -280 430 -280 480 { lab=pfd_reset}
+N -280 380 -280 430 { lab=pfd_reset}
+N -260 430 -260 480 { lab=QA}
+N -260 380 -260 430 { lab=QA}
+N -240 430 -240 480 { lab=QB}
+N -240 380 -240 430 { lab=QB}
+N -200 430 -200 480 { lab=Up}
+N -200 380 -200 430 { lab=Up}
+N -180 430 -180 480 { lab=nUp}
+N -180 380 -180 430 { lab=nUp}
+N -160 430 -160 480 { lab=Down}
+N -160 380 -160 430 { lab=Down}
+N -140 430 -140 480 { lab=nDown}
+N -140 380 -140 430 { lab=nDown}
+N -20 380 -20 430 { lab=lf_vc}
+N 20 430 20 480 { lab=vctrl}
+N 20 380 20 430 { lab=vctrl}
+N 40 430 40 480 { lab=vco_out}
+N 40 380 40 430 { lab=vco_out}
+N 60 430 60 480 { lab=vco_buffer_out}
+N 60 380 60 430 { lab=vco_buffer_out}
+N 80 430 80 480 { lab=out_to_div}
+N 80 380 80 430 { lab=out_to_div}
+N 200 430 200 480 { lab=out_by_2}
+N 200 380 200 430 { lab=out_by_2}
+N 220 430 220 480 { lab=n_out_by_2}
+N 220 380 220 430 { lab=n_out_by_2}
+N 360 430 360 480 { lab=clk_5}
+N 360 380 360 430 { lab=clk_5}
+N 660 250 660 280 { lab=out_to_pad}
+N 660 340 660 370 { lab=vss}
+N 520 380 520 430 { lab=out_to_buffer}
+N 380 380 380 430 { lab=clk_out_div}
+N 400 380 400 430 { lab=clk_d}
+N 420 380 420 430 { lab=clk_2_f}
+N 440 380 440 430 { lab=s0n}
+N 460 380 460 430 { lab=s1n}
+N 480 380 480 430 { lab=out_div}
+N -160 90 -160 120 { lab=D1}
+N -110 90 -110 120 { lab=S1}
+N -80 90 -80 120 { lab=S0}
+N -50 90 -50 120 { lab=MC}
+N -20 -110 -20 -80 { lab=vss}
+N -20 -200 -20 -170 { lab=D1}
+N -390 -320 -390 -290 { lab=vss}
+N -390 -410 -390 -380 { lab=S1}
+N -60 -320 -60 -290 { lab=vss}
+N -60 -410 -60 -380 { lab=S0}
+N 280 -320 280 -290 { lab=vss}
+N 280 -410 280 -380 { lab=MC}
+C {vsource.sym} -620 -150 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -550 -150 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -470 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -620 -90 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -620 -210 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -90 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -470 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -210 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -470 -210 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 290 -180 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param vd1 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+.options GMIN = 1e-10
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/charge_pump_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/loop_filter_v2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/ring_osc_buffer_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/buffer_salida_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/freq_div_pex_c.spice
+
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(clk_0) = 0.0
+.ic v(n_clk_0) = 0.0
+.ic v(clk_1) = 0.0
+.ic v(n_clk_1) = 0.0
+.ic v(clk_pre) = 0.0
+.ic v(clk_5) = 0.0
+.ic v(clk_d) = 0.0
+.ic v(clk_2_f) = 0.0
+.ic v(s1n) = 0.0
+.ic v(s0n) = 0.0
+.ic v(out_div) = 0.0
+
+
+* Simulation
+.control
+ tran 0.01ns 2us
+ meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+ let T = Tosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14 v(out_div)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_div)
+ plot v(out_div) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+.end
+"}
+C {vsource.sym} -100 -140 0 0 {name=VD0 value=\{vd0\}}
+C {lab_pin.sym} -100 -80 3 0 {name=l52 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -100 -200 1 0 {name=l53 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -590 50 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -590 470 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -490 120 2 0 {name=l23 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -590 410 0 0 {name=I0 value=\{iref\}}
+C {noconn.sym} -490 140 2 0 {name=l75}
+C {noconn.sym} -490 160 2 0 {name=l76}
+C {noconn.sym} -490 180 2 0 {name=l77}
+C {noconn.sym} -490 200 2 0 {name=l78}
+C {noconn.sym} -490 220 2 0 {name=l79}
+C {noconn.sym} -490 240 2 0 {name=l80}
+C {noconn.sym} -490 260 2 0 {name=l81}
+C {noconn.sym} -490 280 2 0 {name=l82}
+C {noconn.sym} -490 300 2 0 {name=l83}
+C {lab_pin.sym} 400 90 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 440 90 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -260 80 1 0 {name=l9 sig_type=std_logic lab=iref_cp}
+C {lab_pin.sym} -200 90 1 0 {name=l10 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -360 250 2 1 {name=l11 sig_type=std_logic lab=A}
+C {lab_wire.sym} 620 250 0 1 {name=l61 sig_type=std_logic lab=out_to_pad}
+C {noconn.sym} 340 430 1 1 {name=l66}
+C {noconn.sym} 320 430 1 1 {name=l67}
+C {noconn.sym} 300 430 1 1 {name=l68}
+C {noconn.sym} 280 430 1 1 {name=l69}
+C {noconn.sym} 260 430 1 1 {name=l70}
+C {noconn.sym} 180 430 1 1 {name=l24}
+C {noconn.sym} 160 430 1 1 {name=l42}
+C {noconn.sym} 140 430 1 1 {name=l43}
+C {noconn.sym} 120 430 1 1 {name=l44}
+C {noconn.sym} -100 480 3 0 {name=l33}
+C {noconn.sym} -80 480 3 0 {name=l34}
+C {lab_wire.sym} -100 440 3 0 {name=l50 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} -80 440 3 0 {name=l51 sig_type=std_logic lab=pswitch}
+C {noconn.sym} -60 480 3 0 {name=l56}
+C {lab_wire.sym} -60 440 3 0 {name=l57 sig_type=std_logic lab=biasp}
+C {noconn.sym} -280 480 3 0 {name=l54}
+C {lab_wire.sym} -280 440 3 0 {name=l55 sig_type=std_logic lab=pfd_reset}
+C {noconn.sym} -260 480 3 0 {name=l12}
+C {lab_wire.sym} -260 440 3 0 {name=l13 sig_type=std_logic lab=QA}
+C {noconn.sym} -240 480 3 0 {name=l15}
+C {lab_wire.sym} -240 440 3 0 {name=l16 sig_type=std_logic lab=QB}
+C {noconn.sym} -200 480 3 0 {name=l17}
+C {lab_wire.sym} -200 440 3 0 {name=l18 sig_type=std_logic lab=Up}
+C {noconn.sym} -180 480 3 0 {name=l20}
+C {lab_wire.sym} -180 440 3 0 {name=l21 sig_type=std_logic lab=nUp}
+C {noconn.sym} -160 480 3 0 {name=l22}
+C {lab_wire.sym} -160 440 3 0 {name=l25 sig_type=std_logic lab=Down}
+C {noconn.sym} -140 480 3 0 {name=l26}
+C {lab_wire.sym} -140 440 3 0 {name=l27 sig_type=std_logic lab=nDown}
+C {noconn.sym} -20 430 1 1 {name=l28}
+C {noconn.sym} 20 480 3 0 {name=l29}
+C {lab_wire.sym} 20 440 3 0 {name=l30 sig_type=std_logic lab=vctrl}
+C {noconn.sym} 40 480 3 0 {name=l31}
+C {lab_wire.sym} 40 440 3 0 {name=l32 sig_type=std_logic lab=vco_out}
+C {noconn.sym} 60 480 3 0 {name=l35}
+C {lab_wire.sym} 60 440 3 0 {name=l37 sig_type=std_logic lab=vco_buffer_out}
+C {noconn.sym} 80 480 3 0 {name=l38}
+C {lab_wire.sym} 80 440 3 0 {name=l39 sig_type=std_logic lab=out_to_div}
+C {noconn.sym} 200 480 3 0 {name=l40}
+C {lab_wire.sym} 200 440 3 0 {name=l41 sig_type=std_logic lab=out_by_2}
+C {noconn.sym} 220 480 3 0 {name=l45}
+C {lab_wire.sym} 220 440 3 0 {name=l46 sig_type=std_logic lab=n_out_by_2}
+C {noconn.sym} 360 480 3 0 {name=l47}
+C {lab_wire.sym} 360 440 3 0 {name=l49 sig_type=std_logic lab=clk_5}
+C {lab_wire.sym} -20 390 3 0 {name=l58 sig_type=std_logic lab=lf_vc}
+C {lab_wire.sym} 120 420 3 0 {name=l59 sig_type=std_logic lab=out_div_2}
+C {lab_wire.sym} 140 420 3 0 {name=l60 sig_type=std_logic lab=n_out_div_2}
+C {lab_wire.sym} 160 420 3 0 {name=l62 sig_type=std_logic lab=out_buffer_div_2}
+C {lab_wire.sym} 180 420 3 0 {name=l63 sig_type=std_logic lab=n_out_buffer_div_2}
+C {lab_wire.sym} 260 420 3 0 {name=l64 sig_type=std_logic lab=clk_0}
+C {lab_wire.sym} 280 420 3 0 {name=l65 sig_type=std_logic lab=n_clk_0}
+C {lab_wire.sym} 300 420 3 0 {name=l71 sig_type=std_logic lab=clk_1}
+C {lab_wire.sym} 320 420 3 0 {name=l72 sig_type=std_logic lab=n_clk_1}
+C {lab_wire.sym} 340 420 3 0 {name=l73 sig_type=std_logic lab=clk_pre}
+C {bias.sym} -590 210 0 0 {name=x2}
+C {netlist_not_shown.sym} 460 -180 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {capa.sym} 660 310 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 660 370 3 0 {name=l48 sig_type=std_logic lab=vss}
+C {noconn.sym} 520 430 3 0 {name=l74}
+C {lab_wire.sym} 520 390 3 0 {name=l84 sig_type=std_logic lab=out_to_buffer}
+C {noconn.sym} 380 430 1 1 {name=l85}
+C {lab_wire.sym} 380 420 3 0 {name=l86 sig_type=std_logic lab=clk_out_div}
+C {noconn.sym} 400 430 1 1 {name=l87}
+C {lab_wire.sym} 400 420 3 0 {name=l88 sig_type=std_logic lab=clk_d}
+C {noconn.sym} 420 430 1 1 {name=l89}
+C {lab_wire.sym} 420 420 3 0 {name=l90 sig_type=std_logic lab=clk_2_f}
+C {noconn.sym} 440 430 1 1 {name=l91}
+C {lab_wire.sym} 440 420 3 0 {name=l92 sig_type=std_logic lab=s0n}
+C {noconn.sym} 460 430 1 1 {name=l93}
+C {lab_wire.sym} 460 420 3 0 {name=l94 sig_type=std_logic lab=s1n}
+C {noconn.sym} 480 430 1 1 {name=l95}
+C {lab_wire.sym} 480 420 3 0 {name=l96 sig_type=std_logic lab=out_div}
+C {lab_pin.sym} -160 90 1 0 {name=l97 sig_type=std_logic lab=D1}
+C {lab_pin.sym} -110 90 1 0 {name=l98 sig_type=std_logic lab=S1}
+C {lab_pin.sym} -80 90 1 0 {name=l99 sig_type=std_logic lab=S0}
+C {lab_pin.sym} -50 90 1 0 {name=l100 sig_type=std_logic lab=MC}
+C {vsource.sym} -20 -140 0 0 {name=VD1 value=\{vd1\}}
+C {lab_pin.sym} -20 -80 3 0 {name=l101 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -20 -200 1 0 {name=l102 sig_type=std_logic lab=D1}
+C {lab_pin.sym} -390 -290 3 0 {name=l103 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -390 -410 1 0 {name=l104 sig_type=std_logic lab=S1}
+C {vsource.sym} -390 -350 0 0 {name=VMC value="PULSE(0.0 0.0 0 1p 1p 400n 800n) DC \{vin\} AC 0"}
+C {lab_pin.sym} -60 -290 3 0 {name=l105 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -60 -410 1 0 {name=l106 sig_type=std_logic lab=S0}
+C {vsource.sym} -60 -350 0 0 {name=VMC1 value="PULSE(\{vin\} \{vin\} 0 1p 1p 200n 400n) DC \{vin\} AC 0"}
+C {lab_pin.sym} 280 -290 3 0 {name=l107 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 280 -410 1 0 {name=l108 sig_type=std_logic lab=MC}
+C {vsource.sym} 280 -350 0 0 {name=VMC2 value="PULSE(\{vin\} \{vin\} 0 1p 1p 100n 200n) DC \{vin\} AC 0"}
+C {top_pll_v3_pex_no_integration.sym} 80 250 0 0 {name=x1}
diff --git a/xschem/top_pll_v3.sch b/xschem/top_pll_v3.sch
new file mode 100644
index 0000000..985ca90
--- /dev/null
+++ b/xschem/top_pll_v3.sch
@@ -0,0 +1,192 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -750 -360 -750 -330 { lab=vss}
+N -890 -270 -850 -270 { lab=in_ref}
+N -850 -270 -840 -270 { lab=in_ref}
+N -890 -190 -840 -190 { lab=out_div}
+N -790 -360 -790 -330 { lab=vdd}
+N -400 -250 -310 -250 { lab=nUp}
+N -400 -210 -310 -210 { lab=Down}
+N -360 -170 -310 -170 { lab=nDown}
+N -360 -290 -310 -290 { lab=Up}
+N 410 -330 410 -300 { lab=vdd}
+N 410 -160 410 -130 { lab=vss}
+N 530 260 570 260 { lab=out_to_div}
+N 330 -190 340 -190 { lab=vco_D0}
+N 230 -230 340 -230 { lab=vco_vctrl}
+N 480 -230 520 -230 { lab=vco_out}
+N -460 -170 -360 -170 { lab=nDown}
+N -460 -210 -400 -210 { lab=Down}
+N -460 -250 -400 -250 { lab=nUp}
+N -460 -290 -360 -290 { lab=Up}
+N -700 -190 -600 -190 { lab=pfd_QB}
+N -530 -360 -530 -330 { lab=vdd}
+N -530 -130 -530 -100 { lab=vss}
+N -890 -190 -890 260 { lab=out_div}
+N 330 -190 330 -150 { lab=vco_D0}
+N 180 150 180 180 { lab=vdd}
+N -210 -360 -210 -330 { lab=vdd}
+N -180 -360 -180 -330 { lab=vss}
+N -50 -230 -30 -230 { lab=vco_vctrl}
+N -270 -370 -270 -330 { lab=iref_cp}
+N 10 280 90 280 { lab=n_out_by_2}
+N 10 240 90 240 { lab=out_by_2}
+N -60 240 10 240 { lab=out_by_2}
+N -60 280 10 280 { lab=n_out_by_2}
+N -90 240 -60 240 { lab=out_by_2}
+N -90 280 -60 280 { lab=n_out_by_2}
+N -890 260 -470 260 { lab=out_div}
+N 60 -70 60 -40 { lab=vss}
+N 30 -230 90 -230 { lab=vco_vctrl}
+N 90 -230 230 -230 { lab=vco_vctrl}
+N 60 -230 60 -210 { lab=vco_vctrl}
+N 120 -140 160 -140 { lab=lf_vc}
+N 520 -230 580 -230 { lab=vco_out}
+N 620 -330 620 -300 { lab=vdd}
+N 660 -330 660 -300 { lab=vss}
+N 700 -250 740 -250 { lab=out_to_buffer}
+N 700 -210 750 -210 { lab=out_to_div}
+N 870 -210 870 260 { lab=out_to_div}
+N 570 260 750 260 { lab=out_to_div}
+N 640 -160 640 -120 { lab=out_first_buffer}
+N 750 -210 870 -210 { lab=out_to_div}
+N 750 260 870 260 { lab=out_to_div}
+N 230 260 530 260 { lab=out_to_div}
+N 140 150 140 180 { lab=vss}
+N -640 -300 -640 -270 { lab=pfd_QA}
+N -640 -190 -640 -160 { lab=pfd_QB}
+N -450 -310 -440 -310 { lab=Up}
+N -450 -310 -450 -290 { lab=Up}
+N -450 -270 -440 -270 { lab=nUp}
+N -450 -270 -450 -250 { lab=nUp}
+N -450 -230 -440 -230 { lab=Down}
+N -450 -230 -450 -210 { lab=Down}
+N -450 -190 -440 -190 { lab=nDown}
+N -450 -190 -450 -170 { lab=nDown}
+N -770 -130 -770 -100 { lab=pfd_reset}
+N -700 -270 -600 -270 { lab=pfd_QA}
+N -260 -130 -260 -100 { lab=cp_nswitch}
+N -230 -130 -230 -100 { lab=cp_pswitch}
+N -200 -130 -200 -100 { lab=cp_biasp}
+N -140 -230 -50 -230 { lab=vco_vctrl}
+N -30 -230 30 -230 { lab=vco_vctrl}
+N 160 -320 160 -240 { lab=vco_vctrl}
+N 160 -240 160 -230 { lab=vco_vctrl}
+N 520 -320 520 -230 { lab=vco_out}
+N 370 220 370 260 { lab=out_to_div}
+N 0 200 0 240 { lab=out_by_2}
+N 0 280 0 320 { lab=n_out_by_2}
+N 190 340 190 380 { lab=out_div_2}
+N 170 340 170 380 { lab=n_out_div_2}
+N 150 340 150 380 { lab=out_buffer_div_2}
+N 130 340 130 380 { lab=n_out_buffer_div_2}
+N -770 260 -770 300 { lab=out_div}
+N 740 -250 930 -250 { lab=out_to_buffer}
+N 810 -300 810 -250 { lab=out_to_buffer}
+N 970 -330 970 -300 { lab=vdd}
+N 970 -200 970 -170 { lab=vss}
+N 1060 -250 1100 -250 { lab=out_to_pad}
+N -470 260 -360 260 { lab=out_div}
+N -280 150 -280 180 { lab=vdd}
+N -300 150 -300 180 { lab=vss}
+N -130 150 -130 180 { lab=s_1}
+N -150 150 -150 180 { lab=s_0}
+N -170 150 -170 180 { lab=MC}
+N -120 390 -120 420 { lab=clk_0}
+N -140 390 -140 420 { lab=n_clk_0}
+N -160 390 -160 420 { lab=clk_1}
+N -180 390 -180 420 { lab=n_clk_1}
+N -120 350 -120 390 { lab=clk_0}
+N -140 340 -140 390 { lab=n_clk_0}
+N -160 340 -160 390 { lab=clk_1}
+N -180 340 -180 390 { lab=n_clk_1}
+N -120 340 -120 350 { lab=clk_0}
+N -200 390 -200 420 { lab=clk_pre}
+N -220 390 -220 420 { lab=clk_5}
+N -240 390 -240 420 { lab=clk_out_mux21}
+N -260 390 -260 420 { lab=clk_d}
+N -200 350 -200 390 { lab=clk_pre}
+N -220 340 -220 390 { lab=clk_5}
+N -240 340 -240 390 { lab=clk_out_mux21}
+N -260 340 -260 390 { lab=clk_d}
+N -200 340 -200 350 { lab=clk_pre}
+N -280 390 -280 420 { lab=clk_2_f}
+N -300 390 -300 420 { lab=s0n}
+N -320 390 -320 420 { lab=s1n}
+N -280 340 -280 390 { lab=clk_2_f}
+N -300 340 -300 390 { lab=s0n}
+N -320 340 -320 390 { lab=s1n}
+N -10 -140 0 -140 { lab=vco_D0}
+N -10 -140 -10 -100 { lab=vco_D0}
+C {lab_pin.sym} 410 -330 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -130 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -530 -360 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -530 -100 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 180 150 1 0 {name=l45 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -210 -360 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -180 -360 1 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 60 -40 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 620 -330 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 660 -330 1 0 {name=l40 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 150 1 0 {name=l12 sig_type=std_logic lab=vss}
+C {iopin.sym} -790 -360 3 0 {name=p1 lab=vdd}
+C {iopin.sym} -750 -360 3 0 {name=p2 lab=vss}
+C {ipin.sym} -890 -270 0 0 {name=p3 lab=in_ref}
+C {iopin.sym} -640 -300 3 0 {name=p4 lab=pfd_QA}
+C {iopin.sym} -640 -160 1 0 {name=p5 lab=pfd_QB}
+C {iopin.sym} -440 -310 0 0 {name=p6 lab=Up}
+C {iopin.sym} -440 -270 0 0 {name=p7 lab=nUp}
+C {iopin.sym} -440 -230 0 0 {name=p8 lab=Down}
+C {iopin.sym} -440 -190 0 0 {name=p9 lab=nDown}
+C {iopin.sym} -770 -100 1 0 {name=p10 lab=pfd_reset}
+C {iopin.sym} -260 -100 1 0 {name=p11 lab=cp_nswitch}
+C {iopin.sym} -230 -100 1 0 {name=p12 lab=cp_pswitch}
+C {iopin.sym} -200 -100 1 0 {name=p13 lab=cp_biasp}
+C {ipin.sym} -270 -370 1 0 {name=p14 lab=iref_cp}
+C {iopin.sym} 160 -140 0 0 {name=p15 lab=lf_vc}
+C {ipin.sym} 330 -150 3 0 {name=p16 lab=vco_D0}
+C {iopin.sym} 160 -320 3 0 {name=p17 lab=vco_vctrl}
+C {iopin.sym} 520 -320 3 0 {name=p18 lab=vco_out}
+C {iopin.sym} 640 -120 1 0 {name=p19 lab=out_first_buffer}
+C {iopin.sym} 810 -300 3 0 {name=p20 lab=out_to_buffer}
+C {iopin.sym} 370 220 3 0 {name=p21 lab=out_to_div}
+C {iopin.sym} 0 200 3 0 {name=p22 lab=out_by_2}
+C {iopin.sym} 0 320 1 0 {name=p23 lab=n_out_by_2}
+C {iopin.sym} 190 380 1 0 {name=p24 lab=out_div_2}
+C {iopin.sym} 170 380 1 0 {name=p25 lab=n_out_div_2}
+C {iopin.sym} 150 380 1 0 {name=p26 lab=out_buffer_div_2}
+C {iopin.sym} 130 380 1 0 {name=p27 lab=n_out_buffer_div_2}
+C {iopin.sym} -770 300 1 0 {name=p33 lab=out_div}
+C {lab_pin.sym} 970 -330 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 970 -170 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {opin.sym} 1100 -250 0 0 {name=p35 lab=out_to_pad}
+C {lab_pin.sym} -280 150 1 0 {name=l3 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -300 150 1 0 {name=l4 sig_type=std_logic lab=vss}
+C {iopin.sym} -120 420 1 0 {name=p48 sig_type=std_logic lab=clk_0}
+C {iopin.sym} -140 420 1 0 {name=p49 sig_type=std_logic lab=n_clk_0}
+C {iopin.sym} -160 420 1 0 {name=p50 sig_type=std_logic lab=clk_1}
+C {iopin.sym} -180 420 1 0 {name=p51 sig_type=std_logic lab=n_clk_1}
+C {iopin.sym} -200 420 1 0 {name=p52 sig_type=std_logic lab=clk_pre}
+C {iopin.sym} -220 420 1 0 {name=p53 sig_type=std_logic lab=clk_5}
+C {iopin.sym} -240 420 3 1 {name=p54 sig_type=std_logic lab=clk_out_mux21}
+C {iopin.sym} -260 420 1 0 {name=p55 sig_type=std_logic lab=clk_d}
+C {iopin.sym} -280 420 1 0 {name=p56 sig_type=std_logic lab=clk_2_f}
+C {iopin.sym} -300 420 1 0 {name=p57 sig_type=std_logic lab=s0n}
+C {iopin.sym} -320 420 1 0 {name=p58 sig_type=std_logic lab=s1n}
+C {ipin.sym} -170 150 1 0 {name=p28 sig_type=std_logic lab=MC}
+C {ipin.sym} -150 150 1 0 {name=p29 sig_type=std_logic lab=s_0}
+C {ipin.sym} -130 150 1 0 {name=p30 sig_type=std_logic lab=s_1}
+C {PFD.sym} -770 -230 0 0 {name=x1}
+C {pfd_cp_interface.sym} -530 -230 0 0 {name=x2}
+C {charge_pump.sym} -230 -230 0 0 {name=x3}
+C {csvco.sym} 410 -230 0 0 {name=x5}
+C {ring_osc_buffer.sym} 640 -230 0 0 {name=x6}
+C {buffer_salida.sym} 990 -250 0 0 {name=x7}
+C {div_by_2.sym} 160 260 0 1 {name=x8}
+C {freq_div.sym} -200 260 0 1 {name=x9}
+C {loop_filter_v2.sym} 60 -140 0 0 {name=x4}
+C {ipin.sym} -10 -100 3 0 {name=p31 lab=lf_D0}
diff --git a/xschem/top_pll_v3.sym b/xschem/top_pll_v3.sym
new file mode 100644
index 0000000..7c53df5
--- /dev/null
+++ b/xschem/top_pll_v3.sym
@@ -0,0 +1,208 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -340 -130 -340 -110 {}
+L 4 -410 0 -390 0 {}
+L 4 -380 110 340 110 {}
+L 4 470 -110 470 110 {}
+L 4 -390 -110 -390 100 {}
+L 4 -380 70 -380 100 {}
+L 4 -370 70 330 70 {}
+L 4 460 70 460 110 {}
+L 4 -380 -110 340 -110 {}
+L 4 -390 100 -390 110 {}
+L 4 -380 100 -380 110 {}
+L 4 -370 90 -370 110 {}
+L 4 -370 90 -310 90 {}
+L 4 -310 90 -310 110 {}
+L 4 -290 90 -290 110 {}
+L 4 -290 90 -210 90 {}
+L 4 -210 90 -210 110 {}
+L 4 -190 90 -190 110 {}
+L 4 -190 90 -130 90 {}
+L 4 -130 90 -130 110 {}
+L 4 -110 90 -110 110 {}
+L 4 -110 90 -90 90 {}
+L 4 -90 90 -90 110 {}
+L 4 -70 90 -70 110 {}
+L 4 -70 90 10 90 {}
+L 4 10 90 10 110 {}
+L 4 30 90 30 110 {}
+L 4 30 90 150 90 {}
+L 4 150 90 150 110 {}
+L 4 170 90 170 110 {}
+L 4 170 90 410 90 {}
+L 4 410 90 410 110 {}
+L 4 430 90 430 110 {}
+L 4 430 90 450 90 {}
+L 4 450 90 450 110 {}
+L 4 340 110 460 110 {}
+L 4 -390 110 -380 110 {}
+L 4 -380 70 -370 70 {}
+L 4 330 70 460 70 {}
+L 4 460 110 470 110 {}
+L 4 340 -110 470 -110 {}
+L 4 -390 -110 -380 -110 {}
+L 4 -290 -110 -290 -90 {}
+L 4 -290 -90 -270 -90 {}
+L 4 -270 -110 -270 -90 {}
+L 4 -210 -110 -210 -90 {}
+L 4 -210 -90 -120 -90 {}
+L 4 -120 -110 -120 -90 {}
+L 4 -250 -110 -250 -90 {}
+L 4 -250 -90 -230 -90 {}
+L 4 -230 -110 -230 -90 {}
+L 4 -310 -110 -310 -70 {}
+L 4 -310 -70 -100 -70 {}
+L 4 -100 -110 -100 -70 {}
+L 4 -280 -130 -280 -110 {}
+L 4 -240 -130 -240 -110 {}
+L 4 -190 -130 -190 -110 {}
+L 4 -160 -130 -160 -110 {}
+L 4 -130 -130 -130 -110 {}
+L 4 470 -0 490 0 {}
+L 7 360 -130 360 -110 {}
+L 7 320 -130 320 -110 {}
+L 7 -40 110 -40 130 {}
+L 7 -60 110 -60 130 {}
+L 7 -280 110 -280 130 {}
+L 7 -340 110 -340 130 {}
+L 7 440 110 440 130 {}
+L 7 -260 110 -260 130 {}
+L 7 -240 110 -240 130 {}
+L 7 -220 110 -220 130 {}
+L 7 -320 110 -320 130 {}
+L 7 -100 110 -100 130 {}
+L 7 -20 110 -20 130 {}
+L 7 -140 110 -140 130 {}
+L 7 -160 110 -160 130 {}
+L 7 -180 110 -180 130 {}
+L 7 -360 110 -360 130 {}
+L 7 120 110 120 130 {}
+L 7 0 110 0 130 {}
+L 7 400 110 400 130 {}
+L 7 140 110 140 130 {}
+L 7 60 110 60 130 {}
+L 7 40 110 40 130 {}
+L 7 80 110 80 130 {}
+L 7 100 110 100 130 {}
+L 7 200 110 200 130 {}
+L 7 380 110 380 130 {}
+L 7 360 110 360 130 {}
+L 7 340 110 340 130 {}
+L 7 320 110 320 130 {}
+L 7 300 110 300 130 {}
+L 7 280 110 280 130 {}
+L 7 260 110 260 130 {}
+L 7 240 110 240 130 {}
+L 7 220 110 220 130 {}
+L 7 180 110 180 130 {}
+B 5 -342.5 -132.5 -337.5 -127.5 {name=iref_cp dir=in }
+B 5 357.5 -132.5 362.5 -127.5 {name=vss dir=inout }
+B 5 317.5 -132.5 322.5 -127.5 {name=vdd dir=inout }
+B 5 -42.5 127.5 -37.5 132.5 {name=vco_out dir=inout }
+B 5 -62.5 127.5 -57.5 132.5 {name=vco_vctrl dir=inout }
+B 5 -282.5 127.5 -277.5 132.5 {name=Up dir=inout }
+B 5 -342.5 127.5 -337.5 132.5 {name=pfd_QA dir=inout }
+B 5 437.5 127.5 442.5 132.5 {name=out_to_buffer dir=inout }
+B 5 -412.5 -2.5 -407.5 2.5 {name=in_ref dir=in }
+B 5 -262.5 127.5 -257.5 132.5 {name=nUp dir=inout }
+B 5 487.5 -2.5 492.5 2.5 {name=out_to_pad dir=out }
+B 5 -242.5 127.5 -237.5 132.5 {name=Down dir=inout }
+B 5 -222.5 127.5 -217.5 132.5 {name=nDown dir=inout }
+B 5 -322.5 127.5 -317.5 132.5 {name=pfd_QB dir=inout }
+B 5 -282.5 -132.5 -277.5 -127.5 {name=lf_D0 dir=in }
+B 5 -102.5 127.5 -97.5 132.5 {name=lf_vc dir=inout }
+B 5 -22.5 127.5 -17.5 132.5 {name=out_first_buffer dir=inout }
+B 5 -142.5 127.5 -137.5 132.5 {name=cp_biasp dir=inout }
+B 5 -162.5 127.5 -157.5 132.5 {name=cp_pswitch dir=inout }
+B 5 -182.5 127.5 -177.5 132.5 {name=cp_nswitch dir=inout }
+B 5 -362.5 127.5 -357.5 132.5 {name=pfd_reset dir=inout }
+B 5 -162.5 -132.5 -157.5 -127.5 {name=s_0 sig_type=std_logic dir=in}
+B 5 -132.5 -132.5 -127.5 -127.5 {name=MC sig_type=std_logic dir=in}
+B 5 -192.5 -132.5 -187.5 -127.5 {name=s_1 sig_type=std_logic dir=in}
+B 5 117.5 127.5 122.5 132.5 {name=out_by_2 dir=inout }
+B 5 -2.5 127.5 2.5 132.5 {name=out_to_div dir=inout }
+B 5 397.5 127.5 402.5 132.5 {name=out_div dir=inout }
+B 5 137.5 127.5 142.5 132.5 {name=n_out_by_2 dir=inout }
+B 5 57.5 127.5 62.5 132.5 {name=n_out_div_2 dir=inout }
+B 5 37.5 127.5 42.5 132.5 {name=out_div_2 dir=inout }
+B 5 77.5 127.5 82.5 132.5 {name=n_out_buffer_div_2 dir=inout }
+B 5 97.5 127.5 102.5 132.5 {name=out_buffer_div_2 dir=inout }
+B 5 197.5 127.5 202.5 132.5 {name=n_clk_0 sig_type=std_logic dir=inout }
+B 5 377.5 127.5 382.5 132.5 {name=s1n sig_type=std_logic dir=inout }
+B 5 357.5 127.5 362.5 132.5 {name=s0n sig_type=std_logic dir=inout }
+B 5 337.5 127.5 342.5 132.5 {name=clk_2_f sig_type=std_logic dir=inout }
+B 5 317.5 127.5 322.5 132.5 {name=clk_d sig_type=std_logic dir=inout }
+B 5 297.5 127.5 302.5 132.5 {name=clk_out_mux21 sig_type=std_logic dir=inout }
+B 5 277.5 127.5 282.5 132.5 {name=clk_5 sig_type=std_logic dir=inout }
+B 5 257.5 127.5 262.5 132.5 {name=clk_pre sig_type=std_logic dir=inout }
+B 5 237.5 127.5 242.5 132.5 {name=n_clk_1 sig_type=std_logic dir=inout }
+B 5 217.5 127.5 222.5 132.5 {name=clk_1 sig_type=std_logic dir=inout }
+B 5 177.5 127.5 182.5 132.5 {name=clk_0 sig_type=std_logic dir=inout }
+B 5 -242.5 -132.5 -237.5 -127.5 {name=lf_D0 dir=in}
+T {@symname} -33 -6 0 0 0.3 0.3 {}
+T {@name} -15 -102 0 0 0.2 0.2 {}
+T {iref_cp} -336 -105 1 0 0.2 0.2 {}
+T {vss} 364 -105 1 0 0.2 0.2 {}
+T {vdd} 324 -105 1 0 0.2 0.2 {}
+T {vco_out} -41 190 1 1 0.2 0.2 {}
+T {vco_vctrl} -61 190 1 1 0.2 0.2 {}
+T {Up} -294 165 3 0 0.2 0.2 {}
+T {pfd_QA} -354 165 3 0 0.2 0.2 {}
+T {out_to_buffer} 439 190 1 1 0.2 0.2 {}
+T {in_ref} -375 -4 0 0 0.2 0.2 {}
+T {nUp} -274 165 3 0 0.2 0.2 {}
+T {out_to_pad} 465 -4 0 1 0.2 0.2 {}
+T {Down} -254 165 3 0 0.2 0.2 {}
+T {nDown} -234 165 3 0 0.2 0.2 {}
+T {pfd_QB} -334 165 3 0 0.2 0.2 {}
+T {vco_D0} -294 -155 3 1 0.2 0.2 {}
+T {lf_vc} -101 160 1 1 0.2 0.2 {}
+T {out_first_buffer} -21 190 1 1 0.2 0.2 {}
+T {cp_biasp} -141 180 1 1 0.2 0.2 {}
+T {cp_pswitch} -161 180 1 1 0.2 0.2 {}
+T {cp_nswitch} -181 180 1 1 0.2 0.2 {}
+T {pfd_reset} -374 165 3 0 0.2 0.2 {}
+T {s_0} -174 -135 3 1 0.2 0.2 {}
+T {MC} -144 -135 3 1 0.2 0.2 {}
+T {s_1} -204 -135 3 1 0.2 0.2 {}
+T {out_by_2} 106 210 3 0 0.2 0.2 {}
+T {out_to_div} -1 190 1 1 0.2 0.2 {}
+T {out_div} 399 190 1 1 0.2 0.2 {}
+T {n_out_by_2} 126 210 3 0 0.2 0.2 {}
+T {n_out_div_2} 46 210 3 0 0.2 0.2 {}
+T {out_div_2} 26 210 3 0 0.2 0.2 {}
+T {n_out_buffer_div_2} 66 210 3 0 0.2 0.2 {}
+T {out_buffer_div_2} 86 210 3 0 0.2 0.2 {}
+T {n_clk_0} 199 190 1 1 0.2 0.2 {}
+T {s1n} 379 190 1 1 0.2 0.2 {}
+T {s0n} 359 190 1 1 0.2 0.2 {}
+T {clk_2_f} 339 190 1 1 0.2 0.2 {}
+T {clk_d} 319 190 1 1 0.2 0.2 {}
+T {clk_out_mux21} 299 190 1 1 0.2 0.2 {}
+T {clk_5} 279 190 1 1 0.2 0.2 {}
+T {clk_pre} 259 190 1 1 0.2 0.2 {}
+T {n_clk_1} 239 190 1 1 0.2 0.2 {}
+T {clk_1} 219 190 1 1 0.2 0.2 {}
+T {clk_0} 179 190 1 1 0.2 0.2 {}
+T {lf_D0} -254 -155 3 1 0.2 0.2 {}
+T {PFD} -350 93.5 0 0 0.2 0.2 {}
+T {Interface} -273.75 94.75 0 0 0.2 0.2 {}
+T {CP} -166.25 93.5 0 0 0.2 0.2 {}
+T {LF} -106.25 93.5 0 0 0.2 0.2 {}
+T {VCO} -42.5 93.5 0 0 0.2 0.2 {}
+T {DIV_BY_2} 65 93.5 0 0 0.2 0.2 {}
+T {FREQ_DIV} 261.25 93.5 0 0 0.2 0.2 {}
+T {OUT} 430 93.5 0 0 0.2 0.2 {}
+T {DEBUG} 3.75 73.5 0 0 0.2 0.2 {}
+T {CONFIG} -236.25 -86.5 0 0 0.2 0.2 {}
+T {FREQ_DIV} -186.25 -105.25 0 0 0.2 0.2 {}
+T {VCO} -290 -105.25 0 0 0.2 0.2 {}
+T {LF} -245 -105.25 0 0 0.2 0.2 {}
diff --git a/xschem/top_pll_v3_no_integration.sch b/xschem/top_pll_v3_no_integration.sch
new file mode 100644
index 0000000..855407d
--- /dev/null
+++ b/xschem/top_pll_v3_no_integration.sch
@@ -0,0 +1,192 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -750 -360 -750 -330 { lab=vss}
+N -890 -270 -850 -270 { lab=in_ref}
+N -850 -270 -840 -270 { lab=in_ref}
+N -890 -190 -840 -190 { lab=out_div}
+N -790 -360 -790 -330 { lab=vdd}
+N -400 -250 -310 -250 { lab=nUp}
+N -400 -210 -310 -210 { lab=Down}
+N -360 -170 -310 -170 { lab=nDown}
+N -360 -290 -310 -290 { lab=Up}
+N 410 -330 410 -300 { lab=vdd}
+N 410 -160 410 -130 { lab=vss}
+N 530 260 570 260 { lab=out_to_div}
+N 330 -190 340 -190 { lab=vco_D0}
+N 230 -230 340 -230 { lab=vco_vctrl}
+N 480 -230 520 -230 { lab=vco_out}
+N -460 -170 -360 -170 { lab=nDown}
+N -460 -210 -400 -210 { lab=Down}
+N -460 -250 -400 -250 { lab=nUp}
+N -460 -290 -360 -290 { lab=Up}
+N -700 -190 -600 -190 { lab=pfd_QB}
+N -530 -360 -530 -330 { lab=vdd}
+N -530 -130 -530 -100 { lab=vss}
+N -890 -190 -890 260 { lab=out_div}
+N 330 -190 330 -150 { lab=vco_D0}
+N 180 150 180 180 { lab=vdd}
+N -210 -360 -210 -330 { lab=vdd}
+N -180 -360 -180 -330 { lab=vss}
+N -50 -230 -30 -230 { lab=vco_vctrl}
+N -270 -370 -270 -330 { lab=iref_cp}
+N 10 280 90 280 { lab=n_out_by_2}
+N 10 240 90 240 { lab=out_by_2}
+N -60 240 10 240 { lab=out_by_2}
+N -60 280 10 280 { lab=n_out_by_2}
+N -90 240 -60 240 { lab=out_by_2}
+N -90 280 -60 280 { lab=n_out_by_2}
+N -890 260 -470 260 { lab=out_div}
+N 60 -70 60 -40 { lab=vss}
+N 30 -230 90 -230 { lab=vco_vctrl}
+N 90 -230 230 -230 { lab=vco_vctrl}
+N 60 -230 60 -210 { lab=vco_vctrl}
+N 120 -140 160 -140 { lab=lf_vc}
+N 520 -230 580 -230 { lab=vco_out}
+N 620 -330 620 -300 { lab=vdd}
+N 660 -330 660 -300 { lab=vss}
+N 700 -250 740 -250 { lab=out_to_buffer}
+N 700 -210 750 -210 { lab=out_to_div}
+N 870 -210 870 260 { lab=out_to_div}
+N 570 260 750 260 { lab=out_to_div}
+N 640 -160 640 -120 { lab=out_first_buffer}
+N 750 -210 870 -210 { lab=out_to_div}
+N 750 260 870 260 { lab=out_to_div}
+N 230 260 530 260 { lab=out_to_div}
+N 140 150 140 180 { lab=vss}
+N -640 -300 -640 -270 { lab=pfd_QA}
+N -640 -190 -640 -160 { lab=pfd_QB}
+N -450 -310 -440 -310 { lab=Up}
+N -450 -310 -450 -290 { lab=Up}
+N -450 -270 -440 -270 { lab=nUp}
+N -450 -270 -450 -250 { lab=nUp}
+N -450 -230 -440 -230 { lab=Down}
+N -450 -230 -450 -210 { lab=Down}
+N -450 -190 -440 -190 { lab=nDown}
+N -450 -190 -450 -170 { lab=nDown}
+N -770 -130 -770 -100 { lab=pfd_reset}
+N -700 -270 -600 -270 { lab=pfd_QA}
+N -260 -130 -260 -100 { lab=cp_nswitch}
+N -230 -130 -230 -100 { lab=cp_pswitch}
+N -200 -130 -200 -100 { lab=cp_biasp}
+N -140 -230 -50 -230 { lab=vco_vctrl}
+N -30 -230 30 -230 { lab=vco_vctrl}
+N 160 -320 160 -240 { lab=vco_vctrl}
+N 160 -240 160 -230 { lab=vco_vctrl}
+N 520 -320 520 -230 { lab=vco_out}
+N 370 220 370 260 { lab=out_to_div}
+N 0 200 0 240 { lab=out_by_2}
+N 0 280 0 320 { lab=n_out_by_2}
+N 190 340 190 380 { lab=out_div_2}
+N 170 340 170 380 { lab=n_out_div_2}
+N 150 340 150 380 { lab=out_buffer_div_2}
+N 130 340 130 380 { lab=n_out_buffer_div_2}
+N -770 260 -770 300 { lab=out_div}
+N 740 -250 930 -250 { lab=out_to_buffer}
+N 810 -300 810 -250 { lab=out_to_buffer}
+N 970 -330 970 -300 { lab=vdd}
+N 970 -200 970 -170 { lab=vss}
+N 1060 -250 1100 -250 { lab=out_to_pad}
+N -470 260 -360 260 { lab=out_div}
+N -280 150 -280 180 { lab=vdd}
+N -300 150 -300 180 { lab=vss}
+N -130 150 -130 180 { lab=s_1}
+N -150 150 -150 180 { lab=s_0}
+N -170 150 -170 180 { lab=MC}
+N -120 390 -120 420 { lab=clk_0}
+N -140 390 -140 420 { lab=n_clk_0}
+N -160 390 -160 420 { lab=clk_1}
+N -180 390 -180 420 { lab=n_clk_1}
+N -120 350 -120 390 { lab=clk_0}
+N -140 340 -140 390 { lab=n_clk_0}
+N -160 340 -160 390 { lab=clk_1}
+N -180 340 -180 390 { lab=n_clk_1}
+N -120 340 -120 350 { lab=clk_0}
+N -200 390 -200 420 { lab=clk_pre}
+N -220 390 -220 420 { lab=clk_5}
+N -240 390 -240 420 { lab=clk_out_mux21}
+N -260 390 -260 420 { lab=clk_d}
+N -200 350 -200 390 { lab=clk_pre}
+N -220 340 -220 390 { lab=clk_5}
+N -240 340 -240 390 { lab=clk_out_mux21}
+N -260 340 -260 390 { lab=clk_d}
+N -200 340 -200 350 { lab=clk_pre}
+N -280 390 -280 420 { lab=clk_2_f}
+N -300 390 -300 420 { lab=s0n}
+N -320 390 -320 420 { lab=s1n}
+N -280 340 -280 390 { lab=clk_2_f}
+N -300 340 -300 390 { lab=s0n}
+N -320 340 -320 390 { lab=s1n}
+N -30 -140 -0 -140 { lab=lf_D0}
+N -30 -140 -30 -110 { lab=lf_D0}
+C {lab_pin.sym} 410 -330 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -130 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -530 -360 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -530 -100 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 180 150 1 0 {name=l45 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -210 -360 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -180 -360 1 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 60 -40 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 620 -330 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 660 -330 1 0 {name=l40 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 150 1 0 {name=l12 sig_type=std_logic lab=vss}
+C {iopin.sym} -790 -360 3 0 {name=p1 lab=vdd}
+C {iopin.sym} -750 -360 3 0 {name=p2 lab=vss}
+C {ipin.sym} -890 -270 0 0 {name=p3 lab=in_ref}
+C {iopin.sym} -640 -300 3 0 {name=p4 lab=pfd_QA}
+C {iopin.sym} -640 -160 1 0 {name=p5 lab=pfd_QB}
+C {iopin.sym} -440 -310 0 0 {name=p6 lab=Up}
+C {iopin.sym} -440 -270 0 0 {name=p7 lab=nUp}
+C {iopin.sym} -440 -230 0 0 {name=p8 lab=Down}
+C {iopin.sym} -440 -190 0 0 {name=p9 lab=nDown}
+C {iopin.sym} -770 -100 1 0 {name=p10 lab=pfd_reset}
+C {iopin.sym} -260 -100 1 0 {name=p11 lab=cp_nswitch}
+C {iopin.sym} -230 -100 1 0 {name=p12 lab=cp_pswitch}
+C {iopin.sym} -200 -100 1 0 {name=p13 lab=cp_biasp}
+C {ipin.sym} -270 -370 1 0 {name=p14 lab=iref_cp}
+C {iopin.sym} 160 -140 0 0 {name=p15 lab=lf_vc}
+C {ipin.sym} 330 -150 3 0 {name=p16 lab=vco_D0}
+C {iopin.sym} 160 -320 3 0 {name=p17 lab=vco_vctrl}
+C {iopin.sym} 520 -320 3 0 {name=p18 lab=vco_out}
+C {iopin.sym} 640 -120 1 0 {name=p19 lab=out_first_buffer}
+C {iopin.sym} 810 -300 3 0 {name=p20 lab=out_to_buffer}
+C {iopin.sym} 370 220 3 0 {name=p21 lab=out_to_div}
+C {iopin.sym} 0 200 3 0 {name=p22 lab=out_by_2}
+C {iopin.sym} 0 320 1 0 {name=p23 lab=n_out_by_2}
+C {iopin.sym} 190 380 1 0 {name=p24 lab=out_div_2}
+C {iopin.sym} 170 380 1 0 {name=p25 lab=n_out_div_2}
+C {iopin.sym} 150 380 1 0 {name=p26 lab=out_buffer_div_2}
+C {iopin.sym} 130 380 1 0 {name=p27 lab=n_out_buffer_div_2}
+C {iopin.sym} -770 300 1 0 {name=p33 lab=out_div}
+C {lab_pin.sym} 970 -330 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 970 -170 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {opin.sym} 1100 -250 0 0 {name=p35 lab=out_to_pad}
+C {lab_pin.sym} -280 150 1 0 {name=l3 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -300 150 1 0 {name=l4 sig_type=std_logic lab=vss}
+C {iopin.sym} -120 420 1 0 {name=p48 sig_type=std_logic lab=clk_0}
+C {iopin.sym} -140 420 1 0 {name=p49 sig_type=std_logic lab=n_clk_0}
+C {iopin.sym} -160 420 1 0 {name=p50 sig_type=std_logic lab=clk_1}
+C {iopin.sym} -180 420 1 0 {name=p51 sig_type=std_logic lab=n_clk_1}
+C {iopin.sym} -200 420 1 0 {name=p52 sig_type=std_logic lab=clk_pre}
+C {iopin.sym} -220 420 1 0 {name=p53 sig_type=std_logic lab=clk_5}
+C {iopin.sym} -240 420 3 1 {name=p54 sig_type=std_logic lab=clk_out_mux21}
+C {iopin.sym} -260 420 1 0 {name=p55 sig_type=std_logic lab=clk_d}
+C {iopin.sym} -280 420 1 0 {name=p56 sig_type=std_logic lab=clk_2_f}
+C {iopin.sym} -300 420 1 0 {name=p57 sig_type=std_logic lab=s0n}
+C {iopin.sym} -320 420 1 0 {name=p58 sig_type=std_logic lab=s1n}
+C {ipin.sym} -170 150 1 0 {name=p28 sig_type=std_logic lab=MC}
+C {ipin.sym} -150 150 1 0 {name=p29 sig_type=std_logic lab=s_0}
+C {ipin.sym} -130 150 1 0 {name=p30 sig_type=std_logic lab=s_1}
+C {ipin.sym} -30 -110 3 0 {name=p31 lab=lf_D0}
+C {PFD_pex_c.sym} -770 -230 0 0 {name=x1}
+C {pfd_cp_interface_pex_c.sym} -530 -230 0 0 {name=x2}
+C {csvco_v2_pex_c.sym} 410 -230 0 0 {name=x3}
+C {charge_pump_pex_c.sym} -230 -230 0 0 {name=x4}
+C {loop_filter_v2_pex_c.sym} 60 -140 0 0 {name=x5}
+C {ring_osc_buffer_pex_c.sym} 640 -230 0 0 {name=x6}
+C {buffer_salida_pex_c.sym} 990 -250 0 0 {name=x7}
+C {div_by_2_pex_c.sym} 160 260 0 1 {name=x8}
+C {freq_div_pex_c.sym} -200 260 0 1 {name=x9}
diff --git a/xschem/top_pll_v3_pex_c.sym b/xschem/top_pll_v3_pex_c.sym
new file mode 100644
index 0000000..be54766
--- /dev/null
+++ b/xschem/top_pll_v3_pex_c.sym
@@ -0,0 +1,208 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -340 -130 -340 -110 {}
+L 4 -410 0 -390 0 {}
+L 4 -380 110 340 110 {}
+L 4 470 -110 470 110 {}
+L 4 -390 -110 -390 100 {}
+L 4 -380 70 -380 100 {}
+L 4 -370 70 330 70 {}
+L 4 460 70 460 110 {}
+L 4 -380 -110 340 -110 {}
+L 4 -390 100 -390 110 {}
+L 4 -380 100 -380 110 {}
+L 4 -370 90 -370 110 {}
+L 4 -370 90 -310 90 {}
+L 4 -310 90 -310 110 {}
+L 4 -290 90 -290 110 {}
+L 4 -290 90 -210 90 {}
+L 4 -210 90 -210 110 {}
+L 4 -190 90 -190 110 {}
+L 4 -190 90 -130 90 {}
+L 4 -130 90 -130 110 {}
+L 4 -110 90 -110 110 {}
+L 4 -110 90 -90 90 {}
+L 4 -90 90 -90 110 {}
+L 4 -70 90 -70 110 {}
+L 4 -70 90 10 90 {}
+L 4 10 90 10 110 {}
+L 4 30 90 30 110 {}
+L 4 30 90 150 90 {}
+L 4 150 90 150 110 {}
+L 4 170 90 170 110 {}
+L 4 170 90 410 90 {}
+L 4 410 90 410 110 {}
+L 4 430 90 430 110 {}
+L 4 430 90 450 90 {}
+L 4 450 90 450 110 {}
+L 4 340 110 460 110 {}
+L 4 -390 110 -380 110 {}
+L 4 -380 70 -370 70 {}
+L 4 330 70 460 70 {}
+L 4 460 110 470 110 {}
+L 4 340 -110 470 -110 {}
+L 4 -390 -110 -380 -110 {}
+L 4 -290 -110 -290 -90 {}
+L 4 -290 -90 -270 -90 {}
+L 4 -270 -110 -270 -90 {}
+L 4 -210 -110 -210 -90 {}
+L 4 -210 -90 -120 -90 {}
+L 4 -120 -110 -120 -90 {}
+L 4 -250 -110 -250 -90 {}
+L 4 -250 -90 -230 -90 {}
+L 4 -230 -110 -230 -90 {}
+L 4 -310 -110 -310 -70 {}
+L 4 -310 -70 -100 -70 {}
+L 4 -100 -110 -100 -70 {}
+L 4 -280 -130 -280 -110 {}
+L 4 -240 -130 -240 -110 {}
+L 4 -190 -130 -190 -110 {}
+L 4 -160 -130 -160 -110 {}
+L 4 -130 -130 -130 -110 {}
+L 4 470 -0 490 0 {}
+L 7 360 -130 360 -110 {}
+L 7 320 -130 320 -110 {}
+L 7 -40 110 -40 130 {}
+L 7 -60 110 -60 130 {}
+L 7 -280 110 -280 130 {}
+L 7 -340 110 -340 130 {}
+L 7 440 110 440 130 {}
+L 7 -260 110 -260 130 {}
+L 7 -240 110 -240 130 {}
+L 7 -220 110 -220 130 {}
+L 7 -320 110 -320 130 {}
+L 7 -100 110 -100 130 {}
+L 7 -20 110 -20 130 {}
+L 7 -140 110 -140 130 {}
+L 7 -160 110 -160 130 {}
+L 7 -180 110 -180 130 {}
+L 7 -360 110 -360 130 {}
+L 7 120 110 120 130 {}
+L 7 0 110 0 130 {}
+L 7 400 110 400 130 {}
+L 7 140 110 140 130 {}
+L 7 60 110 60 130 {}
+L 7 40 110 40 130 {}
+L 7 80 110 80 130 {}
+L 7 100 110 100 130 {}
+L 7 200 110 200 130 {}
+L 7 380 110 380 130 {}
+L 7 360 110 360 130 {}
+L 7 340 110 340 130 {}
+L 7 320 110 320 130 {}
+L 7 300 110 300 130 {}
+L 7 280 110 280 130 {}
+L 7 260 110 260 130 {}
+L 7 240 110 240 130 {}
+L 7 220 110 220 130 {}
+L 7 180 110 180 130 {}
+B 5 -342.5 -132.5 -337.5 -127.5 {name=iref_cp dir=in }
+B 5 357.5 -132.5 362.5 -127.5 {name=vss dir=inout }
+B 5 317.5 -132.5 322.5 -127.5 {name=vdd dir=inout }
+B 5 -42.5 127.5 -37.5 132.5 {name=vco_out dir=inout }
+B 5 -62.5 127.5 -57.5 132.5 {name=vco_vctrl dir=inout }
+B 5 -282.5 127.5 -277.5 132.5 {name=Up dir=inout }
+B 5 -342.5 127.5 -337.5 132.5 {name=pfd_QA dir=inout }
+B 5 437.5 127.5 442.5 132.5 {name=out_to_buffer dir=inout }
+B 5 -412.5 -2.5 -407.5 2.5 {name=in_ref dir=in }
+B 5 -262.5 127.5 -257.5 132.5 {name=nUp dir=inout }
+B 5 487.5 -2.5 492.5 2.5 {name=out_to_pad dir=out }
+B 5 -242.5 127.5 -237.5 132.5 {name=Down dir=inout }
+B 5 -222.5 127.5 -217.5 132.5 {name=nDown dir=inout }
+B 5 -322.5 127.5 -317.5 132.5 {name=pfd_QB dir=inout }
+B 5 -282.5 -132.5 -277.5 -127.5 {name=lf_D0 dir=in }
+B 5 -102.5 127.5 -97.5 132.5 {name=lf_vc dir=inout }
+B 5 -22.5 127.5 -17.5 132.5 {name=out_first_buffer dir=inout }
+B 5 -142.5 127.5 -137.5 132.5 {name=cp_biasp dir=inout }
+B 5 -162.5 127.5 -157.5 132.5 {name=cp_pswitch dir=inout }
+B 5 -182.5 127.5 -177.5 132.5 {name=cp_nswitch dir=inout }
+B 5 -362.5 127.5 -357.5 132.5 {name=pfd_reset dir=inout }
+B 5 -162.5 -132.5 -157.5 -127.5 {name=s_0 sig_type=std_logic dir=in}
+B 5 -132.5 -132.5 -127.5 -127.5 {name=MC sig_type=std_logic dir=in}
+B 5 -192.5 -132.5 -187.5 -127.5 {name=s_1 sig_type=std_logic dir=in}
+B 5 117.5 127.5 122.5 132.5 {name=out_by_2 dir=inout }
+B 5 -2.5 127.5 2.5 132.5 {name=out_to_div dir=inout }
+B 5 397.5 127.5 402.5 132.5 {name=out_div dir=inout }
+B 5 137.5 127.5 142.5 132.5 {name=n_out_by_2 dir=inout }
+B 5 57.5 127.5 62.5 132.5 {name=n_out_div_2 dir=inout }
+B 5 37.5 127.5 42.5 132.5 {name=out_div_2 dir=inout }
+B 5 77.5 127.5 82.5 132.5 {name=n_out_buffer_div_2 dir=inout }
+B 5 97.5 127.5 102.5 132.5 {name=out_buffer_div_2 dir=inout }
+B 5 197.5 127.5 202.5 132.5 {name=n_clk_0 sig_type=std_logic dir=inout }
+B 5 377.5 127.5 382.5 132.5 {name=s1n sig_type=std_logic dir=inout }
+B 5 357.5 127.5 362.5 132.5 {name=s0n sig_type=std_logic dir=inout }
+B 5 337.5 127.5 342.5 132.5 {name=clk_2_f sig_type=std_logic dir=inout }
+B 5 317.5 127.5 322.5 132.5 {name=clk_d sig_type=std_logic dir=inout }
+B 5 297.5 127.5 302.5 132.5 {name=clk_out_mux21 sig_type=std_logic dir=inout }
+B 5 277.5 127.5 282.5 132.5 {name=clk_5 sig_type=std_logic dir=inout }
+B 5 257.5 127.5 262.5 132.5 {name=clk_pre sig_type=std_logic dir=inout }
+B 5 237.5 127.5 242.5 132.5 {name=n_clk_1 sig_type=std_logic dir=inout }
+B 5 217.5 127.5 222.5 132.5 {name=clk_1 sig_type=std_logic dir=inout }
+B 5 177.5 127.5 182.5 132.5 {name=clk_0 sig_type=std_logic dir=inout }
+B 5 -242.5 -132.5 -237.5 -127.5 {name=lf_D0 dir=in}
+T {@symname} -33 -6 0 0 0.3 0.3 {}
+T {@name} -15 -102 0 0 0.2 0.2 {}
+T {iref_cp} -336 -105 1 0 0.2 0.2 {}
+T {vss} 364 -105 1 0 0.2 0.2 {}
+T {vdd} 324 -105 1 0 0.2 0.2 {}
+T {vco_out} -41 190 1 1 0.2 0.2 {}
+T {vco_vctrl} -61 190 1 1 0.2 0.2 {}
+T {Up} -294 165 3 0 0.2 0.2 {}
+T {pfd_QA} -354 165 3 0 0.2 0.2 {}
+T {out_to_buffer} 439 190 1 1 0.2 0.2 {}
+T {in_ref} -375 -4 0 0 0.2 0.2 {}
+T {nUp} -274 165 3 0 0.2 0.2 {}
+T {out_to_pad} 465 -4 0 1 0.2 0.2 {}
+T {Down} -254 165 3 0 0.2 0.2 {}
+T {nDown} -234 165 3 0 0.2 0.2 {}
+T {pfd_QB} -334 165 3 0 0.2 0.2 {}
+T {vco_D0} -294 -155 3 1 0.2 0.2 {}
+T {lf_vc} -101 160 1 1 0.2 0.2 {}
+T {out_first_buffer} -21 190 1 1 0.2 0.2 {}
+T {cp_biasp} -141 180 1 1 0.2 0.2 {}
+T {cp_pswitch} -161 180 1 1 0.2 0.2 {}
+T {cp_nswitch} -181 180 1 1 0.2 0.2 {}
+T {pfd_reset} -374 165 3 0 0.2 0.2 {}
+T {s_0} -174 -135 3 1 0.2 0.2 {}
+T {MC} -144 -135 3 1 0.2 0.2 {}
+T {s_1} -204 -135 3 1 0.2 0.2 {}
+T {out_by_2} 106 210 3 0 0.2 0.2 {}
+T {out_to_div} -1 190 1 1 0.2 0.2 {}
+T {out_div} 399 190 1 1 0.2 0.2 {}
+T {n_out_by_2} 126 210 3 0 0.2 0.2 {}
+T {n_out_div_2} 46 210 3 0 0.2 0.2 {}
+T {out_div_2} 26 210 3 0 0.2 0.2 {}
+T {n_out_buffer_div_2} 66 210 3 0 0.2 0.2 {}
+T {out_buffer_div_2} 86 210 3 0 0.2 0.2 {}
+T {n_clk_0} 199 190 1 1 0.2 0.2 {}
+T {s1n} 379 190 1 1 0.2 0.2 {}
+T {s0n} 359 190 1 1 0.2 0.2 {}
+T {clk_2_f} 339 190 1 1 0.2 0.2 {}
+T {clk_d} 319 190 1 1 0.2 0.2 {}
+T {clk_out_mux21} 299 190 1 1 0.2 0.2 {}
+T {clk_5} 279 190 1 1 0.2 0.2 {}
+T {clk_pre} 259 190 1 1 0.2 0.2 {}
+T {n_clk_1} 239 190 1 1 0.2 0.2 {}
+T {clk_1} 219 190 1 1 0.2 0.2 {}
+T {clk_0} 179 190 1 1 0.2 0.2 {}
+T {lf_D0} -254 -155 3 1 0.2 0.2 {}
+T {PFD} -350 93.5 0 0 0.2 0.2 {}
+T {Interface} -273.75 94.75 0 0 0.2 0.2 {}
+T {CP} -166.25 93.5 0 0 0.2 0.2 {}
+T {LF} -106.25 93.5 0 0 0.2 0.2 {}
+T {VCO} -42.5 93.5 0 0 0.2 0.2 {}
+T {DIV_BY_2} 65 93.5 0 0 0.2 0.2 {}
+T {FREQ_DIV} 261.25 93.5 0 0 0.2 0.2 {}
+T {OUT} 430 93.5 0 0 0.2 0.2 {}
+T {DEBUG} 3.75 73.5 0 0 0.2 0.2 {}
+T {CONFIG} -236.25 -86.5 0 0 0.2 0.2 {}
+T {FREQ_DIV} -186.25 -105.25 0 0 0.2 0.2 {}
+T {VCO} -290 -105.25 0 0 0.2 0.2 {}
+T {LF} -245 -105.25 0 0 0.2 0.2 {}
diff --git a/xschem/top_pll_v3_pex_no_integration.sch b/xschem/top_pll_v3_pex_no_integration.sch
new file mode 100644
index 0000000..abe6aec
--- /dev/null
+++ b/xschem/top_pll_v3_pex_no_integration.sch
@@ -0,0 +1,192 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -750 -360 -750 -330 { lab=vss}
+N -890 -270 -850 -270 { lab=in_ref}
+N -850 -270 -840 -270 { lab=in_ref}
+N -890 -190 -840 -190 { lab=out_div}
+N -790 -360 -790 -330 { lab=vdd}
+N -400 -250 -310 -250 { lab=nUp}
+N -400 -210 -310 -210 { lab=Down}
+N -360 -170 -310 -170 { lab=nDown}
+N -360 -290 -310 -290 { lab=Up}
+N 410 -330 410 -300 { lab=vdd}
+N 410 -160 410 -130 { lab=vss}
+N 530 260 570 260 { lab=out_to_div}
+N 330 -190 340 -190 { lab=vco_D0}
+N 230 -230 340 -230 { lab=vco_vctrl}
+N 480 -230 520 -230 { lab=vco_out}
+N -460 -170 -360 -170 { lab=nDown}
+N -460 -210 -400 -210 { lab=Down}
+N -460 -250 -400 -250 { lab=nUp}
+N -460 -290 -360 -290 { lab=Up}
+N -700 -190 -600 -190 { lab=pfd_QB}
+N -530 -360 -530 -330 { lab=vdd}
+N -530 -130 -530 -100 { lab=vss}
+N -890 -190 -890 260 { lab=out_div}
+N 330 -190 330 -150 { lab=vco_D0}
+N 180 150 180 180 { lab=vdd}
+N -210 -360 -210 -330 { lab=vdd}
+N -180 -360 -180 -330 { lab=vss}
+N -50 -230 -30 -230 { lab=vco_vctrl}
+N -270 -370 -270 -330 { lab=iref_cp}
+N 10 280 90 280 { lab=n_out_by_2}
+N 10 240 90 240 { lab=out_by_2}
+N -60 240 10 240 { lab=out_by_2}
+N -60 280 10 280 { lab=n_out_by_2}
+N -90 240 -60 240 { lab=out_by_2}
+N -90 280 -60 280 { lab=n_out_by_2}
+N -890 260 -470 260 { lab=out_div}
+N 60 -70 60 -40 { lab=vss}
+N 30 -230 90 -230 { lab=vco_vctrl}
+N 90 -230 230 -230 { lab=vco_vctrl}
+N 60 -230 60 -210 { lab=vco_vctrl}
+N 120 -140 160 -140 { lab=lf_vc}
+N 520 -230 580 -230 { lab=vco_out}
+N 620 -330 620 -300 { lab=vdd}
+N 660 -330 660 -300 { lab=vss}
+N 700 -250 740 -250 { lab=out_to_buffer}
+N 700 -210 750 -210 { lab=out_to_div}
+N 870 -210 870 260 { lab=out_to_div}
+N 570 260 750 260 { lab=out_to_div}
+N 640 -160 640 -120 { lab=out_first_buffer}
+N 750 -210 870 -210 { lab=out_to_div}
+N 750 260 870 260 { lab=out_to_div}
+N 230 260 530 260 { lab=out_to_div}
+N 140 150 140 180 { lab=vss}
+N -640 -300 -640 -270 { lab=pfd_QA}
+N -640 -190 -640 -160 { lab=pfd_QB}
+N -450 -310 -440 -310 { lab=Up}
+N -450 -310 -450 -290 { lab=Up}
+N -450 -270 -440 -270 { lab=nUp}
+N -450 -270 -450 -250 { lab=nUp}
+N -450 -230 -440 -230 { lab=Down}
+N -450 -230 -450 -210 { lab=Down}
+N -450 -190 -440 -190 { lab=nDown}
+N -450 -190 -450 -170 { lab=nDown}
+N -770 -130 -770 -100 { lab=pfd_reset}
+N -700 -270 -600 -270 { lab=pfd_QA}
+N -260 -130 -260 -100 { lab=cp_nswitch}
+N -230 -130 -230 -100 { lab=cp_pswitch}
+N -200 -130 -200 -100 { lab=cp_biasp}
+N -140 -230 -50 -230 { lab=vco_vctrl}
+N -30 -230 30 -230 { lab=vco_vctrl}
+N 160 -320 160 -240 { lab=vco_vctrl}
+N 160 -240 160 -230 { lab=vco_vctrl}
+N 520 -320 520 -230 { lab=vco_out}
+N 370 220 370 260 { lab=out_to_div}
+N 0 200 0 240 { lab=out_by_2}
+N 0 280 0 320 { lab=n_out_by_2}
+N 190 340 190 380 { lab=out_div_2}
+N 170 340 170 380 { lab=n_out_div_2}
+N 150 340 150 380 { lab=out_buffer_div_2}
+N 130 340 130 380 { lab=n_out_buffer_div_2}
+N -770 260 -770 300 { lab=out_div}
+N 740 -250 930 -250 { lab=out_to_buffer}
+N 810 -300 810 -250 { lab=out_to_buffer}
+N 970 -330 970 -300 { lab=vdd}
+N 970 -200 970 -170 { lab=vss}
+N 1060 -250 1100 -250 { lab=out_to_pad}
+N -470 260 -360 260 { lab=out_div}
+N -280 150 -280 180 { lab=vdd}
+N -300 150 -300 180 { lab=vss}
+N -130 150 -130 180 { lab=s_1}
+N -150 150 -150 180 { lab=s_0}
+N -170 150 -170 180 { lab=MC}
+N -120 390 -120 420 { lab=clk_0}
+N -140 390 -140 420 { lab=n_clk_0}
+N -160 390 -160 420 { lab=clk_1}
+N -180 390 -180 420 { lab=n_clk_1}
+N -120 350 -120 390 { lab=clk_0}
+N -140 340 -140 390 { lab=n_clk_0}
+N -160 340 -160 390 { lab=clk_1}
+N -180 340 -180 390 { lab=n_clk_1}
+N -120 340 -120 350 { lab=clk_0}
+N -200 390 -200 420 { lab=clk_pre}
+N -220 390 -220 420 { lab=clk_5}
+N -240 390 -240 420 { lab=clk_out_mux21}
+N -260 390 -260 420 { lab=clk_d}
+N -200 350 -200 390 { lab=clk_pre}
+N -220 340 -220 390 { lab=clk_5}
+N -240 340 -240 390 { lab=clk_out_mux21}
+N -260 340 -260 390 { lab=clk_d}
+N -200 340 -200 350 { lab=clk_pre}
+N -280 390 -280 420 { lab=clk_2_f}
+N -300 390 -300 420 { lab=s0n}
+N -320 390 -320 420 { lab=s1n}
+N -280 340 -280 390 { lab=clk_2_f}
+N -300 340 -300 390 { lab=s0n}
+N -320 340 -320 390 { lab=s1n}
+N -30 -140 -0 -140 { lab=lf_D0}
+N -30 -140 -30 -110 { lab=lf_D0}
+C {lab_pin.sym} 410 -330 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -130 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -530 -360 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -530 -100 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 180 150 1 0 {name=l45 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -210 -360 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -180 -360 1 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 60 -40 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 620 -330 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 660 -330 1 0 {name=l40 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 150 1 0 {name=l12 sig_type=std_logic lab=vss}
+C {iopin.sym} -790 -360 3 0 {name=p1 lab=vdd}
+C {iopin.sym} -750 -360 3 0 {name=p2 lab=vss}
+C {ipin.sym} -890 -270 0 0 {name=p3 lab=in_ref}
+C {iopin.sym} -640 -300 3 0 {name=p4 lab=pfd_QA}
+C {iopin.sym} -640 -160 1 0 {name=p5 lab=pfd_QB}
+C {iopin.sym} -440 -310 0 0 {name=p6 lab=Up}
+C {iopin.sym} -440 -270 0 0 {name=p7 lab=nUp}
+C {iopin.sym} -440 -230 0 0 {name=p8 lab=Down}
+C {iopin.sym} -440 -190 0 0 {name=p9 lab=nDown}
+C {iopin.sym} -770 -100 1 0 {name=p10 lab=pfd_reset}
+C {iopin.sym} -260 -100 1 0 {name=p11 lab=cp_nswitch}
+C {iopin.sym} -230 -100 1 0 {name=p12 lab=cp_pswitch}
+C {iopin.sym} -200 -100 1 0 {name=p13 lab=cp_biasp}
+C {ipin.sym} -270 -370 1 0 {name=p14 lab=iref_cp}
+C {iopin.sym} 160 -140 0 0 {name=p15 lab=lf_vc}
+C {ipin.sym} 330 -150 3 0 {name=p16 lab=vco_D0}
+C {iopin.sym} 160 -320 3 0 {name=p17 lab=vco_vctrl}
+C {iopin.sym} 520 -320 3 0 {name=p18 lab=vco_out}
+C {iopin.sym} 640 -120 1 0 {name=p19 lab=out_first_buffer}
+C {iopin.sym} 810 -300 3 0 {name=p20 lab=out_to_buffer}
+C {iopin.sym} 370 220 3 0 {name=p21 lab=out_to_div}
+C {iopin.sym} 0 200 3 0 {name=p22 lab=out_by_2}
+C {iopin.sym} 0 320 1 0 {name=p23 lab=n_out_by_2}
+C {iopin.sym} 190 380 1 0 {name=p24 lab=out_div_2}
+C {iopin.sym} 170 380 1 0 {name=p25 lab=n_out_div_2}
+C {iopin.sym} 150 380 1 0 {name=p26 lab=out_buffer_div_2}
+C {iopin.sym} 130 380 1 0 {name=p27 lab=n_out_buffer_div_2}
+C {iopin.sym} -770 300 1 0 {name=p33 lab=out_div}
+C {lab_pin.sym} 970 -330 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 970 -170 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {opin.sym} 1100 -250 0 0 {name=p35 lab=out_to_pad}
+C {lab_pin.sym} -280 150 1 0 {name=l3 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -300 150 1 0 {name=l4 sig_type=std_logic lab=vss}
+C {iopin.sym} -120 420 1 0 {name=p48 sig_type=std_logic lab=clk_0}
+C {iopin.sym} -140 420 1 0 {name=p49 sig_type=std_logic lab=n_clk_0}
+C {iopin.sym} -160 420 1 0 {name=p50 sig_type=std_logic lab=clk_1}
+C {iopin.sym} -180 420 1 0 {name=p51 sig_type=std_logic lab=n_clk_1}
+C {iopin.sym} -200 420 1 0 {name=p52 sig_type=std_logic lab=clk_pre}
+C {iopin.sym} -220 420 1 0 {name=p53 sig_type=std_logic lab=clk_5}
+C {iopin.sym} -240 420 3 1 {name=p54 sig_type=std_logic lab=clk_out_mux21}
+C {iopin.sym} -260 420 1 0 {name=p55 sig_type=std_logic lab=clk_d}
+C {iopin.sym} -280 420 1 0 {name=p56 sig_type=std_logic lab=clk_2_f}
+C {iopin.sym} -300 420 1 0 {name=p57 sig_type=std_logic lab=s0n}
+C {iopin.sym} -320 420 1 0 {name=p58 sig_type=std_logic lab=s1n}
+C {ipin.sym} -170 150 1 0 {name=p28 sig_type=std_logic lab=MC}
+C {ipin.sym} -150 150 1 0 {name=p29 sig_type=std_logic lab=s_0}
+C {ipin.sym} -130 150 1 0 {name=p30 sig_type=std_logic lab=s_1}
+C {ipin.sym} -30 -110 3 0 {name=p31 lab=lf_D0}
+C {PFD_pex_c.sym} -770 -230 0 0 {name=x1}
+C {pfd_cp_interface_pex_c.sym} -530 -230 0 0 {name=x2}
+C {charge_pump_pex_c.sym} -230 -230 0 0 {name=x4}
+C {loop_filter_v2_pex_c.sym} 60 -140 0 0 {name=x5}
+C {ring_osc_buffer_pex_c.sym} 640 -230 0 0 {name=x6}
+C {buffer_salida_pex_c.sym} 990 -250 0 0 {name=x7}
+C {div_by_2_pex_c.sym} 160 260 0 1 {name=x8}
+C {freq_div_pex_c.sym} -200 260 0 1 {name=x9}
+C {csvco_pex_c.sym} 410 -230 0 0 {name=x3}
diff --git a/xschem/top_pll_v3_pex_no_integration.sym b/xschem/top_pll_v3_pex_no_integration.sym
new file mode 100644
index 0000000..7c53df5
--- /dev/null
+++ b/xschem/top_pll_v3_pex_no_integration.sym
@@ -0,0 +1,208 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -340 -130 -340 -110 {}
+L 4 -410 0 -390 0 {}
+L 4 -380 110 340 110 {}
+L 4 470 -110 470 110 {}
+L 4 -390 -110 -390 100 {}
+L 4 -380 70 -380 100 {}
+L 4 -370 70 330 70 {}
+L 4 460 70 460 110 {}
+L 4 -380 -110 340 -110 {}
+L 4 -390 100 -390 110 {}
+L 4 -380 100 -380 110 {}
+L 4 -370 90 -370 110 {}
+L 4 -370 90 -310 90 {}
+L 4 -310 90 -310 110 {}
+L 4 -290 90 -290 110 {}
+L 4 -290 90 -210 90 {}
+L 4 -210 90 -210 110 {}
+L 4 -190 90 -190 110 {}
+L 4 -190 90 -130 90 {}
+L 4 -130 90 -130 110 {}
+L 4 -110 90 -110 110 {}
+L 4 -110 90 -90 90 {}
+L 4 -90 90 -90 110 {}
+L 4 -70 90 -70 110 {}
+L 4 -70 90 10 90 {}
+L 4 10 90 10 110 {}
+L 4 30 90 30 110 {}
+L 4 30 90 150 90 {}
+L 4 150 90 150 110 {}
+L 4 170 90 170 110 {}
+L 4 170 90 410 90 {}
+L 4 410 90 410 110 {}
+L 4 430 90 430 110 {}
+L 4 430 90 450 90 {}
+L 4 450 90 450 110 {}
+L 4 340 110 460 110 {}
+L 4 -390 110 -380 110 {}
+L 4 -380 70 -370 70 {}
+L 4 330 70 460 70 {}
+L 4 460 110 470 110 {}
+L 4 340 -110 470 -110 {}
+L 4 -390 -110 -380 -110 {}
+L 4 -290 -110 -290 -90 {}
+L 4 -290 -90 -270 -90 {}
+L 4 -270 -110 -270 -90 {}
+L 4 -210 -110 -210 -90 {}
+L 4 -210 -90 -120 -90 {}
+L 4 -120 -110 -120 -90 {}
+L 4 -250 -110 -250 -90 {}
+L 4 -250 -90 -230 -90 {}
+L 4 -230 -110 -230 -90 {}
+L 4 -310 -110 -310 -70 {}
+L 4 -310 -70 -100 -70 {}
+L 4 -100 -110 -100 -70 {}
+L 4 -280 -130 -280 -110 {}
+L 4 -240 -130 -240 -110 {}
+L 4 -190 -130 -190 -110 {}
+L 4 -160 -130 -160 -110 {}
+L 4 -130 -130 -130 -110 {}
+L 4 470 -0 490 0 {}
+L 7 360 -130 360 -110 {}
+L 7 320 -130 320 -110 {}
+L 7 -40 110 -40 130 {}
+L 7 -60 110 -60 130 {}
+L 7 -280 110 -280 130 {}
+L 7 -340 110 -340 130 {}
+L 7 440 110 440 130 {}
+L 7 -260 110 -260 130 {}
+L 7 -240 110 -240 130 {}
+L 7 -220 110 -220 130 {}
+L 7 -320 110 -320 130 {}
+L 7 -100 110 -100 130 {}
+L 7 -20 110 -20 130 {}
+L 7 -140 110 -140 130 {}
+L 7 -160 110 -160 130 {}
+L 7 -180 110 -180 130 {}
+L 7 -360 110 -360 130 {}
+L 7 120 110 120 130 {}
+L 7 0 110 0 130 {}
+L 7 400 110 400 130 {}
+L 7 140 110 140 130 {}
+L 7 60 110 60 130 {}
+L 7 40 110 40 130 {}
+L 7 80 110 80 130 {}
+L 7 100 110 100 130 {}
+L 7 200 110 200 130 {}
+L 7 380 110 380 130 {}
+L 7 360 110 360 130 {}
+L 7 340 110 340 130 {}
+L 7 320 110 320 130 {}
+L 7 300 110 300 130 {}
+L 7 280 110 280 130 {}
+L 7 260 110 260 130 {}
+L 7 240 110 240 130 {}
+L 7 220 110 220 130 {}
+L 7 180 110 180 130 {}
+B 5 -342.5 -132.5 -337.5 -127.5 {name=iref_cp dir=in }
+B 5 357.5 -132.5 362.5 -127.5 {name=vss dir=inout }
+B 5 317.5 -132.5 322.5 -127.5 {name=vdd dir=inout }
+B 5 -42.5 127.5 -37.5 132.5 {name=vco_out dir=inout }
+B 5 -62.5 127.5 -57.5 132.5 {name=vco_vctrl dir=inout }
+B 5 -282.5 127.5 -277.5 132.5 {name=Up dir=inout }
+B 5 -342.5 127.5 -337.5 132.5 {name=pfd_QA dir=inout }
+B 5 437.5 127.5 442.5 132.5 {name=out_to_buffer dir=inout }
+B 5 -412.5 -2.5 -407.5 2.5 {name=in_ref dir=in }
+B 5 -262.5 127.5 -257.5 132.5 {name=nUp dir=inout }
+B 5 487.5 -2.5 492.5 2.5 {name=out_to_pad dir=out }
+B 5 -242.5 127.5 -237.5 132.5 {name=Down dir=inout }
+B 5 -222.5 127.5 -217.5 132.5 {name=nDown dir=inout }
+B 5 -322.5 127.5 -317.5 132.5 {name=pfd_QB dir=inout }
+B 5 -282.5 -132.5 -277.5 -127.5 {name=lf_D0 dir=in }
+B 5 -102.5 127.5 -97.5 132.5 {name=lf_vc dir=inout }
+B 5 -22.5 127.5 -17.5 132.5 {name=out_first_buffer dir=inout }
+B 5 -142.5 127.5 -137.5 132.5 {name=cp_biasp dir=inout }
+B 5 -162.5 127.5 -157.5 132.5 {name=cp_pswitch dir=inout }
+B 5 -182.5 127.5 -177.5 132.5 {name=cp_nswitch dir=inout }
+B 5 -362.5 127.5 -357.5 132.5 {name=pfd_reset dir=inout }
+B 5 -162.5 -132.5 -157.5 -127.5 {name=s_0 sig_type=std_logic dir=in}
+B 5 -132.5 -132.5 -127.5 -127.5 {name=MC sig_type=std_logic dir=in}
+B 5 -192.5 -132.5 -187.5 -127.5 {name=s_1 sig_type=std_logic dir=in}
+B 5 117.5 127.5 122.5 132.5 {name=out_by_2 dir=inout }
+B 5 -2.5 127.5 2.5 132.5 {name=out_to_div dir=inout }
+B 5 397.5 127.5 402.5 132.5 {name=out_div dir=inout }
+B 5 137.5 127.5 142.5 132.5 {name=n_out_by_2 dir=inout }
+B 5 57.5 127.5 62.5 132.5 {name=n_out_div_2 dir=inout }
+B 5 37.5 127.5 42.5 132.5 {name=out_div_2 dir=inout }
+B 5 77.5 127.5 82.5 132.5 {name=n_out_buffer_div_2 dir=inout }
+B 5 97.5 127.5 102.5 132.5 {name=out_buffer_div_2 dir=inout }
+B 5 197.5 127.5 202.5 132.5 {name=n_clk_0 sig_type=std_logic dir=inout }
+B 5 377.5 127.5 382.5 132.5 {name=s1n sig_type=std_logic dir=inout }
+B 5 357.5 127.5 362.5 132.5 {name=s0n sig_type=std_logic dir=inout }
+B 5 337.5 127.5 342.5 132.5 {name=clk_2_f sig_type=std_logic dir=inout }
+B 5 317.5 127.5 322.5 132.5 {name=clk_d sig_type=std_logic dir=inout }
+B 5 297.5 127.5 302.5 132.5 {name=clk_out_mux21 sig_type=std_logic dir=inout }
+B 5 277.5 127.5 282.5 132.5 {name=clk_5 sig_type=std_logic dir=inout }
+B 5 257.5 127.5 262.5 132.5 {name=clk_pre sig_type=std_logic dir=inout }
+B 5 237.5 127.5 242.5 132.5 {name=n_clk_1 sig_type=std_logic dir=inout }
+B 5 217.5 127.5 222.5 132.5 {name=clk_1 sig_type=std_logic dir=inout }
+B 5 177.5 127.5 182.5 132.5 {name=clk_0 sig_type=std_logic dir=inout }
+B 5 -242.5 -132.5 -237.5 -127.5 {name=lf_D0 dir=in}
+T {@symname} -33 -6 0 0 0.3 0.3 {}
+T {@name} -15 -102 0 0 0.2 0.2 {}
+T {iref_cp} -336 -105 1 0 0.2 0.2 {}
+T {vss} 364 -105 1 0 0.2 0.2 {}
+T {vdd} 324 -105 1 0 0.2 0.2 {}
+T {vco_out} -41 190 1 1 0.2 0.2 {}
+T {vco_vctrl} -61 190 1 1 0.2 0.2 {}
+T {Up} -294 165 3 0 0.2 0.2 {}
+T {pfd_QA} -354 165 3 0 0.2 0.2 {}
+T {out_to_buffer} 439 190 1 1 0.2 0.2 {}
+T {in_ref} -375 -4 0 0 0.2 0.2 {}
+T {nUp} -274 165 3 0 0.2 0.2 {}
+T {out_to_pad} 465 -4 0 1 0.2 0.2 {}
+T {Down} -254 165 3 0 0.2 0.2 {}
+T {nDown} -234 165 3 0 0.2 0.2 {}
+T {pfd_QB} -334 165 3 0 0.2 0.2 {}
+T {vco_D0} -294 -155 3 1 0.2 0.2 {}
+T {lf_vc} -101 160 1 1 0.2 0.2 {}
+T {out_first_buffer} -21 190 1 1 0.2 0.2 {}
+T {cp_biasp} -141 180 1 1 0.2 0.2 {}
+T {cp_pswitch} -161 180 1 1 0.2 0.2 {}
+T {cp_nswitch} -181 180 1 1 0.2 0.2 {}
+T {pfd_reset} -374 165 3 0 0.2 0.2 {}
+T {s_0} -174 -135 3 1 0.2 0.2 {}
+T {MC} -144 -135 3 1 0.2 0.2 {}
+T {s_1} -204 -135 3 1 0.2 0.2 {}
+T {out_by_2} 106 210 3 0 0.2 0.2 {}
+T {out_to_div} -1 190 1 1 0.2 0.2 {}
+T {out_div} 399 190 1 1 0.2 0.2 {}
+T {n_out_by_2} 126 210 3 0 0.2 0.2 {}
+T {n_out_div_2} 46 210 3 0 0.2 0.2 {}
+T {out_div_2} 26 210 3 0 0.2 0.2 {}
+T {n_out_buffer_div_2} 66 210 3 0 0.2 0.2 {}
+T {out_buffer_div_2} 86 210 3 0 0.2 0.2 {}
+T {n_clk_0} 199 190 1 1 0.2 0.2 {}
+T {s1n} 379 190 1 1 0.2 0.2 {}
+T {s0n} 359 190 1 1 0.2 0.2 {}
+T {clk_2_f} 339 190 1 1 0.2 0.2 {}
+T {clk_d} 319 190 1 1 0.2 0.2 {}
+T {clk_out_mux21} 299 190 1 1 0.2 0.2 {}
+T {clk_5} 279 190 1 1 0.2 0.2 {}
+T {clk_pre} 259 190 1 1 0.2 0.2 {}
+T {n_clk_1} 239 190 1 1 0.2 0.2 {}
+T {clk_1} 219 190 1 1 0.2 0.2 {}
+T {clk_0} 179 190 1 1 0.2 0.2 {}
+T {lf_D0} -254 -155 3 1 0.2 0.2 {}
+T {PFD} -350 93.5 0 0 0.2 0.2 {}
+T {Interface} -273.75 94.75 0 0 0.2 0.2 {}
+T {CP} -166.25 93.5 0 0 0.2 0.2 {}
+T {LF} -106.25 93.5 0 0 0.2 0.2 {}
+T {VCO} -42.5 93.5 0 0 0.2 0.2 {}
+T {DIV_BY_2} 65 93.5 0 0 0.2 0.2 {}
+T {FREQ_DIV} 261.25 93.5 0 0 0.2 0.2 {}
+T {OUT} 430 93.5 0 0 0.2 0.2 {}
+T {DEBUG} 3.75 73.5 0 0 0.2 0.2 {}
+T {CONFIG} -236.25 -86.5 0 0 0.2 0.2 {}
+T {FREQ_DIV} -186.25 -105.25 0 0 0.2 0.2 {}
+T {VCO} -290 -105.25 0 0 0.2 0.2 {}
+T {LF} -245 -105.25 0 0 0.2 0.2 {}
diff --git a/xschem/trans_gate_mux2to8.sch b/xschem/trans_gate_mux2to8.sch
new file mode 100644
index 0000000..dd820cc
--- /dev/null
+++ b/xschem/trans_gate_mux2to8.sch
@@ -0,0 +1,64 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 380 -100 380 -70 { lab=vss}
+N 380 70 380 100 { lab=vdd}
+N 310 -100 350 -100 { lab=in}
+N 310 -100 310 -40 { lab=in}
+N 280 -40 310 -40 { lab=in}
+N 280 -40 280 0 { lab=in}
+N 310 100 350 100 { lab=in}
+N 310 40 310 100 { lab=in}
+N 280 40 310 40 { lab=in}
+N 280 0 280 40 { lab=in}
+N 410 100 450 100 { lab=out}
+N 450 40 450 100 { lab=out}
+N 450 40 480 40 { lab=out}
+N 480 0 480 40 { lab=out}
+N 410 -100 450 -100 { lab=out}
+N 450 -100 450 -40 { lab=out}
+N 450 -40 480 -40 { lab=out}
+N 480 -40 480 0 { lab=out}
+N 480 -0 540 0 { lab=out}
+N 220 -0 280 0 { lab=in}
+N 380 140 380 170 { lab=en_neg}
+N 380 -170 380 -140 { lab=en_pos}
+C {sky130_fd_pr/pfet_01v8.sym} 380 120 3 0 {name=M2
+L=0.15
+W=1.25
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 380 170 1 0 {name=p1 lab=en_neg}
+C {ipin.sym} 220 0 0 0 {name=p2 lab=in}
+C {opin.sym} 540 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 380 -120 1 0 {name=M1
+L=0.15
+W=1.25
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 380 -70 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 380 70 1 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 380 -170 3 0 {name=p4 lab=en_pos}
+C {iopin.sym} 460 170 1 0 {name=p5 lab=vdd}
+C {iopin.sym} 460 -170 3 0 {name=p6 lab=vss}
diff --git a/xschem/trans_gate_mux2to8.sym b/xschem/trans_gate_mux2to8.sym
new file mode 100644
index 0000000..26859d7
--- /dev/null
+++ b/xschem/trans_gate_mux2to8.sym
@@ -0,0 +1,55 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 0 90 0 {}
+L 4 -90 0 -70 0 {}
+L 4 -20 -50 20 -50 {}
+L 4 -20 -40 20 -40 {}
+L 4 20 -40 20 -20 {}
+L 4 20 -20 40 -20 {}
+L 4 40 -20 40 0 {}
+L 4 40 0 60 0 {}
+L 4 -20 -40 -20 -20 {}
+L 4 -40 -20 -20 -20 {}
+L 4 -40 -20 -40 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -20 50 20 50 {}
+L 4 -20 40 20 40 {}
+L 4 -20 20 -20 40 {}
+L 4 -40 20 -20 20 {}
+L 4 -40 0 -40 20 {}
+L 4 20 20 20 40 {}
+L 4 20 20 40 20 {}
+L 4 40 0 40 20 {}
+L 4 0 -60 -0 -50 {}
+L 4 0 60 0 70 {}
+L 4 -70 80 -0 80 {}
+L 4 -70 -70 -70 80 {}
+L 4 -70 -70 70 -70 {}
+L 4 70 -70 70 80 {}
+L 4 0 80 70 80 {}
+L 7 0 -90 0 -70 {}
+L 7 0 80 0 100 {}
+L 7 -40 -90 -40 -70 {}
+L 7 -40 80 -40 100 {}
+B 5 -2.5 -92.5 2.5 -87.5 {name=en_pos dir=inout }
+B 5 87.5 -2.5 92.5 2.5 {name=out dir=out }
+B 5 -92.5 -2.5 -87.5 2.5 {name=in dir=in }
+B 5 -2.5 97.5 2.5 102.5 {name=en_neg dir=inout }
+B 5 -42.5 -92.5 -37.5 -87.5 {name=vss dir=inout }
+B 5 -42.5 97.5 -37.5 102.5 {name=vdd dir=inout }
+A 4 0 55.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} 14 90 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {en_pos} -14 -95 3 1 0.2 0.2 {}
+T {out} 87 -13 0 1 0.2 0.2 {}
+T {in} -86 -14 0 0 0.2 0.2 {}
+T {en_neg} -2 104 1 1 0.2 0.2 {}
+T {vss} -54 -95 3 1 0.2 0.2 {}
+T {vdd} -42 104 1 1 0.2 0.2 {}
