tree: 8719f97d187bf5d5fd941c17417412ec2eb620a2 [path history] [tgz]
  1. afernandez_residue_amplifier/
  2. simulations/
  3. .spiceinit
  4. analog_wrapper_tb.sch
  5. and_pfd.sch
  6. and_pfd.sym
  7. bias.sch
  8. bias.sym
  9. bias_pex_c.sym
  10. buffer_salida.sch
  11. buffer_salida.sym
  12. buffer_salida_pex_c.sym
  13. cap1_loop_filter.sch
  14. cap1_loop_filter.sym
  15. cap2_loop_filter.sch
  16. cap2_loop_filter.sym
  17. cap3_loop_filter.sch
  18. cap3_loop_filter.sym
  19. charge_pump.sch
  20. charge_pump.sym
  21. charge_pump_pex_c.sym
  22. clock_inverter.sch
  23. clock_inverter.sym
  24. csvco.sch
  25. csvco.sym
  26. csvco_branch.sch
  27. csvco_branch.sym
  28. csvco_pex_c.sym
  29. DFF.sch
  30. DFF.sym
  31. dff_pfd_pex_c.sym
  32. DFlipFlop.sch
  33. DFlipFlop.sym
  34. div_by_2.sch
  35. div_by_2.sym
  36. div_by_2_pex_c.sym
  37. div_by_5.sch
  38. div_by_5.sym
  39. div_by_5_pex_c.sym
  40. example_por.sch
  41. example_por.sym
  42. example_por_tb.sch
  43. example_por_tb.spice.orig
  44. inverter_cp_x1.sch
  45. inverter_cp_x1.sym
  46. inverter_cp_x2.sch
  47. inverter_cp_x2.sym
  48. inverter_csvco.sch
  49. inverter_csvco.sym
  50. inverter_csvco_pex_c.sym
  51. inverter_min_x2.sch
  52. inverter_min_x2.sym
  53. inverter_min_x2_pex_c.sym
  54. inverter_min_x4.sch
  55. inverter_min_x4.sym
  56. inverter_min_x4_pex_c.sym
  57. latch_diff.sch
  58. latch_diff.sym
  59. loop_filter.sch
  60. loop_filter.sym
  61. loop_filter_pex_c.sym
  62. loop_filter_v2.sch
  63. loop_filter_v2.sym
  64. nor.sch
  65. nor.sym
  66. PFD.sch
  67. PFD.sym
  68. pfd_cp_interface.sch
  69. pfd_cp_interface.sym
  70. pfd_cp_interface_pex_c.sym
  71. PFD_pex_c.sym
  72. res_loop_filter.sch
  73. res_loop_filter.sym
  74. ring_osc_buffer.sch
  75. ring_osc_buffer.sym
  76. ring_osc_buffer_pex_c.sym
  77. tb_buffer_salida.sch
  78. tb_buffer_salida_pex_c.sch
  79. tb_charge_pump.sch
  80. tb_csvco.sch
  81. tb_csvco_pex_c.sch
  82. tb_DFF.sch
  83. tb_div_by_2.sch
  84. tb_div_by_2_pex_c.sch
  85. tb_div_by_5.sch
  86. tb_div_by_5_pex_c.sch
  87. tb_inverter_csvco.sch
  88. tb_loop_filter.sch
  89. tb_PFD.sch
  90. tb_PFD_pex.sch
  91. tb_top_pll_v1.sch
  92. tb_top_pll_v1_pex_c.sch
  93. tb_top_pll_v1_pex_no_integration.sch
  94. tb_top_pll_v2_pex_c.sch
  95. top_pll_v1.sch
  96. top_pll_v1.sym
  97. top_pll_v1_pex_c.sym
  98. top_pll_v1_pex_no_integration.sch
  99. top_pll_v1_pex_no_integration.sym
  100. top_pll_v2.sch
  101. top_pll_v2.sym
  102. top_pll_v2_pex_c.sym
  103. top_pll_v2_pex_no_integration.sym
  104. trans_gate.sch
  105. trans_gate.sym
  106. user_analog_project_wrapper.sch
  107. user_analog_project_wrapper.sym
  108. xschemrc