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+## Introduction
+As posgraduate students at [Universidad Nacional del Sur](https://www.uns.edu.ar/) (Bahía Blanca, Argentina) , we ([Álvaro Fernandez](https://github.com/afernandezb) and [Diego Hernando](https://github.com/diegohernando)) are specializing in the analog design of mixed-signal integrated circuits. Particullary we are working on high-speed ADCs and clock circuits applied to optcial coherent digital communications. Therefore this first thest chip contains several circuits that will allow us to corroborate the various methods and techniques learned so far in our studies. This is not our final chip version, but a first approach to whole IC desing.
+
+Our Master's studies are possible thanks to the [Fundación Fulgor](http://www.fundacionfulgor.org.ar/sitio/index.php). Fundación Fulgor seeks to create growth opportunities for as many members of Argentine society as possible. The main instrument for the creation of opportunities is education, together with the search for the insertion of its beneficiaries in the productive process. For this reason, the Foundation focuses its efforts on the education and educational support tasks. Fundación Fulgor develops high-level undergraduate and graduate training programs, generating leaders with experience in leading projects and training human resources with great social impact. To this end, Fundación Fulgor not only provides academic scholarships, but also collaborates closely with several universities ([Universidad Nacional del Sur](https://www.uns.edu.ar/), [Universidad Nacional de Córdoba](https://www.unc.edu.ar/), and in the particular case of microelectronics collaborates with The Argentine School of Micro-Nanoelectronics, Technology and Applications, [EAMTA](https://sites.google.com/view/congresoargentinoelectronica/eamta-2021).
+
+---
+
## Repo Setup
In order to get de PDK, tools and paths needed to get the desing working just run the [skywater_setup.sh](skywater_setup.sh) script.
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- [lvs.sh](ext.sh): compares the layout and schematic `.spice` files, and check if they match.
The script will ask you for the cellname. You need to make sure that the **schematic** and the **layout** views of the cell match in **names** :exclamation:.
The LVS report can be found in `mag/extractions/lvs_{cellname}.out`
-
+
+ ---
+
## Desing Description
-As posgraduate students, we are training ourselves and testing several analog desings from various mixed signal circuits.
-
In this run you can find:
+ - There versions of a A 1GHz Current Starved VCO based PLL:
+ - Version 1: It works wir a reference frequency of 100MHz and generates an output frequency of 1GHz.
+ - Version 2: It adds progrmabillity to the loop filter by adding capacitance in parallel with the secondary loop filter capacitor.
+ - Version 3: It adds progrmabillity not just to the loop filter, but also to the frequency divider. Now is possible to divide the VCO output frequency by 4,6,8,10,12 and 20. This will allow us to use several reference frequencies and to make the PLL work if the tapeout comes in the Slow-Slow corner.
- - A 1GHz Current Starved VCO based PLL
+ - A Residual Amplifier With Variable Output Common Mode and Gain
