Merge branch 'efabless:main' into main
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..19e5b0a
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,16 @@
+# De ser necesario se pueden incluir con git add --force archivo-a-NO-ignorar
+
+#Archivos de extraccion con magic
+*.ext
+*.sim
+*.nodes
+
+#Archivos de logueo en general
+*.log
+
+#Salida de comparaciones LVS
+*.out
+
+#Archivos con resultados numericos de simulacion
+*.raw
+
diff --git a/README.md b/README.md
index 5e01221..3fc6d6b 100644
--- a/README.md
+++ b/README.md
@@ -1,18 +1,79 @@
-# Caravel Analog User
+# Caravel Analog Fulgor
[](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml) [](https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml)
---
-| :exclamation: Important Note |
-|-----------------------------------------|
+## Repo Setup
-## Please fill in your project documentation in this README.md file
+In order to get de PDK, tools and paths needed to get the desing working just run the [skywater_setup.sh](skywater_setup.sh) script.
+
+```
+./skywater_setup.sh
+```
+
+This script creates a directory named `skywater` in `$HOME`. Under this directory you will find the [Google-Skywater 130nm Open Source PDK](https://github.com/google/skywater-pdk) and several tools and configurations needed, in order to work with the analog desing flow.
+
+This script does the following:
+ - Creates `skywater` directory at `$HOME`
+ - Installs all the packages needed to use the opensource tools and the [Google-Skywater 130nm Open Source PDK](https://github.com/google/skywater-pdk)
+ - Installs the simualtion engine [ngspcie](http://ngspice.sourceforge.net/)
+ > There is an issue with the ngspice installation.
+ > If you use `adms` with the install, chances are
+ > that ngspice installation fails due it can't finde
+ > `awk`, although awk is installed. In [Steffan Schippers's video] (https://xschem.sourceforge.io/stefan/xschem_man/video_tutorials/install_xschem_sky130_and_ngspice.mp4)
+ > it's shown how to resolve this issue.
+ - Installs the schematic caputre tool [XSCHEM](https://xschem.sourceforge.io/stefan/index.html)
+ - Installs XSCHEM symbol library for the Google-Skywater 130nm Open Source PDK.
+ - Installs the layout desing tool [magic](http://opencircuitdesign.com/magic/index.html)
+ - Installs the layout desing tool [klayout](https://www.klayout.de/)
+ - Installs the LVS check tool [netgen](http://opencircuitdesign.com/netgen/index.html)
+ - Clones, installs & pathches the [Google-Skywater 130nm Open Source PDK](https://github.com/google/skywater-pdk)
+ - Installs the [Open_PDKs](http://opencircuitdesign.com/open_pdks/index.html)
+
+ ## Running the tools
+
+ ### Xschem
+In the [xschem](xschem) folder all the schematics and spice symbols are located. To open one of those shematics the following commands need to be run:
+```bash
+cd caravel_analog_fulgor/xschem
+xschem {schematic_name.sch}
+```
+In the xschem folder it is found the [xschemrc](xschem/xschemrc) file, where the paths to the xschem libraries are defined.
+There is also a `simualtions` folder where all the `.spice` and `.raw` files are stored.
+
+### Magic
+To run magic and be able to edit or desing a layout the following commands need to be run:
+```bash
+cd caravel_analog_fulgor/mag
+magic -rcfile magicrc {layout_name.mag}
+```
+The [magicrc](magicrc) file specifies where the open_pdk layout libraries are located. If magic is used without the -rcfile specification, the sky130 library won't be loaded.
+
+### Extractions
+In order to get the `.spice` files form layout or extract parasitics from the desings, extractions must be run. The following scripts make easy this step:
+ - [ext.sh](ext.sh): extraction without creating ports. It extract files for LVS and PEX with C parasitics and RC parasitics.
+ - [ext_port.sh](ext_port.sh): creates ports from the layout labels. It generates the same files as the previous script.
+
+To run them, just tipe:
+```bash
+./ext.sh
+./ext_port.sh
+```
+The script will ask you for the cellname. You need to make sure that the **schematic** and the **layout** views of the cell match in **names** :exclamation:.
+
+### LVS
+[netgen](http://opencircuitdesign.com/netgen/index.html) is used as the LVS test tool. You need to provide to it the path to the `.spice` files to compare (from layout and schematic) and with the design rools from the PDK. To make this step easier, there is also a script:
+- [lvs.sh](ext.sh): compares the layout and schematic `.spice` files, and check if they match.
+The script will ask you for the cellname. You need to make sure that the **schematic** and the **layout** views of the cell match in **names** :exclamation:.
+The LVS report can be found in `mag/extractions/lvs_{cellname}.out`
+
+## Desing Description
+
+As posgraduate students, we are training ourselves and testing several analog desings from various mixed signal circuits.
+
+In this run you can find:
+
+ - A 1GHz Current Starved VCO based PLL
-:warning: | Use this sample project for analog user projects.
-:---: | :---
-
----
-
-Refer to [README](docs/source/index.rst) for this sample project documentation.
diff --git a/checks/user_analog_project_wrapper.magic.drc b/checks/user_analog_project_wrapper.magic.drc
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/checks/user_analog_project_wrapper.magic.drc
@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/checks/user_analog_project_wrapper.magic.drc.mag b/checks/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..b2eadb0
--- /dev/null
+++ b/checks/user_analog_project_wrapper.magic.drc.mag
@@ -0,0 +1,4883 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624402262
+<< checkpaint >>
+rect -4732 -4732 588732 708732
+<< nwell >>
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+rect 124441 660015 133067 660083
+<< nsubdiff >>
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+<< nsubdiffcont >>
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+<< locali >>
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+<< viali >>
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+rect 512421 567275 515308 573195
+rect 516800 567275 516824 573195
+rect 510856 567251 516824 567275
+rect 510216 566772 510536 567176
+rect 503912 566673 509880 566697
+rect 503912 560753 503936 566673
+rect 505781 560753 508668 566673
+rect 509856 560753 509880 566673
+rect 503912 560729 509880 560753
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+rect 505781 555373 508668 560729
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+rect 510494 560654 510536 566772
+rect 512421 566697 515308 567251
+rect 517160 567176 517202 573294
+rect 517438 567176 517480 573294
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+rect 519350 567275 522237 573195
+rect 523744 567275 523768 573195
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+rect 517438 560654 517480 566772
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+rect 523744 560753 523768 566673
+rect 517800 560729 523768 560753
+rect 517160 560452 517480 560654
+rect 519350 555373 522237 560729
+rect 491289 555225 522237 555373
+rect 491289 540589 491316 555225
+rect 521952 540589 522237 555225
+rect 491289 540442 522237 540589
+rect 451976 378829 467642 540237
+rect 519350 540149 522237 540442
+rect 451976 363553 452175 378829
+rect 467131 363553 467642 378829
+rect 451976 240343 467642 363553
+rect 451976 227015 452145 240343
+rect 452007 225387 452145 227015
+rect 467421 227015 467642 240343
+rect 545384 432002 561540 584115
+rect 545384 417366 545733 432002
+rect 561009 417366 561540 432002
+rect 467421 225387 467559 227015
+rect 452007 225352 467559 225387
+rect 338385 136722 338714 151535
+rect 100463 136311 116619 136634
+rect 338617 136579 338714 136722
+rect 354310 136722 354541 151535
+rect 545384 151638 561540 417366
+rect 545384 137728 545507 151638
+rect 354310 136579 354407 136722
+rect 545458 136682 545507 137728
+rect 561423 137728 561540 151638
+rect 561423 136682 561472 137728
+rect 545458 136595 561472 136682
+rect 338617 136437 354407 136579
+use mimcap_decoup_1x5 mimcap_decoup_1x5_6
+array 0 0 34500 0 2 6522
+timestamp 1624402262
+transform 1 0 38481 0 1 560871
+box 0 -159 34500 6363
+use top_pll_v1 top_pll_v1_1
+timestamp 1624402262
+transform 1 0 14782 0 1 657248
+box -656 -33693 50195 2860
+use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_2
+array 0 0 6724 0 8 6522
+timestamp 1624402262
+transform 1 0 74005 0 1 616157
+box -3351 -3261 3373 3261
+use top_pll_v2 top_pll_v2_0
+timestamp 1624402262
+transform -1 0 133068 0 1 657248
+box -656 -33693 50195 2860
+use mimcap_decoup_1x5 mimcap_decoup_1x5_5
+array 0 0 34500 0 2 6522
+timestamp 1624402262
+transform 1 0 126717 0 1 559996
+box 0 -159 34500 6363
+use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_1
+array 0 0 6724 0 8 6522
+timestamp 1624402262
+transform 1 0 144463 0 1 616442
+box -3351 -3261 3373 3261
+use top_pll_v1 top_pll_v1_0
+timestamp 1624402262
+transform -1 0 206380 0 1 656706
+box -656 -33693 50195 2860
+use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_0
+array 0 0 6724 0 6 6522
+timestamp 1624402262
+transform 1 0 220679 0 1 616773
+box -3351 -3261 3373 3261
+use mimcap_decoup_1x5 mimcap_decoup_1x5_4
+array 0 0 34500 0 2 6522
+timestamp 1624402262
+transform 1 0 197202 0 1 560156
+box 0 -159 34500 6363
+use bias bias_0
+timestamp 1624402262
+transform 1 0 202834 0 -1 687483
+box -54 -412 44317 2238
+use mimcap_decoup_1x5 mimcap_decoup_1x5_3
+array 0 0 34500 0 1 6522
+timestamp 1624402262
+transform -1 0 345445 0 1 602155
+box 0 -159 34500 6363
+use mimcap_decoup_1x5 mimcap_decoup_1x5_2
+array 0 0 34500 0 2 6522
+timestamp 1624402262
+transform 1 0 291410 0 1 559700
+box 0 -159 34500 6363
+use res_amp_top res_amp_top_0
+timestamp 1624402262
+transform 1 0 349695 0 1 630386
+box -5005 -972 31038 12726
+use mimcap_decoup_1x5 mimcap_decoup_1x5_1
+array 0 0 34500 0 2 6522
+timestamp 1624402262
+transform 1 0 382888 0 1 560156
+box 0 -159 34500 6363
+use mimcap_decoup_1x5 mimcap_decoup_1x5_0
+array 0 0 34500 0 2 6522
+timestamp 1624402262
+transform 1 0 489384 0 1 560611
+box 0 -159 34500 6363
+<< labels >>
+flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1400 0 0 0 gpio_analog[0]
+port 1 nsew
+flabel metal3 s -800 381864 480 381976 0 FreeSans 1400 0 0 0 gpio_analog[10]
+port 2 nsew
+flabel metal3 s -800 338642 480 338754 0 FreeSans 1400 0 0 0 gpio_analog[11]
+port 3 nsew
+flabel metal3 s -800 295420 480 295532 0 FreeSans 1400 0 0 0 gpio_analog[12]
+port 4 nsew
+flabel metal3 s -800 252398 480 252510 0 FreeSans 1400 0 0 0 gpio_analog[13]
+port 5 nsew
+flabel metal3 s -800 124776 480 124888 0 FreeSans 1400 0 0 0 gpio_analog[14]
+port 6 nsew
+flabel metal3 s -800 81554 480 81666 0 FreeSans 1400 0 0 0 gpio_analog[15]
+port 7 nsew
+flabel metal3 s -800 38332 480 38444 0 FreeSans 1400 0 0 0 gpio_analog[16]
+port 8 nsew
+flabel metal3 s -800 16910 480 17022 0 FreeSans 1400 0 0 0 gpio_analog[17]
+port 9 nsew
+flabel metal3 s 583520 313652 584800 313764 0 FreeSans 1400 0 0 0 gpio_analog[1]
+port 10 nsew
+flabel metal3 s 583520 358874 584800 358986 0 FreeSans 1400 0 0 0 gpio_analog[2]
+port 11 nsew
+flabel metal3 s 583520 405296 584800 405408 0 FreeSans 1400 0 0 0 gpio_analog[3]
+port 12 nsew
+flabel metal3 s 583520 449718 584800 449830 0 FreeSans 1400 0 0 0 gpio_analog[4]
+port 13 nsew
+flabel metal3 s 583520 494140 584800 494252 0 FreeSans 1400 0 0 0 gpio_analog[5]
+port 14 nsew
+flabel metal3 s 583520 583562 584800 583674 0 FreeSans 1400 0 0 0 gpio_analog[6]
+port 15 nsew
+flabel metal3 s -800 511530 480 511642 0 FreeSans 1400 0 0 0 gpio_analog[7]
+port 16 nsew
+flabel metal3 s -800 468308 480 468420 0 FreeSans 1400 0 0 0 gpio_analog[8]
+port 17 nsew
+flabel metal3 s -800 425086 480 425198 0 FreeSans 1400 0 0 0 gpio_analog[9]
+port 18 nsew
+flabel metal3 s 583520 270412 584800 270524 0 FreeSans 1400 0 0 0 gpio_noesd[0]
+port 19 nsew
+flabel metal3 s -800 380682 480 380794 0 FreeSans 1400 0 0 0 gpio_noesd[10]
+port 20 nsew
+flabel metal3 s -800 337460 480 337572 0 FreeSans 1400 0 0 0 gpio_noesd[11]
+port 21 nsew
+flabel metal3 s -800 294238 480 294350 0 FreeSans 1400 0 0 0 gpio_noesd[12]
+port 22 nsew
+flabel metal3 s -800 251216 480 251328 0 FreeSans 1400 0 0 0 gpio_noesd[13]
+port 23 nsew
+flabel metal3 s -800 123594 480 123706 0 FreeSans 1400 0 0 0 gpio_noesd[14]
+port 24 nsew
+flabel metal3 s -800 80372 480 80484 0 FreeSans 1400 0 0 0 gpio_noesd[15]
+port 25 nsew
+flabel metal3 s -800 37150 480 37262 0 FreeSans 1400 0 0 0 gpio_noesd[16]
+port 26 nsew
+flabel metal3 s -800 15728 480 15840 0 FreeSans 1400 0 0 0 gpio_noesd[17]
+port 27 nsew
+flabel metal3 s 583520 314834 584800 314946 0 FreeSans 1400 0 0 0 gpio_noesd[1]
+port 28 nsew
+flabel metal3 s 583520 360056 584800 360168 0 FreeSans 1400 0 0 0 gpio_noesd[2]
+port 29 nsew
+flabel metal3 s 583520 406478 584800 406590 0 FreeSans 1400 0 0 0 gpio_noesd[3]
+port 30 nsew
+flabel metal3 s 583520 450900 584800 451012 0 FreeSans 1400 0 0 0 gpio_noesd[4]
+port 31 nsew
+flabel metal3 s 583520 495322 584800 495434 0 FreeSans 1400 0 0 0 gpio_noesd[5]
+port 32 nsew
+flabel metal3 s 583520 584744 584800 584856 0 FreeSans 1400 0 0 0 gpio_noesd[6]
+port 33 nsew
+flabel metal3 s -800 510348 480 510460 0 FreeSans 1400 0 0 0 gpio_noesd[7]
+port 34 nsew
+flabel metal3 s -800 467126 480 467238 0 FreeSans 1400 0 0 0 gpio_noesd[8]
+port 35 nsew
+flabel metal3 s -800 423904 480 424016 0 FreeSans 1400 0 0 0 gpio_noesd[9]
+port 36 nsew
+flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1400 0 0 0 io_analog[0]
+port 37 nsew
+flabel metal3 s 0 680242 1700 685242 0 FreeSans 1400 0 0 0 io_analog[10]
+port 38 nsew
+flabel metal3 s 566594 702300 571594 704800 0 FreeSans 2400 180 0 0 io_analog[1]
+port 39 nsew
+flabel metal3 s 465394 702300 470394 704800 0 FreeSans 2400 180 0 0 io_analog[2]
+port 40 nsew
+flabel metal3 s 413394 702300 418394 704800 0 FreeSans 2400 180 0 0 io_analog[3]
+port 41 nsew
+flabel metal3 s 329294 702300 334294 704800 0 FreeSans 2400 180 0 0 io_analog[4]
+port 42 nsew
+flabel metal3 s 227594 702300 232594 704800 0 FreeSans 2400 180 0 0 io_analog[5]
+port 43 nsew
+flabel metal3 s 175894 702300 180894 704800 0 FreeSans 2400 180 0 0 io_analog[6]
+port 44 nsew
+flabel metal3 s 120194 702300 125194 704800 0 FreeSans 2400 180 0 0 io_analog[7]
+port 45 nsew
+flabel metal3 s 68194 702300 73194 704800 0 FreeSans 2400 180 0 0 io_analog[8]
+port 46 nsew
+flabel metal3 s 16194 702300 21194 704800 0 FreeSans 2400 180 0 0 io_analog[9]
+port 47 nsew
+flabel metal3 s 318994 702300 323994 704800 0 FreeSans 2400 180 0 0 io_analog[4]
+port 42 nsew
+flabel metal3 s 217294 702300 222294 704800 0 FreeSans 2400 180 0 0 io_analog[5]
+port 43 nsew
+flabel metal3 s 165594 702300 170594 704800 0 FreeSans 2400 180 0 0 io_analog[6]
+port 44 nsew
+flabel metal3 s 326794 702300 328994 704800 0 FreeSans 2400 180 0 0 io_clamp_high[0]
+port 48 nsew
+flabel metal3 s 225094 702300 227294 704800 0 FreeSans 2400 180 0 0 io_clamp_high[1]
+port 49 nsew
+flabel metal3 s 173394 702300 175594 704800 0 FreeSans 2400 180 0 0 io_clamp_high[2]
+port 50 nsew
+flabel metal3 s 324294 702300 326494 704800 0 FreeSans 2400 180 0 0 io_clamp_low[0]
+port 51 nsew
+flabel metal3 s 222594 702300 224794 704800 0 FreeSans 2400 180 0 0 io_clamp_low[1]
+port 52 nsew
+flabel metal3 s 170894 702300 173094 704800 0 FreeSans 2400 180 0 0 io_clamp_low[2]
+port 53 nsew
+flabel metal3 s 583520 2726 584800 2838 0 FreeSans 1400 0 0 0 io_in[0]
+port 54 nsew
+flabel metal3 s 583520 408842 584800 408954 0 FreeSans 1400 0 0 0 io_in[10]
+port 55 nsew
+flabel metal3 s 583520 453264 584800 453376 0 FreeSans 1400 0 0 0 io_in[11]
+port 56 nsew
+flabel metal3 s 583520 497686 584800 497798 0 FreeSans 1400 0 0 0 io_in[12]
+port 57 nsew
+flabel metal3 s 583520 587108 584800 587220 0 FreeSans 1400 0 0 0 io_in[13]
+port 58 nsew
+flabel metal3 s -800 507984 480 508096 0 FreeSans 1400 0 0 0 io_in[14]
+port 59 nsew
+flabel metal3 s -800 464762 480 464874 0 FreeSans 1400 0 0 0 io_in[15]
+port 60 nsew
+flabel metal3 s -800 421540 480 421652 0 FreeSans 1400 0 0 0 io_in[16]
+port 61 nsew
+flabel metal3 s -800 378318 480 378430 0 FreeSans 1400 0 0 0 io_in[17]
+port 62 nsew
+flabel metal3 s -800 335096 480 335208 0 FreeSans 1400 0 0 0 io_in[18]
+port 63 nsew
+flabel metal3 s -800 291874 480 291986 0 FreeSans 1400 0 0 0 io_in[19]
+port 64 nsew
+flabel metal3 s 583520 7454 584800 7566 0 FreeSans 1400 0 0 0 io_in[1]
+port 65 nsew
+flabel metal3 s -800 248852 480 248964 0 FreeSans 1400 0 0 0 io_in[20]
+port 66 nsew
+flabel metal3 s -800 121230 480 121342 0 FreeSans 1400 0 0 0 io_in[21]
+port 67 nsew
+flabel metal3 s -800 78008 480 78120 0 FreeSans 1400 0 0 0 io_in[22]
+port 68 nsew
+flabel metal3 s -800 34786 480 34898 0 FreeSans 1400 0 0 0 io_in[23]
+port 69 nsew
+flabel metal3 s -800 13364 480 13476 0 FreeSans 1400 0 0 0 io_in[24]
+port 70 nsew
+flabel metal3 s -800 8636 480 8748 0 FreeSans 1400 0 0 0 io_in[25]
+port 71 nsew
+flabel metal3 s -800 3908 480 4020 0 FreeSans 1400 0 0 0 io_in[26]
+port 72 nsew
+flabel metal3 s 583520 12182 584800 12294 0 FreeSans 1400 0 0 0 io_in[2]
+port 73 nsew
+flabel metal3 s 583520 16910 584800 17022 0 FreeSans 1400 0 0 0 io_in[3]
+port 74 nsew
+flabel metal3 s 583520 21638 584800 21750 0 FreeSans 1400 0 0 0 io_in[4]
+port 75 nsew
+flabel metal3 s 583520 48096 584800 48208 0 FreeSans 1400 0 0 0 io_in[5]
+port 76 nsew
+flabel metal3 s 583520 92754 584800 92866 0 FreeSans 1400 0 0 0 io_in[6]
+port 77 nsew
+flabel metal3 s 583520 272776 584800 272888 0 FreeSans 1400 0 0 0 io_in[7]
+port 78 nsew
+flabel metal3 s 583520 317198 584800 317310 0 FreeSans 1400 0 0 0 io_in[8]
+port 79 nsew
+flabel metal3 s 583520 362420 584800 362532 0 FreeSans 1400 0 0 0 io_in[9]
+port 80 nsew
+flabel metal3 s 583520 1544 584800 1656 0 FreeSans 1400 0 0 0 io_in_3v3[0]
+port 81 nsew
+flabel metal3 s 583520 407660 584800 407772 0 FreeSans 1400 0 0 0 io_in_3v3[10]
+port 82 nsew
+flabel metal3 s 583520 452082 584800 452194 0 FreeSans 1400 0 0 0 io_in_3v3[11]
+port 83 nsew
+flabel metal3 s 583520 496504 584800 496616 0 FreeSans 1400 0 0 0 io_in_3v3[12]
+port 84 nsew
+flabel metal3 s 583520 585926 584800 586038 0 FreeSans 1400 0 0 0 io_in_3v3[13]
+port 85 nsew
+flabel metal3 s -800 509166 480 509278 0 FreeSans 1400 0 0 0 io_in_3v3[14]
+port 86 nsew
+flabel metal3 s -800 465944 480 466056 0 FreeSans 1400 0 0 0 io_in_3v3[15]
+port 87 nsew
+flabel metal3 s -800 422722 480 422834 0 FreeSans 1400 0 0 0 io_in_3v3[16]
+port 88 nsew
+flabel metal3 s -800 379500 480 379612 0 FreeSans 1400 0 0 0 io_in_3v3[17]
+port 89 nsew
+flabel metal3 s -800 336278 480 336390 0 FreeSans 1400 0 0 0 io_in_3v3[18]
+port 90 nsew
+flabel metal3 s -800 293056 480 293168 0 FreeSans 1400 0 0 0 io_in_3v3[19]
+port 91 nsew
+flabel metal3 s 583520 6272 584800 6384 0 FreeSans 1400 0 0 0 io_in_3v3[1]
+port 92 nsew
+flabel metal3 s -800 250034 480 250146 0 FreeSans 1400 0 0 0 io_in_3v3[20]
+port 93 nsew
+flabel metal3 s -800 122412 480 122524 0 FreeSans 1400 0 0 0 io_in_3v3[21]
+port 94 nsew
+flabel metal3 s -800 79190 480 79302 0 FreeSans 1400 0 0 0 io_in_3v3[22]
+port 95 nsew
+flabel metal3 s -800 35968 480 36080 0 FreeSans 1400 0 0 0 io_in_3v3[23]
+port 96 nsew
+flabel metal3 s -800 14546 480 14658 0 FreeSans 1400 0 0 0 io_in_3v3[24]
+port 97 nsew
+flabel metal3 s -800 9818 480 9930 0 FreeSans 1400 0 0 0 io_in_3v3[25]
+port 98 nsew
+flabel metal3 s -800 5090 480 5202 0 FreeSans 1400 0 0 0 io_in_3v3[26]
+port 99 nsew
+flabel metal3 s 583520 11000 584800 11112 0 FreeSans 1400 0 0 0 io_in_3v3[2]
+port 100 nsew
+flabel metal3 s 583520 15728 584800 15840 0 FreeSans 1400 0 0 0 io_in_3v3[3]
+port 101 nsew
+flabel metal3 s 583520 20456 584800 20568 0 FreeSans 1400 0 0 0 io_in_3v3[4]
+port 102 nsew
+flabel metal3 s 583520 46914 584800 47026 0 FreeSans 1400 0 0 0 io_in_3v3[5]
+port 103 nsew
+flabel metal3 s 583520 91572 584800 91684 0 FreeSans 1400 0 0 0 io_in_3v3[6]
+port 104 nsew
+flabel metal3 s 583520 271594 584800 271706 0 FreeSans 1400 0 0 0 io_in_3v3[7]
+port 105 nsew
+flabel metal3 s 583520 316016 584800 316128 0 FreeSans 1400 0 0 0 io_in_3v3[8]
+port 106 nsew
+flabel metal3 s 583520 361238 584800 361350 0 FreeSans 1400 0 0 0 io_in_3v3[9]
+port 107 nsew
+flabel metal3 s 583520 5090 584800 5202 0 FreeSans 1400 0 0 0 io_oeb[0]
+port 108 nsew
+flabel metal3 s 583520 411206 584800 411318 0 FreeSans 1400 0 0 0 io_oeb[10]
+port 109 nsew
+flabel metal3 s 583520 455628 584800 455740 0 FreeSans 1400 0 0 0 io_oeb[11]
+port 110 nsew
+flabel metal3 s 583520 500050 584800 500162 0 FreeSans 1400 0 0 0 io_oeb[12]
+port 111 nsew
+flabel metal3 s 583520 589472 584800 589584 0 FreeSans 1400 0 0 0 io_oeb[13]
+port 112 nsew
+flabel metal3 s -800 505620 480 505732 0 FreeSans 1400 0 0 0 io_oeb[14]
+port 113 nsew
+flabel metal3 s -800 462398 480 462510 0 FreeSans 1400 0 0 0 io_oeb[15]
+port 114 nsew
+flabel metal3 s -800 419176 480 419288 0 FreeSans 1400 0 0 0 io_oeb[16]
+port 115 nsew
+flabel metal3 s -800 375954 480 376066 0 FreeSans 1400 0 0 0 io_oeb[17]
+port 116 nsew
+flabel metal3 s -800 332732 480 332844 0 FreeSans 1400 0 0 0 io_oeb[18]
+port 117 nsew
+flabel metal3 s -800 289510 480 289622 0 FreeSans 1400 0 0 0 io_oeb[19]
+port 118 nsew
+flabel metal3 s 583520 9818 584800 9930 0 FreeSans 1400 0 0 0 io_oeb[1]
+port 119 nsew
+flabel metal3 s -800 246488 480 246600 0 FreeSans 1400 0 0 0 io_oeb[20]
+port 120 nsew
+flabel metal3 s -800 118866 480 118978 0 FreeSans 1400 0 0 0 io_oeb[21]
+port 121 nsew
+flabel metal3 s -800 75644 480 75756 0 FreeSans 1400 0 0 0 io_oeb[22]
+port 122 nsew
+flabel metal3 s -800 32422 480 32534 0 FreeSans 1400 0 0 0 io_oeb[23]
+port 123 nsew
+flabel metal3 s -800 11000 480 11112 0 FreeSans 1400 0 0 0 io_oeb[24]
+port 124 nsew
+flabel metal3 s -800 6272 480 6384 0 FreeSans 1400 0 0 0 io_oeb[25]
+port 125 nsew
+flabel metal3 s -800 1544 480 1656 0 FreeSans 1400 0 0 0 io_oeb[26]
+port 126 nsew
+flabel metal3 s 583520 14546 584800 14658 0 FreeSans 1400 0 0 0 io_oeb[2]
+port 127 nsew
+flabel metal3 s 583520 19274 584800 19386 0 FreeSans 1400 0 0 0 io_oeb[3]
+port 128 nsew
+flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1400 0 0 0 io_oeb[4]
+port 129 nsew
+flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1400 0 0 0 io_oeb[5]
+port 130 nsew
+flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1400 0 0 0 io_oeb[6]
+port 131 nsew
+flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1400 0 0 0 io_oeb[7]
+port 132 nsew
+flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1400 0 0 0 io_oeb[8]
+port 133 nsew
+flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1400 0 0 0 io_oeb[9]
+port 134 nsew
+flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1400 0 0 0 io_out[0]
+port 135 nsew
+flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1400 0 0 0 io_out[10]
+port 136 nsew
+flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1400 0 0 0 io_out[11]
+port 137 nsew
+flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1400 0 0 0 io_out[12]
+port 138 nsew
+flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1400 0 0 0 io_out[13]
+port 139 nsew
+flabel metal3 s -800 506802 480 506914 0 FreeSans 1400 0 0 0 io_out[14]
+port 140 nsew
+flabel metal3 s -800 463580 480 463692 0 FreeSans 1400 0 0 0 io_out[15]
+port 141 nsew
+flabel metal3 s -800 420358 480 420470 0 FreeSans 1400 0 0 0 io_out[16]
+port 142 nsew
+flabel metal3 s -800 377136 480 377248 0 FreeSans 1400 0 0 0 io_out[17]
+port 143 nsew
+flabel metal3 s -800 333914 480 334026 0 FreeSans 1400 0 0 0 io_out[18]
+port 144 nsew
+flabel metal3 s -800 290692 480 290804 0 FreeSans 1400 0 0 0 io_out[19]
+port 145 nsew
+flabel metal3 s 583520 8636 584800 8748 0 FreeSans 1400 0 0 0 io_out[1]
+port 146 nsew
+flabel metal3 s -800 247670 480 247782 0 FreeSans 1400 0 0 0 io_out[20]
+port 147 nsew
+flabel metal3 s -800 120048 480 120160 0 FreeSans 1400 0 0 0 io_out[21]
+port 148 nsew
+flabel metal3 s -800 76826 480 76938 0 FreeSans 1400 0 0 0 io_out[22]
+port 149 nsew
+flabel metal3 s -800 33604 480 33716 0 FreeSans 1400 0 0 0 io_out[23]
+port 150 nsew
+flabel metal3 s -800 12182 480 12294 0 FreeSans 1400 0 0 0 io_out[24]
+port 151 nsew
+flabel metal3 s -800 7454 480 7566 0 FreeSans 1400 0 0 0 io_out[25]
+port 152 nsew
+flabel metal3 s -800 2726 480 2838 0 FreeSans 1400 0 0 0 io_out[26]
+port 153 nsew
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1400 0 0 0 io_out[2]
+port 154 nsew
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1400 0 0 0 io_out[3]
+port 155 nsew
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1400 0 0 0 io_out[4]
+port 156 nsew
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1400 0 0 0 io_out[5]
+port 157 nsew
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1400 0 0 0 io_out[6]
+port 158 nsew
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1400 0 0 0 io_out[7]
+port 159 nsew
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1400 0 0 0 io_out[8]
+port 160 nsew
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1400 0 0 0 io_out[9]
+port 161 nsew
+flabel metal2 s 125816 -800 125928 480 0 FreeSans 1400 90 0 0 la_data_in[0]
+port 162 nsew
+flabel metal2 s 480416 -800 480528 480 0 FreeSans 1400 90 0 0 la_data_in[100]
+port 163 nsew
+flabel metal2 s 483962 -800 484074 480 0 FreeSans 1400 90 0 0 la_data_in[101]
+port 164 nsew
+flabel metal2 s 487508 -800 487620 480 0 FreeSans 1400 90 0 0 la_data_in[102]
+port 165 nsew
+flabel metal2 s 491054 -800 491166 480 0 FreeSans 1400 90 0 0 la_data_in[103]
+port 166 nsew
+flabel metal2 s 494600 -800 494712 480 0 FreeSans 1400 90 0 0 la_data_in[104]
+port 167 nsew
+flabel metal2 s 498146 -800 498258 480 0 FreeSans 1400 90 0 0 la_data_in[105]
+port 168 nsew
+flabel metal2 s 501692 -800 501804 480 0 FreeSans 1400 90 0 0 la_data_in[106]
+port 169 nsew
+flabel metal2 s 505238 -800 505350 480 0 FreeSans 1400 90 0 0 la_data_in[107]
+port 170 nsew
+flabel metal2 s 508784 -800 508896 480 0 FreeSans 1400 90 0 0 la_data_in[108]
+port 171 nsew
+flabel metal2 s 512330 -800 512442 480 0 FreeSans 1400 90 0 0 la_data_in[109]
+port 172 nsew
+flabel metal2 s 161276 -800 161388 480 0 FreeSans 1400 90 0 0 la_data_in[10]
+port 173 nsew
+flabel metal2 s 515876 -800 515988 480 0 FreeSans 1400 90 0 0 la_data_in[110]
+port 174 nsew
+flabel metal2 s 519422 -800 519534 480 0 FreeSans 1400 90 0 0 la_data_in[111]
+port 175 nsew
+flabel metal2 s 522968 -800 523080 480 0 FreeSans 1400 90 0 0 la_data_in[112]
+port 176 nsew
+flabel metal2 s 526514 -800 526626 480 0 FreeSans 1400 90 0 0 la_data_in[113]
+port 177 nsew
+flabel metal2 s 530060 -800 530172 480 0 FreeSans 1400 90 0 0 la_data_in[114]
+port 178 nsew
+flabel metal2 s 533606 -800 533718 480 0 FreeSans 1400 90 0 0 la_data_in[115]
+port 179 nsew
+flabel metal2 s 537152 -800 537264 480 0 FreeSans 1400 90 0 0 la_data_in[116]
+port 180 nsew
+flabel metal2 s 540698 -800 540810 480 0 FreeSans 1400 90 0 0 la_data_in[117]
+port 181 nsew
+flabel metal2 s 544244 -800 544356 480 0 FreeSans 1400 90 0 0 la_data_in[118]
+port 182 nsew
+flabel metal2 s 547790 -800 547902 480 0 FreeSans 1400 90 0 0 la_data_in[119]
+port 183 nsew
+flabel metal2 s 164822 -800 164934 480 0 FreeSans 1400 90 0 0 la_data_in[11]
+port 184 nsew
+flabel metal2 s 551336 -800 551448 480 0 FreeSans 1400 90 0 0 la_data_in[120]
+port 185 nsew
+flabel metal2 s 554882 -800 554994 480 0 FreeSans 1400 90 0 0 la_data_in[121]
+port 186 nsew
+flabel metal2 s 558428 -800 558540 480 0 FreeSans 1400 90 0 0 la_data_in[122]
+port 187 nsew
+flabel metal2 s 561974 -800 562086 480 0 FreeSans 1400 90 0 0 la_data_in[123]
+port 188 nsew
+flabel metal2 s 565520 -800 565632 480 0 FreeSans 1400 90 0 0 la_data_in[124]
+port 189 nsew
+flabel metal2 s 569066 -800 569178 480 0 FreeSans 1400 90 0 0 la_data_in[125]
+port 190 nsew
+flabel metal2 s 572612 -800 572724 480 0 FreeSans 1400 90 0 0 la_data_in[126]
+port 191 nsew
+flabel metal2 s 576158 -800 576270 480 0 FreeSans 1400 90 0 0 la_data_in[127]
+port 192 nsew
+flabel metal2 s 168368 -800 168480 480 0 FreeSans 1400 90 0 0 la_data_in[12]
+port 193 nsew
+flabel metal2 s 171914 -800 172026 480 0 FreeSans 1400 90 0 0 la_data_in[13]
+port 194 nsew
+flabel metal2 s 175460 -800 175572 480 0 FreeSans 1400 90 0 0 la_data_in[14]
+port 195 nsew
+flabel metal2 s 179006 -800 179118 480 0 FreeSans 1400 90 0 0 la_data_in[15]
+port 196 nsew
+flabel metal2 s 182552 -800 182664 480 0 FreeSans 1400 90 0 0 la_data_in[16]
+port 197 nsew
+flabel metal2 s 186098 -800 186210 480 0 FreeSans 1400 90 0 0 la_data_in[17]
+port 198 nsew
+flabel metal2 s 189644 -800 189756 480 0 FreeSans 1400 90 0 0 la_data_in[18]
+port 199 nsew
+flabel metal2 s 193190 -800 193302 480 0 FreeSans 1400 90 0 0 la_data_in[19]
+port 200 nsew
+flabel metal2 s 129362 -800 129474 480 0 FreeSans 1400 90 0 0 la_data_in[1]
+port 201 nsew
+flabel metal2 s 196736 -800 196848 480 0 FreeSans 1400 90 0 0 la_data_in[20]
+port 202 nsew
+flabel metal2 s 200282 -800 200394 480 0 FreeSans 1400 90 0 0 la_data_in[21]
+port 203 nsew
+flabel metal2 s 203828 -800 203940 480 0 FreeSans 1400 90 0 0 la_data_in[22]
+port 204 nsew
+flabel metal2 s 207374 -800 207486 480 0 FreeSans 1400 90 0 0 la_data_in[23]
+port 205 nsew
+flabel metal2 s 210920 -800 211032 480 0 FreeSans 1400 90 0 0 la_data_in[24]
+port 206 nsew
+flabel metal2 s 214466 -800 214578 480 0 FreeSans 1400 90 0 0 la_data_in[25]
+port 207 nsew
+flabel metal2 s 218012 -800 218124 480 0 FreeSans 1400 90 0 0 la_data_in[26]
+port 208 nsew
+flabel metal2 s 221558 -800 221670 480 0 FreeSans 1400 90 0 0 la_data_in[27]
+port 209 nsew
+flabel metal2 s 225104 -800 225216 480 0 FreeSans 1400 90 0 0 la_data_in[28]
+port 210 nsew
+flabel metal2 s 228650 -800 228762 480 0 FreeSans 1400 90 0 0 la_data_in[29]
+port 211 nsew
+flabel metal2 s 132908 -800 133020 480 0 FreeSans 1400 90 0 0 la_data_in[2]
+port 212 nsew
+flabel metal2 s 232196 -800 232308 480 0 FreeSans 1400 90 0 0 la_data_in[30]
+port 213 nsew
+flabel metal2 s 235742 -800 235854 480 0 FreeSans 1400 90 0 0 la_data_in[31]
+port 214 nsew
+flabel metal2 s 239288 -800 239400 480 0 FreeSans 1400 90 0 0 la_data_in[32]
+port 215 nsew
+flabel metal2 s 242834 -800 242946 480 0 FreeSans 1400 90 0 0 la_data_in[33]
+port 216 nsew
+flabel metal2 s 246380 -800 246492 480 0 FreeSans 1400 90 0 0 la_data_in[34]
+port 217 nsew
+flabel metal2 s 249926 -800 250038 480 0 FreeSans 1400 90 0 0 la_data_in[35]
+port 218 nsew
+flabel metal2 s 253472 -800 253584 480 0 FreeSans 1400 90 0 0 la_data_in[36]
+port 219 nsew
+flabel metal2 s 257018 -800 257130 480 0 FreeSans 1400 90 0 0 la_data_in[37]
+port 220 nsew
+flabel metal2 s 260564 -800 260676 480 0 FreeSans 1400 90 0 0 la_data_in[38]
+port 221 nsew
+flabel metal2 s 264110 -800 264222 480 0 FreeSans 1400 90 0 0 la_data_in[39]
+port 222 nsew
+flabel metal2 s 136454 -800 136566 480 0 FreeSans 1400 90 0 0 la_data_in[3]
+port 223 nsew
+flabel metal2 s 267656 -800 267768 480 0 FreeSans 1400 90 0 0 la_data_in[40]
+port 224 nsew
+flabel metal2 s 271202 -800 271314 480 0 FreeSans 1400 90 0 0 la_data_in[41]
+port 225 nsew
+flabel metal2 s 274748 -800 274860 480 0 FreeSans 1400 90 0 0 la_data_in[42]
+port 226 nsew
+flabel metal2 s 278294 -800 278406 480 0 FreeSans 1400 90 0 0 la_data_in[43]
+port 227 nsew
+flabel metal2 s 281840 -800 281952 480 0 FreeSans 1400 90 0 0 la_data_in[44]
+port 228 nsew
+flabel metal2 s 285386 -800 285498 480 0 FreeSans 1400 90 0 0 la_data_in[45]
+port 229 nsew
+flabel metal2 s 288932 -800 289044 480 0 FreeSans 1400 90 0 0 la_data_in[46]
+port 230 nsew
+flabel metal2 s 292478 -800 292590 480 0 FreeSans 1400 90 0 0 la_data_in[47]
+port 231 nsew
+flabel metal2 s 296024 -800 296136 480 0 FreeSans 1400 90 0 0 la_data_in[48]
+port 232 nsew
+flabel metal2 s 299570 -800 299682 480 0 FreeSans 1400 90 0 0 la_data_in[49]
+port 233 nsew
+flabel metal2 s 140000 -800 140112 480 0 FreeSans 1400 90 0 0 la_data_in[4]
+port 234 nsew
+flabel metal2 s 303116 -800 303228 480 0 FreeSans 1400 90 0 0 la_data_in[50]
+port 235 nsew
+flabel metal2 s 306662 -800 306774 480 0 FreeSans 1400 90 0 0 la_data_in[51]
+port 236 nsew
+flabel metal2 s 310208 -800 310320 480 0 FreeSans 1400 90 0 0 la_data_in[52]
+port 237 nsew
+flabel metal2 s 313754 -800 313866 480 0 FreeSans 1400 90 0 0 la_data_in[53]
+port 238 nsew
+flabel metal2 s 317300 -800 317412 480 0 FreeSans 1400 90 0 0 la_data_in[54]
+port 239 nsew
+flabel metal2 s 320846 -800 320958 480 0 FreeSans 1400 90 0 0 la_data_in[55]
+port 240 nsew
+flabel metal2 s 324392 -800 324504 480 0 FreeSans 1400 90 0 0 la_data_in[56]
+port 241 nsew
+flabel metal2 s 327938 -800 328050 480 0 FreeSans 1400 90 0 0 la_data_in[57]
+port 242 nsew
+flabel metal2 s 331484 -800 331596 480 0 FreeSans 1400 90 0 0 la_data_in[58]
+port 243 nsew
+flabel metal2 s 335030 -800 335142 480 0 FreeSans 1400 90 0 0 la_data_in[59]
+port 244 nsew
+flabel metal2 s 143546 -800 143658 480 0 FreeSans 1400 90 0 0 la_data_in[5]
+port 245 nsew
+flabel metal2 s 338576 -800 338688 480 0 FreeSans 1400 90 0 0 la_data_in[60]
+port 246 nsew
+flabel metal2 s 342122 -800 342234 480 0 FreeSans 1400 90 0 0 la_data_in[61]
+port 247 nsew
+flabel metal2 s 345668 -800 345780 480 0 FreeSans 1400 90 0 0 la_data_in[62]
+port 248 nsew
+flabel metal2 s 349214 -800 349326 480 0 FreeSans 1400 90 0 0 la_data_in[63]
+port 249 nsew
+flabel metal2 s 352760 -800 352872 480 0 FreeSans 1400 90 0 0 la_data_in[64]
+port 250 nsew
+flabel metal2 s 356306 -800 356418 480 0 FreeSans 1400 90 0 0 la_data_in[65]
+port 251 nsew
+flabel metal2 s 359852 -800 359964 480 0 FreeSans 1400 90 0 0 la_data_in[66]
+port 252 nsew
+flabel metal2 s 363398 -800 363510 480 0 FreeSans 1400 90 0 0 la_data_in[67]
+port 253 nsew
+flabel metal2 s 366944 -800 367056 480 0 FreeSans 1400 90 0 0 la_data_in[68]
+port 254 nsew
+flabel metal2 s 370490 -800 370602 480 0 FreeSans 1400 90 0 0 la_data_in[69]
+port 255 nsew
+flabel metal2 s 147092 -800 147204 480 0 FreeSans 1400 90 0 0 la_data_in[6]
+port 256 nsew
+flabel metal2 s 374036 -800 374148 480 0 FreeSans 1400 90 0 0 la_data_in[70]
+port 257 nsew
+flabel metal2 s 377582 -800 377694 480 0 FreeSans 1400 90 0 0 la_data_in[71]
+port 258 nsew
+flabel metal2 s 381128 -800 381240 480 0 FreeSans 1400 90 0 0 la_data_in[72]
+port 259 nsew
+flabel metal2 s 384674 -800 384786 480 0 FreeSans 1400 90 0 0 la_data_in[73]
+port 260 nsew
+flabel metal2 s 388220 -800 388332 480 0 FreeSans 1400 90 0 0 la_data_in[74]
+port 261 nsew
+flabel metal2 s 391766 -800 391878 480 0 FreeSans 1400 90 0 0 la_data_in[75]
+port 262 nsew
+flabel metal2 s 395312 -800 395424 480 0 FreeSans 1400 90 0 0 la_data_in[76]
+port 263 nsew
+flabel metal2 s 398858 -800 398970 480 0 FreeSans 1400 90 0 0 la_data_in[77]
+port 264 nsew
+flabel metal2 s 402404 -800 402516 480 0 FreeSans 1400 90 0 0 la_data_in[78]
+port 265 nsew
+flabel metal2 s 405950 -800 406062 480 0 FreeSans 1400 90 0 0 la_data_in[79]
+port 266 nsew
+flabel metal2 s 150638 -800 150750 480 0 FreeSans 1400 90 0 0 la_data_in[7]
+port 267 nsew
+flabel metal2 s 409496 -800 409608 480 0 FreeSans 1400 90 0 0 la_data_in[80]
+port 268 nsew
+flabel metal2 s 413042 -800 413154 480 0 FreeSans 1400 90 0 0 la_data_in[81]
+port 269 nsew
+flabel metal2 s 416588 -800 416700 480 0 FreeSans 1400 90 0 0 la_data_in[82]
+port 270 nsew
+flabel metal2 s 420134 -800 420246 480 0 FreeSans 1400 90 0 0 la_data_in[83]
+port 271 nsew
+flabel metal2 s 423680 -800 423792 480 0 FreeSans 1400 90 0 0 la_data_in[84]
+port 272 nsew
+flabel metal2 s 427226 -800 427338 480 0 FreeSans 1400 90 0 0 la_data_in[85]
+port 273 nsew
+flabel metal2 s 430772 -800 430884 480 0 FreeSans 1400 90 0 0 la_data_in[86]
+port 274 nsew
+flabel metal2 s 434318 -800 434430 480 0 FreeSans 1400 90 0 0 la_data_in[87]
+port 275 nsew
+flabel metal2 s 437864 -800 437976 480 0 FreeSans 1400 90 0 0 la_data_in[88]
+port 276 nsew
+flabel metal2 s 441410 -800 441522 480 0 FreeSans 1400 90 0 0 la_data_in[89]
+port 277 nsew
+flabel metal2 s 154184 -800 154296 480 0 FreeSans 1400 90 0 0 la_data_in[8]
+port 278 nsew
+flabel metal2 s 444956 -800 445068 480 0 FreeSans 1400 90 0 0 la_data_in[90]
+port 279 nsew
+flabel metal2 s 448502 -800 448614 480 0 FreeSans 1400 90 0 0 la_data_in[91]
+port 280 nsew
+flabel metal2 s 452048 -800 452160 480 0 FreeSans 1400 90 0 0 la_data_in[92]
+port 281 nsew
+flabel metal2 s 455594 -800 455706 480 0 FreeSans 1400 90 0 0 la_data_in[93]
+port 282 nsew
+flabel metal2 s 459140 -800 459252 480 0 FreeSans 1400 90 0 0 la_data_in[94]
+port 283 nsew
+flabel metal2 s 462686 -800 462798 480 0 FreeSans 1400 90 0 0 la_data_in[95]
+port 284 nsew
+flabel metal2 s 466232 -800 466344 480 0 FreeSans 1400 90 0 0 la_data_in[96]
+port 285 nsew
+flabel metal2 s 469778 -800 469890 480 0 FreeSans 1400 90 0 0 la_data_in[97]
+port 286 nsew
+flabel metal2 s 473324 -800 473436 480 0 FreeSans 1400 90 0 0 la_data_in[98]
+port 287 nsew
+flabel metal2 s 476870 -800 476982 480 0 FreeSans 1400 90 0 0 la_data_in[99]
+port 288 nsew
+flabel metal2 s 157730 -800 157842 480 0 FreeSans 1400 90 0 0 la_data_in[9]
+port 289 nsew
+flabel metal2 s 126998 -800 127110 480 0 FreeSans 1400 90 0 0 la_data_out[0]
+port 290 nsew
+flabel metal2 s 481598 -800 481710 480 0 FreeSans 1400 90 0 0 la_data_out[100]
+port 291 nsew
+flabel metal2 s 485144 -800 485256 480 0 FreeSans 1400 90 0 0 la_data_out[101]
+port 292 nsew
+flabel metal2 s 488690 -800 488802 480 0 FreeSans 1400 90 0 0 la_data_out[102]
+port 293 nsew
+flabel metal2 s 492236 -800 492348 480 0 FreeSans 1400 90 0 0 la_data_out[103]
+port 294 nsew
+flabel metal2 s 495782 -800 495894 480 0 FreeSans 1400 90 0 0 la_data_out[104]
+port 295 nsew
+flabel metal2 s 499328 -800 499440 480 0 FreeSans 1400 90 0 0 la_data_out[105]
+port 296 nsew
+flabel metal2 s 502874 -800 502986 480 0 FreeSans 1400 90 0 0 la_data_out[106]
+port 297 nsew
+flabel metal2 s 506420 -800 506532 480 0 FreeSans 1400 90 0 0 la_data_out[107]
+port 298 nsew
+flabel metal2 s 509966 -800 510078 480 0 FreeSans 1400 90 0 0 la_data_out[108]
+port 299 nsew
+flabel metal2 s 513512 -800 513624 480 0 FreeSans 1400 90 0 0 la_data_out[109]
+port 300 nsew
+flabel metal2 s 162458 -800 162570 480 0 FreeSans 1400 90 0 0 la_data_out[10]
+port 301 nsew
+flabel metal2 s 517058 -800 517170 480 0 FreeSans 1400 90 0 0 la_data_out[110]
+port 302 nsew
+flabel metal2 s 520604 -800 520716 480 0 FreeSans 1400 90 0 0 la_data_out[111]
+port 303 nsew
+flabel metal2 s 524150 -800 524262 480 0 FreeSans 1400 90 0 0 la_data_out[112]
+port 304 nsew
+flabel metal2 s 527696 -800 527808 480 0 FreeSans 1400 90 0 0 la_data_out[113]
+port 305 nsew
+flabel metal2 s 531242 -800 531354 480 0 FreeSans 1400 90 0 0 la_data_out[114]
+port 306 nsew
+flabel metal2 s 534788 -800 534900 480 0 FreeSans 1400 90 0 0 la_data_out[115]
+port 307 nsew
+flabel metal2 s 538334 -800 538446 480 0 FreeSans 1400 90 0 0 la_data_out[116]
+port 308 nsew
+flabel metal2 s 541880 -800 541992 480 0 FreeSans 1400 90 0 0 la_data_out[117]
+port 309 nsew
+flabel metal2 s 545426 -800 545538 480 0 FreeSans 1400 90 0 0 la_data_out[118]
+port 310 nsew
+flabel metal2 s 548972 -800 549084 480 0 FreeSans 1400 90 0 0 la_data_out[119]
+port 311 nsew
+flabel metal2 s 166004 -800 166116 480 0 FreeSans 1400 90 0 0 la_data_out[11]
+port 312 nsew
+flabel metal2 s 552518 -800 552630 480 0 FreeSans 1400 90 0 0 la_data_out[120]
+port 313 nsew
+flabel metal2 s 556064 -800 556176 480 0 FreeSans 1400 90 0 0 la_data_out[121]
+port 314 nsew
+flabel metal2 s 559610 -800 559722 480 0 FreeSans 1400 90 0 0 la_data_out[122]
+port 315 nsew
+flabel metal2 s 563156 -800 563268 480 0 FreeSans 1400 90 0 0 la_data_out[123]
+port 316 nsew
+flabel metal2 s 566702 -800 566814 480 0 FreeSans 1400 90 0 0 la_data_out[124]
+port 317 nsew
+flabel metal2 s 570248 -800 570360 480 0 FreeSans 1400 90 0 0 la_data_out[125]
+port 318 nsew
+flabel metal2 s 573794 -800 573906 480 0 FreeSans 1400 90 0 0 la_data_out[126]
+port 319 nsew
+flabel metal2 s 577340 -800 577452 480 0 FreeSans 1400 90 0 0 la_data_out[127]
+port 320 nsew
+flabel metal2 s 169550 -800 169662 480 0 FreeSans 1400 90 0 0 la_data_out[12]
+port 321 nsew
+flabel metal2 s 173096 -800 173208 480 0 FreeSans 1400 90 0 0 la_data_out[13]
+port 322 nsew
+flabel metal2 s 176642 -800 176754 480 0 FreeSans 1400 90 0 0 la_data_out[14]
+port 323 nsew
+flabel metal2 s 180188 -800 180300 480 0 FreeSans 1400 90 0 0 la_data_out[15]
+port 324 nsew
+flabel metal2 s 183734 -800 183846 480 0 FreeSans 1400 90 0 0 la_data_out[16]
+port 325 nsew
+flabel metal2 s 187280 -800 187392 480 0 FreeSans 1400 90 0 0 la_data_out[17]
+port 326 nsew
+flabel metal2 s 190826 -800 190938 480 0 FreeSans 1400 90 0 0 la_data_out[18]
+port 327 nsew
+flabel metal2 s 194372 -800 194484 480 0 FreeSans 1400 90 0 0 la_data_out[19]
+port 328 nsew
+flabel metal2 s 130544 -800 130656 480 0 FreeSans 1400 90 0 0 la_data_out[1]
+port 329 nsew
+flabel metal2 s 197918 -800 198030 480 0 FreeSans 1400 90 0 0 la_data_out[20]
+port 330 nsew
+flabel metal2 s 201464 -800 201576 480 0 FreeSans 1400 90 0 0 la_data_out[21]
+port 331 nsew
+flabel metal2 s 205010 -800 205122 480 0 FreeSans 1400 90 0 0 la_data_out[22]
+port 332 nsew
+flabel metal2 s 208556 -800 208668 480 0 FreeSans 1400 90 0 0 la_data_out[23]
+port 333 nsew
+flabel metal2 s 212102 -800 212214 480 0 FreeSans 1400 90 0 0 la_data_out[24]
+port 334 nsew
+flabel metal2 s 215648 -800 215760 480 0 FreeSans 1400 90 0 0 la_data_out[25]
+port 335 nsew
+flabel metal2 s 219194 -800 219306 480 0 FreeSans 1400 90 0 0 la_data_out[26]
+port 336 nsew
+flabel metal2 s 222740 -800 222852 480 0 FreeSans 1400 90 0 0 la_data_out[27]
+port 337 nsew
+flabel metal2 s 226286 -800 226398 480 0 FreeSans 1400 90 0 0 la_data_out[28]
+port 338 nsew
+flabel metal2 s 229832 -800 229944 480 0 FreeSans 1400 90 0 0 la_data_out[29]
+port 339 nsew
+flabel metal2 s 134090 -800 134202 480 0 FreeSans 1400 90 0 0 la_data_out[2]
+port 340 nsew
+flabel metal2 s 233378 -800 233490 480 0 FreeSans 1400 90 0 0 la_data_out[30]
+port 341 nsew
+flabel metal2 s 236924 -800 237036 480 0 FreeSans 1400 90 0 0 la_data_out[31]
+port 342 nsew
+flabel metal2 s 240470 -800 240582 480 0 FreeSans 1400 90 0 0 la_data_out[32]
+port 343 nsew
+flabel metal2 s 244016 -800 244128 480 0 FreeSans 1400 90 0 0 la_data_out[33]
+port 344 nsew
+flabel metal2 s 247562 -800 247674 480 0 FreeSans 1400 90 0 0 la_data_out[34]
+port 345 nsew
+flabel metal2 s 251108 -800 251220 480 0 FreeSans 1400 90 0 0 la_data_out[35]
+port 346 nsew
+flabel metal2 s 254654 -800 254766 480 0 FreeSans 1400 90 0 0 la_data_out[36]
+port 347 nsew
+flabel metal2 s 258200 -800 258312 480 0 FreeSans 1400 90 0 0 la_data_out[37]
+port 348 nsew
+flabel metal2 s 261746 -800 261858 480 0 FreeSans 1400 90 0 0 la_data_out[38]
+port 349 nsew
+flabel metal2 s 265292 -800 265404 480 0 FreeSans 1400 90 0 0 la_data_out[39]
+port 350 nsew
+flabel metal2 s 137636 -800 137748 480 0 FreeSans 1400 90 0 0 la_data_out[3]
+port 351 nsew
+flabel metal2 s 268838 -800 268950 480 0 FreeSans 1400 90 0 0 la_data_out[40]
+port 352 nsew
+flabel metal2 s 272384 -800 272496 480 0 FreeSans 1400 90 0 0 la_data_out[41]
+port 353 nsew
+flabel metal2 s 275930 -800 276042 480 0 FreeSans 1400 90 0 0 la_data_out[42]
+port 354 nsew
+flabel metal2 s 279476 -800 279588 480 0 FreeSans 1400 90 0 0 la_data_out[43]
+port 355 nsew
+flabel metal2 s 283022 -800 283134 480 0 FreeSans 1400 90 0 0 la_data_out[44]
+port 356 nsew
+flabel metal2 s 286568 -800 286680 480 0 FreeSans 1400 90 0 0 la_data_out[45]
+port 357 nsew
+flabel metal2 s 290114 -800 290226 480 0 FreeSans 1400 90 0 0 la_data_out[46]
+port 358 nsew
+flabel metal2 s 293660 -800 293772 480 0 FreeSans 1400 90 0 0 la_data_out[47]
+port 359 nsew
+flabel metal2 s 297206 -800 297318 480 0 FreeSans 1400 90 0 0 la_data_out[48]
+port 360 nsew
+flabel metal2 s 300752 -800 300864 480 0 FreeSans 1400 90 0 0 la_data_out[49]
+port 361 nsew
+flabel metal2 s 141182 -800 141294 480 0 FreeSans 1400 90 0 0 la_data_out[4]
+port 362 nsew
+flabel metal2 s 304298 -800 304410 480 0 FreeSans 1400 90 0 0 la_data_out[50]
+port 363 nsew
+flabel metal2 s 307844 -800 307956 480 0 FreeSans 1400 90 0 0 la_data_out[51]
+port 364 nsew
+flabel metal2 s 311390 -800 311502 480 0 FreeSans 1400 90 0 0 la_data_out[52]
+port 365 nsew
+flabel metal2 s 314936 -800 315048 480 0 FreeSans 1400 90 0 0 la_data_out[53]
+port 366 nsew
+flabel metal2 s 318482 -800 318594 480 0 FreeSans 1400 90 0 0 la_data_out[54]
+port 367 nsew
+flabel metal2 s 322028 -800 322140 480 0 FreeSans 1400 90 0 0 la_data_out[55]
+port 368 nsew
+flabel metal2 s 325574 -800 325686 480 0 FreeSans 1400 90 0 0 la_data_out[56]
+port 369 nsew
+flabel metal2 s 329120 -800 329232 480 0 FreeSans 1400 90 0 0 la_data_out[57]
+port 370 nsew
+flabel metal2 s 332666 -800 332778 480 0 FreeSans 1400 90 0 0 la_data_out[58]
+port 371 nsew
+flabel metal2 s 336212 -800 336324 480 0 FreeSans 1400 90 0 0 la_data_out[59]
+port 372 nsew
+flabel metal2 s 144728 -800 144840 480 0 FreeSans 1400 90 0 0 la_data_out[5]
+port 373 nsew
+flabel metal2 s 339758 -800 339870 480 0 FreeSans 1400 90 0 0 la_data_out[60]
+port 374 nsew
+flabel metal2 s 343304 -800 343416 480 0 FreeSans 1400 90 0 0 la_data_out[61]
+port 375 nsew
+flabel metal2 s 346850 -800 346962 480 0 FreeSans 1400 90 0 0 la_data_out[62]
+port 376 nsew
+flabel metal2 s 350396 -800 350508 480 0 FreeSans 1400 90 0 0 la_data_out[63]
+port 377 nsew
+flabel metal2 s 353942 -800 354054 480 0 FreeSans 1400 90 0 0 la_data_out[64]
+port 378 nsew
+flabel metal2 s 357488 -800 357600 480 0 FreeSans 1400 90 0 0 la_data_out[65]
+port 379 nsew
+flabel metal2 s 361034 -800 361146 480 0 FreeSans 1400 90 0 0 la_data_out[66]
+port 380 nsew
+flabel metal2 s 364580 -800 364692 480 0 FreeSans 1400 90 0 0 la_data_out[67]
+port 381 nsew
+flabel metal2 s 368126 -800 368238 480 0 FreeSans 1400 90 0 0 la_data_out[68]
+port 382 nsew
+flabel metal2 s 371672 -800 371784 480 0 FreeSans 1400 90 0 0 la_data_out[69]
+port 383 nsew
+flabel metal2 s 148274 -800 148386 480 0 FreeSans 1400 90 0 0 la_data_out[6]
+port 384 nsew
+flabel metal2 s 375218 -800 375330 480 0 FreeSans 1400 90 0 0 la_data_out[70]
+port 385 nsew
+flabel metal2 s 378764 -800 378876 480 0 FreeSans 1400 90 0 0 la_data_out[71]
+port 386 nsew
+flabel metal2 s 382310 -800 382422 480 0 FreeSans 1400 90 0 0 la_data_out[72]
+port 387 nsew
+flabel metal2 s 385856 -800 385968 480 0 FreeSans 1400 90 0 0 la_data_out[73]
+port 388 nsew
+flabel metal2 s 389402 -800 389514 480 0 FreeSans 1400 90 0 0 la_data_out[74]
+port 389 nsew
+flabel metal2 s 392948 -800 393060 480 0 FreeSans 1400 90 0 0 la_data_out[75]
+port 390 nsew
+flabel metal2 s 396494 -800 396606 480 0 FreeSans 1400 90 0 0 la_data_out[76]
+port 391 nsew
+flabel metal2 s 400040 -800 400152 480 0 FreeSans 1400 90 0 0 la_data_out[77]
+port 392 nsew
+flabel metal2 s 403586 -800 403698 480 0 FreeSans 1400 90 0 0 la_data_out[78]
+port 393 nsew
+flabel metal2 s 407132 -800 407244 480 0 FreeSans 1400 90 0 0 la_data_out[79]
+port 394 nsew
+flabel metal2 s 151820 -800 151932 480 0 FreeSans 1400 90 0 0 la_data_out[7]
+port 395 nsew
+flabel metal2 s 410678 -800 410790 480 0 FreeSans 1400 90 0 0 la_data_out[80]
+port 396 nsew
+flabel metal2 s 414224 -800 414336 480 0 FreeSans 1400 90 0 0 la_data_out[81]
+port 397 nsew
+flabel metal2 s 417770 -800 417882 480 0 FreeSans 1400 90 0 0 la_data_out[82]
+port 398 nsew
+flabel metal2 s 421316 -800 421428 480 0 FreeSans 1400 90 0 0 la_data_out[83]
+port 399 nsew
+flabel metal2 s 424862 -800 424974 480 0 FreeSans 1400 90 0 0 la_data_out[84]
+port 400 nsew
+flabel metal2 s 428408 -800 428520 480 0 FreeSans 1400 90 0 0 la_data_out[85]
+port 401 nsew
+flabel metal2 s 431954 -800 432066 480 0 FreeSans 1400 90 0 0 la_data_out[86]
+port 402 nsew
+flabel metal2 s 435500 -800 435612 480 0 FreeSans 1400 90 0 0 la_data_out[87]
+port 403 nsew
+flabel metal2 s 439046 -800 439158 480 0 FreeSans 1400 90 0 0 la_data_out[88]
+port 404 nsew
+flabel metal2 s 442592 -800 442704 480 0 FreeSans 1400 90 0 0 la_data_out[89]
+port 405 nsew
+flabel metal2 s 155366 -800 155478 480 0 FreeSans 1400 90 0 0 la_data_out[8]
+port 406 nsew
+flabel metal2 s 446138 -800 446250 480 0 FreeSans 1400 90 0 0 la_data_out[90]
+port 407 nsew
+flabel metal2 s 449684 -800 449796 480 0 FreeSans 1400 90 0 0 la_data_out[91]
+port 408 nsew
+flabel metal2 s 453230 -800 453342 480 0 FreeSans 1400 90 0 0 la_data_out[92]
+port 409 nsew
+flabel metal2 s 456776 -800 456888 480 0 FreeSans 1400 90 0 0 la_data_out[93]
+port 410 nsew
+flabel metal2 s 460322 -800 460434 480 0 FreeSans 1400 90 0 0 la_data_out[94]
+port 411 nsew
+flabel metal2 s 463868 -800 463980 480 0 FreeSans 1400 90 0 0 la_data_out[95]
+port 412 nsew
+flabel metal2 s 467414 -800 467526 480 0 FreeSans 1400 90 0 0 la_data_out[96]
+port 413 nsew
+flabel metal2 s 470960 -800 471072 480 0 FreeSans 1400 90 0 0 la_data_out[97]
+port 414 nsew
+flabel metal2 s 474506 -800 474618 480 0 FreeSans 1400 90 0 0 la_data_out[98]
+port 415 nsew
+flabel metal2 s 478052 -800 478164 480 0 FreeSans 1400 90 0 0 la_data_out[99]
+port 416 nsew
+flabel metal2 s 158912 -800 159024 480 0 FreeSans 1400 90 0 0 la_data_out[9]
+port 417 nsew
+flabel metal2 s 128180 -800 128292 480 0 FreeSans 1400 90 0 0 la_oenb[0]
+port 418 nsew
+flabel metal2 s 482780 -800 482892 480 0 FreeSans 1400 90 0 0 la_oenb[100]
+port 419 nsew
+flabel metal2 s 486326 -800 486438 480 0 FreeSans 1400 90 0 0 la_oenb[101]
+port 420 nsew
+flabel metal2 s 489872 -800 489984 480 0 FreeSans 1400 90 0 0 la_oenb[102]
+port 421 nsew
+flabel metal2 s 493418 -800 493530 480 0 FreeSans 1400 90 0 0 la_oenb[103]
+port 422 nsew
+flabel metal2 s 496964 -800 497076 480 0 FreeSans 1400 90 0 0 la_oenb[104]
+port 423 nsew
+flabel metal2 s 500510 -800 500622 480 0 FreeSans 1400 90 0 0 la_oenb[105]
+port 424 nsew
+flabel metal2 s 504056 -800 504168 480 0 FreeSans 1400 90 0 0 la_oenb[106]
+port 425 nsew
+flabel metal2 s 507602 -800 507714 480 0 FreeSans 1400 90 0 0 la_oenb[107]
+port 426 nsew
+flabel metal2 s 511148 -800 511260 480 0 FreeSans 1400 90 0 0 la_oenb[108]
+port 427 nsew
+flabel metal2 s 514694 -800 514806 480 0 FreeSans 1400 90 0 0 la_oenb[109]
+port 428 nsew
+flabel metal2 s 163640 -800 163752 480 0 FreeSans 1400 90 0 0 la_oenb[10]
+port 429 nsew
+flabel metal2 s 518240 -800 518352 480 0 FreeSans 1400 90 0 0 la_oenb[110]
+port 430 nsew
+flabel metal2 s 521786 -800 521898 480 0 FreeSans 1400 90 0 0 la_oenb[111]
+port 431 nsew
+flabel metal2 s 525332 -800 525444 480 0 FreeSans 1400 90 0 0 la_oenb[112]
+port 432 nsew
+flabel metal2 s 528878 -800 528990 480 0 FreeSans 1400 90 0 0 la_oenb[113]
+port 433 nsew
+flabel metal2 s 532424 -800 532536 480 0 FreeSans 1400 90 0 0 la_oenb[114]
+port 434 nsew
+flabel metal2 s 535970 -800 536082 480 0 FreeSans 1400 90 0 0 la_oenb[115]
+port 435 nsew
+flabel metal2 s 539516 -800 539628 480 0 FreeSans 1400 90 0 0 la_oenb[116]
+port 436 nsew
+flabel metal2 s 543062 -800 543174 480 0 FreeSans 1400 90 0 0 la_oenb[117]
+port 437 nsew
+flabel metal2 s 546608 -800 546720 480 0 FreeSans 1400 90 0 0 la_oenb[118]
+port 438 nsew
+flabel metal2 s 550154 -800 550266 480 0 FreeSans 1400 90 0 0 la_oenb[119]
+port 439 nsew
+flabel metal2 s 167186 -800 167298 480 0 FreeSans 1400 90 0 0 la_oenb[11]
+port 440 nsew
+flabel metal2 s 553700 -800 553812 480 0 FreeSans 1400 90 0 0 la_oenb[120]
+port 441 nsew
+flabel metal2 s 557246 -800 557358 480 0 FreeSans 1400 90 0 0 la_oenb[121]
+port 442 nsew
+flabel metal2 s 560792 -800 560904 480 0 FreeSans 1400 90 0 0 la_oenb[122]
+port 443 nsew
+flabel metal2 s 564338 -800 564450 480 0 FreeSans 1400 90 0 0 la_oenb[123]
+port 444 nsew
+flabel metal2 s 567884 -800 567996 480 0 FreeSans 1400 90 0 0 la_oenb[124]
+port 445 nsew
+flabel metal2 s 571430 -800 571542 480 0 FreeSans 1400 90 0 0 la_oenb[125]
+port 446 nsew
+flabel metal2 s 574976 -800 575088 480 0 FreeSans 1400 90 0 0 la_oenb[126]
+port 447 nsew
+flabel metal2 s 578522 -800 578634 480 0 FreeSans 1400 90 0 0 la_oenb[127]
+port 448 nsew
+flabel metal2 s 170732 -800 170844 480 0 FreeSans 1400 90 0 0 la_oenb[12]
+port 449 nsew
+flabel metal2 s 174278 -800 174390 480 0 FreeSans 1400 90 0 0 la_oenb[13]
+port 450 nsew
+flabel metal2 s 177824 -800 177936 480 0 FreeSans 1400 90 0 0 la_oenb[14]
+port 451 nsew
+flabel metal2 s 181370 -800 181482 480 0 FreeSans 1400 90 0 0 la_oenb[15]
+port 452 nsew
+flabel metal2 s 184916 -800 185028 480 0 FreeSans 1400 90 0 0 la_oenb[16]
+port 453 nsew
+flabel metal2 s 188462 -800 188574 480 0 FreeSans 1400 90 0 0 la_oenb[17]
+port 454 nsew
+flabel metal2 s 192008 -800 192120 480 0 FreeSans 1400 90 0 0 la_oenb[18]
+port 455 nsew
+flabel metal2 s 195554 -800 195666 480 0 FreeSans 1400 90 0 0 la_oenb[19]
+port 456 nsew
+flabel metal2 s 131726 -800 131838 480 0 FreeSans 1400 90 0 0 la_oenb[1]
+port 457 nsew
+flabel metal2 s 199100 -800 199212 480 0 FreeSans 1400 90 0 0 la_oenb[20]
+port 458 nsew
+flabel metal2 s 202646 -800 202758 480 0 FreeSans 1400 90 0 0 la_oenb[21]
+port 459 nsew
+flabel metal2 s 206192 -800 206304 480 0 FreeSans 1400 90 0 0 la_oenb[22]
+port 460 nsew
+flabel metal2 s 209738 -800 209850 480 0 FreeSans 1400 90 0 0 la_oenb[23]
+port 461 nsew
+flabel metal2 s 213284 -800 213396 480 0 FreeSans 1400 90 0 0 la_oenb[24]
+port 462 nsew
+flabel metal2 s 216830 -800 216942 480 0 FreeSans 1400 90 0 0 la_oenb[25]
+port 463 nsew
+flabel metal2 s 220376 -800 220488 480 0 FreeSans 1400 90 0 0 la_oenb[26]
+port 464 nsew
+flabel metal2 s 223922 -800 224034 480 0 FreeSans 1400 90 0 0 la_oenb[27]
+port 465 nsew
+flabel metal2 s 227468 -800 227580 480 0 FreeSans 1400 90 0 0 la_oenb[28]
+port 466 nsew
+flabel metal2 s 231014 -800 231126 480 0 FreeSans 1400 90 0 0 la_oenb[29]
+port 467 nsew
+flabel metal2 s 135272 -800 135384 480 0 FreeSans 1400 90 0 0 la_oenb[2]
+port 468 nsew
+flabel metal2 s 234560 -800 234672 480 0 FreeSans 1400 90 0 0 la_oenb[30]
+port 469 nsew
+flabel metal2 s 238106 -800 238218 480 0 FreeSans 1400 90 0 0 la_oenb[31]
+port 470 nsew
+flabel metal2 s 241652 -800 241764 480 0 FreeSans 1400 90 0 0 la_oenb[32]
+port 471 nsew
+flabel metal2 s 245198 -800 245310 480 0 FreeSans 1400 90 0 0 la_oenb[33]
+port 472 nsew
+flabel metal2 s 248744 -800 248856 480 0 FreeSans 1400 90 0 0 la_oenb[34]
+port 473 nsew
+flabel metal2 s 252290 -800 252402 480 0 FreeSans 1400 90 0 0 la_oenb[35]
+port 474 nsew
+flabel metal2 s 255836 -800 255948 480 0 FreeSans 1400 90 0 0 la_oenb[36]
+port 475 nsew
+flabel metal2 s 259382 -800 259494 480 0 FreeSans 1400 90 0 0 la_oenb[37]
+port 476 nsew
+flabel metal2 s 262928 -800 263040 480 0 FreeSans 1400 90 0 0 la_oenb[38]
+port 477 nsew
+flabel metal2 s 266474 -800 266586 480 0 FreeSans 1400 90 0 0 la_oenb[39]
+port 478 nsew
+flabel metal2 s 138818 -800 138930 480 0 FreeSans 1400 90 0 0 la_oenb[3]
+port 479 nsew
+flabel metal2 s 270020 -800 270132 480 0 FreeSans 1400 90 0 0 la_oenb[40]
+port 480 nsew
+flabel metal2 s 273566 -800 273678 480 0 FreeSans 1400 90 0 0 la_oenb[41]
+port 481 nsew
+flabel metal2 s 277112 -800 277224 480 0 FreeSans 1400 90 0 0 la_oenb[42]
+port 482 nsew
+flabel metal2 s 280658 -800 280770 480 0 FreeSans 1400 90 0 0 la_oenb[43]
+port 483 nsew
+flabel metal2 s 284204 -800 284316 480 0 FreeSans 1400 90 0 0 la_oenb[44]
+port 484 nsew
+flabel metal2 s 287750 -800 287862 480 0 FreeSans 1400 90 0 0 la_oenb[45]
+port 485 nsew
+flabel metal2 s 291296 -800 291408 480 0 FreeSans 1400 90 0 0 la_oenb[46]
+port 486 nsew
+flabel metal2 s 294842 -800 294954 480 0 FreeSans 1400 90 0 0 la_oenb[47]
+port 487 nsew
+flabel metal2 s 298388 -800 298500 480 0 FreeSans 1400 90 0 0 la_oenb[48]
+port 488 nsew
+flabel metal2 s 301934 -800 302046 480 0 FreeSans 1400 90 0 0 la_oenb[49]
+port 489 nsew
+flabel metal2 s 142364 -800 142476 480 0 FreeSans 1400 90 0 0 la_oenb[4]
+port 490 nsew
+flabel metal2 s 305480 -800 305592 480 0 FreeSans 1400 90 0 0 la_oenb[50]
+port 491 nsew
+flabel metal2 s 309026 -800 309138 480 0 FreeSans 1400 90 0 0 la_oenb[51]
+port 492 nsew
+flabel metal2 s 312572 -800 312684 480 0 FreeSans 1400 90 0 0 la_oenb[52]
+port 493 nsew
+flabel metal2 s 316118 -800 316230 480 0 FreeSans 1400 90 0 0 la_oenb[53]
+port 494 nsew
+flabel metal2 s 319664 -800 319776 480 0 FreeSans 1400 90 0 0 la_oenb[54]
+port 495 nsew
+flabel metal2 s 323210 -800 323322 480 0 FreeSans 1400 90 0 0 la_oenb[55]
+port 496 nsew
+flabel metal2 s 326756 -800 326868 480 0 FreeSans 1400 90 0 0 la_oenb[56]
+port 497 nsew
+flabel metal2 s 330302 -800 330414 480 0 FreeSans 1400 90 0 0 la_oenb[57]
+port 498 nsew
+flabel metal2 s 333848 -800 333960 480 0 FreeSans 1400 90 0 0 la_oenb[58]
+port 499 nsew
+flabel metal2 s 337394 -800 337506 480 0 FreeSans 1400 90 0 0 la_oenb[59]
+port 500 nsew
+flabel metal2 s 145910 -800 146022 480 0 FreeSans 1400 90 0 0 la_oenb[5]
+port 501 nsew
+flabel metal2 s 340940 -800 341052 480 0 FreeSans 1400 90 0 0 la_oenb[60]
+port 502 nsew
+flabel metal2 s 344486 -800 344598 480 0 FreeSans 1400 90 0 0 la_oenb[61]
+port 503 nsew
+flabel metal2 s 348032 -800 348144 480 0 FreeSans 1400 90 0 0 la_oenb[62]
+port 504 nsew
+flabel metal2 s 351578 -800 351690 480 0 FreeSans 1400 90 0 0 la_oenb[63]
+port 505 nsew
+flabel metal2 s 355124 -800 355236 480 0 FreeSans 1400 90 0 0 la_oenb[64]
+port 506 nsew
+flabel metal2 s 358670 -800 358782 480 0 FreeSans 1400 90 0 0 la_oenb[65]
+port 507 nsew
+flabel metal2 s 362216 -800 362328 480 0 FreeSans 1400 90 0 0 la_oenb[66]
+port 508 nsew
+flabel metal2 s 365762 -800 365874 480 0 FreeSans 1400 90 0 0 la_oenb[67]
+port 509 nsew
+flabel metal2 s 369308 -800 369420 480 0 FreeSans 1400 90 0 0 la_oenb[68]
+port 510 nsew
+flabel metal2 s 372854 -800 372966 480 0 FreeSans 1400 90 0 0 la_oenb[69]
+port 511 nsew
+flabel metal2 s 149456 -800 149568 480 0 FreeSans 1400 90 0 0 la_oenb[6]
+port 512 nsew
+flabel metal2 s 376400 -800 376512 480 0 FreeSans 1400 90 0 0 la_oenb[70]
+port 513 nsew
+flabel metal2 s 379946 -800 380058 480 0 FreeSans 1400 90 0 0 la_oenb[71]
+port 514 nsew
+flabel metal2 s 383492 -800 383604 480 0 FreeSans 1400 90 0 0 la_oenb[72]
+port 515 nsew
+flabel metal2 s 387038 -800 387150 480 0 FreeSans 1400 90 0 0 la_oenb[73]
+port 516 nsew
+flabel metal2 s 390584 -800 390696 480 0 FreeSans 1400 90 0 0 la_oenb[74]
+port 517 nsew
+flabel metal2 s 394130 -800 394242 480 0 FreeSans 1400 90 0 0 la_oenb[75]
+port 518 nsew
+flabel metal2 s 397676 -800 397788 480 0 FreeSans 1400 90 0 0 la_oenb[76]
+port 519 nsew
+flabel metal2 s 401222 -800 401334 480 0 FreeSans 1400 90 0 0 la_oenb[77]
+port 520 nsew
+flabel metal2 s 404768 -800 404880 480 0 FreeSans 1400 90 0 0 la_oenb[78]
+port 521 nsew
+flabel metal2 s 408314 -800 408426 480 0 FreeSans 1400 90 0 0 la_oenb[79]
+port 522 nsew
+flabel metal2 s 153002 -800 153114 480 0 FreeSans 1400 90 0 0 la_oenb[7]
+port 523 nsew
+flabel metal2 s 411860 -800 411972 480 0 FreeSans 1400 90 0 0 la_oenb[80]
+port 524 nsew
+flabel metal2 s 415406 -800 415518 480 0 FreeSans 1400 90 0 0 la_oenb[81]
+port 525 nsew
+flabel metal2 s 418952 -800 419064 480 0 FreeSans 1400 90 0 0 la_oenb[82]
+port 526 nsew
+flabel metal2 s 422498 -800 422610 480 0 FreeSans 1400 90 0 0 la_oenb[83]
+port 527 nsew
+flabel metal2 s 426044 -800 426156 480 0 FreeSans 1400 90 0 0 la_oenb[84]
+port 528 nsew
+flabel metal2 s 429590 -800 429702 480 0 FreeSans 1400 90 0 0 la_oenb[85]
+port 529 nsew
+flabel metal2 s 433136 -800 433248 480 0 FreeSans 1400 90 0 0 la_oenb[86]
+port 530 nsew
+flabel metal2 s 436682 -800 436794 480 0 FreeSans 1400 90 0 0 la_oenb[87]
+port 531 nsew
+flabel metal2 s 440228 -800 440340 480 0 FreeSans 1400 90 0 0 la_oenb[88]
+port 532 nsew
+flabel metal2 s 443774 -800 443886 480 0 FreeSans 1400 90 0 0 la_oenb[89]
+port 533 nsew
+flabel metal2 s 156548 -800 156660 480 0 FreeSans 1400 90 0 0 la_oenb[8]
+port 534 nsew
+flabel metal2 s 447320 -800 447432 480 0 FreeSans 1400 90 0 0 la_oenb[90]
+port 535 nsew
+flabel metal2 s 450866 -800 450978 480 0 FreeSans 1400 90 0 0 la_oenb[91]
+port 536 nsew
+flabel metal2 s 454412 -800 454524 480 0 FreeSans 1400 90 0 0 la_oenb[92]
+port 537 nsew
+flabel metal2 s 457958 -800 458070 480 0 FreeSans 1400 90 0 0 la_oenb[93]
+port 538 nsew
+flabel metal2 s 461504 -800 461616 480 0 FreeSans 1400 90 0 0 la_oenb[94]
+port 539 nsew
+flabel metal2 s 465050 -800 465162 480 0 FreeSans 1400 90 0 0 la_oenb[95]
+port 540 nsew
+flabel metal2 s 468596 -800 468708 480 0 FreeSans 1400 90 0 0 la_oenb[96]
+port 541 nsew
+flabel metal2 s 472142 -800 472254 480 0 FreeSans 1400 90 0 0 la_oenb[97]
+port 542 nsew
+flabel metal2 s 475688 -800 475800 480 0 FreeSans 1400 90 0 0 la_oenb[98]
+port 543 nsew
+flabel metal2 s 479234 -800 479346 480 0 FreeSans 1400 90 0 0 la_oenb[99]
+port 544 nsew
+flabel metal2 s 160094 -800 160206 480 0 FreeSans 1400 90 0 0 la_oenb[9]
+port 545 nsew
+flabel metal2 s 579704 -800 579816 480 0 FreeSans 1400 90 0 0 user_clock2
+port 546 nsew
+flabel metal2 s 580886 -800 580998 480 0 FreeSans 1400 90 0 0 user_irq[0]
+port 547 nsew
+flabel metal2 s 582068 -800 582180 480 0 FreeSans 1400 90 0 0 user_irq[1]
+port 548 nsew
+flabel metal2 s 583250 -800 583362 480 0 FreeSans 1400 90 0 0 user_irq[2]
+port 549 nsew
+flabel metal3 s 582340 639784 584800 644584 0 FreeSans 1400 0 0 0 vccd1
+port 550 nsew
+flabel metal3 s 582340 629784 584800 634584 0 FreeSans 1400 0 0 0 vccd1
+port 550 nsew
+flabel metal3 s 0 643842 1660 648642 0 FreeSans 1400 0 0 0 vccd2
+port 551 nsew
+flabel metal3 s 0 633842 1660 638642 0 FreeSans 1400 0 0 0 vccd2
+port 551 nsew
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1400 0 0 0 vdda1
+port 552 nsew
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1400 0 0 0 vdda1
+port 552 nsew
+flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1400 0 0 0 vdda1
+port 552 nsew
+flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1400 0 0 0 vdda1
+port 552 nsew
+flabel metal3 s 0 204888 1660 209688 0 FreeSans 1400 0 0 0 vdda2
+port 553 nsew
+flabel metal3 s 0 214888 1660 219688 0 FreeSans 1400 0 0 0 vdda2
+port 553 nsew
+flabel metal3 s 520594 702340 525394 704800 0 FreeSans 2400 180 0 0 vssa1
+port 554 nsew
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 2400 180 0 0 vssa1
+port 554 nsew
+flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1400 0 0 0 vssa1
+port 554 nsew
+flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1400 0 0 0 vssa1
+port 554 nsew
+flabel metal3 s -800 559442 860 564242 0 FreeSans 1400 180 0 0 vssa2
+port 555 nsew
+flabel metal3 s 0 549442 1660 554242 0 FreeSans 1400 0 0 0 vssa2
+port 555 nsew
+flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1400 0 0 0 vssd1
+port 556 nsew
+flabel metal3 s 582340 181430 584800 186230 0 FreeSans 1400 0 0 0 vssd1
+port 556 nsew
+flabel metal3 s 0 172888 1660 177688 0 FreeSans 1400 0 0 0 vssd2
+port 557 nsew
+flabel metal3 s 0 162888 1660 167688 0 FreeSans 1400 0 0 0 vssd2
+port 557 nsew
+flabel metal2 s 524 -800 636 480 0 FreeSans 1400 90 0 0 wb_clk_i
+port 558 nsew
+flabel metal2 s 1706 -800 1818 480 0 FreeSans 1400 90 0 0 wb_rst_i
+port 559 nsew
+flabel metal2 s 2888 -800 3000 480 0 FreeSans 1400 90 0 0 wbs_ack_o
+port 560 nsew
+flabel metal2 s 7616 -800 7728 480 0 FreeSans 1400 90 0 0 wbs_adr_i[0]
+port 561 nsew
+flabel metal2 s 47804 -800 47916 480 0 FreeSans 1400 90 0 0 wbs_adr_i[10]
+port 562 nsew
+flabel metal2 s 51350 -800 51462 480 0 FreeSans 1400 90 0 0 wbs_adr_i[11]
+port 563 nsew
+flabel metal2 s 54896 -800 55008 480 0 FreeSans 1400 90 0 0 wbs_adr_i[12]
+port 564 nsew
+flabel metal2 s 58442 -800 58554 480 0 FreeSans 1400 90 0 0 wbs_adr_i[13]
+port 565 nsew
+flabel metal2 s 61988 -800 62100 480 0 FreeSans 1400 90 0 0 wbs_adr_i[14]
+port 566 nsew
+flabel metal2 s 65534 -800 65646 480 0 FreeSans 1400 90 0 0 wbs_adr_i[15]
+port 567 nsew
+flabel metal2 s 69080 -800 69192 480 0 FreeSans 1400 90 0 0 wbs_adr_i[16]
+port 568 nsew
+flabel metal2 s 72626 -800 72738 480 0 FreeSans 1400 90 0 0 wbs_adr_i[17]
+port 569 nsew
+flabel metal2 s 76172 -800 76284 480 0 FreeSans 1400 90 0 0 wbs_adr_i[18]
+port 570 nsew
+flabel metal2 s 79718 -800 79830 480 0 FreeSans 1400 90 0 0 wbs_adr_i[19]
+port 571 nsew
+flabel metal2 s 12344 -800 12456 480 0 FreeSans 1400 90 0 0 wbs_adr_i[1]
+port 572 nsew
+flabel metal2 s 83264 -800 83376 480 0 FreeSans 1400 90 0 0 wbs_adr_i[20]
+port 573 nsew
+flabel metal2 s 86810 -800 86922 480 0 FreeSans 1400 90 0 0 wbs_adr_i[21]
+port 574 nsew
+flabel metal2 s 90356 -800 90468 480 0 FreeSans 1400 90 0 0 wbs_adr_i[22]
+port 575 nsew
+flabel metal2 s 93902 -800 94014 480 0 FreeSans 1400 90 0 0 wbs_adr_i[23]
+port 576 nsew
+flabel metal2 s 97448 -800 97560 480 0 FreeSans 1400 90 0 0 wbs_adr_i[24]
+port 577 nsew
+flabel metal2 s 100994 -800 101106 480 0 FreeSans 1400 90 0 0 wbs_adr_i[25]
+port 578 nsew
+flabel metal2 s 104540 -800 104652 480 0 FreeSans 1400 90 0 0 wbs_adr_i[26]
+port 579 nsew
+flabel metal2 s 108086 -800 108198 480 0 FreeSans 1400 90 0 0 wbs_adr_i[27]
+port 580 nsew
+flabel metal2 s 111632 -800 111744 480 0 FreeSans 1400 90 0 0 wbs_adr_i[28]
+port 581 nsew
+flabel metal2 s 115178 -800 115290 480 0 FreeSans 1400 90 0 0 wbs_adr_i[29]
+port 582 nsew
+flabel metal2 s 17072 -800 17184 480 0 FreeSans 1400 90 0 0 wbs_adr_i[2]
+port 583 nsew
+flabel metal2 s 118724 -800 118836 480 0 FreeSans 1400 90 0 0 wbs_adr_i[30]
+port 584 nsew
+flabel metal2 s 122270 -800 122382 480 0 FreeSans 1400 90 0 0 wbs_adr_i[31]
+port 585 nsew
+flabel metal2 s 21800 -800 21912 480 0 FreeSans 1400 90 0 0 wbs_adr_i[3]
+port 586 nsew
+flabel metal2 s 26528 -800 26640 480 0 FreeSans 1400 90 0 0 wbs_adr_i[4]
+port 587 nsew
+flabel metal2 s 30074 -800 30186 480 0 FreeSans 1400 90 0 0 wbs_adr_i[5]
+port 588 nsew
+flabel metal2 s 33620 -800 33732 480 0 FreeSans 1400 90 0 0 wbs_adr_i[6]
+port 589 nsew
+flabel metal2 s 37166 -800 37278 480 0 FreeSans 1400 90 0 0 wbs_adr_i[7]
+port 590 nsew
+flabel metal2 s 40712 -800 40824 480 0 FreeSans 1400 90 0 0 wbs_adr_i[8]
+port 591 nsew
+flabel metal2 s 44258 -800 44370 480 0 FreeSans 1400 90 0 0 wbs_adr_i[9]
+port 592 nsew
+flabel metal2 s 4070 -800 4182 480 0 FreeSans 1400 90 0 0 wbs_cyc_i
+port 593 nsew
+flabel metal2 s 8798 -800 8910 480 0 FreeSans 1400 90 0 0 wbs_dat_i[0]
+port 594 nsew
+flabel metal2 s 48986 -800 49098 480 0 FreeSans 1400 90 0 0 wbs_dat_i[10]
+port 595 nsew
+flabel metal2 s 52532 -800 52644 480 0 FreeSans 1400 90 0 0 wbs_dat_i[11]
+port 596 nsew
+flabel metal2 s 56078 -800 56190 480 0 FreeSans 1400 90 0 0 wbs_dat_i[12]
+port 597 nsew
+flabel metal2 s 59624 -800 59736 480 0 FreeSans 1400 90 0 0 wbs_dat_i[13]
+port 598 nsew
+flabel metal2 s 63170 -800 63282 480 0 FreeSans 1400 90 0 0 wbs_dat_i[14]
+port 599 nsew
+flabel metal2 s 66716 -800 66828 480 0 FreeSans 1400 90 0 0 wbs_dat_i[15]
+port 600 nsew
+flabel metal2 s 70262 -800 70374 480 0 FreeSans 1400 90 0 0 wbs_dat_i[16]
+port 601 nsew
+flabel metal2 s 73808 -800 73920 480 0 FreeSans 1400 90 0 0 wbs_dat_i[17]
+port 602 nsew
+flabel metal2 s 77354 -800 77466 480 0 FreeSans 1400 90 0 0 wbs_dat_i[18]
+port 603 nsew
+flabel metal2 s 80900 -800 81012 480 0 FreeSans 1400 90 0 0 wbs_dat_i[19]
+port 604 nsew
+flabel metal2 s 13526 -800 13638 480 0 FreeSans 1400 90 0 0 wbs_dat_i[1]
+port 605 nsew
+flabel metal2 s 84446 -800 84558 480 0 FreeSans 1400 90 0 0 wbs_dat_i[20]
+port 606 nsew
+flabel metal2 s 87992 -800 88104 480 0 FreeSans 1400 90 0 0 wbs_dat_i[21]
+port 607 nsew
+flabel metal2 s 91538 -800 91650 480 0 FreeSans 1400 90 0 0 wbs_dat_i[22]
+port 608 nsew
+flabel metal2 s 95084 -800 95196 480 0 FreeSans 1400 90 0 0 wbs_dat_i[23]
+port 609 nsew
+flabel metal2 s 98630 -800 98742 480 0 FreeSans 1400 90 0 0 wbs_dat_i[24]
+port 610 nsew
+flabel metal2 s 102176 -800 102288 480 0 FreeSans 1400 90 0 0 wbs_dat_i[25]
+port 611 nsew
+flabel metal2 s 105722 -800 105834 480 0 FreeSans 1400 90 0 0 wbs_dat_i[26]
+port 612 nsew
+flabel metal2 s 109268 -800 109380 480 0 FreeSans 1400 90 0 0 wbs_dat_i[27]
+port 613 nsew
+flabel metal2 s 112814 -800 112926 480 0 FreeSans 1400 90 0 0 wbs_dat_i[28]
+port 614 nsew
+flabel metal2 s 116360 -800 116472 480 0 FreeSans 1400 90 0 0 wbs_dat_i[29]
+port 615 nsew
+flabel metal2 s 18254 -800 18366 480 0 FreeSans 1400 90 0 0 wbs_dat_i[2]
+port 616 nsew
+flabel metal2 s 119906 -800 120018 480 0 FreeSans 1400 90 0 0 wbs_dat_i[30]
+port 617 nsew
+flabel metal2 s 123452 -800 123564 480 0 FreeSans 1400 90 0 0 wbs_dat_i[31]
+port 618 nsew
+flabel metal2 s 22982 -800 23094 480 0 FreeSans 1400 90 0 0 wbs_dat_i[3]
+port 619 nsew
+flabel metal2 s 27710 -800 27822 480 0 FreeSans 1400 90 0 0 wbs_dat_i[4]
+port 620 nsew
+flabel metal2 s 31256 -800 31368 480 0 FreeSans 1400 90 0 0 wbs_dat_i[5]
+port 621 nsew
+flabel metal2 s 34802 -800 34914 480 0 FreeSans 1400 90 0 0 wbs_dat_i[6]
+port 622 nsew
+flabel metal2 s 38348 -800 38460 480 0 FreeSans 1400 90 0 0 wbs_dat_i[7]
+port 623 nsew
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 1400 90 0 0 wbs_dat_i[8]
+port 624 nsew
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 1400 90 0 0 wbs_dat_i[9]
+port 625 nsew
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 1400 90 0 0 wbs_dat_o[0]
+port 626 nsew
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 1400 90 0 0 wbs_dat_o[10]
+port 627 nsew
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 1400 90 0 0 wbs_dat_o[11]
+port 628 nsew
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 1400 90 0 0 wbs_dat_o[12]
+port 629 nsew
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 1400 90 0 0 wbs_dat_o[13]
+port 630 nsew
+flabel metal2 s 64352 -800 64464 480 0 FreeSans 1400 90 0 0 wbs_dat_o[14]
+port 631 nsew
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 1400 90 0 0 wbs_dat_o[15]
+port 632 nsew
+flabel metal2 s 71444 -800 71556 480 0 FreeSans 1400 90 0 0 wbs_dat_o[16]
+port 633 nsew
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 1400 90 0 0 wbs_dat_o[17]
+port 634 nsew
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 1400 90 0 0 wbs_dat_o[18]
+port 635 nsew
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 1400 90 0 0 wbs_dat_o[19]
+port 636 nsew
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 1400 90 0 0 wbs_dat_o[1]
+port 637 nsew
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 1400 90 0 0 wbs_dat_o[20]
+port 638 nsew
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 1400 90 0 0 wbs_dat_o[21]
+port 639 nsew
+flabel metal2 s 92720 -800 92832 480 0 FreeSans 1400 90 0 0 wbs_dat_o[22]
+port 640 nsew
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 1400 90 0 0 wbs_dat_o[23]
+port 641 nsew
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 1400 90 0 0 wbs_dat_o[24]
+port 642 nsew
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 1400 90 0 0 wbs_dat_o[25]
+port 643 nsew
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 1400 90 0 0 wbs_dat_o[26]
+port 644 nsew
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 1400 90 0 0 wbs_dat_o[27]
+port 645 nsew
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 1400 90 0 0 wbs_dat_o[28]
+port 646 nsew
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 1400 90 0 0 wbs_dat_o[29]
+port 647 nsew
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 1400 90 0 0 wbs_dat_o[2]
+port 648 nsew
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 1400 90 0 0 wbs_dat_o[30]
+port 649 nsew
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 1400 90 0 0 wbs_dat_o[31]
+port 650 nsew
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 1400 90 0 0 wbs_dat_o[3]
+port 651 nsew
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 1400 90 0 0 wbs_dat_o[4]
+port 652 nsew
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 1400 90 0 0 wbs_dat_o[5]
+port 653 nsew
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 1400 90 0 0 wbs_dat_o[6]
+port 654 nsew
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 1400 90 0 0 wbs_dat_o[7]
+port 655 nsew
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 1400 90 0 0 wbs_dat_o[8]
+port 656 nsew
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 1400 90 0 0 wbs_dat_o[9]
+port 657 nsew
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 1400 90 0 0 wbs_sel_i[0]
+port 658 nsew
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 1400 90 0 0 wbs_sel_i[1]
+port 659 nsew
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 1400 90 0 0 wbs_sel_i[2]
+port 660 nsew
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 1400 90 0 0 wbs_sel_i[3]
+port 661 nsew
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 1400 90 0 0 wbs_stb_i
+port 662 nsew
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 1400 90 0 0 wbs_we_i
+port 663 nsew
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/checks/user_analog_project_wrapper.magic.drc.tcl b/checks/user_analog_project_wrapper.magic.drc.tcl
new file mode 100644
index 0000000..fbf88c9
--- /dev/null
+++ b/checks/user_analog_project_wrapper.magic.drc.tcl
@@ -0,0 +1,15 @@
+box 1800.590um 3168.225um 1800.760um 3168.395; feedback add "This layer can't abut or partially overlap between subcells" medium
+box 1800.590um 3168.285um 1800.760um 3168.480; feedback add "This layer can't abut or partially overlap between subcells" medium
+box 1798.140um 3163.250um 1798.205um 3163.305; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1798.205um 3163.255um 1798.465um 3163.305; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1798.205um 3163.250um 1798.270um 3163.255; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1798.270um 3163.250um 1798.440um 3163.255; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1798.440um 3163.250um 1798.465um 3163.255; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1798.465um 3163.250um 1799.505um 3163.305; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1800.820um 3163.300um 1801.150um 3163.305; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1800.770um 3163.250um 1800.835um 3163.300; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1800.835um 3163.255um 1801.095um 3163.300; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1800.835um 3163.250um 1800.900um 3163.255; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1800.900um 3163.250um 1801.070um 3163.255; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1801.070um 3163.250um 1801.095um 3163.255; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
+box 1801.095um 3163.250um 1801.165um 3163.300; feedback add "Metal1 > 3um spacing to unrelated m1 < 0.28um (met1.3b)" medium
\ No newline at end of file
diff --git a/checks/user_analog_project_wrapper.magic.rdb b/checks/user_analog_project_wrapper.magic.rdb
new file mode 100644
index 0000000..8956e6b
--- /dev/null
+++ b/checks/user_analog_project_wrapper.magic.rdb
@@ -0,0 +1,85 @@
+$user_analog_project_wrapper
+ 100
+r_0_UnknownRul
+500 500 2 Nov 29 03:26:39 2020
+Rule File Pathname: /home/dhernando/caravel_analog_fulgor/checks/user_analog_project_wrapper.magic.drc
+UnknownRul: ["This layer can't abut or partially overlap between subcells"]
+p 1 4
+180000 316800
+180000 316800
+180000 316800
+180000 316800
+p 2 4
+180000 316800
+180000 316800
+180000 316800
+180000 316800
+r_0_met1.3b
+500 500 2 Nov 29 03:26:39 2020
+Rule File Pathname: /home/dhernando/caravel_analog_fulgor/checks/user_analog_project_wrapper.magic.drc
+met1.3b: Metal1 > 3um spacing to unrelated m1 < 0.28um
+p 1 4
+179800 316300
+179800 316300
+179800 316300
+179800 316300
+p 2 4
+179800 316300
+179800 316300
+179800 316300
+179800 316300
+p 3 4
+179800 316300
+179800 316300
+179800 316300
+179800 316300
+p 4 4
+179800 316300
+179800 316300
+179800 316300
+179800 316300
+p 5 4
+179800 316300
+179800 316300
+179800 316300
+179800 316300
+p 6 4
+179800 316300
+179900 316300
+179900 316300
+179800 316300
+p 7 4
+180000 316300
+180100 316300
+180100 316300
+180000 316300
+p 8 4
+180000 316300
+180000 316300
+180000 316300
+180000 316300
+p 9 4
+180000 316300
+180100 316300
+180100 316300
+180000 316300
+p 10 4
+180000 316300
+180000 316300
+180000 316300
+180000 316300
+p 11 4
+180000 316300
+180100 316300
+180100 316300
+180000 316300
+p 12 4
+180100 316300
+180100 316300
+180100 316300
+180100 316300
+p 13 4
+180100 316300
+180100 316300
+180100 316300
+180100 316300
diff --git a/ext.sh b/ext.sh
new file mode 100755
index 0000000..39a6dd7
--- /dev/null
+++ b/ext.sh
@@ -0,0 +1,33 @@
+#!/bin/bash
+
+read -p "Cellname: " cellname
+cd mag
+
+magic -rcfile magicrc -dnull -noconsole << EOF
+box 0 0 0 0
+load ${cellname}.mag -force
+box -100um -100um 100um 100um
+
+extract all
+ext2sim labels on
+ext2sim
+
+#extresist tolerance 10
+#extresist all
+
+ext2spice lvs
+ext2spice hierarchy on
+ext2spice subcircuit on
+ext2spice scale off
+ext2spice -o extractions/${cellname}_lvs.spice
+
+ext2spice cthresh 0.01
+ext2spice -o extractions/${cellname}_pex_c.spice
+
+#ext2spice extresist on
+ext2spice -o extractions/${cellname}_pex_rc.spice
+EOF
+
+rm *.ext
+rm *.sim
+rm *.nodes
diff --git a/ext_port.sh b/ext_port.sh
new file mode 100755
index 0000000..d15fad3
--- /dev/null
+++ b/ext_port.sh
@@ -0,0 +1,34 @@
+#!/bin/bash
+
+read -p "Cellname: " cellname
+cd mag
+
+magic -rcfile magicrc -dnull -noconsole << EOF
+box 0 0 0 0
+load ${cellname}.mag -force
+box -100um -100um 100um 100um
+port makeall
+
+extract all
+ext2sim labels on
+ext2sim
+
+#extresist tolerance 10
+#extresist all
+
+ext2spice lvs
+ext2spice hierarchy on
+ext2spice subcircuit on
+ext2spice scale off
+ext2spice -o extractions/${cellname}_lvs_port.spice
+
+ext2spice cthresh 0.01
+ext2spice -o extractions/${cellname}_pex_c_port.spice
+
+#ext2spice extresist on
+ext2spice -o extractions/${cellname}_pex_rc_port.spice
+EOF
+
+rm *.ext
+rm *.sim
+rm *.nodes
diff --git a/gds/.magicrc b/gds/.magicrc
new file mode 100644
index 0000000..67cdbf8
--- /dev/null
+++ b/gds/.magicrc
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+drc off
+drc euclidean on
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "$::env(PDK_ROOT)/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE maglef
+}
+
+ path search [concat "../$MAGTYPE" [path search]]
+
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/mag/sky130_ml_xx_hd
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag
+}
+
+addpath hexdigits
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 6c15cc7..d028b24 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/info.yaml b/info.yaml
index 8ba8660..ed43aba 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,13 +1,13 @@
---
project:
- description: "An analog project for Google sponsored Open MPW shuttles for SKY130."
+ description: "Analog Test Chip of several circuits used as master tesis"
foundry: "SkyWater"
- git_url: "https://github.com/efabless/caravel_analog_user.git"
- organization: "Efabless"
- organization_url: "http://efabless.com"
- owner: "Tim Edwards"
+ git_url: "https://https://github.com/fredysolis/caravel_analog_fulgor.git"
+ organization: "Fundación Fulgor"
+ organization_url: "http://www.fundacionfulgor.org.ar/sitio/index.php"
+ owner: "Diego Hernando"
process: "SKY130"
- project_name: "Caravel Analog User"
+ project_name: "Caravel Analog Fulgor"
project_id: "00000000"
tags:
- "Open MPW"
diff --git a/lvs.sh b/lvs.sh
new file mode 100755
index 0000000..c4d1f9c
--- /dev/null
+++ b/lvs.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+
+read -p "Cellname: " cellname
+
+netgen lvs mag/extractions/${cellname}_lvs.spice xschem/simulations/${cellname}.spice ~/skywater/pdk/skywater130/sky130A/libs.tech/netgen/sky130A_setup.tcl mag/extractions/lvs_${cellname}.out
+
diff --git a/mag/DFlipFlop.mag b/mag/DFlipFlop.mag
new file mode 100644
index 0000000..23937ec
--- /dev/null
+++ b/mag/DFlipFlop.mag
@@ -0,0 +1,132 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect 559 2292 1181 3068
+rect 559 0 1181 776
+<< pwell >>
+rect 559 1729 1740 2292
+rect 460 1400 1740 1729
+rect 559 776 1740 1400
+<< psubdiff >>
+rect 433 2222 654 2256
+rect 489 1718 1242 1752
+rect 487 1316 1249 1350
+rect 1000 812 1307 846
+<< poly >>
+rect 741 2104 1000 2170
+rect 740 898 999 964
+<< locali >>
+rect 433 2222 462 2256
+rect 556 2222 654 2256
+rect 483 1718 1265 1752
+rect 489 1316 1256 1350
+rect 1028 812 1205 846
+rect 1299 812 1310 846
+<< viali >>
+rect 462 2222 556 2256
+rect 1205 812 1299 846
+<< metal1 >>
+rect 523 3027 1200 3038
+rect 523 2998 1253 3027
+rect -1244 2944 1740 2998
+rect 523 2940 1195 2944
+rect 523 2904 1198 2940
+rect -131 2240 -121 2344
+rect 450 2256 596 2262
+rect 450 2222 462 2256
+rect 556 2222 596 2256
+rect 450 2216 596 2222
+rect 219 1802 229 1854
+rect 361 1814 371 1854
+rect 361 1802 373 1814
+rect 1393 1811 1403 1863
+rect 1486 1811 1496 1863
+rect 587 1712 636 1758
+rect -1244 1498 69 1570
+rect 1105 1310 1167 1356
+rect 219 1254 231 1266
+rect 221 1214 231 1254
+rect 361 1254 373 1266
+rect 361 1214 371 1254
+rect 1392 1208 1402 1260
+rect 1486 1208 1496 1260
+rect 1157 846 1311 852
+rect -91 724 -81 828
+rect 1157 812 1205 846
+rect 1299 812 1311 846
+rect 1157 806 1311 812
+rect 559 124 1181 164
+rect -1244 70 1740 124
+rect 559 30 1181 70
+<< via1 >>
+rect -190 2240 -131 2344
+rect 229 1802 361 1854
+rect 1403 1811 1486 1863
+rect 231 1214 361 1266
+rect 1402 1208 1486 1260
+rect -150 724 -91 828
+<< metal2 >>
+rect -190 2344 -131 2354
+rect -131 2266 40 2318
+rect -190 2230 -131 2240
+rect -12 1854 40 2266
+rect 1521 2258 1577 2369
+rect 229 1854 361 1864
+rect -12 1802 229 1854
+rect 229 1792 361 1802
+rect 1403 1863 1486 1873
+rect 1403 1801 1486 1811
+rect 373 1748 429 1758
+rect 1413 1722 1473 1801
+rect 429 1662 1473 1722
+rect 373 1626 429 1636
+rect 163 1432 219 1442
+rect 219 1346 1473 1406
+rect 163 1310 219 1320
+rect 231 1266 361 1276
+rect 1413 1270 1473 1346
+rect -12 1214 231 1266
+rect -150 828 -91 838
+rect -12 802 40 1214
+rect 231 1204 361 1214
+rect 1402 1260 1486 1270
+rect 1402 1198 1486 1208
+rect -91 750 40 802
+rect -150 714 -91 724
+rect 1311 699 1367 810
+<< via2 >>
+rect 373 1636 429 1748
+rect 163 1320 219 1432
+<< metal3 >>
+rect -997 804 -937 2264
+rect 363 1748 439 1753
+rect 363 1636 373 1748
+rect 429 1636 439 1748
+rect 363 1631 439 1636
+rect 153 1432 229 1437
+rect 153 1320 163 1432
+rect 219 1320 229 1432
+rect 153 1315 229 1320
+use clock_inverter clock_inverter_0
+timestamp 1624049879
+transform 1 0 -1244 0 1 0
+box 0 0 1244 3068
+use latch_diff latch_diff_1
+timestamp 1624049879
+transform -1 0 1707 0 -1 2352
+box -33 -716 1147 2352
+use latch_diff latch_diff_0
+timestamp 1624049879
+transform 1 0 33 0 1 716
+box -33 -716 1147 2352
+<< labels >>
+rlabel metal1 -1244 1498 69 1570 1 vss
+rlabel metal1 -1244 2944 1740 2998 1 vdd
+rlabel metal3 -997 1498 -937 1570 1 D
+rlabel poly 740 898 999 964 1 CLK
+rlabel poly 741 2104 1000 2170 1 nCLK
+rlabel metal2 1311 699 1367 810 1 nQ
+rlabel metal2 1521 2258 1577 2369 1 Q
+<< end >>
diff --git a/mag/example_por.mag b/mag/Old/example_por.mag
similarity index 100%
rename from mag/example_por.mag
rename to mag/Old/example_por.mag
diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag b/mag/Old/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
similarity index 100%
rename from mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
rename to mag/Old/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag b/mag/Old/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
similarity index 100%
rename from mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
rename to mag/Old/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag b/mag/Old/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
similarity index 100%
rename from mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
rename to mag/Old/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag b/mag/Old/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
similarity index 100%
rename from mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
rename to mag/Old/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag b/mag/Old/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
similarity index 100%
rename from mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
rename to mag/Old/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag b/mag/Old/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
rename to mag/Old/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag b/mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
rename to mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag b/mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
rename to mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag b/mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
rename to mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag b/mag/Old/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
rename to mag/Old/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag b/mag/Old/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
similarity index 100%
rename from mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
rename to mag/Old/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
diff --git a/mag/user_analog_proj_example.mag b/mag/Old/user_analog_proj_example.mag
similarity index 100%
rename from mag/user_analog_proj_example.mag
rename to mag/Old/user_analog_proj_example.mag
diff --git a/mag/Old/user_analog_project_wrapper.mag b/mag/Old/user_analog_project_wrapper.mag
new file mode 100644
index 0000000..ebc5e1b
--- /dev/null
+++ b/mag/Old/user_analog_project_wrapper.mag
@@ -0,0 +1,2305 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1620395479
+<< mvpsubdiff >>
+rect 345740 628255 345764 629032
+rect 371078 628255 371102 629032
+<< mvpsubdiffcont >>
+rect 345764 628255 371078 629032
+<< locali >>
+rect 345748 628255 345764 629032
+rect 371078 628255 371094 629032
+<< viali >>
+rect 357593 628300 359298 629000
+<< metal1 >>
+rect 357470 629399 359442 629457
+rect 357470 628057 357538 629399
+rect 359388 628057 359442 629399
+rect 357470 627990 359442 628057
+<< via1 >>
+rect 357538 629000 359388 629399
+rect 357538 628300 357593 629000
+rect 357593 628300 359298 629000
+rect 359298 628300 359388 629000
+rect 357538 628057 359388 628300
+<< metal2 >>
+rect 357470 629399 359442 629457
+rect 357470 628057 357538 629399
+rect 359388 628057 359442 629399
+rect 357470 627990 359442 628057
+rect 524 -800 636 480
+rect 1706 -800 1818 480
+rect 2888 -800 3000 480
+rect 4070 -800 4182 480
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+rect 7616 -800 7728 480
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+rect 573464 196230 576816 455628
+rect 573464 191430 573605 196230
+rect 576629 191430 576816 196230
+rect 573464 191191 576816 191430
+<< via4 >>
+rect 357559 643394 359314 649837
+rect 352028 615249 353603 617829
+rect 363412 615255 364987 617835
+rect 363414 597231 364992 601572
+<< metal5 >>
+rect 357521 649837 359350 649991
+rect 357521 643394 357559 649837
+rect 359314 643394 359350 649837
+rect 351918 617829 353747 617929
+rect 351918 615249 352028 617829
+rect 353603 615249 353747 617829
+rect 351918 614900 353747 615249
+rect 357521 614900 359350 643394
+rect 351918 613071 359350 614900
+rect 363318 617835 365147 617929
+rect 363318 615255 363412 617835
+rect 364987 615255 365147 617835
+rect 363318 601572 365147 615255
+rect 363318 597231 363414 601572
+rect 364992 597231 365147 601572
+rect 363318 597052 365147 597231
+<< comment >>
+rect -100 704000 584100 704100
+rect -100 0 0 704000
+rect 584000 0 584100 704000
+rect -100 -100 584100 0
+use user_analog_proj_example user_analog_proj_example_0
+timestamp 1620310959
+transform 1 0 345668 0 -1 627114
+box -59 -22 25476 8324
+<< labels >>
+flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -800 381864 480 381976 0 FreeSans 1120 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -800 338642 480 338754 0 FreeSans 1120 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -800 295420 480 295532 0 FreeSans 1120 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -800 252398 480 252510 0 FreeSans 1120 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -800 124776 480 124888 0 FreeSans 1120 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -800 81554 480 81666 0 FreeSans 1120 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -800 38332 480 38444 0 FreeSans 1120 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -800 16910 480 17022 0 FreeSans 1120 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 583520 313652 584800 313764 0 FreeSans 1120 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 583520 358874 584800 358986 0 FreeSans 1120 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 583520 405296 584800 405408 0 FreeSans 1120 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 583520 449718 584800 449830 0 FreeSans 1120 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 583520 494140 584800 494252 0 FreeSans 1120 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 583520 583562 584800 583674 0 FreeSans 1120 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -800 511530 480 511642 0 FreeSans 1120 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -800 468308 480 468420 0 FreeSans 1120 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -800 425086 480 425198 0 FreeSans 1120 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 583520 270412 584800 270524 0 FreeSans 1120 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -800 380682 480 380794 0 FreeSans 1120 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -800 337460 480 337572 0 FreeSans 1120 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -800 294238 480 294350 0 FreeSans 1120 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -800 251216 480 251328 0 FreeSans 1120 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -800 123594 480 123706 0 FreeSans 1120 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -800 80372 480 80484 0 FreeSans 1120 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -800 37150 480 37262 0 FreeSans 1120 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -800 15728 480 15840 0 FreeSans 1120 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 583520 314834 584800 314946 0 FreeSans 1120 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 583520 360056 584800 360168 0 FreeSans 1120 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 583520 406478 584800 406590 0 FreeSans 1120 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 583520 450900 584800 451012 0 FreeSans 1120 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 583520 495322 584800 495434 0 FreeSans 1120 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 583520 584744 584800 584856 0 FreeSans 1120 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -800 510348 480 510460 0 FreeSans 1120 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -800 467126 480 467238 0 FreeSans 1120 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -800 423904 480 424016 0 FreeSans 1120 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1120 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 566594 702300 571594 704800 0 FreeSans 1920 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 465394 702300 470394 704800 0 FreeSans 1920 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 413394 702300 418394 704800 0 FreeSans 1920 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 120194 702300 125194 704800 0 FreeSans 1920 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 68194 702300 73194 704800 0 FreeSans 1920 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 16194 702300 21194 704800 0 FreeSans 1920 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 326794 702300 328994 704800 0 FreeSans 1920 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 225094 702300 227294 704800 0 FreeSans 1920 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 173394 702300 175594 704800 0 FreeSans 1920 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 324294 702300 326494 704800 0 FreeSans 1920 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 222594 702300 224794 704800 0 FreeSans 1920 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 170894 702300 173094 704800 0 FreeSans 1920 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 583520 2726 584800 2838 0 FreeSans 1120 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 583520 408842 584800 408954 0 FreeSans 1120 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 583520 453264 584800 453376 0 FreeSans 1120 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 583520 497686 584800 497798 0 FreeSans 1120 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 583520 587108 584800 587220 0 FreeSans 1120 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -800 507984 480 508096 0 FreeSans 1120 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -800 464762 480 464874 0 FreeSans 1120 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -800 421540 480 421652 0 FreeSans 1120 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -800 378318 480 378430 0 FreeSans 1120 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -800 335096 480 335208 0 FreeSans 1120 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -800 291874 480 291986 0 FreeSans 1120 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 583520 7454 584800 7566 0 FreeSans 1120 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -800 248852 480 248964 0 FreeSans 1120 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -800 121230 480 121342 0 FreeSans 1120 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -800 78008 480 78120 0 FreeSans 1120 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -800 34786 480 34898 0 FreeSans 1120 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -800 13364 480 13476 0 FreeSans 1120 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -800 8636 480 8748 0 FreeSans 1120 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -800 3908 480 4020 0 FreeSans 1120 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 583520 12182 584800 12294 0 FreeSans 1120 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 583520 16910 584800 17022 0 FreeSans 1120 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 583520 21638 584800 21750 0 FreeSans 1120 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 583520 48096 584800 48208 0 FreeSans 1120 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 583520 92754 584800 92866 0 FreeSans 1120 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 583520 272776 584800 272888 0 FreeSans 1120 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 583520 317198 584800 317310 0 FreeSans 1120 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 583520 362420 584800 362532 0 FreeSans 1120 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 583520 1544 584800 1656 0 FreeSans 1120 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 583520 407660 584800 407772 0 FreeSans 1120 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 583520 452082 584800 452194 0 FreeSans 1120 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 583520 496504 584800 496616 0 FreeSans 1120 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 583520 585926 584800 586038 0 FreeSans 1120 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -800 509166 480 509278 0 FreeSans 1120 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -800 465944 480 466056 0 FreeSans 1120 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -800 422722 480 422834 0 FreeSans 1120 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -800 379500 480 379612 0 FreeSans 1120 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -800 336278 480 336390 0 FreeSans 1120 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -800 293056 480 293168 0 FreeSans 1120 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 583520 6272 584800 6384 0 FreeSans 1120 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -800 250034 480 250146 0 FreeSans 1120 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -800 122412 480 122524 0 FreeSans 1120 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -800 79190 480 79302 0 FreeSans 1120 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -800 35968 480 36080 0 FreeSans 1120 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -800 14546 480 14658 0 FreeSans 1120 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -800 9818 480 9930 0 FreeSans 1120 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -800 5090 480 5202 0 FreeSans 1120 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 583520 11000 584800 11112 0 FreeSans 1120 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 583520 15728 584800 15840 0 FreeSans 1120 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 583520 20456 584800 20568 0 FreeSans 1120 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 583520 46914 584800 47026 0 FreeSans 1120 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 583520 91572 584800 91684 0 FreeSans 1120 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 583520 271594 584800 271706 0 FreeSans 1120 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 583520 316016 584800 316128 0 FreeSans 1120 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 583520 361238 584800 361350 0 FreeSans 1120 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 583520 5090 584800 5202 0 FreeSans 1120 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 583520 411206 584800 411318 0 FreeSans 1120 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 583520 455628 584800 455740 0 FreeSans 1120 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 583520 500050 584800 500162 0 FreeSans 1120 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 583520 589472 584800 589584 0 FreeSans 1120 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -800 505620 480 505732 0 FreeSans 1120 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -800 462398 480 462510 0 FreeSans 1120 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -800 419176 480 419288 0 FreeSans 1120 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -800 375954 480 376066 0 FreeSans 1120 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -800 332732 480 332844 0 FreeSans 1120 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -800 289510 480 289622 0 FreeSans 1120 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 583520 9818 584800 9930 0 FreeSans 1120 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -800 246488 480 246600 0 FreeSans 1120 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -800 118866 480 118978 0 FreeSans 1120 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -800 75644 480 75756 0 FreeSans 1120 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -800 32422 480 32534 0 FreeSans 1120 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -800 11000 480 11112 0 FreeSans 1120 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -800 6272 480 6384 0 FreeSans 1120 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -800 1544 480 1656 0 FreeSans 1120 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 583520 14546 584800 14658 0 FreeSans 1120 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 583520 19274 584800 19386 0 FreeSans 1120 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1120 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1120 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1120 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1120 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1120 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1120 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1120 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1120 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1120 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1120 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1120 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -800 506802 480 506914 0 FreeSans 1120 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -800 463580 480 463692 0 FreeSans 1120 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -800 420358 480 420470 0 FreeSans 1120 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -800 377136 480 377248 0 FreeSans 1120 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -800 333914 480 334026 0 FreeSans 1120 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -800 290692 480 290804 0 FreeSans 1120 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 583520 8636 584800 8748 0 FreeSans 1120 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -800 247670 480 247782 0 FreeSans 1120 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -800 120048 480 120160 0 FreeSans 1120 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -800 76826 480 76938 0 FreeSans 1120 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -800 33604 480 33716 0 FreeSans 1120 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -800 12182 480 12294 0 FreeSans 1120 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -800 7454 480 7566 0 FreeSans 1120 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -800 2726 480 2838 0 FreeSans 1120 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1120 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1120 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1120 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1120 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1120 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1120 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1120 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1120 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 125816 -800 125928 480 0 FreeSans 1120 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 480416 -800 480528 480 0 FreeSans 1120 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 483962 -800 484074 480 0 FreeSans 1120 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 487508 -800 487620 480 0 FreeSans 1120 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 491054 -800 491166 480 0 FreeSans 1120 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 494600 -800 494712 480 0 FreeSans 1120 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 498146 -800 498258 480 0 FreeSans 1120 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 501692 -800 501804 480 0 FreeSans 1120 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 505238 -800 505350 480 0 FreeSans 1120 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 508784 -800 508896 480 0 FreeSans 1120 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 512330 -800 512442 480 0 FreeSans 1120 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 161276 -800 161388 480 0 FreeSans 1120 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 515876 -800 515988 480 0 FreeSans 1120 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 519422 -800 519534 480 0 FreeSans 1120 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 522968 -800 523080 480 0 FreeSans 1120 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 526514 -800 526626 480 0 FreeSans 1120 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 530060 -800 530172 480 0 FreeSans 1120 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 533606 -800 533718 480 0 FreeSans 1120 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 537152 -800 537264 480 0 FreeSans 1120 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 540698 -800 540810 480 0 FreeSans 1120 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 544244 -800 544356 480 0 FreeSans 1120 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 547790 -800 547902 480 0 FreeSans 1120 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 164822 -800 164934 480 0 FreeSans 1120 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 551336 -800 551448 480 0 FreeSans 1120 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 554882 -800 554994 480 0 FreeSans 1120 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 558428 -800 558540 480 0 FreeSans 1120 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 561974 -800 562086 480 0 FreeSans 1120 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 565520 -800 565632 480 0 FreeSans 1120 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 569066 -800 569178 480 0 FreeSans 1120 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 572612 -800 572724 480 0 FreeSans 1120 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 576158 -800 576270 480 0 FreeSans 1120 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 168368 -800 168480 480 0 FreeSans 1120 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 171914 -800 172026 480 0 FreeSans 1120 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 175460 -800 175572 480 0 FreeSans 1120 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 179006 -800 179118 480 0 FreeSans 1120 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 182552 -800 182664 480 0 FreeSans 1120 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 186098 -800 186210 480 0 FreeSans 1120 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 189644 -800 189756 480 0 FreeSans 1120 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 193190 -800 193302 480 0 FreeSans 1120 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 129362 -800 129474 480 0 FreeSans 1120 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 196736 -800 196848 480 0 FreeSans 1120 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 200282 -800 200394 480 0 FreeSans 1120 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 203828 -800 203940 480 0 FreeSans 1120 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 207374 -800 207486 480 0 FreeSans 1120 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 210920 -800 211032 480 0 FreeSans 1120 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 214466 -800 214578 480 0 FreeSans 1120 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 218012 -800 218124 480 0 FreeSans 1120 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 221558 -800 221670 480 0 FreeSans 1120 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 225104 -800 225216 480 0 FreeSans 1120 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 228650 -800 228762 480 0 FreeSans 1120 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 132908 -800 133020 480 0 FreeSans 1120 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 232196 -800 232308 480 0 FreeSans 1120 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 235742 -800 235854 480 0 FreeSans 1120 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 239288 -800 239400 480 0 FreeSans 1120 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 242834 -800 242946 480 0 FreeSans 1120 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 246380 -800 246492 480 0 FreeSans 1120 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 249926 -800 250038 480 0 FreeSans 1120 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 253472 -800 253584 480 0 FreeSans 1120 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 257018 -800 257130 480 0 FreeSans 1120 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 260564 -800 260676 480 0 FreeSans 1120 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 264110 -800 264222 480 0 FreeSans 1120 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 136454 -800 136566 480 0 FreeSans 1120 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 267656 -800 267768 480 0 FreeSans 1120 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 271202 -800 271314 480 0 FreeSans 1120 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 274748 -800 274860 480 0 FreeSans 1120 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 278294 -800 278406 480 0 FreeSans 1120 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 281840 -800 281952 480 0 FreeSans 1120 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 285386 -800 285498 480 0 FreeSans 1120 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 288932 -800 289044 480 0 FreeSans 1120 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 292478 -800 292590 480 0 FreeSans 1120 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 296024 -800 296136 480 0 FreeSans 1120 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 299570 -800 299682 480 0 FreeSans 1120 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 140000 -800 140112 480 0 FreeSans 1120 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 303116 -800 303228 480 0 FreeSans 1120 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 306662 -800 306774 480 0 FreeSans 1120 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 310208 -800 310320 480 0 FreeSans 1120 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 313754 -800 313866 480 0 FreeSans 1120 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 317300 -800 317412 480 0 FreeSans 1120 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 320846 -800 320958 480 0 FreeSans 1120 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 324392 -800 324504 480 0 FreeSans 1120 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 327938 -800 328050 480 0 FreeSans 1120 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 331484 -800 331596 480 0 FreeSans 1120 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 335030 -800 335142 480 0 FreeSans 1120 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 143546 -800 143658 480 0 FreeSans 1120 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 338576 -800 338688 480 0 FreeSans 1120 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 342122 -800 342234 480 0 FreeSans 1120 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 345668 -800 345780 480 0 FreeSans 1120 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 349214 -800 349326 480 0 FreeSans 1120 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 352760 -800 352872 480 0 FreeSans 1120 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 356306 -800 356418 480 0 FreeSans 1120 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 359852 -800 359964 480 0 FreeSans 1120 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 363398 -800 363510 480 0 FreeSans 1120 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 366944 -800 367056 480 0 FreeSans 1120 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 370490 -800 370602 480 0 FreeSans 1120 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 147092 -800 147204 480 0 FreeSans 1120 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 374036 -800 374148 480 0 FreeSans 1120 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 377582 -800 377694 480 0 FreeSans 1120 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 381128 -800 381240 480 0 FreeSans 1120 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 384674 -800 384786 480 0 FreeSans 1120 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 388220 -800 388332 480 0 FreeSans 1120 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 391766 -800 391878 480 0 FreeSans 1120 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 395312 -800 395424 480 0 FreeSans 1120 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 398858 -800 398970 480 0 FreeSans 1120 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 402404 -800 402516 480 0 FreeSans 1120 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 405950 -800 406062 480 0 FreeSans 1120 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 150638 -800 150750 480 0 FreeSans 1120 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 409496 -800 409608 480 0 FreeSans 1120 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 413042 -800 413154 480 0 FreeSans 1120 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 416588 -800 416700 480 0 FreeSans 1120 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 420134 -800 420246 480 0 FreeSans 1120 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 423680 -800 423792 480 0 FreeSans 1120 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 427226 -800 427338 480 0 FreeSans 1120 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 430772 -800 430884 480 0 FreeSans 1120 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 434318 -800 434430 480 0 FreeSans 1120 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 437864 -800 437976 480 0 FreeSans 1120 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 441410 -800 441522 480 0 FreeSans 1120 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 154184 -800 154296 480 0 FreeSans 1120 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 444956 -800 445068 480 0 FreeSans 1120 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 448502 -800 448614 480 0 FreeSans 1120 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 452048 -800 452160 480 0 FreeSans 1120 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 455594 -800 455706 480 0 FreeSans 1120 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 459140 -800 459252 480 0 FreeSans 1120 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 462686 -800 462798 480 0 FreeSans 1120 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 466232 -800 466344 480 0 FreeSans 1120 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 469778 -800 469890 480 0 FreeSans 1120 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 473324 -800 473436 480 0 FreeSans 1120 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 476870 -800 476982 480 0 FreeSans 1120 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 157730 -800 157842 480 0 FreeSans 1120 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 126998 -800 127110 480 0 FreeSans 1120 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 481598 -800 481710 480 0 FreeSans 1120 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 485144 -800 485256 480 0 FreeSans 1120 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 488690 -800 488802 480 0 FreeSans 1120 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 492236 -800 492348 480 0 FreeSans 1120 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 495782 -800 495894 480 0 FreeSans 1120 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 499328 -800 499440 480 0 FreeSans 1120 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 502874 -800 502986 480 0 FreeSans 1120 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 506420 -800 506532 480 0 FreeSans 1120 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 509966 -800 510078 480 0 FreeSans 1120 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 513512 -800 513624 480 0 FreeSans 1120 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 162458 -800 162570 480 0 FreeSans 1120 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 517058 -800 517170 480 0 FreeSans 1120 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 520604 -800 520716 480 0 FreeSans 1120 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 524150 -800 524262 480 0 FreeSans 1120 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 527696 -800 527808 480 0 FreeSans 1120 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 531242 -800 531354 480 0 FreeSans 1120 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 534788 -800 534900 480 0 FreeSans 1120 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 538334 -800 538446 480 0 FreeSans 1120 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 541880 -800 541992 480 0 FreeSans 1120 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 545426 -800 545538 480 0 FreeSans 1120 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 548972 -800 549084 480 0 FreeSans 1120 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 166004 -800 166116 480 0 FreeSans 1120 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 552518 -800 552630 480 0 FreeSans 1120 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 556064 -800 556176 480 0 FreeSans 1120 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 559610 -800 559722 480 0 FreeSans 1120 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 563156 -800 563268 480 0 FreeSans 1120 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 566702 -800 566814 480 0 FreeSans 1120 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 570248 -800 570360 480 0 FreeSans 1120 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 573794 -800 573906 480 0 FreeSans 1120 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 577340 -800 577452 480 0 FreeSans 1120 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 169550 -800 169662 480 0 FreeSans 1120 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 173096 -800 173208 480 0 FreeSans 1120 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 176642 -800 176754 480 0 FreeSans 1120 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 180188 -800 180300 480 0 FreeSans 1120 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 183734 -800 183846 480 0 FreeSans 1120 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 187280 -800 187392 480 0 FreeSans 1120 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 190826 -800 190938 480 0 FreeSans 1120 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 194372 -800 194484 480 0 FreeSans 1120 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 130544 -800 130656 480 0 FreeSans 1120 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 197918 -800 198030 480 0 FreeSans 1120 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 201464 -800 201576 480 0 FreeSans 1120 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 205010 -800 205122 480 0 FreeSans 1120 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 208556 -800 208668 480 0 FreeSans 1120 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 212102 -800 212214 480 0 FreeSans 1120 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 215648 -800 215760 480 0 FreeSans 1120 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 219194 -800 219306 480 0 FreeSans 1120 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 222740 -800 222852 480 0 FreeSans 1120 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 226286 -800 226398 480 0 FreeSans 1120 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 229832 -800 229944 480 0 FreeSans 1120 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 134090 -800 134202 480 0 FreeSans 1120 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 233378 -800 233490 480 0 FreeSans 1120 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 236924 -800 237036 480 0 FreeSans 1120 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 240470 -800 240582 480 0 FreeSans 1120 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 244016 -800 244128 480 0 FreeSans 1120 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 247562 -800 247674 480 0 FreeSans 1120 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 251108 -800 251220 480 0 FreeSans 1120 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 254654 -800 254766 480 0 FreeSans 1120 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 258200 -800 258312 480 0 FreeSans 1120 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 261746 -800 261858 480 0 FreeSans 1120 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 265292 -800 265404 480 0 FreeSans 1120 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 137636 -800 137748 480 0 FreeSans 1120 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 268838 -800 268950 480 0 FreeSans 1120 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 272384 -800 272496 480 0 FreeSans 1120 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 275930 -800 276042 480 0 FreeSans 1120 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 279476 -800 279588 480 0 FreeSans 1120 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 283022 -800 283134 480 0 FreeSans 1120 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 286568 -800 286680 480 0 FreeSans 1120 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 290114 -800 290226 480 0 FreeSans 1120 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 293660 -800 293772 480 0 FreeSans 1120 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 297206 -800 297318 480 0 FreeSans 1120 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 300752 -800 300864 480 0 FreeSans 1120 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 141182 -800 141294 480 0 FreeSans 1120 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 304298 -800 304410 480 0 FreeSans 1120 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 307844 -800 307956 480 0 FreeSans 1120 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 311390 -800 311502 480 0 FreeSans 1120 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 314936 -800 315048 480 0 FreeSans 1120 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 318482 -800 318594 480 0 FreeSans 1120 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 322028 -800 322140 480 0 FreeSans 1120 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 325574 -800 325686 480 0 FreeSans 1120 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 329120 -800 329232 480 0 FreeSans 1120 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 332666 -800 332778 480 0 FreeSans 1120 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 336212 -800 336324 480 0 FreeSans 1120 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 144728 -800 144840 480 0 FreeSans 1120 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 339758 -800 339870 480 0 FreeSans 1120 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 343304 -800 343416 480 0 FreeSans 1120 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 346850 -800 346962 480 0 FreeSans 1120 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 350396 -800 350508 480 0 FreeSans 1120 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 353942 -800 354054 480 0 FreeSans 1120 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 357488 -800 357600 480 0 FreeSans 1120 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 361034 -800 361146 480 0 FreeSans 1120 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 364580 -800 364692 480 0 FreeSans 1120 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 368126 -800 368238 480 0 FreeSans 1120 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 371672 -800 371784 480 0 FreeSans 1120 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 148274 -800 148386 480 0 FreeSans 1120 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 375218 -800 375330 480 0 FreeSans 1120 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 378764 -800 378876 480 0 FreeSans 1120 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 382310 -800 382422 480 0 FreeSans 1120 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 385856 -800 385968 480 0 FreeSans 1120 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 389402 -800 389514 480 0 FreeSans 1120 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 392948 -800 393060 480 0 FreeSans 1120 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 396494 -800 396606 480 0 FreeSans 1120 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 400040 -800 400152 480 0 FreeSans 1120 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 403586 -800 403698 480 0 FreeSans 1120 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 407132 -800 407244 480 0 FreeSans 1120 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 151820 -800 151932 480 0 FreeSans 1120 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 410678 -800 410790 480 0 FreeSans 1120 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 414224 -800 414336 480 0 FreeSans 1120 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 417770 -800 417882 480 0 FreeSans 1120 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 421316 -800 421428 480 0 FreeSans 1120 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 424862 -800 424974 480 0 FreeSans 1120 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 428408 -800 428520 480 0 FreeSans 1120 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 431954 -800 432066 480 0 FreeSans 1120 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 435500 -800 435612 480 0 FreeSans 1120 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 439046 -800 439158 480 0 FreeSans 1120 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 442592 -800 442704 480 0 FreeSans 1120 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 155366 -800 155478 480 0 FreeSans 1120 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 446138 -800 446250 480 0 FreeSans 1120 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 449684 -800 449796 480 0 FreeSans 1120 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 453230 -800 453342 480 0 FreeSans 1120 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 456776 -800 456888 480 0 FreeSans 1120 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 460322 -800 460434 480 0 FreeSans 1120 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 463868 -800 463980 480 0 FreeSans 1120 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 467414 -800 467526 480 0 FreeSans 1120 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 470960 -800 471072 480 0 FreeSans 1120 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 474506 -800 474618 480 0 FreeSans 1120 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 478052 -800 478164 480 0 FreeSans 1120 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 158912 -800 159024 480 0 FreeSans 1120 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 128180 -800 128292 480 0 FreeSans 1120 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 482780 -800 482892 480 0 FreeSans 1120 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 486326 -800 486438 480 0 FreeSans 1120 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 489872 -800 489984 480 0 FreeSans 1120 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 493418 -800 493530 480 0 FreeSans 1120 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 496964 -800 497076 480 0 FreeSans 1120 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 500510 -800 500622 480 0 FreeSans 1120 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 504056 -800 504168 480 0 FreeSans 1120 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 507602 -800 507714 480 0 FreeSans 1120 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 511148 -800 511260 480 0 FreeSans 1120 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 514694 -800 514806 480 0 FreeSans 1120 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 163640 -800 163752 480 0 FreeSans 1120 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 518240 -800 518352 480 0 FreeSans 1120 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 521786 -800 521898 480 0 FreeSans 1120 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 525332 -800 525444 480 0 FreeSans 1120 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 528878 -800 528990 480 0 FreeSans 1120 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 532424 -800 532536 480 0 FreeSans 1120 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 535970 -800 536082 480 0 FreeSans 1120 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 539516 -800 539628 480 0 FreeSans 1120 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 543062 -800 543174 480 0 FreeSans 1120 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 546608 -800 546720 480 0 FreeSans 1120 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 550154 -800 550266 480 0 FreeSans 1120 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 167186 -800 167298 480 0 FreeSans 1120 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 553700 -800 553812 480 0 FreeSans 1120 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 557246 -800 557358 480 0 FreeSans 1120 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 560792 -800 560904 480 0 FreeSans 1120 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 564338 -800 564450 480 0 FreeSans 1120 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 567884 -800 567996 480 0 FreeSans 1120 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 571430 -800 571542 480 0 FreeSans 1120 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 574976 -800 575088 480 0 FreeSans 1120 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 578522 -800 578634 480 0 FreeSans 1120 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 170732 -800 170844 480 0 FreeSans 1120 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 174278 -800 174390 480 0 FreeSans 1120 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 177824 -800 177936 480 0 FreeSans 1120 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 181370 -800 181482 480 0 FreeSans 1120 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 184916 -800 185028 480 0 FreeSans 1120 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 188462 -800 188574 480 0 FreeSans 1120 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 192008 -800 192120 480 0 FreeSans 1120 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 195554 -800 195666 480 0 FreeSans 1120 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 131726 -800 131838 480 0 FreeSans 1120 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 199100 -800 199212 480 0 FreeSans 1120 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 202646 -800 202758 480 0 FreeSans 1120 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 206192 -800 206304 480 0 FreeSans 1120 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 209738 -800 209850 480 0 FreeSans 1120 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 213284 -800 213396 480 0 FreeSans 1120 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 216830 -800 216942 480 0 FreeSans 1120 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 220376 -800 220488 480 0 FreeSans 1120 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 223922 -800 224034 480 0 FreeSans 1120 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 227468 -800 227580 480 0 FreeSans 1120 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 231014 -800 231126 480 0 FreeSans 1120 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 135272 -800 135384 480 0 FreeSans 1120 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 234560 -800 234672 480 0 FreeSans 1120 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 238106 -800 238218 480 0 FreeSans 1120 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 241652 -800 241764 480 0 FreeSans 1120 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 245198 -800 245310 480 0 FreeSans 1120 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 248744 -800 248856 480 0 FreeSans 1120 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 252290 -800 252402 480 0 FreeSans 1120 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 255836 -800 255948 480 0 FreeSans 1120 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 259382 -800 259494 480 0 FreeSans 1120 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 262928 -800 263040 480 0 FreeSans 1120 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 266474 -800 266586 480 0 FreeSans 1120 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 138818 -800 138930 480 0 FreeSans 1120 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 270020 -800 270132 480 0 FreeSans 1120 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 273566 -800 273678 480 0 FreeSans 1120 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 277112 -800 277224 480 0 FreeSans 1120 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 280658 -800 280770 480 0 FreeSans 1120 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 284204 -800 284316 480 0 FreeSans 1120 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 287750 -800 287862 480 0 FreeSans 1120 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 291296 -800 291408 480 0 FreeSans 1120 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 294842 -800 294954 480 0 FreeSans 1120 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 298388 -800 298500 480 0 FreeSans 1120 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 301934 -800 302046 480 0 FreeSans 1120 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 142364 -800 142476 480 0 FreeSans 1120 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 305480 -800 305592 480 0 FreeSans 1120 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 309026 -800 309138 480 0 FreeSans 1120 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 312572 -800 312684 480 0 FreeSans 1120 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 316118 -800 316230 480 0 FreeSans 1120 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 319664 -800 319776 480 0 FreeSans 1120 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 323210 -800 323322 480 0 FreeSans 1120 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 326756 -800 326868 480 0 FreeSans 1120 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 330302 -800 330414 480 0 FreeSans 1120 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 333848 -800 333960 480 0 FreeSans 1120 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 337394 -800 337506 480 0 FreeSans 1120 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 145910 -800 146022 480 0 FreeSans 1120 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 340940 -800 341052 480 0 FreeSans 1120 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 344486 -800 344598 480 0 FreeSans 1120 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 348032 -800 348144 480 0 FreeSans 1120 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 351578 -800 351690 480 0 FreeSans 1120 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 355124 -800 355236 480 0 FreeSans 1120 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 358670 -800 358782 480 0 FreeSans 1120 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 362216 -800 362328 480 0 FreeSans 1120 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 365762 -800 365874 480 0 FreeSans 1120 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 369308 -800 369420 480 0 FreeSans 1120 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 372854 -800 372966 480 0 FreeSans 1120 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 149456 -800 149568 480 0 FreeSans 1120 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 376400 -800 376512 480 0 FreeSans 1120 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 379946 -800 380058 480 0 FreeSans 1120 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 383492 -800 383604 480 0 FreeSans 1120 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 387038 -800 387150 480 0 FreeSans 1120 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 390584 -800 390696 480 0 FreeSans 1120 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 394130 -800 394242 480 0 FreeSans 1120 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 397676 -800 397788 480 0 FreeSans 1120 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 401222 -800 401334 480 0 FreeSans 1120 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 404768 -800 404880 480 0 FreeSans 1120 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 408314 -800 408426 480 0 FreeSans 1120 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 153002 -800 153114 480 0 FreeSans 1120 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 411860 -800 411972 480 0 FreeSans 1120 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 415406 -800 415518 480 0 FreeSans 1120 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 418952 -800 419064 480 0 FreeSans 1120 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 422498 -800 422610 480 0 FreeSans 1120 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 426044 -800 426156 480 0 FreeSans 1120 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 429590 -800 429702 480 0 FreeSans 1120 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 433136 -800 433248 480 0 FreeSans 1120 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 436682 -800 436794 480 0 FreeSans 1120 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 440228 -800 440340 480 0 FreeSans 1120 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 443774 -800 443886 480 0 FreeSans 1120 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 156548 -800 156660 480 0 FreeSans 1120 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 447320 -800 447432 480 0 FreeSans 1120 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 450866 -800 450978 480 0 FreeSans 1120 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 454412 -800 454524 480 0 FreeSans 1120 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 457958 -800 458070 480 0 FreeSans 1120 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 461504 -800 461616 480 0 FreeSans 1120 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 465050 -800 465162 480 0 FreeSans 1120 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 468596 -800 468708 480 0 FreeSans 1120 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 472142 -800 472254 480 0 FreeSans 1120 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 475688 -800 475800 480 0 FreeSans 1120 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 479234 -800 479346 480 0 FreeSans 1120 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 160094 -800 160206 480 0 FreeSans 1120 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 579704 -800 579816 480 0 FreeSans 1120 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 580886 -800 580998 480 0 FreeSans 1120 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 582068 -800 582180 480 0 FreeSans 1120 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 583250 -800 583362 480 0 FreeSans 1120 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 582340 639784 584800 644584 0 FreeSans 1120 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 582340 629784 584800 634584 0 FreeSans 1120 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 643842 1660 648642 0 FreeSans 1120 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 633842 1660 638642 0 FreeSans 1120 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1120 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1120 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 204888 1660 209688 0 FreeSans 1120 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 214888 1660 219688 0 FreeSans 1120 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 520594 702340 525394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1120 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 559442 1660 564242 0 FreeSans 1120 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 549442 1660 554242 0 FreeSans 1120 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1120 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 582340 181430 584800 186230 0 FreeSans 1120 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 172888 1660 177688 0 FreeSans 1120 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 162888 1660 167688 0 FreeSans 1120 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 524 -800 636 480 0 FreeSans 1120 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 1706 -800 1818 480 0 FreeSans 1120 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 2888 -800 3000 480 0 FreeSans 1120 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 7616 -800 7728 480 0 FreeSans 1120 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 47804 -800 47916 480 0 FreeSans 1120 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 51350 -800 51462 480 0 FreeSans 1120 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 54896 -800 55008 480 0 FreeSans 1120 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 58442 -800 58554 480 0 FreeSans 1120 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 61988 -800 62100 480 0 FreeSans 1120 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 65534 -800 65646 480 0 FreeSans 1120 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 69080 -800 69192 480 0 FreeSans 1120 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 72626 -800 72738 480 0 FreeSans 1120 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 76172 -800 76284 480 0 FreeSans 1120 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 79718 -800 79830 480 0 FreeSans 1120 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 12344 -800 12456 480 0 FreeSans 1120 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 83264 -800 83376 480 0 FreeSans 1120 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 86810 -800 86922 480 0 FreeSans 1120 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 90356 -800 90468 480 0 FreeSans 1120 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 93902 -800 94014 480 0 FreeSans 1120 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 97448 -800 97560 480 0 FreeSans 1120 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 100994 -800 101106 480 0 FreeSans 1120 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 104540 -800 104652 480 0 FreeSans 1120 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 108086 -800 108198 480 0 FreeSans 1120 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 111632 -800 111744 480 0 FreeSans 1120 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 115178 -800 115290 480 0 FreeSans 1120 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 17072 -800 17184 480 0 FreeSans 1120 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 118724 -800 118836 480 0 FreeSans 1120 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 122270 -800 122382 480 0 FreeSans 1120 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 21800 -800 21912 480 0 FreeSans 1120 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 26528 -800 26640 480 0 FreeSans 1120 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 30074 -800 30186 480 0 FreeSans 1120 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 33620 -800 33732 480 0 FreeSans 1120 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 37166 -800 37278 480 0 FreeSans 1120 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 40712 -800 40824 480 0 FreeSans 1120 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 44258 -800 44370 480 0 FreeSans 1120 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 4070 -800 4182 480 0 FreeSans 1120 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 8798 -800 8910 480 0 FreeSans 1120 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 48986 -800 49098 480 0 FreeSans 1120 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 52532 -800 52644 480 0 FreeSans 1120 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 56078 -800 56190 480 0 FreeSans 1120 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 59624 -800 59736 480 0 FreeSans 1120 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 63170 -800 63282 480 0 FreeSans 1120 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 66716 -800 66828 480 0 FreeSans 1120 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 70262 -800 70374 480 0 FreeSans 1120 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 73808 -800 73920 480 0 FreeSans 1120 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 77354 -800 77466 480 0 FreeSans 1120 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 80900 -800 81012 480 0 FreeSans 1120 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 13526 -800 13638 480 0 FreeSans 1120 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 84446 -800 84558 480 0 FreeSans 1120 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 87992 -800 88104 480 0 FreeSans 1120 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 91538 -800 91650 480 0 FreeSans 1120 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 95084 -800 95196 480 0 FreeSans 1120 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 98630 -800 98742 480 0 FreeSans 1120 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 102176 -800 102288 480 0 FreeSans 1120 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 105722 -800 105834 480 0 FreeSans 1120 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 109268 -800 109380 480 0 FreeSans 1120 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 112814 -800 112926 480 0 FreeSans 1120 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 116360 -800 116472 480 0 FreeSans 1120 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 18254 -800 18366 480 0 FreeSans 1120 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 119906 -800 120018 480 0 FreeSans 1120 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 123452 -800 123564 480 0 FreeSans 1120 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 22982 -800 23094 480 0 FreeSans 1120 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 27710 -800 27822 480 0 FreeSans 1120 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 31256 -800 31368 480 0 FreeSans 1120 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 34802 -800 34914 480 0 FreeSans 1120 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 38348 -800 38460 480 0 FreeSans 1120 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 1120 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 1120 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 1120 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 1120 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 1120 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 1120 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 1120 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 64352 -800 64464 480 0 FreeSans 1120 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 1120 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 71444 -800 71556 480 0 FreeSans 1120 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 1120 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 1120 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 1120 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 1120 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 1120 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 1120 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 92720 -800 92832 480 0 FreeSans 1120 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 1120 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 1120 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 1120 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 1120 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 1120 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 1120 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 1120 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 1120 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 1120 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 1120 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 1120 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 1120 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 1120 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 1120 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 1120 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 1120 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 1120 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 1120 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 1120 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 1120 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 1120 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 1120 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
+port 677 nsew signal input
+flabel metal3 572152 640142 580220 644150 0 FreeSans 16000 0 0 0 VCCD1
+flabel metal3 567038 550960 577302 554546 0 FreeSans 16000 0 0 0 VDDA1
+flabel metal3 511190 664896 514962 676272 0 FreeSans 16000 90 0 0 VSSA1
+flabel metal3 561703 191929 571721 195859 0 FreeSans 16000 0 0 0 VSSD1
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/mag/user_analog_project_wrapper_empty.mag b/mag/Old/user_analog_project_wrapper_empty.mag
similarity index 100%
rename from mag/user_analog_project_wrapper_empty.mag
rename to mag/Old/user_analog_project_wrapper_empty.mag
diff --git a/mag/PFD.mag b/mag/PFD.mag
new file mode 100644
index 0000000..8461b8c
--- /dev/null
+++ b/mag/PFD.mag
@@ -0,0 +1,101 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect 2872 706 3790 1304
+rect 3241 700 3768 706
+<< metal1 >>
+rect 1390 1234 1400 1268
+rect 0 1180 1400 1234
+rect 1390 1146 1400 1180
+rect 1472 1234 1482 1268
+rect 2836 1234 3504 1274
+rect 1472 1180 3504 1234
+rect 1472 1146 1482 1180
+rect 2836 1140 3504 1180
+rect 0 652 210 718
+rect 3150 676 3504 1140
+rect 3754 97 3775 101
+rect 2123 36 2176 39
+rect 175 30 2786 36
+rect 0 -30 2872 30
+rect 2952 -26 2962 78
+rect 3014 -26 3024 78
+rect 3651 45 3661 97
+rect 3765 45 3775 97
+rect 3754 35 3775 45
+rect 175 -36 2123 -30
+rect 2159 -36 2786 -30
+rect 3752 -32 3775 -22
+rect 2865 -164 2919 -58
+rect 3651 -84 3661 -32
+rect 3765 -84 3775 -32
+rect 3716 -88 3775 -84
+rect 2872 -434 2919 -164
+rect 0 -718 210 -652
+rect 1390 -1180 1400 -1146
+rect 0 -1234 1400 -1180
+rect 1390 -1268 1400 -1234
+rect 1472 -1180 1482 -1146
+rect 1472 -1234 2872 -1180
+rect 1472 -1268 1482 -1234
+<< via1 >>
+rect 1400 1146 1472 1268
+rect 2962 -26 3014 78
+rect 3661 45 3765 97
+rect 3661 -84 3765 -32
+rect 1400 -1268 1472 -1146
+<< metal2 >>
+rect 1400 1268 1472 1278
+rect 1400 1136 1472 1146
+rect 2802 572 3790 624
+rect 2159 36 2211 436
+rect 3686 107 3738 572
+rect 3661 97 3765 107
+rect 2962 78 3014 88
+rect 2159 -26 2962 36
+rect 3014 -26 3024 36
+rect 3661 35 3765 45
+rect 2159 -36 3024 -26
+rect 3661 -32 3765 -22
+rect 2159 -436 2211 -36
+rect 3661 -94 3765 -84
+rect 3686 -572 3738 -94
+rect 2806 -624 3789 -572
+rect 1400 -1146 1472 -1136
+rect 1400 -1278 1472 -1268
+<< via2 >>
+rect 1400 1146 1472 1268
+rect 1400 -1268 1472 -1146
+<< metal3 >>
+rect 1390 1268 1482 1273
+rect 1390 1146 1400 1268
+rect 1472 1146 1482 1268
+rect 1390 1141 1482 1146
+rect 1400 -1141 1472 1141
+rect 1390 -1146 1482 -1141
+rect 1390 -1268 1400 -1146
+rect 1472 -1268 1482 -1146
+rect 1390 -1273 1482 -1268
+use dff_pfd dff_pfd_1
+timestamp 1624049879
+transform 1 0 0 0 -1 0
+box 0 0 2872 1304
+use dff_pfd dff_pfd_0
+timestamp 1624049879
+transform 1 0 0 0 1 0
+box 0 0 2872 1304
+use and_pfd and_pfd_0
+timestamp 1624049879
+transform -1 0 3790 0 1 -598
+box 0 0 918 1304
+<< labels >>
+rlabel metal1 0 652 210 718 1 A
+rlabel metal1 0 -718 210 -652 1 B
+rlabel metal1 0 -30 2872 30 1 vss
+rlabel metal2 2802 572 3790 624 1 Up
+rlabel metal2 2806 -624 3789 -572 1 Down
+rlabel metal1 0 1180 3504 1234 1 vdd
+rlabel metal2 2159 -436 2211 436 1 Reset
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/DFlipFlop.mag b/mag/afernandez_residue_amplifier/DFlipFlop.mag
new file mode 100644
index 0000000..9e0dd10
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/DFlipFlop.mag
@@ -0,0 +1,132 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623898709
+<< nwell >>
+rect 559 2292 1181 3068
+rect 559 0 1181 776
+<< pwell >>
+rect 559 1729 1740 2292
+rect 460 1400 1740 1729
+rect 559 776 1740 1400
+<< psubdiff >>
+rect 433 2222 654 2256
+rect 489 1718 1242 1752
+rect 487 1316 1249 1350
+rect 1000 812 1307 846
+<< poly >>
+rect 741 2104 1000 2170
+rect 740 898 999 964
+<< locali >>
+rect 433 2222 462 2256
+rect 556 2222 654 2256
+rect 483 1718 1265 1752
+rect 489 1316 1256 1350
+rect 1028 812 1205 846
+rect 1299 812 1310 846
+<< viali >>
+rect 462 2222 556 2256
+rect 1205 812 1299 846
+<< metal1 >>
+rect 523 3027 1200 3038
+rect 523 2998 1253 3027
+rect -1244 2944 1740 2998
+rect 523 2940 1195 2944
+rect 523 2904 1198 2940
+rect -131 2240 -121 2344
+rect 450 2256 596 2262
+rect 450 2222 462 2256
+rect 556 2222 596 2256
+rect 450 2216 596 2222
+rect 219 1802 229 1854
+rect 361 1814 371 1854
+rect 361 1802 373 1814
+rect 1393 1811 1403 1863
+rect 1486 1811 1496 1863
+rect 587 1712 636 1758
+rect -1244 1498 69 1570
+rect 1105 1310 1167 1356
+rect 219 1254 231 1266
+rect 221 1214 231 1254
+rect 361 1254 373 1266
+rect 361 1214 371 1254
+rect 1392 1208 1402 1260
+rect 1486 1208 1496 1260
+rect 1157 846 1311 852
+rect -91 724 -81 828
+rect 1157 812 1205 846
+rect 1299 812 1311 846
+rect 1157 806 1311 812
+rect 559 124 1181 164
+rect -1244 70 1740 124
+rect 559 30 1181 70
+<< via1 >>
+rect -190 2240 -131 2344
+rect 229 1802 361 1854
+rect 1403 1811 1486 1863
+rect 231 1214 361 1266
+rect 1402 1208 1486 1260
+rect -150 724 -91 828
+<< metal2 >>
+rect -190 2344 -131 2354
+rect -131 2266 40 2318
+rect -190 2230 -131 2240
+rect -12 1854 40 2266
+rect 1521 2258 1577 2369
+rect 229 1854 361 1864
+rect -12 1802 229 1854
+rect 229 1792 361 1802
+rect 1403 1863 1486 1873
+rect 1403 1801 1486 1811
+rect 373 1748 429 1758
+rect 1413 1722 1473 1801
+rect 429 1662 1473 1722
+rect 373 1626 429 1636
+rect 163 1432 219 1442
+rect 219 1346 1473 1406
+rect 163 1310 219 1320
+rect 231 1266 361 1276
+rect 1413 1270 1473 1346
+rect -12 1214 231 1266
+rect -150 828 -91 838
+rect -12 802 40 1214
+rect 231 1204 361 1214
+rect 1402 1260 1486 1270
+rect 1402 1198 1486 1208
+rect -91 750 40 802
+rect -150 714 -91 724
+rect 1311 699 1367 810
+<< via2 >>
+rect 373 1636 429 1748
+rect 163 1320 219 1432
+<< metal3 >>
+rect -997 804 -937 2264
+rect 363 1748 439 1753
+rect 363 1636 373 1748
+rect 429 1636 439 1748
+rect 363 1631 439 1636
+rect 153 1432 229 1437
+rect 153 1320 163 1432
+rect 219 1320 229 1432
+rect 153 1315 229 1320
+use clock_inverter *clock_inverter_0
+timestamp 1623799048
+transform 1 0 -1244 0 1 0
+box 0 0 1244 3068
+use latch_diff *latch_diff_1
+timestamp 1623798783
+transform -1 0 1707 0 -1 2352
+box -33 -716 1147 2352
+use latch_diff *latch_diff_0
+timestamp 1623798783
+transform 1 0 33 0 1 716
+box -33 -716 1147 2352
+<< labels >>
+rlabel metal1 -1244 1498 69 1570 1 vss
+rlabel metal1 -1244 2944 1740 2998 1 vdd
+rlabel metal3 -997 1498 -937 1570 1 D
+rlabel poly 740 898 999 964 1 CLK
+rlabel poly 741 2104 1000 2170 1 nCLK
+rlabel metal2 1311 699 1367 810 1 nQ
+rlabel metal2 1521 2258 1577 2369 1 Q
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/buffer_no_inv_x05.mag b/mag/afernandez_residue_amplifier/buffer_no_inv_x05.mag
new file mode 100644
index 0000000..a29603b
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/buffer_no_inv_x05.mag
@@ -0,0 +1,27 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624038785
+<< metal1 >>
+rect 418 1060 443 1086
+rect 423 119 448 123
+rect 420 97 448 119
+rect 420 93 445 97
+rect 418 49 443 75
+<< metal2 >>
+rect 14 526 39 552
+rect 823 529 848 555
+use inverter_min inverter_min_1
+timestamp 1624038681
+transform 1 0 485 0 1 -6
+box -53 16 369 1179
+use inverter_min inverter_min_0
+timestamp 1624038681
+transform 1 0 63 0 1 -6
+box -53 16 369 1179
+<< labels >>
+rlabel metal2 14 526 39 552 1 in
+rlabel metal2 823 529 848 555 1 out
+rlabel metal1 418 1060 443 1086 1 avdd1p8
+rlabel metal1 418 49 443 75 1 avss1p8
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/clock_inverter.mag b/mag/afernandez_residue_amplifier/clock_inverter.mag
new file mode 100644
index 0000000..426331d
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/clock_inverter.mag
@@ -0,0 +1,89 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623799048
+<< metal1 >>
+rect 520 2998 530 3028
+rect 0 2944 530 2998
+rect 520 2914 530 2944
+rect 714 2998 724 3028
+rect 714 2944 1244 2998
+rect 714 2914 724 2944
+rect 210 2264 220 2320
+rect 334 2264 344 2320
+rect 442 2259 848 2325
+rect 1054 2070 1100 2523
+rect 0 1504 1244 1564
+rect 221 804 226 809
+rect 210 748 220 804
+rect 334 748 344 804
+rect 221 743 226 748
+rect 478 743 720 809
+rect 1094 307 1152 1328
+rect 520 124 530 154
+rect 0 70 530 124
+rect 520 40 530 70
+rect 714 124 724 154
+rect 714 70 1244 124
+rect 714 40 724 70
+<< via1 >>
+rect 530 2914 714 3028
+rect 220 2264 334 2320
+rect 220 748 334 804
+rect 530 40 714 154
+<< metal2 >>
+rect 530 3028 714 3038
+rect 530 2904 714 2914
+rect 220 2320 334 2330
+rect 220 2254 334 2264
+rect 220 804 334 814
+rect 220 738 334 748
+rect 530 154 714 164
+rect 530 30 714 40
+<< via2 >>
+rect 530 2914 714 3028
+rect 220 2264 334 2320
+rect 220 748 334 804
+rect 530 40 714 154
+<< metal3 >>
+rect 520 3028 724 3033
+rect 520 2914 530 3028
+rect 714 2914 724 3028
+rect 520 2909 724 2914
+rect 210 2320 344 2325
+rect 210 2264 220 2320
+rect 334 2264 344 2320
+rect 210 2259 344 2264
+rect 247 809 307 2259
+rect 210 804 344 809
+rect 210 748 220 804
+rect 334 748 344 804
+rect 210 743 344 748
+rect 586 159 658 2909
+rect 520 154 724 159
+rect 520 40 530 154
+rect 714 40 724 154
+rect 520 35 724 40
+use inverter_cp_x1 *inverter_cp_x1_1
+timestamp 1623798692
+transform 1 0 0 0 1 2292
+box 0 -758 622 776
+use inverter_cp_x1 *inverter_cp_x1_2
+timestamp 1623798692
+transform 1 0 622 0 1 2292
+box 0 -758 622 776
+use inverter_cp_x1 *inverter_cp_x1_0
+timestamp 1623798692
+transform 1 0 0 0 -1 776
+box 0 -758 622 776
+use trans_gate *trans_gate_0
+timestamp 1623610677
+transform 1 0 675 0 -1 723
+box -53 -811 569 723
+<< labels >>
+rlabel metal1 0 1504 1244 1564 1 vss
+rlabel metal1 0 2944 1244 2998 1 vdd
+rlabel metal3 247 1504 307 1564 1 CLK
+rlabel metal1 1054 2070 1100 2523 1 CLK_d
+rlabel metal1 1094 307 1152 1328 1 nCLK_d
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/delay_cell_buff.mag b/mag/afernandez_residue_amplifier/delay_cell_buff.mag
new file mode 100644
index 0000000..2902697
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/delay_cell_buff.mag
@@ -0,0 +1,480 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624063007
+<< nwell >>
+rect 10300 1147 10722 1823
+rect 11303 1155 11816 1904
+<< pwell >>
+rect 10298 1904 10482 2452
+rect 11528 2270 11816 2452
+rect 11242 1904 11816 2270
+rect 10298 1877 10648 1904
+rect 10318 1823 10648 1877
+<< metal1 >>
+rect 10332 2463 10476 2601
+rect -54 2372 10476 2463
+rect 11492 2452 11816 2601
+rect -54 2280 -44 2372
+rect 28 2326 10476 2372
+rect 28 2280 38 2326
+rect 9123 2320 10476 2326
+rect -54 2186 4 2280
+rect 10851 1913 10861 1976
+rect 10949 1913 10959 1976
+rect 11052 1794 11062 1877
+rect 11150 1794 11160 1877
+rect 11281 1867 11816 1981
+rect 547 1684 557 1756
+rect 618 1684 628 1756
+rect 1073 1684 1083 1756
+rect 1144 1684 1154 1756
+rect 2021 1684 2031 1756
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+rect 9262 1224 10655 1239
+rect 32 1218 57 1220
+rect 328 1218 10655 1224
+rect 0 1190 10655 1218
+rect 11366 1190 11816 1338
+rect 0 1136 11816 1190
+rect 328 1130 10655 1136
+rect -7 141 9 168
+rect -7 49 3 141
+rect 75 49 85 141
+rect -7 28 9 49
+<< via1 >>
+rect -44 2280 28 2372
+rect 10861 1913 10949 1976
+rect 11062 1794 11150 1877
+rect 557 1684 618 1756
+rect 1083 1684 1144 1756
+rect 2031 1684 2092 1756
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+rect 7927 1684 7988 1756
+rect 8453 1684 8514 1756
+rect 9401 1684 9462 1756
+rect 9927 1684 9988 1756
+rect 3 49 75 141
+<< metal2 >>
+rect 62 2537 1547 2538
+rect 62 2486 5975 2537
+rect -44 2372 28 2382
+rect -208 2280 -44 2365
+rect -208 2278 28 2280
+rect -208 124 -124 2278
+rect -44 2270 28 2278
+rect 15 1812 23 1838
+rect 62 1826 114 2486
+rect 1495 2485 5975 2486
+rect 62 1812 79 1826
+rect 1495 1811 1547 2485
+rect 2972 2330 3043 2340
+rect 2972 2246 3043 2256
+rect 2981 1839 3033 2246
+rect 2973 1813 3033 1839
+rect 4451 1837 4503 2485
+rect 2981 1812 3033 1813
+rect 4436 1814 4503 1837
+rect 5923 1817 5975 2485
+rect 7396 2514 7467 2524
+rect 7396 2420 7467 2430
+rect 7404 1836 7456 2420
+rect 4436 1811 4461 1814
+rect 5923 1811 5948 1817
+rect 7388 1813 7456 1836
+rect 7388 1810 7413 1813
+rect 8879 1810 8931 2443
+rect 10861 1976 10949 1986
+rect 10133 1970 10134 1973
+rect 10087 1924 10861 1970
+rect 10087 1804 10133 1924
+rect 10861 1903 10949 1913
+rect 11062 1877 11150 1887
+rect 11062 1784 11150 1794
+rect 557 1756 618 1766
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+rect 1083 1756 1144 1766
+rect 1083 1674 1144 1684
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+rect 5505 1674 5566 1684
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+rect 6453 1674 6514 1684
+rect 6979 1756 7040 1766
+rect 6979 1674 7040 1684
+rect 7927 1756 7988 1766
+rect 7927 1674 7988 1684
+rect 8453 1756 8514 1766
+rect 8453 1674 8514 1684
+rect 9401 1756 9462 1766
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+rect 9927 1756 9988 1766
+rect 9927 1674 9988 1684
+rect 11073 1409 11133 1784
+rect 10952 1349 11133 1409
+rect 10952 756 11012 1349
+rect 10952 682 11012 692
+rect 19 559 80 569
+rect 19 493 80 503
+rect 1671 559 1732 569
+rect 3348 559 3409 569
+rect 1732 518 1751 544
+rect 1671 493 1732 503
+rect 5035 559 5096 569
+rect 3421 520 3446 546
+rect 3348 493 3409 503
+rect 6725 559 6786 569
+rect 5106 519 5131 545
+rect 5035 493 5096 503
+rect 8413 559 8474 569
+rect 6790 520 6815 546
+rect 6725 493 6786 503
+rect 10098 559 10159 569
+rect 11744 567 11805 569
+rect 8481 514 8506 540
+rect 8413 493 8474 503
+rect 11726 559 11805 567
+rect 11726 552 11744 559
+rect 10168 516 10193 542
+rect 10098 493 10159 503
+rect 11727 503 11744 510
+rect 11727 495 11805 503
+rect 11744 493 11805 495
+rect 3 141 75 151
+rect -208 49 3 124
+rect -208 40 75 49
+rect 3 39 75 40
+<< via2 >>
+rect 2972 2256 3043 2330
+rect 7396 2430 7467 2514
+rect 557 1684 618 1756
+rect 1083 1684 1144 1756
+rect 2031 1684 2092 1756
+rect 2557 1684 2618 1756
+rect 3505 1684 3566 1756
+rect 4031 1684 4092 1756
+rect 4979 1684 5040 1756
+rect 5505 1684 5566 1756
+rect 6453 1684 6514 1756
+rect 6979 1684 7040 1756
+rect 7927 1684 7988 1756
+rect 8453 1684 8514 1756
+rect 9401 1684 9462 1756
+rect 9927 1684 9988 1756
+rect 10952 692 11012 756
+rect 19 503 80 559
+rect 1671 503 1732 559
+rect 3348 503 3409 559
+rect 5035 503 5096 559
+rect 6725 503 6786 559
+rect 8413 503 8474 559
+rect 10098 503 10159 559
+rect 11744 503 11805 559
+<< metal3 >>
+rect 2981 2514 7477 2553
+rect 2981 2493 7396 2514
+rect 2981 2335 3041 2493
+rect 7386 2430 7396 2493
+rect 7467 2430 7477 2514
+rect 7386 2425 7477 2430
+rect 2962 2330 3053 2335
+rect 2962 2256 2972 2330
+rect 3043 2256 3053 2330
+rect 2962 2251 3053 2256
+rect 4497 2265 7957 2337
+rect 1632 2014 3218 2086
+rect 1632 1925 1704 2014
+rect 1171 1853 1704 1925
+rect 2753 1859 2903 1919
+rect 2782 1848 2903 1859
+rect 525 1756 628 1761
+rect 525 1684 557 1756
+rect 618 1684 628 1756
+rect 525 1679 628 1684
+rect 1054 1756 1154 1761
+rect 1054 1684 1083 1756
+rect 1144 1684 1154 1756
+rect 1054 1679 1154 1684
+rect 2021 1756 2102 1761
+rect 2021 1684 2031 1756
+rect 2092 1684 2102 1756
+rect 2021 1679 2102 1684
+rect 2547 1756 2628 1761
+rect 2547 1684 2557 1756
+rect 2618 1684 2628 1756
+rect 2547 1679 2628 1684
+rect 525 1183 585 1679
+rect 26 1123 585 1183
+rect 1054 1173 1114 1679
+rect 26 564 86 1123
+rect 1054 1113 1725 1173
+rect 1665 564 1725 1113
+rect 2031 699 2091 1679
+rect 2564 867 2624 1679
+rect 2843 1536 2903 1848
+rect 3146 1769 3218 2014
+rect 4497 1925 4569 2265
+rect 6173 2039 7718 2111
+rect 6173 1925 6245 2039
+rect 4119 1853 4569 1925
+rect 5593 1853 6245 1925
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+rect 3146 1761 3560 1769
+rect 3146 1756 3576 1761
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+rect 9902 1684 9927 1748
+rect 9988 1684 9998 1756
+rect 9902 1679 9998 1684
+rect 9902 1554 9974 1679
+rect 8773 1482 9974 1554
+rect 6980 1275 10476 1335
+rect 6465 1090 10166 1150
+rect 5525 890 8474 950
+rect 5345 749 6788 809
+rect 6728 564 6788 749
+rect 8414 564 8474 890
+rect 10106 564 10166 1090
+rect 10416 931 10476 1275
+rect 10416 871 11810 931
+rect 10942 756 11022 761
+rect 10942 692 10952 756
+rect 11012 692 11022 756
+rect 10942 687 11022 692
+rect 9 563 90 564
+rect 9 559 145 563
+rect 9 503 19 559
+rect 80 503 145 559
+rect 9 498 145 503
+rect 1661 559 1742 564
+rect 1661 503 1671 559
+rect 1732 503 1742 559
+rect 1661 498 1742 503
+rect 3338 559 3419 564
+rect 3338 503 3348 559
+rect 3409 503 3419 559
+rect 3338 498 3419 503
+rect 5025 559 5106 564
+rect 5025 503 5035 559
+rect 5096 503 5106 559
+rect 5025 498 5106 503
+rect 6715 559 6796 564
+rect 6715 503 6725 559
+rect 6786 503 6796 559
+rect 6715 498 6796 503
+rect 8403 559 8484 564
+rect 8403 503 8413 559
+rect 8474 503 8484 559
+rect 8403 498 8484 503
+rect 10088 559 10169 564
+rect 10088 503 10098 559
+rect 10159 503 10169 559
+rect 10088 498 10169 503
+rect 85 112 145 498
+rect 10952 112 11012 687
+rect 11750 564 11810 871
+rect 11734 559 11815 564
+rect 11734 503 11744 559
+rect 11805 503 11815 559
+rect 11734 498 11815 503
+rect 85 52 11012 112
+use mux_2to1_logic mux_2to1_logic_1
+timestamp 1624063007
+transform 1 0 1949 0 -1 1770
+box -475 -633 999 607
+use mux_2to1_logic mux_2to1_logic_0
+timestamp 1624063007
+transform 1 0 475 0 -1 1770
+box -475 -633 999 607
+use buffer_no_inv_x05 buffer_no_inv_x05_0
+timestamp 1624038785
+transform 1 0 -10 0 1 -10
+box 10 10 854 1173
+use buffer_no_inv_x05 buffer_no_inv_x05_1
+timestamp 1624038785
+transform 1 0 834 0 1 -10
+box 10 10 854 1173
+use mux_2to1_logic mux_2to1_logic_2
+timestamp 1624063007
+transform 1 0 3423 0 -1 1770
+box -475 -633 999 607
+use buffer_no_inv_x05 buffer_no_inv_x05_2
+timestamp 1624038785
+transform 1 0 1678 0 1 -10
+box 10 10 854 1173
+use buffer_no_inv_x05 buffer_no_inv_x05_3
+timestamp 1624038785
+transform 1 0 2522 0 1 -10
+box 10 10 854 1173
+use mux_2to1_logic mux_2to1_logic_3
+timestamp 1624063007
+transform 1 0 4897 0 -1 1770
+box -475 -633 999 607
+use buffer_no_inv_x05 buffer_no_inv_x05_4
+timestamp 1624038785
+transform 1 0 3366 0 1 -10
+box 10 10 854 1173
+use buffer_no_inv_x05 buffer_no_inv_x05_5
+timestamp 1624038785
+transform 1 0 4210 0 1 -10
+box 10 10 854 1173
+use mux_2to1_logic mux_2to1_logic_4
+timestamp 1624063007
+transform 1 0 6371 0 -1 1770
+box -475 -633 999 607
+use buffer_no_inv_x05 buffer_no_inv_x05_6
+timestamp 1624038785
+transform 1 0 5054 0 1 -10
+box 10 10 854 1173
+use mux_2to1_logic mux_2to1_logic_5
+timestamp 1624063007
+transform 1 0 7845 0 -1 1770
+box -475 -633 999 607
+use buffer_no_inv_x05 buffer_no_inv_x05_7
+timestamp 1624038785
+transform 1 0 5898 0 1 -10
+box 10 10 854 1173
+use buffer_no_inv_x05 buffer_no_inv_x05_8
+timestamp 1624038785
+transform 1 0 6742 0 1 -10
+box 10 10 854 1173
+use mux_2to1_logic mux_2to1_logic_6
+timestamp 1624063007
+transform 1 0 9319 0 -1 1770
+box -475 -633 999 607
+use buffer_no_inv_x05 buffer_no_inv_x05_9
+timestamp 1624038785
+transform 1 0 7586 0 1 -10
+box 10 10 854 1173
+use buffer_no_inv_x05 buffer_no_inv_x05_10
+timestamp 1624038785
+transform 1 0 8430 0 1 -10
+box 10 10 854 1173
+use buffer_no_inv_x05 buffer_no_inv_x05_11
+timestamp 1624038785
+transform 1 0 9274 0 1 -10
+box 10 10 854 1173
+use buffer_no_inv_x05 buffer_no_inv_x05_12
+timestamp 1624038785
+transform 1 0 10118 0 1 -10
+box 10 10 854 1173
+use buffer_no_inv_x05 buffer_no_inv_x05_13
+timestamp 1624038785
+transform 1 0 10962 0 1 -10
+box 10 10 854 1173
+use nand_logic nand_logic_0
+timestamp 1623952422
+transform 1 0 10695 0 -1 1870
+box -219 -731 833 707
+<< labels >>
+rlabel via2 30 516 55 542 1 clk
+rlabel metal2 8893 2121 8918 2147 1 reg0
+rlabel metal3 6059 2508 6084 2534 1 reg1
+rlabel metal2 80 2501 105 2527 1 reg2
+rlabel metal1 11745 1919 11770 1945 1 clk_out
+rlabel metal1 271 2383 296 2409 1 avss1p8
+rlabel metal1 32 1194 57 1220 1 avdd1p8
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/inverter_cp_x1.mag b/mag/afernandez_residue_amplifier/inverter_cp_x1.mag
new file mode 100644
index 0000000..9863834
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/inverter_cp_x1.mag
@@ -0,0 +1,87 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623798692
+<< nwell >>
+rect 0 688 622 776
+<< pwell >>
+rect 2 -669 622 -626
+rect 0 -721 622 -669
+rect 2 -722 622 -721
+rect 0 -758 622 -722
+<< psubdiff >>
+rect 108 -722 132 -688
+rect 490 -722 514 -688
+<< nsubdiff >>
+rect 108 706 132 740
+rect 490 706 514 740
+<< psubdiffcont >>
+rect 132 -722 490 -688
+<< nsubdiffcont >>
+rect 132 706 490 740
+<< poly >>
+rect 278 33 344 188
+rect 210 17 344 33
+rect 210 -17 226 17
+rect 328 -17 344 17
+rect 210 -33 344 -17
+rect 278 -184 344 -33
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+timestamp 1623610677
+transform 1 0 311 0 1 -335
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+<< end >>
diff --git a/mag/afernandez_residue_amplifier/inverter_min.mag b/mag/afernandez_residue_amplifier/inverter_min.mag
new file mode 100644
index 0000000..d901dd2
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/inverter_min.mag
@@ -0,0 +1,87 @@
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+port 4 n
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/inverter_min_x16.mag b/mag/afernandez_residue_amplifier/inverter_min_x16.mag
new file mode 100644
index 0000000..04c5dfd
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/inverter_min_x16.mag
@@ -0,0 +1,122 @@
+magic
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diff --git a/mag/afernandez_residue_amplifier/inverter_min_x4.mag b/mag/afernandez_residue_amplifier/inverter_min_x4.mag
new file mode 100644
index 0000000..d177d97
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/inverter_min_x4.mag
@@ -0,0 +1,92 @@
+magic
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+timestamp 1623431064
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+<< end >>
diff --git a/mag/afernandez_residue_amplifier/iref_ctrl_res_amp.mag b/mag/afernandez_residue_amplifier/iref_ctrl_res_amp.mag
new file mode 100644
index 0000000..aa1322b
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/iref_ctrl_res_amp.mag
@@ -0,0 +1,420 @@
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+use sky130_fd_pr__nfet_01v8_lvt_72JNYZ sky130_fd_pr__nfet_01v8_lvt_72JNYZ_1
+timestamp 1624032293
+transform 1 0 539 0 1 -263
+box -311 -310 311 310
+use sky130_fd_pr__nfet_01v8_lvt_72JNYZ sky130_fd_pr__nfet_01v8_lvt_72JNYZ_0
+timestamp 1624032293
+transform 1 0 539 0 1 251
+box -311 -310 311 310
+use sky130_fd_pr__nfet_01v8_lvt_B2JNY3 sky130_fd_pr__nfet_01v8_lvt_B2JNY3_1
+timestamp 1623958660
+transform 1 0 1523 0 1 -263
+box -359 -310 359 310
+use sky130_fd_pr__nfet_01v8_lvt_B2JNY3 sky130_fd_pr__nfet_01v8_lvt_B2JNY3_0
+timestamp 1623958660
+transform 1 0 1523 0 1 251
+box -359 -310 359 310
+use sky130_fd_pr__nfet_01v8_lvt_MVT43V sky130_fd_pr__nfet_01v8_lvt_MVT43V_1
+timestamp 1623958102
+transform 1 0 1007 0 1 -263
+box -263 -310 263 310
+use sky130_fd_pr__nfet_01v8_lvt_MVT43V sky130_fd_pr__nfet_01v8_lvt_MVT43V_0
+timestamp 1623958102
+transform 1 0 1007 0 1 251
+box -263 -310 263 310
+use sky130_fd_pr__nfet_01v8_lvt_NMSMYT sky130_fd_pr__nfet_01v8_lvt_NMSMYT_1
+timestamp 1623958459
+transform 1 0 2327 0 1 -263
+box -551 -310 551 310
+use sky130_fd_pr__nfet_01v8_lvt_NMSMYT sky130_fd_pr__nfet_01v8_lvt_NMSMYT_0
+timestamp 1623958459
+transform 1 0 2327 0 1 251
+box -551 -310 551 310
+use sky130_fd_pr__pfet_01v8_XACJHL sky130_fd_pr__pfet_01v8_XACJHL_0
+timestamp 1624020979
+transform -1 0 554 0 1 880
+box -263 -319 263 319
+use sky130_fd_pr__pfet_01v8_XAYTAL sky130_fd_pr__pfet_01v8_XAYTAL_0
+timestamp 1623959550
+transform -1 0 1022 0 1 880
+box -311 -319 311 319
+<< labels >>
+rlabel via1 1258 1198 1292 1233 1 avdd1p8
+rlabel via1 -540 -584 -506 -549 1 avss1p8
+rlabel metal1 168 388 202 423 1 iref
+rlabel metal2 739 441 773 476 1 vctrl
+rlabel metal3 1215 9 1249 44 1 reg0
+rlabel metal3 1819 10 1853 45 1 reg1
+rlabel metal3 2809 13 2843 48 1 reg2
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/latch_diff.mag b/mag/afernandez_residue_amplifier/latch_diff.mag
new file mode 100644
index 0000000..dc7c2ec
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/latch_diff.mag
@@ -0,0 +1,251 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623798783
+<< nwell >>
+rect -33 2264 526 2352
+rect -33 2261 525 2264
+rect -33 2137 307 2261
+rect -33 1900 340 2137
+rect -33 1576 526 1900
+rect -33 -1 526 60
+rect -33 -628 0 -1
+rect -33 -716 526 -628
+<< pwell >>
+rect -33 1030 0 1576
+rect -33 967 503 1030
+rect -33 669 526 967
+rect -33 668 503 669
+rect -33 60 0 668
+<< psubdiff >>
+rect 36 1506 434 1540
+rect 36 563 70 1027
+rect 453 1002 555 1036
+rect 424 600 633 634
+rect 36 130 70 182
+rect 36 96 613 130
+<< nsubdiff >>
+rect 107 2282 131 2316
+rect 393 2282 417 2316
+rect 108 -680 132 -646
+rect 394 -680 418 -646
+<< nsubdiffcont >>
+rect 131 2282 393 2316
+rect 132 -680 394 -646
+<< poly >>
+rect 99 1807 230 1824
+rect 99 1773 124 1807
+rect 192 1773 230 1807
+rect 99 1758 230 1773
+rect 296 -137 427 -122
+rect 296 -171 334 -137
+rect 402 -171 427 -137
+rect 296 -188 427 -171
+<< polycont >>
+rect 124 1773 192 1807
+rect 334 -171 402 -137
+<< locali >>
+rect 108 1773 124 1807
+rect 192 1773 208 1807
+rect 70 1506 434 1540
+rect 70 96 434 130
+rect 318 -171 334 -137
+rect 402 -171 418 -137
+<< viali >>
+rect 36 2282 131 2316
+rect 131 2282 393 2316
+rect 393 2282 490 2316
+rect 36 2194 490 2228
+rect 124 1773 192 1807
+rect 36 1036 70 1540
+rect 36 1002 555 1036
+rect 36 634 70 1002
+rect 36 600 1077 634
+rect 36 96 70 600
+rect 434 96 1112 130
+rect 334 -171 402 -137
+rect 36 -592 490 -558
+rect 36 -680 132 -646
+rect 132 -680 394 -646
+rect 394 -680 490 -646
+<< metal1 >>
+rect -33 2316 526 2322
+rect -33 2282 36 2316
+rect 490 2282 526 2316
+rect -33 2228 526 2282
+rect -33 2194 36 2228
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+rect -33 2188 526 2194
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+rect -33 -558 526 -552
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+rect -33 -646 526 -592
+rect -33 -680 36 -646
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+rect -33 -686 526 -680
+<< via1 >>
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+rect 237 1547 289 1651
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+rect 237 -15 289 89
+rect 332 -137 414 -125
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+rect 402 -171 414 -137
+rect 332 -177 414 -171
+<< metal2 >>
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+rect 237 1537 289 1547
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+rect 719 281 859 511
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+rect 130 94 186 104
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+rect 237 89 289 99
+rect 186 7 237 66
+rect 130 -26 186 -17
+rect 237 -25 289 -15
+rect 312 -122 424 -112
+rect 312 -188 424 -178
+<< via2 >>
+rect 102 1813 214 1814
+rect 102 1761 112 1813
+rect 112 1761 194 1813
+rect 194 1761 214 1813
+rect 102 1758 214 1761
+rect 340 1542 396 1653
+rect 497 1211 553 1323
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+rect 130 -17 186 94
+rect 312 -125 424 -122
+rect 312 -177 332 -125
+rect 332 -177 414 -125
+rect 414 -177 424 -125
+rect 312 -178 424 -177
+<< metal3 >>
+rect 92 1814 224 1819
+rect 92 1758 102 1814
+rect 214 1758 224 1814
+rect 92 1753 224 1758
+rect 128 99 188 1753
+rect 330 1653 406 1658
+rect 330 1542 340 1653
+rect 396 1542 406 1653
+rect 330 1537 406 1542
+rect 120 94 196 99
+rect 120 -17 130 94
+rect 186 -17 196 94
+rect 120 -22 196 -17
+rect 338 -117 398 1537
+rect 495 1328 555 1333
+rect 487 1323 563 1328
+rect 487 1211 497 1323
+rect 553 1211 563 1323
+rect 487 1206 563 1211
+rect 495 399 555 1206
+rect 460 394 592 399
+rect 460 338 470 394
+rect 582 338 592 394
+rect 460 333 592 338
+rect 495 323 555 333
+rect 302 -122 434 -117
+rect 302 -178 312 -122
+rect 424 -178 434 -122
+rect 302 -183 434 -178
+use sky130_fd_pr__nfet_01v8_2BS854 sky130_fd_pr__nfet_01v8_2BS854_0
+timestamp 1623795754
+transform 1 0 836 0 1 395
+box -311 -335 311 335
+use sky130_fd_pr__pfet_01v8_MJG8BZ sky130_fd_pr__pfet_01v8_MJG8BZ_0
+timestamp 1623610677
+transform 1 0 263 0 1 1950
+box -263 -314 263 314
+use sky130_fd_pr__pfet_01v8_MJG8BZ *sky130_fd_pr__pfet_01v8_MJG8BZ_1
+timestamp 1623610677
+transform -1 0 263 0 -1 -314
+box -263 -314 263 314
+use sky130_fd_pr__nfet_01v8_KU9PSX *sky130_fd_pr__nfet_01v8_KU9PSX_1
+timestamp 1623610677
+transform 1 0 263 0 1 1271
+box -263 -305 263 305
+use sky130_fd_pr__nfet_01v8_KU9PSX *sky130_fd_pr__nfet_01v8_KU9PSX_0
+timestamp 1623610677
+transform 1 0 263 0 -1 365
+box -263 -305 263 305
+<< labels >>
+rlabel metal1 -33 654 36 982 1 vss
+rlabel metal1 -33 2228 526 2282 1 vdd
+rlabel metal3 128 94 188 1758 1 Q
+rlabel metal3 338 -122 398 1542 1 nQ
+rlabel metal1 198 1104 328 1138 1 D
+rlabel metal1 198 498 328 532 1 nD
+rlabel metal1 -33 -646 526 -592 1 vdd
+rlabel metal1 714 192 954 232 1 CLK
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/mux_2to1_logic.mag b/mag/afernandez_residue_amplifier/mux_2to1_logic.mag
new file mode 100644
index 0000000..afedecd
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/mux_2to1_logic.mag
@@ -0,0 +1,170 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624063007
+<< nwell >>
+rect -475 579 -53 607
+rect 64 537 341 571
+rect 509 537 963 571
+<< pwell >>
+rect -53 -584 -1 -53
+rect -475 -633 -1 -584
+rect 421 -633 525 -53
+rect 561 -597 911 -563
+rect 947 -633 999 -53
+<< psubdiff >>
+rect 109 -597 133 -563
+rect 291 -597 315 -563
+rect 561 -597 659 -563
+rect 817 -597 911 -563
+<< nsubdiff >>
+rect 509 537 590 571
+rect 867 537 963 571
+<< psubdiffcont >>
+rect 133 -597 291 -563
+rect 659 -597 817 -563
+<< nsubdiffcont >>
+rect 64 537 341 571
+rect 590 537 867 571
+<< poly >>
+rect 123 419 297 485
+rect 649 423 823 489
+<< viali >>
+rect -17 537 64 571
+rect 64 537 341 571
+rect 341 537 437 571
+rect 509 537 590 571
+rect 590 537 867 571
+rect 867 537 963 571
+rect 35 -597 133 -563
+rect 133 -597 291 -563
+rect 291 -597 385 -563
+rect 561 -597 659 -563
+rect 659 -597 817 -563
+rect 817 -597 911 -563
+<< metal1 >>
+rect -475 571 999 607
+rect -475 537 -17 571
+rect 437 537 509 571
+rect 963 537 999 571
+rect -57 531 999 537
+rect 138 425 148 477
+rect 268 425 278 477
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+rect 94 170 137 178
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+rect -475 -557 -53 -554
+rect -475 -563 999 -557
+rect -475 -597 35 -563
+rect 385 -597 561 -563
+rect 911 -597 999 -563
+rect -475 -633 999 -597
+<< via1 >>
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+rect 181 178 239 242
+rect 231 -277 289 -213
+rect 707 178 765 242
+rect 757 -277 815 -213
+rect 177 -505 236 -453
+rect 703 -504 762 -452
+<< metal2 >>
+rect 148 477 268 487
+rect -76 425 148 477
+rect 268 425 522 477
+rect -76 116 -24 425
+rect 148 415 268 425
+rect 181 242 239 252
+rect 181 168 239 178
+rect -294 64 -24 116
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+rect -294 -27 -242 64
+rect -345 -79 -242 -27
+rect -105 -79 7 -27
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+rect 703 -450 762 -442
+rect 470 -452 762 -450
+rect 470 -502 703 -452
+rect 177 -515 236 -505
+rect 703 -514 762 -504
+<< via2 >>
+rect 242 -155 303 -83
+rect 768 -155 829 -83
+<< metal3 >>
+rect 232 -83 313 -78
+rect 758 -83 839 -78
+rect 232 -155 242 -83
+rect 303 -155 768 -83
+rect 829 -155 839 -83
+rect 232 -160 313 -155
+rect 758 -160 839 -155
+use sky130_fd_pr__pfet_01v8_XA7ZMQ sky130_fd_pr__pfet_01v8_XA7ZMQ_0
+timestamp 1623900471
+transform 1 0 210 0 1 277
+box -263 -330 263 330
+use inverter_min inverter_min_0
+timestamp 1624038681
+transform 1 0 -422 0 1 -600
+box -53 16 369 1179
+use sky130_fd_pr__nfet_01v8_HAN8QX sky130_fd_pr__nfet_01v8_HAN8QX_1
+timestamp 1623900471
+transform 1 0 736 0 -1 -343
+box -211 -290 211 290
+use sky130_fd_pr__pfet_01v8_XA7ZMQ sky130_fd_pr__pfet_01v8_XA7ZMQ_1
+timestamp 1623900471
+transform 1 0 736 0 1 277
+box -263 -330 263 330
+use sky130_fd_pr__nfet_01v8_HAN8QX sky130_fd_pr__nfet_01v8_HAN8QX_0
+timestamp 1623900471
+transform 1 0 210 0 -1 -343
+box -211 -290 211 290
+<< labels >>
+rlabel metal2 -332 -64 -311 -46 1 sel
+rlabel metal2 -94 -63 -73 -45 1 sel_b
+rlabel metal1 152 -61 173 -43 1 DinA
+rlabel metal1 681 -62 702 -44 1 DinB
+rlabel via2 786 -132 807 -114 1 out
+rlabel metal1 -390 563 -366 588 1 avdd1p8
+rlabel metal1 -310 -612 -286 -587 1 avss1p8
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/nand_logic.mag b/mag/afernandez_residue_amplifier/nand_logic.mag
new file mode 100644
index 0000000..c125dc5
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/nand_logic.mag
@@ -0,0 +1,117 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623952422
+<< nwell >>
+rect -47 532 671 707
+<< pwell >>
+rect -219 -731 833 -583
+<< psubdiff >>
+rect -111 -716 -87 -682
+rect 175 -716 199 -682
+rect 415 -716 439 -682
+rect 701 -716 725 -682
+<< nsubdiff >>
+rect -11 632 85 666
+rect 539 632 635 666
+<< psubdiffcont >>
+rect -87 -716 175 -682
+rect 439 -716 701 -682
+<< nsubdiffcont >>
+rect 85 632 539 666
+<< poly >>
+rect 162 106 200 114
+rect 162 -54 260 106
+rect 162 -98 180 -54
+rect 246 -98 260 -54
+rect 162 -156 260 -98
+rect 61 -220 260 -156
+rect 125 -222 260 -220
+rect 361 55 459 105
+rect 361 10 377 55
+rect 443 10 459 55
+rect 361 -156 459 10
+rect 361 -158 497 -156
+rect 361 -222 553 -158
+<< polycont >>
+rect 180 -98 246 -54
+rect 377 10 443 55
+<< viali >>
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+rect 85 632 539 666
+rect 539 632 635 666
+rect -11 538 635 572
+rect 361 55 459 71
+rect 361 10 377 55
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+rect 361 -5 459 10
+rect 162 -54 260 -38
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+rect 162 -114 260 -98
+rect -87 -622 701 -588
+rect -183 -716 -87 -682
+rect -87 -716 175 -682
+rect 175 -716 439 -682
+rect 439 -716 701 -682
+rect 701 -716 797 -682
+<< metal1 >>
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+rect -47 632 -11 666
+rect 635 632 671 666
+rect -47 572 671 632
+rect -47 538 -11 572
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+rect 701 -622 833 -588
+rect -219 -682 833 -622
+rect -219 -716 -183 -682
+rect 797 -716 833 -682
+rect -219 -731 833 -716
+use sky130_fd_pr__nfet_01v8_XRJ78J sky130_fd_pr__nfet_01v8_XRJ78J_1
+timestamp 1623948006
+transform -1 0 570 0 1 -346
+box -263 -312 263 312
+use sky130_fd_pr__nfet_01v8_XRJ78J sky130_fd_pr__nfet_01v8_XRJ78J_0
+timestamp 1623948006
+transform 1 0 44 0 1 -346
+box -263 -312 263 312
+use sky130_fd_pr__pfet_01v8_75PKJG sky130_fd_pr__pfet_01v8_75PKJG_0
+timestamp 1623948006
+transform 1 0 312 0 1 287
+box -359 -321 359 321
+<< labels >>
+rlabel viali 211 -101 242 -62 1 in1
+rlabel metal1 554 -86 585 -47 1 out
+rlabel metal1 255 -671 286 -632 1 avss1p8
+rlabel metal1 289 584 320 623 1 avdd1p8
+rlabel metal1 395 15 426 54 1 in2
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/res_amp_lin.mag b/mag/afernandez_residue_amplifier/res_amp_lin.mag
new file mode 100644
index 0000000..a93a9a7
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/res_amp_lin.mag
@@ -0,0 +1,1648 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624396448
+<< nwell >>
+rect 1572 6 4828 915
+rect 2386 -596 4828 6
+rect 1572 -1234 4828 -596
+<< pwell >>
+rect 3200 -1325 3622 -1321
+rect 1572 -1398 4828 -1325
+rect 1572 -1504 2930 -1398
+rect 3054 -1504 4828 -1398
+rect 1572 -2058 4828 -1504
+<< pmos >>
+rect 2586 -377 2616 -177
+rect 2682 -377 2712 -177
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+rect 2874 -377 2904 -177
+rect 2970 -377 3000 -177
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+rect 4406 -1015 4436 -815
+rect 4502 -1015 4532 -815
+rect 4598 -1015 4628 -815
+<< nmoslvt >>
+rect 3396 -1631 3426 -1531
+<< ndiff >>
+rect 3338 -1543 3396 -1531
+rect 3338 -1619 3350 -1543
+rect 3384 -1619 3396 -1543
+rect 3338 -1631 3396 -1619
+rect 3426 -1543 3484 -1531
+rect 3426 -1619 3438 -1543
+rect 3472 -1619 3484 -1543
+rect 3426 -1631 3484 -1619
+<< pdiff >>
+rect 3747 449 3813 461
+rect 3747 273 3763 449
+rect 3797 273 3813 449
+rect 3747 261 3813 273
+rect 3939 449 4005 461
+rect 3939 273 3955 449
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+rect 2904 -377 2970 -365
+rect 3000 -189 3062 -177
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+timestamp 1623969232
+transform -1 0 3924 0 1 361
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+<< labels >>
+rlabel metal4 4907 -378 5109 -176 1 outp
+rlabel metal4 4907 -1016 5109 -814 1 outn
+rlabel nwell 2821 696 3536 855 1 avdd1p8
+rlabel pwell 2830 -1989 3545 -1830 1 avss1p8
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+rlabel metal2 1054 -486 1180 -418 1 inn
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+rlabel metal2 2177 505 2303 580 1 vctrl
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/res_amp_lin_prog.mag b/mag/afernandez_residue_amplifier/res_amp_lin_prog.mag
new file mode 100644
index 0000000..b32516f
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/res_amp_lin_prog.mag
@@ -0,0 +1,521 @@
+magic
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+rect 18047 8941 18286 8951
+rect 19076 9013 19160 9023
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+rect 19076 8947 19160 8957
+<< via2 >>
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+rect 15312 12327 15498 12422
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+<< metal3 >>
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+rect 17217 14062 17263 14117
+rect 18216 14056 18262 14111
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+rect 16082 13539 16088 13664
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+rect 5864 7650 5993 7651
+rect 6199 7650 6259 7696
+rect 5864 7590 6259 7650
+rect 5864 7589 5993 7590
+<< via3 >>
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+rect 15282 12327 15312 12422
+rect 15312 12327 15498 12422
+rect 19283 12001 19485 12141
+rect 19283 10325 19485 10465
+<< metal4 >>
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+rect 15284 13664 16202 13665
+rect 15284 13539 16088 13664
+rect 16201 13539 16202 13664
+rect 15284 13538 16202 13539
+rect 15284 13534 16088 13538
+rect 15284 12423 15419 13534
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+rect 15498 12327 15499 12422
+rect 15281 12326 15499 12327
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+rect 19282 10465 19486 10466
+rect 19282 10325 19283 10465
+rect 19485 10325 19486 10465
+rect 19282 10324 19486 10325
+rect 19283 10315 19485 10324
+use inverter_min_x4 inverter_min_x4_0
+timestamp 1624049879
+transform 1 0 18411 0 -1 8928
+box -53 -616 665 643
+use res_amp_lin res_amp_lin_0
+timestamp 1624396448
+transform 1 0 13177 0 1 11829
+box 1054 -2058 5121 915
+use delay_cell_buff delay_cell_buff_0
+timestamp 1624063007
+transform 1 0 6173 0 1 7077
+box -208 0 11816 2601
+use sky130_fd_pr__nfet_01v8_lvt_72JNYZ sky130_fd_pr__nfet_01v8_lvt_72JNYZ_0
+timestamp 1624032293
+transform 1 0 20195 0 -1 9465
+box -311 -310 311 310
+use sky130_fd_pr__nfet_01v8_lvt_595QY5 sky130_fd_pr__nfet_01v8_lvt_595QY5_0
+timestamp 1624030292
+transform 1 0 20214 0 1 10085
+box -407 -310 407 310
+use sky130_fd_pr__nfet_01v8_lvt_72JNYZ sky130_fd_pr__nfet_01v8_lvt_72JNYZ_1
+timestamp 1624032293
+transform 1 0 20195 0 1 13001
+box -311 -310 311 310
+use sky130_fd_pr__pfet_01v8_lvt_4L9VGG sky130_fd_pr__pfet_01v8_lvt_4L9VGG_0
+timestamp 1624030292
+transform 1 0 20217 0 1 10814
+box -487 -419 487 419
+use sky130_fd_pr__pfet_01v8_lvt_4L9VGG sky130_fd_pr__pfet_01v8_lvt_4L9VGG_1
+timestamp 1624030292
+transform 1 0 20217 0 -1 11652
+box -487 -419 487 419
+use sky130_fd_pr__nfet_01v8_lvt_595QY5 sky130_fd_pr__nfet_01v8_lvt_595QY5_1
+timestamp 1624030292
+transform 1 0 20214 0 -1 12381
+box -407 -310 407 310
+use iref_ctrl_res_amp iref_ctrl_res_amp_0
+timestamp 1624113259
+transform 1 0 15406 0 -1 14113
+box -586 -686 2888 1369
+<< labels >>
+rlabel metal2 14231 11343 14357 11411 1 inn
+rlabel metal2 14231 11055 14357 11123 1 inp
+rlabel metal3 16613 14055 16659 14110 1 iref_reg0
+rlabel metal3 17217 14062 17263 14117 1 iref_reg1
+rlabel metal3 18216 14056 18262 14111 1 iref_reg2
+rlabel metal1 17273 13693 17300 13722 1 iref
+rlabel metal3 5878 7605 5911 7634 1 clk
+rlabel metal2 6250 9575 6284 9607 1 delay_reg2
+rlabel metal3 10019 9586 10053 9618 1 delay_reg1
+rlabel metal2 15061 9475 15095 9507 1 delay_reg0
+rlabel metal2 20931 12329 20986 12376 1 outp_cap
+rlabel metal2 20931 10048 20986 10095 1 outn_cap
+rlabel metal4 18370 10891 18425 10938 1 outn
+rlabel metal4 18378 11537 18433 11584 1 outp
+rlabel metal2 14898 14658 14947 14708 1 avss1p8
+rlabel metal2 14841 12807 14890 12857 1 avdd1p8
+rlabel metal1 20157 9238 20193 9270 1 rst
+rlabel metal1 18156 8224 18193 8264 1 avdd1p8
+rlabel metal1 20155 13197 20192 13237 1 rst
+rlabel metal1 20715 11216 20746 11255 1 avdd1p8
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/res_amp_sync_v2.mag b/mag/afernandez_residue_amplifier/res_amp_sync_v2.mag
new file mode 100644
index 0000000..eefade3
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/res_amp_sync_v2.mag
@@ -0,0 +1,418 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624402156
+<< nwell >>
+rect 3636 6239 4733 7015
+rect 7538 6935 8332 7015
+rect 7509 6239 7622 6935
+rect 3666 4188 4554 4723
+rect 3666 4000 4596 4188
+rect 3666 3954 5436 4000
+rect 3666 3947 7206 3954
+rect 7538 3947 8332 4723
+rect 3666 3890 8332 3947
+rect 3666 3223 3976 3890
+rect 3665 3206 3976 3223
+rect 4556 3208 8332 3890
+rect 4553 3206 8332 3208
+rect 3665 3171 3959 3206
+rect 4553 3171 4718 3206
+rect 5436 3171 8332 3206
+rect 3638 966 4062 1655
+rect 6650 966 8332 1655
+rect 3638 877 8332 966
+rect 4054 871 8332 877
+rect 6650 103 8332 871
+rect 6650 -2189 8332 -1413
+<< pwell >>
+rect 3530 6050 4560 6239
+rect 3530 5585 4978 6050
+rect 3666 4723 4978 5585
+rect 7389 5565 8332 6239
+rect 7538 4723 8332 5565
+rect 6650 2748 8332 3171
+rect 3666 1655 8332 2748
+rect 6650 -1413 8332 103
+<< metal1 >>
+rect 682 6891 736 6945
+rect 3666 6851 4554 6985
+rect 7538 6851 8332 6985
+rect 3732 6209 3742 6289
+rect 3985 6209 3995 6289
+rect 4283 6195 4293 6273
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+rect 7604 6199 7614 6284
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+rect 3603 5645 4554 5813
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+rect 682 3917 8332 3977
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+rect 3661 3783 8332 3917
+rect 4556 3772 6572 3783
+rect 4556 3737 4734 3772
+rect 5432 3737 6572 3772
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+rect 4025 3126 4035 3217
+rect 4141 3126 4151 3217
+rect 4236 3182 4246 3262
+rect 4348 3182 4358 3262
+rect 4436 3131 4798 3211
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+rect 5994 3193 6004 3262
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+rect 4780 1695 5017 1699
+rect 4103 1615 4113 1695
+rect 4230 1615 4240 1695
+rect 4688 1615 4801 1637
+rect 6509 1621 6519 1699
+rect 6641 1621 6651 1699
+rect 682 992 842 1003
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+rect 682 847 8332 992
+rect 682 843 842 847
+rect 6650 715 8332 847
+rect 2656 -69 2666 -17
+rect 2925 -69 2935 -17
+rect 5641 -69 5651 -17
+rect 5910 -69 5920 -17
+rect 6650 -819 8332 -491
+rect 2657 -1293 2667 -1241
+rect 2926 -1293 2936 -1241
+rect 5640 -1293 5650 -1241
+rect 5909 -1293 5919 -1241
+rect 682 -2119 747 -2065
+rect 6650 -2159 8332 -2025
+<< via1 >>
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+rect 4293 6195 4460 6273
+rect 7614 6199 7857 6284
+rect 8165 6195 8332 6273
+rect 2667 6067 2926 6121
+rect 6539 6074 6798 6130
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+rect 2666 -69 2925 -17
+rect 5651 -69 5910 -17
+rect 2667 -1293 2926 -1241
+rect 5650 -1293 5909 -1241
+<< metal2 >>
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+rect 3405 6289 3985 6292
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+rect 930 4250 1002 4726
+rect 514 4178 1002 4250
+rect 516 150 585 4178
+rect 7309 3757 7381 4512
+rect 1497 3685 7381 3757
+rect 1497 3474 1569 3685
+rect 926 3402 1569 3474
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+rect 6004 3272 6126 3282
+rect 4246 3262 4348 3272
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+rect 3916 2207 5477 2265
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+rect 6519 1699 6641 1709
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+rect 4115 1016 4173 1605
+rect 4115 958 6488 1016
+rect 516 81 1027 150
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+rect 6430 138 6488 958
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+rect 5651 -7 5910 3
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+rect 2667 -1241 2926 -1231
+rect 2667 -1313 2926 -1303
+rect 5650 -1241 5909 -1231
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+<< via2 >>
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+rect 2667 6067 2926 6121
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+rect 2661 4842 2925 4895
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+rect 5650 -1293 5909 -1241
+rect 5650 -1303 5909 -1293
+<< metal3 >>
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+rect 4283 6190 4470 6195
+rect 8155 6273 8342 6278
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+rect 2926 -1313 2936 -1241
+rect 5640 -1241 5919 -1236
+rect 5640 -1313 5650 -1241
+rect 5909 -1313 5919 -1241
+<< via3 >>
+rect 2667 6131 2926 6141
+rect 2667 6067 2926 6131
+rect 128 4821 228 4895
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+rect 2661 4822 2925 4832
+rect 2667 3060 2926 3070
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+rect 2667 -1303 2926 -1241
+rect 2667 -1313 2926 -1303
+rect 5650 -1303 5909 -1241
+rect 5650 -1313 5909 -1303
+<< metal4 >>
+rect 2666 6141 2927 6142
+rect 2666 6140 2667 6141
+rect -92 6067 2667 6140
+rect 2926 6067 2927 6141
+rect -92 6066 2927 6067
+rect -92 3072 -18 6066
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+rect 2926 2999 2927 3070
+rect -92 2998 2927 2999
+rect -92 -1240 -18 2998
+rect 127 1828 229 1829
+rect 127 1754 128 1828
+rect 228 1827 2926 1828
+rect 228 1755 2666 1827
+rect 2925 1755 2926 1827
+rect 228 1754 2926 1755
+rect 127 1753 229 1754
+rect 126 4 229 5
+rect 126 -70 127 4
+rect 228 3 5911 4
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+rect 2925 -69 5651 3
+rect 5910 -69 5911 3
+rect 228 -70 5911 -69
+rect 126 -71 229 -70
+rect -92 -1241 5910 -1240
+rect -92 -1313 2667 -1241
+rect 2926 -1313 5650 -1241
+rect 5909 -1313 5910 -1241
+rect -92 -1314 5910 -1313
+use DFlipFlop DFlipFlop_4
+timestamp 1624049879
+transform 1 0 4910 0 -1 879
+box -1244 0 1740 3068
+use DFlipFlop DFlipFlop_3
+timestamp 1624049879
+transform 1 0 1926 0 -1 879
+box -1244 0 1740 3068
+use DFlipFlop DFlipFlop_2
+timestamp 1624049879
+transform 1 0 1926 0 1 879
+box -1244 0 1740 3068
+use nand_logic nand_logic_0
+timestamp 1623952422
+transform 1 0 3885 0 1 3205
+box -219 -731 833 707
+use DFlipFlop DFlipFlop_0
+timestamp 1624049879
+transform 1 0 1926 0 1 3947
+box -1244 0 1740 3068
+use inverter_min_x16 inverter_min_x16_0
+timestamp 1624046389
+transform 1 0 4833 0 -1 1602
+box -53 -616 1817 643
+use nand_logic nand_logic_1
+timestamp 1623952422
+transform 1 0 5655 0 1 3205
+box -219 -731 833 707
+use inverter_min_x4 inverter_min_x4_4
+timestamp 1624049879
+transform 1 0 4115 0 -1 1602
+box -53 -616 665 643
+use inverter_min_x4 inverter_min_x4_3
+timestamp 1624049879
+transform 1 0 6541 0 1 3224
+box -53 -616 665 643
+use inverter_min_x4 inverter_min_x4_1
+timestamp 1624049879
+transform 1 0 4771 0 1 3224
+box -53 -616 665 643
+use DFlipFlop DFlipFlop_1
+timestamp 1624049879
+transform 1 0 5798 0 1 3947
+box -1244 0 1740 3068
+use inverter_min_x4 inverter_min_x4_0
+timestamp 1624049879
+transform 1 0 3795 0 1 6292
+box -53 -616 665 643
+use inverter_min_x4 inverter_min_x4_2
+timestamp 1624049879
+transform 1 0 7667 0 1 6292
+box -53 -616 665 643
+<< labels >>
+rlabel metal1 7614 5716 8332 5771 1 vss
+rlabel metal1 7469 5317 7538 5645 5 vss
+rlabel via1 6551 1642 6601 1680 1 clk_amp
+rlabel metal4 -64 -38 -36 -5 1 clkn
+rlabel metal1 702 6909 718 6931 1 avdd1p8
+rlabel metal1 7130 3142 7183 3188 1 rst
+rlabel metal3 159 4649 206 4710 1 clkp
+rlabel metal1 7948 5421 8048 5515 1 avss1p8
+rlabel metal1 7873 2391 7973 2485 1 avss1p8
+rlabel metal1 7805 -720 7905 -626 1 avss1p8
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/res_amp_top.mag b/mag/afernandez_residue_amplifier/res_amp_top.mag
new file mode 100644
index 0000000..cf22c7f
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/res_amp_top.mag
@@ -0,0 +1,949 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624471326
+<< nwell >>
+rect 18234 4138 21604 4172
+<< pwell >>
+rect 21025 7249 22667 7283
+rect 22739 7250 26841 7284
+rect 26993 4400 27027 7051
+rect 26993 1269 27027 3920
+rect 21025 1046 22667 1080
+rect 22739 1047 26841 1081
+<< psubdiff >>
+rect 21025 7249 21121 7283
+rect 21767 7249 21925 7283
+rect 22571 7249 22667 7283
+rect 22739 7250 22835 7284
+rect 26745 7250 26841 7284
+rect 18334 5923 18358 7205
+rect 20851 5923 20875 7205
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+rect 26993 5221 27027 5379
+rect 26993 4400 27027 4447
+rect 26993 3873 27027 3920
+rect 26993 2941 27027 3099
+rect 18338 1138 18362 2420
+rect 20855 1138 20879 2420
+rect 26993 1269 27027 1331
+rect 21025 1046 21121 1080
+rect 21767 1046 21925 1080
+rect 22571 1046 22667 1080
+rect 22739 1047 22835 1081
+rect 26745 1047 26841 1081
+<< nsubdiff >>
+rect 18234 4138 18330 4172
+rect 19840 4138 19998 4172
+rect 21508 4138 21604 4172
+<< psubdiffcont >>
+rect 21121 7249 21767 7283
+rect 21925 7249 22571 7283
+rect 22835 7250 26745 7284
+rect 18358 5923 20851 7205
+rect 26993 5379 27027 6989
+rect 26993 4447 27027 5221
+rect 26993 3099 27027 3873
+rect 18362 1138 20855 2420
+rect 26993 1331 27027 2941
+rect 21121 1046 21767 1080
+rect 21925 1046 22571 1080
+rect 22835 1047 26745 1081
+<< nsubdiffcont >>
+rect 18330 4138 19840 4172
+rect 19998 4138 21508 4172
+<< locali >>
+rect 18342 5923 18358 7205
+rect 20851 5923 20867 7205
+rect 18346 1138 18362 2420
+rect 20855 1138 20871 2420
+<< viali >>
+rect 21025 7249 21121 7283
+rect 21121 7249 21767 7283
+rect 21767 7249 21925 7283
+rect 21925 7249 22571 7283
+rect 22571 7249 22667 7283
+rect 22739 7250 22835 7284
+rect 22835 7250 26745 7284
+rect 26745 7250 26841 7284
+rect 18358 5923 20851 7205
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+rect 20467 -605 28949 -165
+rect 20467 -611 20491 -605
+rect 19795 -635 20491 -611
+rect -4958 -972 -4262 -948
+use sky130_fd_pr__cap_mim_m3_1_U5ZKVF sky130_fd_pr__cap_mim_m3_1_U5ZKVF_0
+timestamp 1624471326
+transform 1 0 16786 0 1 6344
+box -700 -850 699 850
+use sky130_fd_pr__cap_mim_m3_1_U5ZKVF sky130_fd_pr__cap_mim_m3_1_U5ZKVF_1
+timestamp 1624471326
+transform 1 0 16786 0 1 1968
+box -700 -850 699 850
+use res_amp_lin_prog res_amp_lin_prog_0
+timestamp 1624397222
+transform 1 0 -5726 0 1 -7077
+box 5835 7077 21302 14799
+use res_amp_sync_v2 res_amp_sync_v2_0
+timestamp 1624397222
+transform 1 0 -899 0 1 4870
+box -92 -2189 8342 7015
+use source_follower_buff_diff source_follower_buff_diff_0
+timestamp 1624113565
+transform 1 0 17170 0 1 1168
+box 863 -174 10692 6158
+<< labels >>
+rlabel metal4 8534 12559 8597 12604 1 inn
+rlabel metal4 8060 12573 8123 12618 1 inp
+rlabel metal4 -1064 10918 -1018 10975 1 clkn
+rlabel space -742 9560 -696 9617 1 clkp
+rlabel metal4 27211 5274 27257 5331 1 outp
+rlabel metal4 27221 2994 27267 3051 1 outn
+rlabel metal4 2733 2487 2790 2523 1 delay_reg2
+rlabel metal4 9327 2414 9384 2450 1 delay_reg0
+rlabel metal4 6829 2485 6886 2521 1 delay_reg1
+rlabel metal4 10864 6953 10960 7061 1 iref_reg0
+rlabel metal4 11468 6957 11564 7065 1 iref_reg1
+rlabel metal4 12467 6950 12563 7058 1 iref_reg2
+rlabel metal5 -2784 12535 -2629 12632 1 avss1p8
+rlabel metal5 -4717 12539 -4562 12636 1 avdd1p8
+rlabel metal4 11259 6504 11353 6610 1 iref0
+rlabel via1 18986 5035 19121 5130 1 iref1
+rlabel via1 18985 3197 19120 3292 1 iref3
+rlabel metal3 21744 6516 21940 6620 1 iref2
+rlabel metal3 21745 1699 21941 1803 1 iref4
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__cap_mim_m3_1_U5ZKVF.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__cap_mim_m3_1_U5ZKVF.mag
new file mode 100644
index 0000000..51c0b09
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__cap_mim_m3_1_U5ZKVF.mag
@@ -0,0 +1,33 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624471326
+<< metal3 >>
+rect -700 822 699 850
+rect -700 -822 615 822
+rect 679 -822 699 822
+rect -700 -850 699 -822
+<< via3 >>
+rect 615 -822 679 822
+<< mimcap >>
+rect -600 710 500 750
+rect -600 -710 -560 710
+rect 460 -710 500 710
+rect -600 -750 500 -710
+<< mimcapcontact >>
+rect -560 -710 460 710
+<< metal4 >>
+rect 599 822 695 838
+rect -561 710 461 711
+rect -561 -710 -560 710
+rect 460 -710 461 710
+rect -561 -711 461 -710
+rect 599 -822 615 822
+rect 679 -822 695 822
+rect 599 -838 695 -822
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_1
+string FIXED_BBOX -700 -850 600 850
+string parameters w 5.5 l 7.5 val 87.44 carea 2.00 cperi 0.19 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_283H86.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_283H86.mag
new file mode 100644
index 0000000..4c2c16d
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_283H86.mag
@@ -0,0 +1,304 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623943772
+<< error_p >>
+rect -173 385 -115 391
+rect 19 385 77 391
+rect -173 351 -161 385
+rect 19 351 31 385
+rect -173 345 -115 351
+rect 19 345 77 351
+rect -77 71 -19 77
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+rect 115 37 127 71
+rect -77 31 -19 37
+rect 115 31 173 37
+rect -77 -37 -19 -31
+rect 115 -37 173 -31
+rect -77 -71 -65 -37
+rect 115 -71 127 -37
+rect -77 -77 -19 -71
+rect 115 -77 173 -71
+rect -173 -351 -115 -345
+rect 19 -351 77 -345
+rect -173 -385 -161 -351
+rect 19 -385 31 -351
+rect -173 -391 -115 -385
+rect 19 -391 77 -385
+<< pwell >>
+rect -359 -523 359 523
+<< nmos >>
+rect -159 109 -129 313
+rect -63 109 -33 313
+rect 33 109 63 313
+rect 129 109 159 313
+rect -159 -313 -129 -109
+rect -63 -313 -33 -109
+rect 33 -313 63 -109
+rect 129 -313 159 -109
+<< ndiff >>
+rect -221 301 -159 313
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+rect -221 109 -159 121
+rect -129 301 -63 313
+rect -129 121 -113 301
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+rect 209 -301 221 -121
+rect 159 -313 221 -301
+<< ndiffc >>
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+rect -209 -301 -175 -121
+rect -113 -301 -79 -121
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+rect 175 -301 209 -121
+<< psubdiff >>
+rect -323 453 323 487
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+rect -323 -453 -289 -391
+rect 289 -453 323 -391
+rect -323 -487 -227 -453
+rect 227 -487 323 -453
+<< psubdiffcont >>
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+rect 289 -391 323 391
+rect -227 -487 227 -453
+<< poly >>
+rect -177 385 -111 401
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+rect 15 385 81 401
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+rect 15 -351 81 -335
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+rect 15 -385 31 -351
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+<< polycont >>
+rect -161 351 -127 385
+rect 31 351 65 385
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+rect 127 37 161 71
+rect -65 -71 -31 -37
+rect 127 -71 161 -37
+rect -161 -385 -127 -351
+rect 31 -385 65 -351
+<< locali >>
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+rect 289 391 323 453
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+<< viali >>
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+<< metal1 >>
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+rect -77 -37 -19 -31
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+rect -215 -121 -169 -109
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+rect -119 -121 -73 -109
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+rect -23 -121 23 -109
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+rect 113 -301 119 -121
+rect 73 -313 119 -301
+rect 169 -121 215 -109
+rect 169 -301 175 -121
+rect 209 -301 215 -121
+rect 169 -313 215 -301
+rect -173 -351 -115 -345
+rect -173 -385 -161 -351
+rect -127 -385 -115 -351
+rect -173 -391 -115 -385
+rect 19 -351 77 -345
+rect 19 -385 31 -351
+rect 65 -385 77 -351
+rect 19 -391 77 -385
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -306 -470 306 470
+string parameters w 1.02 l 0.150 m 2 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_2BS6QM.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_2BS6QM.mag
new file mode 100644
index 0000000..a815ca1
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_2BS6QM.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< pwell >>
+rect -311 -335 311 335
+<< nmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< ndiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< ndiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< psubdiff >>
+rect -275 203 -241 265
+rect 241 203 275 265
+rect -275 -265 -241 -203
+rect 241 -265 275 -203
+rect -275 -299 -179 -265
+rect 179 -299 275 -265
+<< psubdiffcont >>
+rect -275 -203 -241 203
+rect 241 -203 275 203
+rect -179 -299 179 -265
+<< poly >>
+rect -111 151 111 181
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -151 -81 -125
+rect -15 -151 15 -125
+rect 81 -151 111 -125
+<< locali >>
+rect -275 203 -241 265
+rect 241 203 275 265
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -275 -265 -241 -203
+rect 241 -265 275 -203
+rect -275 -299 -179 -265
+rect 179 -299 275 -265
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -258 -282 258 282
+string parameters w 1.25 l 0.150 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_2BS854.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_2BS854.mag
new file mode 100644
index 0000000..e3752b2
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_2BS854.mag
@@ -0,0 +1,103 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623795754
+<< pwell >>
+rect -311 -335 311 335
+<< nmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< ndiff >>
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+<< ndiffc >>
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+rect 31 -113 65 113
+rect 127 -113 161 113
+<< psubdiff >>
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+rect 179 -299 241 -265
+<< psubdiffcont >>
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+rect -179 -299 179 -265
+<< poly >>
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+rect 31 113 65 129
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+<< viali >>
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+rect 121 -125 167 -113
+rect -134 -163 130 -157
+rect -134 -203 -122 -163
+rect 118 -203 130 -163
+rect -134 -209 130 -203
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -258 -282 258 282
+string parameters w 1.25 l 0.150 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 0 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_3H67RK.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_3H67RK.mag
new file mode 100644
index 0000000..381fce7
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_3H67RK.mag
@@ -0,0 +1,97 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623899171
+<< error_p >>
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+<< nmos >>
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+rect 17 -183 29 -149
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+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -268 158 268
+string parameters w 1.11 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_72JNYZ.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_72JNYZ.mag
new file mode 100644
index 0000000..bcf7ce5
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_72JNYZ.mag
@@ -0,0 +1,127 @@
+magic
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+rect 161 -88 167 88
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+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -258 -257 258 257
+string parameters w 1 l 0.150 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_8T23P9.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_8T23P9.mag
new file mode 100644
index 0000000..722cbbd
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_8T23P9.mag
@@ -0,0 +1,2455 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623985751
+<< error_p >>
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+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -3954 -257 3954 257
+string parameters w 1 l 0.150 m 1 nf 80 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_B2JNY3.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_B2JNY3.mag
new file mode 100644
index 0000000..09da4e6
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_B2JNY3.mag
@@ -0,0 +1,175 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623958102
+<< error_p >>
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+rect 115 138 127 172
+rect -77 132 -19 138
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+rect -173 -172 -161 -138
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+rect 19 -178 77 -172
+<< pwell >>
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+<< nmos >>
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+<< ndiff >>
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+<< ndiffc >>
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+<< psubdiff >>
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+<< polycont >>
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+<< viali >>
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+rect 79 -88 113 88
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+<< metal1 >>
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+rect 19 -138 77 -132
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+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -306 -257 306 257
+string parameters w 1 l 0.150 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_BHR94T.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_BHR94T.mag
new file mode 100644
index 0000000..7a5d479
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_BHR94T.mag
@@ -0,0 +1,93 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< pwell >>
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+<< nmos >>
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+<< ndiff >>
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+<< psubdiff >>
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+<< psubdiffcont >>
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+rect -179 -299 179 -265
+<< poly >>
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+rect -15 125 15 151
+rect 81 125 111 151
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+rect -15 -151 15 -125
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+<< locali >>
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+<< viali >>
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+<< metal1 >>
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+rect -167 -113 -161 113
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+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -258 -282 258 282
+string parameters w 1.25 l 0.150 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_C5D4P9.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_C5D4P9.mag
new file mode 100644
index 0000000..6cc15e6
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_C5D4P9.mag
@@ -0,0 +1,1600 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623985939
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+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -2034 -466 2034 466
+string parameters w 1 l 0.150 m 2 nf 40 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_CFLRKA.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_CFLRKA.mag
new file mode 100644
index 0000000..83d374f
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_CFLRKA.mag
@@ -0,0 +1,2467 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623985751
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+rect 1025 -381 1037 -347
+rect 979 -387 1037 -381
+rect 1171 -347 1229 -341
+rect 1171 -381 1183 -347
+rect 1217 -381 1229 -347
+rect 1171 -387 1229 -381
+rect 1363 -347 1421 -341
+rect 1363 -381 1375 -347
+rect 1409 -381 1421 -347
+rect 1363 -387 1421 -381
+rect 1555 -347 1613 -341
+rect 1555 -381 1567 -347
+rect 1601 -381 1613 -347
+rect 1555 -387 1613 -381
+rect 1747 -347 1805 -341
+rect 1747 -381 1759 -347
+rect 1793 -381 1805 -347
+rect 1747 -387 1805 -381
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -2034 -466 2034 466
+string parameters w 1 l 0.150 m 2 nf 40 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_DXA56D.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_DXA56D.mag
new file mode 100644
index 0000000..f257bf6
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_DXA56D.mag
@@ -0,0 +1,108 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623431064
+<< pwell >>
+rect -359 -252 359 252
+<< nmos >>
+rect -159 -42 -129 42
+rect -63 -42 -33 42
+rect 33 -42 63 42
+rect 129 -42 159 42
+<< ndiff >>
+rect -221 30 -159 42
+rect -221 -30 -209 30
+rect -175 -30 -159 30
+rect -221 -42 -159 -30
+rect -129 30 -63 42
+rect -129 -30 -113 30
+rect -79 -30 -63 30
+rect -129 -42 -63 -30
+rect -33 30 33 42
+rect -33 -30 -17 30
+rect 17 -30 33 30
+rect -33 -42 33 -30
+rect 63 30 129 42
+rect 63 -30 79 30
+rect 113 -30 129 30
+rect 63 -42 129 -30
+rect 159 30 221 42
+rect 159 -30 175 30
+rect 209 -30 221 30
+rect 159 -42 221 -30
+<< ndiffc >>
+rect -209 -30 -175 30
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+rect 175 -30 209 30
+<< psubdiff >>
+rect -323 120 -289 182
+rect 289 120 323 182
+rect -323 -182 -289 -120
+rect 289 -182 323 -120
+rect -323 -216 -227 -182
+rect 227 -216 323 -182
+<< psubdiffcont >>
+rect -323 -120 -289 120
+rect 289 -120 323 120
+rect -227 -216 227 -182
+<< poly >>
+rect -159 42 -129 68
+rect -63 42 -33 68
+rect 33 42 63 68
+rect 129 42 159 68
+rect -159 -68 -129 -42
+rect -63 -68 -33 -42
+rect 33 -68 63 -42
+rect 129 -68 159 -42
+<< locali >>
+rect -323 120 -289 182
+rect 289 120 323 182
+rect -209 30 -175 46
+rect -209 -46 -175 -30
+rect -113 30 -79 46
+rect -113 -46 -79 -30
+rect -17 30 17 46
+rect -17 -46 17 -30
+rect 79 30 113 46
+rect 79 -46 113 -30
+rect 175 30 209 46
+rect 175 -46 209 -30
+rect -323 -182 -289 -120
+rect 289 -182 323 -120
+rect -323 -216 -227 -182
+rect 227 -216 323 -182
+<< viali >>
+rect -209 -30 -175 30
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+rect 175 -30 209 30
+<< metal1 >>
+rect -215 30 -169 42
+rect -215 -30 -209 30
+rect -175 -30 -169 30
+rect -215 -42 -169 -30
+rect -119 30 -73 42
+rect -119 -30 -113 30
+rect -79 -30 -73 30
+rect -119 -42 -73 -30
+rect -23 30 23 42
+rect -23 -30 -17 30
+rect 17 -30 23 30
+rect -23 -42 23 -30
+rect 73 30 119 42
+rect 73 -30 79 30
+rect 113 -30 119 30
+rect 73 -42 119 -30
+rect 169 30 215 42
+rect 169 -30 175 30
+rect 209 -30 215 30
+rect 169 -42 215 -30
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -306 -199 306 199
+string parameters w 0.420 l 0.150 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_HAN8QX.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_HAN8QX.mag
new file mode 100644
index 0000000..2eb0a16
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_HAN8QX.mag
@@ -0,0 +1,78 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623900471
+<< pwell >>
+rect -211 -290 211 290
+<< nmos >>
+rect -15 -142 15 80
+<< ndiff >>
+rect -73 68 -15 80
+rect -73 -130 -61 68
+rect -27 -130 -15 68
+rect -73 -142 -15 -130
+rect 15 68 73 80
+rect 15 -130 27 68
+rect 61 -130 73 68
+rect 15 -142 73 -130
+<< ndiffc >>
+rect -61 -130 -27 68
+rect 27 -130 61 68
+<< psubdiff >>
+rect -175 220 175 254
+rect -175 158 -141 220
+rect 141 158 175 220
+rect -175 -220 -141 -158
+rect 141 -220 175 -158
+rect -175 -254 -79 -220
+rect 79 -254 175 -220
+<< psubdiffcont >>
+rect -175 -158 -141 158
+rect 141 -158 175 158
+rect -79 -254 79 -220
+<< poly >>
+rect -33 152 33 168
+rect -33 118 -17 152
+rect 17 118 33 152
+rect -33 102 33 118
+rect -15 80 15 102
+rect -15 -168 15 -142
+<< polycont >>
+rect -17 118 17 152
+<< locali >>
+rect -175 220 175 254
+rect -175 158 -141 220
+rect 141 158 175 220
+rect -33 118 -17 152
+rect 17 118 33 152
+rect -61 68 -27 84
+rect -61 -146 -27 -130
+rect 27 68 61 84
+rect 27 -146 61 -130
+rect -175 -220 -141 -158
+rect 141 -220 175 -158
+rect -175 -254 -79 -220
+rect 79 -254 175 -220
+<< viali >>
+rect -17 118 17 152
+rect -61 -130 -27 68
+rect 27 -130 61 68
+<< metal1 >>
+rect -33 152 33 162
+rect -33 118 -17 152
+rect 17 118 33 152
+rect -33 108 33 118
+rect -67 68 -21 80
+rect -67 -130 -61 68
+rect -27 -130 -21 68
+rect -67 -142 -21 -130
+rect 21 68 67 80
+rect 21 -130 27 68
+rect 61 -130 67 68
+rect 21 -142 67 -130
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -237 158 237
+string parameters w 1.11 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_KU9PSX.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_KU9PSX.mag
new file mode 100644
index 0000000..45ca065
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_KU9PSX.mag
@@ -0,0 +1,103 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< pwell >>
+rect -263 -305 263 305
+<< nmos >>
+rect -63 -95 -33 95
+rect 33 -95 63 95
+<< ndiff >>
+rect -125 83 -63 95
+rect -125 -83 -113 83
+rect -79 -83 -63 83
+rect -125 -95 -63 -83
+rect -33 83 33 95
+rect -33 -83 -17 83
+rect 17 -83 33 83
+rect -33 -95 33 -83
+rect 63 83 125 95
+rect 63 -83 79 83
+rect 113 -83 125 83
+rect 63 -95 125 -83
+<< ndiffc >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+<< psubdiff >>
+rect -227 173 -193 235
+rect -227 -235 -193 -173
+rect -227 -269 -168 -235
+rect 178 -269 227 -235
+<< psubdiffcont >>
+rect -227 -173 -193 173
+rect -168 -269 178 -235
+<< poly >>
+rect -63 95 -33 121
+rect 33 95 63 121
+rect -63 -117 -33 -95
+rect 33 -117 63 -95
+rect -81 -133 81 -117
+rect -81 -167 -65 -133
+rect 65 -167 81 -133
+rect -81 -183 81 -167
+<< polycont >>
+rect -65 -167 65 -133
+<< locali >>
+rect -227 173 -193 235
+rect -113 83 -79 99
+rect -113 -99 -79 -83
+rect -17 83 17 99
+rect -17 -99 17 -83
+rect 79 83 113 99
+rect 79 -99 113 -83
+rect -81 -167 -65 -133
+rect 65 -167 81 -133
+rect -227 -235 -193 -173
+rect -227 -269 -168 -235
+rect 178 -269 227 -235
+<< viali >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+rect -65 -167 65 -133
+<< metal1 >>
+rect -119 84 -73 95
+rect -132 -85 -122 84
+rect -70 -85 -60 84
+rect -23 83 23 95
+rect 73 84 119 95
+rect -23 -83 -17 83
+rect 17 -83 23 83
+rect -119 -95 -73 -85
+rect -23 -95 23 -83
+rect 60 -85 70 84
+rect 122 -85 132 84
+rect 73 -95 119 -85
+rect -77 -133 77 -127
+rect -77 -167 -65 -133
+rect 65 -167 77 -133
+rect -77 -173 77 -167
+<< via1 >>
+rect -122 83 -70 84
+rect -122 -83 -113 83
+rect -113 -83 -79 83
+rect -79 -83 -70 83
+rect -122 -85 -70 -83
+rect 70 83 122 84
+rect 70 -83 79 83
+rect 79 -83 113 83
+rect 113 -83 122 83
+rect 70 -85 122 -83
+<< metal2 >>
+rect -122 84 -70 94
+rect 70 84 122 94
+rect -70 -85 70 84
+rect -122 -95 -70 -85
+rect 70 -95 122 -85
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -252 210 252
+string parameters w 0.95 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_L78GGD.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_L78GGD.mag
new file mode 100644
index 0000000..9d64ed3
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_L78GGD.mag
@@ -0,0 +1,82 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1620330026
+<< error_p >>
+rect -29 83 29 89
+rect -29 49 -17 83
+rect -29 43 29 49
+<< pwell >>
+rect -211 -221 211 221
+<< nmos >>
+rect -15 -73 15 11
+<< ndiff >>
+rect -73 -1 -15 11
+rect -73 -61 -61 -1
+rect -27 -61 -15 -1
+rect -73 -73 -15 -61
+rect 15 -1 73 11
+rect 15 -61 27 -1
+rect 61 -61 73 -1
+rect 15 -73 73 -61
+<< ndiffc >>
+rect -61 -61 -27 -1
+rect 27 -61 61 -1
+<< psubdiff >>
+rect -175 151 175 185
+rect -175 89 -141 151
+rect 141 89 175 151
+rect -175 -151 -141 -89
+rect 141 -151 175 -89
+rect -175 -185 -79 -151
+rect 79 -185 175 -151
+<< psubdiffcont >>
+rect -175 -89 -141 89
+rect 141 -89 175 89
+rect -79 -185 79 -151
+<< poly >>
+rect -33 83 33 99
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -33 33 33 49
+rect -15 11 15 33
+rect -15 -99 15 -73
+<< polycont >>
+rect -17 49 17 83
+<< locali >>
+rect -175 151 175 185
+rect -175 89 -141 151
+rect 141 89 175 151
+rect -33 49 -17 83
+rect 17 49 33 83
+rect -61 -1 -27 15
+rect -61 -77 -27 -61
+rect 27 -1 61 15
+rect 27 -77 61 -61
+rect -175 -151 -141 -89
+rect 141 -151 175 -89
+rect -175 -185 -79 -151
+rect 79 -185 175 -151
+<< viali >>
+rect -17 49 17 83
+rect -61 -61 -27 -1
+rect 27 -61 61 -1
+<< metal1 >>
+rect -29 83 29 89
+rect -29 49 -17 83
+rect 17 49 29 83
+rect -29 43 29 49
+rect -67 -1 -21 11
+rect -67 -61 -61 -1
+rect -27 -61 -21 -1
+rect -67 -73 -21 -61
+rect 21 -1 67 11
+rect 21 -61 27 -1
+rect 61 -61 67 -1
+rect 21 -73 67 -61
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -168 158 168
+string parameters w 0.42 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_QQE8KM.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_QQE8KM.mag
new file mode 100644
index 0000000..ada88f4
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_QQE8KM.mag
@@ -0,0 +1,290 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624046389
+<< pwell >>
+rect -935 -252 935 252
+<< nmos >>
+rect -735 -42 -705 42
+rect -639 -42 -609 42
+rect -543 -42 -513 42
+rect -447 -42 -417 42
+rect -351 -42 -321 42
+rect -255 -42 -225 42
+rect -159 -42 -129 42
+rect -63 -42 -33 42
+rect 33 -42 63 42
+rect 129 -42 159 42
+rect 225 -42 255 42
+rect 321 -42 351 42
+rect 417 -42 447 42
+rect 513 -42 543 42
+rect 609 -42 639 42
+rect 705 -42 735 42
+<< ndiff >>
+rect -797 30 -735 42
+rect -797 -30 -785 30
+rect -751 -30 -735 30
+rect -797 -42 -735 -30
+rect -705 30 -639 42
+rect -705 -30 -689 30
+rect -655 -30 -639 30
+rect -705 -42 -639 -30
+rect -609 30 -543 42
+rect -609 -30 -593 30
+rect -559 -30 -543 30
+rect -609 -42 -543 -30
+rect -513 30 -447 42
+rect -513 -30 -497 30
+rect -463 -30 -447 30
+rect -513 -42 -447 -30
+rect -417 30 -351 42
+rect -417 -30 -401 30
+rect -367 -30 -351 30
+rect -417 -42 -351 -30
+rect -321 30 -255 42
+rect -321 -30 -305 30
+rect -271 -30 -255 30
+rect -321 -42 -255 -30
+rect -225 30 -159 42
+rect -225 -30 -209 30
+rect -175 -30 -159 30
+rect -225 -42 -159 -30
+rect -129 30 -63 42
+rect -129 -30 -113 30
+rect -79 -30 -63 30
+rect -129 -42 -63 -30
+rect -33 30 33 42
+rect -33 -30 -17 30
+rect 17 -30 33 30
+rect -33 -42 33 -30
+rect 63 30 129 42
+rect 63 -30 79 30
+rect 113 -30 129 30
+rect 63 -42 129 -30
+rect 159 30 225 42
+rect 159 -30 175 30
+rect 209 -30 225 30
+rect 159 -42 225 -30
+rect 255 30 321 42
+rect 255 -30 271 30
+rect 305 -30 321 30
+rect 255 -42 321 -30
+rect 351 30 417 42
+rect 351 -30 367 30
+rect 401 -30 417 30
+rect 351 -42 417 -30
+rect 447 30 513 42
+rect 447 -30 463 30
+rect 497 -30 513 30
+rect 447 -42 513 -30
+rect 543 30 609 42
+rect 543 -30 559 30
+rect 593 -30 609 30
+rect 543 -42 609 -30
+rect 639 30 705 42
+rect 639 -30 655 30
+rect 689 -30 705 30
+rect 639 -42 705 -30
+rect 735 30 797 42
+rect 735 -30 751 30
+rect 785 -30 797 30
+rect 735 -42 797 -30
+<< ndiffc >>
+rect -785 -30 -751 30
+rect -689 -30 -655 30
+rect -593 -30 -559 30
+rect -497 -30 -463 30
+rect -401 -30 -367 30
+rect -305 -30 -271 30
+rect -209 -30 -175 30
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+rect 175 -30 209 30
+rect 271 -30 305 30
+rect 367 -30 401 30
+rect 463 -30 497 30
+rect 559 -30 593 30
+rect 655 -30 689 30
+rect 751 -30 785 30
+<< psubdiff >>
+rect -899 120 -865 216
+rect 865 120 899 216
+rect -899 -182 -865 -120
+rect 865 -182 899 -120
+rect -899 -216 -803 -182
+rect 803 -216 899 -182
+<< psubdiffcont >>
+rect -899 -120 -865 120
+rect 865 -120 899 120
+rect -803 -216 803 -182
+<< poly >>
+rect -757 64 753 130
+rect -735 42 -705 64
+rect -639 42 -609 64
+rect -543 42 -513 64
+rect -447 42 -417 64
+rect -351 42 -321 64
+rect -255 42 -225 64
+rect -159 42 -129 64
+rect -63 42 -33 64
+rect 33 42 63 64
+rect 129 42 159 64
+rect 225 42 255 64
+rect 321 42 351 64
+rect 417 42 447 64
+rect 513 42 543 64
+rect 609 42 639 64
+rect 705 42 735 64
+rect -735 -64 -705 -42
+rect -639 -64 -609 -42
+rect -543 -64 -513 -42
+rect -447 -64 -417 -42
+rect -351 -64 -321 -42
+rect -255 -64 -225 -42
+rect -159 -64 -129 -42
+rect -63 -64 -33 -42
+rect 33 -64 63 -42
+rect 129 -64 159 -42
+rect 225 -64 255 -42
+rect 321 -64 351 -42
+rect 417 -64 447 -42
+rect 513 -64 543 -42
+rect 609 -64 639 -42
+rect 705 -64 735 -42
+rect -753 -130 757 -64
+<< locali >>
+rect -899 120 -865 216
+rect 865 120 899 216
+rect -785 30 -751 46
+rect -785 -46 -751 -30
+rect -689 30 -655 46
+rect -689 -46 -655 -30
+rect -593 30 -559 46
+rect -593 -46 -559 -30
+rect -497 30 -463 46
+rect -497 -46 -463 -30
+rect -401 30 -367 46
+rect -401 -46 -367 -30
+rect -305 30 -271 46
+rect -305 -46 -271 -30
+rect -209 30 -175 46
+rect -209 -46 -175 -30
+rect -113 30 -79 46
+rect -113 -46 -79 -30
+rect -17 30 17 46
+rect -17 -46 17 -30
+rect 79 30 113 46
+rect 79 -46 113 -30
+rect 175 30 209 46
+rect 175 -46 209 -30
+rect 271 30 305 46
+rect 271 -46 305 -30
+rect 367 30 401 46
+rect 367 -46 401 -30
+rect 463 30 497 46
+rect 463 -46 497 -30
+rect 559 30 593 46
+rect 559 -46 593 -30
+rect 655 30 689 46
+rect 655 -46 689 -30
+rect 751 30 785 46
+rect 751 -46 785 -30
+rect -899 -182 -865 -120
+rect 865 -182 899 -120
+rect -899 -216 -803 -182
+rect 803 -216 899 -182
+<< viali >>
+rect -785 -30 -751 30
+rect -689 -30 -655 30
+rect -593 -30 -559 30
+rect -497 -30 -463 30
+rect -401 -30 -367 30
+rect -305 -30 -271 30
+rect -209 -30 -175 30
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+rect 175 -30 209 30
+rect 271 -30 305 30
+rect 367 -30 401 30
+rect 463 -30 497 30
+rect 559 -30 593 30
+rect 655 -30 689 30
+rect 751 -30 785 30
+<< metal1 >>
+rect -791 30 -745 42
+rect -791 -30 -785 30
+rect -751 -30 -745 30
+rect -791 -42 -745 -30
+rect -695 30 -649 42
+rect -695 -30 -689 30
+rect -655 -30 -649 30
+rect -695 -42 -649 -30
+rect -599 30 -553 42
+rect -599 -30 -593 30
+rect -559 -30 -553 30
+rect -599 -42 -553 -30
+rect -503 30 -457 42
+rect -503 -30 -497 30
+rect -463 -30 -457 30
+rect -503 -42 -457 -30
+rect -407 30 -361 42
+rect -407 -30 -401 30
+rect -367 -30 -361 30
+rect -407 -42 -361 -30
+rect -311 30 -265 42
+rect -311 -30 -305 30
+rect -271 -30 -265 30
+rect -311 -42 -265 -30
+rect -215 30 -169 42
+rect -215 -30 -209 30
+rect -175 -30 -169 30
+rect -215 -42 -169 -30
+rect -119 30 -73 42
+rect -119 -30 -113 30
+rect -79 -30 -73 30
+rect -119 -42 -73 -30
+rect -23 30 23 42
+rect -23 -30 -17 30
+rect 17 -30 23 30
+rect -23 -42 23 -30
+rect 73 30 119 42
+rect 73 -30 79 30
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+rect 649 -42 695 -30
+rect 745 30 791 42
+rect 745 -30 751 30
+rect 785 -30 791 30
+rect 745 -42 791 -30
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -882 -199 882 199
+string parameters w 0.420 l 0.150 m 1 nf 16 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_XRJ78J.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_XRJ78J.mag
new file mode 100644
index 0000000..455b180
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_XRJ78J.mag
@@ -0,0 +1,74 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623948006
+<< pwell >>
+rect -263 -312 263 312
+<< nmos >>
+rect -63 -102 -33 102
+rect 33 -102 63 102
+<< ndiff >>
+rect -125 90 -63 102
+rect -125 -90 -113 90
+rect -79 -90 -63 90
+rect -125 -102 -63 -90
+rect -33 90 33 102
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+rect 17 -90 33 90
+rect -33 -102 33 -90
+rect 63 90 125 102
+rect 63 -90 79 90
+rect 113 -90 125 90
+rect 63 -102 125 -90
+<< ndiffc >>
+rect -113 -90 -79 90
+rect -17 -90 17 90
+rect 79 -90 113 90
+<< psubdiff >>
+rect -227 180 -193 276
+rect -227 -242 -193 -180
+rect -227 -276 -131 -242
+rect 131 -276 263 -242
+<< psubdiffcont >>
+rect -227 -180 -193 180
+rect -131 -276 131 -242
+<< poly >>
+rect -81 124 81 190
+rect -63 102 -33 124
+rect 33 102 63 124
+rect -63 -128 -33 -102
+rect 33 -128 63 -102
+<< locali >>
+rect -227 180 -193 276
+rect -113 90 -79 106
+rect -113 -106 -79 -90
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+rect 79 90 113 106
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+<< viali >>
+rect -113 -90 -79 90
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+<< metal1 >>
+rect -119 90 -73 102
+rect -119 -90 -113 90
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+rect 17 -90 23 90
+rect -23 -102 23 -90
+rect 73 90 119 102
+rect 73 -90 79 90
+rect 113 -90 119 90
+rect 73 -102 119 -90
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -259 210 259
+string parameters w 1.02 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_2AA63D.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_2AA63D.mag
new file mode 100644
index 0000000..12c5656
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_2AA63D.mag
@@ -0,0 +1,100 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623961588
+<< error_p >>
+rect -29 122 29 128
+rect -29 88 -17 122
+rect -29 82 29 88
+rect -29 -88 29 -82
+rect -29 -122 -17 -88
+rect -29 -128 29 -122
+<< pwell >>
+rect -211 -260 211 260
+<< nmoslvt >>
+rect -15 -50 15 50
+<< ndiff >>
+rect -73 38 -15 50
+rect -73 -38 -61 38
+rect -27 -38 -15 38
+rect -73 -50 -15 -38
+rect 15 38 73 50
+rect 15 -38 27 38
+rect 61 -38 73 38
+rect 15 -50 73 -38
+<< ndiffc >>
+rect -61 -38 -27 38
+rect 27 -38 61 38
+<< psubdiff >>
+rect -175 190 -79 224
+rect 79 190 175 224
+rect -175 128 -141 190
+rect 141 128 175 190
+rect -175 -190 -141 -128
+rect 141 -190 175 -128
+rect -175 -224 -79 -190
+rect 79 -224 175 -190
+<< psubdiffcont >>
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+rect -175 -128 -141 128
+rect 141 -128 175 128
+rect -79 -224 79 -190
+<< poly >>
+rect -33 122 33 138
+rect -33 88 -17 122
+rect 17 88 33 122
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+rect -15 50 15 72
+rect -15 -72 15 -50
+rect -33 -88 33 -72
+rect -33 -122 -17 -88
+rect 17 -122 33 -88
+rect -33 -138 33 -122
+<< polycont >>
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+rect -17 -122 17 -88
+<< locali >>
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+rect 79 190 175 224
+rect -175 128 -141 190
+rect 141 128 175 190
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+rect 79 -224 175 -190
+<< viali >>
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+rect -61 -38 -27 38
+rect 27 -38 61 38
+rect -17 -122 17 -88
+<< metal1 >>
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+rect -29 88 -17 122
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+rect -67 38 -21 50
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+rect 21 -50 67 -38
+rect -29 -88 29 -82
+rect -29 -122 -17 -88
+rect 17 -122 29 -88
+rect -29 -128 29 -122
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -158 -207 158 207
+string parameters w 0.5 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_2AP43D.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_2AP43D.mag
new file mode 100644
index 0000000..94610b8
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_2AP43D.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623961588
+<< error_p >>
+rect -29 91 29 97
+rect -29 57 -17 91
+rect -29 51 29 57
+<< pwell >>
+rect -211 -229 211 229
+<< nmoslvt >>
+rect -15 -81 15 19
+<< ndiff >>
+rect -73 7 -15 19
+rect -73 -69 -61 7
+rect -27 -69 -15 7
+rect -73 -81 -15 -69
+rect 15 7 73 19
+rect 15 -69 27 7
+rect 61 -69 73 7
+rect 15 -81 73 -69
+<< ndiffc >>
+rect -61 -69 -27 7
+rect 27 -69 61 7
+<< psubdiff >>
+rect -175 159 -79 193
+rect 79 159 175 193
+rect -175 97 -141 159
+rect 141 97 175 159
+rect -175 -159 -141 -97
+rect 141 -159 175 -97
+rect -175 -193 -79 -159
+rect 79 -193 175 -159
+<< psubdiffcont >>
+rect -79 159 79 193
+rect -175 -97 -141 97
+rect 141 -97 175 97
+rect -79 -193 79 -159
+<< poly >>
+rect -33 91 33 107
+rect -33 57 -17 91
+rect 17 57 33 91
+rect -33 41 33 57
+rect -15 19 15 41
+rect -15 -107 15 -81
+<< polycont >>
+rect -17 57 17 91
+<< locali >>
+rect -175 159 -79 193
+rect 79 159 175 193
+rect -175 97 -141 159
+rect 141 97 175 159
+rect -33 57 -17 91
+rect 17 57 33 91
+rect -61 7 -27 23
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+rect 27 7 61 23
+rect 27 -85 61 -69
+rect -175 -159 -141 -97
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+rect -175 -193 -79 -159
+rect 79 -193 175 -159
+<< viali >>
+rect -17 57 17 91
+rect -61 -69 -27 7
+rect 27 -69 61 7
+<< metal1 >>
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+rect -29 57 -17 91
+rect 17 57 29 91
+rect -29 51 29 57
+rect -67 7 -21 19
+rect -67 -69 -61 7
+rect -27 -69 -21 7
+rect -67 -81 -21 -69
+rect 21 7 67 19
+rect 21 -69 27 7
+rect 61 -69 67 7
+rect 21 -81 67 -69
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -158 -176 158 176
+string parameters w 0.5 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_595QY5.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_595QY5.mag
new file mode 100644
index 0000000..94cc2aa
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_595QY5.mag
@@ -0,0 +1,157 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624030292
+<< pwell >>
+rect -407 -310 407 310
+<< nmoslvt >>
+rect -207 -100 -177 100
+rect -111 -100 -81 100
+rect -15 -100 15 100
+rect 81 -100 111 100
+rect 177 -100 207 100
+<< ndiff >>
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+rect 161 -88 177 88
+rect 111 -100 177 -88
+rect 207 88 269 100
+rect 207 -88 223 88
+rect 257 -88 269 88
+rect 207 -100 269 -88
+<< ndiffc >>
+rect -257 -88 -223 88
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+rect 223 -88 257 88
+<< psubdiff >>
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+rect -371 -240 -337 -178
+rect 337 -240 371 -178
+rect -371 -274 -275 -240
+rect 275 -274 371 -240
+<< psubdiffcont >>
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+rect -371 -178 -337 178
+rect 337 -178 371 178
+rect -275 -274 275 -240
+<< poly >>
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+rect -111 100 -81 126
+rect -15 100 15 126
+rect 81 100 111 126
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+rect -207 -122 -177 -100
+rect -111 -122 -81 -100
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+rect -79 -172 -17 -138
+rect 17 -172 79 -138
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+rect -225 -188 225 -172
+<< polycont >>
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+rect -113 -172 -79 -138
+rect -17 -172 17 -138
+rect 79 -172 113 -138
+rect 175 -172 209 -138
+<< locali >>
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+rect 275 240 371 274
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+rect 209 -172 225 -138
+rect -371 -240 -337 -178
+rect 337 -240 371 -178
+rect -371 -274 -275 -240
+rect 275 -274 371 -240
+<< viali >>
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+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+rect 223 -88 257 88
+rect -209 -172 -175 -138
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+<< metal1 >>
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+rect 25 88 71 100
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+rect 217 -100 263 -88
+rect -221 -138 221 -132
+rect -221 -172 -209 -138
+rect 209 -172 221 -138
+rect -221 -178 221 -172
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -354 -257 354 257
+string parameters w 1 l 0.150 m 1 nf 5 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_72JNYZ.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_72JNYZ.mag
new file mode 100644
index 0000000..943a5fc
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_72JNYZ.mag
@@ -0,0 +1,119 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624032293
+<< pwell >>
+rect -311 -310 311 310
+<< nmoslvt >>
+rect -111 -100 -81 100
+rect -15 -100 15 100
+rect 81 -100 111 100
+<< ndiff >>
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+rect 111 -100 173 -88
+<< ndiffc >>
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+<< psubdiff >>
+rect -275 240 -179 274
+rect 179 240 275 274
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+rect 241 178 275 240
+rect -275 -240 -241 -178
+rect 241 -240 275 -178
+rect -275 -274 -179 -240
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+<< psubdiffcont >>
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+rect -275 -178 -241 178
+rect 241 -178 275 178
+rect -179 -274 179 -240
+<< poly >>
+rect -128 172 130 188
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+rect 17 138 80 172
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+rect -111 100 -81 122
+rect -15 100 15 122
+rect 81 100 111 122
+rect -111 -126 -81 -100
+rect -15 -126 15 -100
+rect 81 -126 111 -100
+<< polycont >>
+rect -112 138 -78 172
+rect -17 138 17 172
+rect 80 138 114 172
+<< locali >>
+rect -275 240 -179 274
+rect 179 240 275 274
+rect -275 178 -241 240
+rect 241 178 275 240
+rect -128 138 -112 172
+rect 114 138 130 172
+rect -161 88 -127 104
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+rect -65 88 -31 104
+rect -65 -104 -31 -88
+rect 31 88 65 104
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+rect 127 88 161 104
+rect 127 -104 161 -88
+rect -275 -240 -241 -178
+rect 241 -240 275 -178
+rect -275 -274 -179 -240
+rect 179 -274 275 -240
+<< viali >>
+rect -112 138 -78 172
+rect -78 138 -17 172
+rect -17 138 17 172
+rect 17 138 80 172
+rect 80 138 114 172
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+<< metal1 >>
+rect -124 172 126 178
+rect -124 138 -112 172
+rect 114 138 126 172
+rect -124 132 126 138
+rect -167 88 -121 100
+rect -167 -88 -161 88
+rect -127 -88 -121 88
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+rect -71 88 -25 100
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+rect 65 -88 71 88
+rect 25 -100 71 -88
+rect 121 88 167 100
+rect 121 -88 127 88
+rect 161 -88 167 88
+rect 121 -100 167 -88
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -258 -257 258 257
+string parameters w 1 l 0.150 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_7BR53M.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_7BR53M.mag
new file mode 100644
index 0000000..c259292
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_7BR53M.mag
@@ -0,0 +1,158 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623956551
+<< pwell >>
+rect -455 -310 455 310
+<< nmoslvt >>
+rect -255 -100 -225 100
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+rect 225 -100 255 100
+<< ndiff >>
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+rect 209 -88 225 88
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+rect 255 88 317 100
+rect 255 -88 271 88
+rect 305 -88 317 88
+rect 255 -100 317 -88
+<< ndiffc >>
+rect -305 -88 -271 88
+rect -209 -88 -175 88
+rect -113 -88 -79 88
+rect -17 -88 17 88
+rect 79 -88 113 88
+rect 175 -88 209 88
+rect 271 -88 305 88
+<< psubdiff >>
+rect -419 240 -323 274
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+<< locali >>
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+<< metal1 >>
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+rect 265 88 311 100
+rect 265 -88 271 88
+rect 305 -88 311 88
+rect 265 -100 311 -88
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -402 -257 402 257
+string parameters w 1 l 0.150 m 1 nf 6 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_9B2JY7.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_9B2JY7.mag
new file mode 100644
index 0000000..0c7c631
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_9B2JY7.mag
@@ -0,0 +1,181 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624020979
+<< pwell >>
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+<< nmoslvt >>
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+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -402 -257 402 257
+string parameters w 1 l 0.150 m 1 nf 6 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_B2JNY3.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_B2JNY3.mag
new file mode 100644
index 0000000..f031d83
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_B2JNY3.mag
@@ -0,0 +1,142 @@
+magic
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+magscale 1 2
+timestamp 1623958660
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+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -306 -257 306 257
+string parameters w 1 l 0.150 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_CAF2P9.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_CAF2P9.mag
new file mode 100644
index 0000000..5217154
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_CAF2P9.mag
@@ -0,0 +1,2566 @@
+magic
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+magscale 1 2
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+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -2034 -884 2034 884
+string parameters w 1 l 0.150 m 4 nf 40 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_CFLRKA.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_CFLRKA.mag
new file mode 100644
index 0000000..9a09c8f
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_CFLRKA.mag
@@ -0,0 +1,1340 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623991863
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+rect 1801 -309 1847 -297
+rect 1897 -121 1943 -109
+rect 1897 -297 1903 -121
+rect 1937 -297 1943 -121
+rect 1897 -309 1943 -297
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -2034 -466 2034 466
+string parameters w 1 l 0.150 m 2 nf 40 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_GV8PYF.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_GV8PYF.mag
new file mode 100644
index 0000000..4001d80
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_GV8PYF.mag
@@ -0,0 +1,103 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623958102
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+rect -9 122 263 188
+rect -263 -310 263 122
+<< nmoslvt >>
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+<< ndiff >>
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+<< ndiffc >>
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+<< psubdiff >>
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+<< psubdiffcont >>
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+<< poly >>
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+<< locali >>
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+<< viali >>
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+rect 79 -88 113 88
+<< metal1 >>
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+rect 17 -88 23 88
+rect -23 -100 23 -88
+rect 73 88 119 100
+rect 73 -88 79 88
+rect 113 -88 119 88
+rect 73 -100 119 -88
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -210 -257 210 257
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_MVT43V.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_MVT43V.mag
new file mode 100644
index 0000000..5790b27
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_MVT43V.mag
@@ -0,0 +1,108 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623958102
+<< pwell >>
+rect -263 192 263 310
+rect -263 188 -79 192
+rect -263 126 -13 188
+rect -6 126 263 192
+rect -263 -310 263 126
+<< nmoslvt >>
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+rect 33 -100 63 100
+<< ndiff >>
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+rect 63 -100 125 -88
+<< ndiffc >>
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+rect -17 -88 17 88
+rect 79 -88 113 88
+<< psubdiff >>
+rect -227 240 -131 274
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+rect -227 178 -193 240
+rect 193 178 227 240
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+rect 193 -240 227 -178
+rect -227 -274 -131 -240
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+<< psubdiffcont >>
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+rect -227 -178 -193 178
+rect 193 -178 227 178
+rect -131 -274 131 -240
+<< poly >>
+rect -79 172 81 188
+rect -79 138 -63 172
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+rect 65 138 81 172
+rect -79 122 81 138
+rect -63 100 -33 122
+rect 33 100 63 122
+rect -63 -126 -33 -100
+rect 33 -126 63 -100
+<< polycont >>
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+rect 31 138 65 172
+<< locali >>
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+rect 193 178 227 240
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+rect 71 138 81 172
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+rect 79 -104 113 -88
+rect -227 -240 -193 -178
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+rect -227 -274 -131 -240
+rect 131 -274 227 -240
+<< viali >>
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+rect -29 138 31 172
+rect 31 138 65 172
+rect 65 138 71 172
+rect -113 -88 -79 88
+rect -17 -88 17 88
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+<< metal1 >>
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+rect -83 172 83 178
+rect -83 138 -71 172
+rect 71 138 83 172
+rect -83 132 83 138
+rect -79 128 81 132
+rect -119 88 -73 100
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+rect 17 -88 23 88
+rect -23 -100 23 -88
+rect 73 88 119 100
+rect 73 -88 79 88
+rect 113 -88 119 88
+rect 73 -100 119 -88
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -210 -257 210 257
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_NMSMYT.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_NMSMYT.mag
new file mode 100644
index 0000000..4ca5e90
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__nfet_01v8_lvt_NMSMYT.mag
@@ -0,0 +1,219 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623958459
+<< pwell >>
+rect -551 188 551 310
+rect -551 122 -302 188
+rect -298 122 -178 188
+rect -176 122 274 188
+rect 277 122 551 188
+rect -551 -310 551 122
+<< nmoslvt >>
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+rect -255 -100 -225 100
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
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+<< ndiff >>
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+<< ndiffc >>
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+<< psubdiff >>
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+<< psubdiffcont >>
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+<< poly >>
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+<< polycont >>
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+rect -160 138 -126 172
+rect -65 138 -31 172
+rect 32 138 66 172
+rect 127 138 161 172
+rect 224 138 258 172
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+<< locali >>
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+<< viali >>
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+<< metal1 >>
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+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string FIXED_BBOX -498 -257 498 257
+string parameters w 1 l 0.150 m 1 nf 8 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_2XL9AN.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_2XL9AN.mag
new file mode 100644
index 0000000..0c91fe7
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_2XL9AN.mag
@@ -0,0 +1,111 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623969232
+<< nwell >>
+rect -311 -319 311 319
+<< pmos >>
+rect -111 -100 -81 100
+rect -15 -100 15 100
+rect 81 -100 111 100
+<< pdiff >>
+rect -173 88 -111 100
+rect -173 -88 -161 88
+rect -127 -88 -111 88
+rect -173 -100 -111 -88
+rect -81 88 -15 100
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+rect 65 -88 81 88
+rect 15 -100 81 -88
+rect 111 88 173 100
+rect 111 -88 127 88
+rect 161 -88 173 88
+rect 111 -100 173 -88
+<< pdiffc >>
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+<< nsubdiff >>
+rect -275 249 -179 283
+rect 179 249 275 283
+rect -275 187 -241 249
+rect 241 187 275 249
+rect -275 -249 -241 -187
+rect 241 -249 275 -187
+rect -275 -283 -179 -249
+rect 179 -283 275 -249
+<< nsubdiffcont >>
+rect -179 249 179 283
+rect -275 -187 -241 187
+rect 241 -187 275 187
+rect -179 -283 179 -249
+<< poly >>
+rect -129 181 129 197
+rect -129 147 -108 181
+rect 110 147 129 181
+rect -129 131 129 147
+rect -111 100 -81 131
+rect -15 100 15 131
+rect 81 100 111 131
+rect -111 -126 -81 -100
+rect -15 -126 15 -100
+rect 81 -126 111 -100
+<< polycont >>
+rect -108 147 110 181
+<< locali >>
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+rect 179 249 275 283
+rect -275 187 -241 249
+rect 241 187 275 249
+rect -124 147 -108 181
+rect 110 147 126 181
+rect -161 88 -127 104
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+rect -65 88 -31 104
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+rect 31 88 65 104
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+rect 127 88 161 104
+rect 127 -104 161 -88
+rect -275 -249 -241 -187
+rect 241 -249 275 -187
+rect -275 -283 -179 -249
+rect 179 -283 275 -249
+<< viali >>
+rect -108 147 110 181
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+<< metal1 >>
+rect -120 181 122 187
+rect -120 147 -108 181
+rect 110 147 122 181
+rect -120 141 122 147
+rect -167 88 -121 100
+rect -167 -88 -161 88
+rect -127 -88 -121 88
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+rect -71 88 -25 100
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+rect 65 -88 71 88
+rect 25 -100 71 -88
+rect 121 88 167 100
+rect 121 -88 127 88
+rect 161 -88 167 88
+rect 121 -100 167 -88
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -258 -266 258 266
+string parameters w 1 l 0.15 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_2XU88L.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_2XU88L.mag
new file mode 100644
index 0000000..4676933
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_2XU88L.mag
@@ -0,0 +1,253 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623947031
+<< error_p >>
+rect -239 181 -181 187
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+rect -239 147 -227 181
+rect 181 147 193 181
+rect -239 141 -181 147
+rect 181 141 239 147
+rect -449 -147 -391 -141
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+rect -449 -181 -437 -147
+rect -29 -181 -17 -147
+rect 391 -181 403 -147
+rect -449 -187 -391 -181
+rect -29 -187 29 -181
+rect 391 -187 449 -181
+<< nwell >>
+rect -635 -319 635 319
+<< pmos >>
+rect -435 -100 -405 100
+rect -225 -100 -195 100
+rect -15 -100 15 100
+rect 195 -100 225 100
+rect 405 -100 435 100
+<< pdiff >>
+rect -497 88 -435 100
+rect -497 -88 -485 88
+rect -451 -88 -435 88
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+rect -405 88 -343 100
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+rect 435 -88 451 88
+rect 485 -88 497 88
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+<< pdiffc >>
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+rect -179 -88 -145 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
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+rect 451 -88 485 88
+<< nsubdiff >>
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+rect 565 187 599 249
+rect -599 -249 -565 -187
+rect 565 -249 599 -187
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+rect 503 -283 599 -249
+<< nsubdiffcont >>
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+rect 565 -187 599 187
+rect -503 -283 503 -249
+<< poly >>
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+rect 177 147 193 181
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+rect 387 -147 453 -131
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+rect 437 -181 453 -147
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+<< polycont >>
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+rect 193 147 227 181
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+rect -17 -181 17 -147
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+<< locali >>
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+rect -599 -249 -565 -187
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+<< viali >>
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+rect 193 147 227 181
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+rect -389 -88 -355 88
+rect -275 -88 -241 88
+rect -179 -88 -145 88
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+rect 451 -88 485 88
+rect -437 -181 -403 -147
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+<< metal1 >>
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+rect 181 181 239 187
+rect 181 147 193 181
+rect 227 147 239 181
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+rect 25 88 71 100
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+rect 139 -88 145 88
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+rect 235 88 281 100
+rect 235 -88 241 88
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+rect 349 88 395 100
+rect 349 -88 355 88
+rect 389 -88 395 88
+rect 349 -100 395 -88
+rect 445 88 491 100
+rect 445 -88 451 88
+rect 485 -88 491 88
+rect 445 -100 491 -88
+rect -449 -147 -391 -141
+rect -449 -181 -437 -147
+rect -403 -181 -391 -147
+rect -449 -187 -391 -181
+rect -29 -147 29 -141
+rect -29 -181 -17 -147
+rect 17 -181 29 -147
+rect -29 -187 29 -181
+rect 391 -147 449 -141
+rect 391 -181 403 -147
+rect 437 -181 449 -147
+rect 391 -187 449 -181
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -582 -266 582 266
+string parameters w 1 l 0.15 m 1 nf 5 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 0 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_2XUYGK.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_2XUYGK.mag
new file mode 100644
index 0000000..2204de4
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_2XUYGK.mag
@@ -0,0 +1,141 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623947381
+<< nwell >>
+rect -407 -319 407 319
+<< pmos >>
+rect -207 -100 -177 100
+rect -111 -100 -81 100
+rect -15 -100 15 100
+rect 81 -100 111 100
+rect 177 -100 207 100
+<< pdiff >>
+rect -269 88 -207 100
+rect -269 -88 -257 88
+rect -223 -88 -207 88
+rect -269 -100 -207 -88
+rect -177 88 -111 100
+rect -177 -88 -161 88
+rect -127 -88 -111 88
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+rect -81 88 -15 100
+rect -81 -88 -65 88
+rect -31 -88 -15 88
+rect -81 -100 -15 -88
+rect 15 88 81 100
+rect 15 -88 31 88
+rect 65 -88 81 88
+rect 15 -100 81 -88
+rect 111 88 177 100
+rect 111 -88 127 88
+rect 161 -88 177 88
+rect 111 -100 177 -88
+rect 207 88 269 100
+rect 207 -88 223 88
+rect 257 -88 269 88
+rect 207 -100 269 -88
+<< pdiffc >>
+rect -257 -88 -223 88
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+rect 223 -88 257 88
+<< nsubdiff >>
+rect -371 249 -275 283
+rect 275 249 371 283
+rect -371 187 -337 249
+rect 337 187 371 249
+rect -371 -249 -337 -187
+rect 337 -249 371 -187
+rect -371 -283 -275 -249
+rect 275 -283 371 -249
+<< nsubdiffcont >>
+rect -275 249 275 283
+rect -371 -187 -337 187
+rect 337 -187 371 187
+rect -275 -283 275 -249
+<< poly >>
+rect -225 181 225 197
+rect -225 147 -177 181
+rect 181 147 225 181
+rect -225 131 225 147
+rect -207 100 -177 131
+rect -111 100 -81 131
+rect -15 100 15 131
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+rect -207 -126 -177 -100
+rect -111 -126 -81 -100
+rect -15 -126 15 -100
+rect 81 -126 111 -100
+rect 177 -126 207 -100
+<< polycont >>
+rect -177 147 181 181
+<< locali >>
+rect -371 249 -275 283
+rect 275 249 371 283
+rect -371 187 -337 249
+rect 337 187 371 249
+rect -206 147 -177 181
+rect 181 147 206 181
+rect -257 88 -223 104
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+rect -161 88 -127 104
+rect -161 -104 -127 -88
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+rect 31 88 65 104
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+rect 127 88 161 104
+rect 127 -104 161 -88
+rect 223 88 257 104
+rect 223 -104 257 -88
+rect -371 -249 -337 -187
+rect 337 -249 371 -187
+rect -371 -283 -275 -249
+rect 275 -283 371 -249
+<< viali >>
+rect -177 147 181 181
+rect -257 -88 -223 88
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+rect 223 -88 257 88
+<< metal1 >>
+rect -199 181 200 187
+rect -206 147 -177 181
+rect 181 147 206 181
+rect -199 141 200 147
+rect -263 88 -217 100
+rect -263 -88 -257 88
+rect -223 -88 -217 88
+rect -263 -100 -217 -88
+rect -167 88 -121 100
+rect -167 -88 -161 88
+rect -127 -88 -121 88
+rect -167 -100 -121 -88
+rect -71 88 -25 100
+rect -71 -88 -65 88
+rect -31 -88 -25 88
+rect -71 -100 -25 -88
+rect 25 88 71 100
+rect 25 -88 31 88
+rect 65 -88 71 88
+rect 25 -100 71 -88
+rect 121 88 167 100
+rect 121 -88 127 88
+rect 161 -88 167 88
+rect 121 -100 167 -88
+rect 217 88 263 100
+rect 217 -88 223 88
+rect 257 -88 263 88
+rect 217 -100 263 -88
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -354 -266 354 266
+string parameters w 1 l 0.15 m 1 nf 5 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_4798MH.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_4798MH.mag
new file mode 100644
index 0000000..5285d6f
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_4798MH.mag
@@ -0,0 +1,93 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< nwell >>
+rect -311 -344 311 344
+<< pmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< pdiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< pdiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< nsubdiff >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< nsubdiffcont >>
+rect -179 274 179 308
+rect -275 -212 -241 212
+rect 241 -212 275 212
+<< poly >>
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -156 -81 -125
+rect -15 -156 15 -125
+rect 81 -156 111 -125
+<< locali >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
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+rect -71 -125 -25 -113
+rect 25 113 71 125
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+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -258 -291 258 291
+string parameters w 1.25 l 0.15 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_5S2X3B.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_5S2X3B.mag
new file mode 100644
index 0000000..4b2c34e
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_5S2X3B.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623899171
+<< error_p >>
+rect 19 192 77 198
+rect 19 158 31 192
+rect 19 152 77 158
+rect -77 -158 -19 -152
+rect -77 -192 -65 -158
+rect -77 -198 -19 -192
+<< nwell >>
+rect -65 173 161 211
+rect -161 -173 161 173
+rect -161 -211 65 -173
+<< pmos >>
+rect -63 -111 -33 111
+rect 33 -111 63 111
+<< pdiff >>
+rect -125 99 -63 111
+rect -125 -99 -113 99
+rect -79 -99 -63 99
+rect -125 -111 -63 -99
+rect -33 99 33 111
+rect -33 -99 -17 99
+rect 17 -99 33 99
+rect -33 -111 33 -99
+rect 63 99 125 111
+rect 63 -99 79 99
+rect 113 -99 125 99
+rect 63 -111 125 -99
+<< pdiffc >>
+rect -113 -99 -79 99
+rect -17 -99 17 99
+rect 79 -99 113 99
+<< poly >>
+rect 15 192 81 208
+rect 15 158 31 192
+rect 65 158 81 192
+rect 15 142 81 158
+rect -63 111 -33 137
+rect 33 111 63 142
+rect -63 -142 -33 -111
+rect 33 -137 63 -111
+rect -81 -158 -15 -142
+rect -81 -192 -65 -158
+rect -31 -192 -15 -158
+rect -81 -208 -15 -192
+<< polycont >>
+rect 31 158 65 192
+rect -65 -192 -31 -158
+<< locali >>
+rect 15 158 31 192
+rect 65 158 81 192
+rect -113 99 -79 115
+rect -113 -115 -79 -99
+rect -17 99 17 115
+rect -17 -115 17 -99
+rect 79 99 113 115
+rect 79 -115 113 -99
+rect -81 -192 -65 -158
+rect -31 -192 -15 -158
+<< viali >>
+rect 31 158 65 192
+rect -113 -99 -79 99
+rect -17 -99 17 99
+rect 79 -99 113 99
+rect -65 -192 -31 -158
+<< metal1 >>
+rect 19 192 77 198
+rect 19 158 31 192
+rect 65 158 77 192
+rect 19 152 77 158
+rect -119 99 -73 111
+rect -119 -99 -113 99
+rect -79 -99 -73 99
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+rect -23 99 23 111
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+rect 73 -111 119 -99
+rect -77 -158 -19 -152
+rect -77 -192 -65 -158
+rect -31 -192 -19 -158
+rect -77 -198 -19 -192
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 1.11 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_6RX2PQ.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_6RX2PQ.mag
new file mode 100644
index 0000000..0d4ab3c
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_6RX2PQ.mag
@@ -0,0 +1,82 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623938174
+<< error_p >>
+rect -29 -95 29 -89
+rect -29 -129 -17 -95
+rect -29 -135 29 -129
+<< nwell >>
+rect -211 -268 211 268
+<< pmos >>
+rect -15 -48 15 120
+<< pdiff >>
+rect -73 108 -15 120
+rect -73 -36 -61 108
+rect -27 -36 -15 108
+rect -73 -48 -15 -36
+rect 15 108 73 120
+rect 15 -36 27 108
+rect 61 -36 73 108
+rect 15 -48 73 -36
+<< pdiffc >>
+rect -61 -36 -27 108
+rect 27 -36 61 108
+<< nsubdiff >>
+rect -175 198 -79 232
+rect 79 198 175 232
+rect -175 135 -141 198
+rect 141 135 175 198
+rect -175 -198 -141 -135
+rect 141 -198 175 -135
+rect -175 -232 175 -198
+<< nsubdiffcont >>
+rect -79 198 79 232
+rect -175 -135 -141 135
+rect 141 -135 175 135
+<< poly >>
+rect -15 120 15 146
+rect -15 -79 15 -48
+rect -33 -95 33 -79
+rect -33 -129 -17 -95
+rect 17 -129 33 -95
+rect -33 -145 33 -129
+<< polycont >>
+rect -17 -129 17 -95
+<< locali >>
+rect -175 198 -79 232
+rect 79 198 175 232
+rect -175 135 -141 198
+rect 141 135 175 198
+rect -61 108 -27 124
+rect -61 -52 -27 -36
+rect 27 108 61 124
+rect 27 -52 61 -36
+rect -33 -129 -17 -95
+rect 17 -129 33 -95
+rect -175 -198 -141 -135
+rect 141 -198 175 -135
+rect -175 -232 175 -198
+<< viali >>
+rect -61 -36 -27 108
+rect 27 -36 61 108
+rect -17 -129 17 -95
+<< metal1 >>
+rect -67 108 -21 120
+rect -67 -36 -61 108
+rect -27 -36 -21 108
+rect -67 -48 -21 -36
+rect 21 108 67 120
+rect 21 -36 27 108
+rect 61 -36 67 108
+rect 21 -48 67 -36
+rect -29 -95 29 -89
+rect -29 -129 -17 -95
+rect 17 -129 29 -95
+rect -29 -135 29 -129
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -215 158 215
+string parameters w 0.84 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_6ZK7MK.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_6ZK7MK.mag
new file mode 100644
index 0000000..c537b69
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_6ZK7MK.mag
@@ -0,0 +1,106 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623899171
+<< error_p >>
+rect 19 192 77 198
+rect 19 158 31 192
+rect 19 152 77 158
+rect -77 -158 -19 -152
+rect -77 -192 -65 -158
+rect -77 -198 -19 -192
+<< nwell >>
+rect -263 -330 263 330
+<< pmos >>
+rect -63 -111 -33 111
+rect 33 -111 63 111
+<< pdiff >>
+rect -125 99 -63 111
+rect -125 -99 -113 99
+rect -79 -99 -63 99
+rect -125 -111 -63 -99
+rect -33 99 33 111
+rect -33 -99 -17 99
+rect 17 -99 33 99
+rect -33 -111 33 -99
+rect 63 99 125 111
+rect 63 -99 79 99
+rect 113 -99 125 99
+rect 63 -111 125 -99
+<< pdiffc >>
+rect -113 -99 -79 99
+rect -17 -99 17 99
+rect 79 -99 113 99
+<< nsubdiff >>
+rect -227 260 227 294
+rect -227 -260 -193 260
+rect 193 -260 227 260
+rect -227 -294 -131 -260
+rect 131 -294 227 -260
+<< nsubdiffcont >>
+rect -131 -294 131 -260
+<< poly >>
+rect 15 192 81 208
+rect 15 158 31 192
+rect 65 158 81 192
+rect 15 142 81 158
+rect -63 111 -33 137
+rect 33 111 63 142
+rect -63 -142 -33 -111
+rect 33 -137 63 -111
+rect -81 -158 -15 -142
+rect -81 -192 -65 -158
+rect -31 -192 -15 -158
+rect -81 -208 -15 -192
+<< polycont >>
+rect 31 158 65 192
+rect -65 -192 -31 -158
+<< locali >>
+rect -227 260 227 294
+rect -227 -260 -193 260
+rect 15 158 31 192
+rect 65 158 81 192
+rect -113 99 -79 115
+rect -113 -115 -79 -99
+rect -17 99 17 115
+rect -17 -115 17 -99
+rect 79 99 113 115
+rect 79 -115 113 -99
+rect -81 -192 -65 -158
+rect -31 -192 -15 -158
+rect 193 -260 227 260
+rect -227 -294 -131 -260
+rect 131 -294 227 -260
+<< viali >>
+rect 31 158 65 192
+rect -113 -99 -79 99
+rect -17 -99 17 99
+rect 79 -99 113 99
+rect -65 -192 -31 -158
+<< metal1 >>
+rect 19 192 77 198
+rect 19 158 31 192
+rect 65 158 77 192
+rect 19 152 77 158
+rect -119 99 -73 111
+rect -119 -99 -113 99
+rect -79 -99 -73 99
+rect -119 -111 -73 -99
+rect -23 99 23 111
+rect -23 -99 -17 99
+rect 17 -99 23 99
+rect -23 -111 23 -99
+rect 73 99 119 111
+rect 73 -99 79 99
+rect 113 -99 119 99
+rect 73 -111 119 -99
+rect -77 -158 -19 -152
+rect -77 -192 -65 -158
+rect -31 -192 -19 -158
+rect -77 -198 -19 -192
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -277 210 277
+string parameters w 1.11 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 0 grc 0 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_6ZZL9K.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_6ZZL9K.mag
new file mode 100644
index 0000000..a979b27
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_6ZZL9K.mag
@@ -0,0 +1,172 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623431064
+<< error_p >>
+rect -77 123 -19 129
+rect 115 123 173 129
+rect -77 89 -65 123
+rect 115 89 127 123
+rect -77 83 -19 89
+rect 115 83 173 89
+rect -173 -89 -115 -83
+rect 19 -89 77 -83
+rect -173 -123 -161 -89
+rect 19 -123 31 -89
+rect -173 -129 -115 -123
+rect 19 -129 77 -123
+<< nwell >>
+rect -359 -261 359 261
+<< pmos >>
+rect -159 -42 -129 42
+rect -63 -42 -33 42
+rect 33 -42 63 42
+rect 129 -42 159 42
+<< pdiff >>
+rect -221 30 -159 42
+rect -221 -30 -209 30
+rect -175 -30 -159 30
+rect -221 -42 -159 -30
+rect -129 30 -63 42
+rect -129 -30 -113 30
+rect -79 -30 -63 30
+rect -129 -42 -63 -30
+rect -33 30 33 42
+rect -33 -30 -17 30
+rect 17 -30 33 30
+rect -33 -42 33 -30
+rect 63 30 129 42
+rect 63 -30 79 30
+rect 113 -30 129 30
+rect 63 -42 129 -30
+rect 159 30 221 42
+rect 159 -30 175 30
+rect 209 -30 221 30
+rect 159 -42 221 -30
+<< pdiffc >>
+rect -209 -30 -175 30
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+rect 175 -30 209 30
+<< nsubdiff >>
+rect -323 191 323 225
+rect -323 129 -289 191
+rect 289 129 323 191
+rect -323 -191 -289 -129
+rect 289 -191 323 -129
+rect -323 -225 -227 -191
+rect 227 -225 323 -191
+<< nsubdiffcont >>
+rect -323 -129 -289 129
+rect 289 -129 323 129
+rect -227 -225 227 -191
+<< poly >>
+rect -81 123 -15 139
+rect -81 89 -65 123
+rect -31 89 -15 123
+rect -81 73 -15 89
+rect 111 123 177 139
+rect 111 89 127 123
+rect 161 89 177 123
+rect 111 73 177 89
+rect -159 42 -129 68
+rect -63 42 -33 73
+rect 33 42 63 68
+rect 129 42 159 73
+rect -159 -73 -129 -42
+rect -63 -68 -33 -42
+rect 33 -73 63 -42
+rect 129 -68 159 -42
+rect -177 -89 -111 -73
+rect -177 -123 -161 -89
+rect -127 -123 -111 -89
+rect -177 -139 -111 -123
+rect 15 -89 81 -73
+rect 15 -123 31 -89
+rect 65 -123 81 -89
+rect 15 -139 81 -123
+<< polycont >>
+rect -65 89 -31 123
+rect 127 89 161 123
+rect -161 -123 -127 -89
+rect 31 -123 65 -89
+<< locali >>
+rect -323 191 323 225
+rect -323 129 -289 191
+rect 289 129 323 191
+rect -81 89 -65 123
+rect -31 89 -15 123
+rect 111 89 127 123
+rect 161 89 177 123
+rect -209 30 -175 46
+rect -209 -46 -175 -30
+rect -113 30 -79 46
+rect -113 -46 -79 -30
+rect -17 30 17 46
+rect -17 -46 17 -30
+rect 79 30 113 46
+rect 79 -46 113 -30
+rect 175 30 209 46
+rect 175 -46 209 -30
+rect -177 -123 -161 -89
+rect -127 -123 -111 -89
+rect 15 -123 31 -89
+rect 65 -123 81 -89
+rect -323 -191 -289 -129
+rect 289 -191 323 -129
+rect -323 -225 -227 -191
+rect 227 -225 323 -191
+<< viali >>
+rect -65 89 -31 123
+rect 127 89 161 123
+rect -209 -30 -175 30
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+rect 175 -30 209 30
+rect -161 -123 -127 -89
+rect 31 -123 65 -89
+<< metal1 >>
+rect -77 123 -19 129
+rect -77 89 -65 123
+rect -31 89 -19 123
+rect -77 83 -19 89
+rect 115 123 173 129
+rect 115 89 127 123
+rect 161 89 173 123
+rect 115 83 173 89
+rect -215 30 -169 42
+rect -215 -30 -209 30
+rect -175 -30 -169 30
+rect -215 -42 -169 -30
+rect -119 30 -73 42
+rect -119 -30 -113 30
+rect -79 -30 -73 30
+rect -119 -42 -73 -30
+rect -23 30 23 42
+rect -23 -30 -17 30
+rect 17 -30 23 30
+rect -23 -42 23 -30
+rect 73 30 119 42
+rect 73 -30 79 30
+rect 113 -30 119 30
+rect 73 -42 119 -30
+rect 169 30 215 42
+rect 169 -30 175 30
+rect 209 -30 215 30
+rect 169 -42 215 -30
+rect -173 -89 -115 -83
+rect -173 -123 -161 -89
+rect -127 -123 -115 -89
+rect -173 -129 -115 -123
+rect 19 -89 77 -83
+rect 19 -123 31 -89
+rect 65 -123 77 -89
+rect 19 -129 77 -123
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -306 -208 306 208
+string parameters w 0.42 l 0.15 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_75PKJG.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_75PKJG.mag
new file mode 100644
index 0000000..95d6000
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_75PKJG.mag
@@ -0,0 +1,110 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623948006
+<< nwell >>
+rect -359 -321 359 321
+<< pmos >>
+rect -159 -102 -129 102
+rect -63 -102 -33 102
+rect 33 -102 63 102
+rect 129 -102 159 102
+<< pdiff >>
+rect -221 90 -159 102
+rect -221 -90 -209 90
+rect -175 -90 -159 90
+rect -221 -102 -159 -90
+rect -129 90 -63 102
+rect -129 -90 -113 90
+rect -79 -90 -63 90
+rect -129 -102 -63 -90
+rect -33 90 33 102
+rect -33 -90 -17 90
+rect 17 -90 33 90
+rect -33 -102 33 -90
+rect 63 90 129 102
+rect 63 -90 79 90
+rect 113 -90 129 90
+rect 63 -102 129 -90
+rect 159 90 221 102
+rect 159 -90 175 90
+rect 209 -90 221 90
+rect 159 -102 221 -90
+<< pdiffc >>
+rect -209 -90 -175 90
+rect -113 -90 -79 90
+rect -17 -90 17 90
+rect 79 -90 113 90
+rect 175 -90 209 90
+<< nsubdiff >>
+rect -323 251 -227 285
+rect 227 251 323 285
+rect -323 189 -289 251
+rect 289 189 323 251
+rect -323 -285 -289 -189
+rect 289 -285 323 -189
+<< nsubdiffcont >>
+rect -227 251 227 285
+rect -323 -189 -289 189
+rect 289 -189 323 189
+<< poly >>
+rect -159 102 -129 128
+rect -63 102 -33 128
+rect 33 102 63 128
+rect 129 102 159 128
+rect -159 -133 -129 -102
+rect -63 -133 -33 -102
+rect 33 -133 63 -102
+rect 129 -133 159 -102
+rect -177 -199 -25 -133
+rect 25 -199 177 -133
+<< locali >>
+rect -323 251 -227 285
+rect 227 251 323 285
+rect -323 189 -289 251
+rect 289 189 323 251
+rect -209 90 -175 106
+rect -209 -106 -175 -90
+rect -113 90 -79 106
+rect -113 -106 -79 -90
+rect -17 90 17 106
+rect -17 -106 17 -90
+rect 79 90 113 106
+rect 79 -106 113 -90
+rect 175 90 209 106
+rect 175 -106 209 -90
+rect -323 -285 -289 -189
+rect 289 -285 323 -189
+<< viali >>
+rect -209 -90 -175 90
+rect -113 -90 -79 90
+rect -17 -90 17 90
+rect 79 -90 113 90
+rect 175 -90 209 90
+<< metal1 >>
+rect -215 90 -169 102
+rect -215 -90 -209 90
+rect -175 -90 -169 90
+rect -215 -102 -169 -90
+rect -119 90 -73 102
+rect -119 -90 -113 90
+rect -79 -90 -73 90
+rect -119 -102 -73 -90
+rect -23 90 23 102
+rect -23 -90 -17 90
+rect 17 -90 23 90
+rect -23 -102 23 -90
+rect 73 90 119 102
+rect 73 -90 79 90
+rect 113 -90 119 90
+rect 73 -102 119 -90
+rect 169 90 215 102
+rect 169 -90 175 90
+rect 209 -90 215 90
+rect 169 -102 215 -90
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -306 -268 306 268
+string parameters w 1.02 l 0.15 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_7KT7MH.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_7KT7MH.mag
new file mode 100644
index 0000000..bb965f5
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_7KT7MH.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< nwell >>
+rect -311 -344 311 344
+<< pmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< pdiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< pdiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< nsubdiff >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< nsubdiffcont >>
+rect -179 274 179 308
+rect -275 -212 -241 212
+rect 241 -212 275 212
+<< poly >>
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -156 -81 -125
+rect -15 -156 15 -125
+rect 81 -156 111 -125
+rect -111 -186 111 -156
+<< locali >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -258 -291 258 291
+string parameters w 1.25 l 0.15 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_BDRUME.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_BDRUME.mag
new file mode 100644
index 0000000..02ab193
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_BDRUME.mag
@@ -0,0 +1,290 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624046389
+<< nwell >>
+rect -935 -303 935 303
+<< pmos >>
+rect -735 -84 -705 84
+rect -639 -84 -609 84
+rect -543 -84 -513 84
+rect -447 -84 -417 84
+rect -351 -84 -321 84
+rect -255 -84 -225 84
+rect -159 -84 -129 84
+rect -63 -84 -33 84
+rect 33 -84 63 84
+rect 129 -84 159 84
+rect 225 -84 255 84
+rect 321 -84 351 84
+rect 417 -84 447 84
+rect 513 -84 543 84
+rect 609 -84 639 84
+rect 705 -84 735 84
+<< pdiff >>
+rect -797 72 -735 84
+rect -797 -72 -785 72
+rect -751 -72 -735 72
+rect -797 -84 -735 -72
+rect -705 72 -639 84
+rect -705 -72 -689 72
+rect -655 -72 -639 72
+rect -705 -84 -639 -72
+rect -609 72 -543 84
+rect -609 -72 -593 72
+rect -559 -72 -543 72
+rect -609 -84 -543 -72
+rect -513 72 -447 84
+rect -513 -72 -497 72
+rect -463 -72 -447 72
+rect -513 -84 -447 -72
+rect -417 72 -351 84
+rect -417 -72 -401 72
+rect -367 -72 -351 72
+rect -417 -84 -351 -72
+rect -321 72 -255 84
+rect -321 -72 -305 72
+rect -271 -72 -255 72
+rect -321 -84 -255 -72
+rect -225 72 -159 84
+rect -225 -72 -209 72
+rect -175 -72 -159 72
+rect -225 -84 -159 -72
+rect -129 72 -63 84
+rect -129 -72 -113 72
+rect -79 -72 -63 72
+rect -129 -84 -63 -72
+rect -33 72 33 84
+rect -33 -72 -17 72
+rect 17 -72 33 72
+rect -33 -84 33 -72
+rect 63 72 129 84
+rect 63 -72 79 72
+rect 113 -72 129 72
+rect 63 -84 129 -72
+rect 159 72 225 84
+rect 159 -72 175 72
+rect 209 -72 225 72
+rect 159 -84 225 -72
+rect 255 72 321 84
+rect 255 -72 271 72
+rect 305 -72 321 72
+rect 255 -84 321 -72
+rect 351 72 417 84
+rect 351 -72 367 72
+rect 401 -72 417 72
+rect 351 -84 417 -72
+rect 447 72 513 84
+rect 447 -72 463 72
+rect 497 -72 513 72
+rect 447 -84 513 -72
+rect 543 72 609 84
+rect 543 -72 559 72
+rect 593 -72 609 72
+rect 543 -84 609 -72
+rect 639 72 705 84
+rect 639 -72 655 72
+rect 689 -72 705 72
+rect 639 -84 705 -72
+rect 735 72 797 84
+rect 735 -72 751 72
+rect 785 -72 797 72
+rect 735 -84 797 -72
+<< pdiffc >>
+rect -785 -72 -751 72
+rect -689 -72 -655 72
+rect -593 -72 -559 72
+rect -497 -72 -463 72
+rect -401 -72 -367 72
+rect -305 -72 -271 72
+rect -209 -72 -175 72
+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+rect 175 -72 209 72
+rect 271 -72 305 72
+rect 367 -72 401 72
+rect 463 -72 497 72
+rect 559 -72 593 72
+rect 655 -72 689 72
+rect 751 -72 785 72
+<< nsubdiff >>
+rect -899 233 -803 267
+rect 803 233 899 267
+rect -899 171 -865 233
+rect 865 171 899 233
+rect -899 -267 -865 -171
+rect 865 -267 899 -171
+<< nsubdiffcont >>
+rect -803 233 803 267
+rect -899 -171 -865 171
+rect 865 -171 899 171
+<< poly >>
+rect -752 110 753 181
+rect -735 84 -705 110
+rect -639 84 -609 110
+rect -543 84 -513 110
+rect -447 84 -417 110
+rect -351 84 -321 110
+rect -255 84 -225 110
+rect -159 84 -129 110
+rect -63 84 -33 110
+rect 33 84 63 110
+rect 129 84 159 110
+rect 225 84 255 110
+rect 321 84 351 110
+rect 417 84 447 110
+rect 513 84 543 110
+rect 609 84 639 110
+rect 705 84 735 110
+rect -735 -110 -705 -84
+rect -639 -110 -609 -84
+rect -543 -110 -513 -84
+rect -447 -110 -417 -84
+rect -351 -110 -321 -84
+rect -255 -110 -225 -84
+rect -159 -110 -129 -84
+rect -63 -110 -33 -84
+rect 33 -110 63 -84
+rect 129 -110 159 -84
+rect 225 -110 255 -84
+rect 321 -110 351 -84
+rect 417 -110 447 -84
+rect 513 -110 543 -84
+rect 609 -110 639 -84
+rect 705 -110 735 -84
+rect -753 -181 752 -110
+<< locali >>
+rect -899 233 -803 267
+rect 803 233 899 267
+rect -899 171 -865 233
+rect 865 171 899 233
+rect -785 72 -751 88
+rect -785 -88 -751 -72
+rect -689 72 -655 88
+rect -689 -88 -655 -72
+rect -593 72 -559 88
+rect -593 -88 -559 -72
+rect -497 72 -463 88
+rect -497 -88 -463 -72
+rect -401 72 -367 88
+rect -401 -88 -367 -72
+rect -305 72 -271 88
+rect -305 -88 -271 -72
+rect -209 72 -175 88
+rect -209 -88 -175 -72
+rect -113 72 -79 88
+rect -113 -88 -79 -72
+rect -17 72 17 88
+rect -17 -88 17 -72
+rect 79 72 113 88
+rect 79 -88 113 -72
+rect 175 72 209 88
+rect 175 -88 209 -72
+rect 271 72 305 88
+rect 271 -88 305 -72
+rect 367 72 401 88
+rect 367 -88 401 -72
+rect 463 72 497 88
+rect 463 -88 497 -72
+rect 559 72 593 88
+rect 559 -88 593 -72
+rect 655 72 689 88
+rect 655 -88 689 -72
+rect 751 72 785 88
+rect 751 -88 785 -72
+rect -899 -267 -865 -171
+rect 865 -267 899 -171
+<< viali >>
+rect -785 -72 -751 72
+rect -689 -72 -655 72
+rect -593 -72 -559 72
+rect -497 -72 -463 72
+rect -401 -72 -367 72
+rect -305 -72 -271 72
+rect -209 -72 -175 72
+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+rect 175 -72 209 72
+rect 271 -72 305 72
+rect 367 -72 401 72
+rect 463 -72 497 72
+rect 559 -72 593 72
+rect 655 -72 689 72
+rect 751 -72 785 72
+<< metal1 >>
+rect -791 72 -745 84
+rect -791 -72 -785 72
+rect -751 -72 -745 72
+rect -791 -84 -745 -72
+rect -695 72 -649 84
+rect -695 -72 -689 72
+rect -655 -72 -649 72
+rect -695 -84 -649 -72
+rect -599 72 -553 84
+rect -599 -72 -593 72
+rect -559 -72 -553 72
+rect -599 -84 -553 -72
+rect -503 72 -457 84
+rect -503 -72 -497 72
+rect -463 -72 -457 72
+rect -503 -84 -457 -72
+rect -407 72 -361 84
+rect -407 -72 -401 72
+rect -367 -72 -361 72
+rect -407 -84 -361 -72
+rect -311 72 -265 84
+rect -311 -72 -305 72
+rect -271 -72 -265 72
+rect -311 -84 -265 -72
+rect -215 72 -169 84
+rect -215 -72 -209 72
+rect -175 -72 -169 72
+rect -215 -84 -169 -72
+rect -119 72 -73 84
+rect -119 -72 -113 72
+rect -79 -72 -73 72
+rect -119 -84 -73 -72
+rect -23 72 23 84
+rect -23 -72 -17 72
+rect 17 -72 23 72
+rect -23 -84 23 -72
+rect 73 72 119 84
+rect 73 -72 79 72
+rect 113 -72 119 72
+rect 73 -84 119 -72
+rect 169 72 215 84
+rect 169 -72 175 72
+rect 209 -72 215 72
+rect 169 -84 215 -72
+rect 265 72 311 84
+rect 265 -72 271 72
+rect 305 -72 311 72
+rect 265 -84 311 -72
+rect 361 72 407 84
+rect 361 -72 367 72
+rect 401 -72 407 72
+rect 361 -84 407 -72
+rect 457 72 503 84
+rect 457 -72 463 72
+rect 497 -72 503 72
+rect 457 -84 503 -72
+rect 553 72 599 84
+rect 553 -72 559 72
+rect 593 -72 599 72
+rect 553 -84 599 -72
+rect 649 72 695 84
+rect 649 -72 655 72
+rect 689 -72 695 72
+rect 649 -84 695 -72
+rect 745 72 791 84
+rect 745 -72 751 72
+rect 785 -72 791 72
+rect 745 -84 791 -72
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -882 -250 882 250
+string parameters w 0.84 l 0.15 m 1 nf 16 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_KZ6ZMQ.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_KZ6ZMQ.mag
new file mode 100644
index 0000000..ffd0b4a
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_KZ6ZMQ.mag
@@ -0,0 +1,112 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623899171
+<< error_p >>
+rect 19 192 77 198
+rect 19 158 31 192
+rect 19 152 77 158
+rect -77 -158 -19 -152
+rect -77 -192 -65 -158
+rect -77 -198 -19 -192
+<< nwell >>
+rect -263 -330 263 330
+<< pmos >>
+rect -63 -111 -33 111
+rect 33 -111 63 111
+<< pdiff >>
+rect -125 99 -63 111
+rect -125 -99 -113 99
+rect -79 -99 -63 99
+rect -125 -111 -63 -99
+rect -33 99 33 111
+rect -33 -99 -17 99
+rect 17 -99 33 99
+rect -33 -111 33 -99
+rect 63 99 125 111
+rect 63 -99 79 99
+rect 113 -99 125 99
+rect 63 -111 125 -99
+<< pdiffc >>
+rect -113 -99 -79 99
+rect -17 -99 17 99
+rect 79 -99 113 99
+<< nsubdiff >>
+rect -227 260 227 294
+rect -227 198 -193 260
+rect 193 198 227 260
+rect -227 -260 -193 -198
+rect 193 -260 227 -198
+rect -227 -294 -131 -260
+rect 131 -294 227 -260
+<< nsubdiffcont >>
+rect -227 -198 -193 198
+rect 193 -198 227 198
+rect -131 -294 131 -260
+<< poly >>
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+rect 15 158 31 192
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+rect -63 111 -33 137
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+rect -63 -142 -33 -111
+rect 33 -137 63 -111
+rect -81 -158 -15 -142
+rect -81 -192 -65 -158
+rect -31 -192 -15 -158
+rect -81 -208 -15 -192
+<< polycont >>
+rect 31 158 65 192
+rect -65 -192 -31 -158
+<< locali >>
+rect -227 260 227 294
+rect -227 198 -193 260
+rect 193 198 227 260
+rect 15 158 31 192
+rect 65 158 81 192
+rect -113 99 -79 115
+rect -113 -115 -79 -99
+rect -17 99 17 115
+rect -17 -115 17 -99
+rect 79 99 113 115
+rect 79 -115 113 -99
+rect -81 -192 -65 -158
+rect -31 -192 -15 -158
+rect -227 -260 -193 -198
+rect 193 -260 227 -198
+rect -227 -294 -131 -260
+rect 131 -294 227 -260
+<< viali >>
+rect 31 158 65 192
+rect -113 -99 -79 99
+rect -17 -99 17 99
+rect 79 -99 113 99
+rect -65 -192 -31 -158
+<< metal1 >>
+rect 19 192 77 198
+rect 19 158 31 192
+rect 65 158 77 192
+rect 19 152 77 158
+rect -119 99 -73 111
+rect -119 -99 -113 99
+rect -79 -99 -73 99
+rect -119 -111 -73 -99
+rect -23 99 23 111
+rect -23 -99 -17 99
+rect 17 -99 23 99
+rect -23 -111 23 -99
+rect 73 99 119 111
+rect 73 -99 79 99
+rect 113 -99 119 99
+rect 73 -111 119 -99
+rect -77 -158 -19 -152
+rect -77 -192 -65 -158
+rect -31 -192 -19 -158
+rect -77 -198 -19 -192
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -277 210 277
+string parameters w 1.11 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_MA7ZZL.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_MA7ZZL.mag
new file mode 100644
index 0000000..d86fa8a
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_MA7ZZL.mag
@@ -0,0 +1,115 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623899171
+<< error_p >>
+rect 19 192 77 198
+rect 19 158 31 192
+rect 19 152 77 158
+rect -77 -158 -19 -152
+rect -77 -192 -65 -158
+rect -77 -198 -19 -192
+<< nwell >>
+rect -263 -330 263 330
+<< pmos >>
+rect -63 -111 -33 111
+rect 33 -111 63 111
+<< pdiff >>
+rect -125 99 -63 111
+rect -125 -99 -113 99
+rect -79 -99 -63 99
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+rect 63 99 125 111
+rect 63 -99 79 99
+rect 113 -99 125 99
+rect 63 -111 125 -99
+<< pdiffc >>
+rect -113 -99 -79 99
+rect -17 -99 17 99
+rect 79 -99 113 99
+<< nsubdiff >>
+rect -227 260 -131 294
+rect 131 260 227 294
+rect -227 198 -193 260
+rect 193 198 227 260
+rect -227 -260 -193 -198
+rect 193 -260 227 -198
+rect -227 -294 -131 -260
+rect 131 -294 227 -260
+<< nsubdiffcont >>
+rect -131 260 131 294
+rect -227 -198 -193 198
+rect 193 -198 227 198
+rect -131 -294 131 -260
+<< poly >>
+rect 15 192 81 208
+rect 15 158 31 192
+rect 65 158 81 192
+rect 15 142 81 158
+rect -63 111 -33 137
+rect 33 111 63 142
+rect -63 -142 -33 -111
+rect 33 -137 63 -111
+rect -81 -158 -15 -142
+rect -81 -192 -65 -158
+rect -31 -192 -15 -158
+rect -81 -208 -15 -192
+<< polycont >>
+rect 31 158 65 192
+rect -65 -192 -31 -158
+<< locali >>
+rect -227 260 -131 294
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+rect 193 198 227 260
+rect 15 158 31 192
+rect 65 158 81 192
+rect -113 99 -79 115
+rect -113 -115 -79 -99
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+rect -227 -294 -131 -260
+rect 131 -294 227 -260
+<< viali >>
+rect 31 158 65 192
+rect -113 -99 -79 99
+rect -17 -99 17 99
+rect 79 -99 113 99
+rect -65 -192 -31 -158
+<< metal1 >>
+rect 19 192 77 198
+rect 19 158 31 192
+rect 65 158 77 192
+rect 19 152 77 158
+rect -119 99 -73 111
+rect -119 -99 -113 99
+rect -79 -99 -73 99
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+rect 73 -111 119 -99
+rect -77 -158 -19 -152
+rect -77 -192 -65 -158
+rect -31 -192 -19 -158
+rect -77 -198 -19 -192
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -277 210 277
+string parameters w 1.11 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 1 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_MJG8BZ.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_MJG8BZ.mag
new file mode 100644
index 0000000..f89ab31
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_MJG8BZ.mag
@@ -0,0 +1,79 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< nwell >>
+rect -263 -314 263 314
+<< pmos >>
+rect -63 -95 -33 95
+rect 33 -95 63 95
+<< pdiff >>
+rect -125 83 -63 95
+rect -125 -83 -113 83
+rect -79 -83 -63 83
+rect -125 -95 -63 -83
+rect -33 83 33 95
+rect -33 -83 -17 83
+rect 17 -83 33 83
+rect -33 -95 33 -83
+rect 63 83 125 95
+rect 63 -83 79 83
+rect 113 -83 125 83
+rect 63 -95 125 -83
+<< pdiffc >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+<< nsubdiff >>
+rect -227 244 -131 278
+rect 131 244 227 278
+rect -227 182 -193 244
+rect 193 182 227 244
+rect -227 -244 -193 -182
+rect 193 -244 227 -182
+<< nsubdiffcont >>
+rect -131 244 131 278
+rect -227 -182 -193 182
+rect 193 -182 227 182
+<< poly >>
+rect -63 95 -33 121
+rect 33 95 63 121
+rect -63 -126 -33 -95
+rect 33 -126 63 -95
+rect -63 -192 63 -126
+<< locali >>
+rect -227 244 -131 278
+rect 131 244 227 278
+rect -227 182 -193 244
+rect 193 182 227 244
+rect -113 83 -79 99
+rect -113 -99 -79 -83
+rect -17 83 17 99
+rect -17 -99 17 -83
+rect 79 83 113 99
+rect 79 -99 113 -83
+rect -227 -244 -193 -182
+rect 193 -244 227 -182
+<< viali >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+<< metal1 >>
+rect -119 83 -73 95
+rect -119 -83 -113 83
+rect -79 -83 -73 83
+rect -119 -95 -73 -83
+rect -23 83 23 95
+rect -23 -83 -17 83
+rect 17 -83 23 83
+rect -23 -95 23 -83
+rect 73 83 119 95
+rect 73 -83 79 83
+rect 113 -83 119 83
+rect 73 -95 119 -83
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -261 210 261
+string parameters w 0.95 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_VCU74W.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_VCU74W.mag
new file mode 100644
index 0000000..78fa107
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_VCU74W.mag
@@ -0,0 +1,347 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623969746
+<< nwell >>
+rect -887 -319 887 319
+<< pmos >>
+rect -687 -100 -657 100
+rect -591 -100 -561 100
+rect -495 -100 -465 100
+rect -399 -100 -369 100
+rect -303 -100 -273 100
+rect -207 -100 -177 100
+rect -111 -100 -81 100
+rect -15 -100 15 100
+rect 81 -100 111 100
+rect 177 -100 207 100
+rect 273 -100 303 100
+rect 369 -100 399 100
+rect 465 -100 495 100
+rect 561 -100 591 100
+rect 657 -100 687 100
+<< pdiff >>
+rect -749 88 -687 100
+rect -749 -88 -737 88
+rect -703 -88 -687 88
+rect -749 -100 -687 -88
+rect -657 88 -591 100
+rect -657 -88 -641 88
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+rect 687 88 749 100
+rect 687 -88 703 88
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+rect 687 -100 749 -88
+<< pdiffc >>
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+rect -353 -88 -319 88
+rect -257 -88 -223 88
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+rect 607 -88 641 88
+rect 703 -88 737 88
+<< nsubdiff >>
+rect -851 249 -755 283
+rect 755 249 851 283
+rect -851 187 -817 249
+rect 817 187 851 249
+rect -851 -249 -817 -187
+rect 817 -249 851 -187
+rect -851 -283 -755 -249
+rect 755 -283 851 -249
+<< nsubdiffcont >>
+rect -755 249 755 283
+rect -851 -187 -817 187
+rect 817 -187 851 187
+rect -755 -283 755 -249
+<< poly >>
+rect -687 100 -657 126
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+rect -399 100 -369 126
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+rect -207 100 -177 126
+rect -111 100 -81 126
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+rect -495 -131 -465 -100
+rect -399 -131 -369 -100
+rect -303 -131 -273 -100
+rect -207 -131 -177 -100
+rect -111 -131 -81 -100
+rect -15 -131 15 -100
+rect 81 -131 111 -100
+rect 177 -131 207 -100
+rect 273 -131 303 -100
+rect 369 -131 399 -100
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+rect 401 -181 463 -147
+rect 497 -181 559 -147
+rect 593 -181 655 -147
+rect 689 -181 705 -147
+rect -705 -197 705 -181
+<< polycont >>
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+rect -593 -181 -559 -147
+rect -497 -181 -463 -147
+rect -401 -181 -367 -147
+rect -305 -181 -271 -147
+rect -209 -181 -175 -147
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+rect -17 -181 17 -147
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+rect 175 -181 209 -147
+rect 271 -181 305 -147
+rect 367 -181 401 -147
+rect 463 -181 497 -147
+rect 559 -181 593 -147
+rect 655 -181 689 -147
+<< locali >>
+rect -851 249 -755 283
+rect 755 249 851 283
+rect -851 187 -817 249
+rect 817 187 851 249
+rect -737 88 -703 104
+rect -737 -104 -703 -88
+rect -641 88 -607 104
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+rect -851 -249 -817 -187
+rect 817 -249 851 -187
+rect -851 -283 -755 -249
+rect 755 -283 851 -249
+<< viali >>
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+rect -641 -88 -607 88
+rect -545 -88 -511 88
+rect -449 -88 -415 88
+rect -353 -88 -319 88
+rect -257 -88 -223 88
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+rect 607 -88 641 88
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+rect -463 -181 -401 -147
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+rect 497 -181 559 -147
+rect 559 -181 593 -147
+rect 593 -181 655 -147
+rect 655 -181 689 -147
+<< metal1 >>
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+rect -743 -88 -737 88
+rect -703 -88 -697 88
+rect -743 -100 -697 -88
+rect -647 88 -601 100
+rect -647 -88 -641 88
+rect -607 -88 -601 88
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+rect -551 88 -505 100
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+rect -511 -88 -505 88
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+rect -455 88 -409 100
+rect -455 -88 -449 88
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+rect -359 88 -313 100
+rect -359 -88 -353 88
+rect -319 -88 -313 88
+rect -359 -100 -313 -88
+rect -263 88 -217 100
+rect -263 -88 -257 88
+rect -223 -88 -217 88
+rect -263 -100 -217 -88
+rect -167 88 -121 100
+rect -167 -88 -161 88
+rect -127 -88 -121 88
+rect -167 -100 -121 -88
+rect -71 88 -25 100
+rect -71 -88 -65 88
+rect -31 -88 -25 88
+rect -71 -100 -25 -88
+rect 25 88 71 100
+rect 25 -88 31 88
+rect 65 -88 71 88
+rect 25 -100 71 -88
+rect 121 88 167 100
+rect 121 -88 127 88
+rect 161 -88 167 88
+rect 121 -100 167 -88
+rect 217 88 263 100
+rect 217 -88 223 88
+rect 257 -88 263 88
+rect 217 -100 263 -88
+rect 313 88 359 100
+rect 313 -88 319 88
+rect 353 -88 359 88
+rect 313 -100 359 -88
+rect 409 88 455 100
+rect 409 -88 415 88
+rect 449 -88 455 88
+rect 409 -100 455 -88
+rect 505 88 551 100
+rect 505 -88 511 88
+rect 545 -88 551 88
+rect 505 -100 551 -88
+rect 601 88 647 100
+rect 601 -88 607 88
+rect 641 -88 647 88
+rect 601 -100 647 -88
+rect 697 88 743 100
+rect 697 -88 703 88
+rect 737 -88 743 88
+rect 697 -100 743 -88
+rect -701 -147 701 -141
+rect -701 -181 -689 -147
+rect 689 -181 701 -147
+rect -701 -187 701 -181
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -834 -266 834 266
+string parameters w 1 l 0.15 m 1 nf 15 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_XA7ZMQ.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_XA7ZMQ.mag
new file mode 100644
index 0000000..cb08cff
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_XA7ZMQ.mag
@@ -0,0 +1,105 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623900471
+<< nwell >>
+rect -263 -330 263 330
+<< pmos >>
+rect -63 -111 -33 111
+rect 33 -111 63 111
+<< pdiff >>
+rect -125 99 -63 111
+rect -125 -99 -113 99
+rect -79 -99 -63 99
+rect -125 -111 -63 -99
+rect -33 99 33 111
+rect -33 -99 -17 99
+rect 17 -99 33 99
+rect -33 -111 33 -99
+rect 63 99 125 111
+rect 63 -99 79 99
+rect 113 -99 125 99
+rect 63 -111 125 -99
+<< pdiffc >>
+rect -113 -99 -79 99
+rect -17 -99 17 99
+rect 79 -99 113 99
+<< nsubdiff >>
+rect -227 260 227 294
+rect -227 198 -193 260
+rect 193 198 227 260
+rect -227 -260 -193 -198
+rect 193 -260 227 -198
+rect -227 -294 -131 -260
+rect 131 -294 227 -260
+<< nsubdiffcont >>
+rect -227 -198 -193 198
+rect 193 -198 227 198
+rect -131 -294 131 -260
+<< poly >>
+rect -87 192 -21 208
+rect -87 158 -71 192
+rect -37 158 -21 192
+rect -87 142 -21 158
+rect 21 192 87 208
+rect 21 158 37 192
+rect 71 158 87 192
+rect 21 142 87 158
+rect -63 111 -33 142
+rect 33 111 63 142
+rect -63 -137 -33 -111
+rect 33 -137 63 -111
+<< polycont >>
+rect -71 158 -37 192
+rect 37 158 71 192
+<< locali >>
+rect -227 260 227 294
+rect -227 198 -193 260
+rect 193 198 227 260
+rect -87 158 -71 192
+rect -37 158 -21 192
+rect 21 158 37 192
+rect 71 158 87 192
+rect -113 99 -79 115
+rect -113 -115 -79 -99
+rect -17 99 17 115
+rect -17 -115 17 -99
+rect 79 99 113 115
+rect 79 -115 113 -99
+rect -227 -260 -193 -198
+rect 193 -260 227 -198
+rect -227 -294 -131 -260
+rect 131 -294 227 -260
+<< viali >>
+rect -71 158 -37 192
+rect 37 158 71 192
+rect -113 -99 -79 99
+rect -17 -99 17 99
+rect 79 -99 113 99
+<< metal1 >>
+rect -87 192 -21 204
+rect -87 158 -71 192
+rect -37 158 -21 192
+rect -87 146 -21 158
+rect 21 192 87 204
+rect 21 158 37 192
+rect 71 158 87 192
+rect 21 146 87 158
+rect -119 99 -73 111
+rect -119 -99 -113 99
+rect -79 -99 -73 99
+rect -119 -111 -73 -99
+rect -23 99 23 111
+rect -23 -99 -17 99
+rect 17 -99 23 99
+rect -23 -111 23 -99
+rect 73 99 119 111
+rect 73 -99 79 99
+rect 113 -99 119 99
+rect 73 -111 119 -99
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -277 210 277
+string parameters w 1.11 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_XACJHL.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_XACJHL.mag
new file mode 100644
index 0000000..7fad39c
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_XACJHL.mag
@@ -0,0 +1,101 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624020979
+<< nwell >>
+rect -263 -319 263 319
+<< pmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< pdiff >>
+rect -125 88 -63 100
+rect -125 -88 -113 88
+rect -79 -88 -63 88
+rect -125 -100 -63 -88
+rect -33 88 33 100
+rect -33 -88 -17 88
+rect 17 -88 33 88
+rect -33 -100 33 -88
+rect 63 88 125 100
+rect 63 -88 79 88
+rect 113 -88 125 88
+rect 63 -100 125 -88
+<< pdiffc >>
+rect -113 -88 -79 88
+rect -17 -88 17 88
+rect 79 -88 113 88
+<< nsubdiff >>
+rect -227 249 -131 283
+rect 131 249 227 283
+rect -227 187 -193 249
+rect 193 187 227 249
+rect -227 -249 -193 -187
+rect 193 -249 227 -187
+rect -227 -283 -131 -249
+rect 131 -283 227 -249
+<< nsubdiffcont >>
+rect -131 249 131 283
+rect -227 -187 -193 187
+rect 193 -187 227 187
+rect -131 -283 131 -249
+<< poly >>
+rect -63 100 -33 126
+rect 33 100 63 126
+rect -63 -131 -33 -100
+rect 33 -131 63 -100
+rect -81 -147 81 -131
+rect -81 -181 -65 -147
+rect -31 -181 31 -147
+rect 65 -181 81 -147
+rect -81 -197 81 -181
+<< polycont >>
+rect -65 -181 -31 -147
+rect 31 -181 65 -147
+<< locali >>
+rect -227 249 -131 283
+rect 131 249 227 283
+rect -227 187 -193 249
+rect 193 187 227 249
+rect -113 88 -79 104
+rect -113 -104 -79 -88
+rect -17 88 17 104
+rect -17 -104 17 -88
+rect 79 88 113 104
+rect 79 -104 113 -88
+rect -81 -181 -65 -147
+rect -31 -181 31 -147
+rect 65 -181 81 -147
+rect -227 -249 -193 -187
+rect 193 -249 227 -187
+rect -227 -283 -131 -249
+rect 131 -283 227 -249
+<< viali >>
+rect -113 -88 -79 88
+rect -17 -88 17 88
+rect 79 -88 113 88
+rect -65 -181 -31 -147
+rect 31 -181 65 -147
+<< metal1 >>
+rect -119 88 -73 100
+rect -119 -88 -113 88
+rect -79 -88 -73 88
+rect -119 -100 -73 -88
+rect -23 88 23 100
+rect -23 -88 -17 88
+rect 17 -88 23 88
+rect -23 -100 23 -88
+rect 73 88 119 100
+rect 73 -88 79 88
+rect 113 -88 119 88
+rect 73 -100 119 -88
+rect -77 -147 77 -141
+rect -77 -181 -65 -147
+rect -31 -181 31 -147
+rect 65 -181 77 -147
+rect -77 -187 77 -181
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -266 210 266
+string parameters w 1 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_XAYTAL.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_XAYTAL.mag
new file mode 100644
index 0000000..98788fa
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_XAYTAL.mag
@@ -0,0 +1,121 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623959550
+<< nwell >>
+rect -311 -319 311 319
+<< pmos >>
+rect -111 -100 -81 100
+rect -15 -100 15 100
+rect 81 -100 111 100
+<< pdiff >>
+rect -173 88 -111 100
+rect -173 -88 -161 88
+rect -127 -88 -111 88
+rect -173 -100 -111 -88
+rect -81 88 -15 100
+rect -81 -88 -65 88
+rect -31 -88 -15 88
+rect -81 -100 -15 -88
+rect 15 88 81 100
+rect 15 -88 31 88
+rect 65 -88 81 88
+rect 15 -100 81 -88
+rect 111 88 173 100
+rect 111 -88 127 88
+rect 161 -88 173 88
+rect 111 -100 173 -88
+<< pdiffc >>
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+<< nsubdiff >>
+rect -275 249 -179 283
+rect 179 249 275 283
+rect -275 187 -241 249
+rect 241 187 275 249
+rect -275 -249 -241 -187
+rect 241 -249 275 -187
+rect -275 -283 -179 -249
+rect 179 -283 275 -249
+<< nsubdiffcont >>
+rect -179 249 179 283
+rect -275 -187 -241 187
+rect 241 -187 275 187
+rect -179 -283 179 -249
+<< poly >>
+rect -111 100 -81 126
+rect -15 100 15 126
+rect 81 100 111 126
+rect -111 -131 -81 -100
+rect -15 -131 15 -100
+rect 81 -131 111 -100
+rect -129 -147 129 -131
+rect -129 -181 -113 -147
+rect -79 -181 -17 -147
+rect 17 -181 79 -147
+rect 113 -181 129 -147
+rect -129 -197 129 -181
+<< polycont >>
+rect -113 -181 -79 -147
+rect -17 -181 17 -147
+rect 79 -181 113 -147
+<< locali >>
+rect -275 249 -179 283
+rect 179 249 275 283
+rect -275 187 -241 249
+rect 241 187 275 249
+rect -161 88 -127 104
+rect -161 -104 -127 -88
+rect -65 88 -31 104
+rect -65 -104 -31 -88
+rect 31 88 65 104
+rect 31 -104 65 -88
+rect 127 88 161 104
+rect 127 -104 161 -88
+rect -129 -181 -113 -147
+rect -79 -181 -17 -147
+rect 17 -181 79 -147
+rect 113 -181 129 -147
+rect -275 -249 -241 -187
+rect 241 -249 275 -187
+rect -275 -283 -179 -249
+rect 179 -283 275 -249
+<< viali >>
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+rect -113 -181 -79 -147
+rect -17 -181 17 -147
+rect 79 -181 113 -147
+<< metal1 >>
+rect -167 88 -121 100
+rect -167 -88 -161 88
+rect -127 -88 -121 88
+rect -167 -100 -121 -88
+rect -71 88 -25 100
+rect -71 -88 -65 88
+rect -31 -88 -25 88
+rect -71 -100 -25 -88
+rect 25 88 71 100
+rect 25 -88 31 88
+rect 65 -88 71 88
+rect 25 -100 71 -88
+rect 121 88 167 100
+rect 121 -88 127 88
+rect 161 -88 167 88
+rect 121 -100 167 -88
+rect -125 -147 125 -141
+rect -125 -181 -113 -147
+rect -79 -181 -17 -147
+rect 17 -181 79 -147
+rect 113 -181 125 -147
+rect -125 -187 125 -181
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -258 -266 258 266
+string parameters w 1 l 0.15 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_ZP3U9B.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_ZP3U9B.mag
new file mode 100644
index 0000000..6535f8a
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_ZP3U9B.mag
@@ -0,0 +1,108 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623431064
+<< nwell >>
+rect -359 -303 359 303
+<< pmos >>
+rect -159 -84 -129 84
+rect -63 -84 -33 84
+rect 33 -84 63 84
+rect 129 -84 159 84
+<< pdiff >>
+rect -221 72 -159 84
+rect -221 -72 -209 72
+rect -175 -72 -159 72
+rect -221 -84 -159 -72
+rect -129 72 -63 84
+rect -129 -72 -113 72
+rect -79 -72 -63 72
+rect -129 -84 -63 -72
+rect -33 72 33 84
+rect -33 -72 -17 72
+rect 17 -72 33 72
+rect -33 -84 33 -72
+rect 63 72 129 84
+rect 63 -72 79 72
+rect 113 -72 129 72
+rect 63 -84 129 -72
+rect 159 72 221 84
+rect 159 -72 175 72
+rect 209 -72 221 72
+rect 159 -84 221 -72
+<< pdiffc >>
+rect -209 -72 -175 72
+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+rect 175 -72 209 72
+<< nsubdiff >>
+rect -323 233 -227 267
+rect 227 233 323 267
+rect -323 171 -289 233
+rect 289 171 323 233
+rect -323 -233 -289 -171
+rect 289 -233 323 -171
+<< nsubdiffcont >>
+rect -227 233 227 267
+rect -323 -171 -289 171
+rect 289 -171 323 171
+<< poly >>
+rect -159 84 -129 110
+rect -63 84 -33 110
+rect 33 84 63 110
+rect 129 84 159 110
+rect -159 -110 -129 -84
+rect -63 -110 -33 -84
+rect 33 -110 63 -84
+rect 129 -110 159 -84
+<< locali >>
+rect -323 233 -227 267
+rect 227 233 323 267
+rect -323 171 -289 233
+rect 289 171 323 233
+rect -209 72 -175 88
+rect -209 -88 -175 -72
+rect -113 72 -79 88
+rect -113 -88 -79 -72
+rect -17 72 17 88
+rect -17 -88 17 -72
+rect 79 72 113 88
+rect 79 -88 113 -72
+rect 175 72 209 88
+rect 175 -88 209 -72
+rect -323 -233 -289 -171
+rect 289 -233 323 -171
+<< viali >>
+rect -209 -72 -175 72
+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+rect 175 -72 209 72
+<< metal1 >>
+rect -215 72 -169 84
+rect -215 -72 -209 72
+rect -175 -72 -169 72
+rect -215 -84 -169 -72
+rect -119 72 -73 84
+rect -119 -72 -113 72
+rect -79 -72 -73 72
+rect -119 -84 -73 -72
+rect -23 72 23 84
+rect -23 -72 -17 72
+rect 17 -72 23 72
+rect -23 -84 23 -72
+rect 73 72 119 84
+rect 73 -72 79 72
+rect 113 -72 119 72
+rect 73 -84 119 -72
+rect 169 72 215 84
+rect 169 -72 175 72
+rect 209 -72 215 72
+rect 169 -84 215 -72
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -306 -250 306 250
+string parameters w 0.84 l 0.15 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_lvt_4L9VGG.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_lvt_4L9VGG.mag
new file mode 100644
index 0000000..d28ba9b
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_lvt_4L9VGG.mag
@@ -0,0 +1,157 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624030292
+<< nwell >>
+rect -487 -419 487 419
+<< pmoslvt >>
+rect -291 -200 -221 200
+rect -163 -200 -93 200
+rect -35 -200 35 200
+rect 93 -200 163 200
+rect 221 -200 291 200
+<< pdiff >>
+rect -349 188 -291 200
+rect -349 -188 -337 188
+rect -303 -188 -291 188
+rect -349 -200 -291 -188
+rect -221 188 -163 200
+rect -221 -188 -209 188
+rect -175 -188 -163 188
+rect -221 -200 -163 -188
+rect -93 188 -35 200
+rect -93 -188 -81 188
+rect -47 -188 -35 188
+rect -93 -200 -35 -188
+rect 35 188 93 200
+rect 35 -188 47 188
+rect 81 -188 93 188
+rect 35 -200 93 -188
+rect 163 188 221 200
+rect 163 -188 175 188
+rect 209 -188 221 188
+rect 163 -200 221 -188
+rect 291 188 349 200
+rect 291 -188 303 188
+rect 337 -188 349 188
+rect 291 -200 349 -188
+<< pdiffc >>
+rect -337 -188 -303 188
+rect -209 -188 -175 188
+rect -81 -188 -47 188
+rect 47 -188 81 188
+rect 175 -188 209 188
+rect 303 -188 337 188
+<< nsubdiff >>
+rect -451 349 -355 383
+rect 355 349 451 383
+rect -451 287 -417 349
+rect 417 287 451 349
+rect -451 -349 -417 -287
+rect 417 -349 451 -287
+rect -451 -383 -355 -349
+rect 355 -383 451 -349
+<< nsubdiffcont >>
+rect -355 349 355 383
+rect -451 -287 -417 287
+rect 417 -287 451 287
+rect -355 -383 355 -349
+<< poly >>
+rect -291 281 291 297
+rect -291 247 -275 281
+rect -237 247 -147 281
+rect -109 247 -19 281
+rect 19 247 109 281
+rect 147 247 237 281
+rect 275 247 291 281
+rect -291 233 291 247
+rect -291 200 -221 233
+rect -163 200 -93 233
+rect -35 200 35 233
+rect 93 200 163 233
+rect 221 200 291 233
+rect -291 -238 -221 -200
+rect -163 -238 -93 -200
+rect -35 -238 35 -200
+rect 93 -238 163 -200
+rect 221 -238 291 -200
+<< polycont >>
+rect -275 247 -237 281
+rect -147 247 -109 281
+rect -19 247 19 281
+rect 109 247 147 281
+rect 237 247 275 281
+<< locali >>
+rect -451 349 -355 383
+rect 355 349 451 383
+rect -451 287 -417 349
+rect 417 287 451 349
+rect -291 247 -275 281
+rect 275 247 291 281
+rect -337 188 -303 204
+rect -337 -204 -303 -188
+rect -209 188 -175 204
+rect -209 -204 -175 -188
+rect -81 188 -47 204
+rect -81 -204 -47 -188
+rect 47 188 81 204
+rect 47 -204 81 -188
+rect 175 188 209 204
+rect 175 -204 209 -188
+rect 303 188 337 204
+rect 303 -204 337 -188
+rect -451 -349 -417 -287
+rect 417 -349 451 -287
+rect -451 -383 -355 -349
+rect 355 -383 451 -349
+<< viali >>
+rect -275 247 -237 281
+rect -237 247 -147 281
+rect -147 247 -109 281
+rect -109 247 -19 281
+rect -19 247 19 281
+rect 19 247 109 281
+rect 109 247 147 281
+rect 147 247 237 281
+rect 237 247 275 281
+rect -337 -188 -303 188
+rect -209 -188 -175 188
+rect -81 -188 -47 188
+rect 47 -188 81 188
+rect 175 -188 209 188
+rect 303 -188 337 188
+<< metal1 >>
+rect -287 281 287 287
+rect -287 247 -275 281
+rect 275 247 287 281
+rect -287 241 287 247
+rect -343 188 -297 200
+rect -343 -188 -337 188
+rect -303 -188 -297 188
+rect -343 -200 -297 -188
+rect -215 188 -169 200
+rect -215 -188 -209 188
+rect -175 -188 -169 188
+rect -215 -200 -169 -188
+rect -87 188 -41 200
+rect -87 -188 -81 188
+rect -47 -188 -41 188
+rect -87 -200 -41 -188
+rect 41 188 87 200
+rect 41 -188 47 188
+rect 81 -188 87 188
+rect 41 -200 87 -188
+rect 169 188 215 200
+rect 169 -188 175 188
+rect 209 -188 215 188
+rect 169 -200 215 -188
+rect 297 188 343 200
+rect 297 -188 303 188
+rect 337 -188 343 188
+rect 297 -200 343 -188
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8_lvt
+string FIXED_BBOX -434 -366 434 366
+string parameters w 2 l 0.35 m 1 nf 5 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_lvt_D3F744.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_lvt_D3F744.mag
new file mode 100644
index 0000000..ed5e11e
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__pfet_01v8_lvt_D3F744.mag
@@ -0,0 +1,252 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623976832
+<< nwell >>
+rect -807 -384 807 384
+<< pmoslvt >>
+rect -611 -236 -541 164
+rect -483 -236 -413 164
+rect -355 -236 -285 164
+rect -227 -236 -157 164
+rect -99 -236 -29 164
+rect 29 -236 99 164
+rect 157 -236 227 164
+rect 285 -236 355 164
+rect 413 -236 483 164
+rect 541 -236 611 164
+<< pdiff >>
+rect -669 152 -611 164
+rect -669 -224 -657 152
+rect -623 -224 -611 152
+rect -669 -236 -611 -224
+rect -541 152 -483 164
+rect -541 -224 -529 152
+rect -495 -224 -483 152
+rect -541 -236 -483 -224
+rect -413 152 -355 164
+rect -413 -224 -401 152
+rect -367 -224 -355 152
+rect -413 -236 -355 -224
+rect -285 152 -227 164
+rect -285 -224 -273 152
+rect -239 -224 -227 152
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+rect -157 152 -99 164
+rect -157 -224 -145 152
+rect -111 -224 -99 152
+rect -157 -236 -99 -224
+rect -29 152 29 164
+rect -29 -224 -17 152
+rect 17 -224 29 152
+rect -29 -236 29 -224
+rect 99 152 157 164
+rect 99 -224 111 152
+rect 145 -224 157 152
+rect 99 -236 157 -224
+rect 227 152 285 164
+rect 227 -224 239 152
+rect 273 -224 285 152
+rect 227 -236 285 -224
+rect 355 152 413 164
+rect 355 -224 367 152
+rect 401 -224 413 152
+rect 355 -236 413 -224
+rect 483 152 541 164
+rect 483 -224 495 152
+rect 529 -224 541 152
+rect 483 -236 541 -224
+rect 611 152 669 164
+rect 611 -224 623 152
+rect 657 -224 669 152
+rect 611 -236 669 -224
+<< pdiffc >>
+rect -657 -224 -623 152
+rect -529 -224 -495 152
+rect -401 -224 -367 152
+rect -273 -224 -239 152
+rect -145 -224 -111 152
+rect -17 -224 17 152
+rect 111 -224 145 152
+rect 239 -224 273 152
+rect 367 -224 401 152
+rect 495 -224 529 152
+rect 623 -224 657 152
+<< nsubdiff >>
+rect -771 314 -675 348
+rect 675 314 771 348
+rect -771 251 -737 314
+rect 737 251 771 314
+rect -771 -314 -737 -251
+rect 737 -314 771 -251
+rect -771 -348 -675 -314
+rect 675 -348 771 -314
+<< nsubdiffcont >>
+rect -675 314 675 348
+rect -771 -251 -737 251
+rect 737 -251 771 251
+rect -675 -348 675 -314
+<< poly >>
+rect -611 245 611 261
+rect -611 211 -595 245
+rect -557 211 -467 245
+rect -429 211 -339 245
+rect -301 211 -211 245
+rect -173 211 -83 245
+rect -45 211 45 245
+rect 83 211 173 245
+rect 211 211 301 245
+rect 339 211 429 245
+rect 467 211 557 245
+rect 595 211 611 245
+rect -611 201 611 211
+rect -611 164 -541 201
+rect -483 164 -413 201
+rect -355 164 -285 201
+rect -227 164 -157 201
+rect -99 164 -29 201
+rect 29 164 99 201
+rect 157 164 227 201
+rect 285 164 355 201
+rect 413 164 483 201
+rect 541 164 611 201
+rect -611 -262 -541 -236
+rect -483 -262 -413 -236
+rect -355 -262 -285 -236
+rect -227 -262 -157 -236
+rect -99 -262 -29 -236
+rect 29 -262 99 -236
+rect 157 -262 227 -236
+rect 285 -262 355 -236
+rect 413 -262 483 -236
+rect 541 -262 611 -236
+<< polycont >>
+rect -595 211 -557 245
+rect -467 211 -429 245
+rect -339 211 -301 245
+rect -211 211 -173 245
+rect -83 211 -45 245
+rect 45 211 83 245
+rect 173 211 211 245
+rect 301 211 339 245
+rect 429 211 467 245
+rect 557 211 595 245
+<< locali >>
+rect -771 314 -675 348
+rect 675 314 771 348
+rect -771 251 -737 314
+rect 737 251 771 314
+rect -611 211 -595 245
+rect 595 211 611 245
+rect -657 152 -623 168
+rect -657 -240 -623 -224
+rect -529 152 -495 168
+rect -529 -240 -495 -224
+rect -401 152 -367 168
+rect -401 -240 -367 -224
+rect -273 152 -239 168
+rect -273 -240 -239 -224
+rect -145 152 -111 168
+rect -145 -240 -111 -224
+rect -17 152 17 168
+rect -17 -240 17 -224
+rect 111 152 145 168
+rect 111 -240 145 -224
+rect 239 152 273 168
+rect 239 -240 273 -224
+rect 367 152 401 168
+rect 367 -240 401 -224
+rect 495 152 529 168
+rect 495 -240 529 -224
+rect 623 152 657 168
+rect 623 -240 657 -224
+rect -771 -314 -737 -251
+rect 737 -314 771 -251
+rect -771 -348 -675 -314
+rect 675 -348 771 -314
+<< viali >>
+rect -595 211 -557 245
+rect -557 211 -467 245
+rect -467 211 -429 245
+rect -429 211 -339 245
+rect -339 211 -301 245
+rect -301 211 -211 245
+rect -211 211 -173 245
+rect -173 211 -83 245
+rect -83 211 -45 245
+rect -45 211 45 245
+rect 45 211 83 245
+rect 83 211 173 245
+rect 173 211 211 245
+rect 211 211 301 245
+rect 301 211 339 245
+rect 339 211 429 245
+rect 429 211 467 245
+rect 467 211 557 245
+rect 557 211 595 245
+rect -657 -224 -623 152
+rect -529 -224 -495 152
+rect -401 -224 -367 152
+rect -273 -224 -239 152
+rect -145 -224 -111 152
+rect -17 -224 17 152
+rect 111 -224 145 152
+rect 239 -224 273 152
+rect 367 -224 401 152
+rect 495 -224 529 152
+rect 623 -224 657 152
+<< metal1 >>
+rect -607 245 607 251
+rect -607 211 -595 245
+rect 595 211 607 245
+rect -607 205 607 211
+rect -663 152 -617 164
+rect -663 -224 -657 152
+rect -623 -224 -617 152
+rect -663 -236 -617 -224
+rect -535 152 -489 164
+rect -535 -224 -529 152
+rect -495 -224 -489 152
+rect -535 -236 -489 -224
+rect -407 152 -361 164
+rect -407 -224 -401 152
+rect -367 -224 -361 152
+rect -407 -236 -361 -224
+rect -279 152 -233 164
+rect -279 -224 -273 152
+rect -239 -224 -233 152
+rect -279 -236 -233 -224
+rect -151 152 -105 164
+rect -151 -224 -145 152
+rect -111 -224 -105 152
+rect -151 -236 -105 -224
+rect -23 152 23 164
+rect -23 -224 -17 152
+rect 17 -224 23 152
+rect -23 -236 23 -224
+rect 105 152 151 164
+rect 105 -224 111 152
+rect 145 -224 151 152
+rect 105 -236 151 -224
+rect 233 152 279 164
+rect 233 -224 239 152
+rect 273 -224 279 152
+rect 233 -236 279 -224
+rect 361 152 407 164
+rect 361 -224 367 152
+rect 401 -224 407 152
+rect 361 -236 407 -224
+rect 489 152 535 164
+rect 489 -224 495 152
+rect 529 -224 535 152
+rect 489 -236 535 -224
+rect 617 152 663 164
+rect 617 -224 623 152
+rect 657 -224 663 152
+rect 617 -236 663 -224
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8_lvt
+string FIXED_BBOX -754 -331 754 331
+string parameters w 2 l 0.35 m 1 nf 10 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/source_follower_buff_diff.mag b/mag/afernandez_residue_amplifier/source_follower_buff_diff.mag
new file mode 100644
index 0000000..c5ad543
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/source_follower_buff_diff.mag
@@ -0,0 +1,92 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624113565
+<< nwell >>
+rect 1027 2742 4581 3209
+<< metal1 >>
+rect 1027 6031 9953 6158
+rect 1027 4628 3874 6031
+rect 4025 5420 4056 5449
+rect 1273 3943 1304 3972
+rect 2752 3927 2762 3983
+rect 2818 3927 3107 3983
+rect 5484 3567 5494 3772
+rect 5619 3567 5629 3772
+rect 9765 3236 9953 6031
+rect 1027 2742 9563 3217
+rect 9630 2759 9953 3236
+rect 5483 2212 5493 2417
+rect 5618 2212 5628 2417
+rect 1229 2011 1260 2040
+rect 2752 2001 2762 2057
+rect 2818 2001 3051 2057
+rect 1037 1300 3899 1356
+rect 1027 -47 3884 1300
+rect 4021 539 4052 568
+rect 9765 -47 9953 2759
+rect 1027 -174 9953 -47
+<< via1 >>
+rect 2762 3927 2818 3983
+rect 5494 3567 5619 3772
+rect 5493 2212 5618 2417
+rect 2762 2001 2818 2057
+<< metal2 >>
+rect 9270 4026 9956 4233
+rect 2762 3983 2818 3993
+rect 2762 3917 2818 3927
+rect 3743 3772 5158 3932
+rect 5494 3772 5619 3782
+rect 3743 3727 5494 3772
+rect 4953 3567 5494 3727
+rect 5494 3557 5619 3567
+rect 5493 2417 5618 2427
+rect 4952 2257 5493 2417
+rect 3742 2212 5493 2257
+rect 2762 2057 2818 2067
+rect 3742 2052 5157 2212
+rect 5493 2202 5618 2212
+rect 2762 1991 2818 2001
+rect 9270 1751 9956 1958
+<< via2 >>
+rect 2762 3927 2818 3983
+rect 2762 2001 2818 2057
+<< metal3 >>
+rect 863 4524 2828 4600
+rect 2752 3983 2828 4524
+rect 2752 3927 2762 3983
+rect 2818 3927 2828 3983
+rect 2752 3922 2828 3927
+rect 2752 2057 2828 2062
+rect 2752 2001 2762 2057
+rect 2818 2001 2828 2057
+rect 2752 1460 2828 2001
+rect 863 1384 2828 1460
+use source_follower_buff_nmos source_follower_buff_nmos_1
+timestamp 1624043228
+transform 1 0 3483 0 -1 4622
+box 336 -1409 7209 1545
+use source_follower_buff_pmos source_follower_buff_pmos_1
+timestamp 1624113565
+transform 1 0 1078 0 -1 4373
+box -51 -311 3503 1296
+use source_follower_buff_nmos source_follower_buff_nmos_0
+timestamp 1624043228
+transform 1 0 3483 0 1 1362
+box 336 -1409 7209 1545
+use source_follower_buff_pmos source_follower_buff_pmos_0
+timestamp 1624113565
+transform 1 0 1078 0 1 1611
+box -51 -311 3503 1296
+<< labels >>
+rlabel metal3 899 4542 930 4571 1 inp
+rlabel metal1 1273 3943 1304 3972 1 iref1
+rlabel metal1 4025 5420 4056 5449 1 iref2
+rlabel metal2 9881 4111 9912 4140 1 outp
+rlabel metal1 9677 3060 9708 3089 1 avss1p8
+rlabel metal1 9451 3068 9482 3097 1 avdd1p8
+rlabel metal2 9849 1828 9880 1857 1 outn
+rlabel metal1 4021 539 4052 568 1 iref4
+rlabel metal1 1229 2011 1260 2040 1 iref3
+rlabel metal3 895 1410 926 1439 1 inn
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/source_follower_buff_nmos.mag b/mag/afernandez_residue_amplifier/source_follower_buff_nmos.mag
new file mode 100644
index 0000000..1163b52
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/source_follower_buff_nmos.mag
@@ -0,0 +1,895 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624043228
+<< pwell >>
+rect 2250 1287 5928 1291
+rect 2049 850 2193 1059
+rect 2250 621 5928 625
+rect 2250 355 5928 359
+rect 2250 -1147 5928 -1143
+rect 6242 -1261 6276 1390
+rect 7186 -616 7209 -612
+rect 372 -1391 2014 -1357
+rect 2086 -1392 6188 -1358
+<< psubdiff >>
+rect 6242 1343 6276 1390
+rect 6242 411 6276 569
+rect 6242 -1261 6276 -1199
+rect 372 -1391 468 -1357
+rect 1114 -1391 1272 -1357
+rect 1918 -1391 2014 -1357
+rect 2086 -1392 2182 -1358
+rect 6092 -1392 6188 -1358
+<< psubdiffcont >>
+rect 6242 569 6276 1343
+rect 6242 -1199 6276 411
+rect 468 -1391 1114 -1357
+rect 1272 -1391 1918 -1357
+rect 2182 -1392 6092 -1358
+<< poly >>
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+rect 2346 1287 2376 1291
+rect 2442 1287 2472 1291
+rect 2538 1287 2568 1291
+rect 2634 1287 2664 1291
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+rect 5706 -1147 5736 -1143
+rect 5802 -1147 5832 -1143
+rect 5898 -1147 5928 -1143
+<< polycont >>
+rect 2083 890 2129 1024
+rect 2084 -42 2130 92
+rect 2084 -460 2130 -326
+rect 2084 -878 2130 -744
+<< viali >>
+rect 2083 1024 2129 1043
+rect 2083 890 2129 1024
+rect 2083 869 2129 890
+rect 2084 92 2130 111
+rect 2084 -42 2130 92
+rect 2084 -63 2130 -42
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+rect 2084 -481 2130 -460
+rect 2084 -744 2130 -725
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+rect 2084 -899 2130 -878
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+rect 2182 -1392 6092 -1358
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+<< metal1 >>
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diff --git a/mag/afernandez_residue_amplifier/source_follower_buff_pmos.mag b/mag/afernandez_residue_amplifier/source_follower_buff_pmos.mag
new file mode 100644
index 0000000..871bcbe
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/source_follower_buff_pmos.mag
@@ -0,0 +1,234 @@
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+rlabel metal1 1973 390 3195 446 1 in
+<< end >>
diff --git a/mag/afernandez_residue_amplifier/trans_gate.mag b/mag/afernandez_residue_amplifier/trans_gate.mag
new file mode 100644
index 0000000..0a9f391
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/trans_gate.mag
@@ -0,0 +1,132 @@
+magic
+tech sky130A
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+timestamp 1623610677
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+use sky130_fd_pr__nfet_01v8_BHR94T sky130_fd_pr__nfet_01v8_BHR94T_0
+timestamp 1623610677
+transform 1 0 258 0 1 -388
+box -311 -335 311 335
+<< labels >>
+rlabel metal1 217 599 569 653 1 vdd
+rlabel metal1 -53 -741 299 -687 1 vss
+rlabel space 419 -605 477 416 1 out
+rlabel space 45 -513 97 508 1 in
+<< end >>
diff --git a/mag/and_pfd.mag b/mag/and_pfd.mag
new file mode 100644
index 0000000..461011c
--- /dev/null
+++ b/mag/and_pfd.mag
@@ -0,0 +1,139 @@
+magic
+tech sky130A
+magscale 1 2
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+<< nwell >>
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+timestamp 1624049879
+transform 1 0 359 0 1 907
+box -263 -309 263 309
+use sky130_fd_pr__nfet_01v8_ZCYAJJ sky130_fd_pr__nfet_01v8_ZCYAJJ_0
+timestamp 1624049879
+transform 1 0 359 0 1 343
+box -359 -255 359 255
+use sky130_fd_pr__nfet_01v8_ZXAV3F sky130_fd_pr__nfet_01v8_ZXAV3F_0
+timestamp 1624049879
+transform 1 0 707 0 1 343
+box -211 -255 211 255
+use sky130_fd_pr__pfet_01v8_4F7GBC sky130_fd_pr__pfet_01v8_4F7GBC_0
+timestamp 1624049879
+transform 1 0 707 0 1 907
+box -211 -309 211 309
+<< labels >>
+rlabel metal1 0 70 918 124 1 vss
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+rlabel metal1 766 298 812 997 1 out
+<< end >>
diff --git a/mag/bias.mag b/mag/bias.mag
new file mode 100644
index 0000000..1300fbd
--- /dev/null
+++ b/mag/bias.mag
@@ -0,0 +1,89 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< metal1 >>
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+timestamp 1624049879
+transform -1 0 5997 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X sky130_fd_pr__pfet_01v8_lvt_8P223X_0
+timestamp 1624049879
+transform 1 0 1964 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X sky130_fd_pr__pfet_01v8_lvt_8P223X_2
+timestamp 1624049879
+transform -1 0 10031 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X sky130_fd_pr__pfet_01v8_lvt_8P223X_3
+timestamp 1624049879
+transform -1 0 14064 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X sky130_fd_pr__pfet_01v8_lvt_8P223X_4
+timestamp 1624049879
+transform -1 0 18098 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X sky130_fd_pr__pfet_01v8_lvt_8P223X_5
+timestamp 1624049879
+transform 1 0 22132 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X sky130_fd_pr__pfet_01v8_lvt_8P223X_6
+timestamp 1624049879
+transform -1 0 26163 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X sky130_fd_pr__pfet_01v8_lvt_8P223X_7
+timestamp 1624049879
+transform -1 0 30197 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X sky130_fd_pr__pfet_01v8_lvt_8P223X_8
+timestamp 1624049879
+transform -1 0 34231 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X sky130_fd_pr__pfet_01v8_lvt_8P223X_9
+timestamp 1624049879
+transform -1 0 38265 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X sky130_fd_pr__pfet_01v8_lvt_8P223X_10
+timestamp 1624049879
+transform -1 0 42299 0 1 1042
+box -2018 -1454 2017 1196
+<< labels >>
+rlabel metal1 -53 2101 44316 2168 1 vdd
+rlabel metal1 20182 -412 24081 -273 1 iref
+rlabel metal1 8082 -412 11981 -273 1 iref_2
+rlabel metal1 12115 -412 16014 -273 1 iref_3
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+rlabel metal1 14 -412 3913 -273 1 iref_0
+rlabel metal1 4048 -412 7947 -273 1 iref_1
+<< end >>
diff --git a/mag/buffer_salida.mag b/mag/buffer_salida.mag
new file mode 100644
index 0000000..fc84c3d
--- /dev/null
+++ b/mag/buffer_salida.mag
@@ -0,0 +1,671 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
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+<< pwell >>
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+timestamp 1624049879
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+timestamp 1624049879
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+timestamp 1624049879
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+transform 1 0 7262 0 1 700
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+timestamp 1624049879
+transform -1 0 7646 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 7646 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 8030 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform -1 0 8414 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 8030 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform 1 0 8414 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 8798 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 8798 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 9182 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 9182 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 9566 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform -1 0 9950 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 9566 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform 1 0 9950 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 10334 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 10334 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 10718 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 10718 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 11102 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform -1 0 11486 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 11102 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform 1 0 11486 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 11870 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 11870 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 12254 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 12254 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 12638 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform -1 0 13022 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 12638 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform 1 0 13022 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform 1 0 13406 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 13406 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 13790 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 13790 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 14174 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform -1 0 14558 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 14174 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform 1 0 14558 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 14942 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 14942 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_38
+timestamp 1624049879
+transform -1 0 15326 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 15326 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 15710 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform -1 0 16094 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 15710 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform 1 0 16094 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_41
+timestamp 1624049879
+transform -1 0 16478 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 16478 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform -1 0 16862 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform -1 0 17246 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 16862 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_43
+timestamp 1624049879
+transform 1 0 17246 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_44
+timestamp 1624049879
+transform -1 0 17630 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 17630 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_45
+timestamp 1624049879
+transform -1 0 18014 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 18014 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_46
+timestamp 1624049879
+transform -1 0 18398 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_47
+timestamp 1624049879
+transform -1 0 18782 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_48
+timestamp 1624049879
+transform 1 0 18398 0 1 700
+box -257 -777 257 744
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+timestamp 1624049879
+transform 1 0 18782 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_48
+timestamp 1624049879
+transform -1 0 19166 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_46
+timestamp 1624049879
+transform 1 0 19166 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_49
+timestamp 1624049879
+transform 1 0 19550 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_49
+timestamp 1624049879
+transform 1 0 19550 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_50
+timestamp 1624049879
+transform -1 0 19934 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_51
+timestamp 1624049879
+transform -1 0 20318 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_52
+timestamp 1624049879
+transform 1 0 19934 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_51
+timestamp 1624049879
+transform 1 0 20318 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_52
+timestamp 1624049879
+transform -1 0 20702 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_50
+timestamp 1624049879
+transform 1 0 20702 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_53
+timestamp 1624049879
+transform -1 0 21086 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_56
+timestamp 1624049879
+transform 1 0 21086 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_54
+timestamp 1624049879
+transform -1 0 21470 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_55
+timestamp 1624049879
+transform -1 0 21854 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_55
+timestamp 1624049879
+transform 1 0 21470 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_54
+timestamp 1624049879
+transform 1 0 21854 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_56
+timestamp 1624049879
+transform -1 0 22238 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_53
+timestamp 1624049879
+transform 1 0 22238 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_57
+timestamp 1624049879
+transform -1 0 22622 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_61
+timestamp 1624049879
+transform 1 0 22622 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_59
+timestamp 1624049879
+transform -1 0 23390 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_58
+timestamp 1624049879
+transform -1 0 23006 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_60
+timestamp 1624049879
+transform 1 0 23006 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_59
+timestamp 1624049879
+transform 1 0 23390 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_60
+timestamp 1624049879
+transform -1 0 23774 0 1 -573
+box -257 -425 257 499
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+timestamp 1624049879
+transform 1 0 23774 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_61
+timestamp 1624049879
+transform -1 0 24158 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_57
+timestamp 1624049879
+transform 1 0 24158 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_63
+timestamp 1624049879
+transform -1 0 24926 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_62
+timestamp 1624049879
+transform -1 0 24542 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_64
+timestamp 1624049879
+transform 1 0 24542 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_63
+timestamp 1624049879
+transform 1 0 24926 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_64
+timestamp 1624049879
+transform -1 0 25310 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_62
+timestamp 1624049879
+transform 1 0 25310 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_65
+timestamp 1624049879
+transform 1 0 25694 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_65
+timestamp 1624049879
+transform 1 0 25694 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_67
+timestamp 1624049879
+transform -1 0 26462 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_66
+timestamp 1624049879
+transform -1 0 26078 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_68
+timestamp 1624049879
+transform 1 0 26078 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_67
+timestamp 1624049879
+transform 1 0 26462 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_68
+timestamp 1624049879
+transform -1 0 26846 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_66
+timestamp 1624049879
+transform 1 0 26846 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_69
+timestamp 1624049879
+transform -1 0 27230 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_72
+timestamp 1624049879
+transform 1 0 27230 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_71
+timestamp 1624049879
+transform -1 0 27998 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_70
+timestamp 1624049879
+transform -1 0 27614 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_71
+timestamp 1624049879
+transform 1 0 27614 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_70
+timestamp 1624049879
+transform 1 0 27998 0 1 700
+box -257 -777 257 744
+use sky130_fd_pr__nfet_01v8_T69Y3A sky130_fd_pr__nfet_01v8_T69Y3A_72
+timestamp 1624049879
+transform -1 0 28382 0 1 -573
+box -257 -425 257 499
+use sky130_fd_pr__pfet_01v8_58ZKDE sky130_fd_pr__pfet_01v8_58ZKDE_69
+timestamp 1624049879
+transform 1 0 28382 0 1 700
+box -257 -777 257 744
+<< labels >>
+rlabel metal1 -63 -107 25 -55 1 in
+rlabel metal1 -63 1532 28694 1538 1 vdd
+rlabel metal1 -63 -1113 28718 -1107 1 vss
+rlabel metal1 27687 -220 28718 64 1 out
+<< end >>
diff --git a/mag/cap1_loop_filter.mag b/mag/cap1_loop_filter.mag
new file mode 100644
index 0000000..53d528a
--- /dev/null
+++ b/mag/cap1_loop_filter.mag
@@ -0,0 +1,38 @@
+magic
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+magscale 1 2
+timestamp 1624049879
+<< metal3 >>
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+<< labels >>
+rlabel metal4 -40452 -15842 -18179 -14842 1 in
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+<< end >>
diff --git a/mag/cap2_loop_filter.mag b/mag/cap2_loop_filter.mag
new file mode 100644
index 0000000..54b2605
--- /dev/null
+++ b/mag/cap2_loop_filter.mag
@@ -0,0 +1,35 @@
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+rlabel metal4 -7038 4492 2600 5492 1 in
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+<< end >>
diff --git a/mag/cap3_loop_filter.mag b/mag/cap3_loop_filter.mag
new file mode 100644
index 0000000..eca5efd
--- /dev/null
+++ b/mag/cap3_loop_filter.mag
@@ -0,0 +1,27 @@
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+<< end >>
diff --git a/mag/cap_vco.mag b/mag/cap_vco.mag
new file mode 100644
index 0000000..52e369f
--- /dev/null
+++ b/mag/cap_vco.mag
@@ -0,0 +1,84 @@
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+<< end >>
diff --git a/mag/charge_pump.mag b/mag/charge_pump.mag
new file mode 100644
index 0000000..deb39e8
--- /dev/null
+++ b/mag/charge_pump.mag
@@ -0,0 +1,578 @@
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+use sky130_fd_pr__nfet_01v8_8GRULZ sky130_fd_pr__nfet_01v8_8GRULZ_0
+timestamp 1624049879
+transform 1 0 4691 0 1 742
+box -1957 -254 1957 254
+use sky130_fd_pr__nfet_01v8_MUHGM9 sky130_fd_pr__nfet_01v8_MUHGM9_0
+timestamp 1624049879
+transform 1 0 3861 0 1 285
+box -1127 -285 1127 285
+use sky130_fd_pr__nfet_01v8_YCGG98 sky130_fd_pr__nfet_01v8_YCGG98_0
+timestamp 1624049879
+transform 1 0 6355 0 1 285
+box -1367 -285 1367 285
+use sky130_fd_pr__pfet_01v8_4ML9WA sky130_fd_pr__pfet_01v8_4ML9WA_0
+timestamp 1624049879
+transform 1 0 5228 0 1 1630
+box -2457 -634 2457 634
+use sky130_fd_pr__nfet_01v8_YCGG98 sky130_fd_pr__nfet_01v8_YCGG98_1
+timestamp 1624049879
+transform -1 0 1367 0 1 285
+box -1367 -285 1367 285
+use sky130_fd_pr__nfet_01v8_YCGG98 sky130_fd_pr__nfet_01v8_YCGG98_2
+timestamp 1624049879
+transform -1 0 1367 0 -1 711
+box -1367 -285 1367 285
+use sky130_fd_pr__pfet_01v8_ND88ZC sky130_fd_pr__pfet_01v8_ND88ZC_1
+timestamp 1624049879
+transform -1 0 1367 0 1 2523
+box -1367 -369 1367 369
+use sky130_fd_pr__pfet_01v8_ND88ZC sky130_fd_pr__pfet_01v8_ND88ZC_0
+timestamp 1624049879
+transform 1 0 6355 0 1 2523
+box -1367 -369 1367 369
+use sky130_fd_pr__pfet_01v8_NKZXKB sky130_fd_pr__pfet_01v8_NKZXKB_0
+timestamp 1624049879
+transform 1 0 3861 0 1 2523
+box -1127 -369 1127 369
+<< labels >>
+rlabel metal2 4957 243 5038 435 1 nswitch
+rlabel metal2 4950 2300 5034 2641 1 pswitch
+rlabel poly 3222 382 3540 652 1 Down
+rlabel metal2 6953 348 7581 2395 1 out
+rlabel poly 3894 382 4788 448 1 nDown
+rlabel poly 3894 2276 4788 2347 1 Up
+rlabel metal1 2676 2224 2780 2775 1 biasp
+rlabel metal1 0 2856 7722 2918 1 vdd
+rlabel metal1 0 -26 7722 36 1 vss
+rlabel metal1 210 452 2524 544 1 iref
+rlabel poly 3216 2084 3540 2342 1 nUp
+<< end >>
diff --git a/mag/clock_inverter.mag b/mag/clock_inverter.mag
new file mode 100644
index 0000000..43a94a8
--- /dev/null
+++ b/mag/clock_inverter.mag
@@ -0,0 +1,89 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< metal1 >>
+rect 520 2998 530 3028
+rect 0 2944 530 2998
+rect 520 2914 530 2944
+rect 714 2998 724 3028
+rect 714 2944 1244 2998
+rect 714 2914 724 2944
+rect 210 2264 220 2320
+rect 334 2264 344 2320
+rect 442 2259 848 2325
+rect 1054 2070 1100 2523
+rect 0 1504 1244 1564
+rect 221 804 226 809
+rect 210 748 220 804
+rect 334 748 344 804
+rect 221 743 226 748
+rect 478 743 720 809
+rect 1094 307 1152 1328
+rect 520 124 530 154
+rect 0 70 530 124
+rect 520 40 530 70
+rect 714 124 724 154
+rect 714 70 1244 124
+rect 714 40 724 70
+<< via1 >>
+rect 530 2914 714 3028
+rect 220 2264 334 2320
+rect 220 748 334 804
+rect 530 40 714 154
+<< metal2 >>
+rect 530 3028 714 3038
+rect 530 2904 714 2914
+rect 220 2320 334 2330
+rect 220 2254 334 2264
+rect 220 804 334 814
+rect 220 738 334 748
+rect 530 154 714 164
+rect 530 30 714 40
+<< via2 >>
+rect 530 2914 714 3028
+rect 220 2264 334 2320
+rect 220 748 334 804
+rect 530 40 714 154
+<< metal3 >>
+rect 520 3028 724 3033
+rect 520 2914 530 3028
+rect 714 2914 724 3028
+rect 520 2909 724 2914
+rect 210 2320 344 2325
+rect 210 2264 220 2320
+rect 334 2264 344 2320
+rect 210 2259 344 2264
+rect 247 809 307 2259
+rect 210 804 344 809
+rect 210 748 220 804
+rect 334 748 344 804
+rect 210 743 344 748
+rect 586 159 658 2909
+rect 520 154 724 159
+rect 520 40 530 154
+rect 714 40 724 154
+rect 520 35 724 40
+use inverter_cp_x1 inverter_cp_x1_1
+timestamp 1624049879
+transform 1 0 0 0 1 2292
+box 0 -758 622 776
+use inverter_cp_x1 inverter_cp_x1_2
+timestamp 1624049879
+transform 1 0 622 0 1 2292
+box 0 -758 622 776
+use inverter_cp_x1 inverter_cp_x1_0
+timestamp 1624049879
+transform 1 0 0 0 -1 776
+box 0 -758 622 776
+use trans_gate trans_gate_0
+timestamp 1624049879
+transform 1 0 675 0 -1 723
+box -53 -811 569 723
+<< labels >>
+rlabel metal1 0 1504 1244 1564 1 vss
+rlabel metal1 0 2944 1244 2998 1 vdd
+rlabel metal3 247 1504 307 1564 1 CLK
+rlabel metal1 1054 2070 1100 2523 1 CLK_d
+rlabel metal1 1094 307 1152 1328 1 nCLK_d
+<< end >>
diff --git a/mag/csvco_branch.mag b/mag/csvco_branch.mag
new file mode 100644
index 0000000..2189a1f
--- /dev/null
+++ b/mag/csvco_branch.mag
@@ -0,0 +1,265 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -363 1865 931 1954
+rect -363 1858 911 1865
+rect -363 1835 -280 1858
+<< pwell >>
+rect 500 321 931 387
+rect 922 -121 931 321
+rect 500 -193 931 -121
+rect 924 -226 931 -193
+rect -354 -904 929 -869
+rect -363 -1001 929 -904
+rect -363 -1002 -231 -1001
+rect 799 -1002 929 -1001
+<< psubdiff >>
+rect 608 -174 632 -140
+rect 790 -174 814 -140
+rect -255 -966 -231 -932
+rect 799 -966 823 -932
+<< nsubdiff >>
+rect -255 1884 -231 1918
+rect 799 1884 823 1918
+<< psubdiffcont >>
+rect 632 -174 790 -140
+rect -231 -966 799 -932
+<< nsubdiffcont >>
+rect -231 1884 799 1918
+<< viali >>
+rect -327 1884 -231 1918
+rect -231 1884 799 1918
+rect 799 1884 895 1918
+rect -327 1795 895 1829
+rect -327 1197 -293 1795
+rect 861 1197 895 1795
+rect -327 1163 895 1197
+rect 536 -85 886 -51
+rect 536 -174 632 -140
+rect 632 -174 790 -140
+rect 790 -174 886 -140
+rect -327 -263 895 -229
+rect -327 -843 -293 -263
+rect 861 -843 895 -263
+rect -327 -877 895 -843
+rect -327 -966 -231 -932
+rect -231 -966 799 -932
+rect 799 -966 895 -932
+<< metal1 >>
+rect -363 1918 931 1924
+rect -363 1884 -327 1918
+rect 895 1884 931 1918
+rect -363 1829 931 1884
+rect -363 1163 -327 1829
+rect -293 1789 861 1795
+rect -293 1203 -287 1789
+rect -180 1693 -170 1745
+rect 738 1693 748 1745
+rect -126 1636 -73 1646
+rect -219 1203 -173 1348
+rect -126 1346 -73 1356
+rect 65 1636 119 1646
+rect 65 1356 66 1636
+rect 257 1637 311 1646
+rect -27 1203 19 1351
+rect 65 1346 119 1356
+rect 165 1203 211 1358
+rect 310 1357 311 1637
+rect 450 1636 502 1646
+rect 257 1346 311 1357
+rect 357 1203 403 1360
+rect 642 1636 694 1646
+rect 450 1346 502 1356
+rect 549 1203 595 1360
+rect 642 1346 694 1356
+rect 741 1203 787 1359
+rect 855 1203 861 1789
+rect -293 1197 861 1203
+rect 895 1163 931 1829
+rect -363 1157 931 1163
+rect 68 1108 500 1157
+rect 209 897 261 907
+rect 209 607 261 617
+rect 68 361 78 413
+rect 286 361 296 413
+rect 356 361 366 413
+rect 490 361 500 413
+rect 631 361 641 413
+rect 693 361 703 413
+rect 209 167 261 177
+rect 644 173 690 361
+rect 772 89 818 556
+rect 209 27 261 37
+rect 619 8 629 60
+rect 733 8 743 60
+rect 500 -51 931 -45
+rect 500 -85 536 -51
+rect 886 -85 931 -51
+rect 500 -140 805 -85
+rect 861 -140 931 -85
+rect 500 -174 536 -140
+rect 886 -174 931 -140
+rect 68 -223 931 -174
+rect -363 -229 931 -223
+rect -363 -877 -327 -229
+rect -293 -269 861 -263
+rect -293 -837 -287 -269
+rect -219 -403 -173 -269
+rect -126 -413 -73 -403
+rect -27 -404 19 -269
+rect 165 -403 211 -269
+rect 357 -403 403 -269
+rect 549 -403 595 -269
+rect 741 -403 787 -269
+rect -126 -703 -73 -693
+rect 65 -413 119 -403
+rect 65 -693 66 -413
+rect 65 -703 119 -693
+rect 257 -412 311 -403
+rect 310 -692 311 -412
+rect 257 -703 311 -692
+rect 450 -413 502 -403
+rect 450 -703 502 -693
+rect 642 -413 694 -403
+rect 642 -703 694 -693
+rect -180 -793 -170 -741
+rect 738 -793 748 -741
+rect 855 -837 861 -269
+rect -293 -843 861 -837
+rect 895 -877 931 -229
+rect -363 -932 931 -877
+rect -363 -966 -327 -932
+rect 895 -966 931 -932
+rect -363 -972 931 -966
+<< via1 >>
+rect -170 1693 738 1745
+rect -126 1356 -73 1636
+rect 66 1356 119 1636
+rect 257 1357 310 1637
+rect 450 1356 502 1636
+rect 642 1356 694 1636
+rect 209 617 261 897
+rect 78 361 286 413
+rect 366 361 490 413
+rect 641 361 693 413
+rect 209 37 261 167
+rect 629 8 733 60
+rect 805 -140 861 -85
+rect 805 -141 861 -140
+rect -126 -693 -73 -413
+rect 66 -693 119 -413
+rect 257 -692 310 -412
+rect 450 -693 502 -413
+rect 642 -693 694 -413
+rect -170 -793 738 -741
+<< metal2 >>
+rect -180 1745 748 1755
+rect -180 1693 -170 1745
+rect 738 1693 748 1745
+rect -180 1683 748 1693
+rect -126 1636 -73 1646
+rect 66 1636 119 1646
+rect -73 1436 66 1563
+rect -126 1346 -73 1356
+rect 257 1637 310 1647
+rect 119 1436 257 1563
+rect 66 1346 119 1356
+rect 209 1357 257 1436
+rect 450 1636 502 1646
+rect 310 1436 450 1563
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+rect 642 1636 694 1646
+rect 502 1436 642 1563
+rect 209 897 261 1347
+rect 450 1346 502 1356
+rect 642 1346 694 1356
+rect 639 1042 719 1046
+rect 831 1042 851 1046
+rect 209 607 261 617
+rect 78 413 286 423
+rect 68 361 78 413
+rect 78 351 286 361
+rect 366 413 490 423
+rect 641 413 693 423
+rect 490 361 641 413
+rect 693 361 931 413
+rect 366 351 490 361
+rect 641 351 693 361
+rect 209 167 261 177
+rect 209 -402 261 37
+rect 629 62 733 72
+rect 629 -4 733 6
+rect 805 -85 861 -75
+rect 805 -151 861 -141
+rect -126 -413 -73 -403
+rect 66 -413 119 -403
+rect -73 -613 66 -486
+rect -126 -703 -73 -693
+rect 209 -412 310 -402
+rect 209 -486 257 -412
+rect 119 -613 257 -486
+rect 66 -703 119 -693
+rect 450 -413 502 -403
+rect 310 -613 450 -486
+rect 257 -702 310 -692
+rect 642 -413 694 -403
+rect 502 -613 642 -486
+rect 450 -703 502 -693
+rect 642 -703 694 -693
+rect -180 -741 748 -731
+rect -180 -793 -170 -741
+rect 738 -793 748 -741
+rect -180 -802 748 -793
+rect -180 -803 738 -802
+<< via2 >>
+rect 719 990 831 1046
+rect 629 60 733 62
+rect 629 8 733 60
+rect 629 6 733 8
+rect 805 -141 861 -85
+<< metal3 >>
+rect 709 1046 863 1051
+rect 709 990 719 1046
+rect 831 990 863 1046
+rect 709 985 863 990
+rect 619 62 743 67
+rect 619 6 629 62
+rect 733 6 743 62
+rect 619 1 743 6
+rect 650 -194 710 1
+rect 803 -80 863 985
+rect 795 -85 871 -80
+rect 795 -141 805 -85
+rect 861 -141 871 -85
+rect 795 -146 871 -141
+use cap_vco cap_vco_0
+timestamp 1624049879
+transform 1 0 5 0 1 528
+box 554 -6 926 514
+use inverter_csvco inverter_csvco_0
+timestamp 1624049879
+transform 1 0 68 0 1 387
+box 0 -597 432 757
+use sky130_fd_pr__pfet_01v8_8DL6ZL sky130_fd_pr__pfet_01v8_8DL6ZL_0
+timestamp 1624049879
+transform -1 0 284 0 -1 1496
+box -647 -369 647 369
+use sky130_fd_pr__nfet_01v8_7H8F5S sky130_fd_pr__nfet_01v8_7H8F5S_0
+timestamp 1624049879
+transform 1 0 284 0 -1 -553
+box -647 -360 647 360
+use sky130_fd_pr__nfet_01v8_EDT3AT sky130_fd_pr__nfet_01v8_EDT3AT_0
+timestamp 1624049879
+transform 1 0 711 0 1 100
+box -211 -221 211 221
+<< labels >>
+rlabel metal1 -363 1829 931 1884 1 vdd
+rlabel metal1 -363 -932 931 -877 1 vss
+rlabel metal2 -180 -803 -170 -731 1 vctrl
+rlabel metal2 -180 1683 -170 1755 1 vbp
+rlabel metal2 68 361 78 413 1 in
+rlabel metal3 650 -194 710 6 1 D0
+rlabel metal2 693 361 931 413 1 out
+<< end >>
diff --git a/mag/csvco_branch_v2.mag b/mag/csvco_branch_v2.mag
new file mode 100644
index 0000000..61b2c26
--- /dev/null
+++ b/mag/csvco_branch_v2.mag
@@ -0,0 +1,219 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624064496
+<< nwell >>
+rect -363 387 931 1955
+<< pwell >>
+rect -363 -680 931 387
+rect -363 -771 162 -680
+rect 184 -771 931 -680
+rect -363 -1002 931 -771
+<< psubdiff >>
+rect 608 -174 632 -140
+rect 790 -174 814 -140
+rect -255 -966 -231 -932
+rect 799 -966 823 -932
+<< nsubdiff >>
+rect -247 1871 -223 1905
+rect 807 1871 831 1905
+<< psubdiffcont >>
+rect 632 -174 790 -140
+rect -231 -966 799 -932
+<< nsubdiffcont >>
+rect -223 1871 807 1905
+<< locali >>
+rect -239 1871 -223 1905
+rect 807 1871 823 1905
+<< viali >>
+rect -223 1871 807 1905
+rect 104 1742 454 1776
+rect 104 1214 138 1742
+rect 420 1214 454 1742
+rect 104 1180 454 1214
+rect 536 -85 886 -51
+rect 536 -174 632 -140
+rect 632 -174 790 -140
+rect 790 -174 886 -140
+rect 106 -285 456 -251
+rect 106 -796 140 -285
+rect 422 -796 456 -285
+rect 106 -837 459 -796
+rect -327 -966 -231 -932
+rect -231 -966 799 -932
+rect 799 -966 895 -932
+<< metal1 >>
+rect -363 1905 931 1911
+rect -363 1871 -223 1905
+rect 807 1871 931 1905
+rect -363 1776 931 1871
+rect -363 1736 104 1776
+rect 68 1180 104 1736
+rect 138 1736 420 1742
+rect 138 1220 144 1736
+rect 185 1641 195 1699
+rect 307 1641 317 1699
+rect 247 1630 311 1641
+rect 347 1595 420 1736
+rect 174 1278 184 1569
+rect 252 1278 262 1569
+rect 342 1291 420 1595
+rect 414 1220 420 1291
+rect 138 1214 420 1220
+rect 454 1736 931 1776
+rect 454 1180 500 1736
+rect 68 1108 500 1180
+rect 209 897 261 907
+rect 209 607 261 617
+rect 68 361 78 413
+rect 286 361 296 413
+rect 356 361 366 413
+rect 490 361 500 413
+rect 631 361 641 413
+rect 693 361 703 413
+rect 209 167 261 177
+rect 644 173 690 361
+rect 760 89 770 234
+rect 831 89 841 234
+rect 209 27 261 37
+rect 619 8 629 60
+rect 733 8 743 60
+rect 61 -174 81 -45
+rect 500 -51 931 -45
+rect 500 -85 536 -51
+rect 886 -85 931 -51
+rect 500 -140 931 -85
+rect 500 -174 536 -140
+rect 886 -174 931 -140
+rect 61 -220 931 -174
+rect 61 -251 932 -220
+rect 61 -790 106 -251
+rect 456 -256 932 -251
+rect 456 -257 737 -256
+rect -363 -837 106 -790
+rect 140 -291 422 -285
+rect 140 -790 146 -291
+rect 416 -364 422 -291
+rect 191 -651 201 -374
+rect 258 -651 268 -374
+rect 249 -701 313 -692
+rect 178 -704 313 -701
+rect 178 -756 184 -704
+rect 308 -756 318 -704
+rect 347 -790 422 -364
+rect 140 -796 422 -790
+rect 456 -291 468 -257
+rect 456 -790 462 -291
+rect 456 -796 931 -790
+rect 459 -837 931 -796
+rect -363 -932 931 -837
+rect -363 -966 -327 -932
+rect 895 -966 931 -932
+rect -363 -972 931 -966
+<< via1 >>
+rect 195 1641 307 1699
+rect 184 1278 252 1569
+rect 209 617 261 897
+rect 78 361 286 413
+rect 366 361 490 413
+rect 641 361 693 413
+rect 209 37 261 167
+rect 770 89 831 234
+rect 629 8 733 60
+rect 201 -651 258 -374
+rect 184 -756 308 -704
+<< metal2 >>
+rect 195 1699 307 1709
+rect 80 1641 195 1682
+rect 307 1641 312 1682
+rect 80 1629 312 1641
+rect 184 1574 252 1579
+rect 184 1569 261 1574
+rect 252 1278 261 1569
+rect 184 1268 261 1278
+rect 209 897 261 1268
+rect 209 607 261 617
+rect 78 413 286 423
+rect 68 361 78 413
+rect 78 351 286 361
+rect 366 413 490 423
+rect 641 413 693 423
+rect 490 361 641 413
+rect 693 361 931 413
+rect 366 351 490 361
+rect 641 351 693 361
+rect 813 244 874 245
+rect 770 235 874 244
+rect 770 234 813 235
+rect 209 167 261 177
+rect 831 89 874 90
+rect 770 80 874 89
+rect 770 79 831 80
+rect 209 -364 261 37
+rect 629 62 733 72
+rect 629 -4 733 6
+rect 201 -374 261 -364
+rect 258 -463 261 -374
+rect 201 -661 258 -651
+rect 184 -703 308 -694
+rect 699 -703 886 -702
+rect 73 -704 321 -703
+rect 73 -756 184 -704
+rect 308 -756 321 -704
+rect 699 -713 900 -703
+rect 699 -748 797 -713
+rect 73 -758 321 -756
+rect 184 -766 308 -758
+rect 797 -781 900 -771
+<< via2 >>
+rect 813 234 874 235
+rect 813 90 831 234
+rect 831 90 874 234
+rect 629 60 733 62
+rect 629 8 733 60
+rect 629 6 733 8
+rect 797 -771 900 -713
+<< metal3 >>
+rect 803 239 884 240
+rect 803 235 886 239
+rect 803 90 813 235
+rect 874 90 886 235
+rect 803 85 886 90
+rect 619 62 743 67
+rect 619 6 629 62
+rect 733 6 743 62
+rect 619 1 743 6
+rect 650 -194 710 1
+rect 819 -708 886 85
+rect 787 -713 910 -708
+rect 787 -771 797 -713
+rect 900 -771 910 -713
+rect 787 -776 910 -771
+use cap_vco cap_vco_0
+timestamp 1624049879
+transform 1 0 -37 0 1 -744
+box 554 -6 926 514
+use sky130_fd_pr__nfet_01v8_EDT3AT sky130_fd_pr__nfet_01v8_EDT3AT_0
+timestamp 1624049879
+transform 1 0 711 0 1 100
+box -211 -221 211 221
+use sky130_fd_pr__nfet_01v8_CBSTVW sky130_fd_pr__nfet_01v8_CBSTVW_0
+timestamp 1624058804
+transform 1 0 281 0 1 -544
+box -211 -329 211 329
+use inverter_csvco inverter_csvco_0
+timestamp 1624049879
+transform 1 0 68 0 1 387
+box 0 -597 432 757
+use sky130_fd_pr__pfet_01v8_MJP3BN sky130_fd_pr__pfet_01v8_MJP3BN_0
+timestamp 1624058804
+transform 1 0 279 0 1 1478
+box -211 -334 211 334
+<< labels >>
+rlabel metal2 68 361 78 413 1 in
+rlabel metal3 650 -194 710 6 1 D0
+rlabel metal2 693 361 931 413 1 out
+rlabel metal2 73 -758 177 -703 1 vctrl
+rlabel metal1 -363 1776 931 1871 1 vdd
+rlabel metal1 -363 -932 931 -837 1 vss
+<< end >>
diff --git a/mag/dff_pfd.mag b/mag/dff_pfd.mag
new file mode 100644
index 0000000..f239682
--- /dev/null
+++ b/mag/dff_pfd.mag
@@ -0,0 +1,88 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< metal1 >>
+rect 0 1180 2872 1234
+rect 0 652 210 718
+rect 545 714 846 718
+rect 545 662 791 714
+rect 895 662 905 714
+rect 1438 662 1448 714
+rect 1552 662 1562 714
+rect 545 652 846 662
+rect 1979 652 2308 718
+rect 1234 572 1244 624
+rect 1348 572 1358 624
+rect 256 497 266 549
+rect 370 497 380 549
+rect 896 472 906 524
+rect 1010 472 1020 524
+rect 1616 481 1626 533
+rect 1730 481 1740 533
+rect 2154 436 2220 557
+rect 2680 481 2690 533
+rect 2794 481 2804 533
+rect 1949 380 1959 432
+rect 2063 380 2073 432
+rect 2149 332 2159 436
+rect 2211 332 2221 436
+rect 2154 329 2220 332
+rect 0 70 2872 124
+<< via1 >>
+rect 791 662 895 714
+rect 1448 662 1552 714
+rect 1244 572 1348 624
+rect 266 497 370 549
+rect 906 472 1010 524
+rect 1626 481 1730 533
+rect 2690 481 2794 533
+rect 1959 380 2063 432
+rect 2159 332 2211 436
+<< metal2 >>
+rect 791 714 895 724
+rect 1448 714 1552 724
+rect 895 662 1448 714
+rect 791 652 895 662
+rect 1448 652 1552 662
+rect 1244 624 1348 634
+rect 266 572 1244 624
+rect 1348 572 2872 624
+rect 266 549 370 572
+rect 1244 562 1348 572
+rect 266 487 370 497
+rect 906 524 1010 534
+rect 906 462 1010 472
+rect 1626 533 2794 543
+rect 1730 491 2690 533
+rect 1626 471 1730 481
+rect 2690 471 2794 481
+rect 931 432 983 462
+rect 1959 432 2063 442
+rect 931 380 1959 432
+rect 1959 370 2063 380
+rect 2159 436 2211 446
+rect 2159 322 2211 332
+use nor_pfd nor_pfd_0
+timestamp 1624049879
+transform 1 0 235 0 1 -468
+box -235 468 483 1772
+use nor_pfd nor_pfd_1
+timestamp 1624049879
+transform 1 0 953 0 1 -468
+box -235 468 483 1772
+use nor_pfd nor_pfd_2
+timestamp 1624049879
+transform 1 0 1671 0 1 -468
+box -235 468 483 1772
+use nor_pfd nor_pfd_3
+timestamp 1624049879
+transform 1 0 2389 0 1 -468
+box -235 468 483 1772
+<< labels >>
+rlabel metal1 0 652 210 718 1 CLK
+rlabel metal1 0 1180 2872 1234 1 vdd
+rlabel metal1 0 70 2872 124 1 vss
+rlabel metal2 2768 572 2872 624 1 Q
+rlabel via1 2159 332 2211 436 1 Reset
+<< end >>
diff --git a/mag/div_by_2.mag b/mag/div_by_2.mag
new file mode 100644
index 0000000..333a768
--- /dev/null
+++ b/mag/div_by_2.mag
@@ -0,0 +1,204 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624402156
+<< nwell >>
+rect 2984 2989 4228 3068
+rect 3203 118 4219 142
+rect 3203 84 4228 118
+rect 3203 83 4219 84
+rect 3203 79 4228 83
+rect 2984 0 4228 79
+<< pwell >>
+rect 2983 1339 4228 1819
+<< locali >>
+rect 1986 2123 2002 2157
+rect 2224 2123 2240 2157
+<< metal1 >>
+rect 2984 3022 4228 3038
+rect 2947 2998 4228 3022
+rect -1244 2957 4228 2998
+rect -1244 2944 3720 2957
+rect 2947 2931 3720 2944
+rect 2986 2918 3533 2931
+rect -190 2228 -180 2356
+rect -116 2228 -106 2356
+rect 2984 2267 2994 2323
+rect 3218 2267 3228 2323
+rect 3352 2253 3753 2333
+rect 4061 2249 4228 2327
+rect 1990 2121 2000 2173
+rect 2226 2121 2236 2173
+rect 1990 2117 2236 2121
+rect 2915 1848 2984 1864
+rect 2915 1825 3020 1848
+rect 2915 1730 4224 1825
+rect 2915 1700 4228 1730
+rect -1244 1498 1313 1570
+rect 2915 1369 3020 1700
+rect 3412 1369 3726 1700
+rect 2915 1339 4228 1369
+rect 2915 1321 3726 1339
+rect 2915 1282 3556 1321
+rect 2915 1266 3130 1282
+rect 2915 1246 3020 1266
+rect 2915 1204 2984 1246
+rect 1992 947 2238 951
+rect 1992 895 2002 947
+rect 2228 895 2238 947
+rect -150 712 -140 840
+rect -76 712 -66 840
+rect 2981 748 2991 804
+rect 3215 748 3225 804
+rect 3352 736 3753 816
+rect 4061 742 4228 820
+rect 2915 148 4220 164
+rect 2915 30 4228 148
+<< via1 >>
+rect -180 2228 -116 2356
+rect 2994 2267 3218 2323
+rect 2000 2121 2226 2173
+rect 2002 895 2228 947
+rect -140 712 -76 840
+rect 2991 748 3215 804
+<< metal2 >>
+rect -180 2356 -116 2366
+rect -180 2218 -116 2228
+rect 2081 2321 2145 2331
+rect 2000 2173 2081 2183
+rect 2994 2323 3218 2333
+rect 2994 2257 3218 2267
+rect 2145 2173 2226 2183
+rect 2000 2111 2226 2121
+rect 250 1569 306 1579
+rect 2555 1570 2611 1580
+rect 306 1477 2555 1549
+rect 306 1475 323 1477
+rect 250 1447 306 1457
+rect 2611 1477 2621 1549
+rect 2555 1448 2611 1458
+rect 2002 947 2228 957
+rect 2002 885 2083 895
+rect -140 840 -76 850
+rect 2147 885 2228 895
+rect 2083 734 2147 744
+rect 2991 804 3215 814
+rect 2991 738 3215 748
+rect -140 702 -76 712
+<< via2 >>
+rect -180 2228 -116 2356
+rect 2081 2173 2145 2321
+rect 2994 2267 3218 2323
+rect 2081 2121 2145 2173
+rect 250 1457 306 1569
+rect 2555 1458 2611 1570
+rect 2083 895 2147 900
+rect -140 712 -76 840
+rect 2083 744 2147 895
+rect 2991 748 3215 804
+<< metal3 >>
+rect -190 2356 -106 2361
+rect -997 804 -937 2264
+rect -190 2228 -180 2356
+rect -116 2228 -106 2356
+rect -190 2223 -106 2228
+rect 2071 2321 2155 2326
+rect 2071 2121 2081 2321
+rect 2145 2121 2155 2321
+rect 2763 2325 2823 2474
+rect 2984 2325 3228 2328
+rect 2763 2323 3246 2325
+rect 2763 2267 2994 2323
+rect 3218 2267 3246 2323
+rect 2763 2265 3246 2267
+rect 2071 2116 2155 2121
+rect 2553 1575 2613 2258
+rect 240 1569 316 1574
+rect 240 1457 250 1569
+rect 306 1457 316 1569
+rect 240 1452 316 1457
+rect 2545 1570 2621 1575
+rect 2545 1458 2555 1570
+rect 2611 1458 2621 1570
+rect 2545 1453 2621 1458
+rect 2073 945 2157 950
+rect -150 840 -66 845
+rect -150 712 -140 840
+rect -76 712 -66 840
+rect 2073 744 2083 945
+rect 2147 744 2157 945
+rect 2073 739 2157 744
+rect -150 707 -66 712
+rect 2553 596 2613 1453
+rect 2763 810 2823 2265
+rect 2984 2262 3228 2265
+rect 2981 808 3225 809
+rect 2977 804 3225 808
+rect 2977 748 2991 804
+rect 3215 748 3225 804
+rect 2977 743 3225 748
+rect 2977 596 3037 743
+rect 2528 536 3037 596
+<< via3 >>
+rect -180 2228 -116 2356
+rect 2081 2121 2145 2321
+rect -140 712 -76 840
+rect 2083 900 2147 945
+rect 2083 744 2147 900
+<< metal4 >>
+rect -181 2356 -115 2357
+rect -181 2228 -180 2356
+rect -116 2324 -115 2356
+rect -116 2322 2139 2324
+rect -116 2321 2146 2322
+rect -116 2260 2081 2321
+rect -116 2228 -115 2260
+rect -181 2227 -115 2228
+rect 2080 2121 2081 2260
+rect 2145 2121 2146 2321
+rect 2080 2120 2146 2121
+rect 2082 945 2148 946
+rect -141 840 -75 841
+rect -141 712 -140 840
+rect -76 808 -75 840
+rect 2082 808 2083 945
+rect -76 744 2083 808
+rect 2147 744 2148 945
+rect -76 712 -75 744
+rect 2082 743 2148 744
+rect -141 711 -75 712
+use DFlipFlop DFlipFlop_0
+timestamp 1624049879
+transform 1 0 1244 0 -1 3068
+box -1244 0 1740 3068
+use inverter_min_x4 inverter_min_x4_0
+timestamp 1624049879
+transform 1 0 3563 0 1 2346
+box -53 -616 665 643
+use inverter_min_x4 inverter_min_x4_1
+timestamp 1624049879
+transform 1 0 3563 0 -1 723
+box -53 -616 665 643
+use inverter_min_x2 inverter_min_x2_1
+timestamp 1624049879
+transform 1 0 3037 0 1 2345
+box -53 -615 473 655
+use inverter_min_x2 inverter_min_x2_0
+timestamp 1624049879
+transform 1 0 3037 0 -1 723
+box -53 -615 473 655
+use clock_inverter clock_inverter_0
+timestamp 1624049879
+transform 1 0 -1244 0 1 0
+box 0 0 1244 3068
+<< labels >>
+rlabel metal1 -1244 2944 2984 2998 1 vdd
+rlabel metal1 -1244 1498 1313 1570 1 vss
+rlabel metal3 -997 1498 -937 1570 1 CLK
+rlabel metal3 2553 1570 2613 2258 1 nout_div
+rlabel metal3 2763 810 2823 2474 1 out_div
+rlabel metal1 4061 2249 4228 2327 1 CLK_2
+rlabel metal1 3352 2253 3753 2333 1 o1
+rlabel metal1 3352 736 3753 816 1 o2
+rlabel metal1 4061 742 4228 820 1 nCLK_2
+<< end >>
diff --git a/mag/div_by_5.mag b/mag/div_by_5.mag
new file mode 100644
index 0000000..4f8c55d
--- /dev/null
+++ b/mag/div_by_5.mag
@@ -0,0 +1,363 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624402156
+<< nwell >>
+rect -556 2925 0 3068
+rect -556 2664 57 2925
+rect -111 2561 57 2664
+rect -40 2555 57 2561
+rect -30 2544 57 2555
+rect 1803 2292 7702 3068
+rect 9171 2292 9793 3068
+rect 12155 2292 12777 3068
+rect 13336 2664 13892 3068
+rect -556 0 0 776
+rect 1803 0 2425 776
+rect 2984 0 3540 404
+rect 5343 0 11242 776
+rect 12155 0 12777 776
+rect 13336 0 13892 776
+<< pwell >>
+rect -556 2241 -150 2292
+rect -40 2241 0 2292
+rect -556 776 0 2241
+rect 5965 776 7368 2292
+rect 13336 776 13892 2292
+<< viali >>
+rect -134 2343 -55 2507
+rect 13765 2324 13836 2537
+rect -312 2204 -237 2294
+rect 6771 2238 7063 2299
+rect 7175 2196 7309 2283
+rect 13405 2206 13518 2260
+rect 13581 2230 13645 2316
+rect -523 2043 -356 2093
+rect 6736 2050 6825 2183
+rect 2989 974 3189 1025
+rect 3228 773 3304 866
+rect 3406 536 3486 738
+<< metal1 >>
+rect -556 2904 13892 3038
+rect -357 2643 -199 2904
+rect 6819 2643 7074 2904
+rect 13535 2643 13693 2904
+rect 13759 2537 13842 2549
+rect -144 2330 -134 2521
+rect -55 2330 -45 2521
+rect -333 2199 -323 2317
+rect -223 2199 -213 2317
+rect 6263 2308 7075 2367
+rect 6759 2299 7075 2308
+rect 6759 2238 6771 2299
+rect 7063 2238 7075 2299
+rect 6759 2232 7075 2238
+rect -318 2192 -231 2199
+rect 7163 2196 7175 2336
+rect 7309 2196 7321 2336
+rect 13395 2266 13405 2298
+rect 13393 2206 13405 2266
+rect 13518 2266 13528 2298
+rect 13518 2206 13530 2266
+rect 13569 2230 13579 2334
+rect 13645 2230 13655 2334
+rect 13759 2324 13765 2537
+rect 13836 2324 13842 2537
+rect 13759 2312 13842 2324
+rect 13575 2218 13651 2230
+rect 13393 2200 13530 2206
+rect -535 2093 -516 2152
+rect -385 2093 -344 2152
+rect 1987 2120 1997 2184
+rect 2237 2120 2247 2184
+rect 5527 2120 5537 2184
+rect 5777 2120 5787 2184
+rect 6730 2183 6831 2195
+rect 7163 2190 7321 2196
+rect -535 2043 -523 2093
+rect -356 2043 -344 2093
+rect 6701 2050 6711 2183
+rect 6849 2050 6859 2183
+rect 9355 2120 9365 2184
+rect 9605 2120 9615 2184
+rect 12339 2120 12349 2184
+rect 12589 2120 12599 2184
+rect -535 2037 -516 2043
+rect -385 2037 -344 2043
+rect 6730 2038 6831 2050
+rect -357 1698 -199 1943
+rect 6819 1698 7073 1944
+rect 13535 1698 13693 1943
+rect -556 1416 36 1698
+rect -556 1370 0 1416
+rect 2984 1370 3540 1698
+rect 6524 1370 7371 1698
+rect 13317 1370 13892 1698
+rect 3183 1125 3341 1370
+rect 2964 1025 3201 1031
+rect 2964 974 2989 1025
+rect 3189 974 3201 1025
+rect 2964 968 3201 974
+rect 1981 884 1991 948
+rect 2231 884 2241 948
+rect 2964 760 3023 968
+rect 5521 884 5531 948
+rect 5771 884 5781 948
+rect 9349 884 9359 948
+rect 9599 884 9609 948
+rect 12333 884 12343 948
+rect 12583 884 12593 948
+rect 3222 872 3310 878
+rect 3218 771 3228 872
+rect 3304 771 3314 872
+rect 3222 761 3310 771
+rect 2652 701 3023 760
+rect 3400 738 3492 750
+rect 3396 536 3406 738
+rect 3486 536 3496 738
+rect 3400 524 3492 536
+rect 3183 164 3341 425
+rect -556 30 13892 164
+<< via1 >>
+rect -134 2507 -55 2521
+rect -134 2343 -55 2507
+rect -134 2330 -55 2343
+rect -323 2294 -223 2317
+rect -323 2204 -312 2294
+rect -312 2204 -237 2294
+rect -237 2204 -223 2294
+rect -323 2199 -223 2204
+rect 7175 2283 7309 2336
+rect 7175 2196 7309 2283
+rect 13405 2260 13518 2298
+rect 13405 2206 13518 2260
+rect 13579 2316 13645 2334
+rect 13579 2230 13581 2316
+rect 13581 2230 13645 2316
+rect -516 2093 -385 2152
+rect 1997 2120 2237 2184
+rect 5537 2120 5777 2184
+rect -516 2043 -385 2093
+rect 6711 2050 6736 2183
+rect 6736 2050 6825 2183
+rect 6825 2050 6849 2183
+rect 9365 2120 9605 2184
+rect 12349 2120 12589 2184
+rect -516 2037 -385 2043
+rect 1991 884 2231 948
+rect 5531 884 5771 948
+rect 9359 884 9599 948
+rect 12343 884 12583 948
+rect 3228 866 3304 872
+rect 3228 773 3304 866
+rect 3228 771 3304 773
+rect 3406 536 3486 738
+<< metal2 >>
+rect -516 2737 7309 2869
+rect -516 2152 -384 2737
+rect 7175 2700 7309 2737
+rect -326 2568 6364 2700
+rect -326 2317 -221 2568
+rect -326 2199 -323 2317
+rect -223 2199 -221 2317
+rect -134 2521 -55 2531
+rect -134 2254 227 2330
+rect 6232 2287 6364 2568
+rect 7175 2685 10684 2700
+rect 7175 2573 10572 2685
+rect 7175 2568 10684 2573
+rect 7175 2336 7309 2568
+rect 10572 2563 10684 2568
+rect 13089 2464 13529 2540
+rect -326 2197 -221 2199
+rect -323 2189 -223 2197
+rect 10137 2259 10572 2325
+rect 13395 2298 13529 2464
+rect 13395 2206 13405 2298
+rect 13518 2206 13529 2298
+rect 13395 2196 13529 2206
+rect 13569 2230 13579 2334
+rect 13645 2230 13655 2334
+rect -385 2037 -384 2152
+rect 1997 2184 2237 2194
+rect 1997 2110 2237 2120
+rect 5537 2184 5777 2194
+rect 5537 2110 5777 2120
+rect 6711 2183 6849 2193
+rect 7175 2186 7309 2196
+rect -516 2015 -384 2037
+rect 9365 2184 9605 2194
+rect 9365 2110 9605 2120
+rect 12349 2184 12589 2194
+rect 12349 2110 12589 2120
+rect 6095 1601 6151 1611
+rect 3237 1518 6095 1594
+rect 1991 948 2231 958
+rect 1991 874 2231 884
+rect 3237 882 3313 1518
+rect 6095 1469 6151 1479
+rect 6711 1599 6849 2050
+rect 6711 1591 7683 1599
+rect 6711 1469 7617 1591
+rect 7673 1469 7683 1591
+rect 10133 1590 10189 1600
+rect 10131 1498 10133 1570
+rect 6711 1461 7683 1469
+rect 10601 1590 10657 1600
+rect 10189 1498 10601 1570
+rect 10133 1468 10189 1478
+rect 10657 1550 11273 1570
+rect 13569 1564 13655 2230
+rect 11484 1550 13655 1564
+rect 10657 1478 13655 1550
+rect 10601 1468 10657 1478
+rect 3228 872 3313 882
+rect 5531 948 5771 958
+rect 5531 874 5771 884
+rect 9359 948 9599 958
+rect 9359 874 9599 884
+rect 12343 948 12583 958
+rect 12343 874 12583 884
+rect 3304 776 3313 872
+rect 3228 761 3304 771
+rect 3406 738 3767 814
+rect 10131 743 10578 809
+rect 3406 526 3486 536
+rect 3406 525 3482 526
+<< via2 >>
+rect 10572 2573 10684 2685
+rect 1997 2120 2237 2184
+rect 5537 2120 5777 2184
+rect 9365 2120 9605 2184
+rect 12349 2120 12589 2184
+rect 1991 884 2231 948
+rect 6095 1479 6151 1601
+rect 7617 1469 7673 1591
+rect 10133 1478 10189 1590
+rect 10601 1478 10657 1590
+rect 5531 884 5771 948
+rect 9359 884 9599 948
+rect 12343 884 12583 948
+<< metal3 >>
+rect 10562 2685 10694 2690
+rect 10562 2573 10572 2685
+rect 10684 2573 10694 2685
+rect 10562 2568 10694 2573
+rect 1987 2184 2247 2189
+rect 1987 2120 1997 2184
+rect 2237 2120 2247 2184
+rect 1987 2115 2247 2120
+rect 5527 2184 5787 2189
+rect 5527 2120 5537 2184
+rect 5777 2120 5787 2184
+rect 5527 2115 5787 2120
+rect 9355 2184 9615 2189
+rect 9355 2120 9365 2184
+rect 9605 2120 9615 2184
+rect 9355 2115 9615 2120
+rect 6085 1601 6161 1606
+rect 6085 1479 6095 1601
+rect 6151 1479 6161 1601
+rect 6085 1474 6161 1479
+rect 7607 1591 7683 1596
+rect 10599 1595 10659 2568
+rect 12339 2184 12599 2189
+rect 12339 2120 12349 2184
+rect 12589 2120 12599 2184
+rect 12339 2115 12599 2120
+rect 7607 1469 7617 1591
+rect 7673 1469 7683 1591
+rect 10123 1590 10199 1595
+rect 10123 1478 10133 1590
+rect 10189 1478 10199 1590
+rect 10123 1473 10199 1478
+rect 10591 1590 10667 1595
+rect 10591 1478 10601 1590
+rect 10657 1478 10667 1590
+rect 10591 1473 10667 1478
+rect 7607 1464 7683 1469
+rect 1981 948 2241 953
+rect 1981 884 1991 948
+rect 2231 884 2241 948
+rect 1981 879 2241 884
+rect 5521 948 5781 953
+rect 5521 884 5531 948
+rect 5771 884 5781 948
+rect 5521 879 5781 884
+rect 9349 948 9609 953
+rect 9349 884 9359 948
+rect 9599 884 9609 948
+rect 9349 879 9609 884
+rect 10599 804 10659 1473
+rect 12333 948 12593 953
+rect 12333 884 12343 948
+rect 12583 884 12593 948
+rect 12333 879 12593 884
+<< via3 >>
+rect 1997 2120 2237 2184
+rect 5537 2120 5777 2184
+rect 9365 2120 9605 2184
+rect 12349 2120 12589 2184
+rect 1991 884 2231 948
+rect 5531 884 5771 948
+rect 9359 884 9599 948
+rect 12343 884 12583 948
+<< metal4 >>
+rect 1996 2184 12590 2185
+rect 1996 2120 1997 2184
+rect 2237 2120 5537 2184
+rect 5777 2120 9365 2184
+rect 9605 2120 12349 2184
+rect 12589 2120 12590 2184
+rect 1996 2119 12590 2120
+rect 1990 948 12584 949
+rect 1990 884 1991 948
+rect 2231 884 5531 948
+rect 5771 884 9359 948
+rect 9599 884 12343 948
+rect 12583 884 12584 948
+rect 1990 883 12584 884
+use DFlipFlop DFlipFlop_3
+timestamp 1624049879
+transform 1 0 11596 0 -1 3068
+box -1244 0 1740 3068
+use DFlipFlop DFlipFlop_1
+timestamp 1624049879
+transform 1 0 4784 0 1 0
+box -1244 0 1740 3068
+use DFlipFlop DFlipFlop_2
+timestamp 1624049879
+transform 1 0 8612 0 1 0
+box -1244 0 1740 3068
+use DFlipFlop DFlipFlop_0
+timestamp 1624049879
+transform 1 0 1244 0 1 0
+box -1244 0 1740 3068
+use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_1
+timestamp 1624049879
+transform 1 0 3022 0 -1 1108
+box -38 -49 518 715
+use sky130_fd_sc_hs__xor2_1 sky130_fd_sc_hs__xor2_1_0
+timestamp 1624049879
+transform -1 0 7330 0 1 1960
+box -38 -49 806 715
+use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_0
+timestamp 1624049879
+transform 1 0 -518 0 1 1960
+box -38 -49 518 715
+use sky130_fd_sc_hs__or2_1 sky130_fd_sc_hs__or2_1_0
+timestamp 1624049879
+transform 1 0 13374 0 1 1960
+box -38 -49 518 715
+<< labels >>
+rlabel metal2 7175 2568 10572 2700 1 Q1
+rlabel metal1 6263 2308 7075 2367 1 Q0
+rlabel metal1 -556 1370 0 1698 1 vss
+rlabel metal1 2652 701 3023 760 1 nQ2
+rlabel metal4 5771 883 9359 949 1 CLK
+rlabel metal4 5777 2119 9365 2185 1 nCLK
+rlabel metal1 -556 2904 13892 3038 1 vdd
+rlabel viali 13765 2324 13836 2537 1 CLK_5
+rlabel metal2 3237 1518 6095 1594 1 nQ0
+rlabel metal2 13089 2464 13529 2540 1 Q1_shift
+<< end >>
diff --git a/mag/example.gds b/mag/example.gds
new file mode 100644
index 0000000..6f69f04
--- /dev/null
+++ b/mag/example.gds
Binary files differ
diff --git a/mag/extractions/csvco_branch_v2_lvs.spice b/mag/extractions/csvco_branch_v2_lvs.spice
new file mode 100644
index 0000000..b104bdf
--- /dev/null
+++ b/mag/extractions/csvco_branch_v2_lvs.spice
@@ -0,0 +1,43 @@
+* NGSPICE file created from csvco_branch_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+*C1 t VSUBS 0.42fF
+*C2 b VSUBS 0.09fF
+.ends
+
+* Top level circuit csvco_branch_v2
+
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+.end
+
diff --git a/mag/extractions/csvco_branch_v2_pex_c.spice b/mag/extractions/csvco_branch_v2_pex_c.spice
new file mode 100644
index 0000000..a271b47
--- /dev/null
+++ b/mag/extractions/csvco_branch_v2_pex_c.spice
@@ -0,0 +1,104 @@
+* NGSPICE file created from csvco_branch_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n119# a_n33_n207# 0.02fF
+C1 a_n33_n207# a_15_n119# 0.02fF
+C2 a_n73_n119# a_15_n119# 0.51fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n186# a_15_n186# 0.51fF
+C1 a_n73_n186# a_n33_145# 0.01fF
+C2 w_n211_n334# a_15_n186# 0.21fF
+C3 w_n211_n334# a_n33_145# 0.05fF
+C4 w_n211_n334# a_n73_n186# 0.21fF
+C5 a_15_n186# a_n33_145# 0.01fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n73_n11# 0.15fF
+C1 a_n33_n99# a_n73_n11# 0.02fF
+C2 a_n33_n99# a_15_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# a_20_n114# 0.42fF
+C1 w_n216_n334# a_20_n114# 0.20fF
+C2 w_n216_n334# a_n78_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vdd vbulkp 0.04fF
+C1 out in 0.11fF
+C2 out vbulkp 0.08fF
+C3 in vdd 0.01fF
+C4 in vss 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+
+* Top level circuit csvco_branch_v2
+
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C1 vdd cap_vco_0/t 0.06fF
+C2 inverter_csvco_0/vss vctrl 0.23fF
+C3 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C4 inverter_csvco_0/vss in 0.01fF
+C5 inverter_csvco_0/vdd vdd 0.97fF
+C6 inverter_csvco_0/vss out 0.03fF
+C7 out cap_vco_0/t 0.70fF
+C8 D0 out 0.09fF
+C9 out vdd 0.03fF
+C10 inverter_csvco_0/vdd in 0.01fF
+C11 inverter_csvco_0/vdd out 0.02fF
+C12 out in 0.06fF
+C13 m1_185_1641# vdd 0.48fF
+C14 inverter_csvco_0/vss D0 0.01fF
+C15 vdd vss 3.61fF
+C16 out vss 0.94fF
+C17 inverter_csvco_0/vdd vss 0.23fF
+C18 in vss 0.70fF
+C19 inverter_csvco_0/vss vss 0.61fF
+C20 D0 vss -0.68fF
+C21 m1_185_1641# vss -0.03fF
+C22 cap_vco_0/t vss 7.22fF
+C23 vctrl vss 0.44fF
+.end
+
diff --git a/mag/extractions/csvco_branch_v2_pex_rc.spice b/mag/extractions/csvco_branch_v2_pex_rc.spice
new file mode 100644
index 0000000..c83b08d
--- /dev/null
+++ b/mag/extractions/csvco_branch_v2_pex_rc.spice
@@ -0,0 +1,104 @@
+* NGSPICE file created from csvco_branch_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n207# a_n73_n119# 0.02fF
+C1 a_n33_n207# a_15_n119# 0.02fF
+C2 a_15_n119# a_n73_n119# 0.51fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n334# a_n33_145# 0.05fF
+C1 w_n211_n334# a_15_n186# 0.21fF
+C2 w_n211_n334# a_n73_n186# 0.21fF
+C3 a_15_n186# a_n33_145# 0.01fF
+C4 a_n73_n186# a_n33_145# 0.01fF
+C5 a_n73_n186# a_15_n186# 0.51fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n99# a_n73_n11# 0.02fF
+C1 a_n33_n99# a_15_n11# 0.02fF
+C2 a_15_n11# a_n73_n11# 0.15fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_20_n114# 0.20fF
+C1 w_n216_n334# a_n78_n114# 0.20fF
+C2 a_n78_n114# a_20_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vdd in 0.01fF
+C1 in vss 0.01fF
+C2 vbulkp out 0.08fF
+C3 vbulkp vdd 0.04fF
+C4 out in 0.11fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+
+* Top level circuit csvco_branch_v2
+
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 m1_185_1641# vdd 0.48fF
+C1 out D0 0.09fF
+C2 out inverter_csvco_0/vss 0.03fF
+C3 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C4 in inverter_csvco_0/vss 0.01fF
+C5 out vdd 0.03fF
+C6 out inverter_csvco_0/vdd 0.02fF
+C7 out cap_vco_0/t 0.70fF
+C8 D0 inverter_csvco_0/vss 0.01fF
+C9 inverter_csvco_0/vdd vdd 0.97fF
+C10 out in 0.06fF
+C11 cap_vco_0/t vdd 0.06fF
+C12 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C13 vctrl inverter_csvco_0/vss 0.23fF
+C14 in inverter_csvco_0/vdd 0.01fF
+C15 vdd vss 3.61fF
+C16 out vss 0.94fF
+C17 inverter_csvco_0/vdd vss 0.23fF
+C18 in vss 0.70fF
+C19 inverter_csvco_0/vss vss 0.61fF
+C20 D0 vss -0.68fF
+C21 m1_185_1641# vss -0.03fF
+C22 cap_vco_0/t vss 7.22fF
+C23 vctrl vss 0.44fF
+.end
+
diff --git a/mag/extractions/loop_filter_v2_lvs.spice b/mag/extractions/loop_filter_v2_lvs.spice
new file mode 100644
index 0000000..4f65d5a
--- /dev/null
+++ b/mag/extractions/loop_filter_v2_lvs.spice
@@ -0,0 +1,93 @@
+* NGSPICE file created from loop_filter_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+
+* Top level circuit loop_filter_v2
+
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.end
+
diff --git a/mag/extractions/loop_filter_v2_pex_c.spice b/mag/extractions/loop_filter_v2_pex_c.spice
new file mode 100644
index 0000000..3f1f29b
--- /dev/null
+++ b/mag/extractions/loop_filter_v2_pex_c.spice
@@ -0,0 +1,251 @@
+* NGSPICE file created from loop_filter_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C1 m3_n2650_8000# m3_2669_8000# 2.73fF
+C2 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C3 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C4 m3_2669_n13200# m3_n2650_n13200# 2.73fF
+C5 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C6 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
+C7 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C8 m3_n7969_2700# c1_n13188_n13100# 58.86fF
+C9 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C10 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C11 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C12 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C13 m3_2669_8000# c1_n13188_n13100# 58.61fF
+C14 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C15 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C16 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C17 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C18 m3_2669_2700# m3_2669_n2600# 3.28fF
+C19 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C20 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C21 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C22 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C23 m3_7988_n13200# m3_7988_n7900# 3.39fF
+C24 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C25 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C26 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C27 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C28 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C29 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C30 m3_7988_n2600# m3_7988_2700# 3.39fF
+C31 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C32 m3_2669_2700# m3_2669_8000# 3.28fF
+C33 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C34 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C35 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C36 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C37 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C38 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C39 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C40 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C41 m3_2669_8000# m3_7988_8000# 2.73fF
+C42 m3_2669_2700# m3_7988_2700# 2.73fF
+C43 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C44 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C45 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C46 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C47 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C48 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C49 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C50 m3_7988_n2600# m3_7988_n7900# 3.39fF
+C51 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C52 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C53 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C54 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
+C55 m3_n13288_2700# c1_n13188_n13100# 58.61fF
+C56 m3_7988_8000# m3_7988_2700# 3.39fF
+C57 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C58 m3_2669_n2600# c1_n13188_n13100# 58.86fF
+C59 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C60 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C61 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
+C62 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C63 m3_n2650_n2600# m3_n2650_2700# 3.28fF
+C64 m3_2669_2700# m3_n2650_2700# 2.73fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
+C1 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C2 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C3 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C4 m3_10_n4250# m3_n4309_50# 1.75fF
+C5 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C6 m3_10_n4250# c1_110_n4150# 81.11fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 out in 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C1 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
+C2 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C3 c1_2269_n6300# c1_n2050_n6300# 1.99fF
+C4 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C5 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C6 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C7 m3_n2150_2200# m3_n6469_2200# 1.75fF
+C8 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C9 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C10 c1_n6369_n6300# m3_n6469_2200# 38.10fF
+C11 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C12 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C13 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C14 m3_n2150_2200# m3_n2150_n2100# 2.63fF
+C15 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C16 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C17 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C18 c1_2269_n6300# m3_2169_n6400# 121.67fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 out in 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_n88_n300# a_n118_n388# 0.11fF
+C1 a_30_n300# a_n88_n300# 0.61fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+
+* Top level circuit loop_filter_v2
+
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 cap3_loop_filter_0/in in 0.79fF
+C1 vc_pex in 0.18fF
+C2 in D0_cap 0.07fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.end
+
diff --git a/mag/extractions/loop_filter_v2_pex_rc.spice b/mag/extractions/loop_filter_v2_pex_rc.spice
new file mode 100644
index 0000000..37936db
--- /dev/null
+++ b/mag/extractions/loop_filter_v2_pex_rc.spice
@@ -0,0 +1,251 @@
+* NGSPICE file created from loop_filter_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C1 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C2 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C3 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C4 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C5 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C6 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C7 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C8 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C9 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C10 m3_7988_2700# m3_2669_2700# 2.73fF
+C11 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C12 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C13 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C14 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C15 m3_2669_n2600# m3_2669_2700# 3.28fF
+C16 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C17 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C18 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C19 m3_n13288_2700# c1_n13188_n13100# 58.61fF
+C20 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C21 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C22 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C23 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C24 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C25 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C26 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C27 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C28 m3_2669_n2600# c1_n13188_n13100# 58.86fF
+C29 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C30 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C31 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C32 m3_n2650_8000# m3_2669_8000# 2.73fF
+C33 m3_7988_n2600# m3_7988_n7900# 3.39fF
+C34 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C35 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C36 m3_2669_8000# m3_7988_8000# 2.73fF
+C37 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C38 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C39 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C40 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C41 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C42 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C43 m3_n7969_2700# m3_n7969_n2600# 3.28fF
+C44 m3_7988_2700# m3_7988_n2600# 3.39fF
+C45 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C46 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C47 m3_2669_n2600# m3_n2650_n2600# 2.73fF
+C48 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
+C49 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C50 m3_7988_2700# m3_7988_8000# 3.39fF
+C51 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C52 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C53 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C54 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C55 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C56 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C57 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C58 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C59 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C60 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C61 m3_n2650_2700# m3_2669_2700# 2.73fF
+C62 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C63 m3_2669_8000# m3_2669_2700# 3.28fF
+C64 m3_7988_n13200# m3_7988_n7900# 3.39fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C1 m3_10_n4250# m3_n4309_50# 1.75fF
+C2 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C3 c1_n4209_n4150# m3_n4309_50# 38.10fF
+C4 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C5 c1_110_n4150# m3_10_n4250# 81.11fF
+C6 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 in out 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C1 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C2 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C3 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C4 c1_n6369_n6300# m3_n6469_2200# 38.10fF
+C5 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C6 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C7 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C8 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C9 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C10 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C11 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C12 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C13 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C14 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C15 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C16 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C17 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C18 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_n88_n300# a_30_n300# 0.61fF
+C1 a_n88_n300# a_n118_n388# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+
+* Top level circuit loop_filter_v2
+
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 vc_pex in 0.18fF
+C1 cap3_loop_filter_0/in in 0.79fF
+C2 D0_cap in 0.07fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.end
+
diff --git a/mag/extractions/lvs b/mag/extractions/lvs
new file mode 100644
index 0000000..7a5e6d8
--- /dev/null
+++ b/mag/extractions/lvs
@@ -0,0 +1,78 @@
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_AQR2CW in circuit inverter_csvco (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_HRYSXS in circuit inverter_csvco (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_CBSTVW in circuit csvco_branch_v2 (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_MJP3BN in circuit csvco_branch_v2 (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_EDT3AT in circuit csvco_branch_v2 (0)(1 instance)
+Flattening unmatched subcell cap_vco in circuit csvco_branch_v2 (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_CBAU6Y in circuit mag/extractions/ring_osc_v2_lvs.spice (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_4757AC in circuit mag/extractions/ring_osc_v2_lvs.spice (0)(1 instance)
+Equate elements: no current cell.
+Equate elements: no current cell.
+
+Subcircuit summary:
+Circuit 1: inverter_csvco |Circuit 2: inverter_csvco
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+sky130_fd_pr__pfet_01v8 (1) |sky130_fd_pr__pfet_01v8 (1)
+Number of devices: 2 |Number of devices: 2
+Number of nets: 6 |Number of nets: 6
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: inverter_csvco |Circuit 2: inverter_csvco
+-------------------------------------------|-------------------------------------------
+vss |vss
+vbulkn |vbulkn
+vdd |vdd
+vbulkp |vbulkp
+out |out
+in |in
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes inverter_csvco and inverter_csvco are equivalent.
+
+Subcircuit summary:
+Circuit 1: csvco_branch_v2 |Circuit 2: csvco_branch_v2
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
+sky130_fd_pr__pfet_01v8 (1) |sky130_fd_pr__pfet_01v8 (1)
+inverter_csvco (1) |inverter_csvco (1)
+c (1) |c (1)
+Number of devices: 5 |Number of devices: 5
+Number of nets: 10 |Number of nets: 10
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: csvco_branch_v2 |Circuit 2: csvco_branch_v2
+-------------------------------------------|-------------------------------------------
+vdd |vdd
+vss |vss
+m1_185_1641# |vbp **Mismatch**
+vctrl |vctrl
+D0 |D0
+in |in
+out |out
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes csvco_branch_v2 and csvco_branch_v2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: mag/extractions/ring_osc_v2_lvs |Circuit 2: xschem/simulations/csvco_v2.spi
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
+csvco_branch_v2 (3) |csvco_branch_v2 (3)
+sky130_fd_pr__pfet_01v8 (1) |sky130_fd_pr__pfet_01v8 (1)
+Number of devices: 5 |Number of devices: 5
+Number of nets: 8 |Number of nets: 8
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match with 2 symmetries.
+Circuits match correctly.
+Cells have no pins; pin matching not needed.
+Device classes mag/extractions/ring_osc_v2_lvs.spice and xschem/simulations/csvco_v2.spice are equivalent.
+Circuits match uniquely.
diff --git a/mag/extractions/ring_osc_v2_lvs.spice b/mag/extractions/ring_osc_v2_lvs.spice
new file mode 100644
index 0000000..43179a3
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_lvs.spice
@@ -0,0 +1,62 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+*C1 t VSUBS 0.42fF
+*C2 b VSUBS 0.09fF
+.ends
+
+
+.subckt csvco_branch_v2 vctrl in D0 out m1_185_1641# vss vdd
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+
+* Top level circuit ring_osc_v2
+
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in D0 csvco_branch_v2_2/in vbp vss vdd
++ csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco D0 csvco_branch_v2_1/in vbp vss vdd csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in D0 out_vco vbp vss vdd csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+.end
+
diff --git a/mag/extractions/ring_osc_v2_lvs_port.spice b/mag/extractions/ring_osc_v2_lvs_port.spice
new file mode 100644
index 0000000..7ae1803
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_lvs_port.spice
@@ -0,0 +1,52 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt csvco_branch_v2 vctrl in D0 out m1_185_1641# vss vdd
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt ring_osc_v2 vss vdd out_vco D0 vctrl vbp
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in D0 csvco_branch_v2_2/in vbp vss vdd
++ csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco D0 csvco_branch_v2_1/in vbp vss vdd csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in D0 out_vco vbp vss vdd csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+.ends
+
diff --git a/mag/extractions/ring_osc_v2_pex_c.spice b/mag/extractions/ring_osc_v2_pex_c.spice
new file mode 100644
index 0000000..a29f6f9
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_pex_c.spice
@@ -0,0 +1,169 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_15_n150# 0.51fF
+C1 a_n33_n238# a_15_n150# 0.02fF
+C2 a_n33_n238# a_n73_n150# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n119# a_15_n119# 0.51fF
+C1 a_n33_n207# a_15_n119# 0.02fF
+C2 a_n33_n207# a_n73_n119# 0.02fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_145# a_n73_n186# 0.01fF
+C1 w_n211_n334# a_n73_n186# 0.21fF
+C2 w_n211_n334# a_n33_145# 0.05fF
+C3 a_15_n186# a_n73_n186# 0.51fF
+C4 a_n33_145# a_15_n186# 0.01fF
+C5 w_n211_n334# a_15_n186# 0.21fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_15_n11# 0.15fF
+C1 a_n33_n99# a_15_n11# 0.02fF
+C2 a_n33_n99# a_n73_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_n78_n114# 0.20fF
+C1 a_20_n114# a_n78_n114# 0.42fF
+C2 w_n216_n334# a_20_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vss in 0.01fF
+C1 in vdd 0.01fF
+C2 in out 0.11fF
+C3 vdd vbulkp 0.04fF
+C4 vbulkp out 0.08fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch_v2 vctrl in cap_vco_0/t D0 out m1_185_1641# vss vdd inverter_csvco_0/vss
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 cap_vco_0/t vctrl 0.03fF
+C1 inverter_csvco_0/vss in 0.01fF
+C2 inverter_csvco_0/vss vctrl 0.23fF
+C3 vdd out 0.03fF
+C4 in inverter_csvco_0/vdd 0.01fF
+C5 out D0 0.09fF
+C6 cap_vco_0/t out 0.11fF
+C7 inverter_csvco_0/vss out 0.03fF
+C8 in out 0.06fF
+C9 inverter_csvco_0/vdd out 0.02fF
+C10 vdd m1_185_1641# 0.48fF
+C11 vdd inverter_csvco_0/vdd 0.97fF
+C12 cap_vco_0/t D0 0.18fF
+C13 m1_185_1641# inverter_csvco_0/vdd 0.13fF
+C14 inverter_csvco_0/vss D0 0.01fF
+C15 inverter_csvco_0/vss cap_vco_0/t 0.12fF
+C16 vdd vss 3.58fF
+C17 out vss 0.87fF
+C18 inverter_csvco_0/vdd vss 0.14fF
+C19 in vss 0.70fF
+C20 inverter_csvco_0/vss vss 0.72fF
+C21 D0 vss -0.49fF
+C22 m1_185_1641# vss -0.03fF
+C23 cap_vco_0/t vss 8.30fF
+C24 vctrl vss 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n369# a_n33_181# 0.05fF
+C1 a_n33_181# a_n73_n150# 0.01fF
+C2 w_n211_n369# a_n73_n150# 0.20fF
+C3 a_n33_181# a_15_n150# 0.01fF
+C4 w_n211_n369# a_15_n150# 0.20fF
+C5 a_15_n150# a_n73_n150# 0.51fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+
+* Top level circuit ring_osc_v2
+
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in csvco_branch_v2_1/cap_vco_0/t D0 csvco_branch_v2_2/in
++ vbp vss vdd csvco_branch_v2_1/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco csvco_branch_v2_0/cap_vco_0/t D0 csvco_branch_v2_1/in
++ vbp vss vdd csvco_branch_v2_0/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in csvco_branch_v2_2/cap_vco_0/t D0 out_vco
++ vbp vss vdd csvco_branch_v2_2/inverter_csvco_0/vss csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+C0 csvco_branch_v2_2/inverter_csvco_0/vss D0 0.04fF
+C1 csvco_branch_v2_1/in out_vco 0.76fF
+C2 csvco_branch_v2_1/cap_vco_0/t vctrl 0.24fF
+C3 D0 csvco_branch_v2_2/cap_vco_0/t 1.03fF
+C4 out_vco csvco_branch_v2_2/in 0.59fF
+C5 csvco_branch_v2_1/cap_vco_0/t D0 0.12fF
+C6 vbp vctrl 0.06fF
+C7 csvco_branch_v2_0/cap_vco_0/t vctrl 0.24fF
+C8 D0 csvco_branch_v2_1/inverter_csvco_0/vss 0.04fF
+C9 csvco_branch_v2_0/cap_vco_0/t D0 0.12fF
+C10 vbp vdd 3.04fF
+C11 csvco_branch_v2_1/in vdd 0.01fF
+C12 vdd csvco_branch_v2_2/in 0.01fF
+C13 vdd vss 14.19fF
+C14 csvco_branch_v2_2/inverter_csvco_0/vdd vss 0.14fF
+C15 csvco_branch_v2_2/inverter_csvco_0/vss vss 0.44fF
+C16 csvco_branch_v2_2/cap_vco_0/t vss 7.06fF
+C17 csvco_branch_v2_1/in vss 1.66fF
+C18 csvco_branch_v2_0/inverter_csvco_0/vdd vss 0.14fF
+C19 out_vco vss 0.49fF
+C20 csvco_branch_v2_0/inverter_csvco_0/vss vss 0.44fF
+C21 D0 vss -1.46fF
+C22 vbp vss -0.38fF
+C23 csvco_branch_v2_0/cap_vco_0/t vss 7.07fF
+C24 vctrl vss 5.55fF
+C25 csvco_branch_v2_2/in vss 1.67fF
+C26 csvco_branch_v2_1/inverter_csvco_0/vdd vss 0.14fF
+C27 csvco_branch_v2_1/inverter_csvco_0/vss vss 0.44fF
+C28 csvco_branch_v2_1/cap_vco_0/t vss 7.07fF
+.end
+
diff --git a/mag/extractions/ring_osc_v2_pex_c_port.spice b/mag/extractions/ring_osc_v2_pex_c_port.spice
new file mode 100644
index 0000000..e943714
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_pex_c_port.spice
@@ -0,0 +1,174 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n73_n150# 0.51fF
+C1 a_15_n150# a_n33_n238# 0.02fF
+C2 a_n33_n238# a_n73_n150# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n119# a_n73_n119# 0.51fF
+C1 a_15_n119# a_n33_n207# 0.02fF
+C2 a_n33_n207# a_n73_n119# 0.02fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n186# w_n211_n334# 0.21fF
+C1 a_n73_n186# a_n33_145# 0.01fF
+C2 a_n73_n186# w_n211_n334# 0.21fF
+C3 a_15_n186# a_n73_n186# 0.51fF
+C4 w_n211_n334# a_n33_145# 0.05fF
+C5 a_15_n186# a_n33_145# 0.01fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n73_n11# 0.15fF
+C1 a_15_n11# a_n33_n99# 0.02fF
+C2 a_n33_n99# a_n73_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_20_n114# w_n216_n334# 0.20fF
+C1 a_n78_n114# w_n216_n334# 0.20fF
+C2 a_20_n114# a_n78_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 out vbulkp 0.08fF
+C1 out in 0.11fF
+C2 vdd vbulkp 0.04fF
+C3 in vss 0.01fF
+C4 in vdd 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch_v2 vctrl in cap_vco_0/t D0 out m1_185_1641# vss vdd inverter_csvco_0/vss
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 vdd out 0.03fF
+C1 out inverter_csvco_0/vdd 0.02fF
+C2 vctrl cap_vco_0/t 0.03fF
+C3 D0 cap_vco_0/t 0.18fF
+C4 vdd m1_185_1641# 0.48fF
+C5 inverter_csvco_0/vss vctrl 0.23fF
+C6 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C7 inverter_csvco_0/vss cap_vco_0/t 0.12fF
+C8 D0 inverter_csvco_0/vss 0.01fF
+C9 in inverter_csvco_0/vss 0.01fF
+C10 in inverter_csvco_0/vdd 0.01fF
+C11 out cap_vco_0/t 0.11fF
+C12 D0 out 0.09fF
+C13 out in 0.06fF
+C14 vdd inverter_csvco_0/vdd 0.97fF
+C15 out inverter_csvco_0/vss 0.03fF
+C16 vdd vss 3.58fF
+C17 out vss 0.87fF
+C18 inverter_csvco_0/vdd vss 0.14fF
+C19 in vss 0.70fF
+C20 inverter_csvco_0/vss vss 0.72fF
+C21 D0 vss -0.49fF
+C22 m1_185_1641# vss -0.03fF
+C23 cap_vco_0/t vss 8.30fF
+C24 vctrl vss 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_15_n150# 0.51fF
+C1 a_15_n150# a_n33_181# 0.01fF
+C2 w_n211_n369# a_15_n150# 0.20fF
+C3 a_n73_n150# a_n33_181# 0.01fF
+C4 w_n211_n369# a_n73_n150# 0.20fF
+C5 w_n211_n369# a_n33_181# 0.05fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt csvco_v2_pex_c vdd out_vco D0 vctrl vss vbp
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in csvco_branch_v2_1/cap_vco_0/t D0 csvco_branch_v2_2/in
++ vbp vss vdd csvco_branch_v2_1/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco csvco_branch_v2_0/cap_vco_0/t D0 csvco_branch_v2_1/in
++ vbp vss vdd csvco_branch_v2_0/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in csvco_branch_v2_2/cap_vco_0/t D0 out_vco
++ vbp vss vdd csvco_branch_v2_2/inverter_csvco_0/vss csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+C0 csvco_branch_v2_0/cap_vco_0/t vctrl 0.24fF
+C1 csvco_branch_v2_1/in out_vco 0.76fF
+C2 csvco_branch_v2_1/inverter_csvco_0/vss D0 0.04fF
+C3 csvco_branch_v2_0/cap_vco_0/t D0 0.12fF
+C4 csvco_branch_v2_2/in vdd 0.01fF
+C5 vbp vdd 3.04fF
+C6 vctrl vbp 0.06fF
+C7 vctrl csvco_branch_v2_1/cap_vco_0/t 0.24fF
+C8 csvco_branch_v2_2/in out_vco 0.59fF
+C9 D0 csvco_branch_v2_2/inverter_csvco_0/vss 0.04fF
+C10 D0 csvco_branch_v2_2/cap_vco_0/t 1.03fF
+C11 csvco_branch_v2_1/in vdd 0.01fF
+C12 D0 csvco_branch_v2_1/cap_vco_0/t 0.12fF
+C13 vdd vss 14.19fF
+C14 csvco_branch_v2_2/inverter_csvco_0/vdd vss 0.14fF
+C15 csvco_branch_v2_2/inverter_csvco_0/vss vss 0.44fF
+C16 csvco_branch_v2_2/cap_vco_0/t vss 7.06fF
+C17 csvco_branch_v2_1/in vss 1.66fF
+C18 csvco_branch_v2_0/inverter_csvco_0/vdd vss 0.14fF
+C19 out_vco vss 0.49fF
+C20 csvco_branch_v2_0/inverter_csvco_0/vss vss 0.44fF
+C21 D0 vss -1.24fF
+C22 vbp vss -0.38fF
+C23 csvco_branch_v2_0/cap_vco_0/t vss 7.07fF
+C24 vctrl vss 5.55fF
+C25 csvco_branch_v2_2/in vss 1.67fF
+C26 csvco_branch_v2_1/inverter_csvco_0/vdd vss 0.14fF
+C27 csvco_branch_v2_1/inverter_csvco_0/vss vss 0.44fF
+C28 csvco_branch_v2_1/cap_vco_0/t vss 7.07fF
+.ends
+
diff --git a/mag/extractions/ring_osc_v2_pex_rc.spice b/mag/extractions/ring_osc_v2_pex_rc.spice
new file mode 100644
index 0000000..ef45b0a
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_pex_rc.spice
@@ -0,0 +1,169 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_n33_n238# 0.02fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 a_15_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n119# a_n33_n207# 0.02fF
+C1 a_15_n119# a_n73_n119# 0.51fF
+C2 a_15_n119# a_n33_n207# 0.02fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_145# w_n211_n334# 0.05fF
+C1 a_15_n186# a_n73_n186# 0.51fF
+C2 a_n73_n186# a_n33_145# 0.01fF
+C3 a_15_n186# a_n33_145# 0.01fF
+C4 a_n73_n186# w_n211_n334# 0.21fF
+C5 a_15_n186# w_n211_n334# 0.21fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_n33_n99# 0.02fF
+C1 a_15_n11# a_n73_n11# 0.15fF
+C2 a_15_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_20_n114# a_n78_n114# 0.42fF
+C1 a_n78_n114# w_n216_n334# 0.20fF
+C2 a_20_n114# w_n216_n334# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vdd 0.01fF
+C1 out vbulkp 0.08fF
+C2 in out 0.11fF
+C3 vdd vbulkp 0.04fF
+C4 in vss 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch_v2 vctrl in cap_vco_0/t D0 out m1_185_1641# vss vdd inverter_csvco_0/vss
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 out in 0.06fF
+C1 out inverter_csvco_0/vss 0.03fF
+C2 vctrl cap_vco_0/t 0.03fF
+C3 vdd inverter_csvco_0/vdd 0.97fF
+C4 out inverter_csvco_0/vdd 0.02fF
+C5 out D0 0.09fF
+C6 vdd out 0.03fF
+C7 vctrl inverter_csvco_0/vss 0.23fF
+C8 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C9 vdd m1_185_1641# 0.48fF
+C10 inverter_csvco_0/vss cap_vco_0/t 0.12fF
+C11 in inverter_csvco_0/vss 0.01fF
+C12 D0 cap_vco_0/t 0.18fF
+C13 out cap_vco_0/t 0.11fF
+C14 inverter_csvco_0/vdd in 0.01fF
+C15 D0 inverter_csvco_0/vss 0.01fF
+C16 vdd vss 3.58fF
+C17 out vss 0.87fF
+C18 inverter_csvco_0/vdd vss 0.14fF
+C19 in vss 0.70fF
+C20 inverter_csvco_0/vss vss 0.72fF
+C21 D0 vss -0.49fF
+C22 m1_185_1641# vss -0.03fF
+C23 cap_vco_0/t vss 8.30fF
+C24 vctrl vss 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_181# w_n211_n369# 0.05fF
+C1 a_n73_n150# w_n211_n369# 0.20fF
+C2 a_15_n150# w_n211_n369# 0.20fF
+C3 a_n73_n150# a_n33_181# 0.01fF
+C4 a_n33_181# a_15_n150# 0.01fF
+C5 a_n73_n150# a_15_n150# 0.51fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+
+* Top level circuit ring_osc_v2
+
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in csvco_branch_v2_1/cap_vco_0/t D0 csvco_branch_v2_2/in
++ vbp vss vdd csvco_branch_v2_1/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco csvco_branch_v2_0/cap_vco_0/t D0 csvco_branch_v2_1/in
++ vbp vss vdd csvco_branch_v2_0/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in csvco_branch_v2_2/cap_vco_0/t D0 out_vco
++ vbp vss vdd csvco_branch_v2_2/inverter_csvco_0/vss csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+C0 csvco_branch_v2_1/in vdd 0.01fF
+C1 csvco_branch_v2_1/in out_vco 0.76fF
+C2 vctrl csvco_branch_v2_0/cap_vco_0/t 0.24fF
+C3 vctrl csvco_branch_v2_1/cap_vco_0/t 0.24fF
+C4 csvco_branch_v2_2/in vdd 0.01fF
+C5 csvco_branch_v2_2/in out_vco 0.59fF
+C6 D0 csvco_branch_v2_0/cap_vco_0/t 0.12fF
+C7 vdd vbp 3.04fF
+C8 D0 csvco_branch_v2_1/cap_vco_0/t 0.12fF
+C9 D0 csvco_branch_v2_2/cap_vco_0/t 1.03fF
+C10 D0 csvco_branch_v2_2/inverter_csvco_0/vss 0.04fF
+C11 D0 csvco_branch_v2_1/inverter_csvco_0/vss 0.04fF
+C12 vctrl vbp 0.06fF
+C13 vdd vss 14.19fF
+C14 csvco_branch_v2_2/inverter_csvco_0/vdd vss 0.14fF
+C15 csvco_branch_v2_2/inverter_csvco_0/vss vss 0.44fF
+C16 csvco_branch_v2_2/cap_vco_0/t vss 7.06fF
+C17 csvco_branch_v2_1/in vss 1.66fF
+C18 csvco_branch_v2_0/inverter_csvco_0/vdd vss 0.14fF
+C19 out_vco vss 0.49fF
+C20 csvco_branch_v2_0/inverter_csvco_0/vss vss 0.44fF
+C21 D0 vss -1.46fF
+C22 vbp vss -0.38fF
+C23 csvco_branch_v2_0/cap_vco_0/t vss 7.07fF
+C24 vctrl vss 5.55fF
+C25 csvco_branch_v2_2/in vss 1.67fF
+C26 csvco_branch_v2_1/inverter_csvco_0/vdd vss 0.14fF
+C27 csvco_branch_v2_1/inverter_csvco_0/vss vss 0.44fF
+C28 csvco_branch_v2_1/cap_vco_0/t vss 7.07fF
+.end
+
diff --git a/mag/extractions/ring_osc_v2_pex_rc_port.spice b/mag/extractions/ring_osc_v2_pex_rc_port.spice
new file mode 100644
index 0000000..2af6754
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_pex_rc_port.spice
@@ -0,0 +1,167 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_n33_n238# 0.02fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 a_15_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n119# a_n33_n207# 0.02fF
+C1 a_15_n119# a_n73_n119# 0.51fF
+C2 a_15_n119# a_n33_n207# 0.02fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_145# w_n211_n334# 0.05fF
+C1 a_n73_n186# a_n33_145# 0.01fF
+C2 a_15_n186# a_n33_145# 0.01fF
+C3 a_n73_n186# w_n211_n334# 0.21fF
+C4 a_15_n186# w_n211_n334# 0.21fF
+C5 a_15_n186# a_n73_n186# 0.51fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_n33_n99# 0.02fF
+C1 a_15_n11# a_n73_n11# 0.15fF
+C2 a_15_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# w_n216_n334# 0.20fF
+C1 a_20_n114# w_n216_n334# 0.20fF
+C2 a_20_n114# a_n78_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 out in 0.11fF
+C1 vbulkp out 0.08fF
+C2 vdd in 0.01fF
+C3 vss in 0.01fF
+C4 vbulkp vdd 0.04fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch_v2 vctrl in cap_vco_0/t D0 out m1_185_1641# vss vdd inverter_csvco_0/vss
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 out in 0.06fF
+C1 vctrl cap_vco_0/t 0.03fF
+C2 out inverter_csvco_0/vss 0.03fF
+C3 out inverter_csvco_0/vdd 0.02fF
+C4 vdd m1_185_1641# 0.48fF
+C5 inverter_csvco_0/vss cap_vco_0/t 0.12fF
+C6 vdd inverter_csvco_0/vdd 0.97fF
+C7 D0 inverter_csvco_0/vss 0.01fF
+C8 out cap_vco_0/t 0.11fF
+C9 vdd out 0.03fF
+C10 out D0 0.09fF
+C11 inverter_csvco_0/vss vctrl 0.23fF
+C12 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C13 in inverter_csvco_0/vss 0.01fF
+C14 inverter_csvco_0/vdd in 0.01fF
+C15 D0 cap_vco_0/t 0.18fF
+C16 vdd vss 3.58fF
+C17 out vss 0.87fF
+C18 inverter_csvco_0/vdd vss 0.14fF
+C19 in vss 0.70fF
+C20 inverter_csvco_0/vss vss 0.72fF
+C21 D0 vss -0.49fF
+C22 m1_185_1641# vss -0.03fF
+C23 cap_vco_0/t vss 8.30fF
+C24 vctrl vss 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n369# a_n73_n150# 0.20fF
+C1 w_n211_n369# a_n33_181# 0.05fF
+C2 a_n73_n150# a_n33_181# 0.01fF
+C3 w_n211_n369# a_15_n150# 0.20fF
+C4 a_n73_n150# a_15_n150# 0.51fF
+C5 a_n33_181# a_15_n150# 0.01fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt ring_osc_v2 vss vdd out_vco D0 vctrl vbp
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in csvco_branch_v2_1/cap_vco_0/t D0 csvco_branch_v2_2/in
++ vbp vss vdd csvco_branch_v2_1/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco csvco_branch_v2_0/cap_vco_0/t D0 csvco_branch_v2_1/in
++ vbp vss vdd csvco_branch_v2_0/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in csvco_branch_v2_2/cap_vco_0/t D0 out_vco
++ vbp vss vdd csvco_branch_v2_2/inverter_csvco_0/vss csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+C0 vctrl vbp 0.06fF
+C1 csvco_branch_v2_1/in vdd 0.01fF
+C2 csvco_branch_v2_1/in out_vco 0.76fF
+C3 vctrl csvco_branch_v2_0/cap_vco_0/t 0.24fF
+C4 csvco_branch_v2_2/in vdd 0.01fF
+C5 csvco_branch_v2_1/cap_vco_0/t vctrl 0.24fF
+C6 csvco_branch_v2_2/in out_vco 0.59fF
+C7 D0 csvco_branch_v2_0/cap_vco_0/t 0.12fF
+C8 vdd vbp 3.04fF
+C9 csvco_branch_v2_1/cap_vco_0/t D0 0.12fF
+C10 D0 csvco_branch_v2_2/cap_vco_0/t 1.03fF
+C11 D0 csvco_branch_v2_2/inverter_csvco_0/vss 0.04fF
+C12 D0 csvco_branch_v2_1/inverter_csvco_0/vss 0.04fF
+C13 vdd vss 14.19fF
+C14 csvco_branch_v2_2/inverter_csvco_0/vdd vss 0.14fF
+C15 csvco_branch_v2_2/inverter_csvco_0/vss vss 0.44fF
+C16 csvco_branch_v2_2/cap_vco_0/t vss 7.06fF
+C17 csvco_branch_v2_1/in vss 1.66fF
+C18 csvco_branch_v2_0/inverter_csvco_0/vdd vss 0.14fF
+C19 out_vco vss 0.49fF
+C20 csvco_branch_v2_0/inverter_csvco_0/vss vss 0.44fF
+C21 D0 vss -1.24fF
+C22 vbp vss -0.38fF
+C23 csvco_branch_v2_0/cap_vco_0/t vss 7.07fF
+C24 vctrl vss 5.55fF
+C25 csvco_branch_v2_2/in vss 1.67fF
+C26 csvco_branch_v2_1/inverter_csvco_0/vdd vss 0.14fF
+C27 csvco_branch_v2_1/inverter_csvco_0/vss vss 0.44fF
+C28 csvco_branch_v2_1/cap_vco_0/t vss 7.07fF
+.ends
+
diff --git a/mag/extractions/top_pll_v1_lvs.spice b/mag/extractions/top_pll_v1_lvs.spice
new file mode 100644
index 0000000..a2768de
--- /dev/null
+++ b/mag/extractions/top_pll_v1_lvs.spice
@@ -0,0 +1,783 @@
+* NGSPICE file created from top_pll_v1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt charge_pump Down out iref pswitch nDown biasp Up nswitch vss vdd nUp
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x1 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+.ends
+
+.subckt clock_inverter vss CLK vdd CLK_d nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt latch_diff nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+.ends
+
+.subckt DFlipFlop vss nQ Q vdd CLK nCLK D
+Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
++ latch_diff
+Xlatch_diff_1 nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D latch_diff
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+.ends
+
+.subckt div_by_2 vss vdd CLK_2 nCLK_2 o1 CLK out_div o2 nout_div
+XDFlipFlop_0 vss nout_div out_div vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK nout_div DFlipFlop
+Xclock_inverter_0 vss CLK vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+.ends
+
+.subckt buffer_salida in out vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+*C1 t VSUBS 0.42fF
+*C2 b VSUBS 0.09fF
+.ends
+
+
+.subckt csvco_branch vctrl in vbp D0 out vss vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+.ends
+
+.subckt ring_osc vctrl vdd vss D0 out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp D0 csvco_branch_1/in vss vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp D0 out_vco vss vdd csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp D0 csvco_branch_2/in vss
++ vdd csvco_branch
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt div_by_5 nCLK vdd Q0 CLK nQ0 CLK_5 nQ2 vss Q1 Q1_shift
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 vss nQ2 DFlipFlop_0/Q vdd CLK nCLK DFlipFlop_0/D DFlipFlop
+XDFlipFlop_1 vss nQ0 Q0 vdd CLK nCLK DFlipFlop_1/D DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ Q1 vdd CLK nCLK DFlipFlop_2/D DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ Q1_shift vdd nCLK CLK Q1 DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+.ends
+
+.subckt pfd_cp_interface vss vdd Down QA QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 QB vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
+Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS w_n359_n309# a_n63_n116# a_n159_n207#
++ a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt nor_pfd out vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss vdd B A out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+.ends
+
+.subckt dff_pfd vss vdd Q CLK Reset
+Xnor_pfd_0 nor_pfd_2/A vss vdd CLK Q nor_pfd
+Xnor_pfd_1 Q vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_3/A vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_2/B vss vdd nor_pfd_3/A Reset nor_pfd
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt and_pfd vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd Up A Reset dff_pfd
+Xdff_pfd_1 vss vdd Down B Reset dff_pfd
+Xand_pfd_0 vss Reset vdd Up Down and_pfd
+.ends
+
+
+* Top level circuit top_pll_v1
+
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
+Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss vco_D0 vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 n_out_by_2 vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2 vss
++ div_5_Q1 div_5_Q1_shift div_by_5
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+.end
+
diff --git a/mag/extractions/top_pll_v1_lvs_port.spice b/mag/extractions/top_pll_v1_lvs_port.spice
new file mode 100644
index 0000000..302fddc
--- /dev/null
+++ b/mag/extractions/top_pll_v1_lvs_port.spice
@@ -0,0 +1,776 @@
+* NGSPICE file created from top_pll_v1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt charge_pump Down out iref pswitch nDown biasp Up nswitch vss vdd nUp
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x1 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+.ends
+
+.subckt clock_inverter vss CLK vdd CLK_d nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt latch_diff nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+.ends
+
+.subckt DFlipFlop vss nQ Q vdd CLK nCLK D
+Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
++ latch_diff
+Xlatch_diff_1 nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D latch_diff
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+.ends
+
+.subckt div_by_2 vss vdd CLK_2 nCLK_2 o1 CLK out_div o2 nout_div
+XDFlipFlop_0 vss nout_div out_div vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK nout_div DFlipFlop
+Xclock_inverter_0 vss CLK vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+.ends
+
+.subckt buffer_salida in out vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt csvco_branch vctrl in vbp D0 out vss vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+.ends
+
+.subckt ring_osc vctrl vdd vss D0 out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp D0 csvco_branch_1/in vss vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp D0 out_vco vss vdd csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp D0 csvco_branch_2/in vss
++ vdd csvco_branch
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt div_by_5 nCLK vdd Q0 CLK nQ0 CLK_5 nQ2 vss Q1 Q1_shift
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 vss nQ2 DFlipFlop_0/Q vdd CLK nCLK DFlipFlop_0/D DFlipFlop
+XDFlipFlop_1 vss nQ0 Q0 vdd CLK nCLK DFlipFlop_1/D DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ Q1 vdd CLK nCLK DFlipFlop_2/D DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ Q1_shift vdd nCLK CLK Q1 DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+.ends
+
+.subckt pfd_cp_interface vss vdd Down QA QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 QB vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
+Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS w_n359_n309# a_n63_n116# a_n159_n207#
++ a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt nor_pfd out vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss vdd B A out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+.ends
+
+.subckt dff_pfd vss vdd Q CLK Reset
+Xnor_pfd_0 nor_pfd_2/A vss vdd CLK Q nor_pfd
+Xnor_pfd_1 Q vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_3/A vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_2/B vss vdd nor_pfd_3/A Reset nor_pfd
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt and_pfd vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd Up A Reset dff_pfd
+Xdff_pfd_1 vss vdd Down B Reset dff_pfd
+Xand_pfd_0 vss Reset vdd Up Down and_pfd
+.ends
+
+.subckt top_pll_v1 pfd_reset in_ref QA QB Down nDown Up nUp biasp pswitch nswitch
++ vco_vctrl vco_D0 vco_out out_first_buffer out_to_div out_div_2 n_out_div_2 n_out_buffer_div_2
++ out_buffer_div_2 out_by_2 n_out_by_2 div_5_Q1_shift out_div_by_5 div_5_Q1 div_5_Q0
++ div_5_nQ0 div_5_nQ2 iref_cp vdd vss lf_vc
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
+Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss vco_D0 vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 n_out_by_2 vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2 vss
++ div_5_Q1 div_5_Q1_shift div_by_5
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+.ends
+
diff --git a/mag/extractions/top_pll_v1_pex_c.spice b/mag/extractions/top_pll_v1_pex_c.spice
new file mode 100644
index 0000000..55c72a5
--- /dev/null
+++ b/mag/extractions/top_pll_v1_pex_c.spice
@@ -0,0 +1,2875 @@
+* NGSPICE file created from top_pll_v1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C1 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C2 m3_7988_2700# m3_7988_8000# 3.39fF
+C3 m3_2669_n2600# m3_n2650_n2600# 2.73fF
+C4 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C5 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C6 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C7 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C8 m3_2669_8000# m3_n2650_8000# 2.73fF
+C9 m3_n7969_2700# m3_n7969_n2600# 3.28fF
+C10 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C11 m3_2669_n2600# m3_2669_2700# 3.28fF
+C12 m3_7988_n2600# m3_7988_2700# 3.39fF
+C13 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C14 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C15 m3_7988_n2600# m3_7988_n7900# 3.39fF
+C16 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C17 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C18 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C19 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C20 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C21 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C22 m3_n7969_2700# m3_n7969_8000# 3.28fF
+C23 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
+C24 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C25 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C26 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C27 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C28 m3_n7969_2700# c1_n13188_n13100# 58.86fF
+C29 m3_2669_2700# m3_2669_8000# 3.28fF
+C30 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C31 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C32 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C33 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C34 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C35 m3_2669_8000# m3_7988_8000# 2.73fF
+C36 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C37 m3_n2650_n2600# m3_n7969_n2600# 2.73fF
+C38 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C39 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C40 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C41 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C42 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C43 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C44 m3_2669_n2600# c1_n13188_n13100# 58.86fF
+C45 m3_7988_n13200# m3_7988_n7900# 3.39fF
+C46 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C47 m3_n2650_2700# m3_2669_2700# 2.73fF
+C48 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C49 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C50 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C51 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C52 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C53 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C54 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C55 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C56 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C57 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C58 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C59 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C60 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C61 m3_2669_2700# m3_7988_2700# 2.73fF
+C62 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C63 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C64 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C1 c1_2269_n6300# m3_2169_n6400# 121.67fF
+C2 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C3 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C4 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C5 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C6 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C7 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C8 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C9 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C10 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C11 c1_2269_n6300# c1_n2050_n6300# 1.99fF
+C12 c1_n6369_n6300# m3_n6469_2200# 38.10fF
+C13 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C14 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C15 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C16 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C17 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C18 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 vc_pex vss -38.13fF
+C2 res_loop_filter_2/out vss 8.49fF
+C3 in vss -18.79fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 w_n2457_n634# a_1803_n486# 0.02fF
+C1 w_n2457_n634# a_2261_n486# 0.02fF
+C2 a_n945_n486# w_n2457_n634# 0.02fF
+C3 w_n2457_n634# a_n1861_n486# 0.02fF
+C4 w_n2457_n634# a_1345_n486# 0.02fF
+C5 w_n2457_n634# a_429_n486# 0.02fF
+C6 a_n2319_n486# w_n2457_n634# 0.02fF
+C7 w_n2457_n634# a_n1403_n486# 0.02fF
+C8 w_n2457_n634# a_n29_n486# 0.02fF
+C9 w_n2457_n634# a_n487_n486# 0.02fF
+C10 w_n2457_n634# a_887_n486# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n1041_n75# a_n657_n75# 0.03fF
+C1 a_687_n75# a_591_n75# 0.22fF
+C2 a_15_n75# a_111_n75# 0.22fF
+C3 a_n945_n75# a_n1137_n75# 0.08fF
+C4 a_n753_n75# a_n657_n75# 0.22fF
+C5 a_687_n75# a_879_n75# 0.08fF
+C6 a_687_n75# a_399_n75# 0.05fF
+C7 a_879_n75# a_1071_n75# 0.08fF
+C8 a_n465_n75# a_n273_n75# 0.08fF
+C9 a_303_n75# a_495_n75# 0.08fF
+C10 a_n561_n75# a_n177_n75# 0.03fF
+C11 a_n81_n75# a_303_n75# 0.03fF
+C12 a_1167_n75# a_879_n75# 0.05fF
+C13 a_975_n75# a_591_n75# 0.03fF
+C14 a_783_n75# a_687_n75# 0.22fF
+C15 a_207_n75# a_591_n75# 0.03fF
+C16 a_975_n75# a_879_n75# 0.22fF
+C17 a_783_n75# a_1071_n75# 0.05fF
+C18 a_n945_n75# a_n657_n75# 0.05fF
+C19 a_207_n75# a_399_n75# 0.08fF
+C20 a_687_n75# a_495_n75# 0.08fF
+C21 a_n1229_n75# a_n849_n75# 0.03fF
+C22 a_n465_n75# a_n849_n75# 0.03fF
+C23 a_n81_n75# a_n369_n75# 0.05fF
+C24 a_783_n75# a_1167_n75# 0.03fF
+C25 a_783_n75# a_975_n75# 0.08fF
+C26 a_n1041_n75# a_n849_n75# 0.08fF
+C27 a_n177_n75# a_n369_n75# 0.08fF
+C28 a_n753_n75# a_n849_n75# 0.22fF
+C29 a_n1041_n75# a_n1229_n75# 0.08fF
+C30 a_207_n75# a_495_n75# 0.05fF
+C31 a_111_n75# a_399_n75# 0.05fF
+C32 a_15_n75# a_399_n75# 0.03fF
+C33 a_n81_n75# a_207_n75# 0.05fF
+C34 a_n753_n75# a_n465_n75# 0.05fF
+C35 a_207_n75# a_n177_n75# 0.03fF
+C36 a_n753_n75# a_n1041_n75# 0.05fF
+C37 a_n561_n75# a_n369_n75# 0.08fF
+C38 a_n81_n75# a_n273_n75# 0.08fF
+C39 a_n945_n75# a_n849_n75# 0.22fF
+C40 a_495_n75# a_111_n75# 0.03fF
+C41 a_n81_n75# a_111_n75# 0.08fF
+C42 a_n657_n75# a_n561_n75# 0.22fF
+C43 a_n1229_n75# a_n945_n75# 0.05fF
+C44 a_n273_n75# a_n177_n75# 0.22fF
+C45 a_n81_n75# a_15_n75# 0.22fF
+C46 a_303_n75# a_687_n75# 0.03fF
+C47 a_111_n75# a_n177_n75# 0.05fF
+C48 a_15_n75# a_n177_n75# 0.08fF
+C49 a_n1041_n75# a_n945_n75# 0.22fF
+C50 a_879_n75# a_591_n75# 0.05fF
+C51 a_399_n75# a_591_n75# 0.08fF
+C52 a_n753_n75# a_n945_n75# 0.08fF
+C53 a_n81_n75# a_n465_n75# 0.03fF
+C54 a_687_n75# a_1071_n75# 0.03fF
+C55 a_303_n75# a_207_n75# 0.22fF
+C56 a_n273_n75# a_n561_n75# 0.05fF
+C57 a_n465_n75# a_n177_n75# 0.05fF
+C58 a_n657_n75# a_n369_n75# 0.05fF
+C59 a_783_n75# a_591_n75# 0.08fF
+C60 a_1167_n75# a_1071_n75# 0.22fF
+C61 a_783_n75# a_879_n75# 0.22fF
+C62 a_975_n75# a_687_n75# 0.05fF
+C63 a_783_n75# a_399_n75# 0.03fF
+C64 a_975_n75# a_1071_n75# 0.22fF
+C65 a_495_n75# a_591_n75# 0.22fF
+C66 a_495_n75# a_879_n75# 0.03fF
+C67 a_n849_n75# a_n561_n75# 0.05fF
+C68 a_495_n75# a_399_n75# 0.22fF
+C69 a_303_n75# a_111_n75# 0.08fF
+C70 a_15_n75# a_303_n75# 0.05fF
+C71 a_1167_n75# a_975_n75# 0.08fF
+C72 a_n465_n75# a_n561_n75# 0.22fF
+C73 a_n273_n75# a_n369_n75# 0.22fF
+C74 a_783_n75# a_495_n75# 0.05fF
+C75 a_n849_n75# a_n1137_n75# 0.05fF
+C76 a_n273_n75# a_n657_n75# 0.03fF
+C77 a_15_n75# a_n369_n75# 0.03fF
+C78 a_n1229_n75# a_n1137_n75# 0.22fF
+C79 a_n753_n75# a_n561_n75# 0.08fF
+C80 a_n1041_n75# a_n1137_n75# 0.22fF
+C81 a_n465_n75# a_n369_n75# 0.22fF
+C82 a_207_n75# a_111_n75# 0.22fF
+C83 a_15_n75# a_207_n75# 0.08fF
+C84 a_n657_n75# a_n849_n75# 0.08fF
+C85 a_n753_n75# a_n1137_n75# 0.03fF
+C86 a_n81_n75# a_n177_n75# 0.22fF
+C87 a_303_n75# a_591_n75# 0.05fF
+C88 a_n465_n75# a_n657_n75# 0.08fF
+C89 a_n945_n75# a_n561_n75# 0.03fF
+C90 a_303_n75# a_399_n75# 0.22fF
+C91 a_n273_n75# a_111_n75# 0.03fF
+C92 a_n753_n75# a_n369_n75# 0.03fF
+C93 a_15_n75# a_n273_n75# 0.05fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n513_n75# a_n417_n75# 0.22fF
+C1 a_255_n75# a_351_n75# 0.22fF
+C2 a_735_n75# a_927_n75# 0.08fF
+C3 a_159_n75# a_447_n75# 0.05fF
+C4 a_351_n75# a_63_n75# 0.05fF
+C5 a_543_n75# a_735_n75# 0.08fF
+C6 a_n225_n75# a_n33_n75# 0.08fF
+C7 a_447_n75# a_831_n75# 0.03fF
+C8 a_159_n75# a_n225_n75# 0.03fF
+C9 a_n321_n75# a_63_n75# 0.03fF
+C10 a_33_n101# a_n927_n101# 0.08fF
+C11 a_n321_n75# a_n129_n75# 0.08fF
+C12 a_543_n75# a_927_n75# 0.03fF
+C13 a_351_n75# a_n33_n75# 0.03fF
+C14 a_159_n75# a_351_n75# 0.08fF
+C15 a_831_n75# a_639_n75# 0.08fF
+C16 a_n321_n75# a_n33_n75# 0.05fF
+C17 a_n417_n75# a_n129_n75# 0.05fF
+C18 a_n513_n75# a_n129_n75# 0.03fF
+C19 a_255_n75# a_543_n75# 0.05fF
+C20 a_447_n75# a_639_n75# 0.08fF
+C21 a_n33_n75# a_n417_n75# 0.03fF
+C22 a_351_n75# a_447_n75# 0.22fF
+C23 a_735_n75# a_831_n75# 0.22fF
+C24 a_n801_n75# a_n609_n75# 0.08fF
+C25 a_255_n75# a_63_n75# 0.08fF
+C26 a_n225_n75# a_n609_n75# 0.03fF
+C27 a_n801_n75# a_n989_n75# 0.08fF
+C28 a_255_n75# a_n129_n75# 0.03fF
+C29 a_n897_n75# a_n801_n75# 0.22fF
+C30 a_n129_n75# a_63_n75# 0.08fF
+C31 a_159_n75# a_543_n75# 0.03fF
+C32 a_n609_n75# a_n989_n75# 0.03fF
+C33 a_927_n75# a_831_n75# 0.22fF
+C34 a_n801_n75# a_n705_n75# 0.22fF
+C35 a_n225_n75# a_n321_n75# 0.22fF
+C36 a_735_n75# a_447_n75# 0.05fF
+C37 a_543_n75# a_831_n75# 0.05fF
+C38 a_351_n75# a_639_n75# 0.05fF
+C39 a_255_n75# a_n33_n75# 0.05fF
+C40 a_n897_n75# a_n609_n75# 0.05fF
+C41 a_n897_n75# a_n989_n75# 0.22fF
+C42 a_159_n75# a_255_n75# 0.22fF
+C43 a_n609_n75# a_n321_n75# 0.05fF
+C44 a_n609_n75# a_n705_n75# 0.22fF
+C45 a_n33_n75# a_63_n75# 0.22fF
+C46 a_n705_n75# a_n989_n75# 0.05fF
+C47 a_159_n75# a_63_n75# 0.22fF
+C48 a_n801_n75# a_n417_n75# 0.03fF
+C49 a_n33_n75# a_n129_n75# 0.22fF
+C50 a_n225_n75# a_n417_n75# 0.08fF
+C51 a_n513_n75# a_n801_n75# 0.05fF
+C52 a_n513_n75# a_n225_n75# 0.05fF
+C53 a_159_n75# a_n129_n75# 0.05fF
+C54 a_n897_n75# a_n705_n75# 0.08fF
+C55 a_543_n75# a_447_n75# 0.22fF
+C56 a_735_n75# a_639_n75# 0.22fF
+C57 a_n321_n75# a_n705_n75# 0.03fF
+C58 a_n609_n75# a_n417_n75# 0.08fF
+C59 a_735_n75# a_351_n75# 0.03fF
+C60 a_n513_n75# a_n609_n75# 0.22fF
+C61 a_255_n75# a_447_n75# 0.08fF
+C62 a_159_n75# a_n33_n75# 0.08fF
+C63 a_927_n75# a_639_n75# 0.05fF
+C64 a_447_n75# a_63_n75# 0.03fF
+C65 a_n897_n75# a_n513_n75# 0.03fF
+C66 a_543_n75# a_639_n75# 0.22fF
+C67 a_n321_n75# a_n417_n75# 0.22fF
+C68 a_n417_n75# a_n705_n75# 0.05fF
+C69 a_n513_n75# a_n705_n75# 0.08fF
+C70 a_n513_n75# a_n321_n75# 0.08fF
+C71 a_n225_n75# a_63_n75# 0.05fF
+C72 a_543_n75# a_351_n75# 0.08fF
+C73 a_n225_n75# a_n129_n75# 0.22fF
+C74 a_255_n75# a_639_n75# 0.03fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_159_n150# a_63_n150# 0.43fF
+C1 a_n129_n150# a_63_n150# 0.16fF
+C2 a_n801_n150# a_n989_n150# 0.16fF
+C3 a_255_n150# a_351_n150# 0.43fF
+C4 a_n513_n150# a_n417_n150# 0.43fF
+C5 a_n609_n150# a_n321_n150# 0.10fF
+C6 a_927_n150# a_543_n150# 0.07fF
+C7 a_n225_n150# a_n33_n150# 0.16fF
+C8 a_543_n150# a_735_n150# 0.16fF
+C9 a_n321_n150# a_n705_n150# 0.07fF
+C10 a_n609_n150# a_n989_n150# 0.07fF
+C11 a_447_n150# a_63_n150# 0.07fF
+C12 a_n801_n150# a_n417_n150# 0.07fF
+C13 a_447_n150# a_639_n150# 0.16fF
+C14 a_831_n150# a_639_n150# 0.16fF
+C15 a_n989_n150# a_n705_n150# 0.10fF
+C16 a_n33_n150# a_63_n150# 0.43fF
+C17 a_927_n150# a_831_n150# 0.43fF
+C18 a_n609_n150# a_n417_n150# 0.16fF
+C19 a_351_n150# a_63_n150# 0.10fF
+C20 a_255_n150# a_63_n150# 0.16fF
+C21 a_735_n150# a_831_n150# 0.43fF
+C22 a_447_n150# a_735_n150# 0.10fF
+C23 a_351_n150# a_639_n150# 0.10fF
+C24 a_255_n150# a_639_n150# 0.07fF
+C25 a_n417_n150# a_n705_n150# 0.10fF
+C26 a_n513_n150# a_n225_n150# 0.10fF
+C27 a_n225_n150# a_63_n150# 0.10fF
+C28 a_n513_n150# a_n897_n150# 0.07fF
+C29 a_n321_n150# a_n129_n150# 0.16fF
+C30 a_735_n150# a_351_n150# 0.07fF
+C31 a_n417_n150# a_n321_n150# 0.43fF
+C32 a_543_n150# a_159_n150# 0.07fF
+C33 a_n897_n150# a_n801_n150# 0.43fF
+C34 a_n513_n150# a_n801_n150# 0.10fF
+C35 a_n609_n150# a_n225_n150# 0.07fF
+C36 a_159_n150# a_n129_n150# 0.10fF
+C37 a_543_n150# a_447_n150# 0.43fF
+C38 a_543_n150# a_831_n150# 0.10fF
+C39 a_n33_n150# a_n321_n150# 0.10fF
+C40 a_n609_n150# a_n897_n150# 0.10fF
+C41 a_n417_n150# a_n129_n150# 0.10fF
+C42 a_n609_n150# a_n513_n150# 0.43fF
+C43 a_927_n150# a_639_n150# 0.10fF
+C44 a_159_n150# a_447_n150# 0.10fF
+C45 a_n897_n150# a_n705_n150# 0.16fF
+C46 a_n513_n150# a_n705_n150# 0.16fF
+C47 a_735_n150# a_639_n150# 0.43fF
+C48 a_543_n150# a_351_n150# 0.16fF
+C49 a_255_n150# a_543_n150# 0.10fF
+C50 a_n225_n150# a_n321_n150# 0.43fF
+C51 a_n33_n150# a_159_n150# 0.16fF
+C52 a_n33_n150# a_n129_n150# 0.43fF
+C53 a_n609_n150# a_n801_n150# 0.16fF
+C54 a_447_n150# a_831_n150# 0.07fF
+C55 a_927_n150# a_735_n150# 0.16fF
+C56 a_159_n150# a_351_n150# 0.16fF
+C57 a_n33_n150# a_n417_n150# 0.07fF
+C58 a_255_n150# a_159_n150# 0.43fF
+C59 a_255_n150# a_n129_n150# 0.07fF
+C60 a_n801_n150# a_n705_n150# 0.43fF
+C61 a_33_n247# a_n927_n247# 0.09fF
+C62 a_n513_n150# a_n321_n150# 0.16fF
+C63 a_n321_n150# a_63_n150# 0.07fF
+C64 a_n897_n150# a_n989_n150# 0.43fF
+C65 a_n225_n150# a_159_n150# 0.07fF
+C66 a_n225_n150# a_n129_n150# 0.43fF
+C67 a_447_n150# a_351_n150# 0.43fF
+C68 a_255_n150# a_447_n150# 0.16fF
+C69 a_n609_n150# a_n705_n150# 0.43fF
+C70 a_n225_n150# a_n417_n150# 0.16fF
+C71 a_543_n150# a_639_n150# 0.43fF
+C72 a_n33_n150# a_351_n150# 0.07fF
+C73 a_n513_n150# a_n129_n150# 0.07fF
+C74 a_255_n150# a_n33_n150# 0.10fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_687_n44# a_329_n44# 0.04fF
+C1 a_1045_n44# a_1403_n44# 0.04fF
+C2 a_n387_n44# a_n29_n44# 0.04fF
+C3 a_n1461_n44# a_n1819_n44# 0.04fF
+C4 a_n745_n44# a_n387_n44# 0.04fF
+C5 a_n745_n44# a_n1103_n44# 0.04fF
+C6 a_n1461_n44# a_n1103_n44# 0.04fF
+C7 a_n29_n44# a_329_n44# 0.04fF
+C8 a_1045_n44# a_687_n44# 0.04fF
+C9 a_1761_n44# a_1403_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_399_n150# a_783_n150# 0.07fF
+C1 a_15_n150# a_n369_n150# 0.07fF
+C2 a_n561_n150# a_n465_n150# 0.43fF
+C3 a_n81_n150# a_303_n150# 0.07fF
+C4 a_879_n150# a_687_n150# 0.16fF
+C5 a_n657_n150# a_n369_n150# 0.10fF
+C6 w_n1367_n369# a_975_n150# 0.05fF
+C7 a_111_n150# a_207_n150# 0.43fF
+C8 a_591_n150# a_783_n150# 0.16fF
+C9 a_975_n150# a_1167_n150# 0.16fF
+C10 a_879_n150# a_495_n150# 0.07fF
+C11 a_399_n150# a_207_n150# 0.16fF
+C12 a_n369_n150# a_n753_n150# 0.07fF
+C13 a_n81_n150# a_n177_n150# 0.43fF
+C14 a_303_n150# a_15_n150# 0.10fF
+C15 a_n657_n150# a_n1041_n150# 0.07fF
+C16 a_879_n150# w_n1367_n369# 0.04fF
+C17 a_1071_n150# a_975_n150# 0.43fF
+C18 a_879_n150# a_1167_n150# 0.10fF
+C19 a_591_n150# a_207_n150# 0.07fF
+C20 a_783_n150# a_975_n150# 0.16fF
+C21 a_n81_n150# a_n465_n150# 0.07fF
+C22 a_n1137_n150# a_n945_n150# 0.16fF
+C23 a_n1041_n150# a_n753_n150# 0.10fF
+C24 a_n561_n150# a_n849_n150# 0.10fF
+C25 a_15_n150# a_n177_n150# 0.16fF
+C26 a_399_n150# a_111_n150# 0.10fF
+C27 a_n273_n150# a_111_n150# 0.07fF
+C28 a_879_n150# a_1071_n150# 0.16fF
+C29 a_879_n150# a_783_n150# 0.43fF
+C30 a_n849_n150# a_n945_n150# 0.43fF
+C31 a_n657_n150# a_n465_n150# 0.16fF
+C32 a_591_n150# a_399_n150# 0.16fF
+C33 a_n1229_n150# a_n945_n150# 0.10fF
+C34 a_n81_n150# a_207_n150# 0.10fF
+C35 a_n465_n150# a_n753_n150# 0.10fF
+C36 a_n561_n150# a_n273_n150# 0.10fF
+C37 a_n1137_n150# a_n753_n150# 0.07fF
+C38 a_687_n150# a_495_n150# 0.16fF
+C39 a_303_n150# a_687_n150# 0.07fF
+C40 a_207_n150# a_15_n150# 0.16fF
+C41 a_n369_n150# a_n177_n150# 0.16fF
+C42 a_n657_n150# a_n849_n150# 0.16fF
+C43 a_303_n150# a_495_n150# 0.16fF
+C44 a_n81_n150# a_111_n150# 0.16fF
+C45 a_n465_n150# a_n369_n150# 0.43fF
+C46 a_591_n150# a_975_n150# 0.07fF
+C47 a_n849_n150# a_n753_n150# 0.43fF
+C48 a_n273_n150# a_n81_n150# 0.16fF
+C49 a_111_n150# a_15_n150# 0.43fF
+C50 a_n561_n150# a_n945_n150# 0.07fF
+C51 a_399_n150# a_15_n150# 0.07fF
+C52 a_n273_n150# a_15_n150# 0.10fF
+C53 a_879_n150# a_591_n150# 0.10fF
+C54 a_n657_n150# a_n273_n150# 0.07fF
+C55 a_1071_n150# a_687_n150# 0.07fF
+C56 w_n1367_n369# a_1167_n150# 0.14fF
+C57 a_687_n150# a_783_n150# 0.43fF
+C58 a_n1041_n150# a_n1137_n150# 0.43fF
+C59 a_783_n150# a_495_n150# 0.10fF
+C60 a_n465_n150# a_n177_n150# 0.10fF
+C61 a_879_n150# a_975_n150# 0.43fF
+C62 a_n657_n150# a_n561_n150# 0.43fF
+C63 a_1071_n150# w_n1367_n369# 0.07fF
+C64 a_n1041_n150# a_n849_n150# 0.16fF
+C65 a_1071_n150# a_1167_n150# 0.43fF
+C66 a_783_n150# a_1167_n150# 0.07fF
+C67 a_207_n150# a_495_n150# 0.10fF
+C68 a_303_n150# a_207_n150# 0.43fF
+C69 a_n561_n150# a_n753_n150# 0.16fF
+C70 a_n1041_n150# a_n1229_n150# 0.16fF
+C71 a_n657_n150# a_n945_n150# 0.10fF
+C72 a_n273_n150# a_n369_n150# 0.43fF
+C73 a_n81_n150# a_15_n150# 0.43fF
+C74 a_1071_n150# a_783_n150# 0.10fF
+C75 a_207_n150# a_n177_n150# 0.07fF
+C76 a_n753_n150# a_n945_n150# 0.16fF
+C77 a_111_n150# a_495_n150# 0.07fF
+C78 a_303_n150# a_111_n150# 0.16fF
+C79 a_n849_n150# a_n465_n150# 0.07fF
+C80 a_399_n150# a_687_n150# 0.10fF
+C81 a_399_n150# a_495_n150# 0.43fF
+C82 a_399_n150# a_303_n150# 0.43fF
+C83 a_n561_n150# a_n369_n150# 0.16fF
+C84 a_n849_n150# a_n1137_n150# 0.10fF
+C85 a_111_n150# a_n177_n150# 0.10fF
+C86 a_591_n150# a_687_n150# 0.43fF
+C87 a_591_n150# a_495_n150# 0.43fF
+C88 a_591_n150# a_303_n150# 0.10fF
+C89 a_n273_n150# a_n177_n150# 0.43fF
+C90 a_n1137_n150# a_n1229_n150# 0.43fF
+C91 a_n657_n150# a_n753_n150# 0.43fF
+C92 a_n273_n150# a_n465_n150# 0.16fF
+C93 a_n81_n150# a_n369_n150# 0.10fF
+C94 a_687_n150# a_975_n150# 0.10fF
+C95 a_n1041_n150# a_n945_n150# 0.43fF
+C96 a_n849_n150# a_n1229_n150# 0.07fF
+C97 a_n561_n150# a_n177_n150# 0.07fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vdd nUp vss Down biasp out pswitch iref nDown Up
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 nswitch out 1.28fF
+C1 nswitch Down 2.27fF
+C2 biasp pswitch 3.11fF
+C3 vdd pswitch 3.98fF
+C4 nDown Down 0.13fF
+C5 nDown nswitch 0.31fF
+C6 nswitch iref 1.91fF
+C7 Up pswitch 0.70fF
+C8 vdd out 6.66fF
+C9 nUp Up 0.15fF
+C10 biasp nswitch 0.03fF
+C11 nswitch vdd 0.07fF
+C12 nUp pswitch 5.66fF
+C13 biasp iref 0.80fF
+C14 pswitch out 4.91fF
+C15 nUp out 0.31fF
+C16 nswitch pswitch 0.06fF
+C17 biasp vdd 2.64fF
+C18 nUp Down 0.25fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 w_n311_n344# a_n81_n125# 0.09fF
+C3 a_15_n125# a_n173_n125# 0.13fF
+C4 a_n81_n125# a_111_n125# 0.13fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 w_n311_n344# a_111_n125# 0.14fF
+C8 w_n311_n344# a_n173_n125# 0.14fF
+C9 a_15_n125# w_n311_n344# 0.09fF
+C10 a_81_n156# a_n15_n156# 0.02fF
+C11 a_n111_n156# a_n15_n156# 0.02fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n15_n151# a_n111_n151# 0.02fF
+C1 a_n81_n125# a_111_n125# 0.13fF
+C2 a_n173_n125# a_111_n125# 0.08fF
+C3 a_15_n125# a_111_n125# 0.36fF
+C4 a_81_n151# a_n15_n151# 0.02fF
+C5 a_n173_n125# a_n81_n125# 0.36fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 a_n173_n125# a_15_n125# 0.13fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 vdd m1_187_n605# 0.55fF
+C1 m1_187_n605# m1_45_n513# 0.36fF
+C2 vdd m1_45_n513# 0.69fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# w_n311_n344# 0.14fF
+C1 a_n81_n125# w_n311_n344# 0.09fF
+C2 a_15_n125# w_n311_n344# 0.09fF
+C3 a_111_n125# a_n81_n125# 0.13fF
+C4 w_n311_n344# a_n173_n125# 0.14fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_n81_n125# a_15_n125# 0.36fF
+C7 a_111_n125# a_n173_n125# 0.08fF
+C8 a_n81_n125# a_n173_n125# 0.36fF
+C9 a_15_n125# a_n173_n125# 0.13fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 a_111_n125# a_n173_n125# 0.08fF
+C3 a_15_n125# a_n81_n125# 0.36fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 out vdd 0.10fF
+C1 out in 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in CLK 0.31fF
+C1 vdd CLK_d 0.03fF
+C2 vdd inverter_cp_x1_0/out 0.28fF
+C3 vdd CLK 0.36fF
+C4 vdd inverter_cp_x1_2/in 0.21fF
+C5 nCLK_d inverter_cp_x1_0/out 0.11fF
+C6 vdd nCLK_d 0.03fF
+C7 CLK_d inverter_cp_x1_2/in 0.12fF
+C8 CLK inverter_cp_x1_0/out 0.31fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_63_n95# a_n125_n95# 0.10fF
+C1 a_63_n95# a_n33_n95# 0.28fF
+C2 a_n125_n95# a_n33_n95# 0.28fF
+C3 w_n263_n314# a_63_n95# 0.11fF
+C4 w_n263_n314# a_n125_n95# 0.11fF
+C5 w_n263_n314# a_n33_n95# 0.08fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_n173_n125# 0.36fF
+C1 a_111_n125# a_n81_n125# 0.13fF
+C2 a_15_n125# a_n173_n125# 0.13fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n81_n125# a_15_n125# 0.36fF
+C5 a_n129_n213# a_n173_n125# 0.02fF
+C6 a_n129_n213# a_111_n125# 0.01fF
+C7 a_n129_n213# a_n81_n125# 0.10fF
+C8 a_n129_n213# a_15_n125# 0.10fF
+C9 a_111_n125# a_n173_n125# 0.08fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_n125_n95# 0.88fF
+C1 a_n81_n183# a_n125_n95# 0.16fF
+C2 a_n81_n183# a_n33_n95# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 nQ vdd 0.16fF
+C1 m1_657_280# Q 0.94fF
+C2 m1_657_280# CLK 0.24fF
+C3 nD Q 0.05fF
+C4 m1_657_280# nQ 1.41fF
+C5 D Q 0.05fF
+C6 nQ nD 0.05fF
+C7 nQ D 0.05fF
+C8 nQ Q 0.93fF
+C9 vdd Q 0.16fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
++ nCLK latch_diff_0/nD
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 Q latch_diff_1/nD 0.01fF
+C1 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C2 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C3 latch_diff_1/D latch_diff_0/nD 0.41fF
+C4 latch_diff_0/D latch_diff_1/nD 0.04fF
+C5 latch_diff_0/D latch_diff_1/D 0.11fF
+C6 vdd latch_diff_0/nD 0.14fF
+C7 latch_diff_1/nD latch_diff_1/D 0.33fF
+C8 vdd latch_diff_0/D 0.09fF
+C9 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C10 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C11 latch_diff_0/D latch_diff_0/m1_657_280# 0.37fF
+C12 vdd latch_diff_1/nD 0.02fF
+C13 vdd latch_diff_1/D 0.03fF
+C14 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C15 nQ latch_diff_1/nD 0.08fF
+C16 nQ latch_diff_1/D 0.11fF
+C17 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C18 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_63_n84# a_n33_n84# 0.24fF
+C1 w_n359_n303# a_159_n84# 0.08fF
+C2 a_n129_n84# a_n221_n84# 0.24fF
+C3 a_63_n84# a_159_n84# 0.24fF
+C4 a_n33_n84# a_n129_n84# 0.24fF
+C5 a_n33_n84# a_n221_n84# 0.09fF
+C6 w_n359_n303# a_63_n84# 0.06fF
+C7 a_n129_n84# a_159_n84# 0.05fF
+C8 a_n221_n84# a_159_n84# 0.04fF
+C9 a_n33_n84# a_159_n84# 0.09fF
+C10 a_n63_n110# a_n159_n110# 0.02fF
+C11 w_n359_n303# a_n129_n84# 0.06fF
+C12 w_n359_n303# a_n221_n84# 0.08fF
+C13 w_n359_n303# a_n33_n84# 0.05fF
+C14 a_33_n110# a_129_n110# 0.02fF
+C15 a_63_n84# a_n129_n84# 0.09fF
+C16 a_63_n84# a_n221_n84# 0.05fF
+C17 a_n63_n110# a_33_n110# 0.02fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n129_n42# a_n221_n42# 0.12fF
+C1 a_63_n42# a_n33_n42# 0.12fF
+C2 a_n221_n42# a_159_n42# 0.02fF
+C3 a_n159_n68# a_n63_n68# 0.02fF
+C4 a_n129_n42# a_n33_n42# 0.12fF
+C5 a_n129_n42# a_63_n42# 0.05fF
+C6 a_n33_n42# a_159_n42# 0.05fF
+C7 a_63_n42# a_159_n42# 0.12fF
+C8 a_33_n68# a_129_n68# 0.02fF
+C9 a_n129_n42# a_159_n42# 0.03fF
+C10 a_n221_n42# a_n33_n42# 0.05fF
+C11 a_n221_n42# a_63_n42# 0.03fF
+C12 a_33_n68# a_n63_n68# 0.02fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 out vdd 0.62fF
+C1 out in 0.67fF
+C2 in vdd 0.33fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n42# a_63_n42# 0.12fF
+C1 a_n125_n42# a_n33_n42# 0.12fF
+C2 a_33_n68# a_n63_n68# 0.02fF
+C3 a_n125_n42# a_63_n42# 0.05fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n63_n110# a_33_n110# 0.02fF
+C1 a_n125_n84# a_n33_n84# 0.24fF
+C2 w_n263_n303# a_n33_n84# 0.07fF
+C3 a_63_n84# a_n125_n84# 0.09fF
+C4 a_63_n84# w_n263_n303# 0.10fF
+C5 a_63_n84# a_n33_n84# 0.24fF
+C6 w_n263_n303# a_n125_n84# 0.10fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 vdd in 0.01fF
+C1 vdd out 0.15fF
+C2 out in 0.30fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 DFlipFlop_0/nCLK vdd 0.30fF
+C1 o2 nCLK_2 0.11fF
+C2 out_div vdd 0.03fF
+C3 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C4 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C5 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C6 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C7 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C8 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C9 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
+C10 CLK_2 o1 0.11fF
+C11 nout_div vdd 0.16fF
+C12 o2 vdd 0.14fF
+C13 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/nD 0.12fF
+C14 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
+C15 nout_div DFlipFlop_0/CLK 0.42fF
+C16 DFlipFlop_0/nCLK nout_div 0.43fF
+C17 nCLK_2 vdd 0.08fF
+C18 nout_div out_div 0.22fF
+C19 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C20 vdd o1 0.14fF
+C21 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C22 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C23 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C24 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C25 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/CLK -0.48fF
+C26 out_div o1 0.01fF
+C27 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C28 DFlipFlop_0/nCLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.46fF
+C29 CLK_2 vdd 0.08fF
+C30 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C31 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C32 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C33 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C34 DFlipFlop_0/CLK vdd 0.40fF
+C35 nCLK_2 vss 1.08fF
+C36 o2 vss 2.21fF
+C37 CLK_2 vss 1.08fF
+C38 o1 vss 2.21fF
+C39 DFlipFlop_0/CLK vss 1.03fF
+C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C42 CLK vss 3.27fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n257_n777# a_n221_n600# 0.25fF
+C1 a_n257_n777# a_n129_n600# 0.29fF
+C2 a_n221_n600# a_n129_n600# 7.87fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n257_n404# a_n221_n300# 0.21fF
+C1 a_n221_n300# a_n129_n300# 4.05fF
+C2 a_n257_n404# a_n129_n300# 0.30fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 a_3996_n100# vdd 3.68fF
+C1 a_678_n100# a_3996_n100# 6.52fF
+C2 a_3996_n100# out 55.19fF
+C3 a_678_n100# vdd 0.08fF
+C4 out vdd 47.17fF
+C5 vdd in 0.02fF
+C6 a_678_n100# in 0.81fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n238# a_n73_n150# 0.02fF
+C1 a_15_n150# a_n33_n238# 0.02fF
+C2 a_15_n150# a_n73_n150# 0.51fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_181# a_15_n150# 0.01fF
+C1 a_n73_n150# a_15_n150# 0.51fF
+C2 w_n211_n369# a_n33_181# 0.05fF
+C3 a_n73_n150# w_n211_n369# 0.20fF
+C4 w_n211_n369# a_15_n150# 0.20fF
+C5 a_n73_n150# a_n33_181# 0.01fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n129_n150# a_159_n150# 0.10fF
+C1 a_n465_172# a_n129_n150# 0.10fF
+C2 a_n509_n150# a_n321_n150# 0.16fF
+C3 a_n465_172# a_159_n150# 0.10fF
+C4 a_n417_n150# a_n321_n150# 0.43fF
+C5 a_63_n150# a_447_n150# 0.07fF
+C6 a_63_n150# a_255_n150# 0.16fF
+C7 a_n129_n150# a_255_n150# 0.07fF
+C8 a_447_n150# a_159_n150# 0.10fF
+C9 a_n465_172# a_447_n150# 0.01fF
+C10 a_n417_n150# a_n33_n150# 0.07fF
+C11 a_255_n150# a_159_n150# 0.43fF
+C12 a_n465_172# a_255_n150# 0.10fF
+C13 a_351_n150# a_n33_n150# 0.07fF
+C14 a_n33_n150# a_n321_n150# 0.10fF
+C15 a_447_n150# a_255_n150# 0.16fF
+C16 a_n509_n150# a_n225_n150# 0.10fF
+C17 a_n129_n150# a_n509_n150# 0.07fF
+C18 a_n417_n150# a_n225_n150# 0.16fF
+C19 a_n417_n150# a_n129_n150# 0.10fF
+C20 a_n465_172# a_n509_n150# 0.01fF
+C21 a_351_n150# a_63_n150# 0.10fF
+C22 a_n417_n150# a_n465_172# 0.10fF
+C23 a_63_n150# a_n321_n150# 0.07fF
+C24 a_351_n150# a_159_n150# 0.16fF
+C25 a_n225_n150# a_n321_n150# 0.43fF
+C26 a_n465_172# a_351_n150# 0.10fF
+C27 a_n129_n150# a_n321_n150# 0.16fF
+C28 a_n465_172# a_n321_n150# 0.10fF
+C29 a_63_n150# a_n33_n150# 0.43fF
+C30 a_n33_n150# a_n225_n150# 0.16fF
+C31 a_351_n150# a_447_n150# 0.43fF
+C32 a_n129_n150# a_n33_n150# 0.43fF
+C33 a_351_n150# a_255_n150# 0.43fF
+C34 a_n33_n150# a_159_n150# 0.16fF
+C35 a_n465_172# a_n33_n150# 0.10fF
+C36 a_n33_n150# a_255_n150# 0.10fF
+C37 a_63_n150# a_n225_n150# 0.10fF
+C38 a_n417_n150# a_n509_n150# 0.43fF
+C39 a_n129_n150# a_63_n150# 0.16fF
+C40 a_n129_n150# a_n225_n150# 0.43fF
+C41 a_63_n150# a_159_n150# 0.43fF
+C42 a_n225_n150# a_159_n150# 0.07fF
+C43 a_n465_172# a_63_n150# 0.10fF
+C44 a_n465_172# a_n225_n150# 0.10fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n321_n150# a_n33_n150# 0.10fF
+C1 a_n321_n150# a_n129_n150# 0.16fF
+C2 a_n321_n150# a_n225_n150# 0.43fF
+C3 a_63_n150# a_159_n150# 0.43fF
+C4 a_63_n150# a_n33_n150# 0.43fF
+C5 a_63_n150# a_n129_n150# 0.16fF
+C6 a_n321_n150# w_n647_n369# 0.05fF
+C7 a_63_n150# a_n225_n150# 0.10fF
+C8 a_63_n150# w_n647_n369# 0.02fF
+C9 a_n417_n150# a_n33_n150# 0.07fF
+C10 a_n417_n150# a_n129_n150# 0.10fF
+C11 a_n465_n247# a_159_n150# 0.08fF
+C12 a_n465_n247# a_n33_n150# 0.08fF
+C13 a_n417_n150# a_n225_n150# 0.16fF
+C14 a_n465_n247# a_n129_n150# 0.08fF
+C15 a_n321_n150# a_63_n150# 0.07fF
+C16 a_n465_n247# a_n225_n150# 0.08fF
+C17 a_n417_n150# w_n647_n369# 0.07fF
+C18 a_n465_n247# w_n647_n369# 0.47fF
+C19 a_n321_n150# a_n417_n150# 0.43fF
+C20 a_255_n150# a_351_n150# 0.43fF
+C21 a_n321_n150# a_n465_n247# 0.08fF
+C22 a_447_n150# a_255_n150# 0.16fF
+C23 a_n465_n247# a_63_n150# 0.08fF
+C24 a_n417_n150# a_n465_n247# 0.08fF
+C25 a_447_n150# a_351_n150# 0.43fF
+C26 a_n509_n150# a_n129_n150# 0.07fF
+C27 a_n509_n150# a_n225_n150# 0.10fF
+C28 a_255_n150# a_159_n150# 0.43fF
+C29 a_255_n150# a_n33_n150# 0.10fF
+C30 a_255_n150# a_n129_n150# 0.07fF
+C31 a_n509_n150# w_n647_n369# 0.14fF
+C32 a_255_n150# w_n647_n369# 0.05fF
+C33 a_n321_n150# a_n509_n150# 0.16fF
+C34 a_159_n150# a_351_n150# 0.16fF
+C35 a_n33_n150# a_351_n150# 0.07fF
+C36 a_255_n150# a_63_n150# 0.16fF
+C37 a_447_n150# a_159_n150# 0.10fF
+C38 a_n509_n150# a_n417_n150# 0.43fF
+C39 w_n647_n369# a_351_n150# 0.07fF
+C40 a_447_n150# w_n647_n369# 0.14fF
+C41 a_255_n150# a_n465_n247# 0.08fF
+C42 a_63_n150# a_351_n150# 0.10fF
+C43 a_447_n150# a_63_n150# 0.07fF
+C44 a_n465_n247# a_351_n150# 0.08fF
+C45 a_159_n150# a_n33_n150# 0.16fF
+C46 a_n129_n150# a_159_n150# 0.10fF
+C47 a_n129_n150# a_n33_n150# 0.43fF
+C48 a_159_n150# a_n225_n150# 0.07fF
+C49 a_n33_n150# a_n225_n150# 0.16fF
+C50 a_n129_n150# a_n225_n150# 0.43fF
+C51 a_159_n150# w_n647_n369# 0.04fF
+C52 w_n647_n369# a_n33_n150# 0.02fF
+C53 a_n129_n150# w_n647_n369# 0.02fF
+C54 w_n647_n369# a_n225_n150# 0.04fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n99# a_n73_n11# 0.02fF
+C1 a_15_n11# a_n73_n11# 0.15fF
+C2 a_15_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# a_20_n114# 0.42fF
+C1 a_n78_n114# w_n216_n334# 0.20fF
+C2 w_n216_n334# a_20_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vss 0.01fF
+C1 vbulkp vdd 0.04fF
+C2 vbulkp out 0.08fF
+C3 in vdd 0.01fF
+C4 in out 0.11fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 inverter_csvco_0/vdd out 0.02fF
+C1 vbp inverter_csvco_0/vdd 0.75fF
+C2 cap_vco_0/t out 0.70fF
+C3 inverter_csvco_0/vdd vdd 1.89fF
+C4 cap_vco_0/t vdd 0.04fF
+C5 inverter_csvco_0/vdd in 0.01fF
+C6 D0 out 0.09fF
+C7 inverter_csvco_0/vss D0 0.02fF
+C8 vbp vdd 1.21fF
+C9 out in 0.06fF
+C10 vctrl inverter_csvco_0/vss 0.87fF
+C11 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C12 inverter_csvco_0/vss out 0.03fF
+C13 inverter_csvco_0/vss in 0.01fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vdd vss csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
+C1 csvco_branch_2/in out_vco 0.58fF
+C2 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C3 D0 csvco_branch_1/inverter_csvco_0/vss 0.68fF
+C4 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C5 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
+C6 csvco_branch_1/cap_vco_0/t out_vco 0.03fF
+C7 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C8 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C9 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C10 D0 csvco_branch_0/inverter_csvco_0/vss 0.49fF
+C11 csvco_branch_1/in out_vco 0.76fF
+C12 vctrl csvco_branch_2/vbp 0.06fF
+C13 vdd csvco_branch_2/vbp 1.49fF
+C14 D0 vctrl 4.41fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 vdd o1 0.09fF
+C1 out_div vdd 0.17fF
+C2 out_div out_pad 0.15fF
+C3 out_div o1 0.11fF
+C4 vdd out_pad 0.10fF
+C5 in_vco vss 0.83fF
+C6 out_pad vss 0.70fF
+C7 out_div vss 3.00fF
+C8 vdd vss 14.54fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 VPB VPWR 0.06fF
+C1 B VGND 0.10fF
+C2 a_355_368# VPWR 0.37fF
+C3 a_355_368# A 0.02fF
+C4 B VPWR 0.09fF
+C5 a_194_125# X 0.29fF
+C6 VGND VPWR 0.01fF
+C7 B A 0.28fF
+C8 A VGND 0.31fF
+C9 A VPWR 0.15fF
+C10 a_355_368# a_194_125# 0.51fF
+C11 B a_194_125# 0.57fF
+C12 a_355_368# X 0.17fF
+C13 a_194_125# VGND 0.25fF
+C14 a_194_125# a_158_392# 0.06fF
+C15 B X 0.13fF
+C16 VGND X 0.28fF
+C17 a_194_125# VPWR 0.33fF
+C18 a_194_125# A 0.18fF
+C19 VPWR X 0.07fF
+C20 B a_355_368# 0.08fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 A B 0.08fF
+C1 A a_56_136# 0.17fF
+C2 VPWR B 0.02fF
+C3 VPWR a_56_136# 0.57fF
+C4 B X 0.02fF
+C5 X a_56_136# 0.26fF
+C6 A VGND 0.21fF
+C7 B a_56_136# 0.30fF
+C8 X VGND 0.15fF
+C9 VPWR A 0.07fF
+C10 VPWR VPB 0.04fF
+C11 VPWR X 0.20fF
+C12 B VGND 0.03fF
+C13 VGND a_56_136# 0.06fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 X VGND 0.16fF
+C1 A a_63_368# 0.28fF
+C2 VGND B 0.11fF
+C3 a_152_368# a_63_368# 0.03fF
+C4 a_63_368# VGND 0.27fF
+C5 X VPWR 0.18fF
+C6 VPWR VPB 0.04fF
+C7 VPWR B 0.01fF
+C8 X A 0.02fF
+C9 VPWR A 0.05fF
+C10 A B 0.10fF
+C11 X a_63_368# 0.33fF
+C12 VPWR a_63_368# 0.29fF
+C13 a_63_368# B 0.14fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
++ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
++ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
++ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C1 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C2 Q1_shift DFlipFlop_3/nQ 0.04fF
+C3 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C4 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C5 DFlipFlop_1/latch_diff_1/m1_657_280# nQ0 0.21fF
+C6 DFlipFlop_0/latch_diff_0/D Q0 0.42fF
+C7 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C8 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C9 nCLK sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.11fF
+C10 DFlipFlop_3/nQ Q1 0.10fF
+C11 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
+C12 vdd DFlipFlop_2/nQ 0.02fF
+C13 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C14 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.08fF
+C15 nCLK Q1 -0.01fF
+C16 nCLK nQ2 0.10fF
+C17 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C18 DFlipFlop_2/D Q1 0.10fF
+C19 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C20 DFlipFlop_0/D Q0 0.39fF
+C21 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C22 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C23 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C24 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C25 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C26 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
+C27 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C28 vdd DFlipFlop_0/D 0.19fF
+C29 Q1_shift vdd 0.10fF
+C30 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
+C31 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C32 Q1 Q0 9.65fF
+C33 Q0 nQ2 0.23fF
+C34 vdd Q1 9.49fF
+C35 vdd nQ2 0.04fF
+C36 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C37 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C38 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C39 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
+C40 CLK nQ0 0.19fF
+C41 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C42 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C43 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C44 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C45 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C46 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C47 nCLK DFlipFlop_0/Q 0.11fF
+C48 nCLK DFlipFlop_3/latch_diff_1/D 0.14fF
+C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C50 nCLK DFlipFlop_1/D 0.14fF
+C51 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C52 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C53 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C54 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C55 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q1 0.09fF
+C56 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C57 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q1 0.20fF
+C58 DFlipFlop_3/latch_diff_1/nD Q1 1.24fF
+C59 DFlipFlop_0/Q Q0 0.21fF
+C60 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C61 CLK DFlipFlop_2/nQ 0.13fF
+C62 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C63 DFlipFlop_1/D Q0 0.07fF
+C64 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C65 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C66 nCLK DFlipFlop_3/nQ 0.02fF
+C67 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C68 vdd DFlipFlop_1/D 0.25fF
+C69 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q0 0.42fF
+C70 DFlipFlop_2/D nCLK 0.41fF
+C71 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C72 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C73 DFlipFlop_0/latch_diff_1/nD Q1 0.10fF
+C74 nQ0 Q1 0.06fF
+C75 nQ0 nQ2 0.03fF
+C76 vdd DFlipFlop_3/nQ 0.02fF
+C77 CLK Q1 -0.10fF
+C78 nCLK Q0 0.20fF
+C79 CLK nQ2 0.17fF
+C80 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C81 DFlipFlop_2/D Q0 0.25fF
+C82 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C83 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C84 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C85 vdd nCLK 0.34fF
+C86 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C87 vdd DFlipFlop_2/D 0.07fF
+C88 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C89 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C90 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C91 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C92 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C93 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C94 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C95 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C96 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C97 vdd Q0 5.33fF
+C98 Q1 DFlipFlop_2/nQ 0.31fF
+C99 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
+C100 Q1 DFlipFlop_0/latch_diff_0/D 0.15fF
+C101 Q1 DFlipFlop_3/latch_diff_1/m1_657_280# 0.28fF
+C102 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.28fF
+C103 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C104 nCLK DFlipFlop_1/latch_diff_1/D 0.08fF
+C105 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C106 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C107 nQ0 DFlipFlop_1/D 0.12fF
+C108 DFlipFlop_3/latch_diff_1/nD nCLK 0.09fF
+C109 CLK DFlipFlop_0/Q 0.08fF
+C110 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
+C111 DFlipFlop_0/D Q1 0.13fF
+C112 CLK DFlipFlop_1/D 0.21fF
+C113 Q1_shift Q1 0.36fF
+C114 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C115 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C116 nCLK DFlipFlop_1/latch_diff_1/nD 0.16fF
+C117 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C118 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C119 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C120 vdd CLK_5 0.15fF
+C121 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C122 Q1 nQ2 0.07fF
+C123 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C124 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C125 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C126 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C127 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C128 DFlipFlop_3/nQ CLK 0.01fF
+C129 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C130 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C131 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C132 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C133 nCLK nQ0 0.09fF
+C134 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C135 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C136 DFlipFlop_2/D CLK 0.14fF
+C137 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
+C138 nCLK sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.02fF
+C139 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C140 DFlipFlop_3/latch_diff_0/m1_657_280# Q1 0.28fF
+C141 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C142 nQ0 Q0 0.33fF
+C143 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.08fF
+C144 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
+C145 CLK Q0 0.08fF
+C146 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C147 nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
+C148 vdd nQ0 0.11fF
+C149 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C150 vdd CLK 0.41fF
+C151 DFlipFlop_0/Q Q1 0.13fF
+C152 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C153 nCLK DFlipFlop_2/nQ 0.09fF
+C154 DFlipFlop_0/Q nQ2 0.09fF
+C155 Q1 DFlipFlop_1/D 0.03fF
+C156 sky130_fd_sc_hs__xor2_1_0/a_355_368# Q0 0.03fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 DFlipFlop_2/nQ vss 0.50fF
+C172 Q1 vss 8.55fF
+C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 nQ0 vss 3.42fF
+C183 Q0 vss 0.53fF
+C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n129_n125# a_63_n125# 0.13fF
+C1 a_255_n125# a_n129_n125# 0.06fF
+C2 a_n255_n151# a_n159_n151# 0.02fF
+C3 a_n33_n125# a_63_n125# 0.36fF
+C4 a_255_n125# a_n33_n125# 0.08fF
+C5 a_n63_n151# a_n159_n151# 0.02fF
+C6 a_n225_n125# a_n317_n125# 0.36fF
+C7 a_159_n125# a_n225_n125# 0.06fF
+C8 a_255_n125# a_63_n125# 0.13fF
+C9 a_n129_n125# a_n225_n125# 0.36fF
+C10 a_n129_n125# a_n317_n125# 0.13fF
+C11 a_n129_n125# a_159_n125# 0.08fF
+C12 a_225_n151# a_129_n151# 0.02fF
+C13 a_n33_n125# a_n225_n125# 0.13fF
+C14 a_n33_n125# a_n317_n125# 0.08fF
+C15 a_n33_n125# a_159_n125# 0.13fF
+C16 a_n225_n125# a_63_n125# 0.08fF
+C17 a_n129_n125# a_n33_n125# 0.36fF
+C18 a_n63_n151# a_33_n151# 0.02fF
+C19 a_33_n151# a_129_n151# 0.02fF
+C20 a_63_n125# a_n317_n125# 0.06fF
+C21 a_159_n125# a_63_n125# 0.36fF
+C22 a_255_n125# a_159_n125# 0.36fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n455_n344# a_255_n125# 0.11fF
+C1 w_n455_n344# a_159_n125# 0.06fF
+C2 a_n225_n125# a_n33_n125# 0.13fF
+C3 a_n129_n125# a_63_n125# 0.13fF
+C4 a_n255_n154# a_n159_n154# 0.02fF
+C5 a_255_n125# a_n33_n125# 0.08fF
+C6 a_n129_n125# a_n317_n125# 0.13fF
+C7 a_n33_n125# a_159_n125# 0.13fF
+C8 a_n129_n125# w_n455_n344# 0.04fF
+C9 a_n225_n125# a_159_n125# 0.06fF
+C10 a_n129_n125# a_n33_n125# 0.36fF
+C11 a_255_n125# a_159_n125# 0.36fF
+C12 a_63_n125# a_n317_n125# 0.06fF
+C13 a_n129_n125# a_n225_n125# 0.36fF
+C14 w_n455_n344# a_63_n125# 0.04fF
+C15 a_33_n154# a_129_n154# 0.02fF
+C16 w_n455_n344# a_n317_n125# 0.11fF
+C17 a_n129_n125# a_255_n125# 0.06fF
+C18 a_n129_n125# a_159_n125# 0.08fF
+C19 a_63_n125# a_n33_n125# 0.36fF
+C20 a_n317_n125# a_n33_n125# 0.08fF
+C21 w_n455_n344# a_n33_n125# 0.05fF
+C22 a_225_n154# a_129_n154# 0.02fF
+C23 a_63_n125# a_n225_n125# 0.08fF
+C24 a_n63_n154# a_n159_n154# 0.02fF
+C25 a_n317_n125# a_n225_n125# 0.36fF
+C26 a_33_n154# a_n63_n154# 0.02fF
+C27 w_n455_n344# a_n225_n125# 0.06fF
+C28 a_63_n125# a_255_n125# 0.13fF
+C29 a_63_n125# a_159_n125# 0.36fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 vdd in 0.04fF
+C1 in out 0.85fF
+C2 vdd out 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 Up inverter_cp_x1_2/in 0.12fF
+C1 Down vdd 0.09fF
+C2 nUp vdd 0.14fF
+C3 Down inverter_cp_x1_0/out 0.12fF
+C4 vdd QA 0.02fF
+C5 Down nDown 0.23fF
+C6 vdd inverter_cp_x1_0/out 0.25fF
+C7 nDown vdd 0.80fF
+C8 QB vdd 0.02fF
+C9 nDown inverter_cp_x1_0/out 0.11fF
+C10 nUp Up 0.20fF
+C11 Up vdd 0.60fF
+C12 vdd inverter_cp_x1_2/in 0.42fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n63_n116# a_n159_n207# 0.12fF
+C1 w_n359_n309# a_63_n90# 0.06fF
+C2 w_n359_n309# a_n221_n90# 0.09fF
+C3 a_63_n90# a_n129_n90# 0.09fF
+C4 a_n33_n90# w_n359_n309# 0.05fF
+C5 w_n359_n309# a_159_n90# 0.09fF
+C6 a_n221_n90# a_n129_n90# 0.26fF
+C7 a_n33_n90# a_n129_n90# 0.26fF
+C8 a_n129_n90# a_159_n90# 0.06fF
+C9 a_63_n90# a_n221_n90# 0.06fF
+C10 a_n33_n90# a_63_n90# 0.26fF
+C11 a_63_n90# a_159_n90# 0.26fF
+C12 a_n33_n90# a_n221_n90# 0.09fF
+C13 a_n221_n90# a_159_n90# 0.04fF
+C14 a_n33_n90# a_159_n90# 0.09fF
+C15 w_n359_n309# a_n129_n90# 0.06fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n33_n45# 0.13fF
+C1 a_n129_71# a_33_n71# 0.04fF
+C2 a_63_n45# a_n125_n45# 0.05fF
+C3 a_n33_n45# a_n125_n45# 0.13fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C1 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C2 out vdd 0.11fF
+C3 vdd A 0.09fF
+C4 out A 0.06fF
+C5 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C6 out B 0.40fF
+C7 A B 0.24fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 Reset nor_pfd_3/A 0.12fF
+C1 vdd nor_pfd_2/A -0.01fF
+C2 CLK Q 0.04fF
+C3 Reset Q 0.14fF
+C4 nor_pfd_3/A Q 0.98fF
+C5 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C6 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C7 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C8 vdd nor_pfd_2/B 0.02fF
+C9 nor_pfd_2/A Q 1.38fF
+C10 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C11 nor_pfd_2/B Reset 0.43fF
+C12 nor_pfd_2/B nor_pfd_3/A 0.58fF
+C13 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C14 nor_pfd_2/B Q 2.22fF
+C15 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C16 vdd nor_pfd_3/A 0.09fF
+C17 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C18 vdd Q 0.08fF
+C19 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_159_n45# a_n221_n45# 0.02fF
+C1 a_63_n45# a_n221_n45# 0.03fF
+C2 a_n221_n45# a_n129_n45# 0.13fF
+C3 a_n63_n71# a_n159_n173# 0.10fF
+C4 a_63_n45# a_159_n45# 0.13fF
+C5 a_159_n45# a_n129_n45# 0.03fF
+C6 a_63_n45# a_n129_n45# 0.05fF
+C7 a_n33_n45# a_n221_n45# 0.05fF
+C8 a_159_n45# a_n33_n45# 0.05fF
+C9 a_63_n45# a_n33_n45# 0.13fF
+C10 a_n33_n45# a_n129_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n33_n90# a_n125_n90# 0.26fF
+C1 a_63_n90# a_n125_n90# 0.09fF
+C2 a_n99_n187# a_33_n187# 0.04fF
+C3 a_63_n90# a_n33_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n73_n45# a_15_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n73_n90# a_15_n90# 0.31fF
+C1 a_n73_n90# w_n211_n309# 0.04fF
+C2 a_15_n90# w_n211_n309# 0.09fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 a_656_410# out 0.20fF
+C1 A vdd 0.05fF
+C2 a_656_410# vdd 0.20fF
+C3 A B 0.33fF
+C4 a_656_410# B 0.30fF
+C5 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C6 vdd out 0.10fF
+C7 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C8 A a_656_410# 0.04fF
+C9 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 dff_pfd_1/nor_pfd_2/B vdd 0.04fF
+C1 Reset vdd 0.02fF
+C2 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C3 Up Down 0.06fF
+C4 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
+C5 vdd Down 0.08fF
+C6 vdd Up 1.62fF
+C7 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
+C8 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C9 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+
+* Top level circuit top_pll_v1
+
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 nswitch vdd nUp vss Down biasp vco_vctrl pswitch iref_cp nDown Up charge_pump
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss ring_osc_0/csvco_branch_0/inverter_csvco_0/vss ring_osc_0/csvco_branch_2/vbp
++ vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 vdd n_out_by_2 1.03fF
+C1 div_5_nQ2 n_out_by_2 0.10fF
+C2 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C3 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C4 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
+C5 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_out_by_2 0.12fF
+C6 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C7 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
+C8 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C9 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
+C10 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
+C11 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C12 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C13 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C14 vdd Up 0.28fF
+C15 nUp vco_vctrl 0.02fF
+C16 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
+C17 vdd iref_cp 0.15fF
+C18 nswitch vco_vctrl -0.06fF
+C19 biasp nDown 0.26fF
+C20 nUp biasp -0.17fF
+C21 out_to_buffer out_to_div 0.13fF
+C22 nUp nDown -0.09fF
+C23 vco_vctrl out_by_2 0.53fF
+C24 nswitch nDown 0.76fF
+C25 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
+C26 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C27 div_5_Q0 n_out_by_2 -0.12fF
+C28 Up pswitch 1.98fF
+C29 QA vdd -0.04fF
+C30 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 0.27fF
+C31 vco_D0 vdd 0.03fF
+C32 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
+C33 biasp Down 1.24fF
+C34 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C35 Down nDown 2.55fF
+C36 nswitch Down 0.54fF
+C37 div_5_Q1 out_div_by_5 0.01fF
+C38 div_by_5_0/DFlipFlop_3/latch_diff_0/D out_by_2 0.11fF
+C39 div_5_Q1 vco_vctrl 0.14fF
+C40 out_to_div vdd 0.21fF
+C41 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
+C42 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
+C43 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
+C44 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
+C45 div_5_nQ0 out_by_2 0.32fF
+C46 div_5_Q1 out_by_2 0.42fF
+C47 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C48 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C49 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C50 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
+C51 vco_vctrl n_out_by_2 0.52fF
+C52 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C53 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C54 vdd out_div_by_5 0.28fF
+C55 vdd vco_vctrl -1.02fF
+C56 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C57 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C58 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C59 div_5_Q1_shift out_div_by_5 0.05fF
+C60 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C61 nUp vdd 0.05fF
+C62 vdd nDown 0.22fF
+C63 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C64 div_5_nQ2 out_by_2 0.16fF
+C65 vdd out_by_2 0.97fF
+C66 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C67 lf_vc vdd 0.02fF
+C68 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# n_out_by_2 0.01fF
+C69 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
+C70 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
+C71 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C72 pswitch nDown 0.53fF
+C73 nUp pswitch 0.85fF
+C74 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
+C75 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C76 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C77 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
+C78 div_by_5_0/DFlipFlop_2/latch_diff_0/D n_out_by_2 0.12fF
+C79 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C80 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
+C81 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C82 div_by_5_0/DFlipFlop_2/latch_diff_1/D n_out_by_2 0.10fF
+C83 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C84 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
+C85 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C86 div_5_nQ0 n_out_by_2 0.10fF
+C87 biasp Up 0.26fF
+C88 div_by_5_0/DFlipFlop_0/Q out_by_2 0.09fF
+C89 div_5_Q1 n_out_by_2 1.04fF
+C90 vdd buffer_salida_0/a_678_n100# 0.24fF
+C91 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C92 nUp Up 2.72fF
+C93 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C94 out_to_buffer vdd 0.07fF
+C95 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C96 div_by_5_0/DFlipFlop_1/D out_by_2 0.38fF
+C97 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
+C98 div_5_Q0 vco_vctrl 0.48fF
+C99 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
+C100 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C101 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C102 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C103 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C104 div_5_Q0 out_by_2 0.09fF
+C105 iref_cp Down 0.09fF
+C106 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
+C107 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.46fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss -0.40fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.31fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 5.50fF
+C141 Up vss 2.37fF
+C142 Down vss 7.92fF
+C143 nDown vss -2.20fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C158 div_5_Q1 vss 4.28fF
+C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_nQ0 vss 0.59fF
+C169 div_5_Q0 vss 0.01fF
+C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_to_buffer vss 1.57fF
+C196 out_to_div vss 4.46fF
+C197 out_first_buffer vss 2.88fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 vco_D0 vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 n_out_buffer_div_2 vss 1.63fF
+C216 out_buffer_div_2 vss 1.60fF
+C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 nswitch vss 3.73fF
+C232 biasp vss 5.44fF
+C233 iref_cp vss 2.81fF
+C234 vco_vctrl vss -19.28fF
+C235 pswitch vss 3.57fF
+C236 lf_vc vss -59.89fF
+C237 loop_filter_0/res_loop_filter_2/out vss 7.90fF
+.end
+
diff --git a/mag/extractions/top_pll_v1_pex_c_port.spice b/mag/extractions/top_pll_v1_pex_c_port.spice
new file mode 100644
index 0000000..17a76d5
--- /dev/null
+++ b/mag/extractions/top_pll_v1_pex_c_port.spice
@@ -0,0 +1,2883 @@
+* NGSPICE file created from top_pll_v1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_2669_8000# m3_n2650_8000# 2.73fF
+C1 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C2 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C3 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C4 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C5 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C6 m3_n2650_2700# m3_2669_2700# 2.73fF
+C7 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C8 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C9 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C10 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C11 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C12 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C13 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C14 m3_2669_n2600# m3_2669_2700# 3.28fF
+C15 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C16 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C17 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C18 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C19 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C20 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C21 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C22 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C23 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C24 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C25 m3_2669_n13200# m3_7988_n13200# 2.73fF
+C26 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C27 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C28 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C29 m3_2669_8000# m3_2669_2700# 3.28fF
+C30 m3_7988_2700# m3_7988_n2600# 3.39fF
+C31 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C32 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C33 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C34 m3_7988_2700# m3_2669_2700# 2.73fF
+C35 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C36 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C37 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C38 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C39 m3_2669_n2600# c1_n13188_n13100# 58.86fF
+C40 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C41 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C42 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C43 m3_2669_8000# m3_7988_8000# 2.73fF
+C44 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C45 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C46 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C47 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C48 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C49 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C50 m3_7988_2700# m3_7988_8000# 3.39fF
+C51 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C52 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C53 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C54 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C55 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C56 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C57 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C58 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C59 m3_2669_n2600# m3_n2650_n2600# 2.73fF
+C60 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C61 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C62 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C63 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C64 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C1 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C2 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C3 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C4 c1_n6369_n6300# m3_n6469_2200# 38.10fF
+C5 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C6 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C7 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C8 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C9 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C10 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C11 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
+C12 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C13 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C14 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C15 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C16 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C17 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C18 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 vc_pex vss -38.13fF
+C2 res_loop_filter_2/out vss 8.49fF
+C3 in vss -18.79fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 w_n2457_n634# a_2261_n486# 0.02fF
+C1 w_n2457_n634# a_n29_n486# 0.02fF
+C2 w_n2457_n634# a_n1403_n486# 0.02fF
+C3 w_n2457_n634# a_1345_n486# 0.02fF
+C4 w_n2457_n634# a_1803_n486# 0.02fF
+C5 w_n2457_n634# a_n2319_n486# 0.02fF
+C6 w_n2457_n634# a_n945_n486# 0.02fF
+C7 w_n2457_n634# a_n1861_n486# 0.02fF
+C8 w_n2457_n634# a_n487_n486# 0.02fF
+C9 w_n2457_n634# a_887_n486# 0.02fF
+C10 w_n2457_n634# a_429_n486# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n945_n75# a_n753_n75# 0.08fF
+C1 a_n849_n75# a_n561_n75# 0.05fF
+C2 a_111_n75# a_399_n75# 0.05fF
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+C4 a_n81_n75# a_111_n75# 0.08fF
+C5 a_n1137_n75# a_n753_n75# 0.03fF
+C6 a_303_n75# a_591_n75# 0.05fF
+C7 a_591_n75# a_495_n75# 0.22fF
+C8 a_303_n75# a_495_n75# 0.08fF
+C9 a_399_n75# a_207_n75# 0.08fF
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+C11 a_n273_n75# a_n465_n75# 0.08fF
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+C13 a_n81_n75# a_207_n75# 0.05fF
+C14 a_975_n75# a_1071_n75# 0.22fF
+C15 a_n1041_n75# a_n753_n75# 0.05fF
+C16 a_n945_n75# a_n1137_n75# 0.08fF
+C17 a_975_n75# a_879_n75# 0.22fF
+C18 a_15_n75# a_399_n75# 0.03fF
+C19 a_n81_n75# a_n465_n75# 0.03fF
+C20 a_n177_n75# a_n369_n75# 0.08fF
+C21 a_n657_n75# a_n753_n75# 0.22fF
+C22 a_n81_n75# a_15_n75# 0.22fF
+C23 a_n657_n75# a_n465_n75# 0.08fF
+C24 a_n849_n75# a_n1229_n75# 0.03fF
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+C26 a_975_n75# a_1167_n75# 0.08fF
+C27 a_n177_n75# a_n561_n75# 0.03fF
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+C31 a_n369_n75# a_n753_n75# 0.03fF
+C32 a_n369_n75# a_n465_n75# 0.22fF
+C33 a_879_n75# a_1071_n75# 0.08fF
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+C36 a_591_n75# a_207_n75# 0.03fF
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+C38 a_303_n75# a_207_n75# 0.22fF
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+C48 a_n273_n75# a_n657_n75# 0.03fF
+C49 a_15_n75# a_303_n75# 0.05fF
+C50 a_687_n75# a_879_n75# 0.08fF
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+C52 a_1167_n75# a_879_n75# 0.05fF
+C53 a_399_n75# a_687_n75# 0.05fF
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+C61 a_n849_n75# a_n1137_n75# 0.05fF
+C62 a_879_n75# a_783_n75# 0.22fF
+C63 a_n273_n75# a_n561_n75# 0.05fF
+C64 a_n177_n75# a_207_n75# 0.03fF
+C65 a_399_n75# a_783_n75# 0.03fF
+C66 a_n81_n75# a_n369_n75# 0.05fF
+C67 a_687_n75# a_783_n75# 0.22fF
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+C69 a_n657_n75# a_n369_n75# 0.05fF
+C70 a_1167_n75# a_783_n75# 0.03fF
+C71 a_591_n75# a_879_n75# 0.05fF
+C72 a_n849_n75# a_n1041_n75# 0.08fF
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+C76 a_399_n75# a_591_n75# 0.08fF
+C77 a_303_n75# a_399_n75# 0.22fF
+C78 a_15_n75# a_207_n75# 0.08fF
+C79 a_n657_n75# a_n561_n75# 0.22fF
+C80 a_399_n75# a_495_n75# 0.22fF
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+C83 a_591_n75# a_687_n75# 0.22fF
+C84 a_303_n75# a_687_n75# 0.03fF
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+C86 a_n1229_n75# a_n945_n75# 0.05fF
+C87 a_n465_n75# a_n753_n75# 0.05fF
+C88 a_n561_n75# a_n369_n75# 0.08fF
+C89 a_n1229_n75# a_n1137_n75# 0.22fF
+C90 a_111_n75# a_n273_n75# 0.03fF
+C91 a_591_n75# a_783_n75# 0.08fF
+C92 a_495_n75# a_783_n75# 0.05fF
+C93 a_n273_n75# a_n177_n75# 0.22fF
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+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
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+C117 a_n1041_n75# w_n1367_n285# 0.04fF
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+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n417_n75# a_n129_n75# 0.05fF
+C1 a_63_n75# a_447_n75# 0.03fF
+C2 a_n417_n75# a_n609_n75# 0.08fF
+C3 a_n513_n75# a_n705_n75# 0.08fF
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+C8 a_735_n75# a_543_n75# 0.08fF
+C9 a_n609_n75# a_n321_n75# 0.05fF
+C10 a_n129_n75# a_255_n75# 0.03fF
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+C13 a_n513_n75# a_n129_n75# 0.03fF
+C14 a_159_n75# a_543_n75# 0.03fF
+C15 a_n417_n75# a_n801_n75# 0.03fF
+C16 a_831_n75# a_639_n75# 0.08fF
+C17 a_351_n75# a_255_n75# 0.22fF
+C18 a_n513_n75# a_n609_n75# 0.22fF
+C19 a_351_n75# a_543_n75# 0.08fF
+C20 a_n705_n75# a_n989_n75# 0.05fF
+C21 a_n513_n75# a_n897_n75# 0.03fF
+C22 a_831_n75# a_447_n75# 0.03fF
+C23 a_n417_n75# a_n225_n75# 0.08fF
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+C28 a_63_n75# a_n321_n75# 0.03fF
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+C31 a_447_n75# a_255_n75# 0.08fF
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+C34 a_n897_n75# a_n705_n75# 0.08fF
+C35 a_447_n75# a_543_n75# 0.22fF
+C36 a_927_n75# a_543_n75# 0.03fF
+C37 a_n609_n75# a_n989_n75# 0.03fF
+C38 a_n897_n75# a_n989_n75# 0.22fF
+C39 a_63_n75# a_255_n75# 0.08fF
+C40 a_n33_n75# a_255_n75# 0.05fF
+C41 a_735_n75# a_351_n75# 0.03fF
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+C43 a_159_n75# a_n129_n75# 0.05fF
+C44 a_735_n75# a_639_n75# 0.22fF
+C45 a_n705_n75# a_n801_n75# 0.22fF
+C46 a_159_n75# a_351_n75# 0.08fF
+C47 a_n417_n75# a_n321_n75# 0.22fF
+C48 a_n897_n75# a_n609_n75# 0.05fF
+C49 a_n801_n75# a_n989_n75# 0.08fF
+C50 a_735_n75# a_447_n75# 0.05fF
+C51 a_927_n75# a_735_n75# 0.08fF
+C52 a_n417_n75# a_n513_n75# 0.22fF
+C53 a_351_n75# a_639_n75# 0.05fF
+C54 a_n609_n75# a_n801_n75# 0.08fF
+C55 a_831_n75# a_543_n75# 0.05fF
+C56 a_159_n75# a_447_n75# 0.05fF
+C57 a_n897_n75# a_n801_n75# 0.22fF
+C58 a_n129_n75# a_63_n75# 0.08fF
+C59 a_n513_n75# a_n321_n75# 0.08fF
+C60 a_n225_n75# a_n129_n75# 0.22fF
+C61 a_351_n75# a_447_n75# 0.22fF
+C62 a_n129_n75# a_n33_n75# 0.22fF
+C63 a_159_n75# a_63_n75# 0.22fF
+C64 a_159_n75# a_n225_n75# 0.03fF
+C65 a_159_n75# a_n33_n75# 0.08fF
+C66 a_n225_n75# a_n609_n75# 0.03fF
+C67 a_63_n75# a_351_n75# 0.05fF
+C68 a_351_n75# a_n33_n75# 0.03fF
+C69 a_543_n75# a_255_n75# 0.05fF
+C70 a_n417_n75# a_n705_n75# 0.05fF
+C71 a_447_n75# a_639_n75# 0.08fF
+C72 a_927_n75# a_639_n75# 0.05fF
+C73 a_n705_n75# a_n321_n75# 0.03fF
+C74 a_735_n75# a_831_n75# 0.22fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n801_n150# a_n513_n150# 0.10fF
+C1 a_351_n150# a_639_n150# 0.10fF
+C2 a_63_n150# a_n321_n150# 0.07fF
+C3 a_351_n150# a_159_n150# 0.16fF
+C4 a_n897_n150# a_n705_n150# 0.16fF
+C5 a_543_n150# a_735_n150# 0.16fF
+C6 a_639_n150# a_447_n150# 0.16fF
+C7 a_n609_n150# a_n705_n150# 0.43fF
+C8 a_n33_n150# a_n225_n150# 0.16fF
+C9 a_n33_n150# a_255_n150# 0.10fF
+C10 a_n417_n150# a_n705_n150# 0.10fF
+C11 a_159_n150# a_447_n150# 0.10fF
+C12 a_n897_n150# a_n513_n150# 0.07fF
+C13 a_n801_n150# a_n989_n150# 0.16fF
+C14 a_n609_n150# a_n513_n150# 0.43fF
+C15 a_255_n150# a_639_n150# 0.07fF
+C16 a_n609_n150# a_n225_n150# 0.07fF
+C17 a_n417_n150# a_n513_n150# 0.43fF
+C18 a_159_n150# a_n225_n150# 0.07fF
+C19 a_255_n150# a_159_n150# 0.43fF
+C20 a_n417_n150# a_n225_n150# 0.16fF
+C21 a_351_n150# a_63_n150# 0.10fF
+C22 a_n705_n150# a_n321_n150# 0.07fF
+C23 a_351_n150# a_543_n150# 0.16fF
+C24 a_351_n150# a_735_n150# 0.07fF
+C25 a_n897_n150# a_n801_n150# 0.43fF
+C26 a_n129_n150# a_n513_n150# 0.07fF
+C27 a_n609_n150# a_n801_n150# 0.16fF
+C28 a_n129_n150# a_n225_n150# 0.43fF
+C29 a_255_n150# a_n129_n150# 0.07fF
+C30 a_639_n150# a_831_n150# 0.16fF
+C31 a_n801_n150# a_n417_n150# 0.07fF
+C32 a_63_n150# a_447_n150# 0.07fF
+C33 a_n897_n150# a_n989_n150# 0.43fF
+C34 a_543_n150# a_447_n150# 0.43fF
+C35 a_735_n150# a_447_n150# 0.10fF
+C36 a_n609_n150# a_n989_n150# 0.07fF
+C37 a_n321_n150# a_n513_n150# 0.16fF
+C38 a_n321_n150# a_n225_n150# 0.43fF
+C39 a_n33_n150# a_159_n150# 0.16fF
+C40 a_n33_n150# a_n417_n150# 0.07fF
+C41 a_63_n150# a_n225_n150# 0.10fF
+C42 a_255_n150# a_63_n150# 0.16fF
+C43 a_255_n150# a_543_n150# 0.10fF
+C44 a_n609_n150# a_n897_n150# 0.10fF
+C45 a_831_n150# a_927_n150# 0.43fF
+C46 a_n33_n150# a_n129_n150# 0.43fF
+C47 a_n609_n150# a_n417_n150# 0.16fF
+C48 a_351_n150# a_447_n150# 0.43fF
+C49 a_n33_n150# a_n321_n150# 0.10fF
+C50 a_543_n150# a_831_n150# 0.10fF
+C51 a_831_n150# a_735_n150# 0.43fF
+C52 a_639_n150# a_927_n150# 0.10fF
+C53 a_33_n247# a_n927_n247# 0.09fF
+C54 a_n33_n150# a_63_n150# 0.43fF
+C55 a_159_n150# a_n129_n150# 0.10fF
+C56 a_351_n150# a_255_n150# 0.43fF
+C57 a_n417_n150# a_n129_n150# 0.10fF
+C58 a_n705_n150# a_n513_n150# 0.16fF
+C59 a_n609_n150# a_n321_n150# 0.10fF
+C60 a_n417_n150# a_n321_n150# 0.43fF
+C61 a_543_n150# a_639_n150# 0.43fF
+C62 a_255_n150# a_447_n150# 0.16fF
+C63 a_639_n150# a_735_n150# 0.43fF
+C64 a_63_n150# a_159_n150# 0.43fF
+C65 a_543_n150# a_159_n150# 0.07fF
+C66 a_n225_n150# a_n513_n150# 0.10fF
+C67 a_n801_n150# a_n705_n150# 0.43fF
+C68 a_n321_n150# a_n129_n150# 0.16fF
+C69 a_351_n150# a_n33_n150# 0.07fF
+C70 a_n989_n150# a_n705_n150# 0.10fF
+C71 a_63_n150# a_n129_n150# 0.16fF
+C72 a_831_n150# a_447_n150# 0.07fF
+C73 a_543_n150# a_927_n150# 0.07fF
+C74 a_735_n150# a_927_n150# 0.16fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n387_n44# a_n29_n44# 0.04fF
+C1 a_329_n44# a_n29_n44# 0.04fF
+C2 a_n1461_n44# a_n1103_n44# 0.04fF
+C3 a_n1461_n44# a_n1819_n44# 0.04fF
+C4 a_1045_n44# a_687_n44# 0.04fF
+C5 a_n745_n44# a_n1103_n44# 0.04fF
+C6 a_1403_n44# a_1761_n44# 0.04fF
+C7 a_1403_n44# a_1045_n44# 0.04fF
+C8 a_n745_n44# a_n387_n44# 0.04fF
+C9 a_329_n44# a_687_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n849_n150# a_n1137_n150# 0.10fF
+C1 a_n81_n150# a_n273_n150# 0.16fF
+C2 a_n1229_n150# a_n945_n150# 0.10fF
+C3 a_207_n150# a_303_n150# 0.43fF
+C4 a_15_n150# a_n369_n150# 0.07fF
+C5 a_399_n150# a_591_n150# 0.16fF
+C6 a_495_n150# a_303_n150# 0.16fF
+C7 a_111_n150# a_15_n150# 0.43fF
+C8 a_n945_n150# a_n753_n150# 0.16fF
+C9 a_n849_n150# a_n561_n150# 0.10fF
+C10 a_n945_n150# a_n1137_n150# 0.16fF
+C11 a_n657_n150# a_n753_n150# 0.43fF
+C12 a_1071_n150# a_783_n150# 0.10fF
+C13 a_n465_n150# a_n753_n150# 0.10fF
+C14 a_1071_n150# a_1167_n150# 0.43fF
+C15 a_n81_n150# a_207_n150# 0.10fF
+C16 a_591_n150# a_303_n150# 0.10fF
+C17 a_n945_n150# a_n561_n150# 0.07fF
+C18 a_1071_n150# a_975_n150# 0.43fF
+C19 a_n657_n150# a_n561_n150# 0.43fF
+C20 a_n657_n150# a_n273_n150# 0.07fF
+C21 a_207_n150# a_495_n150# 0.10fF
+C22 a_n465_n150# a_n561_n150# 0.43fF
+C23 a_495_n150# a_783_n150# 0.10fF
+C24 a_399_n150# a_687_n150# 0.10fF
+C25 a_n465_n150# a_n273_n150# 0.16fF
+C26 a_783_n150# a_1167_n150# 0.07fF
+C27 a_111_n150# a_399_n150# 0.10fF
+C28 a_1071_n150# w_n1367_n369# 0.07fF
+C29 a_n753_n150# a_n369_n150# 0.07fF
+C30 a_n1229_n150# a_n1041_n150# 0.16fF
+C31 a_399_n150# a_15_n150# 0.07fF
+C32 a_975_n150# a_783_n150# 0.16fF
+C33 a_n177_n150# a_n561_n150# 0.07fF
+C34 a_n177_n150# a_n273_n150# 0.43fF
+C35 a_591_n150# a_207_n150# 0.07fF
+C36 a_n1041_n150# a_n753_n150# 0.10fF
+C37 a_975_n150# a_1167_n150# 0.16fF
+C38 a_n81_n150# a_n465_n150# 0.07fF
+C39 a_591_n150# a_783_n150# 0.16fF
+C40 a_687_n150# a_303_n150# 0.07fF
+C41 a_591_n150# a_495_n150# 0.43fF
+C42 a_n1041_n150# a_n1137_n150# 0.43fF
+C43 a_1071_n150# a_879_n150# 0.16fF
+C44 a_n369_n150# a_n561_n150# 0.16fF
+C45 a_n849_n150# a_n945_n150# 0.43fF
+C46 a_111_n150# a_303_n150# 0.16fF
+C47 a_n369_n150# a_n273_n150# 0.43fF
+C48 a_n657_n150# a_n849_n150# 0.16fF
+C49 a_111_n150# a_n273_n150# 0.07fF
+C50 w_n1367_n369# a_1167_n150# 0.14fF
+C51 a_1071_n150# a_687_n150# 0.07fF
+C52 a_15_n150# a_303_n150# 0.10fF
+C53 a_n849_n150# a_n465_n150# 0.07fF
+C54 a_591_n150# a_975_n150# 0.07fF
+C55 a_n81_n150# a_n177_n150# 0.43fF
+C56 a_15_n150# a_n273_n150# 0.10fF
+C57 w_n1367_n369# a_975_n150# 0.05fF
+C58 a_207_n150# a_n177_n150# 0.07fF
+C59 a_n657_n150# a_n945_n150# 0.10fF
+C60 a_783_n150# a_879_n150# 0.43fF
+C61 a_495_n150# a_879_n150# 0.07fF
+C62 a_n81_n150# a_n369_n150# 0.10fF
+C63 a_111_n150# a_n81_n150# 0.16fF
+C64 a_1167_n150# a_879_n150# 0.10fF
+C65 a_783_n150# a_687_n150# 0.43fF
+C66 a_n657_n150# a_n465_n150# 0.16fF
+C67 a_495_n150# a_687_n150# 0.16fF
+C68 a_n1229_n150# a_n1137_n150# 0.43fF
+C69 a_111_n150# a_207_n150# 0.43fF
+C70 a_n81_n150# a_15_n150# 0.43fF
+C71 a_111_n150# a_495_n150# 0.07fF
+C72 a_975_n150# a_879_n150# 0.43fF
+C73 a_207_n150# a_15_n150# 0.16fF
+C74 a_n753_n150# a_n1137_n150# 0.07fF
+C75 a_591_n150# a_879_n150# 0.10fF
+C76 a_975_n150# a_687_n150# 0.10fF
+C77 a_399_n150# a_303_n150# 0.43fF
+C78 a_n849_n150# a_n1041_n150# 0.16fF
+C79 w_n1367_n369# a_879_n150# 0.04fF
+C80 a_n465_n150# a_n177_n150# 0.10fF
+C81 a_591_n150# a_687_n150# 0.43fF
+C82 a_n753_n150# a_n561_n150# 0.16fF
+C83 a_n657_n150# a_n369_n150# 0.10fF
+C84 a_n1041_n150# a_n945_n150# 0.43fF
+C85 a_n465_n150# a_n369_n150# 0.43fF
+C86 a_n657_n150# a_n1041_n150# 0.07fF
+C87 a_n273_n150# a_n561_n150# 0.10fF
+C88 a_399_n150# a_207_n150# 0.16fF
+C89 a_687_n150# a_879_n150# 0.16fF
+C90 a_399_n150# a_783_n150# 0.07fF
+C91 a_n369_n150# a_n177_n150# 0.16fF
+C92 a_399_n150# a_495_n150# 0.43fF
+C93 a_111_n150# a_n177_n150# 0.10fF
+C94 a_n1229_n150# a_n849_n150# 0.07fF
+C95 a_15_n150# a_n177_n150# 0.16fF
+C96 a_n81_n150# a_303_n150# 0.07fF
+C97 a_n849_n150# a_n753_n150# 0.43fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vdd nUp vss Down biasp out pswitch iref nDown Up
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 out pswitch 4.91fF
+C1 nswitch vdd 0.07fF
+C2 out nUp 0.31fF
+C3 out vdd 6.66fF
+C4 Down nDown 0.13fF
+C5 nswitch out 1.28fF
+C6 iref biasp 0.80fF
+C7 pswitch biasp 3.11fF
+C8 pswitch Up 0.70fF
+C9 Down nUp 0.25fF
+C10 nswitch Down 2.27fF
+C11 pswitch nUp 5.66fF
+C12 Up nUp 0.15fF
+C13 biasp vdd 2.64fF
+C14 iref nswitch 1.91fF
+C15 pswitch vdd 3.98fF
+C16 nswitch biasp 0.03fF
+C17 nswitch pswitch 0.06fF
+C18 nswitch nDown 0.31fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_n111_n156# a_n15_n156# 0.02fF
+C2 a_n81_n125# w_n311_n344# 0.09fF
+C3 a_111_n125# a_n81_n125# 0.13fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_81_n156# a_n15_n156# 0.02fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 a_111_n125# w_n311_n344# 0.14fF
+C8 a_n173_n125# w_n311_n344# 0.14fF
+C9 a_111_n125# a_n173_n125# 0.08fF
+C10 a_15_n125# w_n311_n344# 0.09fF
+C11 a_15_n125# a_111_n125# 0.36fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n15_n151# a_81_n151# 0.02fF
+C1 a_15_n125# a_n81_n125# 0.36fF
+C2 a_n111_n151# a_n15_n151# 0.02fF
+C3 a_n173_n125# a_111_n125# 0.08fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_n173_n125# a_15_n125# 0.13fF
+C6 a_n81_n125# a_111_n125# 0.13fF
+C7 a_15_n125# a_111_n125# 0.36fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 vdd m1_45_n513# 0.69fF
+C1 m1_187_n605# vdd 0.55fF
+C2 m1_187_n605# m1_45_n513# 0.36fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_111_n125# w_n311_n344# 0.14fF
+C2 a_n81_n125# a_n173_n125# 0.36fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_15_n125# w_n311_n344# 0.09fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_n81_n125# w_n311_n344# 0.09fF
+C7 a_111_n125# a_n173_n125# 0.08fF
+C8 w_n311_n344# a_n173_n125# 0.14fF
+C9 a_15_n125# a_n81_n125# 0.36fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n81_n125# 0.13fF
+C1 a_111_n125# a_n173_n125# 0.08fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 a_15_n125# a_n173_n125# 0.13fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 in out 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd CLK_d 0.03fF
+C1 nCLK_d vdd 0.03fF
+C2 vdd inverter_cp_x1_2/in 0.21fF
+C3 CLK inverter_cp_x1_2/in 0.31fF
+C4 CLK_d inverter_cp_x1_2/in 0.12fF
+C5 vdd inverter_cp_x1_0/out 0.28fF
+C6 CLK inverter_cp_x1_0/out 0.31fF
+C7 nCLK_d inverter_cp_x1_0/out 0.11fF
+C8 vdd CLK 0.36fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_n125_n95# 0.28fF
+C1 a_n33_n95# w_n263_n314# 0.08fF
+C2 a_63_n95# a_n33_n95# 0.28fF
+C3 a_n125_n95# w_n263_n314# 0.11fF
+C4 a_63_n95# a_n125_n95# 0.10fF
+C5 a_63_n95# w_n263_n314# 0.11fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n81_n125# 0.36fF
+C1 a_n173_n125# a_n129_n213# 0.02fF
+C2 a_111_n125# a_n173_n125# 0.08fF
+C3 a_15_n125# a_n81_n125# 0.36fF
+C4 a_15_n125# a_n129_n213# 0.10fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_n173_n125# a_15_n125# 0.13fF
+C7 a_n81_n125# a_n129_n213# 0.10fF
+C8 a_111_n125# a_n81_n125# 0.13fF
+C9 a_111_n125# a_n129_n213# 0.01fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n33_n95# 0.88fF
+C1 a_n125_n95# a_n81_n183# 0.16fF
+C2 a_n33_n95# a_n81_n183# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 CLK m1_657_280# 0.24fF
+C1 vdd Q 0.16fF
+C2 Q nD 0.05fF
+C3 D Q 0.05fF
+C4 nQ m1_657_280# 1.41fF
+C5 vdd nQ 0.16fF
+C6 nQ nD 0.05fF
+C7 D nQ 0.05fF
+C8 Q nQ 0.93fF
+C9 Q m1_657_280# 0.94fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
++ nCLK latch_diff_0/nD
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 nQ latch_diff_1/nD 0.08fF
+C1 latch_diff_1/D latch_diff_1/nD 0.33fF
+C2 vdd latch_diff_0/D 0.09fF
+C3 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C4 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C5 latch_diff_1/D latch_diff_1/m1_657_280# 0.32fF
+C6 latch_diff_0/D latch_diff_1/nD 0.04fF
+C7 latch_diff_0/D latch_diff_0/m1_657_280# 0.37fF
+C8 nQ latch_diff_1/D 0.11fF
+C9 vdd latch_diff_0/nD 0.14fF
+C10 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C11 latch_diff_1/D latch_diff_0/D 0.11fF
+C12 latch_diff_0/nD latch_diff_1/D 0.41fF
+C13 vdd latch_diff_1/nD 0.02fF
+C14 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
+C15 Q latch_diff_1/nD 0.01fF
+C16 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C17 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C18 vdd latch_diff_1/D 0.03fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n129_n84# a_63_n84# 0.09fF
+C1 a_159_n84# a_n33_n84# 0.09fF
+C2 a_n221_n84# w_n359_n303# 0.08fF
+C3 a_n221_n84# a_n129_n84# 0.24fF
+C4 w_n359_n303# a_n33_n84# 0.05fF
+C5 a_33_n110# a_129_n110# 0.02fF
+C6 a_n129_n84# a_n33_n84# 0.24fF
+C7 w_n359_n303# a_159_n84# 0.08fF
+C8 a_n221_n84# a_63_n84# 0.05fF
+C9 a_159_n84# a_n129_n84# 0.05fF
+C10 a_n33_n84# a_63_n84# 0.24fF
+C11 a_n63_n110# a_33_n110# 0.02fF
+C12 a_n63_n110# a_n159_n110# 0.02fF
+C13 a_159_n84# a_63_n84# 0.24fF
+C14 w_n359_n303# a_n129_n84# 0.06fF
+C15 a_n221_n84# a_n33_n84# 0.09fF
+C16 w_n359_n303# a_63_n84# 0.06fF
+C17 a_n221_n84# a_159_n84# 0.04fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n129_n42# a_n33_n42# 0.12fF
+C1 a_n221_n42# a_159_n42# 0.02fF
+C2 a_n221_n42# a_63_n42# 0.03fF
+C3 a_n129_n42# a_159_n42# 0.03fF
+C4 a_n129_n42# a_63_n42# 0.05fF
+C5 a_33_n68# a_n63_n68# 0.02fF
+C6 a_159_n42# a_n33_n42# 0.05fF
+C7 a_n33_n42# a_63_n42# 0.12fF
+C8 a_33_n68# a_129_n68# 0.02fF
+C9 a_n63_n68# a_n159_n68# 0.02fF
+C10 a_159_n42# a_63_n42# 0.12fF
+C11 a_n221_n42# a_n129_n42# 0.12fF
+C12 a_n221_n42# a_n33_n42# 0.05fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 out vdd 0.62fF
+C1 in vdd 0.33fF
+C2 in out 0.67fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n125_n42# a_n33_n42# 0.12fF
+C1 a_33_n68# a_n63_n68# 0.02fF
+C2 a_63_n42# a_n33_n42# 0.12fF
+C3 a_63_n42# a_n125_n42# 0.05fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n33_n84# a_63_n84# 0.24fF
+C1 a_n33_n84# w_n263_n303# 0.07fF
+C2 a_63_n84# w_n263_n303# 0.10fF
+C3 a_33_n110# a_n63_n110# 0.02fF
+C4 a_n33_n84# a_n125_n84# 0.24fF
+C5 a_63_n84# a_n125_n84# 0.09fF
+C6 w_n263_n303# a_n125_n84# 0.10fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 out in 0.30fF
+C1 out vdd 0.15fF
+C2 vdd in 0.01fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C1 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
+C2 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C3 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C4 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C5 DFlipFlop_0/latch_diff_0/D DFlipFlop_0/nCLK 0.13fF
+C6 nCLK_2 vdd 0.08fF
+C7 vdd DFlipFlop_0/CLK 0.40fF
+C8 DFlipFlop_0/latch_diff_0/nD nout_div 0.07fF
+C9 vdd DFlipFlop_0/nCLK 0.30fF
+C10 out_div nout_div 0.22fF
+C11 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C12 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C13 out_div o1 0.01fF
+C14 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C15 CLK_2 o1 0.11fF
+C16 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C17 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C18 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C19 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/CLK -0.48fF
+C20 DFlipFlop_0/latch_diff_0/D nout_div 0.09fF
+C21 vdd out_div 0.03fF
+C22 vdd o2 0.14fF
+C23 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C24 vdd CLK_2 0.08fF
+C25 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
+C26 vdd nout_div 0.16fF
+C27 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C28 vdd o1 0.14fF
+C29 nCLK_2 o2 0.11fF
+C30 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C31 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C32 nout_div DFlipFlop_0/CLK 0.42fF
+C33 nout_div DFlipFlop_0/nCLK 0.43fF
+C34 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C35 nCLK_2 vss 1.08fF
+C36 o2 vss 2.21fF
+C37 CLK_2 vss 1.08fF
+C38 o1 vss 2.21fF
+C39 DFlipFlop_0/CLK vss 1.03fF
+C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C42 CLK vss 3.27fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n257_n777# a_n221_n600# 0.25fF
+C1 a_n129_n600# a_n221_n600# 7.87fF
+C2 a_n257_n777# a_n129_n600# 0.29fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n221_n300# a_n129_n300# 4.05fF
+C1 a_n257_n404# a_n129_n300# 0.30fF
+C2 a_n221_n300# a_n257_n404# 0.21fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 in a_678_n100# 0.81fF
+C1 vdd in 0.02fF
+C2 vdd out 47.17fF
+C3 vdd a_678_n100# 0.08fF
+C4 a_3996_n100# out 55.19fF
+C5 a_3996_n100# a_678_n100# 6.52fF
+C6 a_3996_n100# vdd 3.68fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n238# a_n73_n150# 0.02fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 a_15_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n369# a_n33_181# 0.05fF
+C1 a_15_n150# w_n211_n369# 0.20fF
+C2 a_n73_n150# a_n33_181# 0.01fF
+C3 a_n73_n150# a_15_n150# 0.51fF
+C4 a_n73_n150# w_n211_n369# 0.20fF
+C5 a_15_n150# a_n33_181# 0.01fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n129_n150# a_63_n150# 0.16fF
+C1 a_447_n150# a_159_n150# 0.10fF
+C2 a_n321_n150# a_n33_n150# 0.10fF
+C3 a_n225_n150# a_159_n150# 0.07fF
+C4 a_447_n150# a_n465_172# 0.01fF
+C5 a_n225_n150# a_n465_172# 0.10fF
+C6 a_n33_n150# a_159_n150# 0.16fF
+C7 a_n465_172# a_n509_n150# 0.01fF
+C8 a_n417_n150# a_n225_n150# 0.16fF
+C9 a_n321_n150# a_n465_172# 0.10fF
+C10 a_255_n150# a_447_n150# 0.16fF
+C11 a_n33_n150# a_n465_172# 0.10fF
+C12 a_n417_n150# a_n509_n150# 0.43fF
+C13 a_447_n150# a_351_n150# 0.43fF
+C14 a_447_n150# a_63_n150# 0.07fF
+C15 a_n417_n150# a_n321_n150# 0.43fF
+C16 a_n225_n150# a_63_n150# 0.10fF
+C17 a_n417_n150# a_n33_n150# 0.07fF
+C18 a_n465_172# a_159_n150# 0.10fF
+C19 a_n129_n150# a_n225_n150# 0.43fF
+C20 a_255_n150# a_n33_n150# 0.10fF
+C21 a_n321_n150# a_63_n150# 0.07fF
+C22 a_351_n150# a_n33_n150# 0.07fF
+C23 a_n33_n150# a_63_n150# 0.43fF
+C24 a_n129_n150# a_n509_n150# 0.07fF
+C25 a_n321_n150# a_n129_n150# 0.16fF
+C26 a_n417_n150# a_n465_172# 0.10fF
+C27 a_255_n150# a_159_n150# 0.43fF
+C28 a_n129_n150# a_n33_n150# 0.43fF
+C29 a_351_n150# a_159_n150# 0.16fF
+C30 a_159_n150# a_63_n150# 0.43fF
+C31 a_255_n150# a_n465_172# 0.10fF
+C32 a_351_n150# a_n465_172# 0.10fF
+C33 a_n465_172# a_63_n150# 0.10fF
+C34 a_n129_n150# a_159_n150# 0.10fF
+C35 a_n129_n150# a_n465_172# 0.10fF
+C36 a_n225_n150# a_n509_n150# 0.10fF
+C37 a_255_n150# a_351_n150# 0.43fF
+C38 a_255_n150# a_63_n150# 0.16fF
+C39 a_n417_n150# a_n129_n150# 0.10fF
+C40 a_n321_n150# a_n225_n150# 0.43fF
+C41 a_351_n150# a_63_n150# 0.10fF
+C42 a_n225_n150# a_n33_n150# 0.16fF
+C43 a_255_n150# a_n129_n150# 0.07fF
+C44 a_n321_n150# a_n509_n150# 0.16fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n225_n150# a_n321_n150# 0.43fF
+C1 a_n417_n150# a_n33_n150# 0.07fF
+C2 a_n417_n150# w_n647_n369# 0.07fF
+C3 a_n33_n150# a_n321_n150# 0.10fF
+C4 w_n647_n369# a_n321_n150# 0.05fF
+C5 a_63_n150# a_n321_n150# 0.07fF
+C6 a_n129_n150# a_159_n150# 0.10fF
+C7 a_n129_n150# a_n225_n150# 0.43fF
+C8 a_n129_n150# a_255_n150# 0.07fF
+C9 a_n129_n150# a_n33_n150# 0.43fF
+C10 a_n225_n150# a_159_n150# 0.07fF
+C11 a_n129_n150# w_n647_n369# 0.02fF
+C12 a_255_n150# a_159_n150# 0.43fF
+C13 a_447_n150# a_351_n150# 0.43fF
+C14 a_63_n150# a_n129_n150# 0.16fF
+C15 a_n33_n150# a_159_n150# 0.16fF
+C16 w_n647_n369# a_159_n150# 0.04fF
+C17 a_n225_n150# a_n33_n150# 0.16fF
+C18 a_255_n150# a_n33_n150# 0.10fF
+C19 a_n225_n150# w_n647_n369# 0.04fF
+C20 a_n465_n247# a_n417_n150# 0.08fF
+C21 a_63_n150# a_159_n150# 0.43fF
+C22 a_255_n150# w_n647_n369# 0.05fF
+C23 a_63_n150# a_n225_n150# 0.10fF
+C24 a_63_n150# a_255_n150# 0.16fF
+C25 a_n417_n150# a_n509_n150# 0.43fF
+C26 w_n647_n369# a_n33_n150# 0.02fF
+C27 a_n465_n247# a_n321_n150# 0.08fF
+C28 a_63_n150# a_n33_n150# 0.43fF
+C29 a_63_n150# w_n647_n369# 0.02fF
+C30 a_n509_n150# a_n321_n150# 0.16fF
+C31 a_n129_n150# a_n465_n247# 0.08fF
+C32 a_n129_n150# a_n509_n150# 0.07fF
+C33 a_n465_n247# a_159_n150# 0.08fF
+C34 a_n465_n247# a_n225_n150# 0.08fF
+C35 a_255_n150# a_n465_n247# 0.08fF
+C36 a_159_n150# a_351_n150# 0.16fF
+C37 a_n509_n150# a_n225_n150# 0.10fF
+C38 a_n465_n247# a_n33_n150# 0.08fF
+C39 a_255_n150# a_351_n150# 0.43fF
+C40 a_n465_n247# w_n647_n369# 0.47fF
+C41 a_63_n150# a_n465_n247# 0.08fF
+C42 a_n33_n150# a_351_n150# 0.07fF
+C43 a_n509_n150# w_n647_n369# 0.14fF
+C44 w_n647_n369# a_351_n150# 0.07fF
+C45 a_63_n150# a_351_n150# 0.10fF
+C46 a_n417_n150# a_n321_n150# 0.43fF
+C47 a_447_n150# a_159_n150# 0.10fF
+C48 a_255_n150# a_447_n150# 0.16fF
+C49 a_n465_n247# a_351_n150# 0.08fF
+C50 a_n129_n150# a_n417_n150# 0.10fF
+C51 a_447_n150# w_n647_n369# 0.14fF
+C52 a_63_n150# a_447_n150# 0.07fF
+C53 a_n129_n150# a_n321_n150# 0.16fF
+C54 a_n417_n150# a_n225_n150# 0.16fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n73_n11# 0.15fF
+C1 a_n33_n99# a_n73_n11# 0.02fF
+C2 a_n33_n99# a_15_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_n78_n114# 0.20fF
+C1 a_n78_n114# a_20_n114# 0.42fF
+C2 w_n216_n334# a_20_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vdd 0.01fF
+C1 vdd vbulkp 0.04fF
+C2 in vss 0.01fF
+C3 in out 0.11fF
+C4 vbulkp out 0.08fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 vdd inverter_csvco_0/vdd 1.89fF
+C1 inverter_csvco_0/vss out 0.03fF
+C2 inverter_csvco_0/vss in 0.01fF
+C3 vdd cap_vco_0/t 0.04fF
+C4 inverter_csvco_0/vdd vbp 0.75fF
+C5 out D0 0.09fF
+C6 inverter_csvco_0/vss vctrl 0.87fF
+C7 inverter_csvco_0/vdd out 0.02fF
+C8 inverter_csvco_0/vdd in 0.01fF
+C9 inverter_csvco_0/vss D0 0.02fF
+C10 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C11 out in 0.06fF
+C12 out cap_vco_0/t 0.70fF
+C13 vdd vbp 1.21fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vdd vss csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C1 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C2 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
+C3 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C4 csvco_branch_2/vbp vctrl 0.06fF
+C5 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C6 D0 vctrl 4.41fF
+C7 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C8 csvco_branch_2/vbp vdd 1.49fF
+C9 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C10 out_vco csvco_branch_2/in 0.58fF
+C11 csvco_branch_1/cap_vco_0/t out_vco 0.03fF
+C12 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C13 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
+C14 out_vco csvco_branch_1/in 0.76fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 vdd out_pad 0.10fF
+C1 out_div out_pad 0.15fF
+C2 vdd out_div 0.17fF
+C3 vdd o1 0.09fF
+C4 out_div o1 0.11fF
+C5 in_vco vss 0.83fF
+C6 out_pad vss 0.70fF
+C7 out_div vss 3.00fF
+C8 vdd vss 14.54fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_355_368# a_194_125# 0.51fF
+C1 a_355_368# X 0.17fF
+C2 VPWR VPB 0.06fF
+C3 a_355_368# A 0.02fF
+C4 B a_194_125# 0.57fF
+C5 B X 0.13fF
+C6 VGND VPWR 0.01fF
+C7 B A 0.28fF
+C8 X a_194_125# 0.29fF
+C9 B VGND 0.10fF
+C10 A a_194_125# 0.18fF
+C11 a_355_368# VPWR 0.37fF
+C12 a_194_125# a_158_392# 0.06fF
+C13 VGND a_194_125# 0.25fF
+C14 VGND X 0.28fF
+C15 B VPWR 0.09fF
+C16 VGND A 0.31fF
+C17 B a_355_368# 0.08fF
+C18 VPWR a_194_125# 0.33fF
+C19 X VPWR 0.07fF
+C20 A VPWR 0.15fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 A B 0.08fF
+C1 X a_56_136# 0.26fF
+C2 VPB VPWR 0.04fF
+C3 VGND X 0.15fF
+C4 A VPWR 0.07fF
+C5 VPWR B 0.02fF
+C6 X B 0.02fF
+C7 VGND a_56_136# 0.06fF
+C8 A a_56_136# 0.17fF
+C9 VPWR X 0.20fF
+C10 VGND A 0.21fF
+C11 B a_56_136# 0.30fF
+C12 VGND B 0.03fF
+C13 VPWR a_56_136# 0.57fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 a_63_368# a_152_368# 0.03fF
+C1 a_63_368# X 0.33fF
+C2 X VPWR 0.18fF
+C3 a_63_368# A 0.28fF
+C4 A VPWR 0.05fF
+C5 VGND B 0.11fF
+C6 VGND X 0.16fF
+C7 VPB VPWR 0.04fF
+C8 B A 0.10fF
+C9 A X 0.02fF
+C10 a_63_368# VPWR 0.29fF
+C11 a_63_368# B 0.14fF
+C12 B VPWR 0.01fF
+C13 a_63_368# VGND 0.27fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
++ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
++ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
++ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C2 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C3 DFlipFlop_3/nQ CLK 0.01fF
+C4 Q1 DFlipFlop_2/D 0.10fF
+C5 nQ2 DFlipFlop_0/Q 0.09fF
+C6 nQ0 nQ2 0.03fF
+C7 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C8 nCLK DFlipFlop_1/D 0.14fF
+C9 Q1 nQ2 0.07fF
+C10 nQ0 DFlipFlop_1/latch_diff_0/D 0.09fF
+C11 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C12 vdd nQ0 0.11fF
+C13 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
+C14 Q1 DFlipFlop_3/latch_diff_1/D 0.79fF
+C15 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C16 DFlipFlop_1/latch_diff_1/m1_657_280# nQ0 0.21fF
+C17 vdd Q1 9.49fF
+C18 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C19 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C20 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C21 DFlipFlop_3/nQ Q1 0.10fF
+C22 CLK DFlipFlop_0/Q 0.08fF
+C23 CLK nQ0 0.19fF
+C24 DFlipFlop_2/D nCLK 0.41fF
+C25 CLK Q1 -0.10fF
+C26 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C27 nQ2 nCLK 0.10fF
+C28 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C29 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C30 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C31 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C32 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C33 nCLK DFlipFlop_3/latch_diff_1/D 0.14fF
+C34 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
+C35 vdd nCLK 0.34fF
+C36 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C37 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C38 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C39 DFlipFlop_3/nQ nCLK 0.02fF
+C40 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
+C41 nCLK sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.02fF
+C42 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C43 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C44 Q1 DFlipFlop_0/Q 0.13fF
+C45 nQ0 Q1 0.06fF
+C46 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C47 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C48 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C49 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C50 DFlipFlop_3/latch_diff_0/m1_657_280# Q1 0.28fF
+C51 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C52 DFlipFlop_2/latch_diff_1/m1_657_280# Q1 0.03fF
+C53 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C54 CLK_5 vdd 0.15fF
+C55 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C56 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
+C57 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
+C58 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C59 sky130_fd_sc_hs__and2_1_0/a_56_136# Q1 0.14fF
+C60 nCLK DFlipFlop_0/Q 0.11fF
+C61 nQ0 nCLK 0.09fF
+C62 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C63 Q1 nCLK -0.01fF
+C64 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C65 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C66 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C67 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C68 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C69 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C70 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C71 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q1 0.09fF
+C72 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C73 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C74 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C75 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C76 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C77 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C78 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C79 Q0 DFlipFlop_1/D 0.07fF
+C80 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C81 Q0 DFlipFlop_0/D 0.39fF
+C82 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C83 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
+C84 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C85 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C86 vdd Q1_shift 0.10fF
+C87 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C88 Q0 DFlipFlop_2/D 0.25fF
+C89 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
+C90 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C91 DFlipFlop_3/nQ Q1_shift 0.04fF
+C92 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
+C93 vdd DFlipFlop_2/nQ 0.02fF
+C94 Q0 nQ2 0.23fF
+C95 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C96 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
+C97 vdd Q0 5.33fF
+C98 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C99 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C100 CLK DFlipFlop_2/nQ 0.13fF
+C101 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C102 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C103 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q1 0.20fF
+C104 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
+C105 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C106 CLK Q0 0.08fF
+C107 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C108 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
+C109 Q1 Q1_shift 0.36fF
+C110 vdd DFlipFlop_1/D 0.25fF
+C111 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C112 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C113 vdd DFlipFlop_0/D 0.19fF
+C114 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C115 DFlipFlop_2/nQ Q1 0.31fF
+C116 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C117 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C118 Q0 DFlipFlop_0/Q 0.21fF
+C119 CLK DFlipFlop_1/D 0.21fF
+C120 Q0 nQ0 0.33fF
+C121 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C122 Q0 Q1 9.65fF
+C123 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C124 vdd DFlipFlop_2/D 0.07fF
+C125 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C126 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C127 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C128 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
+C129 vdd nQ2 0.04fF
+C130 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C131 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C132 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.08fF
+C133 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C134 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C135 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C136 CLK DFlipFlop_2/D 0.14fF
+C137 DFlipFlop_2/nQ nCLK 0.09fF
+C138 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C139 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C140 nQ0 DFlipFlop_1/D 0.12fF
+C141 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C142 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
+C143 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C144 CLK nQ2 0.17fF
+C145 Q1 DFlipFlop_1/D 0.03fF
+C146 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C147 DFlipFlop_3/nQ vdd 0.02fF
+C148 Q0 nCLK 0.20fF
+C149 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C150 DFlipFlop_0/D Q1 0.13fF
+C151 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C152 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C153 vdd CLK 0.41fF
+C154 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C155 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C156 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 DFlipFlop_2/nQ vss 0.50fF
+C172 Q1 vss 8.55fF
+C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 nQ0 vss 3.42fF
+C183 Q0 vss 0.53fF
+C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n63_n151# a_33_n151# 0.02fF
+C1 a_159_n125# a_255_n125# 0.36fF
+C2 a_n317_n125# a_63_n125# 0.06fF
+C3 a_n129_n125# a_n225_n125# 0.36fF
+C4 a_63_n125# a_159_n125# 0.36fF
+C5 a_n317_n125# a_n33_n125# 0.08fF
+C6 a_63_n125# a_255_n125# 0.13fF
+C7 a_n33_n125# a_159_n125# 0.13fF
+C8 a_n33_n125# a_255_n125# 0.08fF
+C9 a_63_n125# a_n33_n125# 0.36fF
+C10 a_n63_n151# a_n159_n151# 0.02fF
+C11 a_n255_n151# a_n159_n151# 0.02fF
+C12 a_129_n151# a_33_n151# 0.02fF
+C13 a_n317_n125# a_n129_n125# 0.13fF
+C14 a_n129_n125# a_159_n125# 0.08fF
+C15 a_225_n151# a_129_n151# 0.02fF
+C16 a_n129_n125# a_255_n125# 0.06fF
+C17 a_63_n125# a_n129_n125# 0.13fF
+C18 a_n129_n125# a_n33_n125# 0.36fF
+C19 a_n317_n125# a_n225_n125# 0.36fF
+C20 a_n225_n125# a_159_n125# 0.06fF
+C21 a_63_n125# a_n225_n125# 0.08fF
+C22 a_n33_n125# a_n225_n125# 0.13fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n225_n125# a_n33_n125# 0.13fF
+C1 a_63_n125# a_159_n125# 0.36fF
+C2 a_n129_n125# a_n317_n125# 0.13fF
+C3 a_n225_n125# a_63_n125# 0.08fF
+C4 a_n129_n125# a_n33_n125# 0.36fF
+C5 a_n63_n154# a_33_n154# 0.02fF
+C6 a_129_n154# a_33_n154# 0.02fF
+C7 a_n225_n125# a_159_n125# 0.06fF
+C8 a_n159_n154# a_n63_n154# 0.02fF
+C9 a_n129_n125# a_63_n125# 0.13fF
+C10 a_129_n154# a_225_n154# 0.02fF
+C11 a_255_n125# a_n33_n125# 0.08fF
+C12 a_n129_n125# a_159_n125# 0.08fF
+C13 a_n159_n154# a_n255_n154# 0.02fF
+C14 w_n455_n344# a_n317_n125# 0.11fF
+C15 w_n455_n344# a_n33_n125# 0.05fF
+C16 a_n129_n125# a_n225_n125# 0.36fF
+C17 a_255_n125# a_63_n125# 0.13fF
+C18 w_n455_n344# a_63_n125# 0.04fF
+C19 a_255_n125# a_159_n125# 0.36fF
+C20 w_n455_n344# a_159_n125# 0.06fF
+C21 w_n455_n344# a_n225_n125# 0.06fF
+C22 a_n317_n125# a_n33_n125# 0.08fF
+C23 a_n129_n125# a_255_n125# 0.06fF
+C24 a_n129_n125# w_n455_n344# 0.04fF
+C25 a_n317_n125# a_63_n125# 0.06fF
+C26 a_63_n125# a_n33_n125# 0.36fF
+C27 a_n33_n125# a_159_n125# 0.13fF
+C28 a_255_n125# w_n455_n344# 0.11fF
+C29 a_n317_n125# a_n225_n125# 0.36fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 vdd in 0.04fF
+C1 vdd out 0.29fF
+C2 in out 0.85fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 vdd QB 0.02fF
+C1 vdd Down 0.09fF
+C2 nUp Up 0.20fF
+C3 vdd inverter_cp_x1_2/in 0.42fF
+C4 inverter_cp_x1_0/out nDown 0.11fF
+C5 vdd nUp 0.14fF
+C6 nDown Down 0.23fF
+C7 vdd Up 0.60fF
+C8 vdd nDown 0.80fF
+C9 inverter_cp_x1_2/in Up 0.12fF
+C10 inverter_cp_x1_0/out Down 0.12fF
+C11 vdd inverter_cp_x1_0/out 0.25fF
+C12 vdd QA 0.02fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n129_n90# a_63_n90# 0.09fF
+C1 a_n221_n90# a_63_n90# 0.06fF
+C2 w_n359_n309# a_n129_n90# 0.06fF
+C3 a_n221_n90# w_n359_n309# 0.09fF
+C4 a_63_n90# a_159_n90# 0.26fF
+C5 w_n359_n309# a_159_n90# 0.09fF
+C6 w_n359_n309# a_63_n90# 0.06fF
+C7 a_n129_n90# a_n33_n90# 0.26fF
+C8 a_n221_n90# a_n33_n90# 0.09fF
+C9 a_n33_n90# a_159_n90# 0.09fF
+C10 a_n33_n90# a_63_n90# 0.26fF
+C11 a_n221_n90# a_n129_n90# 0.26fF
+C12 w_n359_n309# a_n33_n90# 0.05fF
+C13 a_n129_n90# a_159_n90# 0.06fF
+C14 a_n63_n116# a_n159_n207# 0.12fF
+C15 a_n221_n90# a_159_n90# 0.04fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n33_n45# 0.13fF
+C1 a_n125_n45# a_n33_n45# 0.13fF
+C2 a_63_n45# a_n125_n45# 0.05fF
+C3 a_n129_71# a_33_n71# 0.04fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
+C1 A out 0.06fF
+C2 vdd out 0.11fF
+C3 B out 0.40fF
+C4 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out 0.08fF
+C5 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C6 vdd A 0.09fF
+C7 B A 0.24fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C1 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C2 vdd nor_pfd_2/A -0.01fF
+C3 nor_pfd_2/B Reset 0.43fF
+C4 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C5 Reset Q 0.14fF
+C6 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C7 nor_pfd_2/B nor_pfd_3/A 0.58fF
+C8 nor_pfd_3/A Q 0.98fF
+C9 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C10 vdd nor_pfd_2/B 0.02fF
+C11 vdd Q 0.08fF
+C12 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C13 Q nor_pfd_2/A 1.38fF
+C14 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C15 CLK Q 0.04fF
+C16 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C17 Reset nor_pfd_3/A 0.12fF
+C18 nor_pfd_2/B Q 2.22fF
+C19 vdd nor_pfd_3/A 0.09fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_n45# a_159_n45# 0.03fF
+C1 a_n221_n45# a_159_n45# 0.02fF
+C2 a_63_n45# a_159_n45# 0.13fF
+C3 a_n221_n45# a_n129_n45# 0.13fF
+C4 a_n33_n45# a_159_n45# 0.05fF
+C5 a_63_n45# a_n129_n45# 0.05fF
+C6 a_n63_n71# a_n159_n173# 0.10fF
+C7 a_n33_n45# a_n129_n45# 0.13fF
+C8 a_63_n45# a_n221_n45# 0.03fF
+C9 a_n221_n45# a_n33_n45# 0.05fF
+C10 a_63_n45# a_n33_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n125_n90# a_63_n90# 0.09fF
+C1 a_n33_n90# a_63_n90# 0.26fF
+C2 a_33_n187# a_n99_n187# 0.04fF
+C3 a_n125_n90# a_n33_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_15_n45# a_n73_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n73_n90# w_n211_n309# 0.04fF
+C1 a_15_n90# w_n211_n309# 0.09fF
+C2 a_15_n90# a_n73_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 A vdd 0.05fF
+C1 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C2 out sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.03fF
+C3 B a_656_410# 0.30fF
+C4 out a_656_410# 0.20fF
+C5 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C6 B A 0.33fF
+C7 a_656_410# A 0.04fF
+C8 a_656_410# vdd 0.20fF
+C9 out vdd 0.10fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 Down Up 0.06fF
+C1 vdd Up 1.62fF
+C2 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
+C3 vdd Reset 0.02fF
+C4 dff_pfd_1/nor_pfd_2/B vdd 0.04fF
+C5 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C6 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C7 Down vdd 0.08fF
+C8 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
+C9 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v1_pex_c iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
++ pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
++ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
++ n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 nswitch vdd nUp vss Down biasp vco_vctrl pswitch iref_cp nDown Up charge_pump
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vss
++ vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C1 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C3 n_out_by_2 vco_vctrl 0.52fF
+C4 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
+C5 vco_vctrl nswitch -0.06fF
+C6 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
+C7 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C8 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C9 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
+C10 biasp nUp -0.17fF
+C11 QA vdd -0.04fF
+C12 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
+C13 out_by_2 div_5_nQ0 0.32fF
+C14 out_div_by_5 div_5_Q1 0.01fF
+C15 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C16 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C17 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
+C18 div_5_Q0 vco_vctrl 0.48fF
+C19 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
+C20 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C21 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C22 div_5_Q0 out_by_2 0.09fF
+C23 buffer_salida_0/a_678_n100# vdd 0.24fF
+C24 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C25 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C26 div_by_5_0/DFlipFlop_2/latch_diff_0/D n_out_by_2 0.12fF
+C27 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C28 n_out_by_2 div_5_Q1 1.04fF
+C29 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# n_out_by_2 -0.05fF
+C30 lf_vc vdd 0.02fF
+C31 biasp Down 1.24fF
+C32 nUp vdd 0.05fF
+C33 iref_cp vdd 0.15fF
+C34 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C35 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
+C36 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
+C37 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C38 pswitch nUp 0.85fF
+C39 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C40 buffer_salida_0/a_678_n100# out_to_buffer 0.22fF
+C41 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
+C42 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
+C43 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
+C44 out_by_2 vco_vctrl 0.53fF
+C45 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C46 out_div_by_5 vdd 0.28fF
+C47 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
+C48 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C49 Down iref_cp 0.09fF
+C50 div_5_nQ2 n_out_by_2 0.10fF
+C51 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C52 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C53 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C54 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C55 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
+C56 n_out_by_2 vdd 1.03fF
+C57 biasp nDown 0.26fF
+C58 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
+C59 vco_vctrl div_5_Q1 0.14fF
+C60 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C61 vdd out_to_buffer 0.07fF
+C62 biasp Up 0.26fF
+C63 out_to_div vdd 0.21fF
+C64 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C65 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C66 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C67 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
+C68 out_by_2 div_5_Q1 0.42fF
+C69 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C70 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C71 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
+C72 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
+C73 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C74 vco_D0 vdd 0.03fF
+C75 nUp nDown -0.09fF
+C76 Down nswitch 0.54fF
+C77 Up nUp 2.72fF
+C78 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C79 div_5_nQ0 n_out_by_2 0.10fF
+C80 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C81 div_by_5_0/DFlipFlop_2/latch_diff_1/nD n_out_by_2 0.24fF
+C82 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C83 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
+C84 out_to_div out_to_buffer 0.13fF
+C85 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 0.27fF
+C86 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C87 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
+C88 nUp vco_vctrl 0.02fF
+C89 nDown vdd 0.22fF
+C90 div_by_5_0/DFlipFlop_2/latch_diff_1/D n_out_by_2 0.10fF
+C91 out_by_2 div_5_nQ2 0.16fF
+C92 Up vdd 0.28fF
+C93 div_5_Q0 n_out_by_2 -0.12fF
+C94 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C95 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
+C96 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
+C97 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C98 pswitch nDown 0.53fF
+C99 vco_vctrl vdd -1.02fF
+C100 pswitch Up 1.98fF
+C101 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C102 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C103 Down nDown 2.55fF
+C104 out_by_2 vdd 0.97fF
+C105 div_5_Q1_shift out_div_by_5 0.05fF
+C106 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C107 nDown nswitch 0.76fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.93fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss 1.39fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.76fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 6.05fF
+C141 Up vss 2.16fF
+C142 Down vss 6.16fF
+C143 nDown vss 3.38fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C158 div_5_Q1 vss 4.28fF
+C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_nQ0 vss 0.59fF
+C169 div_5_Q0 vss 0.01fF
+C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_to_buffer vss 1.57fF
+C196 out_to_div vss 4.46fF
+C197 out_first_buffer vss 2.88fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 vco_D0 vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 n_out_buffer_div_2 vss 1.63fF
+C216 out_buffer_div_2 vss 1.60fF
+C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 nswitch vss 3.73fF
+C232 biasp vss 5.44fF
+C233 iref_cp vss 2.81fF
+C234 vco_vctrl vss -19.28fF
+C235 pswitch vss 3.57fF
+C236 lf_vc vss -59.89fF
+C237 loop_filter_0/res_loop_filter_2/out vss 7.90fF
+.ends
+
diff --git a/mag/extractions/top_pll_v1_pex_rc.spice b/mag/extractions/top_pll_v1_pex_rc.spice
new file mode 100644
index 0000000..2042783
--- /dev/null
+++ b/mag/extractions/top_pll_v1_pex_rc.spice
@@ -0,0 +1,2875 @@
+* NGSPICE file created from top_pll_v1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C1 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C2 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C3 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C4 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C5 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C6 m3_2669_n13200# m3_7988_n13200# 2.73fF
+C7 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C8 m3_2669_8000# m3_7988_8000# 2.73fF
+C9 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
+C10 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C11 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C12 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C13 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C14 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
+C15 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C16 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C17 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C18 m3_2669_2700# m3_2669_n2600# 3.28fF
+C19 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C20 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C21 m3_7988_2700# m3_7988_8000# 3.39fF
+C22 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C23 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C24 m3_2669_n2600# c1_n13188_n13100# 58.86fF
+C25 m3_2669_8000# m3_n2650_8000# 2.73fF
+C26 m3_n2650_2700# m3_2669_2700# 2.73fF
+C27 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C28 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C29 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C30 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C31 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C32 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C33 m3_n13288_2700# c1_n13188_n13100# 58.61fF
+C34 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C35 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C36 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C37 m3_7988_2700# m3_7988_n2600# 3.39fF
+C38 m3_7988_n13200# m3_7988_n7900# 3.39fF
+C39 m3_n7969_2700# c1_n13188_n13100# 58.86fF
+C40 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C41 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C42 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C43 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C44 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C45 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C46 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C47 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C48 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C49 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C50 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C51 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C52 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C53 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C54 m3_2669_8000# m3_2669_2700# 3.28fF
+C55 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C56 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C57 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C58 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C59 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C60 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C61 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C62 m3_2669_8000# c1_n13188_n13100# 58.61fF
+C63 m3_7988_2700# m3_2669_2700# 2.73fF
+C64 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C1 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C2 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C3 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C4 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C5 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C6 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C7 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C8 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C9 c1_n6369_n6300# m3_n6469_2200# 38.10fF
+C10 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C11 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C12 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C13 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C14 m3_n2150_2200# m3_n6469_2200# 1.75fF
+C15 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C16 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C17 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C18 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 vc_pex vss -38.13fF
+C2 res_loop_filter_2/out vss 8.49fF
+C3 in vss -18.79fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_n1861_n486# w_n2457_n634# 0.02fF
+C1 a_n2319_n486# w_n2457_n634# 0.02fF
+C2 w_n2457_n634# a_1803_n486# 0.02fF
+C3 a_n1403_n486# w_n2457_n634# 0.02fF
+C4 w_n2457_n634# a_n29_n486# 0.02fF
+C5 w_n2457_n634# a_887_n486# 0.02fF
+C6 a_2261_n486# w_n2457_n634# 0.02fF
+C7 w_n2457_n634# a_n945_n486# 0.02fF
+C8 a_n487_n486# w_n2457_n634# 0.02fF
+C9 w_n2457_n634# a_1345_n486# 0.02fF
+C10 w_n2457_n634# a_429_n486# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n561_n75# a_n657_n75# 0.22fF
+C1 a_n561_n75# a_n177_n75# 0.03fF
+C2 a_399_n75# a_111_n75# 0.05fF
+C3 a_783_n75# a_879_n75# 0.22fF
+C4 a_111_n75# a_495_n75# 0.03fF
+C5 a_687_n75# a_879_n75# 0.08fF
+C6 a_n849_n75# a_n753_n75# 0.22fF
+C7 a_111_n75# a_15_n75# 0.22fF
+C8 a_207_n75# a_399_n75# 0.08fF
+C9 a_n849_n75# a_n1041_n75# 0.08fF
+C10 a_207_n75# a_495_n75# 0.05fF
+C11 a_1071_n75# a_975_n75# 0.22fF
+C12 a_207_n75# a_15_n75# 0.08fF
+C13 a_n561_n75# a_n849_n75# 0.05fF
+C14 a_n945_n75# a_n753_n75# 0.08fF
+C15 a_n657_n75# a_n849_n75# 0.08fF
+C16 a_n273_n75# a_111_n75# 0.03fF
+C17 a_n1229_n75# a_n1041_n75# 0.08fF
+C18 a_n945_n75# a_n1041_n75# 0.22fF
+C19 a_399_n75# a_495_n75# 0.22fF
+C20 a_975_n75# a_591_n75# 0.03fF
+C21 a_1167_n75# a_975_n75# 0.08fF
+C22 a_n369_n75# a_n465_n75# 0.22fF
+C23 a_207_n75# a_591_n75# 0.03fF
+C24 a_399_n75# a_15_n75# 0.03fF
+C25 a_n81_n75# a_111_n75# 0.08fF
+C26 a_n1137_n75# a_n753_n75# 0.03fF
+C27 a_n369_n75# a_15_n75# 0.03fF
+C28 a_n561_n75# a_n945_n75# 0.03fF
+C29 a_783_n75# a_975_n75# 0.08fF
+C30 a_n1137_n75# a_n1041_n75# 0.22fF
+C31 a_975_n75# a_687_n75# 0.05fF
+C32 a_207_n75# a_n81_n75# 0.05fF
+C33 a_n945_n75# a_n657_n75# 0.05fF
+C34 a_n177_n75# a_111_n75# 0.05fF
+C35 a_303_n75# a_111_n75# 0.08fF
+C36 a_399_n75# a_591_n75# 0.08fF
+C37 a_n273_n75# a_n465_n75# 0.08fF
+C38 a_n465_n75# a_n753_n75# 0.05fF
+C39 a_591_n75# a_495_n75# 0.22fF
+C40 a_1167_n75# a_1071_n75# 0.22fF
+C41 a_207_n75# a_n177_n75# 0.03fF
+C42 a_207_n75# a_303_n75# 0.22fF
+C43 a_n369_n75# a_n273_n75# 0.22fF
+C44 a_n369_n75# a_n753_n75# 0.03fF
+C45 a_n273_n75# a_15_n75# 0.05fF
+C46 a_783_n75# a_399_n75# 0.03fF
+C47 a_n81_n75# a_n465_n75# 0.03fF
+C48 a_399_n75# a_687_n75# 0.05fF
+C49 a_975_n75# a_879_n75# 0.22fF
+C50 a_783_n75# a_495_n75# 0.05fF
+C51 a_n849_n75# a_n1229_n75# 0.03fF
+C52 a_687_n75# a_495_n75# 0.08fF
+C53 a_n945_n75# a_n849_n75# 0.22fF
+C54 a_n561_n75# a_n465_n75# 0.22fF
+C55 a_783_n75# a_1071_n75# 0.05fF
+C56 a_1071_n75# a_687_n75# 0.03fF
+C57 a_n369_n75# a_n81_n75# 0.05fF
+C58 a_n81_n75# a_15_n75# 0.22fF
+C59 a_n561_n75# a_n369_n75# 0.08fF
+C60 a_n657_n75# a_n465_n75# 0.08fF
+C61 a_n177_n75# a_n465_n75# 0.05fF
+C62 a_303_n75# a_399_n75# 0.22fF
+C63 a_303_n75# a_495_n75# 0.08fF
+C64 a_n369_n75# a_n657_n75# 0.05fF
+C65 a_n1137_n75# a_n849_n75# 0.05fF
+C66 a_n369_n75# a_n177_n75# 0.08fF
+C67 a_n177_n75# a_15_n75# 0.08fF
+C68 a_303_n75# a_15_n75# 0.05fF
+C69 a_n753_n75# a_n1041_n75# 0.05fF
+C70 a_n945_n75# a_n1229_n75# 0.05fF
+C71 a_783_n75# a_591_n75# 0.08fF
+C72 a_879_n75# a_495_n75# 0.03fF
+C73 a_687_n75# a_591_n75# 0.22fF
+C74 a_1167_n75# a_783_n75# 0.03fF
+C75 a_n273_n75# a_n81_n75# 0.08fF
+C76 a_1071_n75# a_879_n75# 0.08fF
+C77 a_n561_n75# a_n273_n75# 0.05fF
+C78 a_n561_n75# a_n753_n75# 0.08fF
+C79 a_n465_n75# a_n849_n75# 0.03fF
+C80 a_n1137_n75# a_n1229_n75# 0.22fF
+C81 a_783_n75# a_687_n75# 0.22fF
+C82 a_303_n75# a_591_n75# 0.05fF
+C83 a_207_n75# a_111_n75# 0.22fF
+C84 a_n273_n75# a_n657_n75# 0.03fF
+C85 a_n945_n75# a_n1137_n75# 0.08fF
+C86 a_n273_n75# a_n177_n75# 0.22fF
+C87 a_n657_n75# a_n753_n75# 0.22fF
+C88 a_n657_n75# a_n1041_n75# 0.03fF
+C89 a_879_n75# a_591_n75# 0.05fF
+C90 a_1167_n75# a_879_n75# 0.05fF
+C91 a_303_n75# a_687_n75# 0.03fF
+C92 a_n81_n75# a_n177_n75# 0.22fF
+C93 a_303_n75# a_n81_n75# 0.03fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_927_n75# a_639_n75# 0.05fF
+C1 a_543_n75# a_447_n75# 0.22fF
+C2 a_543_n75# a_159_n75# 0.03fF
+C3 a_n33_n75# a_n321_n75# 0.05fF
+C4 a_n927_n101# a_33_n101# 0.08fF
+C5 a_n321_n75# a_63_n75# 0.03fF
+C6 a_735_n75# a_927_n75# 0.08fF
+C7 a_255_n75# a_351_n75# 0.22fF
+C8 a_n705_n75# a_n321_n75# 0.03fF
+C9 a_159_n75# a_447_n75# 0.05fF
+C10 a_n129_n75# a_159_n75# 0.05fF
+C11 a_n321_n75# a_n417_n75# 0.22fF
+C12 a_n225_n75# a_n33_n75# 0.08fF
+C13 a_n705_n75# a_n989_n75# 0.05fF
+C14 a_n225_n75# a_63_n75# 0.05fF
+C15 a_n897_n75# a_n989_n75# 0.22fF
+C16 a_n225_n75# a_n417_n75# 0.08fF
+C17 a_543_n75# a_255_n75# 0.05fF
+C18 a_831_n75# a_927_n75# 0.22fF
+C19 a_n321_n75# a_n609_n75# 0.05fF
+C20 a_447_n75# a_255_n75# 0.08fF
+C21 a_159_n75# a_255_n75# 0.22fF
+C22 a_n129_n75# a_255_n75# 0.03fF
+C23 a_n33_n75# a_63_n75# 0.22fF
+C24 a_n989_n75# a_n609_n75# 0.03fF
+C25 a_n801_n75# a_n989_n75# 0.08fF
+C26 a_735_n75# a_639_n75# 0.22fF
+C27 a_n225_n75# a_n609_n75# 0.03fF
+C28 a_n33_n75# a_n417_n75# 0.03fF
+C29 a_n897_n75# a_n705_n75# 0.08fF
+C30 a_n705_n75# a_n417_n75# 0.05fF
+C31 a_n513_n75# a_n321_n75# 0.08fF
+C32 a_543_n75# a_927_n75# 0.03fF
+C33 a_n225_n75# a_n513_n75# 0.05fF
+C34 a_n129_n75# a_n321_n75# 0.08fF
+C35 a_831_n75# a_639_n75# 0.08fF
+C36 a_639_n75# a_351_n75# 0.05fF
+C37 a_n33_n75# a_351_n75# 0.03fF
+C38 a_n705_n75# a_n609_n75# 0.22fF
+C39 a_63_n75# a_351_n75# 0.05fF
+C40 a_n897_n75# a_n609_n75# 0.05fF
+C41 a_n801_n75# a_n705_n75# 0.22fF
+C42 a_n801_n75# a_n897_n75# 0.22fF
+C43 a_n609_n75# a_n417_n75# 0.08fF
+C44 a_n225_n75# a_159_n75# 0.03fF
+C45 a_n225_n75# a_n129_n75# 0.22fF
+C46 a_735_n75# a_831_n75# 0.22fF
+C47 a_n801_n75# a_n417_n75# 0.03fF
+C48 a_735_n75# a_351_n75# 0.03fF
+C49 a_543_n75# a_639_n75# 0.22fF
+C50 a_n705_n75# a_n513_n75# 0.08fF
+C51 a_n897_n75# a_n513_n75# 0.03fF
+C52 a_n513_n75# a_n417_n75# 0.22fF
+C53 a_543_n75# a_735_n75# 0.08fF
+C54 a_447_n75# a_639_n75# 0.08fF
+C55 a_n801_n75# a_n609_n75# 0.08fF
+C56 a_n33_n75# a_159_n75# 0.08fF
+C57 a_n129_n75# a_n33_n75# 0.22fF
+C58 a_447_n75# a_63_n75# 0.03fF
+C59 a_159_n75# a_63_n75# 0.22fF
+C60 a_n129_n75# a_63_n75# 0.08fF
+C61 a_735_n75# a_447_n75# 0.05fF
+C62 a_n129_n75# a_n417_n75# 0.05fF
+C63 a_n513_n75# a_n609_n75# 0.22fF
+C64 a_n801_n75# a_n513_n75# 0.05fF
+C65 a_543_n75# a_831_n75# 0.05fF
+C66 a_543_n75# a_351_n75# 0.08fF
+C67 a_639_n75# a_255_n75# 0.03fF
+C68 a_n33_n75# a_255_n75# 0.05fF
+C69 a_255_n75# a_63_n75# 0.08fF
+C70 a_n225_n75# a_n321_n75# 0.22fF
+C71 a_831_n75# a_447_n75# 0.03fF
+C72 a_447_n75# a_351_n75# 0.22fF
+C73 a_159_n75# a_351_n75# 0.08fF
+C74 a_n129_n75# a_n513_n75# 0.03fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n609_n150# a_n989_n150# 0.07fF
+C1 a_n129_n150# a_n225_n150# 0.43fF
+C2 a_n129_n150# a_n513_n150# 0.07fF
+C3 a_n705_n150# a_n989_n150# 0.10fF
+C4 a_n417_n150# a_n321_n150# 0.43fF
+C5 a_159_n150# a_543_n150# 0.07fF
+C6 a_n513_n150# a_n225_n150# 0.10fF
+C7 a_543_n150# a_447_n150# 0.43fF
+C8 a_n417_n150# a_n801_n150# 0.07fF
+C9 a_n897_n150# a_n609_n150# 0.10fF
+C10 a_639_n150# a_447_n150# 0.16fF
+C11 a_n705_n150# a_n897_n150# 0.16fF
+C12 a_n129_n150# a_n417_n150# 0.10fF
+C13 a_543_n150# a_255_n150# 0.10fF
+C14 a_63_n150# a_n33_n150# 0.43fF
+C15 a_831_n150# a_543_n150# 0.10fF
+C16 a_n225_n150# a_n417_n150# 0.16fF
+C17 a_n513_n150# a_n417_n150# 0.43fF
+C18 a_n989_n150# a_n801_n150# 0.16fF
+C19 a_159_n150# a_n33_n150# 0.16fF
+C20 a_159_n150# a_63_n150# 0.43fF
+C21 a_639_n150# a_255_n150# 0.07fF
+C22 a_63_n150# a_447_n150# 0.07fF
+C23 a_831_n150# a_639_n150# 0.16fF
+C24 a_n705_n150# a_n609_n150# 0.43fF
+C25 a_159_n150# a_447_n150# 0.10fF
+C26 a_927_n150# a_543_n150# 0.07fF
+C27 a_351_n150# a_543_n150# 0.16fF
+C28 a_n897_n150# a_n801_n150# 0.43fF
+C29 a_639_n150# a_927_n150# 0.10fF
+C30 a_639_n150# a_351_n150# 0.10fF
+C31 a_n33_n150# a_255_n150# 0.10fF
+C32 a_735_n150# a_543_n150# 0.16fF
+C33 a_63_n150# a_255_n150# 0.16fF
+C34 a_n33_n150# a_n321_n150# 0.10fF
+C35 a_63_n150# a_n321_n150# 0.07fF
+C36 a_159_n150# a_255_n150# 0.43fF
+C37 a_n927_n247# a_33_n247# 0.09fF
+C38 a_n609_n150# a_n321_n150# 0.10fF
+C39 a_255_n150# a_447_n150# 0.16fF
+C40 a_639_n150# a_735_n150# 0.43fF
+C41 a_831_n150# a_447_n150# 0.07fF
+C42 a_n705_n150# a_n321_n150# 0.07fF
+C43 a_n609_n150# a_n801_n150# 0.16fF
+C44 a_n897_n150# a_n513_n150# 0.07fF
+C45 a_351_n150# a_n33_n150# 0.07fF
+C46 a_n705_n150# a_n801_n150# 0.43fF
+C47 a_63_n150# a_351_n150# 0.10fF
+C48 a_n129_n150# a_n33_n150# 0.43fF
+C49 a_159_n150# a_351_n150# 0.16fF
+C50 a_n129_n150# a_63_n150# 0.16fF
+C51 a_351_n150# a_447_n150# 0.43fF
+C52 a_n129_n150# a_159_n150# 0.10fF
+C53 a_n225_n150# a_n33_n150# 0.16fF
+C54 a_63_n150# a_n225_n150# 0.10fF
+C55 a_n225_n150# a_n609_n150# 0.07fF
+C56 a_n513_n150# a_n609_n150# 0.43fF
+C57 a_159_n150# a_n225_n150# 0.07fF
+C58 a_n705_n150# a_n513_n150# 0.16fF
+C59 a_735_n150# a_447_n150# 0.10fF
+C60 a_351_n150# a_255_n150# 0.43fF
+C61 a_831_n150# a_927_n150# 0.43fF
+C62 a_n129_n150# a_255_n150# 0.07fF
+C63 a_n129_n150# a_n321_n150# 0.16fF
+C64 a_n33_n150# a_n417_n150# 0.07fF
+C65 a_n417_n150# a_n609_n150# 0.16fF
+C66 a_n897_n150# a_n989_n150# 0.43fF
+C67 a_639_n150# a_543_n150# 0.43fF
+C68 a_831_n150# a_735_n150# 0.43fF
+C69 a_n705_n150# a_n417_n150# 0.10fF
+C70 a_n225_n150# a_n321_n150# 0.43fF
+C71 a_n513_n150# a_n321_n150# 0.16fF
+C72 a_n513_n150# a_n801_n150# 0.10fF
+C73 a_735_n150# a_927_n150# 0.16fF
+C74 a_735_n150# a_351_n150# 0.07fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n1461_n44# a_n1103_n44# 0.04fF
+C1 a_n29_n44# a_329_n44# 0.04fF
+C2 a_n387_n44# a_n745_n44# 0.04fF
+C3 a_n29_n44# a_n387_n44# 0.04fF
+C4 a_687_n44# a_329_n44# 0.04fF
+C5 a_1045_n44# a_687_n44# 0.04fF
+C6 a_1045_n44# a_1403_n44# 0.04fF
+C7 a_n745_n44# a_n1103_n44# 0.04fF
+C8 a_1761_n44# a_1403_n44# 0.04fF
+C9 a_n1461_n44# a_n1819_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_783_n150# a_399_n150# 0.07fF
+C1 a_111_n150# a_495_n150# 0.07fF
+C2 a_n849_n150# a_n465_n150# 0.07fF
+C3 a_1071_n150# a_1167_n150# 0.43fF
+C4 a_n945_n150# a_n561_n150# 0.07fF
+C5 a_15_n150# a_303_n150# 0.10fF
+C6 a_975_n150# a_1167_n150# 0.16fF
+C7 a_n369_n150# a_n273_n150# 0.43fF
+C8 a_n465_n150# a_n177_n150# 0.10fF
+C9 a_n657_n150# a_n945_n150# 0.10fF
+C10 a_n945_n150# a_n1041_n150# 0.43fF
+C11 a_n369_n150# a_n753_n150# 0.07fF
+C12 a_111_n150# a_15_n150# 0.43fF
+C13 a_783_n150# a_1167_n150# 0.07fF
+C14 a_15_n150# a_n81_n150# 0.43fF
+C15 a_879_n150# a_591_n150# 0.10fF
+C16 a_207_n150# a_591_n150# 0.07fF
+C17 a_207_n150# a_303_n150# 0.43fF
+C18 a_n945_n150# a_n1229_n150# 0.10fF
+C19 a_n177_n150# a_n369_n150# 0.16fF
+C20 a_n465_n150# a_n369_n150# 0.43fF
+C21 a_879_n150# a_687_n150# 0.16fF
+C22 a_n945_n150# a_n753_n150# 0.16fF
+C23 a_975_n150# a_591_n150# 0.07fF
+C24 a_n657_n150# a_n561_n150# 0.43fF
+C25 a_111_n150# a_207_n150# 0.43fF
+C26 a_111_n150# a_n273_n150# 0.07fF
+C27 a_399_n150# a_591_n150# 0.16fF
+C28 a_207_n150# a_n81_n150# 0.10fF
+C29 a_303_n150# a_399_n150# 0.43fF
+C30 a_n1137_n150# a_n945_n150# 0.16fF
+C31 a_n81_n150# a_n273_n150# 0.16fF
+C32 a_n657_n150# a_n1041_n150# 0.07fF
+C33 a_879_n150# a_495_n150# 0.07fF
+C34 a_207_n150# a_495_n150# 0.10fF
+C35 a_1071_n150# a_687_n150# 0.07fF
+C36 a_n849_n150# a_n945_n150# 0.43fF
+C37 a_687_n150# a_975_n150# 0.10fF
+C38 a_687_n150# a_399_n150# 0.10fF
+C39 a_783_n150# a_591_n150# 0.16fF
+C40 a_111_n150# a_399_n150# 0.10fF
+C41 a_879_n150# w_n1367_n369# 0.04fF
+C42 a_399_n150# a_495_n150# 0.43fF
+C43 a_783_n150# a_687_n150# 0.43fF
+C44 a_n561_n150# a_n273_n150# 0.10fF
+C45 a_111_n150# a_n177_n150# 0.10fF
+C46 a_n1229_n150# a_n1041_n150# 0.16fF
+C47 a_15_n150# a_207_n150# 0.16fF
+C48 a_15_n150# a_n273_n150# 0.10fF
+C49 a_n657_n150# a_n273_n150# 0.07fF
+C50 a_n81_n150# a_n177_n150# 0.43fF
+C51 a_n561_n150# a_n753_n150# 0.16fF
+C52 a_n81_n150# a_n465_n150# 0.07fF
+C53 a_1071_n150# w_n1367_n369# 0.07fF
+C54 a_n657_n150# a_n753_n150# 0.43fF
+C55 w_n1367_n369# a_975_n150# 0.05fF
+C56 a_n1041_n150# a_n753_n150# 0.10fF
+C57 a_783_n150# a_495_n150# 0.10fF
+C58 a_n1137_n150# a_n1041_n150# 0.43fF
+C59 a_n849_n150# a_n561_n150# 0.10fF
+C60 a_15_n150# a_399_n150# 0.07fF
+C61 a_n849_n150# a_n657_n150# 0.16fF
+C62 a_n849_n150# a_n1041_n150# 0.16fF
+C63 a_n177_n150# a_n561_n150# 0.07fF
+C64 a_n465_n150# a_n561_n150# 0.43fF
+C65 a_15_n150# a_n177_n150# 0.16fF
+C66 a_n81_n150# a_n369_n150# 0.10fF
+C67 a_n657_n150# a_n465_n150# 0.16fF
+C68 w_n1367_n369# a_1167_n150# 0.14fF
+C69 a_303_n150# a_591_n150# 0.10fF
+C70 a_n1137_n150# a_n1229_n150# 0.43fF
+C71 a_879_n150# a_1071_n150# 0.16fF
+C72 a_879_n150# a_975_n150# 0.43fF
+C73 a_207_n150# a_399_n150# 0.16fF
+C74 a_n849_n150# a_n1229_n150# 0.07fF
+C75 a_687_n150# a_591_n150# 0.43fF
+C76 a_n1137_n150# a_n753_n150# 0.07fF
+C77 a_303_n150# a_687_n150# 0.07fF
+C78 a_111_n150# a_303_n150# 0.16fF
+C79 a_n369_n150# a_n561_n150# 0.16fF
+C80 a_n849_n150# a_n753_n150# 0.43fF
+C81 a_1071_n150# a_975_n150# 0.43fF
+C82 a_879_n150# a_783_n150# 0.43fF
+C83 a_207_n150# a_n177_n150# 0.07fF
+C84 a_303_n150# a_n81_n150# 0.07fF
+C85 a_15_n150# a_n369_n150# 0.07fF
+C86 a_n657_n150# a_n369_n150# 0.10fF
+C87 a_n177_n150# a_n273_n150# 0.43fF
+C88 a_n465_n150# a_n273_n150# 0.16fF
+C89 a_591_n150# a_495_n150# 0.43fF
+C90 a_303_n150# a_495_n150# 0.16fF
+C91 a_n849_n150# a_n1137_n150# 0.10fF
+C92 a_n465_n150# a_n753_n150# 0.10fF
+C93 a_879_n150# a_1167_n150# 0.10fF
+C94 a_111_n150# a_n81_n150# 0.16fF
+C95 a_1071_n150# a_783_n150# 0.10fF
+C96 a_783_n150# a_975_n150# 0.16fF
+C97 a_687_n150# a_495_n150# 0.16fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vdd nUp vss Down biasp out pswitch iref nDown Up
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 out nUp 0.31fF
+C1 pswitch nswitch 0.06fF
+C2 biasp nswitch 0.03fF
+C3 nDown Down 0.13fF
+C4 Up nUp 0.15fF
+C5 out nswitch 1.28fF
+C6 pswitch vdd 3.98fF
+C7 biasp vdd 2.64fF
+C8 out vdd 6.66fF
+C9 biasp iref 0.80fF
+C10 nUp Down 0.25fF
+C11 vdd nswitch 0.07fF
+C12 pswitch biasp 3.11fF
+C13 nDown nswitch 0.31fF
+C14 out pswitch 4.91fF
+C15 iref nswitch 1.91fF
+C16 Down nswitch 2.27fF
+C17 pswitch nUp 5.66fF
+C18 pswitch Up 0.70fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n111_n156# a_n15_n156# 0.02fF
+C1 a_81_n156# a_n15_n156# 0.02fF
+C2 a_111_n125# a_15_n125# 0.36fF
+C3 w_n311_n344# a_15_n125# 0.09fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 w_n311_n344# a_111_n125# 0.14fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 a_n173_n125# a_15_n125# 0.13fF
+C8 a_111_n125# a_n81_n125# 0.13fF
+C9 a_111_n125# a_n173_n125# 0.08fF
+C10 w_n311_n344# a_n81_n125# 0.09fF
+C11 w_n311_n344# a_n173_n125# 0.14fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_15_n125# 0.13fF
+C1 a_n81_n125# a_15_n125# 0.36fF
+C2 a_111_n125# a_n173_n125# 0.08fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_111_n125# a_15_n125# 0.36fF
+C5 a_n15_n151# a_n111_n151# 0.02fF
+C6 a_n15_n151# a_81_n151# 0.02fF
+C7 a_n81_n125# a_n173_n125# 0.36fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 vdd m1_187_n605# 0.55fF
+C1 m1_45_n513# vdd 0.69fF
+C2 m1_45_n513# m1_187_n605# 0.36fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n81_n125# 0.36fF
+C1 a_n173_n125# a_n81_n125# 0.36fF
+C2 w_n311_n344# a_n81_n125# 0.09fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n173_n125# a_111_n125# 0.08fF
+C5 a_111_n125# w_n311_n344# 0.14fF
+C6 a_n173_n125# a_15_n125# 0.13fF
+C7 a_15_n125# w_n311_n344# 0.09fF
+C8 a_n173_n125# w_n311_n344# 0.14fF
+C9 a_111_n125# a_n81_n125# 0.13fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_15_n125# 0.36fF
+C1 a_n81_n125# a_15_n125# 0.36fF
+C2 a_111_n125# a_n173_n125# 0.08fF
+C3 a_n81_n125# a_n173_n125# 0.36fF
+C4 a_n81_n125# a_111_n125# 0.13fF
+C5 a_n173_n125# a_15_n125# 0.13fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 out in 0.32fF
+C1 vdd out 0.10fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in vdd 0.21fF
+C1 CLK inverter_cp_x1_0/out 0.31fF
+C2 inverter_cp_x1_2/in CLK_d 0.12fF
+C3 inverter_cp_x1_2/in CLK 0.31fF
+C4 vdd nCLK_d 0.03fF
+C5 vdd CLK_d 0.03fF
+C6 nCLK_d inverter_cp_x1_0/out 0.11fF
+C7 CLK vdd 0.36fF
+C8 vdd inverter_cp_x1_0/out 0.28fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n33_n95# 0.28fF
+C1 w_n263_n314# a_63_n95# 0.11fF
+C2 a_n33_n95# a_63_n95# 0.28fF
+C3 w_n263_n314# a_n33_n95# 0.08fF
+C4 a_n125_n95# a_63_n95# 0.10fF
+C5 w_n263_n314# a_n125_n95# 0.11fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_15_n125# 0.36fF
+C1 a_n129_n213# a_n173_n125# 0.02fF
+C2 a_n129_n213# a_111_n125# 0.01fF
+C3 a_n173_n125# a_15_n125# 0.13fF
+C4 a_15_n125# a_111_n125# 0.36fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 a_n129_n213# a_15_n125# 0.10fF
+C7 a_n81_n125# a_111_n125# 0.13fF
+C8 a_n173_n125# a_111_n125# 0.08fF
+C9 a_n129_n213# a_n81_n125# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n81_n183# a_n125_n95# 0.16fF
+C1 a_n33_n95# a_n125_n95# 0.88fF
+C2 a_n81_n183# a_n33_n95# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 nQ D 0.05fF
+C1 Q D 0.05fF
+C2 nD nQ 0.05fF
+C3 nD Q 0.05fF
+C4 nQ vdd 0.16fF
+C5 Q vdd 0.16fF
+C6 nQ Q 0.93fF
+C7 nQ m1_657_280# 1.41fF
+C8 m1_657_280# Q 0.94fF
+C9 m1_657_280# CLK 0.24fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
++ nCLK latch_diff_0/nD
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C1 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C2 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C3 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C4 latch_diff_1/D latch_diff_1/nD 0.33fF
+C5 Q latch_diff_1/nD 0.01fF
+C6 vdd latch_diff_1/D 0.03fF
+C7 vdd latch_diff_1/nD 0.02fF
+C8 nQ latch_diff_1/D 0.11fF
+C9 nQ latch_diff_1/nD 0.08fF
+C10 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C11 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C12 latch_diff_0/nD latch_diff_1/D 0.41fF
+C13 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C14 latch_diff_0/D latch_diff_1/D 0.11fF
+C15 vdd latch_diff_0/nD 0.14fF
+C16 latch_diff_0/D latch_diff_1/nD 0.04fF
+C17 vdd latch_diff_0/D 0.09fF
+C18 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n129_n84# w_n359_n303# 0.06fF
+C1 a_159_n84# w_n359_n303# 0.08fF
+C2 a_n63_n110# a_n159_n110# 0.02fF
+C3 a_63_n84# a_n33_n84# 0.24fF
+C4 a_n33_n84# a_n221_n84# 0.09fF
+C5 a_n129_n84# a_n33_n84# 0.24fF
+C6 a_159_n84# a_n33_n84# 0.09fF
+C7 w_n359_n303# a_n33_n84# 0.05fF
+C8 a_129_n110# a_33_n110# 0.02fF
+C9 a_63_n84# a_n221_n84# 0.05fF
+C10 a_63_n84# a_n129_n84# 0.09fF
+C11 a_159_n84# a_63_n84# 0.24fF
+C12 a_n129_n84# a_n221_n84# 0.24fF
+C13 a_159_n84# a_n221_n84# 0.04fF
+C14 a_159_n84# a_n129_n84# 0.05fF
+C15 a_63_n84# w_n359_n303# 0.06fF
+C16 w_n359_n303# a_n221_n84# 0.08fF
+C17 a_n63_n110# a_33_n110# 0.02fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_63_n42# a_n221_n42# 0.03fF
+C1 a_n129_n42# a_n33_n42# 0.12fF
+C2 a_n33_n42# a_63_n42# 0.12fF
+C3 a_n33_n42# a_n221_n42# 0.05fF
+C4 a_33_n68# a_129_n68# 0.02fF
+C5 a_n63_n68# a_33_n68# 0.02fF
+C6 a_n129_n42# a_159_n42# 0.03fF
+C7 a_63_n42# a_159_n42# 0.12fF
+C8 a_159_n42# a_n221_n42# 0.02fF
+C9 a_n33_n42# a_159_n42# 0.05fF
+C10 a_n63_n68# a_n159_n68# 0.02fF
+C11 a_n129_n42# a_63_n42# 0.05fF
+C12 a_n129_n42# a_n221_n42# 0.12fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 in vdd 0.33fF
+C1 vdd out 0.62fF
+C2 in out 0.67fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_33_n68# a_n63_n68# 0.02fF
+C1 a_63_n42# a_n125_n42# 0.05fF
+C2 a_n33_n42# a_63_n42# 0.12fF
+C3 a_n33_n42# a_n125_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n125_n84# a_63_n84# 0.09fF
+C1 a_63_n84# w_n263_n303# 0.10fF
+C2 a_n125_n84# a_n33_n84# 0.24fF
+C3 a_n33_n84# w_n263_n303# 0.07fF
+C4 a_n63_n110# a_33_n110# 0.02fF
+C5 a_n33_n84# a_63_n84# 0.24fF
+C6 a_n125_n84# w_n263_n303# 0.10fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 vdd out 0.15fF
+C1 in out 0.30fF
+C2 vdd in 0.01fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C1 vdd CLK_2 0.08fF
+C2 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C3 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
+C4 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C5 DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.29fF
+C6 DFlipFlop_0/nCLK nout_div 0.43fF
+C7 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C8 o1 vdd 0.14fF
+C9 nCLK_2 o2 0.11fF
+C10 vdd nout_div 0.16fF
+C11 DFlipFlop_0/CLK nout_div 0.42fF
+C12 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C13 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C14 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C15 DFlipFlop_0/nCLK vdd 0.30fF
+C16 o1 out_div 0.01fF
+C17 nout_div out_div 0.22fF
+C18 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C19 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/nD 0.11fF
+C20 DFlipFlop_0/nCLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.46fF
+C21 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C22 DFlipFlop_0/CLK vdd 0.40fF
+C23 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C24 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C25 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C26 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/nD 0.12fF
+C27 vdd out_div 0.03fF
+C28 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
+C29 o1 CLK_2 0.11fF
+C30 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C31 vdd o2 0.14fF
+C32 nCLK_2 vdd 0.08fF
+C33 DFlipFlop_0/latch_diff_0/D nout_div 0.09fF
+C34 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C35 nCLK_2 vss 1.08fF
+C36 o2 vss 2.21fF
+C37 CLK_2 vss 1.08fF
+C38 o1 vss 2.21fF
+C39 DFlipFlop_0/CLK vss 1.03fF
+C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C42 CLK vss 3.27fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n257_n777# a_n221_n600# 0.25fF
+C1 a_n129_n600# a_n221_n600# 7.87fF
+C2 a_n129_n600# a_n257_n777# 0.29fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n221_n300# a_n129_n300# 4.05fF
+C1 a_n257_n404# a_n129_n300# 0.30fF
+C2 a_n257_n404# a_n221_n300# 0.21fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 a_3996_n100# vdd 3.68fF
+C1 vdd in 0.02fF
+C2 a_3996_n100# out 55.19fF
+C3 a_3996_n100# a_678_n100# 6.52fF
+C4 a_678_n100# in 0.81fF
+C5 vdd out 47.17fF
+C6 vdd a_678_n100# 0.08fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_n33_n238# 0.02fF
+C1 a_15_n150# a_n33_n238# 0.02fF
+C2 a_15_n150# a_n73_n150# 0.51fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_181# w_n211_n369# 0.05fF
+C1 a_n73_n150# w_n211_n369# 0.20fF
+C2 a_15_n150# a_n33_181# 0.01fF
+C3 a_n73_n150# a_15_n150# 0.51fF
+C4 a_n73_n150# a_n33_181# 0.01fF
+C5 a_15_n150# w_n211_n369# 0.20fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n509_n150# a_n465_172# 0.01fF
+C1 a_447_n150# a_n465_172# 0.01fF
+C2 a_255_n150# a_n129_n150# 0.07fF
+C3 a_n33_n150# a_n465_172# 0.10fF
+C4 a_n417_n150# a_n465_172# 0.10fF
+C5 a_n321_n150# a_n129_n150# 0.16fF
+C6 a_n129_n150# a_n509_n150# 0.07fF
+C7 a_n33_n150# a_n129_n150# 0.43fF
+C8 a_n417_n150# a_n129_n150# 0.10fF
+C9 a_159_n150# a_351_n150# 0.16fF
+C10 a_n129_n150# a_n465_172# 0.10fF
+C11 a_n225_n150# a_159_n150# 0.07fF
+C12 a_63_n150# a_351_n150# 0.10fF
+C13 a_63_n150# a_159_n150# 0.43fF
+C14 a_255_n150# a_351_n150# 0.43fF
+C15 a_63_n150# a_n225_n150# 0.10fF
+C16 a_159_n150# a_255_n150# 0.43fF
+C17 a_351_n150# a_447_n150# 0.43fF
+C18 a_n33_n150# a_351_n150# 0.07fF
+C19 a_159_n150# a_447_n150# 0.10fF
+C20 a_n33_n150# a_159_n150# 0.16fF
+C21 a_n225_n150# a_n321_n150# 0.43fF
+C22 a_n225_n150# a_n509_n150# 0.10fF
+C23 a_63_n150# a_255_n150# 0.16fF
+C24 a_351_n150# a_n465_172# 0.10fF
+C25 a_63_n150# a_n321_n150# 0.07fF
+C26 a_n33_n150# a_n225_n150# 0.16fF
+C27 a_n417_n150# a_n225_n150# 0.16fF
+C28 a_63_n150# a_447_n150# 0.07fF
+C29 a_159_n150# a_n465_172# 0.10fF
+C30 a_n33_n150# a_63_n150# 0.43fF
+C31 a_n225_n150# a_n465_172# 0.10fF
+C32 a_159_n150# a_n129_n150# 0.10fF
+C33 a_255_n150# a_447_n150# 0.16fF
+C34 a_n321_n150# a_n509_n150# 0.16fF
+C35 a_63_n150# a_n465_172# 0.10fF
+C36 a_n33_n150# a_255_n150# 0.10fF
+C37 a_n225_n150# a_n129_n150# 0.43fF
+C38 a_n33_n150# a_n321_n150# 0.10fF
+C39 a_n417_n150# a_n321_n150# 0.43fF
+C40 a_n417_n150# a_n509_n150# 0.43fF
+C41 a_63_n150# a_n129_n150# 0.16fF
+C42 a_255_n150# a_n465_172# 0.10fF
+C43 a_n33_n150# a_n417_n150# 0.07fF
+C44 a_n321_n150# a_n465_172# 0.10fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_255_n150# a_447_n150# 0.16fF
+C1 a_n33_n150# a_159_n150# 0.16fF
+C2 a_n465_n247# a_159_n150# 0.08fF
+C3 w_n647_n369# a_63_n150# 0.02fF
+C4 a_n321_n150# a_63_n150# 0.07fF
+C5 a_63_n150# a_447_n150# 0.07fF
+C6 a_n225_n150# a_63_n150# 0.10fF
+C7 a_n129_n150# a_255_n150# 0.07fF
+C8 w_n647_n369# a_351_n150# 0.07fF
+C9 a_n33_n150# a_255_n150# 0.10fF
+C10 a_351_n150# a_447_n150# 0.43fF
+C11 a_n465_n247# a_255_n150# 0.08fF
+C12 a_n129_n150# a_63_n150# 0.16fF
+C13 w_n647_n369# a_n509_n150# 0.14fF
+C14 a_n321_n150# a_n509_n150# 0.16fF
+C15 a_n33_n150# a_63_n150# 0.43fF
+C16 a_n225_n150# a_n509_n150# 0.10fF
+C17 w_n647_n369# a_n321_n150# 0.05fF
+C18 a_n465_n247# a_63_n150# 0.08fF
+C19 w_n647_n369# a_447_n150# 0.14fF
+C20 a_n225_n150# w_n647_n369# 0.04fF
+C21 a_n33_n150# a_351_n150# 0.07fF
+C22 a_n225_n150# a_n321_n150# 0.43fF
+C23 a_n129_n150# a_n509_n150# 0.07fF
+C24 a_n465_n247# a_351_n150# 0.08fF
+C25 a_n129_n150# w_n647_n369# 0.02fF
+C26 a_n129_n150# a_n321_n150# 0.16fF
+C27 w_n647_n369# a_n33_n150# 0.02fF
+C28 a_n225_n150# a_n129_n150# 0.43fF
+C29 a_n321_n150# a_n33_n150# 0.10fF
+C30 a_159_n150# a_255_n150# 0.43fF
+C31 a_n509_n150# a_n417_n150# 0.43fF
+C32 w_n647_n369# a_n465_n247# 0.47fF
+C33 a_n321_n150# a_n465_n247# 0.08fF
+C34 a_n225_n150# a_n33_n150# 0.16fF
+C35 w_n647_n369# a_n417_n150# 0.07fF
+C36 a_n225_n150# a_n465_n247# 0.08fF
+C37 a_n321_n150# a_n417_n150# 0.43fF
+C38 a_159_n150# a_63_n150# 0.43fF
+C39 a_n225_n150# a_n417_n150# 0.16fF
+C40 a_n129_n150# a_n33_n150# 0.43fF
+C41 a_n129_n150# a_n465_n247# 0.08fF
+C42 a_159_n150# a_351_n150# 0.16fF
+C43 a_n465_n247# a_n33_n150# 0.08fF
+C44 a_n129_n150# a_n417_n150# 0.10fF
+C45 a_255_n150# a_63_n150# 0.16fF
+C46 a_n33_n150# a_n417_n150# 0.07fF
+C47 a_n465_n247# a_n417_n150# 0.08fF
+C48 w_n647_n369# a_159_n150# 0.04fF
+C49 a_255_n150# a_351_n150# 0.43fF
+C50 a_159_n150# a_447_n150# 0.10fF
+C51 a_n225_n150# a_159_n150# 0.07fF
+C52 a_63_n150# a_351_n150# 0.10fF
+C53 w_n647_n369# a_255_n150# 0.05fF
+C54 a_n129_n150# a_159_n150# 0.10fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_15_n11# 0.15fF
+C1 a_n73_n11# a_n33_n99# 0.02fF
+C2 a_15_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# w_n216_n334# 0.20fF
+C1 a_n78_n114# a_20_n114# 0.42fF
+C2 w_n216_n334# a_20_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vdd vbulkp 0.04fF
+C1 vbulkp out 0.08fF
+C2 vdd in 0.01fF
+C3 in out 0.11fF
+C4 in vss 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 vbp inverter_csvco_0/vdd 0.75fF
+C1 inverter_csvco_0/vss D0 0.02fF
+C2 inverter_csvco_0/vss out 0.03fF
+C3 inverter_csvco_0/vss in 0.01fF
+C4 vdd cap_vco_0/t 0.04fF
+C5 D0 out 0.09fF
+C6 vdd vbp 1.21fF
+C7 out cap_vco_0/t 0.70fF
+C8 inverter_csvco_0/vss vctrl 0.87fF
+C9 out in 0.06fF
+C10 vdd inverter_csvco_0/vdd 1.89fF
+C11 out inverter_csvco_0/vdd 0.02fF
+C12 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C13 in inverter_csvco_0/vdd 0.01fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vdd vss csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 csvco_branch_2/in out_vco 0.58fF
+C1 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C2 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
+C3 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C4 vctrl csvco_branch_2/vbp 0.06fF
+C5 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C6 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
+C7 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C8 csvco_branch_1/in out_vco 0.76fF
+C9 vctrl D0 4.41fF
+C10 vdd csvco_branch_2/vbp 1.49fF
+C11 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C12 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C13 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C14 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 out_div o1 0.11fF
+C1 o1 vdd 0.09fF
+C2 out_div vdd 0.17fF
+C3 out_div out_pad 0.15fF
+C4 out_pad vdd 0.10fF
+C5 in_vco vss 0.83fF
+C6 out_pad vss 0.70fF
+C7 out_div vss 3.00fF
+C8 vdd vss 14.54fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 B X 0.13fF
+C1 X VGND 0.28fF
+C2 VPWR X 0.07fF
+C3 a_158_392# a_194_125# 0.06fF
+C4 a_355_368# a_194_125# 0.51fF
+C5 a_355_368# A 0.02fF
+C6 A a_194_125# 0.18fF
+C7 a_355_368# B 0.08fF
+C8 B a_194_125# 0.57fF
+C9 VGND a_194_125# 0.25fF
+C10 a_355_368# VPWR 0.37fF
+C11 VPWR a_194_125# 0.33fF
+C12 B A 0.28fF
+C13 A VGND 0.31fF
+C14 VPWR A 0.15fF
+C15 a_355_368# X 0.17fF
+C16 X a_194_125# 0.29fF
+C17 VPB VPWR 0.06fF
+C18 B VGND 0.10fF
+C19 VPWR B 0.09fF
+C20 VPWR VGND 0.01fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 X VGND 0.15fF
+C1 A a_56_136# 0.17fF
+C2 VGND B 0.03fF
+C3 X a_56_136# 0.26fF
+C4 a_56_136# B 0.30fF
+C5 A B 0.08fF
+C6 X B 0.02fF
+C7 a_56_136# VPWR 0.57fF
+C8 A VPWR 0.07fF
+C9 X VPWR 0.20fF
+C10 VPWR B 0.02fF
+C11 VGND a_56_136# 0.06fF
+C12 VPB VPWR 0.04fF
+C13 A VGND 0.21fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 A X 0.02fF
+C1 B a_63_368# 0.14fF
+C2 B VGND 0.11fF
+C3 VPB VPWR 0.04fF
+C4 VPWR X 0.18fF
+C5 A VPWR 0.05fF
+C6 A B 0.10fF
+C7 a_152_368# a_63_368# 0.03fF
+C8 B VPWR 0.01fF
+C9 VGND a_63_368# 0.27fF
+C10 a_63_368# X 0.33fF
+C11 A a_63_368# 0.28fF
+C12 VGND X 0.16fF
+C13 a_63_368# VPWR 0.29fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
++ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
++ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
++ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 nQ0 Q0 0.33fF
+C1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q0 0.42fF
+C2 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q1 0.20fF
+C3 nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
+C4 nCLK DFlipFlop_3/latch_diff_1/D 0.14fF
+C5 nCLK DFlipFlop_2/D 0.41fF
+C6 Q0 Q1 9.65fF
+C7 nQ0 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.04fF
+C8 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.28fF
+C9 CLK Q0 0.08fF
+C10 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C11 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C12 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
+C13 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C14 DFlipFlop_0/Q Q0 0.21fF
+C15 sky130_fd_sc_hs__and2_1_1/a_56_136# vdd 0.04fF
+C16 DFlipFlop_2/latch_diff_1/m1_657_280# Q1 0.03fF
+C17 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C18 vdd DFlipFlop_0/D 0.19fF
+C19 nCLK nQ2 0.10fF
+C20 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C21 DFlipFlop_2/latch_diff_1/nD CLK 0.09fF
+C22 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C23 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C24 DFlipFlop_1/D nQ0 0.12fF
+C25 DFlipFlop_3/nQ vdd 0.02fF
+C26 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C27 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C28 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C29 DFlipFlop_1/D Q1 0.03fF
+C30 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C31 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
+C32 nQ0 Q1 0.06fF
+C33 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q1 0.21fF
+C34 CLK DFlipFlop_1/D 0.21fF
+C35 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
+C36 CLK nQ0 0.19fF
+C37 Q1 DFlipFlop_2/nQ 0.31fF
+C38 nCLK sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.11fF
+C39 CLK Q1 -0.10fF
+C40 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C41 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C42 nCLK Q0 0.20fF
+C43 vdd DFlipFlop_2/D 0.07fF
+C44 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C45 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q1 0.09fF
+C46 DFlipFlop_0/Q Q1 0.13fF
+C47 CLK DFlipFlop_2/nQ 0.13fF
+C48 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C49 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C50 DFlipFlop_0/Q CLK 0.08fF
+C51 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C52 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C53 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C54 nQ2 vdd 0.04fF
+C55 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C56 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C57 nQ0 DFlipFlop_1/latch_diff_0/nD 0.08fF
+C58 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
+C59 nQ0 DFlipFlop_1/latch_diff_0/D 0.09fF
+C60 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C61 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
+C62 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C63 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C64 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C65 nCLK DFlipFlop_1/D 0.14fF
+C66 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C67 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C68 nCLK nQ0 0.09fF
+C69 Q0 DFlipFlop_0/D 0.39fF
+C70 DFlipFlop_3/latch_diff_0/m1_657_280# Q1 0.28fF
+C71 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
+C72 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C73 nCLK Q1 -0.01fF
+C74 DFlipFlop_3/nQ Q1_shift 0.04fF
+C75 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C76 vdd Q1_shift 0.10fF
+C77 sky130_fd_sc_hs__xor2_1_0/a_355_368# vdd 0.03fF
+C78 nQ0 DFlipFlop_1/latch_diff_0/m1_657_280# 0.25fF
+C79 nCLK DFlipFlop_2/nQ 0.09fF
+C80 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C81 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C82 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C83 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C84 vdd Q0 5.33fF
+C85 Q1 DFlipFlop_0/latch_diff_0/D 0.15fF
+C86 nCLK DFlipFlop_0/Q 0.11fF
+C87 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
+C88 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C89 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C90 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C91 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C92 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C93 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C94 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
+C95 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C96 DFlipFlop_0/latch_diff_1/nD Q1 0.10fF
+C97 Q0 DFlipFlop_2/D 0.25fF
+C98 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C99 Q1 DFlipFlop_0/D 0.13fF
+C100 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C101 Q0 DFlipFlop_0/latch_diff_1/D 0.23fF
+C102 DFlipFlop_2/latch_diff_0/D Q1 0.42fF
+C103 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C104 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C105 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
+C106 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C107 vdd DFlipFlop_1/D 0.25fF
+C108 vdd nQ0 0.11fF
+C109 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C110 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
+C111 DFlipFlop_3/nQ Q1 0.10fF
+C112 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C113 nQ2 Q0 0.23fF
+C114 vdd Q1 9.49fF
+C115 nCLK DFlipFlop_1/latch_diff_1/nD 0.16fF
+C116 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C117 vdd DFlipFlop_2/nQ 0.02fF
+C118 CLK DFlipFlop_3/nQ 0.01fF
+C119 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C120 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
+C121 CLK vdd 0.41fF
+C122 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C123 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
+C124 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
+C125 Q1 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C126 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C127 Q1 DFlipFlop_2/D 0.10fF
+C128 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C129 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
+C130 CLK_5 vdd 0.15fF
+C131 sky130_fd_sc_hs__xor2_1_0/a_355_368# Q0 0.03fF
+C132 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C133 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C134 CLK DFlipFlop_2/D 0.14fF
+C135 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C136 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C137 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C138 nCLK DFlipFlop_1/latch_diff_1/D 0.08fF
+C139 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C140 nQ2 nQ0 0.03fF
+C141 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
+C142 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C143 nQ2 Q1 0.07fF
+C144 DFlipFlop_3/latch_diff_1/nD Q1 1.24fF
+C145 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C146 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C147 CLK nQ2 0.17fF
+C148 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C149 nCLK DFlipFlop_3/nQ 0.02fF
+C150 DFlipFlop_0/Q nQ2 0.09fF
+C151 nCLK vdd 0.34fF
+C152 nCLK sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.02fF
+C153 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C154 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C155 Q1 Q1_shift 0.36fF
+C156 DFlipFlop_1/D Q0 0.07fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 DFlipFlop_2/nQ vss 0.50fF
+C172 Q1 vss 8.55fF
+C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 nQ0 vss 3.42fF
+C183 Q0 vss 0.53fF
+C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n129_n125# a_159_n125# 0.08fF
+C1 a_n225_n125# a_n129_n125# 0.36fF
+C2 a_n63_n151# a_n159_n151# 0.02fF
+C3 a_n317_n125# a_63_n125# 0.06fF
+C4 a_129_n151# a_33_n151# 0.02fF
+C5 a_n317_n125# a_n33_n125# 0.08fF
+C6 a_n317_n125# a_n225_n125# 0.36fF
+C7 a_n317_n125# a_n129_n125# 0.13fF
+C8 a_129_n151# a_225_n151# 0.02fF
+C9 a_255_n125# a_63_n125# 0.13fF
+C10 a_n33_n125# a_63_n125# 0.36fF
+C11 a_63_n125# a_159_n125# 0.36fF
+C12 a_n225_n125# a_63_n125# 0.08fF
+C13 a_n33_n125# a_255_n125# 0.08fF
+C14 a_63_n125# a_n129_n125# 0.13fF
+C15 a_n255_n151# a_n159_n151# 0.02fF
+C16 a_255_n125# a_159_n125# 0.36fF
+C17 a_255_n125# a_n129_n125# 0.06fF
+C18 a_n63_n151# a_33_n151# 0.02fF
+C19 a_n33_n125# a_159_n125# 0.13fF
+C20 a_n225_n125# a_n33_n125# 0.13fF
+C21 a_n33_n125# a_n129_n125# 0.36fF
+C22 a_n225_n125# a_159_n125# 0.06fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_63_n125# w_n455_n344# 0.04fF
+C1 a_129_n154# a_225_n154# 0.02fF
+C2 a_n33_n125# a_n129_n125# 0.36fF
+C3 a_n129_n125# a_n225_n125# 0.36fF
+C4 a_n129_n125# a_159_n125# 0.08fF
+C5 a_n33_n125# a_255_n125# 0.08fF
+C6 a_159_n125# a_255_n125# 0.36fF
+C7 a_63_n125# a_n129_n125# 0.13fF
+C8 a_n129_n125# w_n455_n344# 0.04fF
+C9 a_63_n125# a_255_n125# 0.13fF
+C10 a_255_n125# w_n455_n344# 0.11fF
+C11 a_n33_n125# a_n317_n125# 0.08fF
+C12 a_n317_n125# a_n225_n125# 0.36fF
+C13 a_n255_n154# a_n159_n154# 0.02fF
+C14 a_63_n125# a_n317_n125# 0.06fF
+C15 a_n317_n125# w_n455_n344# 0.11fF
+C16 a_n129_n125# a_255_n125# 0.06fF
+C17 a_n159_n154# a_n63_n154# 0.02fF
+C18 a_33_n154# a_n63_n154# 0.02fF
+C19 a_n33_n125# a_n225_n125# 0.13fF
+C20 a_n33_n125# a_159_n125# 0.13fF
+C21 a_159_n125# a_n225_n125# 0.06fF
+C22 a_n33_n125# a_63_n125# 0.36fF
+C23 a_63_n125# a_n225_n125# 0.08fF
+C24 a_63_n125# a_159_n125# 0.36fF
+C25 a_129_n154# a_33_n154# 0.02fF
+C26 a_n33_n125# w_n455_n344# 0.05fF
+C27 w_n455_n344# a_n225_n125# 0.06fF
+C28 a_n129_n125# a_n317_n125# 0.13fF
+C29 a_159_n125# w_n455_n344# 0.06fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 in vdd 0.04fF
+C1 out in 0.85fF
+C2 out vdd 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 vdd Up 0.60fF
+C1 nUp Up 0.20fF
+C2 vdd inverter_cp_x1_0/out 0.25fF
+C3 vdd nUp 0.14fF
+C4 QB vdd 0.02fF
+C5 vdd nDown 0.80fF
+C6 inverter_cp_x1_0/out nDown 0.11fF
+C7 vdd QA 0.02fF
+C8 Down vdd 0.09fF
+C9 Down inverter_cp_x1_0/out 0.12fF
+C10 Down nDown 0.23fF
+C11 Up inverter_cp_x1_2/in 0.12fF
+C12 vdd inverter_cp_x1_2/in 0.42fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_63_n90# a_n129_n90# 0.09fF
+C1 a_159_n90# a_63_n90# 0.26fF
+C2 a_n221_n90# a_63_n90# 0.06fF
+C3 a_n33_n90# w_n359_n309# 0.05fF
+C4 a_n33_n90# a_n129_n90# 0.26fF
+C5 a_n159_n207# a_n63_n116# 0.12fF
+C6 a_n33_n90# a_159_n90# 0.09fF
+C7 a_n33_n90# a_n221_n90# 0.09fF
+C8 w_n359_n309# a_n129_n90# 0.06fF
+C9 w_n359_n309# a_159_n90# 0.09fF
+C10 a_n221_n90# w_n359_n309# 0.09fF
+C11 a_159_n90# a_n129_n90# 0.06fF
+C12 a_n221_n90# a_n129_n90# 0.26fF
+C13 a_n33_n90# a_63_n90# 0.26fF
+C14 a_n221_n90# a_159_n90# 0.04fF
+C15 w_n359_n309# a_63_n90# 0.06fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n33_n45# a_63_n45# 0.13fF
+C1 a_n33_n45# a_n125_n45# 0.13fF
+C2 a_n129_71# a_33_n71# 0.04fF
+C3 a_63_n45# a_n125_n45# 0.05fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C1 out B 0.40fF
+C2 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C3 B A 0.24fF
+C4 out A 0.06fF
+C5 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
+C6 out vdd 0.11fF
+C7 vdd A 0.09fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C1 nor_pfd_2/B nor_pfd_3/A 0.58fF
+C2 Q CLK 0.04fF
+C3 Q vdd 0.08fF
+C4 nor_pfd_3/A vdd 0.09fF
+C5 nor_pfd_2/B vdd 0.02fF
+C6 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C7 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C8 Q nor_pfd_2/A 1.38fF
+C9 Q Reset 0.14fF
+C10 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C11 Reset nor_pfd_3/A 0.12fF
+C12 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C13 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C14 nor_pfd_2/B Reset 0.43fF
+C15 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C16 Q nor_pfd_3/A 0.98fF
+C17 Q nor_pfd_2/B 2.22fF
+C18 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C19 nor_pfd_2/A vdd -0.01fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n33_n45# a_63_n45# 0.13fF
+C1 a_n129_n45# a_n33_n45# 0.13fF
+C2 a_n33_n45# a_159_n45# 0.05fF
+C3 a_n129_n45# a_63_n45# 0.05fF
+C4 a_n33_n45# a_n221_n45# 0.05fF
+C5 a_63_n45# a_159_n45# 0.13fF
+C6 a_63_n45# a_n221_n45# 0.03fF
+C7 a_n129_n45# a_159_n45# 0.03fF
+C8 a_n129_n45# a_n221_n45# 0.13fF
+C9 a_n63_n71# a_n159_n173# 0.10fF
+C10 a_n221_n45# a_159_n45# 0.02fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n33_n90# a_n125_n90# 0.26fF
+C1 a_33_n187# a_n99_n187# 0.04fF
+C2 a_63_n90# a_n125_n90# 0.09fF
+C3 a_n33_n90# a_63_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_15_n45# a_n73_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 w_n211_n309# a_15_n90# 0.09fF
+C1 a_n73_n90# a_15_n90# 0.31fF
+C2 a_n73_n90# w_n211_n309# 0.04fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 A a_656_410# 0.04fF
+C1 vdd a_656_410# 0.20fF
+C2 vdd out 0.10fF
+C3 vdd A 0.05fF
+C4 B a_656_410# 0.30fF
+C5 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
+C6 A B 0.33fF
+C7 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C8 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C9 out a_656_410# 0.20fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C1 vdd Down 0.08fF
+C2 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C3 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C4 vdd Up 1.62fF
+C5 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C6 vdd Reset 0.02fF
+C7 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
+C8 Up Down 0.06fF
+C9 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+
+* Top level circuit top_pll_v1
+
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 nswitch vdd nUp vss Down biasp vco_vctrl pswitch iref_cp nDown Up charge_pump
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss ring_osc_0/csvco_branch_0/inverter_csvco_0/vss ring_osc_0/csvco_branch_2/vbp
++ vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 vco_vctrl div_5_Q1 0.14fF
+C1 div_by_5_0/DFlipFlop_1/D out_by_2 0.38fF
+C2 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C3 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.33fF
+C4 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C5 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C6 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C7 vdd out_div_by_5 0.28fF
+C8 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C9 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C10 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C11 div_by_5_0/DFlipFlop_2/latch_diff_1/nD n_out_by_2 0.24fF
+C12 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
+C13 vco_vctrl vdd -1.02fF
+C14 vco_vctrl nswitch -0.06fF
+C15 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C16 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
+C17 vdd lf_vc 0.02fF
+C18 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
+C19 nUp biasp -0.17fF
+C20 div_by_5_0/DFlipFlop_2/latch_diff_0/D n_out_by_2 0.12fF
+C21 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
+C22 nUp Up 2.72fF
+C23 div_5_nQ0 out_by_2 0.32fF
+C24 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C25 biasp Up 0.26fF
+C26 div_5_nQ0 n_out_by_2 0.10fF
+C27 vdd vco_D0 0.03fF
+C28 vco_vctrl out_by_2 0.53fF
+C29 vco_vctrl n_out_by_2 0.52fF
+C30 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
+C31 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
+C32 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
+C33 div_5_Q0 out_by_2 0.09fF
+C34 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C35 div_5_Q0 n_out_by_2 -0.12fF
+C36 biasp Down 1.24fF
+C37 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C38 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
+C39 nUp vdd 0.05fF
+C40 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C41 vdd buffer_salida_0/a_678_n100# 0.24fF
+C42 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C43 vdd Up 0.28fF
+C44 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
+C45 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
+C46 nUp pswitch 0.85fF
+C47 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
+C48 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
+C49 nUp nDown -0.09fF
+C50 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
+C51 pswitch Up 1.98fF
+C52 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
+C53 nDown biasp 0.26fF
+C54 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
+C55 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
+C56 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C57 nswitch Down 0.54fF
+C58 div_5_Q1_shift out_div_by_5 0.05fF
+C59 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
+C60 out_by_2 div_5_Q1 0.42fF
+C61 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C62 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
+C63 out_by_2 div_5_nQ2 0.16fF
+C64 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C65 div_5_Q1 n_out_by_2 1.04fF
+C66 div_by_5_0/DFlipFlop_2/latch_diff_1/D n_out_by_2 0.10fF
+C67 div_5_nQ2 n_out_by_2 0.10fF
+C68 nDown Down 2.55fF
+C69 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C70 vdd out_to_div 0.21fF
+C71 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 0.27fF
+C72 vdd nDown 0.22fF
+C73 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C74 vco_vctrl div_5_Q0 0.48fF
+C75 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C76 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
+C77 vdd QA -0.04fF
+C78 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# n_out_by_2 -0.05fF
+C79 nDown nswitch 0.76fF
+C80 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
+C81 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C82 vdd out_by_2 0.97fF
+C83 pswitch nDown 0.53fF
+C84 vdd n_out_by_2 1.03fF
+C85 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
+C86 vdd out_to_buffer 0.07fF
+C87 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
+C88 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
+C89 out_to_buffer out_to_div 0.13fF
+C90 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C91 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C92 Down iref_cp 0.09fF
+C93 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# n_out_by_2 0.01fF
+C94 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C95 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
+C96 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C97 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
+C98 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
+C99 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C100 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_out_by_2 0.12fF
+C101 div_5_Q1 out_div_by_5 0.01fF
+C102 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
+C103 vdd iref_cp 0.15fF
+C104 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C105 vco_vctrl nUp 0.02fF
+C106 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C107 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.46fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss -0.40fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.31fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 5.50fF
+C141 Up vss 2.37fF
+C142 Down vss 7.92fF
+C143 nDown vss -2.20fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C158 div_5_Q1 vss 4.28fF
+C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_nQ0 vss 0.59fF
+C169 div_5_Q0 vss 0.01fF
+C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_to_buffer vss 1.57fF
+C196 out_to_div vss 4.46fF
+C197 out_first_buffer vss 2.88fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 vco_D0 vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 n_out_buffer_div_2 vss 1.63fF
+C216 out_buffer_div_2 vss 1.60fF
+C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 nswitch vss 3.73fF
+C232 biasp vss 5.44fF
+C233 iref_cp vss 2.81fF
+C234 vco_vctrl vss -19.28fF
+C235 pswitch vss 3.57fF
+C236 lf_vc vss -59.89fF
+C237 loop_filter_0/res_loop_filter_2/out vss 7.90fF
+.end
+
diff --git a/mag/extractions/top_pll_v1_pex_rc_port.spice b/mag/extractions/top_pll_v1_pex_rc_port.spice
new file mode 100644
index 0000000..9019034
--- /dev/null
+++ b/mag/extractions/top_pll_v1_pex_rc_port.spice
@@ -0,0 +1,2876 @@
+* NGSPICE file created from top_pll_v1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C1 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C2 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C3 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C4 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C5 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C6 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C7 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C8 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C9 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C10 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C11 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C12 m3_n7969_2700# m3_n7969_n2600# 3.28fF
+C13 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C14 m3_2669_8000# m3_n2650_8000# 2.73fF
+C15 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C16 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C17 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C18 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C19 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C20 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C21 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C22 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C23 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C24 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C25 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C26 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C27 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C28 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C29 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C30 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C31 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C32 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C33 m3_n2650_n2600# m3_n7969_n2600# 2.73fF
+C34 m3_n2650_2700# m3_2669_2700# 2.73fF
+C35 m3_2669_2700# m3_2669_8000# 3.28fF
+C36 m3_2669_2700# m3_7988_2700# 2.73fF
+C37 m3_7988_2700# m3_7988_n2600# 3.39fF
+C38 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C39 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C40 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C41 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
+C42 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C43 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C44 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C45 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C46 m3_2669_2700# m3_2669_n2600# 3.28fF
+C47 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C48 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C49 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C50 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C51 m3_7988_8000# m3_2669_8000# 2.73fF
+C52 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C53 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C54 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C55 m3_7988_8000# m3_7988_2700# 3.39fF
+C56 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C57 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C58 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C59 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C60 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C61 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C62 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C63 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C64 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C1 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C2 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C3 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C4 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C5 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
+C6 c1_2269_n6300# c1_n2050_n6300# 1.99fF
+C7 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C8 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C9 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C10 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C11 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C12 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C13 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C14 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C15 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C16 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C17 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C18 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 out in 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 vc_pex vss -38.13fF
+C2 res_loop_filter_2/out vss 8.49fF
+C3 in vss -18.79fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_429_n486# w_n2457_n634# 0.02fF
+C1 a_n945_n486# w_n2457_n634# 0.02fF
+C2 w_n2457_n634# a_n1403_n486# 0.02fF
+C3 a_1345_n486# w_n2457_n634# 0.02fF
+C4 a_n1861_n486# w_n2457_n634# 0.02fF
+C5 a_887_n486# w_n2457_n634# 0.02fF
+C6 a_n2319_n486# w_n2457_n634# 0.02fF
+C7 a_1803_n486# w_n2457_n634# 0.02fF
+C8 a_n29_n486# w_n2457_n634# 0.02fF
+C9 a_n487_n486# w_n2457_n634# 0.02fF
+C10 a_2261_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n81_n75# a_15_n75# 0.22fF
+C1 a_n849_n75# a_n1229_n75# 0.03fF
+C2 a_n273_n75# a_n561_n75# 0.05fF
+C3 a_591_n75# a_207_n75# 0.03fF
+C4 a_n177_n75# a_n561_n75# 0.03fF
+C5 a_495_n75# a_591_n75# 0.22fF
+C6 a_n849_n75# a_n1041_n75# 0.08fF
+C7 a_n945_n75# a_n1229_n75# 0.05fF
+C8 a_303_n75# a_15_n75# 0.05fF
+C9 a_n945_n75# a_n1041_n75# 0.22fF
+C10 a_975_n75# a_687_n75# 0.05fF
+C11 a_399_n75# a_687_n75# 0.05fF
+C12 a_687_n75# a_783_n75# 0.22fF
+C13 a_n561_n75# a_n753_n75# 0.08fF
+C14 a_879_n75# a_687_n75# 0.08fF
+C15 a_n561_n75# a_n657_n75# 0.22fF
+C16 a_n273_n75# a_111_n75# 0.03fF
+C17 a_n273_n75# a_n177_n75# 0.22fF
+C18 a_n177_n75# a_111_n75# 0.05fF
+C19 a_591_n75# a_303_n75# 0.05fF
+C20 a_111_n75# a_399_n75# 0.05fF
+C21 a_495_n75# a_207_n75# 0.05fF
+C22 a_975_n75# a_783_n75# 0.08fF
+C23 a_n465_n75# a_n369_n75# 0.22fF
+C24 a_n849_n75# a_n465_n75# 0.03fF
+C25 a_879_n75# a_975_n75# 0.22fF
+C26 a_399_n75# a_783_n75# 0.03fF
+C27 a_n945_n75# a_n849_n75# 0.22fF
+C28 a_687_n75# a_1071_n75# 0.03fF
+C29 a_207_n75# a_n81_n75# 0.05fF
+C30 a_n81_n75# a_n369_n75# 0.05fF
+C31 a_879_n75# a_783_n75# 0.22fF
+C32 a_n273_n75# a_n657_n75# 0.03fF
+C33 a_n273_n75# a_15_n75# 0.05fF
+C34 a_111_n75# a_15_n75# 0.22fF
+C35 a_n465_n75# a_n81_n75# 0.03fF
+C36 a_n177_n75# a_15_n75# 0.08fF
+C37 a_591_n75# a_687_n75# 0.22fF
+C38 a_399_n75# a_15_n75# 0.03fF
+C39 a_207_n75# a_303_n75# 0.22fF
+C40 a_495_n75# a_303_n75# 0.08fF
+C41 a_n1137_n75# a_n753_n75# 0.03fF
+C42 a_975_n75# a_1071_n75# 0.22fF
+C43 a_1167_n75# a_975_n75# 0.08fF
+C44 a_n657_n75# a_n753_n75# 0.22fF
+C45 a_591_n75# a_975_n75# 0.03fF
+C46 a_1071_n75# a_783_n75# 0.05fF
+C47 a_303_n75# a_n81_n75# 0.03fF
+C48 a_879_n75# a_1071_n75# 0.08fF
+C49 a_399_n75# a_591_n75# 0.08fF
+C50 a_n561_n75# a_n369_n75# 0.08fF
+C51 a_1167_n75# a_783_n75# 0.03fF
+C52 a_n849_n75# a_n561_n75# 0.05fF
+C53 a_879_n75# a_1167_n75# 0.05fF
+C54 a_591_n75# a_783_n75# 0.08fF
+C55 a_n465_n75# a_n561_n75# 0.22fF
+C56 a_n1137_n75# a_n1229_n75# 0.22fF
+C57 a_879_n75# a_591_n75# 0.05fF
+C58 a_n945_n75# a_n561_n75# 0.03fF
+C59 a_495_n75# a_687_n75# 0.08fF
+C60 a_n1137_n75# a_n1041_n75# 0.22fF
+C61 a_n1041_n75# a_n753_n75# 0.05fF
+C62 a_n1041_n75# a_n657_n75# 0.03fF
+C63 a_111_n75# a_207_n75# 0.22fF
+C64 a_495_n75# a_111_n75# 0.03fF
+C65 a_n177_n75# a_207_n75# 0.03fF
+C66 a_n273_n75# a_n369_n75# 0.22fF
+C67 a_1167_n75# a_1071_n75# 0.22fF
+C68 a_n177_n75# a_n369_n75# 0.08fF
+C69 a_399_n75# a_207_n75# 0.08fF
+C70 a_495_n75# a_399_n75# 0.22fF
+C71 a_n273_n75# a_n465_n75# 0.08fF
+C72 a_n177_n75# a_n465_n75# 0.05fF
+C73 a_495_n75# a_783_n75# 0.05fF
+C74 a_n1229_n75# a_n1041_n75# 0.08fF
+C75 a_687_n75# a_303_n75# 0.03fF
+C76 a_879_n75# a_495_n75# 0.03fF
+C77 a_n273_n75# a_n81_n75# 0.08fF
+C78 a_111_n75# a_n81_n75# 0.08fF
+C79 a_n177_n75# a_n81_n75# 0.22fF
+C80 a_n1137_n75# a_n849_n75# 0.05fF
+C81 a_n753_n75# a_n369_n75# 0.03fF
+C82 a_n849_n75# a_n753_n75# 0.22fF
+C83 a_n945_n75# a_n1137_n75# 0.08fF
+C84 a_207_n75# a_15_n75# 0.08fF
+C85 a_n657_n75# a_n369_n75# 0.05fF
+C86 a_n465_n75# a_n753_n75# 0.05fF
+C87 a_n849_n75# a_n657_n75# 0.08fF
+C88 a_15_n75# a_n369_n75# 0.03fF
+C89 a_111_n75# a_303_n75# 0.08fF
+C90 a_n945_n75# a_n753_n75# 0.08fF
+C91 a_n465_n75# a_n657_n75# 0.08fF
+C92 a_399_n75# a_303_n75# 0.22fF
+C93 a_n945_n75# a_n657_n75# 0.05fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n513_n75# a_n417_n75# 0.22fF
+C1 a_831_n75# a_543_n75# 0.05fF
+C2 a_n609_n75# a_n225_n75# 0.03fF
+C3 a_159_n75# a_543_n75# 0.03fF
+C4 a_n897_n75# a_n513_n75# 0.03fF
+C5 a_n705_n75# a_n513_n75# 0.08fF
+C6 a_n129_n75# a_n417_n75# 0.05fF
+C7 a_n801_n75# a_n513_n75# 0.05fF
+C8 a_n609_n75# a_n513_n75# 0.22fF
+C9 a_543_n75# a_351_n75# 0.08fF
+C10 a_543_n75# a_447_n75# 0.22fF
+C11 a_n321_n75# a_n33_n75# 0.05fF
+C12 a_159_n75# a_n33_n75# 0.08fF
+C13 a_63_n75# a_n225_n75# 0.05fF
+C14 a_63_n75# a_255_n75# 0.08fF
+C15 a_639_n75# a_735_n75# 0.22fF
+C16 a_255_n75# a_639_n75# 0.03fF
+C17 a_927_n75# a_735_n75# 0.08fF
+C18 a_927_n75# a_639_n75# 0.05fF
+C19 a_n225_n75# a_n513_n75# 0.05fF
+C20 a_159_n75# a_351_n75# 0.08fF
+C21 a_33_n101# a_n927_n101# 0.08fF
+C22 a_831_n75# a_447_n75# 0.03fF
+C23 a_159_n75# a_447_n75# 0.05fF
+C24 a_n33_n75# a_351_n75# 0.03fF
+C25 a_n321_n75# a_n417_n75# 0.22fF
+C26 a_n33_n75# a_n417_n75# 0.03fF
+C27 a_n225_n75# a_n129_n75# 0.22fF
+C28 a_63_n75# a_n129_n75# 0.08fF
+C29 a_255_n75# a_n129_n75# 0.03fF
+C30 a_n705_n75# a_n321_n75# 0.03fF
+C31 a_n989_n75# a_n897_n75# 0.22fF
+C32 a_n705_n75# a_n989_n75# 0.05fF
+C33 a_n801_n75# a_n989_n75# 0.08fF
+C34 a_n321_n75# a_n609_n75# 0.05fF
+C35 a_447_n75# a_351_n75# 0.22fF
+C36 a_n609_n75# a_n989_n75# 0.03fF
+C37 a_n129_n75# a_n513_n75# 0.03fF
+C38 a_543_n75# a_735_n75# 0.08fF
+C39 a_255_n75# a_543_n75# 0.05fF
+C40 a_639_n75# a_543_n75# 0.22fF
+C41 a_927_n75# a_543_n75# 0.03fF
+C42 a_n705_n75# a_n417_n75# 0.05fF
+C43 a_n801_n75# a_n417_n75# 0.03fF
+C44 a_n609_n75# a_n417_n75# 0.08fF
+C45 a_n705_n75# a_n897_n75# 0.08fF
+C46 a_n321_n75# a_n225_n75# 0.22fF
+C47 a_63_n75# a_n321_n75# 0.03fF
+C48 a_159_n75# a_n225_n75# 0.03fF
+C49 a_63_n75# a_159_n75# 0.22fF
+C50 a_831_n75# a_735_n75# 0.22fF
+C51 a_n801_n75# a_n897_n75# 0.22fF
+C52 a_n705_n75# a_n801_n75# 0.22fF
+C53 a_159_n75# a_255_n75# 0.22fF
+C54 a_n33_n75# a_n225_n75# 0.08fF
+C55 a_63_n75# a_n33_n75# 0.22fF
+C56 a_n609_n75# a_n897_n75# 0.05fF
+C57 a_831_n75# a_639_n75# 0.08fF
+C58 a_n705_n75# a_n609_n75# 0.22fF
+C59 a_255_n75# a_n33_n75# 0.05fF
+C60 a_831_n75# a_927_n75# 0.22fF
+C61 a_n801_n75# a_n609_n75# 0.08fF
+C62 a_n321_n75# a_n513_n75# 0.08fF
+C63 a_63_n75# a_351_n75# 0.05fF
+C64 a_351_n75# a_735_n75# 0.03fF
+C65 a_255_n75# a_351_n75# 0.22fF
+C66 a_63_n75# a_447_n75# 0.03fF
+C67 a_n225_n75# a_n417_n75# 0.08fF
+C68 a_447_n75# a_735_n75# 0.05fF
+C69 a_639_n75# a_351_n75# 0.05fF
+C70 a_255_n75# a_447_n75# 0.08fF
+C71 a_n321_n75# a_n129_n75# 0.08fF
+C72 a_159_n75# a_n129_n75# 0.05fF
+C73 a_639_n75# a_447_n75# 0.08fF
+C74 a_n33_n75# a_n129_n75# 0.22fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_351_n150# a_447_n150# 0.43fF
+C1 a_n609_n150# a_n989_n150# 0.07fF
+C2 a_831_n150# a_639_n150# 0.16fF
+C3 a_159_n150# a_n33_n150# 0.16fF
+C4 a_n989_n150# a_n705_n150# 0.10fF
+C5 a_255_n150# a_639_n150# 0.07fF
+C6 a_n513_n150# a_n129_n150# 0.07fF
+C7 a_n609_n150# a_n801_n150# 0.16fF
+C8 a_n801_n150# a_n705_n150# 0.43fF
+C9 a_n417_n150# a_n801_n150# 0.07fF
+C10 a_63_n150# a_n129_n150# 0.16fF
+C11 a_n33_n150# a_255_n150# 0.10fF
+C12 a_159_n150# a_351_n150# 0.16fF
+C13 a_735_n150# a_447_n150# 0.10fF
+C14 a_543_n150# a_927_n150# 0.07fF
+C15 a_255_n150# a_351_n150# 0.43fF
+C16 a_n129_n150# a_n321_n150# 0.16fF
+C17 a_831_n150# a_735_n150# 0.43fF
+C18 a_n129_n150# a_n225_n150# 0.43fF
+C19 a_n609_n150# a_n705_n150# 0.43fF
+C20 a_n609_n150# a_n417_n150# 0.16fF
+C21 a_n417_n150# a_n705_n150# 0.10fF
+C22 a_159_n150# a_n129_n150# 0.10fF
+C23 a_n417_n150# a_n33_n150# 0.07fF
+C24 a_n513_n150# a_n897_n150# 0.07fF
+C25 a_n129_n150# a_255_n150# 0.07fF
+C26 a_639_n150# a_351_n150# 0.10fF
+C27 a_n513_n150# a_n321_n150# 0.16fF
+C28 a_n513_n150# a_n225_n150# 0.10fF
+C29 a_831_n150# a_927_n150# 0.43fF
+C30 a_543_n150# a_447_n150# 0.43fF
+C31 a_63_n150# a_n321_n150# 0.07fF
+C32 a_n33_n150# a_351_n150# 0.07fF
+C33 a_33_n247# a_n927_n247# 0.09fF
+C34 a_63_n150# a_n225_n150# 0.10fF
+C35 a_63_n150# a_447_n150# 0.07fF
+C36 a_639_n150# a_735_n150# 0.43fF
+C37 a_159_n150# a_543_n150# 0.07fF
+C38 a_159_n150# a_63_n150# 0.43fF
+C39 a_543_n150# a_831_n150# 0.10fF
+C40 a_543_n150# a_255_n150# 0.10fF
+C41 a_n225_n150# a_n321_n150# 0.43fF
+C42 a_n513_n150# a_n801_n150# 0.10fF
+C43 a_735_n150# a_351_n150# 0.07fF
+C44 a_63_n150# a_255_n150# 0.16fF
+C45 a_n417_n150# a_n129_n150# 0.10fF
+C46 a_n33_n150# a_n129_n150# 0.43fF
+C47 a_n897_n150# a_n989_n150# 0.43fF
+C48 a_639_n150# a_927_n150# 0.10fF
+C49 a_n897_n150# a_n801_n150# 0.43fF
+C50 a_159_n150# a_n225_n150# 0.07fF
+C51 a_159_n150# a_447_n150# 0.10fF
+C52 a_831_n150# a_447_n150# 0.07fF
+C53 a_255_n150# a_447_n150# 0.16fF
+C54 a_543_n150# a_639_n150# 0.43fF
+C55 a_n609_n150# a_n513_n150# 0.43fF
+C56 a_n513_n150# a_n705_n150# 0.16fF
+C57 a_n513_n150# a_n417_n150# 0.43fF
+C58 a_159_n150# a_255_n150# 0.43fF
+C59 a_n989_n150# a_n801_n150# 0.16fF
+C60 a_n33_n150# a_63_n150# 0.43fF
+C61 a_927_n150# a_735_n150# 0.16fF
+C62 a_543_n150# a_351_n150# 0.16fF
+C63 a_n609_n150# a_n897_n150# 0.10fF
+C64 a_n897_n150# a_n705_n150# 0.16fF
+C65 a_63_n150# a_351_n150# 0.10fF
+C66 a_n609_n150# a_n321_n150# 0.10fF
+C67 a_n321_n150# a_n705_n150# 0.07fF
+C68 a_n417_n150# a_n321_n150# 0.43fF
+C69 a_n609_n150# a_n225_n150# 0.07fF
+C70 a_639_n150# a_447_n150# 0.16fF
+C71 a_n33_n150# a_n321_n150# 0.10fF
+C72 a_n417_n150# a_n225_n150# 0.16fF
+C73 a_543_n150# a_735_n150# 0.16fF
+C74 a_n33_n150# a_n225_n150# 0.16fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n29_n44# a_n387_n44# 0.04fF
+C1 a_1403_n44# a_1761_n44# 0.04fF
+C2 a_n1819_n44# a_n1461_n44# 0.04fF
+C3 a_329_n44# a_n29_n44# 0.04fF
+C4 a_n1103_n44# a_n745_n44# 0.04fF
+C5 a_n1103_n44# a_n1461_n44# 0.04fF
+C6 a_n745_n44# a_n387_n44# 0.04fF
+C7 a_1045_n44# a_687_n44# 0.04fF
+C8 a_1045_n44# a_1403_n44# 0.04fF
+C9 a_329_n44# a_687_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_111_n150# a_15_n150# 0.43fF
+C1 a_783_n150# a_1071_n150# 0.10fF
+C2 a_n369_n150# a_15_n150# 0.07fF
+C3 a_1167_n150# a_783_n150# 0.07fF
+C4 a_n1137_n150# a_n1041_n150# 0.43fF
+C5 a_303_n150# a_15_n150# 0.10fF
+C6 a_n945_n150# a_n849_n150# 0.43fF
+C7 a_n465_n150# a_n849_n150# 0.07fF
+C8 a_n561_n150# a_n753_n150# 0.16fF
+C9 a_207_n150# a_495_n150# 0.10fF
+C10 a_495_n150# a_687_n150# 0.16fF
+C11 a_n753_n150# a_n657_n150# 0.43fF
+C12 a_n369_n150# a_n753_n150# 0.07fF
+C13 a_303_n150# a_591_n150# 0.10fF
+C14 a_399_n150# a_111_n150# 0.10fF
+C15 a_687_n150# a_975_n150# 0.10fF
+C16 w_n1367_n369# a_975_n150# 0.05fF
+C17 a_303_n150# a_399_n150# 0.43fF
+C18 a_n1229_n150# a_n1137_n150# 0.43fF
+C19 a_n753_n150# a_n1137_n150# 0.07fF
+C20 a_975_n150# a_1071_n150# 0.43fF
+C21 a_1167_n150# a_975_n150# 0.16fF
+C22 a_591_n150# a_783_n150# 0.16fF
+C23 a_879_n150# a_783_n150# 0.43fF
+C24 a_n849_n150# a_n1041_n150# 0.16fF
+C25 a_n561_n150# a_n657_n150# 0.43fF
+C26 a_n561_n150# a_n369_n150# 0.16fF
+C27 a_399_n150# a_783_n150# 0.07fF
+C28 a_n369_n150# a_n657_n150# 0.10fF
+C29 a_687_n150# a_1071_n150# 0.07fF
+C30 a_303_n150# a_111_n150# 0.16fF
+C31 w_n1367_n369# a_1071_n150# 0.07fF
+C32 a_207_n150# a_n81_n150# 0.10fF
+C33 a_n465_n150# a_n81_n150# 0.07fF
+C34 a_495_n150# a_591_n150# 0.43fF
+C35 a_495_n150# a_879_n150# 0.07fF
+C36 a_1167_n150# w_n1367_n369# 0.14fF
+C37 a_n849_n150# a_n1229_n150# 0.07fF
+C38 a_n849_n150# a_n753_n150# 0.43fF
+C39 a_n465_n150# a_n273_n150# 0.16fF
+C40 a_1167_n150# a_1071_n150# 0.43fF
+C41 a_591_n150# a_975_n150# 0.07fF
+C42 a_207_n150# a_n177_n150# 0.07fF
+C43 a_n465_n150# a_n177_n150# 0.10fF
+C44 a_879_n150# a_975_n150# 0.43fF
+C45 a_n945_n150# a_n1041_n150# 0.43fF
+C46 a_495_n150# a_399_n150# 0.43fF
+C47 a_207_n150# a_15_n150# 0.16fF
+C48 a_n81_n150# a_n273_n150# 0.16fF
+C49 a_n81_n150# a_n177_n150# 0.43fF
+C50 a_207_n150# a_591_n150# 0.07fF
+C51 a_591_n150# a_687_n150# 0.43fF
+C52 a_879_n150# a_687_n150# 0.16fF
+C53 a_n945_n150# a_n1229_n150# 0.10fF
+C54 a_n177_n150# a_n273_n150# 0.43fF
+C55 a_n945_n150# a_n753_n150# 0.16fF
+C56 a_n465_n150# a_n753_n150# 0.10fF
+C57 w_n1367_n369# a_879_n150# 0.04fF
+C58 a_n561_n150# a_n849_n150# 0.10fF
+C59 a_n81_n150# a_15_n150# 0.43fF
+C60 a_207_n150# a_399_n150# 0.16fF
+C61 a_n849_n150# a_n657_n150# 0.16fF
+C62 a_495_n150# a_111_n150# 0.07fF
+C63 a_879_n150# a_1071_n150# 0.16fF
+C64 a_399_n150# a_687_n150# 0.10fF
+C65 a_1167_n150# a_879_n150# 0.10fF
+C66 a_15_n150# a_n273_n150# 0.10fF
+C67 a_303_n150# a_495_n150# 0.16fF
+C68 a_15_n150# a_n177_n150# 0.16fF
+C69 a_n849_n150# a_n1137_n150# 0.10fF
+C70 a_n1229_n150# a_n1041_n150# 0.16fF
+C71 a_n753_n150# a_n1041_n150# 0.10fF
+C72 a_207_n150# a_111_n150# 0.43fF
+C73 a_n561_n150# a_n945_n150# 0.07fF
+C74 a_n561_n150# a_n465_n150# 0.43fF
+C75 a_n945_n150# a_n657_n150# 0.10fF
+C76 a_n465_n150# a_n657_n150# 0.16fF
+C77 a_n465_n150# a_n369_n150# 0.43fF
+C78 a_495_n150# a_783_n150# 0.10fF
+C79 a_591_n150# a_879_n150# 0.10fF
+C80 a_207_n150# a_303_n150# 0.43fF
+C81 a_303_n150# a_687_n150# 0.07fF
+C82 a_975_n150# a_783_n150# 0.16fF
+C83 a_399_n150# a_15_n150# 0.07fF
+C84 a_n945_n150# a_n1137_n150# 0.16fF
+C85 a_n81_n150# a_111_n150# 0.16fF
+C86 a_591_n150# a_399_n150# 0.16fF
+C87 a_n81_n150# a_n369_n150# 0.10fF
+C88 a_111_n150# a_n273_n150# 0.07fF
+C89 a_n561_n150# a_n273_n150# 0.10fF
+C90 a_n273_n150# a_n657_n150# 0.07fF
+C91 a_n369_n150# a_n273_n150# 0.43fF
+C92 a_303_n150# a_n81_n150# 0.07fF
+C93 a_111_n150# a_n177_n150# 0.10fF
+C94 a_n561_n150# a_n177_n150# 0.07fF
+C95 a_n369_n150# a_n177_n150# 0.16fF
+C96 a_n1041_n150# a_n657_n150# 0.07fF
+C97 a_687_n150# a_783_n150# 0.43fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vdd nUp vss Down biasp out pswitch iref nDown Up
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 nswitch biasp 0.03fF
+C1 pswitch nswitch 0.06fF
+C2 Down nUp 0.25fF
+C3 Up pswitch 0.70fF
+C4 pswitch nUp 5.66fF
+C5 vdd out 6.66fF
+C6 Down nDown 0.13fF
+C7 pswitch out 4.91fF
+C8 iref biasp 0.80fF
+C9 Up nUp 0.15fF
+C10 out nswitch 1.28fF
+C11 vdd biasp 2.64fF
+C12 vdd pswitch 3.98fF
+C13 nDown nswitch 0.31fF
+C14 out nUp 0.31fF
+C15 pswitch biasp 3.11fF
+C16 iref nswitch 1.91fF
+C17 Down nswitch 2.27fF
+C18 vdd nswitch 0.07fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_81_n156# a_n15_n156# 0.02fF
+C1 a_111_n125# a_15_n125# 0.36fF
+C2 w_n311_n344# a_15_n125# 0.09fF
+C3 w_n311_n344# a_111_n125# 0.14fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_n111_n156# a_n15_n156# 0.02fF
+C6 a_n173_n125# a_15_n125# 0.13fF
+C7 a_n81_n125# a_15_n125# 0.36fF
+C8 a_111_n125# a_n173_n125# 0.08fF
+C9 a_111_n125# a_n81_n125# 0.13fF
+C10 w_n311_n344# a_n173_n125# 0.14fF
+C11 w_n311_n344# a_n81_n125# 0.09fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n15_n151# a_n111_n151# 0.02fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_81_n151# a_n15_n151# 0.02fF
+C3 a_111_n125# a_n173_n125# 0.08fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_n81_n125# a_15_n125# 0.36fF
+C7 a_111_n125# a_n81_n125# 0.13fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_45_n513# vdd 0.69fF
+C1 m1_45_n513# m1_187_n605# 0.36fF
+C2 m1_187_n605# vdd 0.55fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_15_n125# a_n81_n125# 0.36fF
+C2 a_111_n125# a_15_n125# 0.36fF
+C3 a_n173_n125# w_n311_n344# 0.14fF
+C4 a_n81_n125# w_n311_n344# 0.09fF
+C5 a_n173_n125# a_n81_n125# 0.36fF
+C6 a_111_n125# w_n311_n344# 0.14fF
+C7 a_111_n125# a_n173_n125# 0.08fF
+C8 a_111_n125# a_n81_n125# 0.13fF
+C9 a_15_n125# w_n311_n344# 0.09fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n81_n125# 0.13fF
+C1 a_111_n125# a_15_n125# 0.36fF
+C2 a_n173_n125# a_n81_n125# 0.36fF
+C3 a_n173_n125# a_15_n125# 0.13fF
+C4 a_n81_n125# a_15_n125# 0.36fF
+C5 a_111_n125# a_n173_n125# 0.08fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 out vdd 0.10fF
+C1 out in 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_0/out nCLK_d 0.11fF
+C1 vdd inverter_cp_x1_2/in 0.21fF
+C2 vdd nCLK_d 0.03fF
+C3 CLK inverter_cp_x1_2/in 0.31fF
+C4 vdd inverter_cp_x1_0/out 0.28fF
+C5 vdd CLK_d 0.03fF
+C6 CLK inverter_cp_x1_0/out 0.31fF
+C7 vdd CLK 0.36fF
+C8 inverter_cp_x1_2/in CLK_d 0.12fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_63_n95# a_n33_n95# 0.28fF
+C1 a_n125_n95# w_n263_n314# 0.11fF
+C2 a_n125_n95# a_n33_n95# 0.28fF
+C3 w_n263_n314# a_n33_n95# 0.08fF
+C4 a_n125_n95# a_63_n95# 0.10fF
+C5 w_n263_n314# a_63_n95# 0.11fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_15_n125# 0.13fF
+C1 a_n173_n125# a_111_n125# 0.08fF
+C2 a_111_n125# a_15_n125# 0.36fF
+C3 a_n81_n125# a_n129_n213# 0.10fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_n173_n125# a_n129_n213# 0.02fF
+C6 a_n81_n125# a_15_n125# 0.36fF
+C7 a_n129_n213# a_15_n125# 0.10fF
+C8 a_n81_n125# a_111_n125# 0.13fF
+C9 a_n129_n213# a_111_n125# 0.01fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_n81_n183# 0.10fF
+C1 a_n125_n95# a_n33_n95# 0.88fF
+C2 a_n125_n95# a_n81_n183# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 nQ vdd 0.16fF
+C1 nQ Q 0.93fF
+C2 m1_657_280# CLK 0.24fF
+C3 m1_657_280# nQ 1.41fF
+C4 Q vdd 0.16fF
+C5 nQ D 0.05fF
+C6 nQ nD 0.05fF
+C7 m1_657_280# Q 0.94fF
+C8 Q D 0.05fF
+C9 Q nD 0.05fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
++ nCLK latch_diff_0/nD
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C1 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C2 vdd latch_diff_1/nD 0.02fF
+C3 vdd latch_diff_0/D 0.09fF
+C4 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C5 latch_diff_1/D latch_diff_1/nD 0.33fF
+C6 latch_diff_1/D latch_diff_0/D 0.11fF
+C7 latch_diff_0/nD vdd 0.14fF
+C8 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C9 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C10 latch_diff_1/D nQ 0.11fF
+C11 latch_diff_0/nD latch_diff_1/D 0.41fF
+C12 Q latch_diff_1/nD 0.01fF
+C13 latch_diff_1/D vdd 0.03fF
+C14 latch_diff_0/D latch_diff_1/nD 0.04fF
+C15 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C16 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C17 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C18 nQ latch_diff_1/nD 0.08fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n33_n84# a_n129_n84# 0.24fF
+C1 a_n33_n84# a_n221_n84# 0.09fF
+C2 a_n33_n84# w_n359_n303# 0.05fF
+C3 a_n63_n110# a_33_n110# 0.02fF
+C4 a_129_n110# a_33_n110# 0.02fF
+C5 a_n63_n110# a_n159_n110# 0.02fF
+C6 a_159_n84# a_n129_n84# 0.05fF
+C7 a_159_n84# a_n221_n84# 0.04fF
+C8 w_n359_n303# a_159_n84# 0.08fF
+C9 a_n33_n84# a_63_n84# 0.24fF
+C10 a_n221_n84# a_n129_n84# 0.24fF
+C11 w_n359_n303# a_n129_n84# 0.06fF
+C12 w_n359_n303# a_n221_n84# 0.08fF
+C13 a_63_n84# a_159_n84# 0.24fF
+C14 a_63_n84# a_n129_n84# 0.09fF
+C15 a_63_n84# a_n221_n84# 0.05fF
+C16 a_63_n84# w_n359_n303# 0.06fF
+C17 a_n33_n84# a_159_n84# 0.09fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_63_n42# a_n221_n42# 0.03fF
+C1 a_n33_n42# a_n129_n42# 0.12fF
+C2 a_63_n42# a_n33_n42# 0.12fF
+C3 a_159_n42# a_n129_n42# 0.03fF
+C4 a_63_n42# a_159_n42# 0.12fF
+C5 a_63_n42# a_n129_n42# 0.05fF
+C6 a_n221_n42# a_n33_n42# 0.05fF
+C7 a_129_n68# a_33_n68# 0.02fF
+C8 a_n221_n42# a_159_n42# 0.02fF
+C9 a_159_n42# a_n33_n42# 0.05fF
+C10 a_n159_n68# a_n63_n68# 0.02fF
+C11 a_33_n68# a_n63_n68# 0.02fF
+C12 a_n221_n42# a_n129_n42# 0.12fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 out in 0.67fF
+C1 out vdd 0.62fF
+C2 in vdd 0.33fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_n125_n42# a_63_n42# 0.05fF
+C2 a_n125_n42# a_n33_n42# 0.12fF
+C3 a_63_n42# a_n33_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 w_n263_n303# a_n33_n84# 0.07fF
+C1 a_n125_n84# a_63_n84# 0.09fF
+C2 w_n263_n303# a_n125_n84# 0.10fF
+C3 w_n263_n303# a_63_n84# 0.10fF
+C4 a_33_n110# a_n63_n110# 0.02fF
+C5 a_n33_n84# a_n125_n84# 0.24fF
+C6 a_n33_n84# a_63_n84# 0.24fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 out vdd 0.15fF
+C1 in vdd 0.01fF
+C2 in out 0.30fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 nCLK_2 vdd 0.08fF
+C1 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C2 DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.29fF
+C3 DFlipFlop_0/CLK nout_div 0.42fF
+C4 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
+C5 nout_div DFlipFlop_0/nCLK 0.43fF
+C6 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C7 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
+C8 nout_div DFlipFlop_0/latch_diff_1/m1_657_280# 0.21fF
+C9 CLK_2 vdd 0.08fF
+C10 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
+C11 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C12 o2 vdd 0.14fF
+C13 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C14 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C15 DFlipFlop_0/nCLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.46fF
+C16 out_div vdd 0.03fF
+C17 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/nD 0.11fF
+C18 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C19 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C20 CLK_2 o1 0.11fF
+C21 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C22 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C23 nout_div vdd 0.16fF
+C24 nout_div out_div 0.22fF
+C25 DFlipFlop_0/latch_diff_0/D DFlipFlop_0/nCLK 0.13fF
+C26 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/nD 0.12fF
+C27 o1 vdd 0.14fF
+C28 o1 out_div 0.01fF
+C29 DFlipFlop_0/CLK vdd 0.40fF
+C30 vdd DFlipFlop_0/nCLK 0.30fF
+C31 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C32 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C33 nCLK_2 o2 0.11fF
+C34 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
+C35 nCLK_2 vss 1.08fF
+C36 o2 vss 2.21fF
+C37 CLK_2 vss 1.08fF
+C38 o1 vss 2.21fF
+C39 DFlipFlop_0/CLK vss 1.03fF
+C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C42 CLK vss 3.27fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n257_n777# a_n129_n600# 0.29fF
+C1 a_n257_n777# a_n221_n600# 0.25fF
+C2 a_n129_n600# a_n221_n600# 7.87fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n221_n300# a_n129_n300# 4.05fF
+C1 a_n221_n300# a_n257_n404# 0.21fF
+C2 a_n257_n404# a_n129_n300# 0.30fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 out vdd 47.17fF
+C1 vdd a_3996_n100# 3.68fF
+C2 in vdd 0.02fF
+C3 a_678_n100# a_3996_n100# 6.52fF
+C4 a_678_n100# in 0.81fF
+C5 out a_3996_n100# 55.19fF
+C6 a_678_n100# vdd 0.08fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n238# a_n73_n150# 0.02fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 a_15_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_15_n150# 0.51fF
+C1 w_n211_n369# a_n33_181# 0.05fF
+C2 a_15_n150# a_n33_181# 0.01fF
+C3 a_n73_n150# a_n33_181# 0.01fF
+C4 w_n211_n369# a_15_n150# 0.20fF
+C5 a_n73_n150# w_n211_n369# 0.20fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n465_172# a_159_n150# 0.10fF
+C1 a_n465_172# a_447_n150# 0.01fF
+C2 a_n465_172# a_n225_n150# 0.10fF
+C3 a_63_n150# a_n465_172# 0.10fF
+C4 a_n465_172# a_n129_n150# 0.10fF
+C5 a_n465_172# a_n33_n150# 0.10fF
+C6 a_n465_172# a_351_n150# 0.10fF
+C7 a_n417_n150# a_n321_n150# 0.43fF
+C8 a_n321_n150# a_n225_n150# 0.43fF
+C9 a_159_n150# a_255_n150# 0.43fF
+C10 a_n465_172# a_n509_n150# 0.01fF
+C11 a_447_n150# a_255_n150# 0.16fF
+C12 a_n417_n150# a_n225_n150# 0.16fF
+C13 a_447_n150# a_159_n150# 0.10fF
+C14 a_159_n150# a_n225_n150# 0.07fF
+C15 a_63_n150# a_n321_n150# 0.07fF
+C16 a_63_n150# a_255_n150# 0.16fF
+C17 a_n321_n150# a_n129_n150# 0.16fF
+C18 a_63_n150# a_159_n150# 0.43fF
+C19 a_n321_n150# a_n33_n150# 0.10fF
+C20 a_63_n150# a_447_n150# 0.07fF
+C21 a_n417_n150# a_n129_n150# 0.10fF
+C22 a_255_n150# a_n129_n150# 0.07fF
+C23 a_63_n150# a_n225_n150# 0.10fF
+C24 a_n417_n150# a_n33_n150# 0.07fF
+C25 a_n33_n150# a_255_n150# 0.10fF
+C26 a_159_n150# a_n129_n150# 0.10fF
+C27 a_255_n150# a_351_n150# 0.43fF
+C28 a_n33_n150# a_159_n150# 0.16fF
+C29 a_n129_n150# a_n225_n150# 0.43fF
+C30 a_159_n150# a_351_n150# 0.16fF
+C31 a_447_n150# a_351_n150# 0.43fF
+C32 a_n321_n150# a_n509_n150# 0.16fF
+C33 a_n33_n150# a_n225_n150# 0.16fF
+C34 a_n417_n150# a_n509_n150# 0.43fF
+C35 a_63_n150# a_n129_n150# 0.16fF
+C36 a_n509_n150# a_n225_n150# 0.10fF
+C37 a_63_n150# a_n33_n150# 0.43fF
+C38 a_63_n150# a_351_n150# 0.10fF
+C39 a_n33_n150# a_n129_n150# 0.43fF
+C40 a_n33_n150# a_351_n150# 0.07fF
+C41 a_n509_n150# a_n129_n150# 0.07fF
+C42 a_n465_172# a_n321_n150# 0.10fF
+C43 a_n417_n150# a_n465_172# 0.10fF
+C44 a_n465_172# a_255_n150# 0.10fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n321_n150# a_n225_n150# 0.43fF
+C1 a_n33_n150# a_n465_n247# 0.08fF
+C2 a_63_n150# a_n33_n150# 0.43fF
+C3 a_n33_n150# w_n647_n369# 0.02fF
+C4 a_n417_n150# a_n33_n150# 0.07fF
+C5 a_n33_n150# a_n225_n150# 0.16fF
+C6 a_n321_n150# a_n509_n150# 0.16fF
+C7 a_n129_n150# a_n465_n247# 0.08fF
+C8 a_n33_n150# a_159_n150# 0.16fF
+C9 a_63_n150# a_n129_n150# 0.16fF
+C10 a_n129_n150# w_n647_n369# 0.02fF
+C11 a_n129_n150# a_n417_n150# 0.10fF
+C12 a_63_n150# a_n465_n247# 0.08fF
+C13 a_n129_n150# a_n225_n150# 0.43fF
+C14 w_n647_n369# a_n465_n247# 0.47fF
+C15 a_63_n150# w_n647_n369# 0.02fF
+C16 a_n33_n150# a_351_n150# 0.07fF
+C17 a_n417_n150# a_n465_n247# 0.08fF
+C18 a_n129_n150# a_159_n150# 0.10fF
+C19 a_n417_n150# w_n647_n369# 0.07fF
+C20 a_n465_n247# a_n225_n150# 0.08fF
+C21 a_63_n150# a_n225_n150# 0.10fF
+C22 w_n647_n369# a_n225_n150# 0.04fF
+C23 a_n417_n150# a_n225_n150# 0.16fF
+C24 a_255_n150# a_n33_n150# 0.10fF
+C25 a_n465_n247# a_159_n150# 0.08fF
+C26 a_63_n150# a_159_n150# 0.43fF
+C27 a_n129_n150# a_n509_n150# 0.07fF
+C28 w_n647_n369# a_159_n150# 0.04fF
+C29 a_159_n150# a_n225_n150# 0.07fF
+C30 a_n465_n247# a_351_n150# 0.08fF
+C31 w_n647_n369# a_n509_n150# 0.14fF
+C32 a_63_n150# a_447_n150# 0.07fF
+C33 a_63_n150# a_351_n150# 0.10fF
+C34 a_n417_n150# a_n509_n150# 0.43fF
+C35 a_447_n150# w_n647_n369# 0.14fF
+C36 a_255_n150# a_n129_n150# 0.07fF
+C37 w_n647_n369# a_351_n150# 0.07fF
+C38 a_n225_n150# a_n509_n150# 0.10fF
+C39 a_255_n150# a_n465_n247# 0.08fF
+C40 a_255_n150# a_63_n150# 0.16fF
+C41 a_255_n150# w_n647_n369# 0.05fF
+C42 a_447_n150# a_159_n150# 0.10fF
+C43 a_159_n150# a_351_n150# 0.16fF
+C44 a_n33_n150# a_n321_n150# 0.10fF
+C45 a_255_n150# a_159_n150# 0.43fF
+C46 a_447_n150# a_351_n150# 0.43fF
+C47 a_n129_n150# a_n321_n150# 0.16fF
+C48 a_255_n150# a_447_n150# 0.16fF
+C49 a_255_n150# a_351_n150# 0.43fF
+C50 a_n465_n247# a_n321_n150# 0.08fF
+C51 a_63_n150# a_n321_n150# 0.07fF
+C52 w_n647_n369# a_n321_n150# 0.05fF
+C53 a_n129_n150# a_n33_n150# 0.43fF
+C54 a_n417_n150# a_n321_n150# 0.43fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n99# a_n73_n11# 0.02fF
+C1 a_15_n11# a_n33_n99# 0.02fF
+C2 a_15_n11# a_n73_n11# 0.15fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_20_n114# 0.20fF
+C1 a_n78_n114# w_n216_n334# 0.20fF
+C2 a_n78_n114# a_20_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vdd 0.01fF
+C1 in out 0.11fF
+C2 vdd vbulkp 0.04fF
+C3 in vss 0.01fF
+C4 out vbulkp 0.08fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 in inverter_csvco_0/vss 0.01fF
+C1 inverter_csvco_0/vss D0 0.02fF
+C2 out inverter_csvco_0/vss 0.03fF
+C3 inverter_csvco_0/vdd vdd 1.89fF
+C4 cap_vco_0/t vdd 0.04fF
+C5 vbp inverter_csvco_0/vdd 0.75fF
+C6 in out 0.06fF
+C7 vctrl inverter_csvco_0/vss 0.87fF
+C8 out D0 0.09fF
+C9 in inverter_csvco_0/vdd 0.01fF
+C10 vbp vdd 1.21fF
+C11 out inverter_csvco_0/vdd 0.02fF
+C12 cap_vco_0/t out 0.70fF
+C13 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vdd vss csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
+C1 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
+C2 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C3 out_vco csvco_branch_1/in 0.76fF
+C4 vctrl D0 4.41fF
+C5 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C6 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C7 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C8 csvco_branch_2/vbp vdd 1.49fF
+C9 csvco_branch_1/cap_vco_0/t out_vco 0.03fF
+C10 out_vco csvco_branch_2/in 0.58fF
+C11 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss 0.06fF
+C12 csvco_branch_2/vbp vctrl 0.06fF
+C13 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C14 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 o1 out_div 0.11fF
+C1 vdd out_pad 0.10fF
+C2 out_div out_pad 0.15fF
+C3 vdd out_div 0.17fF
+C4 o1 vdd 0.09fF
+C5 in_vco vss 0.83fF
+C6 out_pad vss 0.70fF
+C7 out_div vss 3.00fF
+C8 vdd vss 14.54fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 B X 0.13fF
+C1 VGND X 0.28fF
+C2 a_194_125# a_158_392# 0.06fF
+C3 a_194_125# A 0.18fF
+C4 a_355_368# A 0.02fF
+C5 a_194_125# a_355_368# 0.51fF
+C6 B A 0.28fF
+C7 a_194_125# B 0.57fF
+C8 B a_355_368# 0.08fF
+C9 X VPWR 0.07fF
+C10 VGND A 0.31fF
+C11 VGND a_194_125# 0.25fF
+C12 VGND B 0.10fF
+C13 VPB VPWR 0.06fF
+C14 A VPWR 0.15fF
+C15 a_194_125# VPWR 0.33fF
+C16 a_355_368# VPWR 0.37fF
+C17 B VPWR 0.09fF
+C18 VGND VPWR 0.01fF
+C19 a_194_125# X 0.29fF
+C20 a_355_368# X 0.17fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 X a_56_136# 0.26fF
+C1 X VGND 0.15fF
+C2 VPWR A 0.07fF
+C3 VPWR B 0.02fF
+C4 a_56_136# VGND 0.06fF
+C5 B X 0.02fF
+C6 A a_56_136# 0.17fF
+C7 B a_56_136# 0.30fF
+C8 A VGND 0.21fF
+C9 B VGND 0.03fF
+C10 VPWR VPB 0.04fF
+C11 VPWR X 0.20fF
+C12 B A 0.08fF
+C13 VPWR a_56_136# 0.57fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 a_152_368# a_63_368# 0.03fF
+C1 B VPWR 0.01fF
+C2 B A 0.10fF
+C3 X a_63_368# 0.33fF
+C4 B VGND 0.11fF
+C5 VPWR a_63_368# 0.29fF
+C6 A a_63_368# 0.28fF
+C7 X VPWR 0.18fF
+C8 VPB VPWR 0.04fF
+C9 A X 0.02fF
+C10 VGND a_63_368# 0.27fF
+C11 VGND X 0.16fF
+C12 A VPWR 0.05fF
+C13 B a_63_368# 0.14fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
++ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
++ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
++ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C1 sky130_fd_sc_hs__and2_1_1/a_56_136# CLK 0.06fF
+C2 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C3 nCLK DFlipFlop_3/latch_diff_1/D 0.14fF
+C4 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
+C5 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C6 DFlipFlop_2/D nCLK 0.41fF
+C7 Q1 Q1_shift 0.36fF
+C8 nQ0 nCLK 0.09fF
+C9 Q1 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C10 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C11 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C12 Q0 DFlipFlop_0/D 0.39fF
+C13 DFlipFlop_3/latch_diff_1/nD nCLK 0.09fF
+C14 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
+C15 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C16 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C17 nCLK nQ2 0.10fF
+C18 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK 0.14fF
+C19 DFlipFlop_2/D vdd 0.07fF
+C20 nQ0 vdd 0.11fF
+C21 Q1 DFlipFlop_0/D 0.13fF
+C22 Q0 CLK 0.08fF
+C23 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C24 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C25 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C26 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C27 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
+C28 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C29 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C30 vdd nQ2 0.04fF
+C31 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C32 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C33 Q1 CLK -0.10fF
+C34 sky130_fd_sc_hs__and2_1_1/a_56_136# vdd 0.04fF
+C35 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C36 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
+C37 Q0 nCLK 0.20fF
+C38 Q1 DFlipFlop_3/nQ 0.10fF
+C39 nQ2 DFlipFlop_0/Q 0.09fF
+C40 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C41 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C42 DFlipFlop_1/D CLK 0.21fF
+C43 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C44 Q1 nCLK -0.01fF
+C45 Q1 DFlipFlop_2/nQ 0.31fF
+C46 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C47 nQ0 nQ2 0.03fF
+C48 Q0 vdd 5.33fF
+C49 Q1 DFlipFlop_0/latch_diff_0/D 0.15fF
+C50 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C51 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C52 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C53 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C54 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C55 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
+C56 DFlipFlop_2/latch_diff_0/D Q1 0.42fF
+C57 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C58 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C59 DFlipFlop_1/D nCLK 0.14fF
+C60 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C61 Q1 vdd 9.49fF
+C62 Q0 DFlipFlop_0/Q 0.21fF
+C63 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C64 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C65 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C66 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C67 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
+C68 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C69 Q1_shift DFlipFlop_3/nQ 0.04fF
+C70 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
+C71 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C72 Q1 DFlipFlop_0/Q 0.13fF
+C73 DFlipFlop_2/D Q0 0.25fF
+C74 vdd DFlipFlop_1/D 0.25fF
+C75 Q0 nQ0 0.33fF
+C76 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C77 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C78 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C79 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C80 Q1 DFlipFlop_3/latch_diff_1/D 0.79fF
+C81 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C82 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C83 Q1 DFlipFlop_2/D 0.10fF
+C84 Q1 nQ0 0.06fF
+C85 Q0 nQ2 0.23fF
+C86 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C87 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q0 0.42fF
+C88 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C89 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
+C90 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C91 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C92 vdd Q1_shift 0.10fF
+C93 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.08fF
+C94 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C95 Q1 nQ2 0.07fF
+C96 DFlipFlop_2/latch_diff_1/nD CLK 0.09fF
+C97 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C98 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C99 CLK DFlipFlop_3/nQ 0.01fF
+C100 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q1 0.21fF
+C101 nQ0 DFlipFlop_1/D 0.12fF
+C102 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C103 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C104 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C105 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C106 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C107 Q1 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C108 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C109 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
+C110 CLK DFlipFlop_2/nQ 0.13fF
+C111 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
+C112 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C113 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C114 vdd DFlipFlop_0/D 0.19fF
+C115 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C116 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C117 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C118 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
+C119 DFlipFlop_3/nQ nCLK 0.02fF
+C120 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C121 nQ0 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.04fF
+C122 Q1 Q0 9.65fF
+C123 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C124 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C125 vdd CLK 0.41fF
+C126 Q1_shift sky130_fd_sc_hs__or2_1_0/a_63_368# -0.27fF
+C127 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C128 DFlipFlop_2/nQ nCLK 0.09fF
+C129 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
+C130 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
+C131 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C132 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C133 vdd DFlipFlop_3/nQ 0.02fF
+C134 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C135 vdd CLK_5 0.15fF
+C136 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
+C137 CLK DFlipFlop_0/Q 0.08fF
+C138 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C139 Q0 DFlipFlop_1/D 0.07fF
+C140 DFlipFlop_2/latch_diff_0/D nCLK 0.11fF
+C141 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C142 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_1/D 0.03fF
+C143 nQ0 DFlipFlop_1/latch_diff_0/nD 0.08fF
+C144 vdd nCLK 0.34fF
+C145 vdd DFlipFlop_2/nQ 0.02fF
+C146 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C147 Q1 DFlipFlop_1/D 0.03fF
+C148 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C149 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C150 DFlipFlop_2/D CLK 0.14fF
+C151 nQ0 CLK 0.19fF
+C152 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C153 nCLK DFlipFlop_0/Q 0.11fF
+C154 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q1 0.20fF
+C155 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C156 CLK nQ2 0.17fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 DFlipFlop_2/nQ vss 0.50fF
+C172 Q1 vss 8.55fF
+C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 nQ0 vss 3.42fF
+C183 Q0 vss 0.53fF
+C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n225_n125# a_n317_n125# 0.36fF
+C1 a_129_n151# a_33_n151# 0.02fF
+C2 a_63_n125# a_n129_n125# 0.13fF
+C3 a_63_n125# a_n33_n125# 0.36fF
+C4 a_159_n125# a_255_n125# 0.36fF
+C5 a_63_n125# a_n317_n125# 0.06fF
+C6 a_n129_n125# a_n33_n125# 0.36fF
+C7 a_n129_n125# a_n317_n125# 0.13fF
+C8 a_n33_n125# a_n317_n125# 0.08fF
+C9 a_159_n125# a_n225_n125# 0.06fF
+C10 a_63_n125# a_255_n125# 0.13fF
+C11 a_n255_n151# a_n159_n151# 0.02fF
+C12 a_n63_n151# a_n159_n151# 0.02fF
+C13 a_n129_n125# a_255_n125# 0.06fF
+C14 a_n33_n125# a_255_n125# 0.08fF
+C15 a_n63_n151# a_33_n151# 0.02fF
+C16 a_63_n125# a_159_n125# 0.36fF
+C17 a_63_n125# a_n225_n125# 0.08fF
+C18 a_159_n125# a_n129_n125# 0.08fF
+C19 a_159_n125# a_n33_n125# 0.13fF
+C20 a_n129_n125# a_n225_n125# 0.36fF
+C21 a_n33_n125# a_n225_n125# 0.13fF
+C22 a_129_n151# a_225_n151# 0.02fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_129_n154# a_33_n154# 0.02fF
+C1 a_255_n125# a_63_n125# 0.13fF
+C2 a_255_n125# a_n33_n125# 0.08fF
+C3 a_255_n125# a_n129_n125# 0.06fF
+C4 a_n159_n154# a_n255_n154# 0.02fF
+C5 a_n63_n154# a_33_n154# 0.02fF
+C6 a_159_n125# a_63_n125# 0.36fF
+C7 a_159_n125# a_n33_n125# 0.13fF
+C8 a_159_n125# a_n129_n125# 0.08fF
+C9 w_n455_n344# a_n225_n125# 0.06fF
+C10 a_255_n125# a_159_n125# 0.36fF
+C11 w_n455_n344# a_n317_n125# 0.11fF
+C12 a_n225_n125# a_n317_n125# 0.36fF
+C13 w_n455_n344# a_63_n125# 0.04fF
+C14 w_n455_n344# a_n33_n125# 0.05fF
+C15 a_n225_n125# a_63_n125# 0.08fF
+C16 w_n455_n344# a_n129_n125# 0.04fF
+C17 a_n225_n125# a_n33_n125# 0.13fF
+C18 a_n129_n125# a_n225_n125# 0.36fF
+C19 a_n159_n154# a_n63_n154# 0.02fF
+C20 a_n317_n125# a_63_n125# 0.06fF
+C21 a_n317_n125# a_n33_n125# 0.08fF
+C22 a_255_n125# w_n455_n344# 0.11fF
+C23 a_n129_n125# a_n317_n125# 0.13fF
+C24 a_63_n125# a_n33_n125# 0.36fF
+C25 a_n129_n125# a_63_n125# 0.13fF
+C26 a_159_n125# w_n455_n344# 0.06fF
+C27 a_129_n154# a_225_n154# 0.02fF
+C28 a_n129_n125# a_n33_n125# 0.36fF
+C29 a_159_n125# a_n225_n125# 0.06fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 in out 0.85fF
+C1 vdd out 0.29fF
+C2 vdd in 0.04fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 Down vdd 0.09fF
+C1 Up inverter_cp_x1_2/in 0.12fF
+C2 inverter_cp_x1_0/out nDown 0.11fF
+C3 vdd nUp 0.14fF
+C4 Up vdd 0.60fF
+C5 Down nDown 0.23fF
+C6 vdd nDown 0.80fF
+C7 Down inverter_cp_x1_0/out 0.12fF
+C8 vdd inverter_cp_x1_0/out 0.25fF
+C9 vdd inverter_cp_x1_2/in 0.42fF
+C10 Up nUp 0.20fF
+C11 vdd QA 0.02fF
+C12 vdd QB 0.02fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_63_n90# a_n33_n90# 0.26fF
+C1 a_n63_n116# a_n159_n207# 0.12fF
+C2 a_n221_n90# a_63_n90# 0.06fF
+C3 a_63_n90# a_159_n90# 0.26fF
+C4 w_n359_n309# a_63_n90# 0.06fF
+C5 a_n129_n90# a_n33_n90# 0.26fF
+C6 a_n221_n90# a_n129_n90# 0.26fF
+C7 a_n129_n90# a_159_n90# 0.06fF
+C8 a_n221_n90# a_n33_n90# 0.09fF
+C9 w_n359_n309# a_n129_n90# 0.06fF
+C10 a_159_n90# a_n33_n90# 0.09fF
+C11 a_n221_n90# a_159_n90# 0.04fF
+C12 w_n359_n309# a_n33_n90# 0.05fF
+C13 w_n359_n309# a_n221_n90# 0.09fF
+C14 a_63_n90# a_n129_n90# 0.09fF
+C15 w_n359_n309# a_159_n90# 0.09fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n125_n45# a_n33_n45# 0.13fF
+C1 a_33_n71# a_n129_71# 0.04fF
+C2 a_n125_n45# a_63_n45# 0.05fF
+C3 a_63_n45# a_n33_n45# 0.13fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C1 A vdd 0.09fF
+C2 B out 0.40fF
+C3 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
+C4 A out 0.06fF
+C5 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out 0.08fF
+C6 A B 0.24fF
+C7 vdd out 0.11fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C1 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C2 nor_pfd_2/A Q 1.38fF
+C3 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C4 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C5 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C6 Q nor_pfd_3/A 0.98fF
+C7 nor_pfd_2/B Q 2.22fF
+C8 nor_pfd_2/B nor_pfd_3/A 0.58fF
+C9 CLK Q 0.04fF
+C10 nor_pfd_2/A vdd -0.01fF
+C11 vdd Q 0.08fF
+C12 vdd nor_pfd_3/A 0.09fF
+C13 vdd nor_pfd_2/B 0.02fF
+C14 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C15 Reset Q 0.14fF
+C16 Reset nor_pfd_3/A 0.12fF
+C17 nor_pfd_2/B Reset 0.43fF
+C18 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C19 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n159_n173# a_n63_n71# 0.10fF
+C1 a_n129_n45# a_n221_n45# 0.13fF
+C2 a_63_n45# a_n129_n45# 0.05fF
+C3 a_n33_n45# a_n221_n45# 0.05fF
+C4 a_n129_n45# a_159_n45# 0.03fF
+C5 a_63_n45# a_n33_n45# 0.13fF
+C6 a_159_n45# a_n33_n45# 0.05fF
+C7 a_63_n45# a_n221_n45# 0.03fF
+C8 a_159_n45# a_n221_n45# 0.02fF
+C9 a_63_n45# a_159_n45# 0.13fF
+C10 a_n129_n45# a_n33_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n99_n187# a_33_n187# 0.04fF
+C1 a_63_n90# a_n125_n90# 0.09fF
+C2 a_n33_n90# a_n125_n90# 0.26fF
+C3 a_63_n90# a_n33_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n73_n45# a_15_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 w_n211_n309# a_15_n90# 0.09fF
+C1 a_n73_n90# a_15_n90# 0.31fF
+C2 a_n73_n90# w_n211_n309# 0.04fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
+C1 A B 0.33fF
+C2 vdd a_656_410# 0.20fF
+C3 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C4 A a_656_410# 0.04fF
+C5 vdd A 0.05fF
+C6 a_656_410# out 0.20fF
+C7 vdd out 0.10fF
+C8 a_656_410# B 0.30fF
+C9 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 Down Up 0.06fF
+C1 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C2 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C3 vdd Reset 0.02fF
+C4 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C5 vdd Down 0.08fF
+C6 vdd Up 1.62fF
+C7 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C8 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C9 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v1 pfd_reset in_ref QA QB Down nDown Up nUp biasp pswitch nswitch
++ vco_vctrl vco_D0 vco_out out_first_buffer out_to_div out_div_2 n_out_div_2 n_out_buffer_div_2
++ out_buffer_div_2 out_by_2 n_out_by_2 div_5_Q1_shift out_div_by_5 div_5_Q1 div_5_Q0
++ div_5_nQ0 div_5_nQ2 iref_cp vdd vss lf_vc
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 nswitch vdd nUp vss Down biasp vco_vctrl pswitch iref_cp nDown Up charge_pump
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vss
++ vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 n_out_by_2 div_5_nQ0 0.10fF
+C1 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C3 vco_vctrl nswitch -0.06fF
+C4 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C5 biasp nUp -0.17fF
+C6 vdd nUp 0.05fF
+C7 vco_vctrl out_by_2 0.53fF
+C8 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C9 n_out_by_2 vco_vctrl 0.52fF
+C10 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C11 nswitch Down 0.54fF
+C12 vdd out_div_by_5 0.28fF
+C13 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C14 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
+C15 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C16 nDown Down 2.55fF
+C17 div_5_Q0 out_by_2 0.09fF
+C18 nUp Up 2.72fF
+C19 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C20 n_out_by_2 div_5_Q0 -0.12fF
+C21 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C22 out_by_2 div_5_nQ2 0.16fF
+C23 vdd QA -0.04fF
+C24 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C25 n_out_by_2 div_5_nQ2 0.10fF
+C26 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C27 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# n_out_by_2 -0.05fF
+C28 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
+C29 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C30 nUp nDown -0.09fF
+C31 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C32 div_5_Q1 out_by_2 0.42fF
+C33 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C34 vco_vctrl div_5_Q0 0.48fF
+C35 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
+C36 div_5_Q1 n_out_by_2 1.04fF
+C37 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
+C38 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C39 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C40 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
+C41 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
+C42 vdd iref_cp 0.15fF
+C43 vco_D0 vdd 0.03fF
+C44 vdd out_to_div 0.21fF
+C45 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_to_div -0.16fF
+C46 nUp vco_vctrl 0.02fF
+C47 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
+C48 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C49 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C50 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
+C51 pswitch Up 1.98fF
+C52 out_to_div out_to_buffer 0.13fF
+C53 div_5_Q1 vco_vctrl 0.14fF
+C54 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C55 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
+C56 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
+C57 vdd out_to_buffer 0.07fF
+C58 div_by_5_0/DFlipFlop_1/D out_by_2 0.38fF
+C59 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C60 div_by_5_0/DFlipFlop_0/Q out_by_2 0.09fF
+C61 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C62 biasp Up 0.26fF
+C63 vdd Up 0.28fF
+C64 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_out_by_2 0.12fF
+C65 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C66 pswitch nDown 0.53fF
+C67 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
+C68 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
+C69 vdd buffer_salida_0/a_678_n100# 0.24fF
+C70 div_by_5_0/DFlipFlop_3/latch_diff_0/D out_by_2 0.11fF
+C71 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C72 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
+C73 vdd out_by_2 0.97fF
+C74 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
+C75 vdd n_out_by_2 1.03fF
+C76 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C77 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C78 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C79 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# n_out_by_2 0.01fF
+C80 biasp nDown 0.26fF
+C81 vdd nDown 0.22fF
+C82 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
+C83 div_5_Q1 out_div_by_5 0.01fF
+C84 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
+C85 out_div_by_5 div_5_Q1_shift 0.05fF
+C86 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C87 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
+C88 iref_cp Down 0.09fF
+C89 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
+C90 vdd vco_vctrl -1.02fF
+C91 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C92 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.17fF
+C93 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C94 biasp Down 1.24fF
+C95 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
+C96 vdd lf_vc 0.02fF
+C97 nDown nswitch 0.76fF
+C98 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C99 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C100 pswitch nUp 0.85fF
+C101 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
+C102 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
+C103 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
+C104 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
+C105 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
+C106 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C107 div_5_nQ0 out_by_2 0.32fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.93fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss 1.39fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.76fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 6.05fF
+C141 Up vss 2.16fF
+C142 Down vss 6.16fF
+C143 nDown vss 3.38fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C158 div_5_Q1 vss 4.28fF
+C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_nQ0 vss 0.59fF
+C169 div_5_Q0 vss 0.01fF
+C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_to_buffer vss 1.57fF
+C196 out_to_div vss 4.46fF
+C197 out_first_buffer vss 2.88fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 vco_D0 vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 n_out_buffer_div_2 vss 1.63fF
+C216 out_buffer_div_2 vss 1.60fF
+C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 nswitch vss 3.73fF
+C232 biasp vss 5.44fF
+C233 iref_cp vss 2.81fF
+C234 vco_vctrl vss -19.28fF
+C235 pswitch vss 3.57fF
+C236 lf_vc vss -59.89fF
+C237 loop_filter_0/res_loop_filter_2/out vss 7.90fF
+.ends
+
diff --git a/mag/extractions/top_pll_v2_lvs.spice b/mag/extractions/top_pll_v2_lvs.spice
new file mode 100644
index 0000000..ece73dc
--- /dev/null
+++ b/mag/extractions/top_pll_v2_lvs.spice
@@ -0,0 +1,801 @@
+* NGSPICE file created from top_pll_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt charge_pump Down out iref pswitch nDown biasp Up nswitch vss vdd nUp
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x1 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+.ends
+
+.subckt clock_inverter vss CLK vdd CLK_d nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt latch_diff nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+.ends
+
+.subckt DFlipFlop vss nQ Q vdd CLK nCLK D
+Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
++ latch_diff
+Xlatch_diff_1 nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D latch_diff
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+.ends
+
+.subckt div_by_2 vss vdd CLK_2 nCLK_2 o1 CLK out_div o2 nout_div
+XDFlipFlop_0 vss nout_div out_div vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK nout_div DFlipFlop
+Xclock_inverter_0 vss CLK vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+.ends
+
+.subckt buffer_salida in out vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+*C1 t VSUBS 0.42fF
+*C2 b VSUBS 0.09fF
+.ends
+
+
+.subckt csvco_branch vctrl in vbp D0 out vss vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+.ends
+
+.subckt ring_osc vctrl vdd vss D0 out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp D0 csvco_branch_1/in vss vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp D0 out_vco vss vdd csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp D0 csvco_branch_2/in vss
++ vdd csvco_branch
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt div_by_5 nCLK vdd Q0 CLK nQ0 CLK_5 nQ2 vss Q1 Q1_shift
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 vss nQ2 DFlipFlop_0/Q vdd CLK nCLK DFlipFlop_0/D DFlipFlop
+XDFlipFlop_1 vss nQ0 Q0 vdd CLK nCLK DFlipFlop_1/D DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ Q1 vdd CLK nCLK DFlipFlop_2/D DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ Q1_shift vdd nCLK CLK Q1 DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+.ends
+
+.subckt pfd_cp_interface vss vdd Down QA QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 QB vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
+Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS w_n359_n309# a_n63_n116# a_n159_n207#
++ a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt nor_pfd out vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss vdd B A out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+.ends
+
+.subckt dff_pfd vss vdd Q CLK Reset
+Xnor_pfd_0 nor_pfd_2/A vss vdd CLK Q nor_pfd
+Xnor_pfd_1 Q vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_3/A vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_2/B vss vdd nor_pfd_3/A Reset nor_pfd
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt and_pfd vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd Up A Reset dff_pfd
+Xdff_pfd_1 vss vdd Down B Reset dff_pfd
+Xand_pfd_0 vss Reset vdd Up Down and_pfd
+.ends
+
+
+* Top level circuit top_pll_v2
+
+Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss D0_vco vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 n_out_by_2 vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2 vss
++ div_5_Q1 div_5_Q1_shift div_by_5
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+.end
+
diff --git a/mag/extractions/top_pll_v2_lvs_port.spice b/mag/extractions/top_pll_v2_lvs_port.spice
new file mode 100644
index 0000000..0fa9e5a
--- /dev/null
+++ b/mag/extractions/top_pll_v2_lvs_port.spice
@@ -0,0 +1,794 @@
+* NGSPICE file created from top_pll_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt charge_pump Down out iref pswitch nDown biasp Up nswitch vss vdd nUp
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x1 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+.ends
+
+.subckt clock_inverter vss CLK vdd CLK_d nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt latch_diff nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+.ends
+
+.subckt DFlipFlop vss nQ Q vdd CLK nCLK D
+Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
++ latch_diff
+Xlatch_diff_1 nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D latch_diff
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+.ends
+
+.subckt div_by_2 vss vdd CLK_2 nCLK_2 o1 CLK out_div o2 nout_div
+XDFlipFlop_0 vss nout_div out_div vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK nout_div DFlipFlop
+Xclock_inverter_0 vss CLK vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+.ends
+
+.subckt buffer_salida in out vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt csvco_branch vctrl in vbp D0 out vss vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+.ends
+
+.subckt ring_osc vctrl vdd vss D0 out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp D0 csvco_branch_1/in vss vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp D0 out_vco vss vdd csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp D0 csvco_branch_2/in vss
++ vdd csvco_branch
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt div_by_5 nCLK vdd Q0 CLK nQ0 CLK_5 nQ2 vss Q1 Q1_shift
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 vss nQ2 DFlipFlop_0/Q vdd CLK nCLK DFlipFlop_0/D DFlipFlop
+XDFlipFlop_1 vss nQ0 Q0 vdd CLK nCLK DFlipFlop_1/D DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ Q1 vdd CLK nCLK DFlipFlop_2/D DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ Q1_shift vdd nCLK CLK Q1 DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+.ends
+
+.subckt pfd_cp_interface vss vdd Down QA QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 QB vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
+Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS w_n359_n309# a_n63_n116# a_n159_n207#
++ a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt nor_pfd out vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss vdd B A out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+.ends
+
+.subckt dff_pfd vss vdd Q CLK Reset
+Xnor_pfd_0 nor_pfd_2/A vss vdd CLK Q nor_pfd
+Xnor_pfd_1 Q vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_3/A vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_2/B vss vdd nor_pfd_3/A Reset nor_pfd
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt and_pfd vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd Up A Reset dff_pfd
+Xdff_pfd_1 vss vdd Down B Reset dff_pfd
+Xand_pfd_0 vss Reset vdd Up Down and_pfd
+.ends
+
+.subckt top_pll_v2 pfd_reset in_ref QA QB Down nDown Up nUp biasp pswitch nswitch
++ vco_vctrl vco_out out_first_buffer out_to_div out_div_2 n_out_div_2 n_out_buffer_div_2
++ out_buffer_div_2 out_by_2 n_out_by_2 div_5_Q1_shift out_div_by_5 div_5_Q1 div_5_Q0
++ div_5_nQ0 div_5_nQ2 iref_cp vdd vss lf_vc D0_vco
+Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss D0_vco vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 n_out_by_2 vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2 vss
++ div_5_Q1 div_5_Q1_shift div_by_5
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+.ends
+
diff --git a/mag/extractions/top_pll_v2_pex_c.spice b/mag/extractions/top_pll_v2_pex_c.spice
new file mode 100644
index 0000000..dece08e
--- /dev/null
+++ b/mag/extractions/top_pll_v2_pex_c.spice
@@ -0,0 +1,2927 @@
+* NGSPICE file created from top_pll_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_1803_n486# w_n2457_n634# 0.02fF
+C1 a_n29_n486# w_n2457_n634# 0.02fF
+C2 a_n487_n486# w_n2457_n634# 0.02fF
+C3 a_n945_n486# w_n2457_n634# 0.02fF
+C4 a_n1861_n486# w_n2457_n634# 0.02fF
+C5 a_n1403_n486# w_n2457_n634# 0.02fF
+C6 a_2261_n486# w_n2457_n634# 0.02fF
+C7 a_n2319_n486# w_n2457_n634# 0.02fF
+C8 a_429_n486# w_n2457_n634# 0.02fF
+C9 a_1345_n486# w_n2457_n634# 0.02fF
+C10 a_887_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n81_n75# a_n369_n75# 0.05fF
+C1 a_n849_n75# a_n465_n75# 0.03fF
+C2 a_591_n75# a_879_n75# 0.05fF
+C3 a_495_n75# a_399_n75# 0.22fF
+C4 a_n369_n75# a_n465_n75# 0.22fF
+C5 a_783_n75# a_1167_n75# 0.03fF
+C6 a_687_n75# a_783_n75# 0.22fF
+C7 a_591_n75# a_303_n75# 0.05fF
+C8 a_n657_n75# a_n273_n75# 0.03fF
+C9 a_n945_n75# a_n561_n75# 0.03fF
+C10 a_n177_n75# a_n273_n75# 0.22fF
+C11 a_111_n75# a_15_n75# 0.22fF
+C12 a_1071_n75# a_879_n75# 0.08fF
+C13 a_n753_n75# a_n1041_n75# 0.05fF
+C14 a_n1137_n75# a_n753_n75# 0.03fF
+C15 a_591_n75# a_495_n75# 0.22fF
+C16 a_591_n75# a_399_n75# 0.08fF
+C17 a_n81_n75# a_207_n75# 0.05fF
+C18 a_n753_n75# a_n561_n75# 0.08fF
+C19 a_n273_n75# a_n369_n75# 0.22fF
+C20 a_n753_n75# a_n945_n75# 0.08fF
+C21 a_591_n75# a_975_n75# 0.03fF
+C22 a_879_n75# a_783_n75# 0.22fF
+C23 a_n849_n75# a_n657_n75# 0.08fF
+C24 a_n657_n75# a_n369_n75# 0.05fF
+C25 a_n177_n75# a_n369_n75# 0.08fF
+C26 a_303_n75# a_207_n75# 0.22fF
+C27 a_1071_n75# a_975_n75# 0.22fF
+C28 a_495_n75# a_783_n75# 0.05fF
+C29 a_111_n75# a_n81_n75# 0.08fF
+C30 a_399_n75# a_783_n75# 0.03fF
+C31 a_n561_n75# a_n465_n75# 0.22fF
+C32 a_207_n75# a_495_n75# 0.05fF
+C33 a_15_n75# a_n81_n75# 0.22fF
+C34 a_207_n75# a_399_n75# 0.08fF
+C35 a_975_n75# a_783_n75# 0.08fF
+C36 a_591_n75# a_783_n75# 0.08fF
+C37 a_n177_n75# a_207_n75# 0.03fF
+C38 a_111_n75# a_303_n75# 0.08fF
+C39 a_591_n75# a_207_n75# 0.03fF
+C40 a_n753_n75# a_n465_n75# 0.05fF
+C41 a_111_n75# a_n273_n75# 0.03fF
+C42 a_15_n75# a_303_n75# 0.05fF
+C43 a_n273_n75# a_n561_n75# 0.05fF
+C44 a_n657_n75# a_n1041_n75# 0.03fF
+C45 a_111_n75# a_495_n75# 0.03fF
+C46 a_1071_n75# a_783_n75# 0.05fF
+C47 a_111_n75# a_399_n75# 0.05fF
+C48 a_15_n75# a_n273_n75# 0.05fF
+C49 a_n657_n75# a_n561_n75# 0.22fF
+C50 a_111_n75# a_n177_n75# 0.05fF
+C51 a_n177_n75# a_n561_n75# 0.03fF
+C52 a_n657_n75# a_n945_n75# 0.05fF
+C53 a_15_n75# a_399_n75# 0.03fF
+C54 a_879_n75# a_1167_n75# 0.05fF
+C55 a_n1229_n75# a_n849_n75# 0.03fF
+C56 a_879_n75# a_687_n75# 0.08fF
+C57 a_n81_n75# a_n465_n75# 0.03fF
+C58 a_n849_n75# a_n1041_n75# 0.08fF
+C59 a_n1137_n75# a_n849_n75# 0.05fF
+C60 a_15_n75# a_n177_n75# 0.08fF
+C61 a_687_n75# a_303_n75# 0.03fF
+C62 a_n849_n75# a_n561_n75# 0.05fF
+C63 a_n849_n75# a_n945_n75# 0.22fF
+C64 a_n753_n75# a_n657_n75# 0.22fF
+C65 a_n369_n75# a_n561_n75# 0.08fF
+C66 a_687_n75# a_495_n75# 0.08fF
+C67 a_n81_n75# a_303_n75# 0.03fF
+C68 a_687_n75# a_399_n75# 0.05fF
+C69 a_15_n75# a_n369_n75# 0.03fF
+C70 a_n81_n75# a_n273_n75# 0.08fF
+C71 a_975_n75# a_1167_n75# 0.08fF
+C72 a_n273_n75# a_n465_n75# 0.08fF
+C73 a_975_n75# a_687_n75# 0.05fF
+C74 a_n849_n75# a_n753_n75# 0.22fF
+C75 a_591_n75# a_687_n75# 0.22fF
+C76 a_n753_n75# a_n369_n75# 0.03fF
+C77 a_111_n75# a_207_n75# 0.22fF
+C78 a_n81_n75# a_n177_n75# 0.22fF
+C79 a_n1229_n75# a_n1041_n75# 0.08fF
+C80 a_n1229_n75# a_n1137_n75# 0.22fF
+C81 a_n657_n75# a_n465_n75# 0.08fF
+C82 a_n177_n75# a_n465_n75# 0.05fF
+C83 a_879_n75# a_495_n75# 0.03fF
+C84 a_n1137_n75# a_n1041_n75# 0.22fF
+C85 a_1071_n75# a_1167_n75# 0.22fF
+C86 a_15_n75# a_207_n75# 0.08fF
+C87 a_303_n75# a_495_n75# 0.08fF
+C88 a_1071_n75# a_687_n75# 0.03fF
+C89 a_303_n75# a_399_n75# 0.22fF
+C90 a_n1229_n75# a_n945_n75# 0.05fF
+C91 a_879_n75# a_975_n75# 0.22fF
+C92 a_n1041_n75# a_n945_n75# 0.22fF
+C93 a_n1137_n75# a_n945_n75# 0.08fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_159_n75# a_63_n75# 0.22fF
+C1 a_351_n75# a_735_n75# 0.03fF
+C2 a_n801_n75# a_n417_n75# 0.03fF
+C3 a_831_n75# a_735_n75# 0.22fF
+C4 a_n927_n101# a_33_n101# 0.08fF
+C5 a_543_n75# a_159_n75# 0.03fF
+C6 a_255_n75# a_639_n75# 0.03fF
+C7 a_n513_n75# a_n609_n75# 0.22fF
+C8 a_n897_n75# a_n609_n75# 0.05fF
+C9 a_n225_n75# a_n321_n75# 0.22fF
+C10 a_n801_n75# a_n989_n75# 0.08fF
+C11 a_351_n75# a_n33_n75# 0.03fF
+C12 a_n417_n75# a_n129_n75# 0.05fF
+C13 a_n897_n75# a_n513_n75# 0.03fF
+C14 a_351_n75# a_159_n75# 0.08fF
+C15 a_447_n75# a_639_n75# 0.08fF
+C16 a_447_n75# a_255_n75# 0.08fF
+C17 a_351_n75# a_63_n75# 0.05fF
+C18 a_n801_n75# a_n609_n75# 0.08fF
+C19 a_351_n75# a_543_n75# 0.08fF
+C20 a_543_n75# a_831_n75# 0.05fF
+C21 a_927_n75# a_735_n75# 0.08fF
+C22 a_n801_n75# a_n513_n75# 0.05fF
+C23 a_n321_n75# a_n705_n75# 0.03fF
+C24 a_n33_n75# a_n129_n75# 0.22fF
+C25 a_n801_n75# a_n897_n75# 0.22fF
+C26 a_n225_n75# a_n417_n75# 0.08fF
+C27 a_159_n75# a_n129_n75# 0.05fF
+C28 a_639_n75# a_735_n75# 0.22fF
+C29 a_n321_n75# a_n417_n75# 0.22fF
+C30 a_n129_n75# a_63_n75# 0.08fF
+C31 a_n513_n75# a_n129_n75# 0.03fF
+C32 a_n225_n75# a_n33_n75# 0.08fF
+C33 a_n33_n75# a_255_n75# 0.05fF
+C34 a_447_n75# a_735_n75# 0.05fF
+C35 a_n225_n75# a_159_n75# 0.03fF
+C36 a_n321_n75# a_n33_n75# 0.05fF
+C37 a_543_n75# a_927_n75# 0.03fF
+C38 a_159_n75# a_255_n75# 0.22fF
+C39 a_n225_n75# a_n609_n75# 0.03fF
+C40 a_n417_n75# a_n705_n75# 0.05fF
+C41 a_n225_n75# a_63_n75# 0.05fF
+C42 a_255_n75# a_63_n75# 0.08fF
+C43 a_n321_n75# a_n609_n75# 0.05fF
+C44 a_543_n75# a_639_n75# 0.22fF
+C45 a_n225_n75# a_n513_n75# 0.05fF
+C46 a_543_n75# a_255_n75# 0.05fF
+C47 a_n321_n75# a_63_n75# 0.03fF
+C48 a_n989_n75# a_n705_n75# 0.05fF
+C49 a_447_n75# a_159_n75# 0.05fF
+C50 a_n321_n75# a_n513_n75# 0.08fF
+C51 a_927_n75# a_831_n75# 0.22fF
+C52 a_447_n75# a_63_n75# 0.03fF
+C53 a_351_n75# a_639_n75# 0.05fF
+C54 a_351_n75# a_255_n75# 0.22fF
+C55 a_n609_n75# a_n705_n75# 0.22fF
+C56 a_447_n75# a_543_n75# 0.22fF
+C57 a_831_n75# a_639_n75# 0.08fF
+C58 a_n417_n75# a_n33_n75# 0.03fF
+C59 a_n513_n75# a_n705_n75# 0.08fF
+C60 a_n897_n75# a_n705_n75# 0.08fF
+C61 a_n417_n75# a_n609_n75# 0.08fF
+C62 a_351_n75# a_447_n75# 0.22fF
+C63 a_447_n75# a_831_n75# 0.03fF
+C64 a_n225_n75# a_n129_n75# 0.22fF
+C65 a_n417_n75# a_n513_n75# 0.22fF
+C66 a_n129_n75# a_255_n75# 0.03fF
+C67 a_543_n75# a_735_n75# 0.08fF
+C68 a_n989_n75# a_n609_n75# 0.03fF
+C69 a_n33_n75# a_159_n75# 0.08fF
+C70 a_n801_n75# a_n705_n75# 0.22fF
+C71 a_n321_n75# a_n129_n75# 0.08fF
+C72 a_n33_n75# a_63_n75# 0.22fF
+C73 a_927_n75# a_639_n75# 0.05fF
+C74 a_n989_n75# a_n897_n75# 0.22fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n989_n150# a_n801_n150# 0.16fF
+C1 a_n417_n150# a_n513_n150# 0.43fF
+C2 a_159_n150# a_543_n150# 0.07fF
+C3 a_n129_n150# a_63_n150# 0.16fF
+C4 a_33_n247# a_n927_n247# 0.09fF
+C5 a_n33_n150# a_n417_n150# 0.07fF
+C6 a_n321_n150# a_n705_n150# 0.07fF
+C7 a_n33_n150# a_351_n150# 0.07fF
+C8 a_447_n150# a_351_n150# 0.43fF
+C9 a_63_n150# a_255_n150# 0.16fF
+C10 a_n989_n150# a_n705_n150# 0.10fF
+C11 a_735_n150# a_639_n150# 0.43fF
+C12 a_n225_n150# a_n609_n150# 0.07fF
+C13 a_831_n150# a_447_n150# 0.07fF
+C14 a_n225_n150# a_n417_n150# 0.16fF
+C15 a_n129_n150# a_n321_n150# 0.16fF
+C16 a_927_n150# a_831_n150# 0.43fF
+C17 a_n225_n150# a_n513_n150# 0.10fF
+C18 a_159_n150# a_351_n150# 0.16fF
+C19 a_n225_n150# a_n33_n150# 0.16fF
+C20 a_159_n150# a_n33_n150# 0.16fF
+C21 a_159_n150# a_447_n150# 0.10fF
+C22 a_639_n150# a_255_n150# 0.07fF
+C23 a_735_n150# a_543_n150# 0.16fF
+C24 a_63_n150# a_351_n150# 0.10fF
+C25 a_n897_n150# a_n609_n150# 0.10fF
+C26 a_n129_n150# a_255_n150# 0.07fF
+C27 a_639_n150# a_543_n150# 0.43fF
+C28 a_n801_n150# a_n609_n150# 0.16fF
+C29 a_159_n150# a_n225_n150# 0.07fF
+C30 a_n33_n150# a_63_n150# 0.43fF
+C31 a_447_n150# a_63_n150# 0.07fF
+C32 a_n801_n150# a_n417_n150# 0.07fF
+C33 a_n897_n150# a_n513_n150# 0.07fF
+C34 a_n609_n150# a_n705_n150# 0.43fF
+C35 a_n609_n150# a_n321_n150# 0.10fF
+C36 a_n801_n150# a_n513_n150# 0.10fF
+C37 a_n989_n150# a_n609_n150# 0.07fF
+C38 a_n417_n150# a_n705_n150# 0.10fF
+C39 a_735_n150# a_351_n150# 0.07fF
+C40 a_n417_n150# a_n321_n150# 0.43fF
+C41 a_543_n150# a_255_n150# 0.10fF
+C42 a_n225_n150# a_63_n150# 0.10fF
+C43 a_n513_n150# a_n705_n150# 0.16fF
+C44 a_n321_n150# a_n513_n150# 0.16fF
+C45 a_159_n150# a_63_n150# 0.43fF
+C46 a_639_n150# a_351_n150# 0.10fF
+C47 a_735_n150# a_447_n150# 0.10fF
+C48 a_n33_n150# a_n321_n150# 0.10fF
+C49 a_735_n150# a_831_n150# 0.43fF
+C50 a_735_n150# a_927_n150# 0.16fF
+C51 a_n129_n150# a_n417_n150# 0.10fF
+C52 a_639_n150# a_447_n150# 0.16fF
+C53 a_831_n150# a_639_n150# 0.16fF
+C54 a_n129_n150# a_n513_n150# 0.07fF
+C55 a_927_n150# a_639_n150# 0.10fF
+C56 a_n225_n150# a_n321_n150# 0.43fF
+C57 a_351_n150# a_255_n150# 0.43fF
+C58 a_n129_n150# a_n33_n150# 0.43fF
+C59 a_n33_n150# a_255_n150# 0.10fF
+C60 a_447_n150# a_255_n150# 0.16fF
+C61 a_543_n150# a_351_n150# 0.16fF
+C62 a_n225_n150# a_n129_n150# 0.43fF
+C63 a_159_n150# a_n129_n150# 0.10fF
+C64 a_543_n150# a_447_n150# 0.43fF
+C65 a_n897_n150# a_n801_n150# 0.43fF
+C66 a_831_n150# a_543_n150# 0.10fF
+C67 a_63_n150# a_n321_n150# 0.07fF
+C68 a_927_n150# a_543_n150# 0.07fF
+C69 a_n609_n150# a_n417_n150# 0.16fF
+C70 a_159_n150# a_255_n150# 0.43fF
+C71 a_n897_n150# a_n705_n150# 0.16fF
+C72 a_n609_n150# a_n513_n150# 0.43fF
+C73 a_n801_n150# a_n705_n150# 0.43fF
+C74 a_n897_n150# a_n989_n150# 0.43fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n1103_n44# a_n745_n44# 0.04fF
+C1 a_n1461_n44# a_n1819_n44# 0.04fF
+C2 a_n387_n44# a_n745_n44# 0.04fF
+C3 a_687_n44# a_1045_n44# 0.04fF
+C4 a_329_n44# a_n29_n44# 0.04fF
+C5 a_1403_n44# a_1045_n44# 0.04fF
+C6 a_n387_n44# a_n29_n44# 0.04fF
+C7 a_329_n44# a_687_n44# 0.04fF
+C8 a_n1461_n44# a_n1103_n44# 0.04fF
+C9 a_1403_n44# a_1761_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_207_n150# a_399_n150# 0.16fF
+C1 a_n273_n150# a_n369_n150# 0.43fF
+C2 a_783_n150# a_495_n150# 0.10fF
+C3 a_399_n150# a_303_n150# 0.43fF
+C4 a_591_n150# a_495_n150# 0.43fF
+C5 a_n177_n150# a_n561_n150# 0.07fF
+C6 a_n945_n150# a_n1041_n150# 0.43fF
+C7 a_n81_n150# a_n177_n150# 0.43fF
+C8 a_879_n150# a_783_n150# 0.43fF
+C9 a_111_n150# a_399_n150# 0.10fF
+C10 a_591_n150# a_879_n150# 0.10fF
+C11 a_207_n150# a_15_n150# 0.16fF
+C12 a_n849_n150# a_n465_n150# 0.07fF
+C13 a_15_n150# a_303_n150# 0.10fF
+C14 a_n753_n150# a_n1137_n150# 0.07fF
+C15 a_975_n150# w_n1367_n369# 0.05fF
+C16 a_591_n150# a_783_n150# 0.16fF
+C17 a_1071_n150# w_n1367_n369# 0.07fF
+C18 a_687_n150# a_495_n150# 0.16fF
+C19 a_n849_n150# a_n1041_n150# 0.16fF
+C20 a_1071_n150# a_975_n150# 0.43fF
+C21 a_111_n150# a_15_n150# 0.43fF
+C22 a_n1229_n150# a_n1041_n150# 0.16fF
+C23 a_1167_n150# w_n1367_n369# 0.14fF
+C24 a_879_n150# a_687_n150# 0.16fF
+C25 a_975_n150# a_1167_n150# 0.16fF
+C26 a_207_n150# a_495_n150# 0.10fF
+C27 a_n849_n150# a_n945_n150# 0.43fF
+C28 a_495_n150# a_303_n150# 0.16fF
+C29 a_1071_n150# a_1167_n150# 0.43fF
+C30 a_n1229_n150# a_n945_n150# 0.10fF
+C31 a_n273_n150# a_15_n150# 0.10fF
+C32 a_687_n150# a_783_n150# 0.43fF
+C33 a_591_n150# a_687_n150# 0.43fF
+C34 a_207_n150# a_n177_n150# 0.07fF
+C35 a_n369_n150# a_15_n150# 0.07fF
+C36 a_111_n150# a_495_n150# 0.07fF
+C37 a_n81_n150# a_207_n150# 0.10fF
+C38 a_n753_n150# a_n465_n150# 0.10fF
+C39 a_n81_n150# a_303_n150# 0.07fF
+C40 a_591_n150# a_207_n150# 0.07fF
+C41 a_n657_n150# a_n465_n150# 0.16fF
+C42 a_n1229_n150# a_n849_n150# 0.07fF
+C43 a_591_n150# a_303_n150# 0.10fF
+C44 a_111_n150# a_n177_n150# 0.10fF
+C45 a_n753_n150# a_n1041_n150# 0.10fF
+C46 a_n657_n150# a_n273_n150# 0.07fF
+C47 a_n81_n150# a_111_n150# 0.16fF
+C48 a_n753_n150# a_n369_n150# 0.07fF
+C49 a_n657_n150# a_n1041_n150# 0.07fF
+C50 a_n465_n150# a_n561_n150# 0.43fF
+C51 a_n465_n150# a_n177_n150# 0.10fF
+C52 a_n657_n150# a_n369_n150# 0.10fF
+C53 a_n81_n150# a_n465_n150# 0.07fF
+C54 a_n753_n150# a_n945_n150# 0.16fF
+C55 a_n273_n150# a_n561_n150# 0.10fF
+C56 a_399_n150# a_15_n150# 0.07fF
+C57 a_n273_n150# a_n177_n150# 0.43fF
+C58 a_n657_n150# a_n945_n150# 0.10fF
+C59 a_n81_n150# a_n273_n150# 0.16fF
+C60 a_n369_n150# a_n561_n150# 0.16fF
+C61 a_n177_n150# a_n369_n150# 0.16fF
+C62 a_687_n150# a_303_n150# 0.07fF
+C63 a_n81_n150# a_n369_n150# 0.10fF
+C64 a_879_n150# w_n1367_n369# 0.04fF
+C65 a_n945_n150# a_n561_n150# 0.07fF
+C66 a_879_n150# a_975_n150# 0.43fF
+C67 a_n753_n150# a_n849_n150# 0.43fF
+C68 a_207_n150# a_303_n150# 0.43fF
+C69 a_879_n150# a_1071_n150# 0.16fF
+C70 a_n657_n150# a_n849_n150# 0.16fF
+C71 a_495_n150# a_399_n150# 0.43fF
+C72 a_975_n150# a_783_n150# 0.16fF
+C73 a_591_n150# a_975_n150# 0.07fF
+C74 a_879_n150# a_1167_n150# 0.10fF
+C75 a_1071_n150# a_783_n150# 0.10fF
+C76 a_111_n150# a_207_n150# 0.43fF
+C77 a_n849_n150# a_n561_n150# 0.10fF
+C78 a_n1041_n150# a_n1137_n150# 0.43fF
+C79 a_111_n150# a_303_n150# 0.16fF
+C80 a_1167_n150# a_783_n150# 0.07fF
+C81 a_783_n150# a_399_n150# 0.07fF
+C82 a_591_n150# a_399_n150# 0.16fF
+C83 a_n945_n150# a_n1137_n150# 0.16fF
+C84 a_975_n150# a_687_n150# 0.10fF
+C85 a_n177_n150# a_15_n150# 0.16fF
+C86 a_1071_n150# a_687_n150# 0.07fF
+C87 a_n81_n150# a_15_n150# 0.43fF
+C88 a_111_n150# a_n273_n150# 0.07fF
+C89 a_n753_n150# a_n657_n150# 0.43fF
+C90 a_n849_n150# a_n1137_n150# 0.10fF
+C91 a_n465_n150# a_n273_n150# 0.16fF
+C92 a_n1229_n150# a_n1137_n150# 0.43fF
+C93 a_687_n150# a_399_n150# 0.10fF
+C94 a_n753_n150# a_n561_n150# 0.16fF
+C95 a_n465_n150# a_n369_n150# 0.43fF
+C96 a_879_n150# a_495_n150# 0.07fF
+C97 a_n657_n150# a_n561_n150# 0.43fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vdd nUp vss Down biasp out pswitch iref nDown Up
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 pswitch vdd 3.98fF
+C1 pswitch nUp 5.66fF
+C2 pswitch nswitch 0.06fF
+C3 nUp Down 0.25fF
+C4 Down nswitch 2.27fF
+C5 vdd nswitch 0.07fF
+C6 iref nswitch 1.91fF
+C7 pswitch biasp 3.11fF
+C8 vdd biasp 2.64fF
+C9 biasp nswitch 0.03fF
+C10 iref biasp 0.80fF
+C11 pswitch out 4.91fF
+C12 nDown Down 0.13fF
+C13 vdd out 6.66fF
+C14 out nUp 0.31fF
+C15 nDown nswitch 0.31fF
+C16 out nswitch 1.28fF
+C17 Up pswitch 0.70fF
+C18 Up nUp 0.15fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C1 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C2 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C3 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C4 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C5 m3_7988_2700# m3_2669_2700# 2.73fF
+C6 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C7 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C8 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C9 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C10 m3_2669_8000# m3_7988_8000# 2.73fF
+C11 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C12 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C13 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C14 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C15 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C16 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C17 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C18 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C19 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C20 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C21 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C22 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
+C23 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C24 m3_2669_2700# m3_n2650_2700# 2.73fF
+C25 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C26 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C27 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C28 m3_2669_8000# m3_2669_2700# 3.28fF
+C29 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C30 m3_7988_n2600# m3_7988_2700# 3.39fF
+C31 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C32 m3_n2650_8000# m3_2669_8000# 2.73fF
+C33 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C34 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C35 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C36 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C37 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C38 m3_2669_2700# m3_2669_n2600# 3.28fF
+C39 m3_2669_8000# c1_n13188_n13100# 58.61fF
+C40 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C41 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C42 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C43 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C44 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C45 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C46 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C47 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C48 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C49 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C50 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C51 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C52 m3_7988_2700# m3_7988_8000# 3.39fF
+C53 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C54 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
+C55 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C56 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C57 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C58 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C59 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C60 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C61 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C62 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C63 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C64 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C1 m3_n4309_50# m3_10_n4250# 1.75fF
+C2 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C3 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C4 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C5 c1_n4209_n4150# c1_110_n4150# 1.32fF
+C6 m3_10_n4250# c1_110_n4150# 81.11fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 in out 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C1 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C2 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C3 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C4 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C5 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C6 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C7 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C8 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C9 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C10 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
+C11 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C12 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C13 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C14 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C15 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C16 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C17 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C18 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 out in 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_30_n300# a_n88_n300# 0.61fF
+C1 a_n118_n388# a_n88_n300# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 D0_cap in 0.07fF
+C1 cap3_loop_filter_0/in in 0.79fF
+C2 vc_pex in 0.18fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# w_n311_n344# 0.14fF
+C1 a_n81_n125# a_111_n125# 0.13fF
+C2 a_n173_n125# w_n311_n344# 0.14fF
+C3 a_n173_n125# a_n81_n125# 0.36fF
+C4 a_15_n125# w_n311_n344# 0.09fF
+C5 a_15_n125# a_n81_n125# 0.36fF
+C6 a_n173_n125# a_111_n125# 0.08fF
+C7 a_81_n156# a_n15_n156# 0.02fF
+C8 a_15_n125# a_111_n125# 0.36fF
+C9 a_n15_n156# a_n111_n156# 0.02fF
+C10 a_n173_n125# a_15_n125# 0.13fF
+C11 a_n81_n125# w_n311_n344# 0.09fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n81_n125# a_15_n125# 0.36fF
+C2 a_n81_n125# a_111_n125# 0.13fF
+C3 a_n173_n125# a_n81_n125# 0.36fF
+C4 a_n111_n151# a_n15_n151# 0.02fF
+C5 a_15_n125# a_111_n125# 0.36fF
+C6 a_n173_n125# a_15_n125# 0.13fF
+C7 a_81_n151# a_n15_n151# 0.02fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_187_n605# m1_45_n513# 0.36fF
+C1 m1_45_n513# vdd 0.69fF
+C2 m1_187_n605# vdd 0.55fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_111_n125# 0.13fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 w_n311_n344# a_n173_n125# 0.14fF
+C3 a_n81_n125# a_15_n125# 0.36fF
+C4 w_n311_n344# a_111_n125# 0.14fF
+C5 a_111_n125# a_n173_n125# 0.08fF
+C6 a_n81_n125# w_n311_n344# 0.09fF
+C7 a_15_n125# w_n311_n344# 0.09fF
+C8 a_n81_n125# a_n173_n125# 0.36fF
+C9 a_15_n125# a_n173_n125# 0.13fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_111_n125# a_n173_n125# 0.08fF
+C2 a_15_n125# a_111_n125# 0.36fF
+C3 a_n81_n125# a_n173_n125# 0.36fF
+C4 a_15_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 in out 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in CLK_d 0.12fF
+C1 vdd inverter_cp_x1_0/out 0.28fF
+C2 vdd CLK 0.36fF
+C3 inverter_cp_x1_0/out CLK 0.31fF
+C4 vdd nCLK_d 0.03fF
+C5 nCLK_d inverter_cp_x1_0/out 0.11fF
+C6 inverter_cp_x1_2/in vdd 0.21fF
+C7 inverter_cp_x1_2/in CLK 0.31fF
+C8 vdd CLK_d 0.03fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_n125_n95# 0.11fF
+C1 w_n263_n314# a_63_n95# 0.11fF
+C2 a_n33_n95# a_n125_n95# 0.28fF
+C3 a_n33_n95# a_63_n95# 0.28fF
+C4 a_63_n95# a_n125_n95# 0.10fF
+C5 w_n263_n314# a_n33_n95# 0.08fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_n173_n125# 0.36fF
+C1 a_111_n125# a_n173_n125# 0.08fF
+C2 a_n129_n213# a_n81_n125# 0.10fF
+C3 a_n129_n213# a_111_n125# 0.01fF
+C4 a_n129_n213# a_n173_n125# 0.02fF
+C5 a_15_n125# a_n81_n125# 0.36fF
+C6 a_15_n125# a_111_n125# 0.36fF
+C7 a_15_n125# a_n173_n125# 0.13fF
+C8 a_111_n125# a_n81_n125# 0.13fF
+C9 a_n129_n213# a_15_n125# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_n125_n95# 0.88fF
+C1 a_n81_n183# a_n33_n95# 0.10fF
+C2 a_n81_n183# a_n125_n95# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 Q vdd 0.16fF
+C1 Q D 0.05fF
+C2 nD nQ 0.05fF
+C3 CLK m1_657_280# 0.24fF
+C4 m1_657_280# nQ 1.41fF
+C5 nD Q 0.05fF
+C6 Q nQ 0.93fF
+C7 vdd nQ 0.16fF
+C8 nQ D 0.05fF
+C9 Q m1_657_280# 0.94fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
++ nCLK latch_diff_0/nD
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C1 Q latch_diff_1/nD 0.01fF
+C2 latch_diff_0/D latch_diff_1/nD 0.04fF
+C3 latch_diff_1/D nQ 0.11fF
+C4 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
+C5 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C6 nQ latch_diff_1/nD 0.08fF
+C7 latch_diff_1/D vdd 0.03fF
+C8 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C9 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C10 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C11 latch_diff_1/nD vdd 0.02fF
+C12 latch_diff_1/D latch_diff_1/nD 0.33fF
+C13 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C14 latch_diff_0/D vdd 0.09fF
+C15 latch_diff_1/D latch_diff_0/D 0.11fF
+C16 latch_diff_1/D latch_diff_1/m1_657_280# 0.32fF
+C17 latch_diff_0/nD vdd 0.14fF
+C18 latch_diff_0/nD latch_diff_1/D 0.41fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n221_n84# a_n33_n84# 0.09fF
+C1 a_n221_n84# a_159_n84# 0.04fF
+C2 w_n359_n303# a_n33_n84# 0.05fF
+C3 a_33_n110# a_n63_n110# 0.02fF
+C4 w_n359_n303# a_159_n84# 0.08fF
+C5 a_n129_n84# a_63_n84# 0.09fF
+C6 a_n159_n110# a_n63_n110# 0.02fF
+C7 a_159_n84# a_n33_n84# 0.09fF
+C8 a_n221_n84# a_63_n84# 0.05fF
+C9 a_n221_n84# a_n129_n84# 0.24fF
+C10 w_n359_n303# a_63_n84# 0.06fF
+C11 a_n129_n84# w_n359_n303# 0.06fF
+C12 a_n33_n84# a_63_n84# 0.24fF
+C13 a_159_n84# a_63_n84# 0.24fF
+C14 a_129_n110# a_33_n110# 0.02fF
+C15 a_n129_n84# a_n33_n84# 0.24fF
+C16 a_n221_n84# w_n359_n303# 0.08fF
+C17 a_n129_n84# a_159_n84# 0.05fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_63_n42# a_159_n42# 0.12fF
+C1 a_63_n42# a_n33_n42# 0.12fF
+C2 a_n221_n42# a_n129_n42# 0.12fF
+C3 a_159_n42# a_n33_n42# 0.05fF
+C4 a_n221_n42# a_63_n42# 0.03fF
+C5 a_129_n68# a_33_n68# 0.02fF
+C6 a_n221_n42# a_159_n42# 0.02fF
+C7 a_63_n42# a_n129_n42# 0.05fF
+C8 a_n221_n42# a_n33_n42# 0.05fF
+C9 a_33_n68# a_n63_n68# 0.02fF
+C10 a_n63_n68# a_n159_n68# 0.02fF
+C11 a_159_n42# a_n129_n42# 0.03fF
+C12 a_n129_n42# a_n33_n42# 0.12fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 vdd in 0.33fF
+C1 out in 0.67fF
+C2 out vdd 0.62fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_n125_n42# a_n33_n42# 0.12fF
+C2 a_63_n42# a_n125_n42# 0.05fF
+C3 a_63_n42# a_n33_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_63_n84# a_n125_n84# 0.09fF
+C1 w_n263_n303# a_63_n84# 0.10fF
+C2 a_n33_n84# a_63_n84# 0.24fF
+C3 w_n263_n303# a_n125_n84# 0.10fF
+C4 a_n63_n110# a_33_n110# 0.02fF
+C5 a_n33_n84# a_n125_n84# 0.24fF
+C6 w_n263_n303# a_n33_n84# 0.07fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 vdd out 0.15fF
+C1 in out 0.30fF
+C2 in vdd 0.01fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 vdd CLK_2 0.08fF
+C1 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C2 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
+C3 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C4 vdd DFlipFlop_0/CLK 0.40fF
+C5 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C6 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C7 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C8 vdd out_div 0.03fF
+C9 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C10 DFlipFlop_0/nCLK vdd 0.30fF
+C11 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C12 vdd o2 0.14fF
+C13 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C14 CLK_2 o1 0.11fF
+C15 o2 nCLK_2 0.11fF
+C16 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C17 nout_div DFlipFlop_0/CLK 0.42fF
+C18 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C19 vdd nCLK_2 0.08fF
+C20 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C21 out_div nout_div 0.22fF
+C22 DFlipFlop_0/nCLK nout_div 0.43fF
+C23 out_div o1 0.01fF
+C24 DFlipFlop_0/nCLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.46fF
+C25 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
+C26 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C27 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C28 vdd nout_div 0.16fF
+C29 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C30 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C31 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C32 vdd o1 0.14fF
+C33 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C34 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C35 nCLK_2 vss 1.08fF
+C36 o2 vss 2.21fF
+C37 CLK_2 vss 1.08fF
+C38 o1 vss 2.21fF
+C39 DFlipFlop_0/CLK vss 1.03fF
+C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C42 CLK vss 3.27fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n257_n777# a_n129_n600# 0.29fF
+C1 a_n257_n777# a_n221_n600# 0.25fF
+C2 a_n129_n600# a_n221_n600# 7.87fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n129_n300# a_n257_n404# 0.30fF
+C1 a_n221_n300# a_n129_n300# 4.05fF
+C2 a_n221_n300# a_n257_n404# 0.21fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 a_678_n100# a_3996_n100# 6.52fF
+C1 vdd a_678_n100# 0.08fF
+C2 a_678_n100# in 0.81fF
+C3 vdd a_3996_n100# 3.68fF
+C4 out a_3996_n100# 55.19fF
+C5 vdd out 47.17fF
+C6 vdd in 0.02fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n238# a_n73_n150# 0.02fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 a_15_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n33_181# 0.01fF
+C1 w_n211_n369# a_n33_181# 0.05fF
+C2 a_15_n150# w_n211_n369# 0.20fF
+C3 a_n73_n150# a_n33_181# 0.01fF
+C4 a_n73_n150# a_15_n150# 0.51fF
+C5 a_n73_n150# w_n211_n369# 0.20fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n225_n150# a_n321_n150# 0.43fF
+C1 a_63_n150# a_n465_172# 0.10fF
+C2 a_255_n150# a_n129_n150# 0.07fF
+C3 a_n321_n150# a_n509_n150# 0.16fF
+C4 a_351_n150# a_n33_n150# 0.07fF
+C5 a_159_n150# a_n33_n150# 0.16fF
+C6 a_447_n150# a_351_n150# 0.43fF
+C7 a_447_n150# a_159_n150# 0.10fF
+C8 a_n225_n150# a_159_n150# 0.07fF
+C9 a_n33_n150# a_n129_n150# 0.43fF
+C10 a_n225_n150# a_n129_n150# 0.43fF
+C11 a_n509_n150# a_n129_n150# 0.07fF
+C12 a_n321_n150# a_n129_n150# 0.16fF
+C13 a_255_n150# a_n465_172# 0.10fF
+C14 a_159_n150# a_351_n150# 0.16fF
+C15 a_159_n150# a_n129_n150# 0.10fF
+C16 a_n465_172# a_n33_n150# 0.10fF
+C17 a_447_n150# a_n465_172# 0.01fF
+C18 a_n225_n150# a_n465_172# 0.10fF
+C19 a_n465_172# a_n509_n150# 0.01fF
+C20 a_255_n150# a_63_n150# 0.16fF
+C21 a_n417_n150# a_n33_n150# 0.07fF
+C22 a_n225_n150# a_n417_n150# 0.16fF
+C23 a_n321_n150# a_n465_172# 0.10fF
+C24 a_n417_n150# a_n509_n150# 0.43fF
+C25 a_63_n150# a_n33_n150# 0.43fF
+C26 a_63_n150# a_447_n150# 0.07fF
+C27 a_63_n150# a_n225_n150# 0.10fF
+C28 a_n465_172# a_351_n150# 0.10fF
+C29 a_159_n150# a_n465_172# 0.10fF
+C30 a_n417_n150# a_n321_n150# 0.43fF
+C31 a_n465_172# a_n129_n150# 0.10fF
+C32 a_63_n150# a_n321_n150# 0.07fF
+C33 a_63_n150# a_351_n150# 0.10fF
+C34 a_63_n150# a_159_n150# 0.43fF
+C35 a_n417_n150# a_n129_n150# 0.10fF
+C36 a_255_n150# a_n33_n150# 0.10fF
+C37 a_255_n150# a_447_n150# 0.16fF
+C38 a_63_n150# a_n129_n150# 0.16fF
+C39 a_n225_n150# a_n33_n150# 0.16fF
+C40 a_n225_n150# a_n509_n150# 0.10fF
+C41 a_255_n150# a_351_n150# 0.43fF
+C42 a_255_n150# a_159_n150# 0.43fF
+C43 a_n417_n150# a_n465_172# 0.10fF
+C44 a_n321_n150# a_n33_n150# 0.10fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n647_n369# a_63_n150# 0.02fF
+C1 a_n321_n150# a_n225_n150# 0.43fF
+C2 a_n225_n150# a_n129_n150# 0.43fF
+C3 a_n321_n150# a_n129_n150# 0.16fF
+C4 a_351_n150# a_255_n150# 0.43fF
+C5 a_159_n150# a_351_n150# 0.16fF
+C6 a_n417_n150# a_n509_n150# 0.43fF
+C7 a_n417_n150# w_n647_n369# 0.07fF
+C8 a_255_n150# a_n33_n150# 0.10fF
+C9 a_159_n150# a_n33_n150# 0.16fF
+C10 a_n225_n150# a_n509_n150# 0.10fF
+C11 a_n225_n150# w_n647_n369# 0.04fF
+C12 a_n321_n150# a_n509_n150# 0.16fF
+C13 a_n321_n150# w_n647_n369# 0.05fF
+C14 a_n129_n150# a_n509_n150# 0.07fF
+C15 a_447_n150# a_63_n150# 0.07fF
+C16 a_n129_n150# w_n647_n369# 0.02fF
+C17 a_159_n150# a_255_n150# 0.43fF
+C18 w_n647_n369# a_n509_n150# 0.14fF
+C19 a_n465_n247# a_351_n150# 0.08fF
+C20 a_351_n150# a_63_n150# 0.10fF
+C21 a_n465_n247# a_n33_n150# 0.08fF
+C22 a_63_n150# a_n33_n150# 0.43fF
+C23 a_n465_n247# a_255_n150# 0.08fF
+C24 a_n465_n247# a_159_n150# 0.08fF
+C25 a_n417_n150# a_n33_n150# 0.07fF
+C26 a_63_n150# a_255_n150# 0.16fF
+C27 a_159_n150# a_63_n150# 0.43fF
+C28 a_447_n150# w_n647_n369# 0.14fF
+C29 a_n225_n150# a_n33_n150# 0.16fF
+C30 a_n321_n150# a_n33_n150# 0.10fF
+C31 a_n129_n150# a_n33_n150# 0.43fF
+C32 a_n225_n150# a_159_n150# 0.07fF
+C33 w_n647_n369# a_351_n150# 0.07fF
+C34 a_n129_n150# a_255_n150# 0.07fF
+C35 a_n129_n150# a_159_n150# 0.10fF
+C36 w_n647_n369# a_n33_n150# 0.02fF
+C37 a_n465_n247# a_63_n150# 0.08fF
+C38 w_n647_n369# a_255_n150# 0.05fF
+C39 w_n647_n369# a_159_n150# 0.04fF
+C40 a_n465_n247# a_n417_n150# 0.08fF
+C41 a_447_n150# a_351_n150# 0.43fF
+C42 a_n465_n247# a_n225_n150# 0.08fF
+C43 a_n465_n247# a_n321_n150# 0.08fF
+C44 a_n225_n150# a_63_n150# 0.10fF
+C45 a_n465_n247# a_n129_n150# 0.08fF
+C46 a_n321_n150# a_63_n150# 0.07fF
+C47 a_n129_n150# a_63_n150# 0.16fF
+C48 a_447_n150# a_255_n150# 0.16fF
+C49 a_447_n150# a_159_n150# 0.10fF
+C50 a_n417_n150# a_n225_n150# 0.16fF
+C51 a_n321_n150# a_n417_n150# 0.43fF
+C52 a_n465_n247# w_n647_n369# 0.47fF
+C53 a_351_n150# a_n33_n150# 0.07fF
+C54 a_n417_n150# a_n129_n150# 0.10fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_15_n11# 0.15fF
+C1 a_n33_n99# a_15_n11# 0.02fF
+C2 a_n73_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_20_n114# a_n78_n114# 0.42fF
+C1 a_20_n114# w_n216_n334# 0.20fF
+C2 w_n216_n334# a_n78_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vdd in 0.01fF
+C1 vss in 0.01fF
+C2 out in 0.11fF
+C3 vdd vbulkp 0.04fF
+C4 vbulkp out 0.08fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 out cap_vco_0/t 0.70fF
+C1 vctrl inverter_csvco_0/vss 0.87fF
+C2 D0 inverter_csvco_0/vss 0.02fF
+C3 inverter_csvco_0/vdd vdd 1.89fF
+C4 out inverter_csvco_0/vdd 0.02fF
+C5 out inverter_csvco_0/vss 0.03fF
+C6 inverter_csvco_0/vdd in 0.01fF
+C7 out D0 0.09fF
+C8 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C9 inverter_csvco_0/vdd vbp 0.75fF
+C10 in inverter_csvco_0/vss 0.01fF
+C11 cap_vco_0/t vdd 0.04fF
+C12 vdd vbp 1.21fF
+C13 out in 0.06fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vdd vss csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
+C1 D0 csvco_branch_1/inverter_csvco_0/vss 0.68fF
+C2 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss 0.06fF
+C3 vctrl csvco_branch_2/vbp 0.06fF
+C4 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C5 csvco_branch_2/in out_vco 0.58fF
+C6 csvco_branch_2/vbp vdd 1.49fF
+C7 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
+C8 D0 csvco_branch_0/inverter_csvco_0/vss 0.49fF
+C9 vctrl D0 4.41fF
+C10 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C11 csvco_branch_1/cap_vco_0/t out_vco 0.03fF
+C12 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C13 csvco_branch_1/in out_vco 0.76fF
+C14 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 vdd o1 0.09fF
+C1 vdd out_pad 0.10fF
+C2 out_div o1 0.11fF
+C3 out_pad out_div 0.15fF
+C4 vdd out_div 0.17fF
+C5 in_vco vss 0.83fF
+C6 out_pad vss 0.70fF
+C7 out_div vss 3.00fF
+C8 vdd vss 14.54fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_194_125# VPWR 0.33fF
+C1 A B 0.28fF
+C2 a_194_125# VGND 0.25fF
+C3 B X 0.13fF
+C4 A a_355_368# 0.02fF
+C5 a_194_125# a_158_392# 0.06fF
+C6 a_355_368# B 0.08fF
+C7 a_355_368# X 0.17fF
+C8 A VPWR 0.15fF
+C9 B VPWR 0.09fF
+C10 VPWR X 0.07fF
+C11 VPWR VPB 0.06fF
+C12 A VGND 0.31fF
+C13 A a_194_125# 0.18fF
+C14 a_355_368# VPWR 0.37fF
+C15 B VGND 0.10fF
+C16 VGND X 0.28fF
+C17 B a_194_125# 0.57fF
+C18 a_194_125# X 0.29fF
+C19 a_355_368# a_194_125# 0.51fF
+C20 VGND VPWR 0.01fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 a_56_136# VPWR 0.57fF
+C1 VPB VPWR 0.04fF
+C2 X VPWR 0.20fF
+C3 VGND B 0.03fF
+C4 VGND A 0.21fF
+C5 A B 0.08fF
+C6 VGND a_56_136# 0.06fF
+C7 a_56_136# B 0.30fF
+C8 A a_56_136# 0.17fF
+C9 VGND X 0.15fF
+C10 X B 0.02fF
+C11 B VPWR 0.02fF
+C12 A VPWR 0.07fF
+C13 X a_56_136# 0.26fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VGND X 0.16fF
+C1 VGND a_63_368# 0.27fF
+C2 a_63_368# X 0.33fF
+C3 X A 0.02fF
+C4 a_63_368# A 0.28fF
+C5 VGND B 0.11fF
+C6 a_63_368# B 0.14fF
+C7 a_63_368# a_152_368# 0.03fF
+C8 X VPWR 0.18fF
+C9 a_63_368# VPWR 0.29fF
+C10 B A 0.10fF
+C11 VPWR A 0.05fF
+C12 B VPWR 0.01fF
+C13 VPB VPWR 0.04fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
++ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
++ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
++ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C1 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C2 CLK nQ2 0.17fF
+C3 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C4 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C5 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C6 DFlipFlop_3/latch_diff_1/nD Q1 1.24fF
+C7 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C8 nQ0 vdd 0.11fF
+C9 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C10 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C11 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C12 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C13 DFlipFlop_0/Q Q1 0.13fF
+C14 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C15 sky130_fd_sc_hs__xor2_1_0/a_355_368# Q0 0.03fF
+C16 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C17 Q1 DFlipFlop_2/D 0.10fF
+C18 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C19 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C20 DFlipFlop_0/latch_diff_0/D Q0 0.42fF
+C21 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C22 nCLK nQ2 0.10fF
+C23 CLK nQ0 0.19fF
+C24 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C25 DFlipFlop_2/nQ Q1 0.31fF
+C26 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C27 DFlipFlop_1/D Q1 0.03fF
+C28 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C29 DFlipFlop_0/Q Q0 0.21fF
+C30 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C31 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C32 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C33 nQ2 nQ0 0.03fF
+C34 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C35 CLK_5 vdd 0.15fF
+C36 Q0 DFlipFlop_2/D 0.25fF
+C37 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C38 DFlipFlop_3/nQ vdd 0.02fF
+C39 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C40 sky130_fd_sc_hs__xor2_1_0/a_355_368# vdd 0.03fF
+C41 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C42 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C43 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C44 nCLK nQ0 0.09fF
+C45 Q1 Q0 9.65fF
+C46 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C47 sky130_fd_sc_hs__and2_1_1/a_56_136# vdd 0.04fF
+C48 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C49 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C50 DFlipFlop_1/D Q0 0.07fF
+C51 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C52 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C53 DFlipFlop_0/latch_diff_1/nD Q1 0.10fF
+C54 CLK DFlipFlop_3/nQ 0.01fF
+C55 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C56 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C57 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C58 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C59 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C60 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C61 Q1 DFlipFlop_0/D 0.13fF
+C62 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C63 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C64 vdd DFlipFlop_2/D 0.07fF
+C65 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C66 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C67 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C68 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C69 DFlipFlop_3/latch_diff_0/m1_657_280# Q1 0.28fF
+C70 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C71 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C72 DFlipFlop_2/nQ vdd 0.02fF
+C73 Q1 vdd 9.49fF
+C74 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C75 CLK DFlipFlop_0/Q 0.08fF
+C76 Q1_shift DFlipFlop_3/nQ 0.04fF
+C77 nCLK DFlipFlop_3/nQ 0.02fF
+C78 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C79 DFlipFlop_1/D vdd 0.25fF
+C80 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C81 CLK DFlipFlop_2/D 0.14fF
+C82 Q0 DFlipFlop_0/D 0.39fF
+C83 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C84 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C85 DFlipFlop_3/latch_diff_1/nD nCLK 0.09fF
+C86 CLK DFlipFlop_2/nQ 0.13fF
+C87 CLK Q1 -0.10fF
+C88 DFlipFlop_0/Q nQ2 0.09fF
+C89 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C90 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C91 CLK DFlipFlop_1/D 0.21fF
+C92 Q0 vdd 5.33fF
+C93 DFlipFlop_0/Q nCLK 0.11fF
+C94 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C95 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C96 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C97 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C98 nCLK DFlipFlop_2/D 0.41fF
+C99 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C100 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C101 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C102 nQ2 Q1 0.07fF
+C103 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
+C104 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C105 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C106 vdd DFlipFlop_0/D 0.19fF
+C107 Q1_shift Q1 0.36fF
+C108 CLK Q0 0.08fF
+C109 DFlipFlop_2/nQ nCLK 0.09fF
+C110 nCLK Q1 -0.01fF
+C111 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C112 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C113 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C114 Q1 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C115 DFlipFlop_1/D nCLK 0.14fF
+C116 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C117 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C118 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C119 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.28fF
+C120 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C121 nCLK DFlipFlop_1/latch_diff_1/D 0.08fF
+C122 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C123 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C124 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C125 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C126 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C127 nQ2 Q0 0.23fF
+C128 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C129 Q1 nQ0 0.06fF
+C130 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C131 DFlipFlop_1/D nQ0 0.12fF
+C132 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C133 nCLK Q0 0.20fF
+C134 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C135 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C136 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C137 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C138 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C139 CLK vdd 0.41fF
+C140 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C141 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C142 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C143 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C144 Q0 nQ0 0.33fF
+C145 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C146 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C147 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C148 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C149 nQ2 vdd 0.04fF
+C150 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C151 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C152 Q1 DFlipFlop_3/nQ 0.10fF
+C153 Q1_shift vdd 0.10fF
+C154 nCLK vdd 0.34fF
+C155 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C156 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 DFlipFlop_2/nQ vss 0.50fF
+C172 Q1 vss 8.55fF
+C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 nQ0 vss 3.42fF
+C183 Q0 vss 0.53fF
+C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n317_n125# a_n33_n125# 0.08fF
+C1 a_n255_n151# a_n159_n151# 0.02fF
+C2 a_255_n125# a_n33_n125# 0.08fF
+C3 a_33_n151# a_n63_n151# 0.02fF
+C4 a_33_n151# a_129_n151# 0.02fF
+C5 a_n129_n125# a_n33_n125# 0.36fF
+C6 a_159_n125# a_n33_n125# 0.13fF
+C7 a_n225_n125# a_n33_n125# 0.13fF
+C8 a_n129_n125# a_n317_n125# 0.13fF
+C9 a_63_n125# a_n33_n125# 0.36fF
+C10 a_n317_n125# a_n225_n125# 0.36fF
+C11 a_n317_n125# a_63_n125# 0.06fF
+C12 a_n129_n125# a_255_n125# 0.06fF
+C13 a_159_n125# a_255_n125# 0.36fF
+C14 a_225_n151# a_129_n151# 0.02fF
+C15 a_n129_n125# a_159_n125# 0.08fF
+C16 a_255_n125# a_63_n125# 0.13fF
+C17 a_n129_n125# a_n225_n125# 0.36fF
+C18 a_159_n125# a_n225_n125# 0.06fF
+C19 a_n129_n125# a_63_n125# 0.13fF
+C20 a_159_n125# a_63_n125# 0.36fF
+C21 a_n159_n151# a_n63_n151# 0.02fF
+C22 a_63_n125# a_n225_n125# 0.08fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n455_n344# a_63_n125# 0.04fF
+C1 w_n455_n344# a_n317_n125# 0.11fF
+C2 w_n455_n344# a_255_n125# 0.11fF
+C3 a_159_n125# a_n33_n125# 0.13fF
+C4 a_159_n125# a_n225_n125# 0.06fF
+C5 a_n33_n125# a_n225_n125# 0.13fF
+C6 a_63_n125# a_n129_n125# 0.13fF
+C7 a_n317_n125# a_n129_n125# 0.13fF
+C8 a_255_n125# a_n129_n125# 0.06fF
+C9 a_63_n125# a_n317_n125# 0.06fF
+C10 a_255_n125# a_63_n125# 0.13fF
+C11 w_n455_n344# a_159_n125# 0.06fF
+C12 a_129_n154# a_225_n154# 0.02fF
+C13 w_n455_n344# a_n33_n125# 0.05fF
+C14 w_n455_n344# a_n225_n125# 0.06fF
+C15 a_n159_n154# a_n255_n154# 0.02fF
+C16 a_159_n125# a_n129_n125# 0.08fF
+C17 a_129_n154# a_33_n154# 0.02fF
+C18 a_n129_n125# a_n33_n125# 0.36fF
+C19 a_n129_n125# a_n225_n125# 0.36fF
+C20 a_159_n125# a_63_n125# 0.36fF
+C21 a_255_n125# a_159_n125# 0.36fF
+C22 a_n63_n154# a_33_n154# 0.02fF
+C23 a_63_n125# a_n33_n125# 0.36fF
+C24 a_n317_n125# a_n33_n125# 0.08fF
+C25 a_255_n125# a_n33_n125# 0.08fF
+C26 a_63_n125# a_n225_n125# 0.08fF
+C27 a_n317_n125# a_n225_n125# 0.36fF
+C28 w_n455_n344# a_n129_n125# 0.04fF
+C29 a_n63_n154# a_n159_n154# 0.02fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 out in 0.85fF
+C1 vdd in 0.04fF
+C2 out vdd 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in Up 0.12fF
+C1 inverter_cp_x1_0/out nDown 0.11fF
+C2 inverter_cp_x1_2/in vdd 0.42fF
+C3 Down vdd 0.09fF
+C4 nDown vdd 0.80fF
+C5 Down nDown 0.23fF
+C6 QB vdd 0.02fF
+C7 nUp Up 0.20fF
+C8 inverter_cp_x1_0/out vdd 0.25fF
+C9 QA vdd 0.02fF
+C10 Down inverter_cp_x1_0/out 0.12fF
+C11 nUp vdd 0.14fF
+C12 Up vdd 0.60fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_63_n90# a_n33_n90# 0.26fF
+C1 a_n129_n90# a_159_n90# 0.06fF
+C2 a_63_n90# a_159_n90# 0.26fF
+C3 a_n159_n207# a_n63_n116# 0.12fF
+C4 a_159_n90# a_n33_n90# 0.09fF
+C5 w_n359_n309# a_n221_n90# 0.09fF
+C6 a_n129_n90# a_n221_n90# 0.26fF
+C7 a_63_n90# a_n221_n90# 0.06fF
+C8 a_n129_n90# w_n359_n309# 0.06fF
+C9 a_63_n90# w_n359_n309# 0.06fF
+C10 a_n33_n90# a_n221_n90# 0.09fF
+C11 a_159_n90# a_n221_n90# 0.04fF
+C12 a_n33_n90# w_n359_n309# 0.05fF
+C13 a_159_n90# w_n359_n309# 0.09fF
+C14 a_n129_n90# a_63_n90# 0.09fF
+C15 a_n129_n90# a_n33_n90# 0.26fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n125_n45# 0.05fF
+C1 a_n33_n45# a_n125_n45# 0.13fF
+C2 a_33_n71# a_n129_71# 0.04fF
+C3 a_63_n45# a_n33_n45# 0.13fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 out A 0.06fF
+C1 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C2 B A 0.24fF
+C3 A vdd 0.09fF
+C4 B out 0.40fF
+C5 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
+C6 out vdd 0.11fF
+C7 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 Q vdd 0.08fF
+C1 Q nor_pfd_2/B 2.22fF
+C2 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C3 Q Reset 0.14fF
+C4 nor_pfd_3/A vdd 0.09fF
+C5 nor_pfd_2/A vdd -0.01fF
+C6 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C7 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C8 Reset nor_pfd_3/A 0.12fF
+C9 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C10 nor_pfd_2/B vdd 0.02fF
+C11 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C12 Q nor_pfd_3/A 0.98fF
+C13 Q nor_pfd_2/A 1.38fF
+C14 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C15 Reset nor_pfd_2/B 0.43fF
+C16 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C17 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C18 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C19 Q CLK 0.04fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_159_n45# a_n33_n45# 0.05fF
+C1 a_63_n45# a_159_n45# 0.13fF
+C2 a_159_n45# a_n221_n45# 0.02fF
+C3 a_n159_n173# a_n63_n71# 0.10fF
+C4 a_63_n45# a_n33_n45# 0.13fF
+C5 a_159_n45# a_n129_n45# 0.03fF
+C6 a_n221_n45# a_n33_n45# 0.05fF
+C7 a_63_n45# a_n221_n45# 0.03fF
+C8 a_n33_n45# a_n129_n45# 0.13fF
+C9 a_63_n45# a_n129_n45# 0.05fF
+C10 a_n221_n45# a_n129_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n125_n90# a_n33_n90# 0.26fF
+C1 a_63_n90# a_n33_n90# 0.26fF
+C2 a_n99_n187# a_33_n187# 0.04fF
+C3 a_n125_n90# a_63_n90# 0.09fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n73_n45# a_15_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_15_n90# w_n211_n309# 0.09fF
+C1 a_n73_n90# w_n211_n309# 0.04fF
+C2 a_15_n90# a_n73_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C1 A vdd 0.05fF
+C2 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C3 a_656_410# A 0.04fF
+C4 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C5 vdd out 0.10fF
+C6 a_656_410# out 0.20fF
+C7 a_656_410# B 0.30fF
+C8 A B 0.33fF
+C9 a_656_410# vdd 0.20fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C1 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C2 Down vdd 0.08fF
+C3 Up Down 0.06fF
+C4 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C5 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
+C6 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
+C7 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C8 Up vdd 1.62fF
+C9 vdd Reset 0.02fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v2_pex_c iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
++ pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
++ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
++ n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer D0_vco
+Xcharge_pump_0 nswitch vdd nUp vss Down biasp vco_vctrl pswitch iref_cp nDown Up charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vss
++ D0_vco ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 vdd buffer_salida_0/a_678_n100# 0.24fF
+C1 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C2 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C3 vdd nDown 0.22fF
+C4 nUp vdd 0.05fF
+C5 out_div_by_5 div_5_Q1_shift 0.05fF
+C6 n_out_by_2 vdd 1.03fF
+C7 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C8 biasp Up 0.26fF
+C9 vdd lf_vc 0.02fF
+C10 Down nDown 2.55fF
+C11 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C12 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C13 vco_vctrl out_by_2 0.53fF
+C14 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C15 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C16 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C17 n_out_by_2 div_5_Q0 -0.12fF
+C18 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C19 n_out_by_2 div_5_Q1 1.04fF
+C20 out_to_buffer out_to_div 0.13fF
+C21 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C22 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C23 vco_vctrl vdd -1.02fF
+C24 biasp nDown 0.26fF
+C25 n_out_by_2 div_5_nQ0 0.10fF
+C26 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C27 biasp nUp -0.17fF
+C28 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C29 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C30 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C31 vco_vctrl div_5_Q0 0.48fF
+C32 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
+C33 Up nUp 2.72fF
+C34 vco_vctrl div_5_Q1 0.14fF
+C35 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C36 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C37 nswitch nDown 0.76fF
+C38 vdd D0_vco 0.03fF
+C39 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C40 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C41 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C42 out_by_2 vdd 0.97fF
+C43 n_out_by_2 div_5_nQ2 0.10fF
+C44 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C45 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C46 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C47 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
+C48 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C49 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C50 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C51 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C52 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
+C53 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C54 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C55 out_by_2 div_5_Q0 0.09fF
+C56 nUp nDown -0.09fF
+C57 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C58 out_by_2 div_5_Q1 0.42fF
+C59 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
+C60 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C61 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C62 out_div_by_5 vdd 0.28fF
+C63 nswitch vco_vctrl -0.06fF
+C64 Up pswitch 1.98fF
+C65 div_5_nQ0 out_by_2 0.32fF
+C66 vdd QA -0.04fF
+C67 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
+C68 div_by_5_0/DFlipFlop_1/D out_by_2 0.38fF
+C69 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
+C70 out_div_by_5 div_5_Q1 0.01fF
+C71 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C72 vco_vctrl nUp 0.02fF
+C73 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C74 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C75 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C76 n_out_by_2 vco_vctrl 0.52fF
+C77 pswitch nDown 0.53fF
+C78 vdd out_to_div 0.21fF
+C79 out_by_2 div_5_nQ2 0.16fF
+C80 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C81 nUp pswitch 0.85fF
+C82 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C83 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C84 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C85 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C86 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C87 Up vdd 0.28fF
+C88 biasp Down 1.24fF
+C89 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C90 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C91 vdd iref_cp 0.15fF
+C92 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C93 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C94 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
+C95 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C96 out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.09fF
+C97 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C98 out_to_buffer vdd 0.07fF
+C99 Down iref_cp 0.09fF
+C100 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
+C101 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C102 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C103 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C104 nswitch Down 0.54fF
+C105 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C106 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
+C107 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.93fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss 1.39fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.76fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 6.05fF
+C141 Up vss 2.16fF
+C142 Down vss 6.16fF
+C143 nDown vss 3.38fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C158 div_5_Q1 vss 4.28fF
+C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_nQ0 vss 0.59fF
+C169 div_5_Q0 vss 0.01fF
+C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_to_buffer vss 1.57fF
+C196 out_to_div vss 4.46fF
+C197 out_first_buffer vss 2.88fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 D0_vco vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 n_out_buffer_div_2 vss 1.63fF
+C216 out_buffer_div_2 vss 1.60fF
+C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 lf_vc vss -59.89fF
+C232 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C233 DO_cap vss 0.01fF
+C234 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C235 nswitch vss 3.73fF
+C236 biasp vss 5.44fF
+C237 iref_cp vss 2.81fF
+C238 vco_vctrl vss -21.20fF
+C239 pswitch vss 3.57fF
+.ends
+
diff --git a/mag/extractions/top_pll_v2_pex_c_port.spice b/mag/extractions/top_pll_v2_pex_c_port.spice
new file mode 100644
index 0000000..dece08e
--- /dev/null
+++ b/mag/extractions/top_pll_v2_pex_c_port.spice
@@ -0,0 +1,2927 @@
+* NGSPICE file created from top_pll_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_1803_n486# w_n2457_n634# 0.02fF
+C1 a_n29_n486# w_n2457_n634# 0.02fF
+C2 a_n487_n486# w_n2457_n634# 0.02fF
+C3 a_n945_n486# w_n2457_n634# 0.02fF
+C4 a_n1861_n486# w_n2457_n634# 0.02fF
+C5 a_n1403_n486# w_n2457_n634# 0.02fF
+C6 a_2261_n486# w_n2457_n634# 0.02fF
+C7 a_n2319_n486# w_n2457_n634# 0.02fF
+C8 a_429_n486# w_n2457_n634# 0.02fF
+C9 a_1345_n486# w_n2457_n634# 0.02fF
+C10 a_887_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n81_n75# a_n369_n75# 0.05fF
+C1 a_n849_n75# a_n465_n75# 0.03fF
+C2 a_591_n75# a_879_n75# 0.05fF
+C3 a_495_n75# a_399_n75# 0.22fF
+C4 a_n369_n75# a_n465_n75# 0.22fF
+C5 a_783_n75# a_1167_n75# 0.03fF
+C6 a_687_n75# a_783_n75# 0.22fF
+C7 a_591_n75# a_303_n75# 0.05fF
+C8 a_n657_n75# a_n273_n75# 0.03fF
+C9 a_n945_n75# a_n561_n75# 0.03fF
+C10 a_n177_n75# a_n273_n75# 0.22fF
+C11 a_111_n75# a_15_n75# 0.22fF
+C12 a_1071_n75# a_879_n75# 0.08fF
+C13 a_n753_n75# a_n1041_n75# 0.05fF
+C14 a_n1137_n75# a_n753_n75# 0.03fF
+C15 a_591_n75# a_495_n75# 0.22fF
+C16 a_591_n75# a_399_n75# 0.08fF
+C17 a_n81_n75# a_207_n75# 0.05fF
+C18 a_n753_n75# a_n561_n75# 0.08fF
+C19 a_n273_n75# a_n369_n75# 0.22fF
+C20 a_n753_n75# a_n945_n75# 0.08fF
+C21 a_591_n75# a_975_n75# 0.03fF
+C22 a_879_n75# a_783_n75# 0.22fF
+C23 a_n849_n75# a_n657_n75# 0.08fF
+C24 a_n657_n75# a_n369_n75# 0.05fF
+C25 a_n177_n75# a_n369_n75# 0.08fF
+C26 a_303_n75# a_207_n75# 0.22fF
+C27 a_1071_n75# a_975_n75# 0.22fF
+C28 a_495_n75# a_783_n75# 0.05fF
+C29 a_111_n75# a_n81_n75# 0.08fF
+C30 a_399_n75# a_783_n75# 0.03fF
+C31 a_n561_n75# a_n465_n75# 0.22fF
+C32 a_207_n75# a_495_n75# 0.05fF
+C33 a_15_n75# a_n81_n75# 0.22fF
+C34 a_207_n75# a_399_n75# 0.08fF
+C35 a_975_n75# a_783_n75# 0.08fF
+C36 a_591_n75# a_783_n75# 0.08fF
+C37 a_n177_n75# a_207_n75# 0.03fF
+C38 a_111_n75# a_303_n75# 0.08fF
+C39 a_591_n75# a_207_n75# 0.03fF
+C40 a_n753_n75# a_n465_n75# 0.05fF
+C41 a_111_n75# a_n273_n75# 0.03fF
+C42 a_15_n75# a_303_n75# 0.05fF
+C43 a_n273_n75# a_n561_n75# 0.05fF
+C44 a_n657_n75# a_n1041_n75# 0.03fF
+C45 a_111_n75# a_495_n75# 0.03fF
+C46 a_1071_n75# a_783_n75# 0.05fF
+C47 a_111_n75# a_399_n75# 0.05fF
+C48 a_15_n75# a_n273_n75# 0.05fF
+C49 a_n657_n75# a_n561_n75# 0.22fF
+C50 a_111_n75# a_n177_n75# 0.05fF
+C51 a_n177_n75# a_n561_n75# 0.03fF
+C52 a_n657_n75# a_n945_n75# 0.05fF
+C53 a_15_n75# a_399_n75# 0.03fF
+C54 a_879_n75# a_1167_n75# 0.05fF
+C55 a_n1229_n75# a_n849_n75# 0.03fF
+C56 a_879_n75# a_687_n75# 0.08fF
+C57 a_n81_n75# a_n465_n75# 0.03fF
+C58 a_n849_n75# a_n1041_n75# 0.08fF
+C59 a_n1137_n75# a_n849_n75# 0.05fF
+C60 a_15_n75# a_n177_n75# 0.08fF
+C61 a_687_n75# a_303_n75# 0.03fF
+C62 a_n849_n75# a_n561_n75# 0.05fF
+C63 a_n849_n75# a_n945_n75# 0.22fF
+C64 a_n753_n75# a_n657_n75# 0.22fF
+C65 a_n369_n75# a_n561_n75# 0.08fF
+C66 a_687_n75# a_495_n75# 0.08fF
+C67 a_n81_n75# a_303_n75# 0.03fF
+C68 a_687_n75# a_399_n75# 0.05fF
+C69 a_15_n75# a_n369_n75# 0.03fF
+C70 a_n81_n75# a_n273_n75# 0.08fF
+C71 a_975_n75# a_1167_n75# 0.08fF
+C72 a_n273_n75# a_n465_n75# 0.08fF
+C73 a_975_n75# a_687_n75# 0.05fF
+C74 a_n849_n75# a_n753_n75# 0.22fF
+C75 a_591_n75# a_687_n75# 0.22fF
+C76 a_n753_n75# a_n369_n75# 0.03fF
+C77 a_111_n75# a_207_n75# 0.22fF
+C78 a_n81_n75# a_n177_n75# 0.22fF
+C79 a_n1229_n75# a_n1041_n75# 0.08fF
+C80 a_n1229_n75# a_n1137_n75# 0.22fF
+C81 a_n657_n75# a_n465_n75# 0.08fF
+C82 a_n177_n75# a_n465_n75# 0.05fF
+C83 a_879_n75# a_495_n75# 0.03fF
+C84 a_n1137_n75# a_n1041_n75# 0.22fF
+C85 a_1071_n75# a_1167_n75# 0.22fF
+C86 a_15_n75# a_207_n75# 0.08fF
+C87 a_303_n75# a_495_n75# 0.08fF
+C88 a_1071_n75# a_687_n75# 0.03fF
+C89 a_303_n75# a_399_n75# 0.22fF
+C90 a_n1229_n75# a_n945_n75# 0.05fF
+C91 a_879_n75# a_975_n75# 0.22fF
+C92 a_n1041_n75# a_n945_n75# 0.22fF
+C93 a_n1137_n75# a_n945_n75# 0.08fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_159_n75# a_63_n75# 0.22fF
+C1 a_351_n75# a_735_n75# 0.03fF
+C2 a_n801_n75# a_n417_n75# 0.03fF
+C3 a_831_n75# a_735_n75# 0.22fF
+C4 a_n927_n101# a_33_n101# 0.08fF
+C5 a_543_n75# a_159_n75# 0.03fF
+C6 a_255_n75# a_639_n75# 0.03fF
+C7 a_n513_n75# a_n609_n75# 0.22fF
+C8 a_n897_n75# a_n609_n75# 0.05fF
+C9 a_n225_n75# a_n321_n75# 0.22fF
+C10 a_n801_n75# a_n989_n75# 0.08fF
+C11 a_351_n75# a_n33_n75# 0.03fF
+C12 a_n417_n75# a_n129_n75# 0.05fF
+C13 a_n897_n75# a_n513_n75# 0.03fF
+C14 a_351_n75# a_159_n75# 0.08fF
+C15 a_447_n75# a_639_n75# 0.08fF
+C16 a_447_n75# a_255_n75# 0.08fF
+C17 a_351_n75# a_63_n75# 0.05fF
+C18 a_n801_n75# a_n609_n75# 0.08fF
+C19 a_351_n75# a_543_n75# 0.08fF
+C20 a_543_n75# a_831_n75# 0.05fF
+C21 a_927_n75# a_735_n75# 0.08fF
+C22 a_n801_n75# a_n513_n75# 0.05fF
+C23 a_n321_n75# a_n705_n75# 0.03fF
+C24 a_n33_n75# a_n129_n75# 0.22fF
+C25 a_n801_n75# a_n897_n75# 0.22fF
+C26 a_n225_n75# a_n417_n75# 0.08fF
+C27 a_159_n75# a_n129_n75# 0.05fF
+C28 a_639_n75# a_735_n75# 0.22fF
+C29 a_n321_n75# a_n417_n75# 0.22fF
+C30 a_n129_n75# a_63_n75# 0.08fF
+C31 a_n513_n75# a_n129_n75# 0.03fF
+C32 a_n225_n75# a_n33_n75# 0.08fF
+C33 a_n33_n75# a_255_n75# 0.05fF
+C34 a_447_n75# a_735_n75# 0.05fF
+C35 a_n225_n75# a_159_n75# 0.03fF
+C36 a_n321_n75# a_n33_n75# 0.05fF
+C37 a_543_n75# a_927_n75# 0.03fF
+C38 a_159_n75# a_255_n75# 0.22fF
+C39 a_n225_n75# a_n609_n75# 0.03fF
+C40 a_n417_n75# a_n705_n75# 0.05fF
+C41 a_n225_n75# a_63_n75# 0.05fF
+C42 a_255_n75# a_63_n75# 0.08fF
+C43 a_n321_n75# a_n609_n75# 0.05fF
+C44 a_543_n75# a_639_n75# 0.22fF
+C45 a_n225_n75# a_n513_n75# 0.05fF
+C46 a_543_n75# a_255_n75# 0.05fF
+C47 a_n321_n75# a_63_n75# 0.03fF
+C48 a_n989_n75# a_n705_n75# 0.05fF
+C49 a_447_n75# a_159_n75# 0.05fF
+C50 a_n321_n75# a_n513_n75# 0.08fF
+C51 a_927_n75# a_831_n75# 0.22fF
+C52 a_447_n75# a_63_n75# 0.03fF
+C53 a_351_n75# a_639_n75# 0.05fF
+C54 a_351_n75# a_255_n75# 0.22fF
+C55 a_n609_n75# a_n705_n75# 0.22fF
+C56 a_447_n75# a_543_n75# 0.22fF
+C57 a_831_n75# a_639_n75# 0.08fF
+C58 a_n417_n75# a_n33_n75# 0.03fF
+C59 a_n513_n75# a_n705_n75# 0.08fF
+C60 a_n897_n75# a_n705_n75# 0.08fF
+C61 a_n417_n75# a_n609_n75# 0.08fF
+C62 a_351_n75# a_447_n75# 0.22fF
+C63 a_447_n75# a_831_n75# 0.03fF
+C64 a_n225_n75# a_n129_n75# 0.22fF
+C65 a_n417_n75# a_n513_n75# 0.22fF
+C66 a_n129_n75# a_255_n75# 0.03fF
+C67 a_543_n75# a_735_n75# 0.08fF
+C68 a_n989_n75# a_n609_n75# 0.03fF
+C69 a_n33_n75# a_159_n75# 0.08fF
+C70 a_n801_n75# a_n705_n75# 0.22fF
+C71 a_n321_n75# a_n129_n75# 0.08fF
+C72 a_n33_n75# a_63_n75# 0.22fF
+C73 a_927_n75# a_639_n75# 0.05fF
+C74 a_n989_n75# a_n897_n75# 0.22fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n989_n150# a_n801_n150# 0.16fF
+C1 a_n417_n150# a_n513_n150# 0.43fF
+C2 a_159_n150# a_543_n150# 0.07fF
+C3 a_n129_n150# a_63_n150# 0.16fF
+C4 a_33_n247# a_n927_n247# 0.09fF
+C5 a_n33_n150# a_n417_n150# 0.07fF
+C6 a_n321_n150# a_n705_n150# 0.07fF
+C7 a_n33_n150# a_351_n150# 0.07fF
+C8 a_447_n150# a_351_n150# 0.43fF
+C9 a_63_n150# a_255_n150# 0.16fF
+C10 a_n989_n150# a_n705_n150# 0.10fF
+C11 a_735_n150# a_639_n150# 0.43fF
+C12 a_n225_n150# a_n609_n150# 0.07fF
+C13 a_831_n150# a_447_n150# 0.07fF
+C14 a_n225_n150# a_n417_n150# 0.16fF
+C15 a_n129_n150# a_n321_n150# 0.16fF
+C16 a_927_n150# a_831_n150# 0.43fF
+C17 a_n225_n150# a_n513_n150# 0.10fF
+C18 a_159_n150# a_351_n150# 0.16fF
+C19 a_n225_n150# a_n33_n150# 0.16fF
+C20 a_159_n150# a_n33_n150# 0.16fF
+C21 a_159_n150# a_447_n150# 0.10fF
+C22 a_639_n150# a_255_n150# 0.07fF
+C23 a_735_n150# a_543_n150# 0.16fF
+C24 a_63_n150# a_351_n150# 0.10fF
+C25 a_n897_n150# a_n609_n150# 0.10fF
+C26 a_n129_n150# a_255_n150# 0.07fF
+C27 a_639_n150# a_543_n150# 0.43fF
+C28 a_n801_n150# a_n609_n150# 0.16fF
+C29 a_159_n150# a_n225_n150# 0.07fF
+C30 a_n33_n150# a_63_n150# 0.43fF
+C31 a_447_n150# a_63_n150# 0.07fF
+C32 a_n801_n150# a_n417_n150# 0.07fF
+C33 a_n897_n150# a_n513_n150# 0.07fF
+C34 a_n609_n150# a_n705_n150# 0.43fF
+C35 a_n609_n150# a_n321_n150# 0.10fF
+C36 a_n801_n150# a_n513_n150# 0.10fF
+C37 a_n989_n150# a_n609_n150# 0.07fF
+C38 a_n417_n150# a_n705_n150# 0.10fF
+C39 a_735_n150# a_351_n150# 0.07fF
+C40 a_n417_n150# a_n321_n150# 0.43fF
+C41 a_543_n150# a_255_n150# 0.10fF
+C42 a_n225_n150# a_63_n150# 0.10fF
+C43 a_n513_n150# a_n705_n150# 0.16fF
+C44 a_n321_n150# a_n513_n150# 0.16fF
+C45 a_159_n150# a_63_n150# 0.43fF
+C46 a_639_n150# a_351_n150# 0.10fF
+C47 a_735_n150# a_447_n150# 0.10fF
+C48 a_n33_n150# a_n321_n150# 0.10fF
+C49 a_735_n150# a_831_n150# 0.43fF
+C50 a_735_n150# a_927_n150# 0.16fF
+C51 a_n129_n150# a_n417_n150# 0.10fF
+C52 a_639_n150# a_447_n150# 0.16fF
+C53 a_831_n150# a_639_n150# 0.16fF
+C54 a_n129_n150# a_n513_n150# 0.07fF
+C55 a_927_n150# a_639_n150# 0.10fF
+C56 a_n225_n150# a_n321_n150# 0.43fF
+C57 a_351_n150# a_255_n150# 0.43fF
+C58 a_n129_n150# a_n33_n150# 0.43fF
+C59 a_n33_n150# a_255_n150# 0.10fF
+C60 a_447_n150# a_255_n150# 0.16fF
+C61 a_543_n150# a_351_n150# 0.16fF
+C62 a_n225_n150# a_n129_n150# 0.43fF
+C63 a_159_n150# a_n129_n150# 0.10fF
+C64 a_543_n150# a_447_n150# 0.43fF
+C65 a_n897_n150# a_n801_n150# 0.43fF
+C66 a_831_n150# a_543_n150# 0.10fF
+C67 a_63_n150# a_n321_n150# 0.07fF
+C68 a_927_n150# a_543_n150# 0.07fF
+C69 a_n609_n150# a_n417_n150# 0.16fF
+C70 a_159_n150# a_255_n150# 0.43fF
+C71 a_n897_n150# a_n705_n150# 0.16fF
+C72 a_n609_n150# a_n513_n150# 0.43fF
+C73 a_n801_n150# a_n705_n150# 0.43fF
+C74 a_n897_n150# a_n989_n150# 0.43fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n1103_n44# a_n745_n44# 0.04fF
+C1 a_n1461_n44# a_n1819_n44# 0.04fF
+C2 a_n387_n44# a_n745_n44# 0.04fF
+C3 a_687_n44# a_1045_n44# 0.04fF
+C4 a_329_n44# a_n29_n44# 0.04fF
+C5 a_1403_n44# a_1045_n44# 0.04fF
+C6 a_n387_n44# a_n29_n44# 0.04fF
+C7 a_329_n44# a_687_n44# 0.04fF
+C8 a_n1461_n44# a_n1103_n44# 0.04fF
+C9 a_1403_n44# a_1761_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_207_n150# a_399_n150# 0.16fF
+C1 a_n273_n150# a_n369_n150# 0.43fF
+C2 a_783_n150# a_495_n150# 0.10fF
+C3 a_399_n150# a_303_n150# 0.43fF
+C4 a_591_n150# a_495_n150# 0.43fF
+C5 a_n177_n150# a_n561_n150# 0.07fF
+C6 a_n945_n150# a_n1041_n150# 0.43fF
+C7 a_n81_n150# a_n177_n150# 0.43fF
+C8 a_879_n150# a_783_n150# 0.43fF
+C9 a_111_n150# a_399_n150# 0.10fF
+C10 a_591_n150# a_879_n150# 0.10fF
+C11 a_207_n150# a_15_n150# 0.16fF
+C12 a_n849_n150# a_n465_n150# 0.07fF
+C13 a_15_n150# a_303_n150# 0.10fF
+C14 a_n753_n150# a_n1137_n150# 0.07fF
+C15 a_975_n150# w_n1367_n369# 0.05fF
+C16 a_591_n150# a_783_n150# 0.16fF
+C17 a_1071_n150# w_n1367_n369# 0.07fF
+C18 a_687_n150# a_495_n150# 0.16fF
+C19 a_n849_n150# a_n1041_n150# 0.16fF
+C20 a_1071_n150# a_975_n150# 0.43fF
+C21 a_111_n150# a_15_n150# 0.43fF
+C22 a_n1229_n150# a_n1041_n150# 0.16fF
+C23 a_1167_n150# w_n1367_n369# 0.14fF
+C24 a_879_n150# a_687_n150# 0.16fF
+C25 a_975_n150# a_1167_n150# 0.16fF
+C26 a_207_n150# a_495_n150# 0.10fF
+C27 a_n849_n150# a_n945_n150# 0.43fF
+C28 a_495_n150# a_303_n150# 0.16fF
+C29 a_1071_n150# a_1167_n150# 0.43fF
+C30 a_n1229_n150# a_n945_n150# 0.10fF
+C31 a_n273_n150# a_15_n150# 0.10fF
+C32 a_687_n150# a_783_n150# 0.43fF
+C33 a_591_n150# a_687_n150# 0.43fF
+C34 a_207_n150# a_n177_n150# 0.07fF
+C35 a_n369_n150# a_15_n150# 0.07fF
+C36 a_111_n150# a_495_n150# 0.07fF
+C37 a_n81_n150# a_207_n150# 0.10fF
+C38 a_n753_n150# a_n465_n150# 0.10fF
+C39 a_n81_n150# a_303_n150# 0.07fF
+C40 a_591_n150# a_207_n150# 0.07fF
+C41 a_n657_n150# a_n465_n150# 0.16fF
+C42 a_n1229_n150# a_n849_n150# 0.07fF
+C43 a_591_n150# a_303_n150# 0.10fF
+C44 a_111_n150# a_n177_n150# 0.10fF
+C45 a_n753_n150# a_n1041_n150# 0.10fF
+C46 a_n657_n150# a_n273_n150# 0.07fF
+C47 a_n81_n150# a_111_n150# 0.16fF
+C48 a_n753_n150# a_n369_n150# 0.07fF
+C49 a_n657_n150# a_n1041_n150# 0.07fF
+C50 a_n465_n150# a_n561_n150# 0.43fF
+C51 a_n465_n150# a_n177_n150# 0.10fF
+C52 a_n657_n150# a_n369_n150# 0.10fF
+C53 a_n81_n150# a_n465_n150# 0.07fF
+C54 a_n753_n150# a_n945_n150# 0.16fF
+C55 a_n273_n150# a_n561_n150# 0.10fF
+C56 a_399_n150# a_15_n150# 0.07fF
+C57 a_n273_n150# a_n177_n150# 0.43fF
+C58 a_n657_n150# a_n945_n150# 0.10fF
+C59 a_n81_n150# a_n273_n150# 0.16fF
+C60 a_n369_n150# a_n561_n150# 0.16fF
+C61 a_n177_n150# a_n369_n150# 0.16fF
+C62 a_687_n150# a_303_n150# 0.07fF
+C63 a_n81_n150# a_n369_n150# 0.10fF
+C64 a_879_n150# w_n1367_n369# 0.04fF
+C65 a_n945_n150# a_n561_n150# 0.07fF
+C66 a_879_n150# a_975_n150# 0.43fF
+C67 a_n753_n150# a_n849_n150# 0.43fF
+C68 a_207_n150# a_303_n150# 0.43fF
+C69 a_879_n150# a_1071_n150# 0.16fF
+C70 a_n657_n150# a_n849_n150# 0.16fF
+C71 a_495_n150# a_399_n150# 0.43fF
+C72 a_975_n150# a_783_n150# 0.16fF
+C73 a_591_n150# a_975_n150# 0.07fF
+C74 a_879_n150# a_1167_n150# 0.10fF
+C75 a_1071_n150# a_783_n150# 0.10fF
+C76 a_111_n150# a_207_n150# 0.43fF
+C77 a_n849_n150# a_n561_n150# 0.10fF
+C78 a_n1041_n150# a_n1137_n150# 0.43fF
+C79 a_111_n150# a_303_n150# 0.16fF
+C80 a_1167_n150# a_783_n150# 0.07fF
+C81 a_783_n150# a_399_n150# 0.07fF
+C82 a_591_n150# a_399_n150# 0.16fF
+C83 a_n945_n150# a_n1137_n150# 0.16fF
+C84 a_975_n150# a_687_n150# 0.10fF
+C85 a_n177_n150# a_15_n150# 0.16fF
+C86 a_1071_n150# a_687_n150# 0.07fF
+C87 a_n81_n150# a_15_n150# 0.43fF
+C88 a_111_n150# a_n273_n150# 0.07fF
+C89 a_n753_n150# a_n657_n150# 0.43fF
+C90 a_n849_n150# a_n1137_n150# 0.10fF
+C91 a_n465_n150# a_n273_n150# 0.16fF
+C92 a_n1229_n150# a_n1137_n150# 0.43fF
+C93 a_687_n150# a_399_n150# 0.10fF
+C94 a_n753_n150# a_n561_n150# 0.16fF
+C95 a_n465_n150# a_n369_n150# 0.43fF
+C96 a_879_n150# a_495_n150# 0.07fF
+C97 a_n657_n150# a_n561_n150# 0.43fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vdd nUp vss Down biasp out pswitch iref nDown Up
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 pswitch vdd 3.98fF
+C1 pswitch nUp 5.66fF
+C2 pswitch nswitch 0.06fF
+C3 nUp Down 0.25fF
+C4 Down nswitch 2.27fF
+C5 vdd nswitch 0.07fF
+C6 iref nswitch 1.91fF
+C7 pswitch biasp 3.11fF
+C8 vdd biasp 2.64fF
+C9 biasp nswitch 0.03fF
+C10 iref biasp 0.80fF
+C11 pswitch out 4.91fF
+C12 nDown Down 0.13fF
+C13 vdd out 6.66fF
+C14 out nUp 0.31fF
+C15 nDown nswitch 0.31fF
+C16 out nswitch 1.28fF
+C17 Up pswitch 0.70fF
+C18 Up nUp 0.15fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C1 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C2 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C3 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C4 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C5 m3_7988_2700# m3_2669_2700# 2.73fF
+C6 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C7 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C8 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C9 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C10 m3_2669_8000# m3_7988_8000# 2.73fF
+C11 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C12 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C13 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C14 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C15 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C16 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C17 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C18 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C19 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C20 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C21 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C22 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
+C23 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C24 m3_2669_2700# m3_n2650_2700# 2.73fF
+C25 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C26 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C27 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C28 m3_2669_8000# m3_2669_2700# 3.28fF
+C29 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C30 m3_7988_n2600# m3_7988_2700# 3.39fF
+C31 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C32 m3_n2650_8000# m3_2669_8000# 2.73fF
+C33 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C34 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C35 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C36 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C37 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C38 m3_2669_2700# m3_2669_n2600# 3.28fF
+C39 m3_2669_8000# c1_n13188_n13100# 58.61fF
+C40 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C41 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C42 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C43 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C44 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C45 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C46 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C47 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C48 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C49 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C50 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C51 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C52 m3_7988_2700# m3_7988_8000# 3.39fF
+C53 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C54 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
+C55 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C56 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C57 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C58 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C59 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C60 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C61 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C62 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C63 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C64 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C1 m3_n4309_50# m3_10_n4250# 1.75fF
+C2 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C3 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C4 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C5 c1_n4209_n4150# c1_110_n4150# 1.32fF
+C6 m3_10_n4250# c1_110_n4150# 81.11fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 in out 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C1 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C2 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C3 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C4 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C5 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C6 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C7 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C8 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C9 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C10 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
+C11 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C12 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C13 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C14 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C15 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C16 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C17 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C18 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 out in 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_30_n300# a_n88_n300# 0.61fF
+C1 a_n118_n388# a_n88_n300# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 D0_cap in 0.07fF
+C1 cap3_loop_filter_0/in in 0.79fF
+C2 vc_pex in 0.18fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# w_n311_n344# 0.14fF
+C1 a_n81_n125# a_111_n125# 0.13fF
+C2 a_n173_n125# w_n311_n344# 0.14fF
+C3 a_n173_n125# a_n81_n125# 0.36fF
+C4 a_15_n125# w_n311_n344# 0.09fF
+C5 a_15_n125# a_n81_n125# 0.36fF
+C6 a_n173_n125# a_111_n125# 0.08fF
+C7 a_81_n156# a_n15_n156# 0.02fF
+C8 a_15_n125# a_111_n125# 0.36fF
+C9 a_n15_n156# a_n111_n156# 0.02fF
+C10 a_n173_n125# a_15_n125# 0.13fF
+C11 a_n81_n125# w_n311_n344# 0.09fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n81_n125# a_15_n125# 0.36fF
+C2 a_n81_n125# a_111_n125# 0.13fF
+C3 a_n173_n125# a_n81_n125# 0.36fF
+C4 a_n111_n151# a_n15_n151# 0.02fF
+C5 a_15_n125# a_111_n125# 0.36fF
+C6 a_n173_n125# a_15_n125# 0.13fF
+C7 a_81_n151# a_n15_n151# 0.02fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_187_n605# m1_45_n513# 0.36fF
+C1 m1_45_n513# vdd 0.69fF
+C2 m1_187_n605# vdd 0.55fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_111_n125# 0.13fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 w_n311_n344# a_n173_n125# 0.14fF
+C3 a_n81_n125# a_15_n125# 0.36fF
+C4 w_n311_n344# a_111_n125# 0.14fF
+C5 a_111_n125# a_n173_n125# 0.08fF
+C6 a_n81_n125# w_n311_n344# 0.09fF
+C7 a_15_n125# w_n311_n344# 0.09fF
+C8 a_n81_n125# a_n173_n125# 0.36fF
+C9 a_15_n125# a_n173_n125# 0.13fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_111_n125# a_n173_n125# 0.08fF
+C2 a_15_n125# a_111_n125# 0.36fF
+C3 a_n81_n125# a_n173_n125# 0.36fF
+C4 a_15_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 in out 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in CLK_d 0.12fF
+C1 vdd inverter_cp_x1_0/out 0.28fF
+C2 vdd CLK 0.36fF
+C3 inverter_cp_x1_0/out CLK 0.31fF
+C4 vdd nCLK_d 0.03fF
+C5 nCLK_d inverter_cp_x1_0/out 0.11fF
+C6 inverter_cp_x1_2/in vdd 0.21fF
+C7 inverter_cp_x1_2/in CLK 0.31fF
+C8 vdd CLK_d 0.03fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_n125_n95# 0.11fF
+C1 w_n263_n314# a_63_n95# 0.11fF
+C2 a_n33_n95# a_n125_n95# 0.28fF
+C3 a_n33_n95# a_63_n95# 0.28fF
+C4 a_63_n95# a_n125_n95# 0.10fF
+C5 w_n263_n314# a_n33_n95# 0.08fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_n173_n125# 0.36fF
+C1 a_111_n125# a_n173_n125# 0.08fF
+C2 a_n129_n213# a_n81_n125# 0.10fF
+C3 a_n129_n213# a_111_n125# 0.01fF
+C4 a_n129_n213# a_n173_n125# 0.02fF
+C5 a_15_n125# a_n81_n125# 0.36fF
+C6 a_15_n125# a_111_n125# 0.36fF
+C7 a_15_n125# a_n173_n125# 0.13fF
+C8 a_111_n125# a_n81_n125# 0.13fF
+C9 a_n129_n213# a_15_n125# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_n125_n95# 0.88fF
+C1 a_n81_n183# a_n33_n95# 0.10fF
+C2 a_n81_n183# a_n125_n95# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 Q vdd 0.16fF
+C1 Q D 0.05fF
+C2 nD nQ 0.05fF
+C3 CLK m1_657_280# 0.24fF
+C4 m1_657_280# nQ 1.41fF
+C5 nD Q 0.05fF
+C6 Q nQ 0.93fF
+C7 vdd nQ 0.16fF
+C8 nQ D 0.05fF
+C9 Q m1_657_280# 0.94fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
++ nCLK latch_diff_0/nD
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C1 Q latch_diff_1/nD 0.01fF
+C2 latch_diff_0/D latch_diff_1/nD 0.04fF
+C3 latch_diff_1/D nQ 0.11fF
+C4 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
+C5 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C6 nQ latch_diff_1/nD 0.08fF
+C7 latch_diff_1/D vdd 0.03fF
+C8 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C9 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C10 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C11 latch_diff_1/nD vdd 0.02fF
+C12 latch_diff_1/D latch_diff_1/nD 0.33fF
+C13 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C14 latch_diff_0/D vdd 0.09fF
+C15 latch_diff_1/D latch_diff_0/D 0.11fF
+C16 latch_diff_1/D latch_diff_1/m1_657_280# 0.32fF
+C17 latch_diff_0/nD vdd 0.14fF
+C18 latch_diff_0/nD latch_diff_1/D 0.41fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n221_n84# a_n33_n84# 0.09fF
+C1 a_n221_n84# a_159_n84# 0.04fF
+C2 w_n359_n303# a_n33_n84# 0.05fF
+C3 a_33_n110# a_n63_n110# 0.02fF
+C4 w_n359_n303# a_159_n84# 0.08fF
+C5 a_n129_n84# a_63_n84# 0.09fF
+C6 a_n159_n110# a_n63_n110# 0.02fF
+C7 a_159_n84# a_n33_n84# 0.09fF
+C8 a_n221_n84# a_63_n84# 0.05fF
+C9 a_n221_n84# a_n129_n84# 0.24fF
+C10 w_n359_n303# a_63_n84# 0.06fF
+C11 a_n129_n84# w_n359_n303# 0.06fF
+C12 a_n33_n84# a_63_n84# 0.24fF
+C13 a_159_n84# a_63_n84# 0.24fF
+C14 a_129_n110# a_33_n110# 0.02fF
+C15 a_n129_n84# a_n33_n84# 0.24fF
+C16 a_n221_n84# w_n359_n303# 0.08fF
+C17 a_n129_n84# a_159_n84# 0.05fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_63_n42# a_159_n42# 0.12fF
+C1 a_63_n42# a_n33_n42# 0.12fF
+C2 a_n221_n42# a_n129_n42# 0.12fF
+C3 a_159_n42# a_n33_n42# 0.05fF
+C4 a_n221_n42# a_63_n42# 0.03fF
+C5 a_129_n68# a_33_n68# 0.02fF
+C6 a_n221_n42# a_159_n42# 0.02fF
+C7 a_63_n42# a_n129_n42# 0.05fF
+C8 a_n221_n42# a_n33_n42# 0.05fF
+C9 a_33_n68# a_n63_n68# 0.02fF
+C10 a_n63_n68# a_n159_n68# 0.02fF
+C11 a_159_n42# a_n129_n42# 0.03fF
+C12 a_n129_n42# a_n33_n42# 0.12fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 vdd in 0.33fF
+C1 out in 0.67fF
+C2 out vdd 0.62fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_n125_n42# a_n33_n42# 0.12fF
+C2 a_63_n42# a_n125_n42# 0.05fF
+C3 a_63_n42# a_n33_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_63_n84# a_n125_n84# 0.09fF
+C1 w_n263_n303# a_63_n84# 0.10fF
+C2 a_n33_n84# a_63_n84# 0.24fF
+C3 w_n263_n303# a_n125_n84# 0.10fF
+C4 a_n63_n110# a_33_n110# 0.02fF
+C5 a_n33_n84# a_n125_n84# 0.24fF
+C6 w_n263_n303# a_n33_n84# 0.07fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 vdd out 0.15fF
+C1 in out 0.30fF
+C2 in vdd 0.01fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 vdd CLK_2 0.08fF
+C1 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C2 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
+C3 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C4 vdd DFlipFlop_0/CLK 0.40fF
+C5 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C6 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C7 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C8 vdd out_div 0.03fF
+C9 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C10 DFlipFlop_0/nCLK vdd 0.30fF
+C11 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C12 vdd o2 0.14fF
+C13 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C14 CLK_2 o1 0.11fF
+C15 o2 nCLK_2 0.11fF
+C16 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C17 nout_div DFlipFlop_0/CLK 0.42fF
+C18 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C19 vdd nCLK_2 0.08fF
+C20 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C21 out_div nout_div 0.22fF
+C22 DFlipFlop_0/nCLK nout_div 0.43fF
+C23 out_div o1 0.01fF
+C24 DFlipFlop_0/nCLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.46fF
+C25 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
+C26 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C27 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C28 vdd nout_div 0.16fF
+C29 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C30 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C31 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C32 vdd o1 0.14fF
+C33 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C34 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C35 nCLK_2 vss 1.08fF
+C36 o2 vss 2.21fF
+C37 CLK_2 vss 1.08fF
+C38 o1 vss 2.21fF
+C39 DFlipFlop_0/CLK vss 1.03fF
+C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C42 CLK vss 3.27fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n257_n777# a_n129_n600# 0.29fF
+C1 a_n257_n777# a_n221_n600# 0.25fF
+C2 a_n129_n600# a_n221_n600# 7.87fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n129_n300# a_n257_n404# 0.30fF
+C1 a_n221_n300# a_n129_n300# 4.05fF
+C2 a_n221_n300# a_n257_n404# 0.21fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 a_678_n100# a_3996_n100# 6.52fF
+C1 vdd a_678_n100# 0.08fF
+C2 a_678_n100# in 0.81fF
+C3 vdd a_3996_n100# 3.68fF
+C4 out a_3996_n100# 55.19fF
+C5 vdd out 47.17fF
+C6 vdd in 0.02fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n238# a_n73_n150# 0.02fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 a_15_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n33_181# 0.01fF
+C1 w_n211_n369# a_n33_181# 0.05fF
+C2 a_15_n150# w_n211_n369# 0.20fF
+C3 a_n73_n150# a_n33_181# 0.01fF
+C4 a_n73_n150# a_15_n150# 0.51fF
+C5 a_n73_n150# w_n211_n369# 0.20fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n225_n150# a_n321_n150# 0.43fF
+C1 a_63_n150# a_n465_172# 0.10fF
+C2 a_255_n150# a_n129_n150# 0.07fF
+C3 a_n321_n150# a_n509_n150# 0.16fF
+C4 a_351_n150# a_n33_n150# 0.07fF
+C5 a_159_n150# a_n33_n150# 0.16fF
+C6 a_447_n150# a_351_n150# 0.43fF
+C7 a_447_n150# a_159_n150# 0.10fF
+C8 a_n225_n150# a_159_n150# 0.07fF
+C9 a_n33_n150# a_n129_n150# 0.43fF
+C10 a_n225_n150# a_n129_n150# 0.43fF
+C11 a_n509_n150# a_n129_n150# 0.07fF
+C12 a_n321_n150# a_n129_n150# 0.16fF
+C13 a_255_n150# a_n465_172# 0.10fF
+C14 a_159_n150# a_351_n150# 0.16fF
+C15 a_159_n150# a_n129_n150# 0.10fF
+C16 a_n465_172# a_n33_n150# 0.10fF
+C17 a_447_n150# a_n465_172# 0.01fF
+C18 a_n225_n150# a_n465_172# 0.10fF
+C19 a_n465_172# a_n509_n150# 0.01fF
+C20 a_255_n150# a_63_n150# 0.16fF
+C21 a_n417_n150# a_n33_n150# 0.07fF
+C22 a_n225_n150# a_n417_n150# 0.16fF
+C23 a_n321_n150# a_n465_172# 0.10fF
+C24 a_n417_n150# a_n509_n150# 0.43fF
+C25 a_63_n150# a_n33_n150# 0.43fF
+C26 a_63_n150# a_447_n150# 0.07fF
+C27 a_63_n150# a_n225_n150# 0.10fF
+C28 a_n465_172# a_351_n150# 0.10fF
+C29 a_159_n150# a_n465_172# 0.10fF
+C30 a_n417_n150# a_n321_n150# 0.43fF
+C31 a_n465_172# a_n129_n150# 0.10fF
+C32 a_63_n150# a_n321_n150# 0.07fF
+C33 a_63_n150# a_351_n150# 0.10fF
+C34 a_63_n150# a_159_n150# 0.43fF
+C35 a_n417_n150# a_n129_n150# 0.10fF
+C36 a_255_n150# a_n33_n150# 0.10fF
+C37 a_255_n150# a_447_n150# 0.16fF
+C38 a_63_n150# a_n129_n150# 0.16fF
+C39 a_n225_n150# a_n33_n150# 0.16fF
+C40 a_n225_n150# a_n509_n150# 0.10fF
+C41 a_255_n150# a_351_n150# 0.43fF
+C42 a_255_n150# a_159_n150# 0.43fF
+C43 a_n417_n150# a_n465_172# 0.10fF
+C44 a_n321_n150# a_n33_n150# 0.10fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n647_n369# a_63_n150# 0.02fF
+C1 a_n321_n150# a_n225_n150# 0.43fF
+C2 a_n225_n150# a_n129_n150# 0.43fF
+C3 a_n321_n150# a_n129_n150# 0.16fF
+C4 a_351_n150# a_255_n150# 0.43fF
+C5 a_159_n150# a_351_n150# 0.16fF
+C6 a_n417_n150# a_n509_n150# 0.43fF
+C7 a_n417_n150# w_n647_n369# 0.07fF
+C8 a_255_n150# a_n33_n150# 0.10fF
+C9 a_159_n150# a_n33_n150# 0.16fF
+C10 a_n225_n150# a_n509_n150# 0.10fF
+C11 a_n225_n150# w_n647_n369# 0.04fF
+C12 a_n321_n150# a_n509_n150# 0.16fF
+C13 a_n321_n150# w_n647_n369# 0.05fF
+C14 a_n129_n150# a_n509_n150# 0.07fF
+C15 a_447_n150# a_63_n150# 0.07fF
+C16 a_n129_n150# w_n647_n369# 0.02fF
+C17 a_159_n150# a_255_n150# 0.43fF
+C18 w_n647_n369# a_n509_n150# 0.14fF
+C19 a_n465_n247# a_351_n150# 0.08fF
+C20 a_351_n150# a_63_n150# 0.10fF
+C21 a_n465_n247# a_n33_n150# 0.08fF
+C22 a_63_n150# a_n33_n150# 0.43fF
+C23 a_n465_n247# a_255_n150# 0.08fF
+C24 a_n465_n247# a_159_n150# 0.08fF
+C25 a_n417_n150# a_n33_n150# 0.07fF
+C26 a_63_n150# a_255_n150# 0.16fF
+C27 a_159_n150# a_63_n150# 0.43fF
+C28 a_447_n150# w_n647_n369# 0.14fF
+C29 a_n225_n150# a_n33_n150# 0.16fF
+C30 a_n321_n150# a_n33_n150# 0.10fF
+C31 a_n129_n150# a_n33_n150# 0.43fF
+C32 a_n225_n150# a_159_n150# 0.07fF
+C33 w_n647_n369# a_351_n150# 0.07fF
+C34 a_n129_n150# a_255_n150# 0.07fF
+C35 a_n129_n150# a_159_n150# 0.10fF
+C36 w_n647_n369# a_n33_n150# 0.02fF
+C37 a_n465_n247# a_63_n150# 0.08fF
+C38 w_n647_n369# a_255_n150# 0.05fF
+C39 w_n647_n369# a_159_n150# 0.04fF
+C40 a_n465_n247# a_n417_n150# 0.08fF
+C41 a_447_n150# a_351_n150# 0.43fF
+C42 a_n465_n247# a_n225_n150# 0.08fF
+C43 a_n465_n247# a_n321_n150# 0.08fF
+C44 a_n225_n150# a_63_n150# 0.10fF
+C45 a_n465_n247# a_n129_n150# 0.08fF
+C46 a_n321_n150# a_63_n150# 0.07fF
+C47 a_n129_n150# a_63_n150# 0.16fF
+C48 a_447_n150# a_255_n150# 0.16fF
+C49 a_447_n150# a_159_n150# 0.10fF
+C50 a_n417_n150# a_n225_n150# 0.16fF
+C51 a_n321_n150# a_n417_n150# 0.43fF
+C52 a_n465_n247# w_n647_n369# 0.47fF
+C53 a_351_n150# a_n33_n150# 0.07fF
+C54 a_n417_n150# a_n129_n150# 0.10fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_15_n11# 0.15fF
+C1 a_n33_n99# a_15_n11# 0.02fF
+C2 a_n73_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_20_n114# a_n78_n114# 0.42fF
+C1 a_20_n114# w_n216_n334# 0.20fF
+C2 w_n216_n334# a_n78_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vdd in 0.01fF
+C1 vss in 0.01fF
+C2 out in 0.11fF
+C3 vdd vbulkp 0.04fF
+C4 vbulkp out 0.08fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 out cap_vco_0/t 0.70fF
+C1 vctrl inverter_csvco_0/vss 0.87fF
+C2 D0 inverter_csvco_0/vss 0.02fF
+C3 inverter_csvco_0/vdd vdd 1.89fF
+C4 out inverter_csvco_0/vdd 0.02fF
+C5 out inverter_csvco_0/vss 0.03fF
+C6 inverter_csvco_0/vdd in 0.01fF
+C7 out D0 0.09fF
+C8 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C9 inverter_csvco_0/vdd vbp 0.75fF
+C10 in inverter_csvco_0/vss 0.01fF
+C11 cap_vco_0/t vdd 0.04fF
+C12 vdd vbp 1.21fF
+C13 out in 0.06fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vdd vss csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
+C1 D0 csvco_branch_1/inverter_csvco_0/vss 0.68fF
+C2 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss 0.06fF
+C3 vctrl csvco_branch_2/vbp 0.06fF
+C4 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C5 csvco_branch_2/in out_vco 0.58fF
+C6 csvco_branch_2/vbp vdd 1.49fF
+C7 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
+C8 D0 csvco_branch_0/inverter_csvco_0/vss 0.49fF
+C9 vctrl D0 4.41fF
+C10 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C11 csvco_branch_1/cap_vco_0/t out_vco 0.03fF
+C12 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C13 csvco_branch_1/in out_vco 0.76fF
+C14 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 vdd o1 0.09fF
+C1 vdd out_pad 0.10fF
+C2 out_div o1 0.11fF
+C3 out_pad out_div 0.15fF
+C4 vdd out_div 0.17fF
+C5 in_vco vss 0.83fF
+C6 out_pad vss 0.70fF
+C7 out_div vss 3.00fF
+C8 vdd vss 14.54fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_194_125# VPWR 0.33fF
+C1 A B 0.28fF
+C2 a_194_125# VGND 0.25fF
+C3 B X 0.13fF
+C4 A a_355_368# 0.02fF
+C5 a_194_125# a_158_392# 0.06fF
+C6 a_355_368# B 0.08fF
+C7 a_355_368# X 0.17fF
+C8 A VPWR 0.15fF
+C9 B VPWR 0.09fF
+C10 VPWR X 0.07fF
+C11 VPWR VPB 0.06fF
+C12 A VGND 0.31fF
+C13 A a_194_125# 0.18fF
+C14 a_355_368# VPWR 0.37fF
+C15 B VGND 0.10fF
+C16 VGND X 0.28fF
+C17 B a_194_125# 0.57fF
+C18 a_194_125# X 0.29fF
+C19 a_355_368# a_194_125# 0.51fF
+C20 VGND VPWR 0.01fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 a_56_136# VPWR 0.57fF
+C1 VPB VPWR 0.04fF
+C2 X VPWR 0.20fF
+C3 VGND B 0.03fF
+C4 VGND A 0.21fF
+C5 A B 0.08fF
+C6 VGND a_56_136# 0.06fF
+C7 a_56_136# B 0.30fF
+C8 A a_56_136# 0.17fF
+C9 VGND X 0.15fF
+C10 X B 0.02fF
+C11 B VPWR 0.02fF
+C12 A VPWR 0.07fF
+C13 X a_56_136# 0.26fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VGND X 0.16fF
+C1 VGND a_63_368# 0.27fF
+C2 a_63_368# X 0.33fF
+C3 X A 0.02fF
+C4 a_63_368# A 0.28fF
+C5 VGND B 0.11fF
+C6 a_63_368# B 0.14fF
+C7 a_63_368# a_152_368# 0.03fF
+C8 X VPWR 0.18fF
+C9 a_63_368# VPWR 0.29fF
+C10 B A 0.10fF
+C11 VPWR A 0.05fF
+C12 B VPWR 0.01fF
+C13 VPB VPWR 0.04fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
++ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
++ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
++ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C1 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C2 CLK nQ2 0.17fF
+C3 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C4 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C5 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C6 DFlipFlop_3/latch_diff_1/nD Q1 1.24fF
+C7 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C8 nQ0 vdd 0.11fF
+C9 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C10 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C11 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C12 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C13 DFlipFlop_0/Q Q1 0.13fF
+C14 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C15 sky130_fd_sc_hs__xor2_1_0/a_355_368# Q0 0.03fF
+C16 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C17 Q1 DFlipFlop_2/D 0.10fF
+C18 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C19 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C20 DFlipFlop_0/latch_diff_0/D Q0 0.42fF
+C21 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C22 nCLK nQ2 0.10fF
+C23 CLK nQ0 0.19fF
+C24 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C25 DFlipFlop_2/nQ Q1 0.31fF
+C26 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C27 DFlipFlop_1/D Q1 0.03fF
+C28 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C29 DFlipFlop_0/Q Q0 0.21fF
+C30 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C31 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C32 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C33 nQ2 nQ0 0.03fF
+C34 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C35 CLK_5 vdd 0.15fF
+C36 Q0 DFlipFlop_2/D 0.25fF
+C37 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C38 DFlipFlop_3/nQ vdd 0.02fF
+C39 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C40 sky130_fd_sc_hs__xor2_1_0/a_355_368# vdd 0.03fF
+C41 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C42 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C43 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C44 nCLK nQ0 0.09fF
+C45 Q1 Q0 9.65fF
+C46 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C47 sky130_fd_sc_hs__and2_1_1/a_56_136# vdd 0.04fF
+C48 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C49 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C50 DFlipFlop_1/D Q0 0.07fF
+C51 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C52 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C53 DFlipFlop_0/latch_diff_1/nD Q1 0.10fF
+C54 CLK DFlipFlop_3/nQ 0.01fF
+C55 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C56 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C57 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C58 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C59 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C60 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C61 Q1 DFlipFlop_0/D 0.13fF
+C62 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C63 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C64 vdd DFlipFlop_2/D 0.07fF
+C65 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C66 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C67 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C68 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C69 DFlipFlop_3/latch_diff_0/m1_657_280# Q1 0.28fF
+C70 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C71 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C72 DFlipFlop_2/nQ vdd 0.02fF
+C73 Q1 vdd 9.49fF
+C74 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C75 CLK DFlipFlop_0/Q 0.08fF
+C76 Q1_shift DFlipFlop_3/nQ 0.04fF
+C77 nCLK DFlipFlop_3/nQ 0.02fF
+C78 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C79 DFlipFlop_1/D vdd 0.25fF
+C80 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C81 CLK DFlipFlop_2/D 0.14fF
+C82 Q0 DFlipFlop_0/D 0.39fF
+C83 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C84 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C85 DFlipFlop_3/latch_diff_1/nD nCLK 0.09fF
+C86 CLK DFlipFlop_2/nQ 0.13fF
+C87 CLK Q1 -0.10fF
+C88 DFlipFlop_0/Q nQ2 0.09fF
+C89 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C90 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C91 CLK DFlipFlop_1/D 0.21fF
+C92 Q0 vdd 5.33fF
+C93 DFlipFlop_0/Q nCLK 0.11fF
+C94 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C95 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C96 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C97 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C98 nCLK DFlipFlop_2/D 0.41fF
+C99 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C100 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C101 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C102 nQ2 Q1 0.07fF
+C103 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
+C104 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C105 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C106 vdd DFlipFlop_0/D 0.19fF
+C107 Q1_shift Q1 0.36fF
+C108 CLK Q0 0.08fF
+C109 DFlipFlop_2/nQ nCLK 0.09fF
+C110 nCLK Q1 -0.01fF
+C111 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C112 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C113 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C114 Q1 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C115 DFlipFlop_1/D nCLK 0.14fF
+C116 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C117 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C118 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C119 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.28fF
+C120 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C121 nCLK DFlipFlop_1/latch_diff_1/D 0.08fF
+C122 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C123 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C124 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C125 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C126 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C127 nQ2 Q0 0.23fF
+C128 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C129 Q1 nQ0 0.06fF
+C130 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C131 DFlipFlop_1/D nQ0 0.12fF
+C132 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C133 nCLK Q0 0.20fF
+C134 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C135 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C136 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C137 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C138 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C139 CLK vdd 0.41fF
+C140 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C141 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C142 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C143 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C144 Q0 nQ0 0.33fF
+C145 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C146 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C147 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C148 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C149 nQ2 vdd 0.04fF
+C150 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C151 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C152 Q1 DFlipFlop_3/nQ 0.10fF
+C153 Q1_shift vdd 0.10fF
+C154 nCLK vdd 0.34fF
+C155 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C156 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 DFlipFlop_2/nQ vss 0.50fF
+C172 Q1 vss 8.55fF
+C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 nQ0 vss 3.42fF
+C183 Q0 vss 0.53fF
+C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n317_n125# a_n33_n125# 0.08fF
+C1 a_n255_n151# a_n159_n151# 0.02fF
+C2 a_255_n125# a_n33_n125# 0.08fF
+C3 a_33_n151# a_n63_n151# 0.02fF
+C4 a_33_n151# a_129_n151# 0.02fF
+C5 a_n129_n125# a_n33_n125# 0.36fF
+C6 a_159_n125# a_n33_n125# 0.13fF
+C7 a_n225_n125# a_n33_n125# 0.13fF
+C8 a_n129_n125# a_n317_n125# 0.13fF
+C9 a_63_n125# a_n33_n125# 0.36fF
+C10 a_n317_n125# a_n225_n125# 0.36fF
+C11 a_n317_n125# a_63_n125# 0.06fF
+C12 a_n129_n125# a_255_n125# 0.06fF
+C13 a_159_n125# a_255_n125# 0.36fF
+C14 a_225_n151# a_129_n151# 0.02fF
+C15 a_n129_n125# a_159_n125# 0.08fF
+C16 a_255_n125# a_63_n125# 0.13fF
+C17 a_n129_n125# a_n225_n125# 0.36fF
+C18 a_159_n125# a_n225_n125# 0.06fF
+C19 a_n129_n125# a_63_n125# 0.13fF
+C20 a_159_n125# a_63_n125# 0.36fF
+C21 a_n159_n151# a_n63_n151# 0.02fF
+C22 a_63_n125# a_n225_n125# 0.08fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n455_n344# a_63_n125# 0.04fF
+C1 w_n455_n344# a_n317_n125# 0.11fF
+C2 w_n455_n344# a_255_n125# 0.11fF
+C3 a_159_n125# a_n33_n125# 0.13fF
+C4 a_159_n125# a_n225_n125# 0.06fF
+C5 a_n33_n125# a_n225_n125# 0.13fF
+C6 a_63_n125# a_n129_n125# 0.13fF
+C7 a_n317_n125# a_n129_n125# 0.13fF
+C8 a_255_n125# a_n129_n125# 0.06fF
+C9 a_63_n125# a_n317_n125# 0.06fF
+C10 a_255_n125# a_63_n125# 0.13fF
+C11 w_n455_n344# a_159_n125# 0.06fF
+C12 a_129_n154# a_225_n154# 0.02fF
+C13 w_n455_n344# a_n33_n125# 0.05fF
+C14 w_n455_n344# a_n225_n125# 0.06fF
+C15 a_n159_n154# a_n255_n154# 0.02fF
+C16 a_159_n125# a_n129_n125# 0.08fF
+C17 a_129_n154# a_33_n154# 0.02fF
+C18 a_n129_n125# a_n33_n125# 0.36fF
+C19 a_n129_n125# a_n225_n125# 0.36fF
+C20 a_159_n125# a_63_n125# 0.36fF
+C21 a_255_n125# a_159_n125# 0.36fF
+C22 a_n63_n154# a_33_n154# 0.02fF
+C23 a_63_n125# a_n33_n125# 0.36fF
+C24 a_n317_n125# a_n33_n125# 0.08fF
+C25 a_255_n125# a_n33_n125# 0.08fF
+C26 a_63_n125# a_n225_n125# 0.08fF
+C27 a_n317_n125# a_n225_n125# 0.36fF
+C28 w_n455_n344# a_n129_n125# 0.04fF
+C29 a_n63_n154# a_n159_n154# 0.02fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 out in 0.85fF
+C1 vdd in 0.04fF
+C2 out vdd 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in Up 0.12fF
+C1 inverter_cp_x1_0/out nDown 0.11fF
+C2 inverter_cp_x1_2/in vdd 0.42fF
+C3 Down vdd 0.09fF
+C4 nDown vdd 0.80fF
+C5 Down nDown 0.23fF
+C6 QB vdd 0.02fF
+C7 nUp Up 0.20fF
+C8 inverter_cp_x1_0/out vdd 0.25fF
+C9 QA vdd 0.02fF
+C10 Down inverter_cp_x1_0/out 0.12fF
+C11 nUp vdd 0.14fF
+C12 Up vdd 0.60fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_63_n90# a_n33_n90# 0.26fF
+C1 a_n129_n90# a_159_n90# 0.06fF
+C2 a_63_n90# a_159_n90# 0.26fF
+C3 a_n159_n207# a_n63_n116# 0.12fF
+C4 a_159_n90# a_n33_n90# 0.09fF
+C5 w_n359_n309# a_n221_n90# 0.09fF
+C6 a_n129_n90# a_n221_n90# 0.26fF
+C7 a_63_n90# a_n221_n90# 0.06fF
+C8 a_n129_n90# w_n359_n309# 0.06fF
+C9 a_63_n90# w_n359_n309# 0.06fF
+C10 a_n33_n90# a_n221_n90# 0.09fF
+C11 a_159_n90# a_n221_n90# 0.04fF
+C12 a_n33_n90# w_n359_n309# 0.05fF
+C13 a_159_n90# w_n359_n309# 0.09fF
+C14 a_n129_n90# a_63_n90# 0.09fF
+C15 a_n129_n90# a_n33_n90# 0.26fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n125_n45# 0.05fF
+C1 a_n33_n45# a_n125_n45# 0.13fF
+C2 a_33_n71# a_n129_71# 0.04fF
+C3 a_63_n45# a_n33_n45# 0.13fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 out A 0.06fF
+C1 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C2 B A 0.24fF
+C3 A vdd 0.09fF
+C4 B out 0.40fF
+C5 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
+C6 out vdd 0.11fF
+C7 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 Q vdd 0.08fF
+C1 Q nor_pfd_2/B 2.22fF
+C2 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C3 Q Reset 0.14fF
+C4 nor_pfd_3/A vdd 0.09fF
+C5 nor_pfd_2/A vdd -0.01fF
+C6 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C7 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C8 Reset nor_pfd_3/A 0.12fF
+C9 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C10 nor_pfd_2/B vdd 0.02fF
+C11 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C12 Q nor_pfd_3/A 0.98fF
+C13 Q nor_pfd_2/A 1.38fF
+C14 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C15 Reset nor_pfd_2/B 0.43fF
+C16 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C17 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C18 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C19 Q CLK 0.04fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_159_n45# a_n33_n45# 0.05fF
+C1 a_63_n45# a_159_n45# 0.13fF
+C2 a_159_n45# a_n221_n45# 0.02fF
+C3 a_n159_n173# a_n63_n71# 0.10fF
+C4 a_63_n45# a_n33_n45# 0.13fF
+C5 a_159_n45# a_n129_n45# 0.03fF
+C6 a_n221_n45# a_n33_n45# 0.05fF
+C7 a_63_n45# a_n221_n45# 0.03fF
+C8 a_n33_n45# a_n129_n45# 0.13fF
+C9 a_63_n45# a_n129_n45# 0.05fF
+C10 a_n221_n45# a_n129_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n125_n90# a_n33_n90# 0.26fF
+C1 a_63_n90# a_n33_n90# 0.26fF
+C2 a_n99_n187# a_33_n187# 0.04fF
+C3 a_n125_n90# a_63_n90# 0.09fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n73_n45# a_15_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_15_n90# w_n211_n309# 0.09fF
+C1 a_n73_n90# w_n211_n309# 0.04fF
+C2 a_15_n90# a_n73_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C1 A vdd 0.05fF
+C2 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C3 a_656_410# A 0.04fF
+C4 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C5 vdd out 0.10fF
+C6 a_656_410# out 0.20fF
+C7 a_656_410# B 0.30fF
+C8 A B 0.33fF
+C9 a_656_410# vdd 0.20fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C1 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C2 Down vdd 0.08fF
+C3 Up Down 0.06fF
+C4 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C5 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
+C6 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
+C7 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C8 Up vdd 1.62fF
+C9 vdd Reset 0.02fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v2_pex_c iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
++ pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
++ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
++ n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer D0_vco
+Xcharge_pump_0 nswitch vdd nUp vss Down biasp vco_vctrl pswitch iref_cp nDown Up charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vss
++ D0_vco ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 vdd buffer_salida_0/a_678_n100# 0.24fF
+C1 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C2 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C3 vdd nDown 0.22fF
+C4 nUp vdd 0.05fF
+C5 out_div_by_5 div_5_Q1_shift 0.05fF
+C6 n_out_by_2 vdd 1.03fF
+C7 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C8 biasp Up 0.26fF
+C9 vdd lf_vc 0.02fF
+C10 Down nDown 2.55fF
+C11 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C12 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C13 vco_vctrl out_by_2 0.53fF
+C14 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C15 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C16 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C17 n_out_by_2 div_5_Q0 -0.12fF
+C18 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C19 n_out_by_2 div_5_Q1 1.04fF
+C20 out_to_buffer out_to_div 0.13fF
+C21 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C22 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C23 vco_vctrl vdd -1.02fF
+C24 biasp nDown 0.26fF
+C25 n_out_by_2 div_5_nQ0 0.10fF
+C26 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C27 biasp nUp -0.17fF
+C28 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C29 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C30 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C31 vco_vctrl div_5_Q0 0.48fF
+C32 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
+C33 Up nUp 2.72fF
+C34 vco_vctrl div_5_Q1 0.14fF
+C35 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C36 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C37 nswitch nDown 0.76fF
+C38 vdd D0_vco 0.03fF
+C39 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C40 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C41 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C42 out_by_2 vdd 0.97fF
+C43 n_out_by_2 div_5_nQ2 0.10fF
+C44 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C45 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C46 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C47 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
+C48 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C49 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C50 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C51 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C52 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
+C53 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C54 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C55 out_by_2 div_5_Q0 0.09fF
+C56 nUp nDown -0.09fF
+C57 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C58 out_by_2 div_5_Q1 0.42fF
+C59 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
+C60 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C61 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C62 out_div_by_5 vdd 0.28fF
+C63 nswitch vco_vctrl -0.06fF
+C64 Up pswitch 1.98fF
+C65 div_5_nQ0 out_by_2 0.32fF
+C66 vdd QA -0.04fF
+C67 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
+C68 div_by_5_0/DFlipFlop_1/D out_by_2 0.38fF
+C69 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
+C70 out_div_by_5 div_5_Q1 0.01fF
+C71 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C72 vco_vctrl nUp 0.02fF
+C73 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C74 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C75 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C76 n_out_by_2 vco_vctrl 0.52fF
+C77 pswitch nDown 0.53fF
+C78 vdd out_to_div 0.21fF
+C79 out_by_2 div_5_nQ2 0.16fF
+C80 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C81 nUp pswitch 0.85fF
+C82 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C83 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C84 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C85 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C86 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C87 Up vdd 0.28fF
+C88 biasp Down 1.24fF
+C89 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C90 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C91 vdd iref_cp 0.15fF
+C92 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C93 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C94 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
+C95 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C96 out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.09fF
+C97 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C98 out_to_buffer vdd 0.07fF
+C99 Down iref_cp 0.09fF
+C100 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
+C101 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C102 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C103 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C104 nswitch Down 0.54fF
+C105 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C106 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
+C107 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.93fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss 1.39fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.76fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 6.05fF
+C141 Up vss 2.16fF
+C142 Down vss 6.16fF
+C143 nDown vss 3.38fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C158 div_5_Q1 vss 4.28fF
+C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_nQ0 vss 0.59fF
+C169 div_5_Q0 vss 0.01fF
+C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_to_buffer vss 1.57fF
+C196 out_to_div vss 4.46fF
+C197 out_first_buffer vss 2.88fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 D0_vco vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 n_out_buffer_div_2 vss 1.63fF
+C216 out_buffer_div_2 vss 1.60fF
+C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 lf_vc vss -59.89fF
+C232 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C233 DO_cap vss 0.01fF
+C234 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C235 nswitch vss 3.73fF
+C236 biasp vss 5.44fF
+C237 iref_cp vss 2.81fF
+C238 vco_vctrl vss -21.20fF
+C239 pswitch vss 3.57fF
+.ends
+
diff --git a/mag/extractions/top_pll_v2_pex_rc.spice b/mag/extractions/top_pll_v2_pex_rc.spice
new file mode 100644
index 0000000..172bdb5
--- /dev/null
+++ b/mag/extractions/top_pll_v2_pex_rc.spice
@@ -0,0 +1,2919 @@
+* NGSPICE file created from top_pll_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_n2319_n486# w_n2457_n634# 0.02fF
+C1 a_1803_n486# w_n2457_n634# 0.02fF
+C2 a_887_n486# w_n2457_n634# 0.02fF
+C3 a_n1861_n486# w_n2457_n634# 0.02fF
+C4 a_n1403_n486# w_n2457_n634# 0.02fF
+C5 a_1345_n486# w_n2457_n634# 0.02fF
+C6 a_n945_n486# w_n2457_n634# 0.02fF
+C7 a_2261_n486# w_n2457_n634# 0.02fF
+C8 a_429_n486# w_n2457_n634# 0.02fF
+C9 a_n487_n486# w_n2457_n634# 0.02fF
+C10 w_n2457_n634# a_n29_n486# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_687_n75# a_399_n75# 0.05fF
+C1 a_n1041_n75# a_n1137_n75# 0.22fF
+C2 a_207_n75# a_n177_n75# 0.03fF
+C3 a_n369_n75# a_n657_n75# 0.05fF
+C4 a_n945_n75# a_n753_n75# 0.08fF
+C5 a_n945_n75# a_n849_n75# 0.22fF
+C6 a_n945_n75# a_n657_n75# 0.05fF
+C7 a_n273_n75# a_15_n75# 0.05fF
+C8 a_n465_n75# a_n177_n75# 0.05fF
+C9 a_n273_n75# a_n561_n75# 0.05fF
+C10 a_n945_n75# a_n1229_n75# 0.05fF
+C11 a_n81_n75# a_15_n75# 0.22fF
+C12 a_975_n75# a_1167_n75# 0.08fF
+C13 a_n753_n75# a_n1137_n75# 0.03fF
+C14 a_111_n75# a_15_n75# 0.22fF
+C15 a_n849_n75# a_n1137_n75# 0.05fF
+C16 a_975_n75# a_591_n75# 0.03fF
+C17 a_n561_n75# a_n753_n75# 0.08fF
+C18 a_207_n75# a_n81_n75# 0.05fF
+C19 a_n561_n75# a_n849_n75# 0.05fF
+C20 a_399_n75# a_783_n75# 0.03fF
+C21 a_399_n75# a_15_n75# 0.03fF
+C22 a_n561_n75# a_n657_n75# 0.22fF
+C23 a_111_n75# a_207_n75# 0.22fF
+C24 a_n273_n75# a_n465_n75# 0.08fF
+C25 a_687_n75# a_1071_n75# 0.03fF
+C26 a_n1229_n75# a_n1137_n75# 0.22fF
+C27 a_207_n75# a_399_n75# 0.08fF
+C28 a_n465_n75# a_n81_n75# 0.03fF
+C29 a_n465_n75# a_n753_n75# 0.05fF
+C30 a_n849_n75# a_n465_n75# 0.03fF
+C31 a_n465_n75# a_n657_n75# 0.08fF
+C32 a_495_n75# a_303_n75# 0.08fF
+C33 a_n273_n75# a_n177_n75# 0.22fF
+C34 a_687_n75# a_303_n75# 0.03fF
+C35 a_879_n75# a_1071_n75# 0.08fF
+C36 a_687_n75# a_495_n75# 0.08fF
+C37 a_1071_n75# a_783_n75# 0.05fF
+C38 a_n177_n75# a_n81_n75# 0.22fF
+C39 a_399_n75# a_591_n75# 0.08fF
+C40 a_111_n75# a_n177_n75# 0.05fF
+C41 a_n1041_n75# a_n753_n75# 0.05fF
+C42 a_n849_n75# a_n1041_n75# 0.08fF
+C43 a_n1041_n75# a_n657_n75# 0.03fF
+C44 a_n273_n75# a_n81_n75# 0.08fF
+C45 a_879_n75# a_495_n75# 0.03fF
+C46 a_n273_n75# a_111_n75# 0.03fF
+C47 a_303_n75# a_15_n75# 0.05fF
+C48 a_n273_n75# a_n657_n75# 0.03fF
+C49 a_495_n75# a_783_n75# 0.05fF
+C50 a_n1041_n75# a_n1229_n75# 0.08fF
+C51 a_687_n75# a_879_n75# 0.08fF
+C52 a_1071_n75# a_1167_n75# 0.22fF
+C53 a_111_n75# a_n81_n75# 0.08fF
+C54 a_207_n75# a_303_n75# 0.22fF
+C55 a_687_n75# a_783_n75# 0.22fF
+C56 a_495_n75# a_207_n75# 0.05fF
+C57 a_n849_n75# a_n753_n75# 0.22fF
+C58 a_n753_n75# a_n657_n75# 0.22fF
+C59 a_n369_n75# a_15_n75# 0.03fF
+C60 a_111_n75# a_399_n75# 0.05fF
+C61 a_n849_n75# a_n657_n75# 0.08fF
+C62 a_n369_n75# a_n561_n75# 0.08fF
+C63 a_n945_n75# a_n1137_n75# 0.08fF
+C64 a_975_n75# a_1071_n75# 0.22fF
+C65 a_n945_n75# a_n561_n75# 0.03fF
+C66 a_n849_n75# a_n1229_n75# 0.03fF
+C67 a_303_n75# a_591_n75# 0.05fF
+C68 a_879_n75# a_783_n75# 0.22fF
+C69 a_n369_n75# a_n465_n75# 0.22fF
+C70 a_495_n75# a_591_n75# 0.22fF
+C71 a_687_n75# a_591_n75# 0.22fF
+C72 a_207_n75# a_15_n75# 0.08fF
+C73 a_975_n75# a_687_n75# 0.05fF
+C74 a_n369_n75# a_n177_n75# 0.08fF
+C75 a_879_n75# a_1167_n75# 0.05fF
+C76 a_n561_n75# a_n465_n75# 0.22fF
+C77 a_879_n75# a_591_n75# 0.05fF
+C78 a_1167_n75# a_783_n75# 0.03fF
+C79 a_303_n75# a_n81_n75# 0.03fF
+C80 a_783_n75# a_591_n75# 0.08fF
+C81 a_n945_n75# a_n1041_n75# 0.22fF
+C82 a_111_n75# a_303_n75# 0.08fF
+C83 a_111_n75# a_495_n75# 0.03fF
+C84 a_975_n75# a_879_n75# 0.22fF
+C85 a_n369_n75# a_n273_n75# 0.22fF
+C86 a_303_n75# a_399_n75# 0.22fF
+C87 a_975_n75# a_783_n75# 0.08fF
+C88 a_207_n75# a_591_n75# 0.03fF
+C89 a_n177_n75# a_15_n75# 0.08fF
+C90 a_495_n75# a_399_n75# 0.22fF
+C91 a_n369_n75# a_n81_n75# 0.05fF
+C92 a_n561_n75# a_n177_n75# 0.03fF
+C93 a_n369_n75# a_n753_n75# 0.03fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n129_n75# a_n513_n75# 0.03fF
+C1 a_831_n75# a_447_n75# 0.03fF
+C2 a_831_n75# a_543_n75# 0.05fF
+C3 a_639_n75# a_255_n75# 0.03fF
+C4 a_351_n75# a_447_n75# 0.22fF
+C5 a_351_n75# a_543_n75# 0.08fF
+C6 a_351_n75# a_63_n75# 0.05fF
+C7 a_n129_n75# a_255_n75# 0.03fF
+C8 a_n417_n75# a_n321_n75# 0.22fF
+C9 a_n897_n75# a_n705_n75# 0.08fF
+C10 a_159_n75# a_n129_n75# 0.05fF
+C11 a_n705_n75# a_n513_n75# 0.08fF
+C12 a_n225_n75# a_n321_n75# 0.22fF
+C13 a_927_n75# a_543_n75# 0.03fF
+C14 a_n801_n75# a_n609_n75# 0.08fF
+C15 a_n129_n75# a_n417_n75# 0.05fF
+C16 a_639_n75# a_447_n75# 0.08fF
+C17 a_63_n75# a_n321_n75# 0.03fF
+C18 a_639_n75# a_543_n75# 0.22fF
+C19 a_n225_n75# a_n129_n75# 0.22fF
+C20 a_n897_n75# a_n513_n75# 0.03fF
+C21 a_n129_n75# a_63_n75# 0.08fF
+C22 a_447_n75# a_735_n75# 0.05fF
+C23 a_735_n75# a_543_n75# 0.08fF
+C24 a_n705_n75# a_n417_n75# 0.05fF
+C25 a_n989_n75# a_n801_n75# 0.08fF
+C26 a_n513_n75# a_n417_n75# 0.22fF
+C27 a_159_n75# a_255_n75# 0.22fF
+C28 a_n225_n75# a_n513_n75# 0.05fF
+C29 a_351_n75# a_n33_n75# 0.03fF
+C30 a_447_n75# a_255_n75# 0.08fF
+C31 a_255_n75# a_543_n75# 0.05fF
+C32 a_255_n75# a_63_n75# 0.08fF
+C33 a_n989_n75# a_n609_n75# 0.03fF
+C34 a_159_n75# a_n225_n75# 0.03fF
+C35 a_n33_n75# a_n321_n75# 0.05fF
+C36 a_159_n75# a_447_n75# 0.05fF
+C37 a_159_n75# a_543_n75# 0.03fF
+C38 a_n609_n75# a_n321_n75# 0.05fF
+C39 a_n801_n75# a_n705_n75# 0.22fF
+C40 a_159_n75# a_63_n75# 0.22fF
+C41 a_n225_n75# a_n417_n75# 0.08fF
+C42 a_n129_n75# a_n33_n75# 0.22fF
+C43 a_n927_n101# a_33_n101# 0.08fF
+C44 a_831_n75# a_927_n75# 0.22fF
+C45 a_n225_n75# a_63_n75# 0.05fF
+C46 a_447_n75# a_543_n75# 0.22fF
+C47 a_831_n75# a_639_n75# 0.08fF
+C48 a_n897_n75# a_n801_n75# 0.22fF
+C49 a_n801_n75# a_n513_n75# 0.05fF
+C50 a_447_n75# a_63_n75# 0.03fF
+C51 a_351_n75# a_639_n75# 0.05fF
+C52 a_n705_n75# a_n609_n75# 0.22fF
+C53 a_831_n75# a_735_n75# 0.22fF
+C54 a_639_n75# a_927_n75# 0.05fF
+C55 a_351_n75# a_735_n75# 0.03fF
+C56 a_n897_n75# a_n609_n75# 0.05fF
+C57 a_n609_n75# a_n513_n75# 0.22fF
+C58 a_n801_n75# a_n417_n75# 0.03fF
+C59 a_n129_n75# a_n321_n75# 0.08fF
+C60 a_n33_n75# a_255_n75# 0.05fF
+C61 a_735_n75# a_927_n75# 0.08fF
+C62 a_159_n75# a_n33_n75# 0.08fF
+C63 a_n989_n75# a_n705_n75# 0.05fF
+C64 a_639_n75# a_735_n75# 0.22fF
+C65 a_n705_n75# a_n321_n75# 0.03fF
+C66 a_n33_n75# a_n417_n75# 0.03fF
+C67 a_351_n75# a_255_n75# 0.22fF
+C68 a_n609_n75# a_n417_n75# 0.08fF
+C69 a_n225_n75# a_n33_n75# 0.08fF
+C70 a_n225_n75# a_n609_n75# 0.03fF
+C71 a_n897_n75# a_n989_n75# 0.22fF
+C72 a_n33_n75# a_63_n75# 0.22fF
+C73 a_n513_n75# a_n321_n75# 0.08fF
+C74 a_351_n75# a_159_n75# 0.08fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n129_n150# a_63_n150# 0.16fF
+C1 a_159_n150# a_n225_n150# 0.07fF
+C2 a_n33_n150# a_n321_n150# 0.10fF
+C3 a_n513_n150# a_n129_n150# 0.07fF
+C4 a_n225_n150# a_63_n150# 0.10fF
+C5 a_735_n150# a_831_n150# 0.43fF
+C6 a_255_n150# a_447_n150# 0.16fF
+C7 a_n225_n150# a_n513_n150# 0.10fF
+C8 a_447_n150# a_639_n150# 0.16fF
+C9 a_n609_n150# a_n989_n150# 0.07fF
+C10 a_n705_n150# a_n989_n150# 0.10fF
+C11 a_639_n150# a_927_n150# 0.10fF
+C12 a_351_n150# a_543_n150# 0.16fF
+C13 a_n321_n150# a_63_n150# 0.07fF
+C14 a_n609_n150# a_n513_n150# 0.43fF
+C15 a_255_n150# a_639_n150# 0.07fF
+C16 a_n801_n150# a_n989_n150# 0.16fF
+C17 a_n705_n150# a_n513_n150# 0.16fF
+C18 a_n513_n150# a_n321_n150# 0.16fF
+C19 a_n989_n150# a_n897_n150# 0.43fF
+C20 a_351_n150# a_n33_n150# 0.07fF
+C21 a_255_n150# a_n129_n150# 0.07fF
+C22 a_n513_n150# a_n801_n150# 0.10fF
+C23 a_447_n150# a_735_n150# 0.10fF
+C24 a_n513_n150# a_n897_n150# 0.07fF
+C25 a_735_n150# a_927_n150# 0.16fF
+C26 a_159_n150# a_351_n150# 0.16fF
+C27 a_351_n150# a_63_n150# 0.10fF
+C28 a_639_n150# a_735_n150# 0.43fF
+C29 a_n225_n150# a_n129_n150# 0.43fF
+C30 a_n33_n150# a_n417_n150# 0.07fF
+C31 a_n129_n150# a_n321_n150# 0.16fF
+C32 a_159_n150# a_543_n150# 0.07fF
+C33 a_n225_n150# a_n609_n150# 0.07fF
+C34 a_543_n150# a_831_n150# 0.10fF
+C35 a_351_n150# a_447_n150# 0.43fF
+C36 a_n225_n150# a_n321_n150# 0.43fF
+C37 a_n513_n150# a_n417_n150# 0.43fF
+C38 a_n609_n150# a_n705_n150# 0.43fF
+C39 a_159_n150# a_n33_n150# 0.16fF
+C40 a_n609_n150# a_n321_n150# 0.10fF
+C41 a_255_n150# a_351_n150# 0.43fF
+C42 a_351_n150# a_639_n150# 0.10fF
+C43 a_n33_n150# a_63_n150# 0.43fF
+C44 a_n705_n150# a_n321_n150# 0.07fF
+C45 a_n609_n150# a_n801_n150# 0.16fF
+C46 a_n705_n150# a_n801_n150# 0.43fF
+C47 a_n609_n150# a_n897_n150# 0.10fF
+C48 a_447_n150# a_543_n150# 0.43fF
+C49 a_n705_n150# a_n897_n150# 0.16fF
+C50 a_159_n150# a_63_n150# 0.43fF
+C51 a_33_n247# a_n927_n247# 0.09fF
+C52 a_543_n150# a_927_n150# 0.07fF
+C53 a_n801_n150# a_n897_n150# 0.43fF
+C54 a_255_n150# a_543_n150# 0.10fF
+C55 a_543_n150# a_639_n150# 0.43fF
+C56 a_351_n150# a_735_n150# 0.07fF
+C57 a_n417_n150# a_n129_n150# 0.10fF
+C58 a_255_n150# a_n33_n150# 0.10fF
+C59 a_n225_n150# a_n417_n150# 0.16fF
+C60 a_159_n150# a_447_n150# 0.10fF
+C61 a_447_n150# a_831_n150# 0.07fF
+C62 a_447_n150# a_63_n150# 0.07fF
+C63 a_831_n150# a_927_n150# 0.43fF
+C64 a_n33_n150# a_n129_n150# 0.43fF
+C65 a_543_n150# a_735_n150# 0.16fF
+C66 a_n609_n150# a_n417_n150# 0.16fF
+C67 a_255_n150# a_159_n150# 0.43fF
+C68 a_n705_n150# a_n417_n150# 0.10fF
+C69 a_n417_n150# a_n321_n150# 0.43fF
+C70 a_255_n150# a_63_n150# 0.16fF
+C71 a_639_n150# a_831_n150# 0.16fF
+C72 a_n33_n150# a_n225_n150# 0.16fF
+C73 a_n417_n150# a_n801_n150# 0.07fF
+C74 a_159_n150# a_n129_n150# 0.10fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n1461_n44# a_n1103_n44# 0.04fF
+C1 a_n387_n44# a_n29_n44# 0.04fF
+C2 a_n1819_n44# a_n1461_n44# 0.04fF
+C3 a_687_n44# a_1045_n44# 0.04fF
+C4 a_687_n44# a_329_n44# 0.04fF
+C5 a_1403_n44# a_1761_n44# 0.04fF
+C6 a_n387_n44# a_n745_n44# 0.04fF
+C7 a_n29_n44# a_329_n44# 0.04fF
+C8 a_n1103_n44# a_n745_n44# 0.04fF
+C9 a_1403_n44# a_1045_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n753_n150# a_n369_n150# 0.07fF
+C1 a_n81_n150# a_207_n150# 0.10fF
+C2 a_n849_n150# a_n561_n150# 0.10fF
+C3 a_n753_n150# a_n465_n150# 0.10fF
+C4 a_n753_n150# a_n561_n150# 0.16fF
+C5 a_15_n150# a_111_n150# 0.43fF
+C6 a_783_n150# a_687_n150# 0.43fF
+C7 a_n273_n150# a_n657_n150# 0.07fF
+C8 a_1167_n150# a_783_n150# 0.07fF
+C9 a_n273_n150# a_111_n150# 0.07fF
+C10 a_n369_n150# a_n657_n150# 0.10fF
+C11 a_495_n150# a_111_n150# 0.07fF
+C12 a_591_n150# a_975_n150# 0.07fF
+C13 a_n177_n150# a_15_n150# 0.16fF
+C14 a_591_n150# a_495_n150# 0.43fF
+C15 a_n273_n150# a_n177_n150# 0.43fF
+C16 a_303_n150# a_399_n150# 0.43fF
+C17 a_n465_n150# a_n657_n150# 0.16fF
+C18 a_n369_n150# a_n177_n150# 0.16fF
+C19 a_n81_n150# a_15_n150# 0.43fF
+C20 a_n657_n150# a_n561_n150# 0.43fF
+C21 a_879_n150# a_1071_n150# 0.16fF
+C22 a_n273_n150# a_n81_n150# 0.16fF
+C23 a_n177_n150# a_n465_n150# 0.10fF
+C24 a_n369_n150# a_n81_n150# 0.10fF
+C25 a_783_n150# a_975_n150# 0.16fF
+C26 a_n177_n150# a_n561_n150# 0.07fF
+C27 a_15_n150# a_207_n150# 0.16fF
+C28 a_783_n150# a_495_n150# 0.10fF
+C29 a_1167_n150# w_n1367_n369# 0.14fF
+C30 a_n81_n150# a_n465_n150# 0.07fF
+C31 a_495_n150# a_207_n150# 0.10fF
+C32 a_n753_n150# a_n849_n150# 0.43fF
+C33 a_399_n150# a_111_n150# 0.10fF
+C34 a_687_n150# a_975_n150# 0.10fF
+C35 a_399_n150# a_591_n150# 0.16fF
+C36 a_n1229_n150# a_n849_n150# 0.07fF
+C37 a_1167_n150# a_975_n150# 0.16fF
+C38 a_687_n150# a_495_n150# 0.16fF
+C39 a_n1041_n150# a_n849_n150# 0.16fF
+C40 a_n849_n150# a_n657_n150# 0.16fF
+C41 w_n1367_n369# a_975_n150# 0.05fF
+C42 a_n945_n150# a_n561_n150# 0.07fF
+C43 a_n849_n150# a_n1137_n150# 0.10fF
+C44 a_399_n150# a_783_n150# 0.07fF
+C45 a_591_n150# a_879_n150# 0.10fF
+C46 a_n273_n150# a_15_n150# 0.10fF
+C47 a_303_n150# a_111_n150# 0.16fF
+C48 a_399_n150# a_207_n150# 0.16fF
+C49 a_n753_n150# a_n1041_n150# 0.10fF
+C50 a_n369_n150# a_15_n150# 0.07fF
+C51 a_303_n150# a_591_n150# 0.10fF
+C52 a_n753_n150# a_n657_n150# 0.43fF
+C53 a_n273_n150# a_n369_n150# 0.43fF
+C54 a_n753_n150# a_n1137_n150# 0.07fF
+C55 a_n1041_n150# a_n1229_n150# 0.16fF
+C56 a_399_n150# a_687_n150# 0.10fF
+C57 a_n1229_n150# a_n1137_n150# 0.43fF
+C58 a_783_n150# a_1071_n150# 0.10fF
+C59 a_n273_n150# a_n465_n150# 0.16fF
+C60 a_n369_n150# a_n465_n150# 0.43fF
+C61 a_303_n150# a_n81_n150# 0.07fF
+C62 a_n273_n150# a_n561_n150# 0.10fF
+C63 a_783_n150# a_879_n150# 0.43fF
+C64 a_n1041_n150# a_n657_n150# 0.07fF
+C65 a_n369_n150# a_n561_n150# 0.16fF
+C66 a_n1041_n150# a_n1137_n150# 0.43fF
+C67 a_687_n150# a_1071_n150# 0.07fF
+C68 a_1167_n150# a_1071_n150# 0.43fF
+C69 a_n945_n150# a_n849_n150# 0.43fF
+C70 a_303_n150# a_207_n150# 0.43fF
+C71 a_n465_n150# a_n561_n150# 0.43fF
+C72 a_879_n150# a_687_n150# 0.16fF
+C73 a_399_n150# a_15_n150# 0.07fF
+C74 a_1167_n150# a_879_n150# 0.10fF
+C75 a_n177_n150# a_111_n150# 0.10fF
+C76 a_303_n150# a_687_n150# 0.07fF
+C77 a_399_n150# a_495_n150# 0.43fF
+C78 w_n1367_n369# a_1071_n150# 0.07fF
+C79 a_n945_n150# a_n753_n150# 0.16fF
+C80 a_n81_n150# a_111_n150# 0.16fF
+C81 a_n945_n150# a_n1229_n150# 0.10fF
+C82 w_n1367_n369# a_879_n150# 0.04fF
+C83 a_975_n150# a_1071_n150# 0.43fF
+C84 a_n81_n150# a_n177_n150# 0.43fF
+C85 a_591_n150# a_783_n150# 0.16fF
+C86 a_111_n150# a_207_n150# 0.43fF
+C87 a_591_n150# a_207_n150# 0.07fF
+C88 a_879_n150# a_975_n150# 0.43fF
+C89 a_n945_n150# a_n1041_n150# 0.43fF
+C90 a_n945_n150# a_n657_n150# 0.10fF
+C91 a_303_n150# a_15_n150# 0.10fF
+C92 a_879_n150# a_495_n150# 0.07fF
+C93 a_n945_n150# a_n1137_n150# 0.16fF
+C94 a_n177_n150# a_207_n150# 0.07fF
+C95 a_591_n150# a_687_n150# 0.43fF
+C96 a_303_n150# a_495_n150# 0.16fF
+C97 a_n849_n150# a_n465_n150# 0.07fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vdd nUp vss Down biasp out pswitch iref nDown Up
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 nswitch vdd 0.07fF
+C1 vdd out 6.66fF
+C2 Down nDown 0.13fF
+C3 vdd pswitch 3.98fF
+C4 Down nswitch 2.27fF
+C5 nswitch nDown 0.31fF
+C6 nswitch out 1.28fF
+C7 nswitch pswitch 0.06fF
+C8 pswitch out 4.91fF
+C9 nswitch iref 1.91fF
+C10 biasp vdd 2.64fF
+C11 Down nUp 0.25fF
+C12 Up pswitch 0.70fF
+C13 nswitch biasp 0.03fF
+C14 nUp out 0.31fF
+C15 biasp pswitch 3.11fF
+C16 nUp pswitch 5.66fF
+C17 biasp iref 0.80fF
+C18 Up nUp 0.15fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C1 m3_7988_2700# m3_7988_n2600# 3.39fF
+C2 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C3 m3_n7969_2700# m3_n7969_n2600# 3.28fF
+C4 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C5 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C6 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C7 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C8 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
+C9 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C10 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C11 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C12 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C13 m3_2669_2700# m3_2669_n2600# 3.28fF
+C14 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C15 m3_7988_8000# m3_7988_2700# 3.39fF
+C16 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C17 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C18 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C19 m3_2669_2700# m3_2669_8000# 3.28fF
+C20 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C21 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C22 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C23 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C24 m3_2669_2700# m3_n2650_2700# 2.73fF
+C25 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C26 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C27 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C28 m3_n2650_n2600# m3_n7969_n2600# 2.73fF
+C29 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C30 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C31 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C32 m3_2669_8000# c1_n13188_n13100# 58.61fF
+C33 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C34 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C35 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C36 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C37 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C38 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C39 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C40 m3_2669_8000# m3_n2650_8000# 2.73fF
+C41 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C42 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C43 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C44 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C45 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C46 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C47 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C48 m3_2669_n2600# m3_n2650_n2600# 2.73fF
+C49 m3_2669_2700# m3_7988_2700# 2.73fF
+C50 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C51 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C52 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C53 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C54 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C55 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C56 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
+C57 m3_2669_n13200# m3_7988_n13200# 2.73fF
+C58 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C59 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C60 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C61 m3_7988_8000# m3_2669_8000# 2.73fF
+C62 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C63 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C64 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 c1_n4209_n4150# c1_110_n4150# 1.32fF
+C1 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C2 m3_10_n4250# c1_110_n4150# 81.11fF
+C3 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C4 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C5 c1_n4209_n4150# m3_n4309_50# 38.10fF
+C6 m3_10_n4250# m3_n4309_50# 1.75fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 in out 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C1 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C2 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C3 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C4 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C5 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C6 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C7 c1_2269_n6300# c1_n2050_n6300# 1.99fF
+C8 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C9 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C10 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C11 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
+C12 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
+C13 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C14 c1_2269_n6300# m3_2169_n6400# 121.67fF
+C15 m3_n2150_2200# m3_n2150_n2100# 2.63fF
+C16 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C17 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C18 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_30_n300# a_n88_n300# 0.61fF
+C1 a_n118_n388# a_n88_n300# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 D0_cap in 0.07fF
+C1 vc_pex in 0.18fF
+C2 in cap3_loop_filter_0/in 0.79fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n311_n344# a_n173_n125# 0.14fF
+C1 a_n111_n156# a_n15_n156# 0.02fF
+C2 w_n311_n344# a_111_n125# 0.14fF
+C3 a_n81_n125# a_15_n125# 0.36fF
+C4 a_n15_n156# a_81_n156# 0.02fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 a_n81_n125# a_111_n125# 0.13fF
+C7 w_n311_n344# a_n81_n125# 0.09fF
+C8 a_15_n125# a_n173_n125# 0.13fF
+C9 a_111_n125# a_15_n125# 0.36fF
+C10 w_n311_n344# a_15_n125# 0.09fF
+C11 a_111_n125# a_n173_n125# 0.08fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n15_n151# a_n111_n151# 0.02fF
+C1 a_81_n151# a_n15_n151# 0.02fF
+C2 a_n81_n125# a_111_n125# 0.13fF
+C3 a_15_n125# a_111_n125# 0.36fF
+C4 a_15_n125# a_n81_n125# 0.36fF
+C5 a_n173_n125# a_111_n125# 0.08fF
+C6 a_n173_n125# a_n81_n125# 0.36fF
+C7 a_n173_n125# a_15_n125# 0.13fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_187_n605# m1_45_n513# 0.36fF
+C1 m1_187_n605# vdd 0.55fF
+C2 m1_45_n513# vdd 0.69fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n81_n125# 0.13fF
+C1 a_15_n125# a_n173_n125# 0.13fF
+C2 a_n173_n125# w_n311_n344# 0.14fF
+C3 a_111_n125# a_n173_n125# 0.08fF
+C4 a_n81_n125# a_n173_n125# 0.36fF
+C5 a_15_n125# w_n311_n344# 0.09fF
+C6 a_111_n125# a_15_n125# 0.36fF
+C7 a_111_n125# w_n311_n344# 0.14fF
+C8 a_15_n125# a_n81_n125# 0.36fF
+C9 a_n81_n125# w_n311_n344# 0.09fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n81_n125# 0.13fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 a_n173_n125# a_n81_n125# 0.36fF
+C4 a_111_n125# a_15_n125# 0.36fF
+C5 a_n173_n125# a_111_n125# 0.08fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 in out 0.32fF
+C1 out vdd 0.10fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in CLK_d 0.12fF
+C1 nCLK_d vdd 0.03fF
+C2 CLK vdd 0.36fF
+C3 nCLK_d inverter_cp_x1_0/out 0.11fF
+C4 inverter_cp_x1_2/in vdd 0.21fF
+C5 inverter_cp_x1_0/out vdd 0.28fF
+C6 CLK inverter_cp_x1_2/in 0.31fF
+C7 CLK inverter_cp_x1_0/out 0.31fF
+C8 CLK_d vdd 0.03fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_63_n95# 0.10fF
+C1 w_n263_n314# a_n33_n95# 0.08fF
+C2 w_n263_n314# a_63_n95# 0.11fF
+C3 w_n263_n314# a_n125_n95# 0.11fF
+C4 a_63_n95# a_n33_n95# 0.28fF
+C5 a_n125_n95# a_n33_n95# 0.28fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_111_n125# 0.13fF
+C1 a_n129_n213# a_15_n125# 0.10fF
+C2 a_n129_n213# a_n173_n125# 0.02fF
+C3 a_n173_n125# a_15_n125# 0.13fF
+C4 a_n129_n213# a_111_n125# 0.01fF
+C5 a_n129_n213# a_n81_n125# 0.10fF
+C6 a_111_n125# a_15_n125# 0.36fF
+C7 a_n173_n125# a_111_n125# 0.08fF
+C8 a_n81_n125# a_15_n125# 0.36fF
+C9 a_n81_n125# a_n173_n125# 0.36fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n81_n183# a_n125_n95# 0.16fF
+C1 a_n81_n183# a_n33_n95# 0.10fF
+C2 a_n33_n95# a_n125_n95# 0.88fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 CLK m1_657_280# 0.24fF
+C1 Q m1_657_280# 0.94fF
+C2 nQ vdd 0.16fF
+C3 nD nQ 0.05fF
+C4 D nQ 0.05fF
+C5 Q vdd 0.16fF
+C6 Q nD 0.05fF
+C7 Q D 0.05fF
+C8 Q nQ 0.93fF
+C9 nQ m1_657_280# 1.41fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
++ nCLK latch_diff_0/nD
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_0/nD latch_diff_1/D 0.41fF
+C1 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C2 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C3 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
+C4 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C5 vdd latch_diff_1/D 0.03fF
+C6 latch_diff_1/nD vdd 0.02fF
+C7 latch_diff_0/D vdd 0.09fF
+C8 latch_diff_1/nD Q 0.01fF
+C9 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C10 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C11 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
+C12 latch_diff_1/nD latch_diff_1/D 0.33fF
+C13 latch_diff_0/D latch_diff_1/D 0.11fF
+C14 latch_diff_1/nD latch_diff_0/D 0.04fF
+C15 nQ latch_diff_1/D 0.11fF
+C16 latch_diff_1/nD nQ 0.08fF
+C17 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C18 vdd latch_diff_0/nD 0.14fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n159_n110# a_n63_n110# 0.02fF
+C1 a_n33_n84# w_n359_n303# 0.05fF
+C2 w_n359_n303# a_n129_n84# 0.06fF
+C3 a_159_n84# a_63_n84# 0.24fF
+C4 a_159_n84# a_n221_n84# 0.04fF
+C5 a_n33_n84# a_63_n84# 0.24fF
+C6 a_n63_n110# a_33_n110# 0.02fF
+C7 a_n221_n84# a_n33_n84# 0.09fF
+C8 a_63_n84# a_n129_n84# 0.09fF
+C9 a_n221_n84# a_n129_n84# 0.24fF
+C10 w_n359_n303# a_63_n84# 0.06fF
+C11 a_n221_n84# w_n359_n303# 0.08fF
+C12 a_129_n110# a_33_n110# 0.02fF
+C13 a_n221_n84# a_63_n84# 0.05fF
+C14 a_159_n84# a_n33_n84# 0.09fF
+C15 a_159_n84# a_n129_n84# 0.05fF
+C16 a_n33_n84# a_n129_n84# 0.24fF
+C17 a_159_n84# w_n359_n303# 0.08fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_n159_n68# 0.02fF
+C1 a_n63_n68# a_33_n68# 0.02fF
+C2 a_n33_n42# a_n221_n42# 0.05fF
+C3 a_n33_n42# a_159_n42# 0.05fF
+C4 a_n129_n42# a_n33_n42# 0.12fF
+C5 a_63_n42# a_n33_n42# 0.12fF
+C6 a_159_n42# a_n221_n42# 0.02fF
+C7 a_n129_n42# a_n221_n42# 0.12fF
+C8 a_63_n42# a_n221_n42# 0.03fF
+C9 a_n129_n42# a_159_n42# 0.03fF
+C10 a_63_n42# a_159_n42# 0.12fF
+C11 a_63_n42# a_n129_n42# 0.05fF
+C12 a_33_n68# a_129_n68# 0.02fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 in out 0.67fF
+C1 vdd out 0.62fF
+C2 in vdd 0.33fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n125_n42# a_n33_n42# 0.12fF
+C1 a_n125_n42# a_63_n42# 0.05fF
+C2 a_n63_n68# a_33_n68# 0.02fF
+C3 a_63_n42# a_n33_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 w_n263_n303# a_n33_n84# 0.07fF
+C1 a_63_n84# a_n33_n84# 0.24fF
+C2 w_n263_n303# a_n125_n84# 0.10fF
+C3 a_63_n84# a_n125_n84# 0.09fF
+C4 a_n33_n84# a_n125_n84# 0.24fF
+C5 w_n263_n303# a_63_n84# 0.10fF
+C6 a_33_n110# a_n63_n110# 0.02fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 in out 0.30fF
+C1 vdd out 0.15fF
+C2 vdd in 0.01fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 CLK_2 vdd 0.08fF
+C1 o1 out_div 0.01fF
+C2 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C3 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C4 vdd DFlipFlop_0/CLK 0.40fF
+C5 out_div vdd 0.03fF
+C6 nout_div DFlipFlop_0/nCLK 0.43fF
+C7 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C8 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
+C9 nCLK_2 vdd 0.08fF
+C10 DFlipFlop_0/latch_diff_0/nD nout_div 0.07fF
+C11 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/CLK -0.48fF
+C12 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C13 o1 vdd 0.14fF
+C14 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C15 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C16 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C17 nout_div DFlipFlop_0/latch_diff_1/m1_657_280# 0.21fF
+C18 nCLK_2 o2 0.11fF
+C19 nout_div DFlipFlop_0/CLK 0.42fF
+C20 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C21 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C22 nout_div out_div 0.22fF
+C23 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C24 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C25 o2 vdd 0.14fF
+C26 vdd DFlipFlop_0/nCLK 0.30fF
+C27 DFlipFlop_0/latch_diff_0/D DFlipFlop_0/nCLK 0.13fF
+C28 nout_div vdd 0.16fF
+C29 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C30 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C31 o1 CLK_2 0.11fF
+C32 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
+C33 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C34 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C35 nCLK_2 vss 1.08fF
+C36 o2 vss 2.21fF
+C37 CLK_2 vss 1.08fF
+C38 o1 vss 2.21fF
+C39 DFlipFlop_0/CLK vss 1.03fF
+C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C42 CLK vss 3.27fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n221_n600# a_n257_n777# 0.25fF
+C1 a_n257_n777# a_n129_n600# 0.29fF
+C2 a_n221_n600# a_n129_n600# 7.87fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n221_n300# a_n257_n404# 0.21fF
+C1 a_n129_n300# a_n221_n300# 4.05fF
+C2 a_n129_n300# a_n257_n404# 0.30fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 a_3996_n100# vdd 3.68fF
+C1 vdd a_678_n100# 0.08fF
+C2 out vdd 47.17fF
+C3 a_3996_n100# a_678_n100# 6.52fF
+C4 in vdd 0.02fF
+C5 out a_3996_n100# 55.19fF
+C6 in a_678_n100# 0.81fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n238# a_15_n150# 0.02fF
+C1 a_n73_n150# a_n33_n238# 0.02fF
+C2 a_n73_n150# a_15_n150# 0.51fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# w_n211_n369# 0.20fF
+C1 w_n211_n369# a_n73_n150# 0.20fF
+C2 a_15_n150# a_n73_n150# 0.51fF
+C3 a_n33_181# w_n211_n369# 0.05fF
+C4 a_15_n150# a_n33_181# 0.01fF
+C5 a_n33_181# a_n73_n150# 0.01fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_63_n150# a_n129_n150# 0.16fF
+C1 a_n321_n150# a_63_n150# 0.07fF
+C2 a_447_n150# a_63_n150# 0.07fF
+C3 a_159_n150# a_n225_n150# 0.07fF
+C4 a_n33_n150# a_159_n150# 0.16fF
+C5 a_n465_172# a_n129_n150# 0.10fF
+C6 a_n321_n150# a_n465_172# 0.10fF
+C7 a_n465_172# a_n417_n150# 0.10fF
+C8 a_447_n150# a_n465_172# 0.01fF
+C9 a_n33_n150# a_255_n150# 0.10fF
+C10 a_n321_n150# a_n129_n150# 0.16fF
+C11 a_n129_n150# a_n417_n150# 0.10fF
+C12 a_159_n150# a_351_n150# 0.16fF
+C13 a_n321_n150# a_n417_n150# 0.43fF
+C14 a_63_n150# a_n225_n150# 0.10fF
+C15 a_n33_n150# a_63_n150# 0.43fF
+C16 a_n509_n150# a_n465_172# 0.01fF
+C17 a_n465_172# a_n225_n150# 0.10fF
+C18 a_255_n150# a_351_n150# 0.43fF
+C19 a_n33_n150# a_n465_172# 0.10fF
+C20 a_n509_n150# a_n129_n150# 0.07fF
+C21 a_n321_n150# a_n509_n150# 0.16fF
+C22 a_n509_n150# a_n417_n150# 0.43fF
+C23 a_63_n150# a_351_n150# 0.10fF
+C24 a_n225_n150# a_n129_n150# 0.43fF
+C25 a_n33_n150# a_n129_n150# 0.43fF
+C26 a_n321_n150# a_n225_n150# 0.43fF
+C27 a_n225_n150# a_n417_n150# 0.16fF
+C28 a_n33_n150# a_n321_n150# 0.10fF
+C29 a_n33_n150# a_n417_n150# 0.07fF
+C30 a_n465_172# a_351_n150# 0.10fF
+C31 a_n509_n150# a_n225_n150# 0.10fF
+C32 a_447_n150# a_351_n150# 0.43fF
+C33 a_n33_n150# a_n225_n150# 0.16fF
+C34 a_255_n150# a_159_n150# 0.43fF
+C35 a_n33_n150# a_351_n150# 0.07fF
+C36 a_63_n150# a_159_n150# 0.43fF
+C37 a_159_n150# a_n465_172# 0.10fF
+C38 a_255_n150# a_63_n150# 0.16fF
+C39 a_159_n150# a_n129_n150# 0.10fF
+C40 a_255_n150# a_n465_172# 0.10fF
+C41 a_447_n150# a_159_n150# 0.10fF
+C42 a_63_n150# a_n465_172# 0.10fF
+C43 a_255_n150# a_n129_n150# 0.07fF
+C44 a_255_n150# a_447_n150# 0.16fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n321_n150# a_n509_n150# 0.16fF
+C1 a_n33_n150# a_255_n150# 0.10fF
+C2 w_n647_n369# a_159_n150# 0.04fF
+C3 a_n129_n150# a_63_n150# 0.16fF
+C4 a_n225_n150# a_n129_n150# 0.43fF
+C5 a_n225_n150# a_n417_n150# 0.16fF
+C6 a_n465_n247# a_159_n150# 0.08fF
+C7 a_n321_n150# a_n33_n150# 0.10fF
+C8 w_n647_n369# a_n509_n150# 0.14fF
+C9 a_n417_n150# a_n129_n150# 0.10fF
+C10 a_63_n150# a_159_n150# 0.43fF
+C11 w_n647_n369# a_255_n150# 0.05fF
+C12 a_n225_n150# a_159_n150# 0.07fF
+C13 a_447_n150# w_n647_n369# 0.14fF
+C14 a_351_n150# a_159_n150# 0.16fF
+C15 a_n465_n247# a_255_n150# 0.08fF
+C16 w_n647_n369# a_n33_n150# 0.02fF
+C17 a_n321_n150# w_n647_n369# 0.05fF
+C18 a_n129_n150# a_159_n150# 0.10fF
+C19 a_n225_n150# a_n509_n150# 0.10fF
+C20 a_63_n150# a_255_n150# 0.16fF
+C21 a_447_n150# a_63_n150# 0.07fF
+C22 a_n465_n247# a_n33_n150# 0.08fF
+C23 a_n321_n150# a_n465_n247# 0.08fF
+C24 a_351_n150# a_255_n150# 0.43fF
+C25 a_351_n150# a_447_n150# 0.43fF
+C26 a_n129_n150# a_n509_n150# 0.07fF
+C27 a_n417_n150# a_n509_n150# 0.43fF
+C28 a_n33_n150# a_63_n150# 0.43fF
+C29 a_n321_n150# a_63_n150# 0.07fF
+C30 a_n225_n150# a_n33_n150# 0.16fF
+C31 a_n129_n150# a_255_n150# 0.07fF
+C32 a_n225_n150# a_n321_n150# 0.43fF
+C33 a_351_n150# a_n33_n150# 0.07fF
+C34 a_n465_n247# w_n647_n369# 0.47fF
+C35 a_n129_n150# a_n33_n150# 0.43fF
+C36 a_n417_n150# a_n33_n150# 0.07fF
+C37 a_n321_n150# a_n129_n150# 0.16fF
+C38 a_n321_n150# a_n417_n150# 0.43fF
+C39 a_159_n150# a_255_n150# 0.43fF
+C40 w_n647_n369# a_63_n150# 0.02fF
+C41 a_447_n150# a_159_n150# 0.10fF
+C42 a_n225_n150# w_n647_n369# 0.04fF
+C43 a_351_n150# w_n647_n369# 0.07fF
+C44 a_n465_n247# a_63_n150# 0.08fF
+C45 a_n33_n150# a_159_n150# 0.16fF
+C46 a_n225_n150# a_n465_n247# 0.08fF
+C47 w_n647_n369# a_n129_n150# 0.02fF
+C48 a_n417_n150# w_n647_n369# 0.07fF
+C49 a_n465_n247# a_351_n150# 0.08fF
+C50 a_447_n150# a_255_n150# 0.16fF
+C51 a_n225_n150# a_63_n150# 0.10fF
+C52 a_351_n150# a_63_n150# 0.10fF
+C53 a_n465_n247# a_n129_n150# 0.08fF
+C54 a_n465_n247# a_n417_n150# 0.08fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n99# a_n73_n11# 0.02fF
+C1 a_n33_n99# a_15_n11# 0.02fF
+C2 a_n73_n11# a_15_n11# 0.15fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_n78_n114# 0.20fF
+C1 a_20_n114# a_n78_n114# 0.42fF
+C2 a_20_n114# w_n216_n334# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vbulkp vdd 0.04fF
+C1 in vdd 0.01fF
+C2 in vss 0.01fF
+C3 out vbulkp 0.08fF
+C4 out in 0.11fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 inverter_csvco_0/vdd vbp 0.75fF
+C1 inverter_csvco_0/vdd in 0.01fF
+C2 out D0 0.09fF
+C3 inverter_csvco_0/vdd vdd 1.89fF
+C4 cap_vco_0/t vdd 0.04fF
+C5 in inverter_csvco_0/vss 0.01fF
+C6 vbp vdd 1.21fF
+C7 inverter_csvco_0/vss D0 0.02fF
+C8 out inverter_csvco_0/vdd 0.02fF
+C9 out cap_vco_0/t 0.70fF
+C10 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C11 vctrl inverter_csvco_0/vss 0.87fF
+C12 out in 0.06fF
+C13 out inverter_csvco_0/vss 0.03fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vdd vss csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C1 csvco_branch_2/vbp vctrl 0.06fF
+C2 D0 csvco_branch_1/inverter_csvco_0/vss 0.68fF
+C3 D0 csvco_branch_0/inverter_csvco_0/vss 0.49fF
+C4 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C5 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C6 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss 0.06fF
+C7 csvco_branch_1/cap_vco_0/t out_vco 0.03fF
+C8 csvco_branch_1/in out_vco 0.76fF
+C9 csvco_branch_2/in out_vco 0.58fF
+C10 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C11 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
+C12 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C13 D0 vctrl 4.41fF
+C14 vdd csvco_branch_2/vbp 1.49fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 out_pad out_div 0.15fF
+C1 vdd out_pad 0.10fF
+C2 vdd out_div 0.17fF
+C3 o1 out_div 0.11fF
+C4 vdd o1 0.09fF
+C5 in_vco vss 0.83fF
+C6 out_pad vss 0.70fF
+C7 out_div vss 3.00fF
+C8 vdd vss 14.54fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_194_125# VGND 0.25fF
+C1 B A 0.28fF
+C2 a_355_368# B 0.08fF
+C3 VPWR X 0.07fF
+C4 VPWR A 0.15fF
+C5 B VGND 0.10fF
+C6 VPWR a_355_368# 0.37fF
+C7 B a_194_125# 0.57fF
+C8 VPWR VGND 0.01fF
+C9 VPWR VPB 0.06fF
+C10 VPWR a_194_125# 0.33fF
+C11 VPWR B 0.09fF
+C12 a_355_368# X 0.17fF
+C13 a_355_368# A 0.02fF
+C14 a_194_125# a_158_392# 0.06fF
+C15 X VGND 0.28fF
+C16 a_194_125# X 0.29fF
+C17 VGND A 0.31fF
+C18 a_194_125# A 0.18fF
+C19 a_355_368# a_194_125# 0.51fF
+C20 B X 0.13fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 A B 0.08fF
+C1 VPB VPWR 0.04fF
+C2 a_56_136# X 0.26fF
+C3 VGND X 0.15fF
+C4 a_56_136# B 0.30fF
+C5 VGND B 0.03fF
+C6 A VPWR 0.07fF
+C7 a_56_136# VPWR 0.57fF
+C8 a_56_136# A 0.17fF
+C9 A VGND 0.21fF
+C10 X B 0.02fF
+C11 a_56_136# VGND 0.06fF
+C12 X VPWR 0.20fF
+C13 B VPWR 0.02fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VPWR a_63_368# 0.29fF
+C1 VPWR A 0.05fF
+C2 a_152_368# a_63_368# 0.03fF
+C3 X a_63_368# 0.33fF
+C4 B a_63_368# 0.14fF
+C5 X A 0.02fF
+C6 B A 0.10fF
+C7 VGND a_63_368# 0.27fF
+C8 VPWR VPB 0.04fF
+C9 X VPWR 0.18fF
+C10 B VPWR 0.01fF
+C11 VGND X 0.16fF
+C12 B VGND 0.11fF
+C13 a_63_368# A 0.28fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
++ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
++ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
++ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C1 DFlipFlop_1/D Q1 0.03fF
+C2 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
+C3 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C4 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C5 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
+C6 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C7 nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
+C8 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
+C9 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C10 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C11 DFlipFlop_3/nQ Q1_shift 0.04fF
+C12 Q1 DFlipFlop_2/D 0.10fF
+C13 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C14 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C15 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C16 Q1 nQ0 0.06fF
+C17 Q1 Q1_shift 0.36fF
+C18 Q1 DFlipFlop_3/latch_diff_1/D 0.79fF
+C19 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
+C20 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C21 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C22 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C23 vdd DFlipFlop_0/D 0.19fF
+C24 Q0 DFlipFlop_0/D 0.39fF
+C25 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C26 sky130_fd_sc_hs__xor2_1_0/a_355_368# Q0 0.03fF
+C27 vdd DFlipFlop_1/D 0.25fF
+C28 Q1 DFlipFlop_0/Q 0.13fF
+C29 DFlipFlop_1/D Q0 0.07fF
+C30 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C31 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C32 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C33 DFlipFlop_3/nQ CLK 0.01fF
+C34 DFlipFlop_1/D nCLK 0.14fF
+C35 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C36 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C37 DFlipFlop_2/nQ CLK 0.13fF
+C38 vdd CLK_5 0.15fF
+C39 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
+C40 nQ0 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.04fF
+C41 Q1 CLK -0.10fF
+C42 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C43 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C44 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C45 vdd DFlipFlop_2/D 0.07fF
+C46 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
+C47 Q0 DFlipFlop_2/D 0.25fF
+C48 vdd nQ0 0.11fF
+C49 nQ0 Q0 0.33fF
+C50 vdd Q1_shift 0.10fF
+C51 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C52 nCLK DFlipFlop_2/D 0.41fF
+C53 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C54 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
+C55 DFlipFlop_3/latch_diff_1/nD nCLK 0.09fF
+C56 nQ0 nCLK 0.09fF
+C57 nCLK DFlipFlop_3/latch_diff_1/D 0.14fF
+C58 nQ0 nQ2 0.03fF
+C59 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
+C60 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C61 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C62 DFlipFlop_0/Q Q0 0.21fF
+C63 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C64 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
+C65 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C66 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C67 DFlipFlop_0/Q nCLK 0.11fF
+C68 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C69 DFlipFlop_0/Q nQ2 0.09fF
+C70 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C71 nCLK sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.11fF
+C72 Q1 DFlipFlop_3/latch_diff_1/m1_657_280# 0.28fF
+C73 nCLK DFlipFlop_1/latch_diff_1/D 0.08fF
+C74 vdd CLK 0.41fF
+C75 Q0 CLK 0.08fF
+C76 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C77 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
+C78 nQ2 CLK 0.17fF
+C79 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
+C80 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C81 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
+C82 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
+C83 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C84 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C85 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C86 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C87 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
+C88 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C89 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C90 Q1 DFlipFlop_3/nQ 0.10fF
+C91 Q1 DFlipFlop_2/nQ 0.31fF
+C92 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C93 Q1 DFlipFlop_0/latch_diff_0/D 0.15fF
+C94 DFlipFlop_1/D nQ0 0.12fF
+C95 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C96 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C97 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C98 Q1_shift sky130_fd_sc_hs__or2_1_0/a_63_368# -0.27fF
+C99 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C100 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C101 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C102 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C103 DFlipFlop_1/D CLK 0.21fF
+C104 Q1 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C105 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C106 vdd DFlipFlop_3/nQ 0.02fF
+C107 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
+C108 vdd DFlipFlop_2/nQ 0.02fF
+C109 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C110 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C111 DFlipFlop_3/nQ nCLK 0.02fF
+C112 DFlipFlop_2/nQ nCLK 0.09fF
+C113 vdd Q1 9.49fF
+C114 Q1 Q0 9.65fF
+C115 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C116 Q1 nCLK -0.01fF
+C117 DFlipFlop_2/D CLK 0.14fF
+C118 Q1 nQ2 0.07fF
+C119 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C120 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C121 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C122 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C123 nQ0 CLK 0.19fF
+C124 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
+C125 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
+C126 nQ0 DFlipFlop_1/latch_diff_0/D 0.09fF
+C127 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q1 0.20fF
+C128 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C129 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C130 DFlipFlop_0/Q CLK 0.08fF
+C131 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C132 Q1 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C133 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C134 nQ0 DFlipFlop_1/latch_diff_0/m1_657_280# 0.25fF
+C135 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C136 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C137 DFlipFlop_1/latch_diff_0/nD CLK 0.08fF
+C138 vdd Q0 5.33fF
+C139 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C140 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
+C141 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
+C142 vdd nCLK 0.34fF
+C143 nCLK Q0 0.20fF
+C144 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C145 vdd nQ2 0.04fF
+C146 nQ2 Q0 0.23fF
+C147 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
+C148 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C149 nQ2 nCLK 0.10fF
+C150 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C151 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C152 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C153 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C154 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C155 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C156 Q1 DFlipFlop_0/D 0.13fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 DFlipFlop_2/nQ vss 0.50fF
+C172 Q1 vss 8.55fF
+C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 nQ0 vss 3.42fF
+C183 Q0 vss 0.53fF
+C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n225_n125# a_n129_n125# 0.36fF
+C1 a_n33_n125# a_n129_n125# 0.36fF
+C2 a_n63_n151# a_33_n151# 0.02fF
+C3 a_n33_n125# a_n225_n125# 0.13fF
+C4 a_255_n125# a_n129_n125# 0.06fF
+C5 a_63_n125# a_n129_n125# 0.13fF
+C6 a_n159_n151# a_n255_n151# 0.02fF
+C7 a_159_n125# a_n129_n125# 0.08fF
+C8 a_n33_n125# a_255_n125# 0.08fF
+C9 a_n317_n125# a_n129_n125# 0.13fF
+C10 a_n63_n151# a_n159_n151# 0.02fF
+C11 a_n225_n125# a_63_n125# 0.08fF
+C12 a_n33_n125# a_63_n125# 0.36fF
+C13 a_129_n151# a_33_n151# 0.02fF
+C14 a_n225_n125# a_159_n125# 0.06fF
+C15 a_n33_n125# a_159_n125# 0.13fF
+C16 a_n225_n125# a_n317_n125# 0.36fF
+C17 a_n33_n125# a_n317_n125# 0.08fF
+C18 a_255_n125# a_63_n125# 0.13fF
+C19 a_225_n151# a_129_n151# 0.02fF
+C20 a_255_n125# a_159_n125# 0.36fF
+C21 a_159_n125# a_63_n125# 0.36fF
+C22 a_63_n125# a_n317_n125# 0.06fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n33_n125# a_63_n125# 0.36fF
+C1 a_225_n154# a_129_n154# 0.02fF
+C2 a_255_n125# a_n129_n125# 0.06fF
+C3 a_n225_n125# a_n317_n125# 0.36fF
+C4 a_n317_n125# w_n455_n344# 0.11fF
+C5 a_255_n125# a_63_n125# 0.13fF
+C6 a_255_n125# a_n33_n125# 0.08fF
+C7 a_n225_n125# a_n129_n125# 0.36fF
+C8 a_n129_n125# w_n455_n344# 0.04fF
+C9 a_n225_n125# a_63_n125# 0.08fF
+C10 a_63_n125# w_n455_n344# 0.04fF
+C11 a_n225_n125# a_n33_n125# 0.13fF
+C12 a_n33_n125# w_n455_n344# 0.05fF
+C13 a_159_n125# a_n129_n125# 0.08fF
+C14 a_n255_n154# a_n159_n154# 0.02fF
+C15 a_159_n125# a_63_n125# 0.36fF
+C16 a_n33_n125# a_159_n125# 0.13fF
+C17 a_n129_n125# a_n317_n125# 0.13fF
+C18 a_255_n125# w_n455_n344# 0.11fF
+C19 a_n317_n125# a_63_n125# 0.06fF
+C20 a_n33_n125# a_n317_n125# 0.08fF
+C21 a_33_n154# a_129_n154# 0.02fF
+C22 a_255_n125# a_159_n125# 0.36fF
+C23 a_33_n154# a_n63_n154# 0.02fF
+C24 a_n225_n125# w_n455_n344# 0.06fF
+C25 a_n129_n125# a_63_n125# 0.13fF
+C26 a_n33_n125# a_n129_n125# 0.36fF
+C27 a_n63_n154# a_n159_n154# 0.02fF
+C28 a_n225_n125# a_159_n125# 0.06fF
+C29 a_159_n125# w_n455_n344# 0.06fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 vdd in 0.04fF
+C1 in out 0.85fF
+C2 vdd out 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 vdd QA 0.02fF
+C1 vdd nUp 0.14fF
+C2 Down nDown 0.23fF
+C3 vdd Up 0.60fF
+C4 inverter_cp_x1_0/out nDown 0.11fF
+C5 vdd QB 0.02fF
+C6 Up nUp 0.20fF
+C7 inverter_cp_x1_0/out Down 0.12fF
+C8 vdd nDown 0.80fF
+C9 vdd Down 0.09fF
+C10 vdd inverter_cp_x1_0/out 0.25fF
+C11 vdd inverter_cp_x1_2/in 0.42fF
+C12 Up inverter_cp_x1_2/in 0.12fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n221_n90# a_63_n90# 0.06fF
+C1 a_159_n90# a_n221_n90# 0.04fF
+C2 a_n33_n90# a_63_n90# 0.26fF
+C3 a_159_n90# a_n33_n90# 0.09fF
+C4 a_n63_n116# a_n159_n207# 0.12fF
+C5 a_n129_n90# a_63_n90# 0.09fF
+C6 a_159_n90# a_n129_n90# 0.06fF
+C7 w_n359_n309# a_63_n90# 0.06fF
+C8 a_159_n90# w_n359_n309# 0.09fF
+C9 a_n221_n90# a_n33_n90# 0.09fF
+C10 a_n129_n90# a_n221_n90# 0.26fF
+C11 a_n221_n90# w_n359_n309# 0.09fF
+C12 a_159_n90# a_63_n90# 0.26fF
+C13 a_n129_n90# a_n33_n90# 0.26fF
+C14 a_n33_n90# w_n359_n309# 0.05fF
+C15 a_n129_n90# w_n359_n309# 0.06fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_71# a_33_n71# 0.04fF
+C1 a_n33_n45# a_n125_n45# 0.13fF
+C2 a_63_n45# a_n33_n45# 0.13fF
+C3 a_63_n45# a_n125_n45# 0.05fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 B out 0.40fF
+C1 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out 0.08fF
+C2 B A 0.24fF
+C3 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
+C4 A out 0.06fF
+C5 vdd out 0.11fF
+C6 vdd A 0.09fF
+C7 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C1 nor_pfd_2/B vdd 0.02fF
+C2 nor_pfd_3/A vdd 0.09fF
+C3 Q nor_pfd_2/B 2.22fF
+C4 nor_pfd_3/A Q 0.98fF
+C5 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C6 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C7 CLK Q 0.04fF
+C8 nor_pfd_2/B Reset 0.43fF
+C9 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C10 nor_pfd_3/A Reset 0.12fF
+C11 Q vdd 0.08fF
+C12 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C13 vdd nor_pfd_2/A -0.01fF
+C14 Q nor_pfd_2/A 1.38fF
+C15 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C16 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C17 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C18 Q Reset 0.14fF
+C19 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_n45# a_n33_n45# 0.13fF
+C1 a_n221_n45# a_159_n45# 0.02fF
+C2 a_n63_n71# a_n159_n173# 0.10fF
+C3 a_n221_n45# a_63_n45# 0.03fF
+C4 a_n221_n45# a_n129_n45# 0.13fF
+C5 a_63_n45# a_159_n45# 0.13fF
+C6 a_n129_n45# a_159_n45# 0.03fF
+C7 a_n129_n45# a_63_n45# 0.05fF
+C8 a_n221_n45# a_n33_n45# 0.05fF
+C9 a_n33_n45# a_159_n45# 0.05fF
+C10 a_63_n45# a_n33_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n125_n90# a_63_n90# 0.09fF
+C1 a_n99_n187# a_33_n187# 0.04fF
+C2 a_n33_n90# a_n125_n90# 0.26fF
+C3 a_n33_n90# a_63_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n73_n45# a_15_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_15_n90# w_n211_n309# 0.09fF
+C1 a_15_n90# a_n73_n90# 0.31fF
+C2 w_n211_n309# a_n73_n90# 0.04fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C1 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C2 A B 0.33fF
+C3 vdd out 0.10fF
+C4 a_656_410# vdd 0.20fF
+C5 A vdd 0.05fF
+C6 a_656_410# out 0.20fF
+C7 a_656_410# A 0.04fF
+C8 out sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.03fF
+C9 a_656_410# B 0.30fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 vdd Up 1.62fF
+C1 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C2 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
+C3 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C4 vdd Reset 0.02fF
+C5 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C6 Down Up 0.06fF
+C7 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
+C8 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
+C9 Down vdd 0.08fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+
+* Top level circuit top_pll_v2
+
+Xcharge_pump_0 nswitch vdd nUp vss Down biasp vco_vctrl pswitch iref_cp nDown Up charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss ring_osc_0/csvco_branch_0/inverter_csvco_0/vss ring_osc_0/csvco_branch_2/vbp
++ D0_vco ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 div_5_nQ0 n_out_by_2 0.10fF
+C1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C2 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
+C3 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C4 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C5 vdd out_div_by_5 0.28fF
+C6 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C7 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
+C8 vdd iref_cp 0.15fF
+C9 vdd out_to_div 0.21fF
+C10 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C11 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
+C12 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
+C13 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
+C14 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
+C15 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C16 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
+C17 vdd Up 0.28fF
+C18 nUp Up 2.72fF
+C19 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C20 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# n_out_by_2 -0.05fF
+C21 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
+C22 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C23 div_5_nQ0 out_by_2 0.32fF
+C24 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C25 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C26 vco_vctrl nswitch -0.06fF
+C27 nUp pswitch 0.85fF
+C28 div_5_Q1 n_out_by_2 1.04fF
+C29 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C30 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C31 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
+C32 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
+C33 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C34 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C35 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C36 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C37 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
+C38 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C39 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
+C40 biasp Up 0.26fF
+C41 vdd lf_vc 0.02fF
+C42 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
+C43 vdd nDown 0.22fF
+C44 nUp nDown -0.09fF
+C45 div_5_Q1 out_by_2 0.42fF
+C46 vdd D0_vco 0.03fF
+C47 biasp Down 1.24fF
+C48 vdd n_out_by_2 1.03fF
+C49 vdd out_to_buffer 0.07fF
+C50 div_by_5_0/DFlipFlop_3/latch_diff_0/D out_by_2 0.11fF
+C51 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 0.27fF
+C52 div_5_Q1 vco_vctrl 0.14fF
+C53 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_out_by_2 0.12fF
+C54 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
+C55 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C56 Down iref_cp 0.09fF
+C57 vco_vctrl n_out_by_2 0.52fF
+C58 n_out_by_2 div_5_Q0 -0.12fF
+C59 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
+C60 out_div_by_5 div_5_Q1_shift 0.05fF
+C61 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C62 n_out_by_2 div_5_nQ2 0.10fF
+C63 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
+C64 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C65 div_by_5_0/DFlipFlop_2/latch_diff_1/nD n_out_by_2 0.24fF
+C66 Down nswitch 0.54fF
+C67 pswitch Up 1.98fF
+C68 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
+C69 div_by_5_0/DFlipFlop_2/latch_diff_1/D n_out_by_2 0.10fF
+C70 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C71 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C72 biasp nDown 0.26fF
+C73 vdd nUp 0.05fF
+C74 vdd out_by_2 0.97fF
+C75 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
+C76 out_div_by_5 div_5_Q1 0.01fF
+C77 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
+C78 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C79 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C80 vdd QA -0.04fF
+C81 vdd vco_vctrl -1.02fF
+C82 nUp vco_vctrl 0.02fF
+C83 out_by_2 vco_vctrl 0.53fF
+C84 out_by_2 div_5_Q0 0.09fF
+C85 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C86 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C87 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C88 out_by_2 div_5_nQ2 0.16fF
+C89 div_by_5_0/DFlipFlop_0/Q out_by_2 0.09fF
+C90 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C91 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
+C92 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C93 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C94 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
+C95 nswitch nDown 0.76fF
+C96 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C97 out_to_buffer out_to_div 0.13fF
+C98 vdd buffer_salida_0/a_678_n100# 0.24fF
+C99 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
+C100 vco_vctrl div_5_Q0 0.48fF
+C101 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
+C102 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
+C103 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
+C104 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C105 pswitch nDown 0.53fF
+C106 biasp nUp -0.17fF
+C107 Down nDown 2.55fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.46fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss -0.40fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.31fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 5.50fF
+C141 Up vss 2.37fF
+C142 Down vss 7.92fF
+C143 nDown vss -2.20fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C158 div_5_Q1 vss 4.28fF
+C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_nQ0 vss 0.59fF
+C169 div_5_Q0 vss 0.01fF
+C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_to_buffer vss 1.57fF
+C196 out_to_div vss 4.46fF
+C197 out_first_buffer vss 2.88fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 D0_vco vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 n_out_buffer_div_2 vss 1.63fF
+C216 out_buffer_div_2 vss 1.60fF
+C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 lf_vc vss -59.89fF
+C232 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C233 DO_cap vss 0.01fF
+C234 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C235 nswitch vss 3.73fF
+C236 biasp vss 5.44fF
+C237 iref_cp vss 2.81fF
+C238 vco_vctrl vss -21.20fF
+C239 pswitch vss 3.57fF
+.end
+
diff --git a/mag/extractions/top_pll_v2_pex_rc_port.spice b/mag/extractions/top_pll_v2_pex_rc_port.spice
new file mode 100644
index 0000000..7828d11
--- /dev/null
+++ b/mag/extractions/top_pll_v2_pex_rc_port.spice
@@ -0,0 +1,2920 @@
+* NGSPICE file created from top_pll_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_n1861_n486# w_n2457_n634# 0.02fF
+C1 a_887_n486# w_n2457_n634# 0.02fF
+C2 a_429_n486# w_n2457_n634# 0.02fF
+C3 w_n2457_n634# a_n29_n486# 0.02fF
+C4 w_n2457_n634# a_1803_n486# 0.02fF
+C5 w_n2457_n634# a_n1403_n486# 0.02fF
+C6 a_1345_n486# w_n2457_n634# 0.02fF
+C7 a_n945_n486# w_n2457_n634# 0.02fF
+C8 a_n487_n486# w_n2457_n634# 0.02fF
+C9 a_2261_n486# w_n2457_n634# 0.02fF
+C10 a_n2319_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n369_n75# a_n177_n75# 0.08fF
+C1 a_n561_n75# a_n657_n75# 0.22fF
+C2 a_111_n75# a_15_n75# 0.22fF
+C3 a_399_n75# a_783_n75# 0.03fF
+C4 a_n561_n75# a_n177_n75# 0.03fF
+C5 a_495_n75# a_591_n75# 0.22fF
+C6 a_975_n75# a_687_n75# 0.05fF
+C7 a_n753_n75# a_n945_n75# 0.08fF
+C8 a_n1137_n75# a_n1229_n75# 0.22fF
+C9 a_975_n75# a_1071_n75# 0.22fF
+C10 a_495_n75# a_111_n75# 0.03fF
+C11 a_n753_n75# a_n465_n75# 0.05fF
+C12 a_1167_n75# a_1071_n75# 0.22fF
+C13 a_207_n75# a_n81_n75# 0.05fF
+C14 a_111_n75# a_n177_n75# 0.05fF
+C15 a_303_n75# a_n81_n75# 0.03fF
+C16 a_n753_n75# a_n1041_n75# 0.05fF
+C17 a_207_n75# a_15_n75# 0.08fF
+C18 a_303_n75# a_15_n75# 0.05fF
+C19 a_879_n75# a_687_n75# 0.08fF
+C20 a_n849_n75# a_n945_n75# 0.22fF
+C21 a_n81_n75# a_n465_n75# 0.03fF
+C22 a_879_n75# a_1071_n75# 0.08fF
+C23 a_n273_n75# a_n81_n75# 0.08fF
+C24 a_495_n75# a_687_n75# 0.08fF
+C25 a_495_n75# a_207_n75# 0.05fF
+C26 a_495_n75# a_303_n75# 0.08fF
+C27 a_399_n75# a_15_n75# 0.03fF
+C28 a_n849_n75# a_n465_n75# 0.03fF
+C29 a_975_n75# a_783_n75# 0.08fF
+C30 a_n273_n75# a_15_n75# 0.05fF
+C31 a_591_n75# a_687_n75# 0.22fF
+C32 a_207_n75# a_n177_n75# 0.03fF
+C33 a_n849_n75# a_n1041_n75# 0.08fF
+C34 a_207_n75# a_591_n75# 0.03fF
+C35 a_591_n75# a_303_n75# 0.05fF
+C36 a_1167_n75# a_783_n75# 0.03fF
+C37 a_n369_n75# a_n465_n75# 0.22fF
+C38 a_n561_n75# a_n945_n75# 0.03fF
+C39 a_n657_n75# a_n945_n75# 0.05fF
+C40 a_n1137_n75# a_n945_n75# 0.08fF
+C41 a_n273_n75# a_n369_n75# 0.22fF
+C42 a_n561_n75# a_n465_n75# 0.22fF
+C43 a_495_n75# a_399_n75# 0.22fF
+C44 a_n657_n75# a_n465_n75# 0.08fF
+C45 a_n273_n75# a_n561_n75# 0.05fF
+C46 a_n273_n75# a_n657_n75# 0.03fF
+C47 a_n1229_n75# a_n945_n75# 0.05fF
+C48 a_207_n75# a_111_n75# 0.22fF
+C49 a_303_n75# a_111_n75# 0.08fF
+C50 a_n177_n75# a_n465_n75# 0.05fF
+C51 a_n1041_n75# a_n657_n75# 0.03fF
+C52 a_n1137_n75# a_n1041_n75# 0.22fF
+C53 a_591_n75# a_399_n75# 0.08fF
+C54 a_n273_n75# a_n177_n75# 0.22fF
+C55 a_975_n75# a_1167_n75# 0.08fF
+C56 a_879_n75# a_783_n75# 0.22fF
+C57 a_n1229_n75# a_n1041_n75# 0.08fF
+C58 a_111_n75# a_399_n75# 0.05fF
+C59 a_n273_n75# a_111_n75# 0.03fF
+C60 a_495_n75# a_783_n75# 0.05fF
+C61 a_n849_n75# a_n753_n75# 0.22fF
+C62 a_303_n75# a_687_n75# 0.03fF
+C63 a_591_n75# a_783_n75# 0.08fF
+C64 a_207_n75# a_303_n75# 0.22fF
+C65 a_975_n75# a_879_n75# 0.22fF
+C66 a_n753_n75# a_n369_n75# 0.03fF
+C67 a_687_n75# a_1071_n75# 0.03fF
+C68 a_879_n75# a_1167_n75# 0.05fF
+C69 a_n753_n75# a_n561_n75# 0.08fF
+C70 a_n753_n75# a_n657_n75# 0.22fF
+C71 a_n1137_n75# a_n753_n75# 0.03fF
+C72 a_15_n75# a_n81_n75# 0.22fF
+C73 a_687_n75# a_399_n75# 0.05fF
+C74 a_207_n75# a_399_n75# 0.08fF
+C75 a_303_n75# a_399_n75# 0.22fF
+C76 a_975_n75# a_591_n75# 0.03fF
+C77 a_n369_n75# a_n81_n75# 0.05fF
+C78 a_n369_n75# a_15_n75# 0.03fF
+C79 a_n1041_n75# a_n945_n75# 0.22fF
+C80 a_n273_n75# a_n465_n75# 0.08fF
+C81 a_n81_n75# a_n177_n75# 0.22fF
+C82 a_n849_n75# a_n561_n75# 0.05fF
+C83 a_n849_n75# a_n657_n75# 0.08fF
+C84 a_687_n75# a_783_n75# 0.22fF
+C85 a_n1137_n75# a_n849_n75# 0.05fF
+C86 a_879_n75# a_495_n75# 0.03fF
+C87 a_15_n75# a_n177_n75# 0.08fF
+C88 a_n369_n75# a_n561_n75# 0.08fF
+C89 a_n369_n75# a_n657_n75# 0.05fF
+C90 a_879_n75# a_591_n75# 0.05fF
+C91 a_783_n75# a_1071_n75# 0.05fF
+C92 a_n849_n75# a_n1229_n75# 0.03fF
+C93 a_111_n75# a_n81_n75# 0.08fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_639_n75# a_543_n75# 0.22fF
+C1 a_927_n75# a_639_n75# 0.05fF
+C2 a_927_n75# a_543_n75# 0.03fF
+C3 a_n225_n75# a_n321_n75# 0.22fF
+C4 a_n609_n75# a_n513_n75# 0.22fF
+C5 a_n897_n75# a_n801_n75# 0.22fF
+C6 a_n609_n75# a_n225_n75# 0.03fF
+C7 a_n705_n75# a_n801_n75# 0.22fF
+C8 a_n129_n75# a_n417_n75# 0.05fF
+C9 a_n225_n75# a_n513_n75# 0.05fF
+C10 a_n33_n75# a_n417_n75# 0.03fF
+C11 a_n129_n75# a_n321_n75# 0.08fF
+C12 a_n33_n75# a_n321_n75# 0.05fF
+C13 a_n801_n75# a_n417_n75# 0.03fF
+C14 a_447_n75# a_351_n75# 0.22fF
+C15 a_n989_n75# a_n801_n75# 0.08fF
+C16 a_63_n75# a_n321_n75# 0.03fF
+C17 a_447_n75# a_735_n75# 0.05fF
+C18 a_447_n75# a_63_n75# 0.03fF
+C19 a_159_n75# a_447_n75# 0.05fF
+C20 a_n129_n75# a_n513_n75# 0.03fF
+C21 a_447_n75# a_255_n75# 0.08fF
+C22 a_n609_n75# a_n801_n75# 0.08fF
+C23 a_831_n75# a_735_n75# 0.22fF
+C24 a_639_n75# a_351_n75# 0.05fF
+C25 a_543_n75# a_351_n75# 0.08fF
+C26 a_n801_n75# a_n513_n75# 0.05fF
+C27 a_639_n75# a_735_n75# 0.22fF
+C28 a_543_n75# a_735_n75# 0.08fF
+C29 a_927_n75# a_735_n75# 0.08fF
+C30 a_159_n75# a_543_n75# 0.03fF
+C31 a_n129_n75# a_n225_n75# 0.22fF
+C32 a_n33_n75# a_n225_n75# 0.08fF
+C33 a_639_n75# a_255_n75# 0.03fF
+C34 a_255_n75# a_543_n75# 0.05fF
+C35 a_n897_n75# a_n705_n75# 0.08fF
+C36 a_n225_n75# a_63_n75# 0.05fF
+C37 a_159_n75# a_n225_n75# 0.03fF
+C38 a_n705_n75# a_n417_n75# 0.05fF
+C39 a_n129_n75# a_n33_n75# 0.22fF
+C40 a_n897_n75# a_n989_n75# 0.22fF
+C41 a_n705_n75# a_n321_n75# 0.03fF
+C42 a_n33_n75# a_351_n75# 0.03fF
+C43 a_n989_n75# a_n705_n75# 0.05fF
+C44 a_n897_n75# a_n609_n75# 0.05fF
+C45 a_n321_n75# a_n417_n75# 0.22fF
+C46 a_n129_n75# a_63_n75# 0.08fF
+C47 a_n33_n75# a_63_n75# 0.22fF
+C48 a_n897_n75# a_n513_n75# 0.03fF
+C49 a_159_n75# a_n129_n75# 0.05fF
+C50 a_159_n75# a_n33_n75# 0.08fF
+C51 a_n609_n75# a_n705_n75# 0.22fF
+C52 a_n129_n75# a_255_n75# 0.03fF
+C53 a_n33_n75# a_255_n75# 0.05fF
+C54 a_351_n75# a_735_n75# 0.03fF
+C55 a_n705_n75# a_n513_n75# 0.08fF
+C56 a_63_n75# a_351_n75# 0.05fF
+C57 a_159_n75# a_351_n75# 0.08fF
+C58 a_n609_n75# a_n417_n75# 0.08fF
+C59 a_255_n75# a_351_n75# 0.22fF
+C60 a_447_n75# a_831_n75# 0.03fF
+C61 a_n609_n75# a_n321_n75# 0.05fF
+C62 a_n417_n75# a_n513_n75# 0.22fF
+C63 a_159_n75# a_63_n75# 0.22fF
+C64 a_447_n75# a_639_n75# 0.08fF
+C65 a_447_n75# a_543_n75# 0.22fF
+C66 a_63_n75# a_255_n75# 0.08fF
+C67 a_n927_n101# a_33_n101# 0.08fF
+C68 a_159_n75# a_255_n75# 0.22fF
+C69 a_n989_n75# a_n609_n75# 0.03fF
+C70 a_n321_n75# a_n513_n75# 0.08fF
+C71 a_831_n75# a_639_n75# 0.08fF
+C72 a_831_n75# a_543_n75# 0.05fF
+C73 a_927_n75# a_831_n75# 0.22fF
+C74 a_n225_n75# a_n417_n75# 0.08fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_543_n150# a_639_n150# 0.43fF
+C1 a_n705_n150# a_n609_n150# 0.43fF
+C2 a_543_n150# a_927_n150# 0.07fF
+C3 a_927_n150# a_639_n150# 0.10fF
+C4 a_n989_n150# a_n801_n150# 0.16fF
+C5 a_255_n150# a_351_n150# 0.43fF
+C6 a_255_n150# a_n33_n150# 0.10fF
+C7 a_n989_n150# a_n609_n150# 0.07fF
+C8 a_447_n150# a_351_n150# 0.43fF
+C9 a_n705_n150# a_n897_n150# 0.16fF
+C10 a_255_n150# a_n129_n150# 0.07fF
+C11 a_n609_n150# a_n801_n150# 0.16fF
+C12 a_n513_n150# a_n705_n150# 0.16fF
+C13 a_n705_n150# a_n417_n150# 0.10fF
+C14 a_351_n150# a_735_n150# 0.07fF
+C15 a_351_n150# a_63_n150# 0.10fF
+C16 a_n33_n150# a_63_n150# 0.43fF
+C17 a_159_n150# a_351_n150# 0.16fF
+C18 a_159_n150# a_n33_n150# 0.16fF
+C19 a_n989_n150# a_n897_n150# 0.43fF
+C20 a_n321_n150# a_63_n150# 0.07fF
+C21 a_n705_n150# a_n321_n150# 0.07fF
+C22 a_n225_n150# a_63_n150# 0.10fF
+C23 a_n129_n150# a_63_n150# 0.16fF
+C24 a_159_n150# a_n225_n150# 0.07fF
+C25 a_n801_n150# a_n897_n150# 0.43fF
+C26 a_543_n150# a_351_n150# 0.16fF
+C27 a_447_n150# a_831_n150# 0.07fF
+C28 a_33_n247# a_n927_n247# 0.09fF
+C29 a_159_n150# a_n129_n150# 0.10fF
+C30 a_n513_n150# a_n801_n150# 0.10fF
+C31 a_n417_n150# a_n801_n150# 0.07fF
+C32 a_351_n150# a_639_n150# 0.10fF
+C33 a_n609_n150# a_n897_n150# 0.10fF
+C34 a_831_n150# a_735_n150# 0.43fF
+C35 a_n513_n150# a_n609_n150# 0.43fF
+C36 a_n417_n150# a_n609_n150# 0.16fF
+C37 a_255_n150# a_447_n150# 0.16fF
+C38 a_n609_n150# a_n321_n150# 0.10fF
+C39 a_n225_n150# a_n609_n150# 0.07fF
+C40 a_543_n150# a_831_n150# 0.10fF
+C41 a_n513_n150# a_n897_n150# 0.07fF
+C42 a_255_n150# a_63_n150# 0.16fF
+C43 a_831_n150# a_639_n150# 0.16fF
+C44 a_447_n150# a_735_n150# 0.10fF
+C45 a_927_n150# a_831_n150# 0.43fF
+C46 a_n513_n150# a_n417_n150# 0.43fF
+C47 a_255_n150# a_159_n150# 0.43fF
+C48 a_447_n150# a_63_n150# 0.07fF
+C49 a_n417_n150# a_n33_n150# 0.07fF
+C50 a_159_n150# a_447_n150# 0.10fF
+C51 a_255_n150# a_543_n150# 0.10fF
+C52 a_351_n150# a_n33_n150# 0.07fF
+C53 a_n513_n150# a_n321_n150# 0.16fF
+C54 a_n417_n150# a_n321_n150# 0.43fF
+C55 a_255_n150# a_639_n150# 0.07fF
+C56 a_n225_n150# a_n513_n150# 0.10fF
+C57 a_n225_n150# a_n417_n150# 0.16fF
+C58 a_543_n150# a_447_n150# 0.43fF
+C59 a_n513_n150# a_n129_n150# 0.07fF
+C60 a_n417_n150# a_n129_n150# 0.10fF
+C61 a_159_n150# a_63_n150# 0.43fF
+C62 a_447_n150# a_639_n150# 0.16fF
+C63 a_n321_n150# a_n33_n150# 0.10fF
+C64 a_n225_n150# a_n33_n150# 0.16fF
+C65 a_543_n150# a_735_n150# 0.16fF
+C66 a_n129_n150# a_n33_n150# 0.43fF
+C67 a_735_n150# a_639_n150# 0.43fF
+C68 a_n225_n150# a_n321_n150# 0.43fF
+C69 a_927_n150# a_735_n150# 0.16fF
+C70 a_n321_n150# a_n129_n150# 0.16fF
+C71 a_n989_n150# a_n705_n150# 0.10fF
+C72 a_n225_n150# a_n129_n150# 0.43fF
+C73 a_159_n150# a_543_n150# 0.07fF
+C74 a_n705_n150# a_n801_n150# 0.43fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_1403_n44# a_1761_n44# 0.04fF
+C1 a_n745_n44# a_n387_n44# 0.04fF
+C2 a_n1103_n44# a_n1461_n44# 0.04fF
+C3 a_n745_n44# a_n1103_n44# 0.04fF
+C4 a_n387_n44# a_n29_n44# 0.04fF
+C5 a_329_n44# a_n29_n44# 0.04fF
+C6 a_1045_n44# a_1403_n44# 0.04fF
+C7 a_n1461_n44# a_n1819_n44# 0.04fF
+C8 a_687_n44# a_329_n44# 0.04fF
+C9 a_687_n44# a_1045_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_879_n150# a_591_n150# 0.10fF
+C1 a_879_n150# a_495_n150# 0.07fF
+C2 a_591_n150# a_495_n150# 0.43fF
+C3 a_111_n150# a_n81_n150# 0.16fF
+C4 a_n945_n150# a_n561_n150# 0.07fF
+C5 a_879_n150# a_687_n150# 0.16fF
+C6 a_n753_n150# a_n465_n150# 0.10fF
+C7 a_n369_n150# a_n273_n150# 0.43fF
+C8 a_591_n150# a_687_n150# 0.43fF
+C9 a_495_n150# a_687_n150# 0.16fF
+C10 a_207_n150# a_591_n150# 0.07fF
+C11 a_207_n150# a_495_n150# 0.10fF
+C12 a_n945_n150# a_n849_n150# 0.43fF
+C13 a_n657_n150# a_n465_n150# 0.16fF
+C14 a_n945_n150# a_n1229_n150# 0.10fF
+C15 a_n657_n150# a_n273_n150# 0.07fF
+C16 w_n1367_n369# a_975_n150# 0.05fF
+C17 a_783_n150# a_399_n150# 0.07fF
+C18 a_303_n150# a_15_n150# 0.10fF
+C19 a_879_n150# a_1071_n150# 0.16fF
+C20 a_n177_n150# a_15_n150# 0.16fF
+C21 a_n369_n150# a_n561_n150# 0.16fF
+C22 a_1071_n150# a_687_n150# 0.07fF
+C23 a_n849_n150# a_n1137_n150# 0.10fF
+C24 a_n273_n150# a_n465_n150# 0.16fF
+C25 a_n177_n150# a_n369_n150# 0.16fF
+C26 a_399_n150# a_15_n150# 0.07fF
+C27 w_n1367_n369# a_1167_n150# 0.14fF
+C28 a_n1041_n150# a_n849_n150# 0.16fF
+C29 a_n753_n150# a_n561_n150# 0.16fF
+C30 a_n1229_n150# a_n1137_n150# 0.43fF
+C31 a_15_n150# a_n81_n150# 0.43fF
+C32 a_n849_n150# a_n753_n150# 0.43fF
+C33 a_n1041_n150# a_n1229_n150# 0.16fF
+C34 a_n657_n150# a_n561_n150# 0.43fF
+C35 a_591_n150# a_303_n150# 0.10fF
+C36 a_303_n150# a_495_n150# 0.16fF
+C37 a_n369_n150# a_n81_n150# 0.10fF
+C38 a_n657_n150# a_n849_n150# 0.16fF
+C39 a_303_n150# a_687_n150# 0.07fF
+C40 a_207_n150# a_303_n150# 0.43fF
+C41 a_n177_n150# a_207_n150# 0.07fF
+C42 a_n465_n150# a_n561_n150# 0.43fF
+C43 a_591_n150# a_399_n150# 0.16fF
+C44 a_495_n150# a_399_n150# 0.43fF
+C45 a_n177_n150# a_n465_n150# 0.10fF
+C46 a_n849_n150# a_n465_n150# 0.07fF
+C47 a_399_n150# a_687_n150# 0.10fF
+C48 a_207_n150# a_399_n150# 0.16fF
+C49 a_n273_n150# a_n561_n150# 0.10fF
+C50 a_111_n150# a_15_n150# 0.43fF
+C51 a_879_n150# w_n1367_n369# 0.04fF
+C52 a_n177_n150# a_n273_n150# 0.43fF
+C53 a_207_n150# a_n81_n150# 0.10fF
+C54 a_975_n150# a_1167_n150# 0.16fF
+C55 a_975_n150# a_783_n150# 0.16fF
+C56 a_n465_n150# a_n81_n150# 0.07fF
+C57 a_783_n150# a_1167_n150# 0.07fF
+C58 a_n273_n150# a_n81_n150# 0.16fF
+C59 a_111_n150# a_495_n150# 0.07fF
+C60 a_n849_n150# a_n561_n150# 0.10fF
+C61 w_n1367_n369# a_1071_n150# 0.07fF
+C62 a_n177_n150# a_n561_n150# 0.07fF
+C63 a_n945_n150# a_n1137_n150# 0.16fF
+C64 a_207_n150# a_111_n150# 0.43fF
+C65 a_n945_n150# a_n1041_n150# 0.43fF
+C66 a_303_n150# a_399_n150# 0.43fF
+C67 a_n945_n150# a_n753_n150# 0.16fF
+C68 a_879_n150# a_975_n150# 0.43fF
+C69 a_n849_n150# a_n1229_n150# 0.07fF
+C70 a_975_n150# a_591_n150# 0.07fF
+C71 a_n273_n150# a_111_n150# 0.07fF
+C72 a_975_n150# a_687_n150# 0.10fF
+C73 a_303_n150# a_n81_n150# 0.07fF
+C74 a_n369_n150# a_15_n150# 0.07fF
+C75 a_n945_n150# a_n657_n150# 0.10fF
+C76 a_n177_n150# a_n81_n150# 0.43fF
+C77 a_879_n150# a_1167_n150# 0.10fF
+C78 a_879_n150# a_783_n150# 0.43fF
+C79 a_783_n150# a_591_n150# 0.16fF
+C80 a_783_n150# a_495_n150# 0.10fF
+C81 a_n1041_n150# a_n1137_n150# 0.43fF
+C82 a_783_n150# a_687_n150# 0.43fF
+C83 a_n753_n150# a_n1137_n150# 0.07fF
+C84 a_n369_n150# a_n753_n150# 0.07fF
+C85 a_1071_n150# a_975_n150# 0.43fF
+C86 a_n1041_n150# a_n753_n150# 0.10fF
+C87 a_207_n150# a_15_n150# 0.16fF
+C88 a_303_n150# a_111_n150# 0.16fF
+C89 a_n657_n150# a_n369_n150# 0.10fF
+C90 a_n177_n150# a_111_n150# 0.10fF
+C91 a_n657_n150# a_n1041_n150# 0.07fF
+C92 a_1071_n150# a_1167_n150# 0.43fF
+C93 a_1071_n150# a_783_n150# 0.10fF
+C94 a_n657_n150# a_n753_n150# 0.43fF
+C95 a_111_n150# a_399_n150# 0.10fF
+C96 a_n369_n150# a_n465_n150# 0.43fF
+C97 a_n273_n150# a_15_n150# 0.10fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vdd nUp vss Down biasp out pswitch iref nDown Up
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 nUp out 0.31fF
+C1 out nswitch 1.28fF
+C2 out vdd 6.66fF
+C3 nUp Down 0.25fF
+C4 pswitch out 4.91fF
+C5 nswitch Down 2.27fF
+C6 iref biasp 0.80fF
+C7 nswitch iref 1.91fF
+C8 nDown Down 0.13fF
+C9 nUp Up 0.15fF
+C10 nswitch biasp 0.03fF
+C11 vdd biasp 2.64fF
+C12 vdd nswitch 0.07fF
+C13 pswitch nUp 5.66fF
+C14 pswitch biasp 3.11fF
+C15 pswitch Up 0.70fF
+C16 pswitch nswitch 0.06fF
+C17 pswitch vdd 3.98fF
+C18 nDown nswitch 0.31fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C1 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C2 m3_2669_n2600# m3_n2650_n2600# 2.73fF
+C3 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C4 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C5 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C6 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C7 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C8 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C9 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C10 m3_7988_n13200# m3_7988_n7900# 3.39fF
+C11 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C12 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C13 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C14 m3_n2650_2700# m3_2669_2700# 2.73fF
+C15 m3_2669_n2600# m3_2669_2700# 3.28fF
+C16 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C17 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C18 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C19 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C20 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C21 m3_n2650_8000# m3_2669_8000# 2.73fF
+C22 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C23 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C24 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C25 m3_7988_2700# m3_7988_8000# 3.39fF
+C26 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C27 m3_7988_n2600# m3_7988_n7900# 3.39fF
+C28 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C29 m3_7988_n2600# m3_7988_2700# 3.39fF
+C30 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C31 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C32 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C33 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C34 m3_7988_2700# m3_2669_2700# 2.73fF
+C35 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C36 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C37 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C38 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C39 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C40 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C41 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C42 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C43 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C44 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C45 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C46 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C47 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C48 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C49 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C50 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C51 m3_n7969_2700# m3_n7969_n2600# 3.28fF
+C52 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C53 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C54 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C55 m3_n7969_2700# c1_n13188_n13100# 58.86fF
+C56 m3_7988_8000# m3_2669_8000# 2.73fF
+C57 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C58 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C59 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C60 m3_n7969_2700# m3_n7969_8000# 3.28fF
+C61 m3_2669_8000# m3_2669_2700# 3.28fF
+C62 m3_2669_n13200# m3_n2650_n13200# 2.73fF
+C63 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C64 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n4309_50# m3_10_n4250# 1.75fF
+C1 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
+C2 m3_10_n4250# c1_110_n4150# 81.11fF
+C3 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C4 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C5 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C6 m3_n4309_n4250# m3_10_n4250# 1.75fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 out in 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C1 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C2 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
+C3 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C4 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C5 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C6 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C7 m3_n2150_2200# m3_n2150_n2100# 2.63fF
+C8 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C9 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
+C10 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C11 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C12 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C13 c1_2269_n6300# c1_n2050_n6300# 1.99fF
+C14 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C15 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C16 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C17 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C18 c1_2269_n6300# m3_2169_n6400# 121.67fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 out in 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_30_n300# a_n88_n300# 0.61fF
+C1 a_n118_n388# a_n88_n300# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 in D0_cap 0.07fF
+C2 in cap3_loop_filter_0/in 0.79fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_111_n125# 0.36fF
+C1 a_n173_n125# a_111_n125# 0.08fF
+C2 a_111_n125# w_n311_n344# 0.14fF
+C3 a_n15_n156# a_n111_n156# 0.02fF
+C4 a_n15_n156# a_81_n156# 0.02fF
+C5 a_n81_n125# a_111_n125# 0.13fF
+C6 a_n173_n125# a_15_n125# 0.13fF
+C7 a_15_n125# w_n311_n344# 0.09fF
+C8 a_n173_n125# w_n311_n344# 0.14fF
+C9 a_n81_n125# a_15_n125# 0.36fF
+C10 a_n81_n125# a_n173_n125# 0.36fF
+C11 a_n81_n125# w_n311_n344# 0.09fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_111_n125# a_n81_n125# 0.13fF
+C2 a_n173_n125# a_15_n125# 0.13fF
+C3 a_15_n125# a_n81_n125# 0.36fF
+C4 a_15_n125# a_111_n125# 0.36fF
+C5 a_n15_n151# a_81_n151# 0.02fF
+C6 a_n173_n125# a_n81_n125# 0.36fF
+C7 a_n15_n151# a_n111_n151# 0.02fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 vdd m1_187_n605# 0.55fF
+C1 m1_45_n513# m1_187_n605# 0.36fF
+C2 m1_45_n513# vdd 0.69fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n311_n344# a_n173_n125# 0.14fF
+C1 a_111_n125# a_n173_n125# 0.08fF
+C2 w_n311_n344# a_n81_n125# 0.09fF
+C3 a_15_n125# a_n173_n125# 0.13fF
+C4 a_111_n125# a_n81_n125# 0.13fF
+C5 a_n81_n125# a_15_n125# 0.36fF
+C6 a_n81_n125# a_n173_n125# 0.36fF
+C7 w_n311_n344# a_111_n125# 0.14fF
+C8 w_n311_n344# a_15_n125# 0.09fF
+C9 a_111_n125# a_15_n125# 0.36fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_n173_n125# 0.36fF
+C1 a_111_n125# a_n81_n125# 0.13fF
+C2 a_15_n125# a_n173_n125# 0.13fF
+C3 a_15_n125# a_111_n125# 0.36fF
+C4 a_15_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_n173_n125# 0.08fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 out in 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd inverter_cp_x1_2/in 0.21fF
+C1 vdd inverter_cp_x1_0/out 0.28fF
+C2 CLK_d inverter_cp_x1_2/in 0.12fF
+C3 CLK_d vdd 0.03fF
+C4 inverter_cp_x1_2/in CLK 0.31fF
+C5 inverter_cp_x1_0/out CLK 0.31fF
+C6 inverter_cp_x1_0/out nCLK_d 0.11fF
+C7 vdd CLK 0.36fF
+C8 vdd nCLK_d 0.03fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_63_n95# a_n33_n95# 0.28fF
+C1 w_n263_n314# a_63_n95# 0.11fF
+C2 a_n125_n95# a_63_n95# 0.10fF
+C3 w_n263_n314# a_n33_n95# 0.08fF
+C4 a_n125_n95# a_n33_n95# 0.28fF
+C5 a_n125_n95# w_n263_n314# 0.11fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_15_n125# 0.36fF
+C1 a_n129_n213# a_111_n125# 0.01fF
+C2 a_n173_n125# a_111_n125# 0.08fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_n129_n213# a_15_n125# 0.10fF
+C5 a_n173_n125# a_15_n125# 0.13fF
+C6 a_n173_n125# a_n129_n213# 0.02fF
+C7 a_n81_n125# a_15_n125# 0.36fF
+C8 a_n81_n125# a_n129_n213# 0.10fF
+C9 a_n81_n125# a_n173_n125# 0.36fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n81_n183# 0.16fF
+C1 a_n33_n95# a_n81_n183# 0.10fF
+C2 a_n33_n95# a_n125_n95# 0.88fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 nD nQ 0.05fF
+C1 vdd nQ 0.16fF
+C2 nD Q 0.05fF
+C3 D nQ 0.05fF
+C4 m1_657_280# nQ 1.41fF
+C5 vdd Q 0.16fF
+C6 m1_657_280# CLK 0.24fF
+C7 D Q 0.05fF
+C8 m1_657_280# Q 0.94fF
+C9 Q nQ 0.93fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
++ nCLK latch_diff_0/nD
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 vdd latch_diff_1/D 0.03fF
+C1 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C2 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C3 latch_diff_0/D latch_diff_0/m1_657_280# 0.37fF
+C4 latch_diff_1/D latch_diff_0/D 0.11fF
+C5 latch_diff_1/D nQ 0.11fF
+C6 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
+C7 Q latch_diff_1/nD 0.01fF
+C8 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C9 latch_diff_1/D latch_diff_1/nD 0.33fF
+C10 latch_diff_0/nD latch_diff_1/D 0.41fF
+C11 vdd latch_diff_0/D 0.09fF
+C12 vdd latch_diff_1/nD 0.02fF
+C13 latch_diff_0/nD vdd 0.14fF
+C14 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C15 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C16 latch_diff_1/nD latch_diff_0/D 0.04fF
+C17 latch_diff_1/nD nQ 0.08fF
+C18 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n33_n84# w_n359_n303# 0.05fF
+C1 a_159_n84# a_n221_n84# 0.04fF
+C2 a_n221_n84# a_n129_n84# 0.24fF
+C3 a_n221_n84# a_63_n84# 0.05fF
+C4 a_n221_n84# w_n359_n303# 0.08fF
+C5 a_159_n84# a_n129_n84# 0.05fF
+C6 a_159_n84# a_63_n84# 0.24fF
+C7 a_33_n110# a_129_n110# 0.02fF
+C8 a_63_n84# a_n129_n84# 0.09fF
+C9 a_159_n84# w_n359_n303# 0.08fF
+C10 a_n33_n84# a_n221_n84# 0.09fF
+C11 a_33_n110# a_n63_n110# 0.02fF
+C12 w_n359_n303# a_n129_n84# 0.06fF
+C13 a_63_n84# w_n359_n303# 0.06fF
+C14 a_n33_n84# a_159_n84# 0.09fF
+C15 a_n159_n110# a_n63_n110# 0.02fF
+C16 a_n33_n84# a_n129_n84# 0.24fF
+C17 a_n33_n84# a_63_n84# 0.24fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n42# a_n221_n42# 0.05fF
+C1 a_n33_n42# a_63_n42# 0.12fF
+C2 a_n33_n42# a_159_n42# 0.05fF
+C3 a_n33_n42# a_n129_n42# 0.12fF
+C4 a_n63_n68# a_n159_n68# 0.02fF
+C5 a_n221_n42# a_63_n42# 0.03fF
+C6 a_n221_n42# a_159_n42# 0.02fF
+C7 a_n221_n42# a_n129_n42# 0.12fF
+C8 a_n63_n68# a_33_n68# 0.02fF
+C9 a_63_n42# a_159_n42# 0.12fF
+C10 a_63_n42# a_n129_n42# 0.05fF
+C11 a_159_n42# a_n129_n42# 0.03fF
+C12 a_33_n68# a_129_n68# 0.02fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 vdd out 0.62fF
+C1 in vdd 0.33fF
+C2 in out 0.67fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_n125_n42# a_n33_n42# 0.12fF
+C2 a_63_n42# a_n33_n42# 0.12fF
+C3 a_63_n42# a_n125_n42# 0.05fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_33_n110# a_n63_n110# 0.02fF
+C1 w_n263_n303# a_n125_n84# 0.10fF
+C2 a_63_n84# a_n125_n84# 0.09fF
+C3 a_n33_n84# a_n125_n84# 0.24fF
+C4 w_n263_n303# a_63_n84# 0.10fF
+C5 a_n33_n84# w_n263_n303# 0.07fF
+C6 a_n33_n84# a_63_n84# 0.24fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 vdd out 0.15fF
+C1 in vdd 0.01fF
+C2 in out 0.30fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C1 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C2 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C3 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/nD 0.12fF
+C4 vdd out_div 0.03fF
+C5 vdd nout_div 0.16fF
+C6 DFlipFlop_0/nCLK nout_div 0.43fF
+C7 vdd DFlipFlop_0/CLK 0.40fF
+C8 nCLK_2 o2 0.11fF
+C9 out_div o1 0.01fF
+C10 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C11 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C12 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C13 vdd DFlipFlop_0/nCLK 0.30fF
+C14 vdd CLK_2 0.08fF
+C15 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
+C16 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C17 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C18 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C19 vdd o1 0.14fF
+C20 o1 CLK_2 0.11fF
+C21 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C22 DFlipFlop_0/latch_diff_0/D nout_div 0.09fF
+C23 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C24 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
+C25 vdd nCLK_2 0.08fF
+C26 DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.29fF
+C27 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
+C28 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C29 out_div nout_div 0.22fF
+C30 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C31 DFlipFlop_0/CLK nout_div 0.42fF
+C32 vdd o2 0.14fF
+C33 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C34 DFlipFlop_0/latch_diff_0/D DFlipFlop_0/nCLK 0.13fF
+C35 nCLK_2 vss 1.08fF
+C36 o2 vss 2.21fF
+C37 CLK_2 vss 1.08fF
+C38 o1 vss 2.21fF
+C39 DFlipFlop_0/CLK vss 1.03fF
+C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C42 CLK vss 3.27fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n221_n600# a_n129_n600# 7.87fF
+C1 a_n221_n600# a_n257_n777# 0.25fF
+C2 a_n129_n600# a_n257_n777# 0.29fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n257_n404# a_n129_n300# 0.30fF
+C1 a_n129_n300# a_n221_n300# 4.05fF
+C2 a_n257_n404# a_n221_n300# 0.21fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 a_678_n100# vdd 0.08fF
+C1 a_678_n100# in 0.81fF
+C2 a_3996_n100# a_678_n100# 6.52fF
+C3 out vdd 47.17fF
+C4 in vdd 0.02fF
+C5 a_3996_n100# out 55.19fF
+C6 a_3996_n100# vdd 3.68fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n33_n238# 0.02fF
+C1 a_n33_n238# a_n73_n150# 0.02fF
+C2 a_15_n150# a_n73_n150# 0.51fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n369# a_15_n150# 0.20fF
+C1 a_n73_n150# w_n211_n369# 0.20fF
+C2 w_n211_n369# a_n33_181# 0.05fF
+C3 a_n73_n150# a_15_n150# 0.51fF
+C4 a_n33_181# a_15_n150# 0.01fF
+C5 a_n73_n150# a_n33_181# 0.01fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n225_n150# a_n321_n150# 0.43fF
+C1 a_63_n150# a_159_n150# 0.43fF
+C2 a_n465_172# a_n321_n150# 0.10fF
+C3 a_447_n150# a_351_n150# 0.43fF
+C4 a_n225_n150# a_n129_n150# 0.43fF
+C5 a_n417_n150# a_n225_n150# 0.16fF
+C6 a_159_n150# a_351_n150# 0.16fF
+C7 a_n465_172# a_n129_n150# 0.10fF
+C8 a_n417_n150# a_n465_172# 0.10fF
+C9 a_255_n150# a_63_n150# 0.16fF
+C10 a_n225_n150# a_n509_n150# 0.10fF
+C11 a_n465_172# a_n509_n150# 0.01fF
+C12 a_255_n150# a_351_n150# 0.43fF
+C13 a_447_n150# a_n465_172# 0.01fF
+C14 a_n225_n150# a_159_n150# 0.07fF
+C15 a_n33_n150# a_63_n150# 0.43fF
+C16 a_n465_172# a_159_n150# 0.10fF
+C17 a_n321_n150# a_n129_n150# 0.16fF
+C18 a_n417_n150# a_n321_n150# 0.43fF
+C19 a_n33_n150# a_351_n150# 0.07fF
+C20 a_n417_n150# a_n129_n150# 0.10fF
+C21 a_255_n150# a_n465_172# 0.10fF
+C22 a_n509_n150# a_n321_n150# 0.16fF
+C23 a_n509_n150# a_n129_n150# 0.07fF
+C24 a_n417_n150# a_n509_n150# 0.43fF
+C25 a_n33_n150# a_n225_n150# 0.16fF
+C26 a_n33_n150# a_n465_172# 0.10fF
+C27 a_159_n150# a_n129_n150# 0.10fF
+C28 a_255_n150# a_n129_n150# 0.07fF
+C29 a_447_n150# a_159_n150# 0.10fF
+C30 a_63_n150# a_351_n150# 0.10fF
+C31 a_n33_n150# a_n321_n150# 0.10fF
+C32 a_n33_n150# a_n129_n150# 0.43fF
+C33 a_447_n150# a_255_n150# 0.16fF
+C34 a_n33_n150# a_n417_n150# 0.07fF
+C35 a_255_n150# a_159_n150# 0.43fF
+C36 a_63_n150# a_n225_n150# 0.10fF
+C37 a_n465_172# a_63_n150# 0.10fF
+C38 a_n465_172# a_351_n150# 0.10fF
+C39 a_n33_n150# a_159_n150# 0.16fF
+C40 a_255_n150# a_n33_n150# 0.10fF
+C41 a_63_n150# a_n321_n150# 0.07fF
+C42 a_n465_172# a_n225_n150# 0.10fF
+C43 a_63_n150# a_n129_n150# 0.16fF
+C44 a_447_n150# a_63_n150# 0.07fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_159_n150# a_n33_n150# 0.16fF
+C1 a_447_n150# w_n647_n369# 0.14fF
+C2 a_159_n150# a_n129_n150# 0.10fF
+C3 a_n417_n150# a_n33_n150# 0.07fF
+C4 a_n417_n150# a_n509_n150# 0.43fF
+C5 a_n417_n150# a_n129_n150# 0.10fF
+C6 a_n33_n150# w_n647_n369# 0.02fF
+C7 w_n647_n369# a_n509_n150# 0.14fF
+C8 a_n225_n150# a_n33_n150# 0.16fF
+C9 a_n225_n150# a_n509_n150# 0.10fF
+C10 w_n647_n369# a_n129_n150# 0.02fF
+C11 a_159_n150# a_63_n150# 0.43fF
+C12 a_n225_n150# a_n129_n150# 0.43fF
+C13 a_n417_n150# a_n321_n150# 0.43fF
+C14 a_255_n150# a_447_n150# 0.16fF
+C15 a_n321_n150# w_n647_n369# 0.05fF
+C16 a_n225_n150# a_n321_n150# 0.43fF
+C17 a_n465_n247# a_n33_n150# 0.08fF
+C18 a_63_n150# w_n647_n369# 0.02fF
+C19 a_n465_n247# a_n129_n150# 0.08fF
+C20 a_n225_n150# a_63_n150# 0.10fF
+C21 a_255_n150# a_n33_n150# 0.10fF
+C22 a_n465_n247# a_n321_n150# 0.08fF
+C23 a_255_n150# a_n129_n150# 0.07fF
+C24 a_n465_n247# a_63_n150# 0.08fF
+C25 a_351_n150# a_447_n150# 0.43fF
+C26 a_255_n150# a_63_n150# 0.16fF
+C27 a_351_n150# a_n33_n150# 0.07fF
+C28 a_351_n150# a_63_n150# 0.10fF
+C29 a_159_n150# w_n647_n369# 0.04fF
+C30 a_159_n150# a_n225_n150# 0.07fF
+C31 a_n417_n150# w_n647_n369# 0.07fF
+C32 a_n417_n150# a_n225_n150# 0.16fF
+C33 a_n225_n150# w_n647_n369# 0.04fF
+C34 a_159_n150# a_n465_n247# 0.08fF
+C35 a_n33_n150# a_n129_n150# 0.43fF
+C36 a_159_n150# a_255_n150# 0.43fF
+C37 a_n417_n150# a_n465_n247# 0.08fF
+C38 a_n129_n150# a_n509_n150# 0.07fF
+C39 a_447_n150# a_63_n150# 0.07fF
+C40 a_n465_n247# w_n647_n369# 0.47fF
+C41 a_n225_n150# a_n465_n247# 0.08fF
+C42 a_n33_n150# a_n321_n150# 0.10fF
+C43 a_n321_n150# a_n509_n150# 0.16fF
+C44 a_n321_n150# a_n129_n150# 0.16fF
+C45 a_255_n150# w_n647_n369# 0.05fF
+C46 a_n33_n150# a_63_n150# 0.43fF
+C47 a_63_n150# a_n129_n150# 0.16fF
+C48 a_159_n150# a_351_n150# 0.16fF
+C49 a_63_n150# a_n321_n150# 0.07fF
+C50 a_255_n150# a_n465_n247# 0.08fF
+C51 a_351_n150# w_n647_n369# 0.07fF
+C52 a_n465_n247# a_351_n150# 0.08fF
+C53 a_159_n150# a_447_n150# 0.10fF
+C54 a_255_n150# a_351_n150# 0.43fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_n33_n99# 0.02fF
+C1 a_15_n11# a_n33_n99# 0.02fF
+C2 a_n73_n11# a_15_n11# 0.15fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# w_n216_n334# 0.20fF
+C1 a_20_n114# w_n216_n334# 0.20fF
+C2 a_n78_n114# a_20_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vdd 0.01fF
+C1 vbulkp vdd 0.04fF
+C2 out in 0.11fF
+C3 out vbulkp 0.08fF
+C4 in vss 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 vbp vdd 1.21fF
+C1 out in 0.06fF
+C2 inverter_csvco_0/vdd out 0.02fF
+C3 inverter_csvco_0/vss D0 0.02fF
+C4 out cap_vco_0/t 0.70fF
+C5 inverter_csvco_0/vdd vbp 0.75fF
+C6 out D0 0.09fF
+C7 inverter_csvco_0/vss out 0.03fF
+C8 inverter_csvco_0/vdd vdd 1.89fF
+C9 inverter_csvco_0/vss vctrl 0.87fF
+C10 vdd cap_vco_0/t 0.04fF
+C11 inverter_csvco_0/vdd in 0.01fF
+C12 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C13 inverter_csvco_0/vss in 0.01fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vdd vss csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 vctrl csvco_branch_2/vbp 0.06fF
+C1 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C2 csvco_branch_2/in out_vco 0.58fF
+C3 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C4 D0 csvco_branch_1/inverter_csvco_0/vss 0.68fF
+C5 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
+C6 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C7 vdd csvco_branch_2/vbp 1.49fF
+C8 csvco_branch_1/in out_vco 0.76fF
+C9 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C10 vctrl D0 4.41fF
+C11 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C12 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C13 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
+C14 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 vdd out_div 0.17fF
+C1 vdd out_pad 0.10fF
+C2 vdd o1 0.09fF
+C3 out_div out_pad 0.15fF
+C4 out_div o1 0.11fF
+C5 in_vco vss 0.83fF
+C6 out_pad vss 0.70fF
+C7 out_div vss 3.00fF
+C8 vdd vss 14.54fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 B A 0.28fF
+C1 VGND B 0.10fF
+C2 VGND A 0.31fF
+C3 VPB VPWR 0.06fF
+C4 a_194_125# B 0.57fF
+C5 a_194_125# A 0.18fF
+C6 VGND a_194_125# 0.25fF
+C7 a_355_368# B 0.08fF
+C8 a_355_368# A 0.02fF
+C9 VPWR B 0.09fF
+C10 VPWR A 0.15fF
+C11 VGND VPWR 0.01fF
+C12 a_355_368# a_194_125# 0.51fF
+C13 X B 0.13fF
+C14 a_194_125# VPWR 0.33fF
+C15 X VGND 0.28fF
+C16 a_355_368# VPWR 0.37fF
+C17 X a_194_125# 0.29fF
+C18 X a_355_368# 0.17fF
+C19 X VPWR 0.07fF
+C20 a_158_392# a_194_125# 0.06fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 VPWR A 0.07fF
+C1 B X 0.02fF
+C2 a_56_136# X 0.26fF
+C3 B a_56_136# 0.30fF
+C4 VPB VPWR 0.04fF
+C5 B A 0.08fF
+C6 A a_56_136# 0.17fF
+C7 VGND X 0.15fF
+C8 VPWR X 0.20fF
+C9 B VGND 0.03fF
+C10 VGND a_56_136# 0.06fF
+C11 VPWR B 0.02fF
+C12 VPWR a_56_136# 0.57fF
+C13 A VGND 0.21fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VGND a_63_368# 0.27fF
+C1 A a_63_368# 0.28fF
+C2 VPB VPWR 0.04fF
+C3 a_63_368# a_152_368# 0.03fF
+C4 B VPWR 0.01fF
+C5 VPWR X 0.18fF
+C6 VPWR a_63_368# 0.29fF
+C7 VPWR A 0.05fF
+C8 B VGND 0.11fF
+C9 B a_63_368# 0.14fF
+C10 VGND X 0.16fF
+C11 a_63_368# X 0.33fF
+C12 B A 0.10fF
+C13 A X 0.02fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
++ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
++ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
++ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C1 vdd Q1 9.49fF
+C2 Q0 DFlipFlop_1/D 0.07fF
+C3 Q0 sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.26fF
+C4 DFlipFlop_0/Q Q1 0.13fF
+C5 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
+C6 sky130_fd_sc_hs__and2_1_0/a_56_136# Q1 0.14fF
+C7 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C8 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C9 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C10 DFlipFlop_2/D Q1 0.10fF
+C11 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C12 nCLK nQ0 0.09fF
+C13 Q0 DFlipFlop_0/latch_diff_1/D 0.23fF
+C14 DFlipFlop_2/nQ vdd 0.02fF
+C15 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C16 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C17 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
+C18 CLK_5 vdd 0.15fF
+C19 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C20 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C21 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C22 nCLK Q1 -0.01fF
+C23 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C24 nQ2 vdd 0.04fF
+C25 DFlipFlop_0/Q nQ2 0.09fF
+C26 Q1 DFlipFlop_3/nQ 0.10fF
+C27 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
+C28 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q1 0.09fF
+C29 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
+C30 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C31 DFlipFlop_3/latch_diff_1/nD nCLK 0.09fF
+C32 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C33 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C34 CLK nQ0 0.19fF
+C35 DFlipFlop_2/nQ nCLK 0.09fF
+C36 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C37 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
+C38 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C39 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C40 Q0 nQ0 0.33fF
+C41 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C42 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C43 DFlipFlop_0/D Q1 0.13fF
+C44 nQ2 nCLK 0.10fF
+C45 CLK Q1 -0.10fF
+C46 nQ0 DFlipFlop_1/D 0.12fF
+C47 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C48 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C49 Q1_shift vdd 0.10fF
+C50 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C51 Q0 Q1 9.65fF
+C52 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C53 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C54 DFlipFlop_2/nQ CLK 0.13fF
+C55 DFlipFlop_1/D Q1 0.03fF
+C56 nQ0 DFlipFlop_1/latch_diff_0/m1_657_280# 0.25fF
+C57 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C58 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C59 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C60 DFlipFlop_2/latch_diff_0/D Q1 0.42fF
+C61 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C62 CLK nQ2 0.17fF
+C63 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C64 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C65 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C66 DFlipFlop_2/D vdd 0.07fF
+C67 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C68 Q1_shift DFlipFlop_3/nQ 0.04fF
+C69 Q0 nQ2 0.23fF
+C70 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
+C71 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C72 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C73 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C74 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
+C75 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_1/D 0.03fF
+C76 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
+C77 nCLK vdd 0.34fF
+C78 DFlipFlop_0/Q nCLK 0.11fF
+C79 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
+C80 vdd DFlipFlop_3/nQ 0.02fF
+C81 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C82 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C83 nCLK DFlipFlop_2/D 0.41fF
+C84 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C85 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C86 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C87 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q1 0.20fF
+C88 nQ0 Q1 0.06fF
+C89 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C90 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C91 DFlipFlop_2/latch_diff_1/m1_657_280# Q1 0.03fF
+C92 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C93 DFlipFlop_3/latch_diff_0/D CLK 0.11fF
+C94 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C95 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C96 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C97 DFlipFlop_1/latch_diff_1/m1_657_280# nQ0 0.21fF
+C98 DFlipFlop_0/D vdd 0.19fF
+C99 nQ0 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.04fF
+C100 CLK vdd 0.41fF
+C101 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C102 nCLK DFlipFlop_3/nQ 0.02fF
+C103 DFlipFlop_0/Q CLK 0.08fF
+C104 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C105 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C106 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C107 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C108 CLK DFlipFlop_2/D 0.14fF
+C109 DFlipFlop_3/latch_diff_1/nD Q1 1.24fF
+C110 DFlipFlop_0/latch_diff_1/nD Q1 0.10fF
+C111 Q0 vdd 5.33fF
+C112 DFlipFlop_0/Q Q0 0.21fF
+C113 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C114 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C115 nQ2 nQ0 0.03fF
+C116 DFlipFlop_1/D vdd 0.25fF
+C117 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C118 nCLK DFlipFlop_1/latch_diff_1/nD 0.16fF
+C119 Q0 DFlipFlop_2/D 0.25fF
+C120 DFlipFlop_2/nQ Q1 0.31fF
+C121 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
+C122 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C123 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C124 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C125 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C126 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C127 CLK DFlipFlop_3/nQ 0.01fF
+C128 nQ2 Q1 0.07fF
+C129 DFlipFlop_0/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C130 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C131 Q0 nCLK 0.20fF
+C132 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C133 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C134 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C135 nCLK DFlipFlop_1/D 0.14fF
+C136 nCLK sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.11fF
+C137 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C138 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C139 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C140 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C141 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C142 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C143 Q0 DFlipFlop_0/D 0.39fF
+C144 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C145 Q1_shift Q1 0.36fF
+C146 Q0 CLK 0.08fF
+C147 nQ0 vdd 0.11fF
+C148 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q1 0.21fF
+C149 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C150 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C151 CLK DFlipFlop_1/D 0.21fF
+C152 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C153 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C154 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C155 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C156 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 DFlipFlop_2/nQ vss 0.50fF
+C172 Q1 vss 8.55fF
+C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 nQ0 vss 3.42fF
+C183 Q0 vss 0.53fF
+C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_129_n151# a_225_n151# 0.02fF
+C1 a_n129_n125# a_63_n125# 0.13fF
+C2 a_129_n151# a_33_n151# 0.02fF
+C3 a_n129_n125# a_159_n125# 0.08fF
+C4 a_n129_n125# a_255_n125# 0.06fF
+C5 a_159_n125# a_63_n125# 0.36fF
+C6 a_n63_n151# a_n159_n151# 0.02fF
+C7 a_255_n125# a_63_n125# 0.13fF
+C8 a_n129_n125# a_n33_n125# 0.36fF
+C9 a_n129_n125# a_n225_n125# 0.36fF
+C10 a_63_n125# a_n33_n125# 0.36fF
+C11 a_n225_n125# a_63_n125# 0.08fF
+C12 a_255_n125# a_159_n125# 0.36fF
+C13 a_n317_n125# a_n129_n125# 0.13fF
+C14 a_159_n125# a_n33_n125# 0.13fF
+C15 a_255_n125# a_n33_n125# 0.08fF
+C16 a_n317_n125# a_63_n125# 0.06fF
+C17 a_n225_n125# a_159_n125# 0.06fF
+C18 a_n225_n125# a_n33_n125# 0.13fF
+C19 a_n317_n125# a_n33_n125# 0.08fF
+C20 a_n317_n125# a_n225_n125# 0.36fF
+C21 a_n63_n151# a_33_n151# 0.02fF
+C22 a_n255_n151# a_n159_n151# 0.02fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n455_n344# a_159_n125# 0.06fF
+C1 a_63_n125# a_n317_n125# 0.06fF
+C2 w_n455_n344# a_n129_n125# 0.04fF
+C3 a_n33_n125# a_159_n125# 0.13fF
+C4 a_n129_n125# a_n33_n125# 0.36fF
+C5 a_n317_n125# a_n225_n125# 0.36fF
+C6 w_n455_n344# a_n33_n125# 0.05fF
+C7 a_255_n125# a_159_n125# 0.36fF
+C8 a_129_n154# a_33_n154# 0.02fF
+C9 a_63_n125# a_n225_n125# 0.08fF
+C10 a_n129_n125# a_255_n125# 0.06fF
+C11 a_n63_n154# a_n159_n154# 0.02fF
+C12 w_n455_n344# a_255_n125# 0.11fF
+C13 a_n317_n125# a_n129_n125# 0.13fF
+C14 a_n159_n154# a_n255_n154# 0.02fF
+C15 a_255_n125# a_n33_n125# 0.08fF
+C16 w_n455_n344# a_n317_n125# 0.11fF
+C17 a_63_n125# a_159_n125# 0.36fF
+C18 a_33_n154# a_n63_n154# 0.02fF
+C19 a_63_n125# a_n129_n125# 0.13fF
+C20 a_129_n154# a_225_n154# 0.02fF
+C21 a_n317_n125# a_n33_n125# 0.08fF
+C22 a_n225_n125# a_159_n125# 0.06fF
+C23 a_n129_n125# a_n225_n125# 0.36fF
+C24 w_n455_n344# a_63_n125# 0.04fF
+C25 a_63_n125# a_n33_n125# 0.36fF
+C26 w_n455_n344# a_n225_n125# 0.06fF
+C27 a_n33_n125# a_n225_n125# 0.13fF
+C28 a_n129_n125# a_159_n125# 0.08fF
+C29 a_63_n125# a_255_n125# 0.13fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 out vdd 0.29fF
+C1 out in 0.85fF
+C2 in vdd 0.04fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in vdd 0.42fF
+C1 Down nDown 0.23fF
+C2 vdd QB 0.02fF
+C3 vdd nUp 0.14fF
+C4 inverter_cp_x1_0/out vdd 0.25fF
+C5 vdd Up 0.60fF
+C6 inverter_cp_x1_0/out nDown 0.11fF
+C7 vdd QA 0.02fF
+C8 inverter_cp_x1_0/out Down 0.12fF
+C9 inverter_cp_x1_2/in Up 0.12fF
+C10 vdd nDown 0.80fF
+C11 Up nUp 0.20fF
+C12 Down vdd 0.09fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_159_n90# w_n359_n309# 0.09fF
+C1 a_63_n90# a_n129_n90# 0.09fF
+C2 a_n221_n90# a_63_n90# 0.06fF
+C3 a_n33_n90# a_63_n90# 0.26fF
+C4 a_n221_n90# a_n129_n90# 0.26fF
+C5 a_n33_n90# a_n129_n90# 0.26fF
+C6 a_63_n90# w_n359_n309# 0.06fF
+C7 a_n33_n90# a_n221_n90# 0.09fF
+C8 a_159_n90# a_63_n90# 0.26fF
+C9 w_n359_n309# a_n129_n90# 0.06fF
+C10 a_159_n90# a_n129_n90# 0.06fF
+C11 a_n221_n90# w_n359_n309# 0.09fF
+C12 a_n33_n90# w_n359_n309# 0.05fF
+C13 a_n221_n90# a_159_n90# 0.04fF
+C14 a_n33_n90# a_159_n90# 0.09fF
+C15 a_n159_n207# a_n63_n116# 0.12fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n125_n45# 0.05fF
+C1 a_n125_n45# a_n33_n45# 0.13fF
+C2 a_n129_71# a_33_n71# 0.04fF
+C3 a_63_n45# a_n33_n45# 0.13fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 vdd A 0.09fF
+C1 B out 0.40fF
+C2 vdd out 0.11fF
+C3 A out 0.06fF
+C4 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C5 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out 0.08fF
+C6 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
+C7 A B 0.24fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 Q nor_pfd_3/A 0.98fF
+C1 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C2 Reset nor_pfd_3/A 0.12fF
+C3 nor_pfd_2/B Q 2.22fF
+C4 nor_pfd_2/B Reset 0.43fF
+C5 nor_pfd_2/A vdd -0.01fF
+C6 vdd nor_pfd_3/A 0.09fF
+C7 Q CLK 0.04fF
+C8 Q Reset 0.14fF
+C9 nor_pfd_2/B vdd 0.02fF
+C10 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C11 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C12 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C13 Q vdd 0.08fF
+C14 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C15 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C16 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C17 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C18 nor_pfd_2/B nor_pfd_3/A 0.58fF
+C19 Q nor_pfd_2/A 1.38fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n33_n45# 0.13fF
+C1 a_n221_n45# a_159_n45# 0.02fF
+C2 a_n129_n45# a_159_n45# 0.03fF
+C3 a_n221_n45# a_n33_n45# 0.05fF
+C4 a_n221_n45# a_63_n45# 0.03fF
+C5 a_n129_n45# a_n33_n45# 0.13fF
+C6 a_n129_n45# a_63_n45# 0.05fF
+C7 a_n63_n71# a_n159_n173# 0.10fF
+C8 a_n33_n45# a_159_n45# 0.05fF
+C9 a_63_n45# a_159_n45# 0.13fF
+C10 a_n221_n45# a_n129_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n33_n90# a_63_n90# 0.26fF
+C1 a_33_n187# a_n99_n187# 0.04fF
+C2 a_63_n90# a_n125_n90# 0.09fF
+C3 a_n33_n90# a_n125_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_15_n45# a_n73_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 w_n211_n309# a_n73_n90# 0.04fF
+C1 w_n211_n309# a_15_n90# 0.09fF
+C2 a_n73_n90# a_15_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 B a_656_410# 0.30fF
+C1 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
+C2 a_656_410# A 0.04fF
+C3 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C4 out vdd 0.10fF
+C5 vdd A 0.05fF
+C6 vdd a_656_410# 0.20fF
+C7 out sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.03fF
+C8 out a_656_410# 0.20fF
+C9 B A 0.33fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 dff_pfd_1/nor_pfd_2/B vdd 0.04fF
+C1 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
+C2 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
+C3 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
+C4 Up Down 0.06fF
+C5 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C6 Reset vdd 0.02fF
+C7 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C8 Up vdd 1.62fF
+C9 Down vdd 0.08fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v2 pfd_reset in_ref QA QB Down nDown Up nUp biasp pswitch nswitch
++ vco_vctrl vco_out out_first_buffer out_to_div out_div_2 n_out_div_2 n_out_buffer_div_2
++ out_buffer_div_2 out_by_2 n_out_by_2 div_5_Q1_shift out_div_by_5 div_5_Q1 div_5_Q0
++ div_5_nQ0 div_5_nQ2 iref_cp vdd vss lf_vc D0_vco
+Xcharge_pump_0 nswitch vdd nUp vss Down biasp vco_vctrl pswitch iref_cp nDown Up charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vss
++ D0_vco ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C1 div_5_Q0 out_by_2 0.09fF
+C2 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C3 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C4 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C5 lf_vc vdd 0.02fF
+C6 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
+C7 nUp vco_vctrl 0.02fF
+C8 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C9 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C10 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C11 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
+C12 Up nUp 2.72fF
+C13 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
+C14 div_by_5_0/DFlipFlop_0/Q out_by_2 0.09fF
+C15 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
+C16 Down nswitch 0.54fF
+C17 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
+C18 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C19 nUp nDown -0.09fF
+C20 div_5_Q1 n_out_by_2 1.04fF
+C21 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
+C22 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C23 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C24 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
+C25 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C26 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.17fF
+C27 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
+C28 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C29 n_out_by_2 vco_vctrl 0.52fF
+C30 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C31 div_5_Q1 out_by_2 0.42fF
+C32 vco_vctrl vdd -1.02fF
+C33 out_div_by_5 vdd 0.28fF
+C34 div_by_5_0/DFlipFlop_2/latch_diff_0/D n_out_by_2 0.12fF
+C35 div_by_5_0/DFlipFlop_1/D out_by_2 0.38fF
+C36 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C37 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C38 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C39 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C40 biasp Down 1.24fF
+C41 Up vdd 0.28fF
+C42 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C43 vco_vctrl out_by_2 0.53fF
+C44 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C45 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C46 div_5_Q0 vco_vctrl 0.48fF
+C47 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C48 out_to_buffer vdd 0.07fF
+C49 nDown vdd 0.22fF
+C50 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
+C51 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
+C52 Up pswitch 1.98fF
+C53 iref_cp vdd 0.15fF
+C54 nUp vdd 0.05fF
+C55 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C56 nswitch vco_vctrl -0.06fF
+C57 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C58 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C59 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C60 nDown pswitch 0.53fF
+C61 out_div_by_5 div_5_Q1_shift 0.05fF
+C62 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
+C63 out_to_buffer out_to_div 0.13fF
+C64 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C65 nDown Down 2.55fF
+C66 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C67 nUp pswitch 0.85fF
+C68 n_out_by_2 div_5_nQ0 0.10fF
+C69 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C70 buffer_salida_0/a_678_n100# vdd 0.24fF
+C71 Down iref_cp 0.09fF
+C72 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C73 QA vdd -0.04fF
+C74 nDown nswitch 0.76fF
+C75 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C76 D0_vco vdd 0.03fF
+C77 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C78 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C79 div_5_Q1 vco_vctrl 0.14fF
+C80 div_5_Q1 out_div_by_5 0.01fF
+C81 div_5_nQ0 out_by_2 0.32fF
+C82 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C83 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_to_div -0.16fF
+C84 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C85 n_out_by_2 vdd 1.03fF
+C86 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C87 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C88 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
+C89 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C90 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
+C91 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C92 div_5_nQ2 n_out_by_2 0.10fF
+C93 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C94 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C95 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C96 Up biasp 0.26fF
+C97 out_by_2 vdd 0.97fF
+C98 n_out_by_2 div_5_Q0 -0.12fF
+C99 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
+C100 nDown biasp 0.26fF
+C101 vdd out_to_div 0.21fF
+C102 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C103 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C104 div_5_nQ2 out_by_2 0.16fF
+C105 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
+C106 nUp biasp -0.17fF
+C107 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.93fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss 1.39fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.76fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 6.05fF
+C141 Up vss 2.16fF
+C142 Down vss 6.16fF
+C143 nDown vss 3.38fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C158 div_5_Q1 vss 4.28fF
+C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_nQ0 vss 0.59fF
+C169 div_5_Q0 vss 0.01fF
+C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_to_buffer vss 1.57fF
+C196 out_to_div vss 4.46fF
+C197 out_first_buffer vss 2.88fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 D0_vco vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 n_out_buffer_div_2 vss 1.63fF
+C216 out_buffer_div_2 vss 1.60fF
+C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 lf_vc vss -59.89fF
+C232 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C233 DO_cap vss 0.01fF
+C234 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C235 nswitch vss 3.73fF
+C236 biasp vss 5.44fF
+C237 iref_cp vss 2.81fF
+C238 vco_vctrl vss -21.20fF
+C239 pswitch vss 3.57fF
+.ends
+
diff --git a/mag/extractions/user_analog_prject_wrapper_lvs.spice b/mag/extractions/user_analog_prject_wrapper_lvs.spice
new file mode 100644
index 0000000..43c04f2
--- /dev/null
+++ b/mag/extractions/user_analog_prject_wrapper_lvs.spice
@@ -0,0 +1,7 @@
+* NGSPICE file created from user_analog_prject_wrapper.ext - technology: sky130A
+
+
+* Top level circuit user_analog_prject_wrapper
+
+.end
+
diff --git a/mag/extractions/user_analog_prject_wrapper_pex_c.spice b/mag/extractions/user_analog_prject_wrapper_pex_c.spice
new file mode 100644
index 0000000..43c04f2
--- /dev/null
+++ b/mag/extractions/user_analog_prject_wrapper_pex_c.spice
@@ -0,0 +1,7 @@
+* NGSPICE file created from user_analog_prject_wrapper.ext - technology: sky130A
+
+
+* Top level circuit user_analog_prject_wrapper
+
+.end
+
diff --git a/mag/extractions/user_analog_prject_wrapper_pex_rc.spice b/mag/extractions/user_analog_prject_wrapper_pex_rc.spice
new file mode 100644
index 0000000..43c04f2
--- /dev/null
+++ b/mag/extractions/user_analog_prject_wrapper_pex_rc.spice
@@ -0,0 +1,7 @@
+* NGSPICE file created from user_analog_prject_wrapper.ext - technology: sky130A
+
+
+* Top level circuit user_analog_prject_wrapper
+
+.end
+
diff --git a/mag/extractions/user_analog_project_wrapper.mag_lvs.spice b/mag/extractions/user_analog_project_wrapper.mag_lvs.spice
new file mode 100644
index 0000000..d9a1e27
--- /dev/null
+++ b/mag/extractions/user_analog_project_wrapper.mag_lvs.spice
@@ -0,0 +1,7 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+
+* Top level circuit user_analog_project_wrapper
+
+.end
+
diff --git a/mag/extractions/user_analog_project_wrapper.mag_pex_c.spice b/mag/extractions/user_analog_project_wrapper.mag_pex_c.spice
new file mode 100644
index 0000000..d9a1e27
--- /dev/null
+++ b/mag/extractions/user_analog_project_wrapper.mag_pex_c.spice
@@ -0,0 +1,7 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+
+* Top level circuit user_analog_project_wrapper
+
+.end
+
diff --git a/mag/extractions/user_analog_project_wrapper.mag_pex_rc.spice b/mag/extractions/user_analog_project_wrapper.mag_pex_rc.spice
new file mode 100644
index 0000000..d9a1e27
--- /dev/null
+++ b/mag/extractions/user_analog_project_wrapper.mag_pex_rc.spice
@@ -0,0 +1,7 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+
+* Top level circuit user_analog_project_wrapper
+
+.end
+
diff --git a/mag/extractions/user_analog_project_wrapper_lvs.spice b/mag/extractions/user_analog_project_wrapper_lvs.spice
new file mode 100644
index 0000000..2c675c4
--- /dev/null
+++ b/mag/extractions/user_analog_project_wrapper_lvs.spice
@@ -0,0 +1,1791 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x1 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+.ends
+
+.subckt clock_inverter vss CLK vdd CLK_d nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
+Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt latch_diff nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+.ends
+
+.subckt DFlipFlop vss nQ Q D vdd CLK nCLK
+Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
++ latch_diff
+Xlatch_diff_1 nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D latch_diff
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x4 vdd in vss out
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BDRUME VSUBS a_351_n84# a_n513_n84# a_639_n84# a_159_n84#
++ a_n321_n84# a_447_n84# a_n753_n181# a_n609_n84# w_n935_n303# a_n129_n84# a_735_n84#
++ a_255_n84# a_n417_n84# a_63_n84# a_543_n84# a_n705_n84# a_n225_n84# a_n797_n84#
++ a_n33_n84#
+X0 a_n705_n84# a_n753_n181# a_n797_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n513_n84# a_n753_n181# a_n609_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n417_n84# a_n753_n181# a_n513_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_n321_n84# a_n753_n181# a_n417_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X4 a_n225_n84# a_n753_n181# a_n321_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 a_n129_n84# a_n753_n181# a_n225_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X6 a_n609_n84# a_n753_n181# a_n705_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_63_n84# a_n753_n181# a_n33_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X8 a_n33_n84# a_n753_n181# a_n129_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X9 a_159_n84# a_n753_n181# a_63_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X10 a_255_n84# a_n753_n181# a_159_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X11 a_351_n84# a_n753_n181# a_255_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X12 a_543_n84# a_n753_n181# a_447_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X13 a_447_n84# a_n753_n181# a_351_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X14 a_639_n84# a_n753_n181# a_543_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X15 a_735_n84# a_n753_n181# a_639_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_QQE8KM a_543_n42# a_n705_n42# a_n225_n42# a_n797_n42#
++ a_n33_n42# a_351_n42# a_n513_n42# a_639_n42# a_159_n42# w_n935_n252# a_n757_64#
++ a_n321_n42# a_447_n42# a_n609_n42# a_n129_n42# a_735_n42# a_255_n42# a_n417_n42#
++ a_63_n42#
+X0 a_63_n42# a_n757_64# a_n33_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n757_64# a_n129_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_351_n42# a_n757_64# a_255_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_159_n42# a_n757_64# a_63_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X4 a_255_n42# a_n757_64# a_159_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 a_447_n42# a_n757_64# a_351_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X6 a_543_n42# a_n757_64# a_447_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X7 a_735_n42# a_n757_64# a_639_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X8 a_639_n42# a_n757_64# a_543_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X9 a_n321_n42# a_n757_64# a_n417_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_n705_n42# a_n757_64# a_n797_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 a_n513_n42# a_n757_64# a_n609_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X12 a_n417_n42# a_n757_64# a_n513_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X13 a_n225_n42# a_n757_64# a_n321_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 a_n129_n42# a_n757_64# a_n225_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X15 a_n609_n42# a_n757_64# a_n705_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x16 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_BDRUME_0 vss out vdd vdd out vdd vdd in out vdd vdd out vdd
++ out vdd out vdd out out out sky130_fd_pr__pfet_01v8_BDRUME
+Xsky130_fd_pr__nfet_01v8_QQE8KM_0 out vss out out out out vss vss out vss in vss vss
++ out vss out vss out vss sky130_fd_pr__nfet_01v8_QQE8KM
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_75PKJG VSUBS a_n33_n102# w_n359_n321# a_n177_n199#
++ a_63_n102# a_n129_n102# a_n221_n102# a_25_n199# a_159_n102#
+X0 a_159_n102# a_25_n199# a_63_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_25_n199# a_n33_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X2 a_n129_n102# a_n177_n199# a_n221_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X3 a_n33_n102# a_n177_n199# a_n129_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XRJ78J a_n33_n102# w_n263_n312# a_63_n102# a_n125_n102#
++ a_n81_124#
+X0 a_n33_n102# a_n81_124# a_n125_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_n81_124# a_n33_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+.ends
+
+.subckt nand_logic avss1p8 in1 avdd1p8 in2 out
+Xsky130_fd_pr__pfet_01v8_75PKJG_0 avss1p8 avdd1p8 avdd1p8 in1 out out avdd1p8 in2
++ avdd1p8 sky130_fd_pr__pfet_01v8_75PKJG
+Xsky130_fd_pr__nfet_01v8_XRJ78J_0 m1_21_n341# avss1p8 avss1p8 avss1p8 in1 sky130_fd_pr__nfet_01v8_XRJ78J
+Xsky130_fd_pr__nfet_01v8_XRJ78J_1 out avss1p8 m1_21_n341# m1_21_n341# in2 sky130_fd_pr__nfet_01v8_XRJ78J
+.ends
+
+.subckt res_amp_sync_v2 vss avdd1p8 clk_amp clkn clkp rst
+XDFlipFlop_0 vss DFlipFlop_0/nQ DFlipFlop_0/Q DFlipFlop_3/D avdd1p8 clkp clkn DFlipFlop
+XDFlipFlop_1 vss DFlipFlop_1/nQ DFlipFlop_2/D DFlipFlop_1/D avdd1p8 DFlipFlop_3/D
++ DFlipFlop_0/Q DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ DFlipFlop_2/Q DFlipFlop_2/D avdd1p8 clkp clkn DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ DFlipFlop_3/Q DFlipFlop_3/D avdd1p8 clkp clkn DFlipFlop
+Xinverter_min_x4_0 avdd1p8 DFlipFlop_0/Q vss DFlipFlop_3/D inverter_min_x4
+Xinverter_min_x4_1 avdd1p8 nand_logic_0/out vss DFlipFlop_4/D inverter_min_x4
+XDFlipFlop_4 vss DFlipFlop_4/nQ DFlipFlop_4/Q DFlipFlop_4/D avdd1p8 clkp clkn DFlipFlop
+Xinverter_min_x4_2 avdd1p8 DFlipFlop_2/D vss DFlipFlop_1/D inverter_min_x4
+Xinverter_min_x4_3 avdd1p8 nand_logic_1/out vss rst inverter_min_x4
+Xinverter_min_x4_4 avdd1p8 DFlipFlop_4/Q vss inverter_min_x4_4/out inverter_min_x4
+Xinverter_min_x16_0 inverter_min_x4_4/out clk_amp vss avdd1p8 inverter_min_x16
+Xnand_logic_0 vss DFlipFlop_2/Q avdd1p8 DFlipFlop_3/Q nand_logic_0/out nand_logic
+Xnand_logic_1 vss DFlipFlop_4/D avdd1p8 clkp nand_logic_1/out nand_logic
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_4L9VGG VSUBS a_291_n200# w_n487_n419# a_35_n200#
++ a_n291_n238# a_n93_n200# a_163_n200# a_n349_n200# a_n221_n200#
+X0 a_291_n200# a_n291_n238# a_163_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_n221_n200# a_n291_n238# a_n349_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_35_n200# a_n291_n238# a_n93_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_163_n200# a_n291_n238# a_35_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_n93_n200# a_n291_n238# a_n221_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_L78GGD a_n73_n73# w_n211_n221# a_15_n73# a_n33_33#
+X0 a_15_n73# a_n33_33# a_n73_n73# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_6RX2PQ VSUBS w_n211_n268# a_15_n48# a_n33_n145# a_n73_n48#
+X0 a_15_n48# a_n33_n145# a_n73_n48# w_n211_n268# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min vdd out in vss
+XXM1 vss vss out in sky130_fd_pr__nfet_01v8_L78GGD
+XXM2 vss vdd out in vdd sky130_fd_pr__pfet_01v8_6RX2PQ
+.ends
+
+.subckt buffer_no_inv_x05 VSUBS in avdd1p8 out
+Xinverter_min_1 avdd1p8 out inverter_min_1/in VSUBS inverter_min
+Xinverter_min_0 avdd1p8 inverter_min_1/in in VSUBS inverter_min
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XA7ZMQ VSUBS a_21_142# a_63_n111# a_n87_142# a_n125_n111#
++ w_n263_n330# a_n33_n111#
+X0 a_n33_n111# a_n87_142# a_n125_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+X1 a_63_n111# a_21_142# a_n33_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HAN8QX a_15_n142# a_n33_102# a_n73_n142# w_n211_n290#
+X0 a_15_n142# a_n33_102# a_n73_n142# w_n211_n290# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+.ends
+
+.subckt mux_2to1_logic sel avdd1p8 w_947_n633# avss1p8 out DinA DinB
+Xinverter_min_0 avdd1p8 sel_b sel avss1p8 inverter_min
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_0 avss1p8 sel DinA sel DinA avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_1 avss1p8 sel_b DinB sel_b DinB avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__nfet_01v8_HAN8QX_0 out sel_b DinA avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+Xsky130_fd_pr__nfet_01v8_HAN8QX_1 out sel DinB avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+.ends
+
+.subckt delay_cell_buff clk clk_out avss1p8 avdd1p8 reg0 reg2 reg1 mux_2to1_logic_5/w_947_n633#
+Xbuffer_no_inv_x05_8 avss1p8 mux_2to1_logic_3/DinA avdd1p8 buffer_no_inv_x05_9/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_9 avss1p8 buffer_no_inv_x05_9/in avdd1p8 mux_2to1_logic_3/DinB
++ buffer_no_inv_x05
+Xmux_2to1_logic_0 reg2 avdd1p8 mux_2to1_logic_0/w_947_n633# avss1p8 mux_2to1_logic_0/out
++ clk mux_2to1_logic_0/DinB mux_2to1_logic
+Xmux_2to1_logic_1 reg2 avdd1p8 mux_2to1_logic_1/w_947_n633# avss1p8 mux_2to1_logic_1/out
++ mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB mux_2to1_logic
+Xmux_2to1_logic_2 reg1 avdd1p8 mux_2to1_logic_2/w_947_n633# avss1p8 mux_2to1_logic_2/out
++ mux_2to1_logic_0/out mux_2to1_logic_1/out mux_2to1_logic
+Xmux_2to1_logic_3 reg2 avdd1p8 mux_2to1_logic_3/w_947_n633# avss1p8 mux_2to1_logic_3/out
++ mux_2to1_logic_3/DinA mux_2to1_logic_3/DinB mux_2to1_logic
+Xmux_2to1_logic_4 reg2 avdd1p8 mux_2to1_logic_4/w_947_n633# avss1p8 mux_2to1_logic_4/out
++ mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB mux_2to1_logic
+Xmux_2to1_logic_5 reg1 avdd1p8 mux_2to1_logic_5/w_947_n633# avss1p8 mux_2to1_logic_5/out
++ mux_2to1_logic_3/out mux_2to1_logic_4/out mux_2to1_logic
+Xmux_2to1_logic_6 reg0 avdd1p8 mux_2to1_logic_6/w_947_n633# avss1p8 nand_logic_0/in1
++ mux_2to1_logic_2/out mux_2to1_logic_5/out mux_2to1_logic
+Xbuffer_no_inv_x05_10 avss1p8 mux_2to1_logic_3/DinB avdd1p8 buffer_no_inv_x05_11/in
++ buffer_no_inv_x05
+Xnand_logic_0 avss1p8 nand_logic_0/in1 avdd1p8 clk clk_out nand_logic
+Xbuffer_no_inv_x05_11 avss1p8 buffer_no_inv_x05_11/in avdd1p8 mux_2to1_logic_4/DinA
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_12 avss1p8 mux_2to1_logic_4/DinA avdd1p8 buffer_no_inv_x05_13/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_13 avss1p8 buffer_no_inv_x05_13/in avdd1p8 mux_2to1_logic_4/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_0 avss1p8 clk avdd1p8 buffer_no_inv_x05_1/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_2 avss1p8 mux_2to1_logic_0/DinB avdd1p8 buffer_no_inv_x05_3/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_1 avss1p8 buffer_no_inv_x05_1/in avdd1p8 mux_2to1_logic_0/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_3 avss1p8 buffer_no_inv_x05_3/in avdd1p8 mux_2to1_logic_1/DinA
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_4 avss1p8 mux_2to1_logic_1/DinA avdd1p8 buffer_no_inv_x05_5/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_5 avss1p8 buffer_no_inv_x05_5/in avdd1p8 mux_2to1_logic_1/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_6 avss1p8 mux_2to1_logic_1/DinB avdd1p8 buffer_no_inv_x05_7/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_7 avss1p8 buffer_no_inv_x05_7/in avdd1p8 mux_2to1_logic_3/DinA
++ buffer_no_inv_x05
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_72JNYZ a_n81_n100# w_n311_n310# a_n128_122# a_111_n100#
++ a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n128_122# a_n81_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n81_n100# a_n128_122# a_n173_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n128_122# a_15_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XL9AN VSUBS w_n311_n319# a_n81_n100# a_111_n100#
++ a_n129_131# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_131# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_131# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_131# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XUYGK VSUBS a_n269_n100# a_n81_n100# w_n407_n319#
++ a_111_n100# a_n177_n100# a_15_n100# a_207_n100# a_n225_131#
+X0 a_207_n100# a_n225_131# a_111_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_131# a_n81_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n225_131# a_15_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n225_131# a_n177_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_131# a_n269_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_2AP43D a_15_n81# a_n33_41# w_n211_n229# a_n73_n81#
+X0 a_15_n81# a_n33_41# a_n73_n81# w_n211_n229# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt res_amp_lin clk vctrl avdd1p8 avss1p8 inn outn outp inp
+Xsky130_fd_pr__pfet_01v8_2XL9AN_0 avss1p8 avdd1p8 a_3747_261# a_3747_261# clk avdd1p8
++ avdd1p8 sky130_fd_pr__pfet_01v8_2XL9AN
+Xsky130_fd_pr__pfet_01v8_2XUYGK_0 avss1p8 a_3747_261# a_3747_261# avdd1p8 a_3747_261#
++ vp vp vp vctrl sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_1 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_0 avss1p8 clk avss1p8 outp sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_2 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_1 avss1p8 clk avss1p8 outn sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_3 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_4 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_5 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_6 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_7 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_8 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_595QY5 a_n269_n100# a_n81_n100# a_111_n100# a_n177_n100#
++ a_15_n100# w_n407_n310# a_207_n100# a_n225_n188#
+X0 a_207_n100# a_n225_n188# a_111_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_n188# a_n81_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n225_n188# a_n177_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_111_n100# a_n225_n188# a_15_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_n188# a_n269_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_9B2JY7 a_n317_n100# a_n33_n100# a_n225_n100# a_n271_122#
++ a_63_n100# a_n129_n100# w_n455_n310# a_255_n100# a_159_n100#
+X0 a_63_n100# a_n271_122# a_n33_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n271_122# a_n129_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n271_122# a_63_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n271_122# a_159_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n225_n100# a_n271_122# a_n317_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n129_n100# a_n271_122# a_n225_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_MVT43V a_n33_n100# w_n263_n310# a_63_n100# a_n79_122#
++ a_n125_n100#
+X0 a_63_n100# a_n79_122# a_n33_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n79_122# a_n125_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_NMSMYT a_n33_n100# a_n321_n100# a_n225_n100# w_n551_n310#
++ a_63_n100# a_n368_122# a_n129_n100# a_351_n100# a_255_n100# a_n413_n100# a_159_n100#
+X0 a_63_n100# a_n368_122# a_n33_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n368_122# a_n129_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n368_122# a_63_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n368_122# a_159_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_351_n100# a_n368_122# a_255_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n321_n100# a_n368_122# a_n413_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n225_n100# a_n368_122# a_n321_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n129_n100# a_n368_122# a_n225_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XAYTAL VSUBS w_n311_n319# a_n81_n100# a_n129_n197#
++ a_111_n100# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_n197# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_n197# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_n197# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_B2JNY3 a_n33_n100# a_63_n100# a_n221_n100# a_n129_n100#
++ w_n359_n310# a_n176_122# a_159_n100#
+X0 a_63_n100# a_n176_122# a_n33_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n176_122# a_n129_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n176_122# a_63_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n176_122# a_n221_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XACJHL VSUBS a_n81_n197# w_n263_n319# a_n33_n100#
++ a_63_n100# a_n125_n100#
+X0 a_63_n100# a_n81_n197# a_n33_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_n197# a_n125_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt iref_ctrl_res_amp vctrl avdd1p8 reg0 reg1 reg2 iref avss1p8
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 iref m1_n356_n363# m1_n356_n363# iref iref iref
++ avss1p8 iref m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_n356_n363# m1_n356_n363# avdd1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_0 m1_964_n363# avss1p8 vctrl iref vctrl sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_1 m1_964_n363# avss1p8 avss1p8 reg0 avss1p8 sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_0 vctrl m1_1996_n363# vctrl avss1p8 m1_1996_n363#
++ iref m1_1996_n363# vctrl m1_1996_n363# vctrl vctrl sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_1 avss1p8 m1_1996_n363# avss1p8 avss1p8 m1_1996_n363#
++ reg2 m1_1996_n363# avss1p8 m1_1996_n363# avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 m1_448_n363# avss1p8 iref m1_448_n363# vctrl
++ vctrl sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 m1_448_n363# avss1p8 avdd1p8 m1_448_n363# avss1p8
++ avss1p8 sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__pfet_01v8_XAYTAL_0 avss1p8 avdd1p8 m1_511_801# avss1p8 m1_511_801#
++ avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8_XAYTAL
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_0 vctrl m1_1384_n363# vctrl m1_1384_n363# avss1p8
++ iref vctrl sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_1 avss1p8 m1_1384_n363# avss1p8 m1_1384_n363#
++ avss1p8 reg1 avss1p8 sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__pfet_01v8_XACJHL_0 avss1p8 vctrl avdd1p8 m1_511_801# vctrl vctrl sky130_fd_pr__pfet_01v8_XACJHL
+.ends
+
+.subckt res_amp_lin_prog avdd1p8 delay_reg2 clk avss1p8 outp_cap iref_reg0 iref_reg1
++ iref_reg2 iref delay_reg0 inn outn_cap inp delay_reg1 rst
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_0 avss1p8 outn_cap avdd1p8 outn_cap res_amp_lin_0/clk
++ outn outn outn outn_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_1 avss1p8 outp_cap avdd1p8 outp_cap res_amp_lin_0/clk
++ outp outp outp outp_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xdelay_cell_buff_0 clk res_amp_lin_0/clk avss1p8 avdd1p8 delay_reg0 delay_reg2 delay_reg1
++ avss1p8 delay_cell_buff
+Xinverter_min_x4_0 avdd1p8 res_amp_lin_0/clk avss1p8 inverter_min_x4_0/out inverter_min_x4
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 outn_cap avss1p8 rst outn_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xres_amp_lin_0 res_amp_lin_0/clk res_amp_lin_0/vctrl avdd1p8 avss1p8 inn outn outp
++ inp res_amp_lin
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 outp_cap avss1p8 rst outp_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_0 outn outn outn outn_cap outn_cap avss1p8 outn_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_1 outp outp outp outp_cap outp_cap avss1p8 outp_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xiref_ctrl_res_amp_0 res_amp_lin_0/vctrl avdd1p8 iref_reg0 iref_reg1 iref_reg2 iref
++ avss1p8 iref_ctrl_res_amp
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_U5ZKVF VSUBS m3_n700_n850# c1_n600_n750#
+X0 c1_n600_n750# m3_n700_n850# sky130_fd_pr__cap_mim_m3_1 l=7.5e+06u w=5.5e+06u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_D3F744 VSUBS a_n285_n236# a_355_n236# a_n29_n236#
++ a_n413_n236# a_99_n236# a_n611_n262# a_483_n236# a_n669_n236# w_n807_n384# a_n157_n236#
++ a_n541_n236# a_227_n236# a_611_n236#
+X0 a_n157_n236# a_n611_n262# a_n285_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_611_n236# a_n611_n262# a_483_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_227_n236# a_n611_n262# a_99_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_n285_n236# a_n611_n262# a_n413_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_99_n236# a_n611_n262# a_n29_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X5 a_355_n236# a_n611_n262# a_227_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X6 a_483_n236# a_n611_n262# a_355_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X7 a_n29_n236# a_n611_n262# a_n157_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X8 a_n413_n236# a_n611_n262# a_n541_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X9 a_n541_n236# a_n611_n262# a_n669_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_VCU74W VSUBS a_495_n100# a_n81_n100# a_399_n100# a_687_n100#
++ a_n749_n100# a_n273_n100# a_111_n100# a_n177_n100# a_n561_n100# a_15_n100# a_n465_n100#
++ a_n705_n197# a_303_n100# a_n369_n100# w_n887_n319# a_207_n100# a_n657_n100# a_591_n100#
+X0 a_303_n100# a_n705_n197# a_207_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_591_n100# a_n705_n197# a_495_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_207_n100# a_n705_n197# a_111_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_399_n100# a_n705_n197# a_303_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_495_n100# a_n705_n197# a_399_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_687_n100# a_n705_n197# a_591_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n561_n100# a_n705_n197# a_n657_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n465_n100# a_n705_n197# a_n561_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n657_n100# a_n705_n197# a_n749_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n369_n100# a_n705_n197# a_n465_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_15_n100# a_n705_n197# a_n81_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_111_n100# a_n705_n197# a_15_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n273_n100# a_n705_n197# a_n369_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n81_n100# a_n705_n197# a_n177_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n177_n100# a_n705_n197# a_n273_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt source_follower_buff_pmos in avdd1p8 out iref avss1p8
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 avss1p8 iref iref iref avss1p8 avss1p8 avss1p8
++ avss1p8 iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_957_828# m1_957_828# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_957_828# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__pfet_01v8_lvt_D3F744_0 avss1p8 out avss1p8 out avss1p8 avss1p8 in out
++ avss1p8 avdd1p8 avss1p8 out out avss1p8 sky130_fd_pr__pfet_01v8_lvt_D3F744
+Xsky130_fd_pr__pfet_01v8_VCU74W_0 avss1p8 m1_957_828# m1_957_828# avdd1p8 m1_957_828#
++ avdd1p8 m1_957_828# m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# m1_957_828#
++ m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+Xsky130_fd_pr__pfet_01v8_VCU74W_1 avss1p8 out out avdd1p8 out avdd1p8 out out avdd1p8
++ avdd1p8 avdd1p8 out m1_957_828# out avdd1p8 avdd1p8 avdd1p8 out avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CFLRKA a_n993_109# a_n1473_n309# a_63_n309# a_1215_n309#
++ a_1215_109# a_n129_n309# a_735_109# a_1599_109# a_n513_n309# a_255_109# a_n1377_n309#
++ a_n1949_109# a_n1761_n309# a_1119_n309# a_1503_n309# a_n1761_109# a_n417_109# a_n417_n309#
++ a_n1281_109# a_n801_n309# a_351_n309# a_63_109# a_1503_109# a_n1665_n309# a_1023_109#
++ a_1887_109# a_1407_n309# a_543_109# a_n705_n309# a_255_n309# a_1791_n309# a_n1569_109#
++ a_n705_109# a_n1569_n309# a_n1089_109# w_n2087_n519# a_n225_109# a_n609_n309# a_159_n309#
++ a_543_n309# a_1695_n309# a_1311_109# a_831_109# a_1695_109# a_n1857_n309# a_n993_n309#
++ a_n33_109# a_351_109# a_n1857_109# a_447_n309# a_831_n309# a_1599_n309# a_n1377_109#
++ a_n897_n309# a_n897_109# a_n513_109# a_1119_109# a_639_109# a_n33_n309# a_735_n309#
++ a_1887_n309# a_159_109# a_n1665_109# a_n1281_n309# a_1023_n309# a_n1185_109# a_n801_109#
++ a_639_n309# a_n321_109# a_1407_109# a_n321_n309# a_927_109# a_447_109# a_1791_109#
++ a_n1185_n309# a_1311_n309# a_n1905_n87# a_927_n309# a_n609_109# a_n225_n309# a_n1473_109#
++ a_n129_109# a_n1949_n309# a_n1089_n309#
+X0 a_n1569_n309# a_n1905_n87# a_n1665_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n87# a_n993_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_927_n309# a_n1905_n87# a_831_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1023_109# a_n1905_n87# a_927_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_255_n309# a_n1905_n87# a_159_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n87# a_1119_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_927_109# a_n1905_n87# a_831_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n1857_n309# a_n1905_n87# a_n1949_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n321_n309# a_n1905_n87# a_n417_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n1761_109# a_n1905_n87# a_n1857_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_543_n309# a_n1905_n87# a_447_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_1503_n309# a_n1905_n87# a_1407_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n1857_109# a_n1905_n87# a_n1949_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n1665_109# a_n1905_n87# a_n1761_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1569_109# a_n1905_n87# a_n1665_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1215_109# a_n1905_n87# a_1119_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_1311_109# a_n1905_n87# a_1215_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_1503_109# a_n1905_n87# a_1407_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_1791_109# a_n1905_n87# a_1695_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n87# a_n1281_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_1119_109# a_n1905_n87# a_1023_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1407_109# a_n1905_n87# a_1311_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_1599_109# a_n1905_n87# a_1503_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1695_109# a_n1905_n87# a_1599_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1887_109# a_n1905_n87# a_1791_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_n1473_n309# a_n1905_n87# a_n1569_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_831_n309# a_n1905_n87# a_735_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1791_n309# a_n1905_n87# a_1695_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n33_109# a_n1905_n87# a_n129_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_351_109# a_n1905_n87# a_255_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_159_n309# a_n1905_n87# a_63_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1119_n309# a_n1905_n87# a_1023_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_159_109# a_n1905_n87# a_63_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_255_109# a_n1905_n87# a_159_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_447_109# a_n1905_n87# a_351_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_543_109# a_n1905_n87# a_447_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_735_109# a_n1905_n87# a_639_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_831_109# a_n1905_n87# a_735_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n225_n309# a_n1905_n87# a_n321_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_639_109# a_n1905_n87# a_543_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_447_n309# a_n1905_n87# a_351_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_1407_n309# a_n1905_n87# a_1311_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_n1473_109# a_n1905_n87# a_n1569_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_n1281_109# a_n1905_n87# a_n1377_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_n1185_109# a_n1905_n87# a_n1281_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_n993_109# a_n1905_n87# a_n1089_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_n1089_n309# a_n1905_n87# a_n1185_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n1377_109# a_n1905_n87# a_n1473_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n1089_109# a_n1905_n87# a_n1185_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_n321_109# a_n1905_n87# a_n417_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n513_n309# a_n1905_n87# a_n609_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_63_n309# a_n1905_n87# a_n33_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_n801_109# a_n1905_n87# a_n897_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_n705_109# a_n1905_n87# a_n801_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_n513_109# a_n1905_n87# a_n609_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_n417_109# a_n1905_n87# a_n513_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n225_109# a_n1905_n87# a_n321_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n129_109# a_n1905_n87# a_n225_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n1377_n309# a_n1905_n87# a_n1473_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_735_n309# a_n1905_n87# a_639_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_1695_n309# a_n1905_n87# a_1599_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n897_109# a_n1905_n87# a_n993_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n609_109# a_n1905_n87# a_n705_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n801_n309# a_n1905_n87# a_n897_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n129_n309# a_n1905_n87# a_n225_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n1761_n309# a_n1905_n87# a_n1857_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n417_n309# a_n1905_n87# a_n513_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_109# a_n1905_n87# a_n33_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_639_n309# a_n1905_n87# a_543_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_1599_n309# a_n1905_n87# a_1503_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n705_n309# a_n1905_n87# a_n801_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1887_n309# a_n1905_n87# a_1791_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n1665_n309# a_n1905_n87# a_n1761_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_1023_n309# a_n1905_n87# a_927_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n993_n309# a_n1905_n87# a_n1089_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_n33_n309# a_n1905_n87# a_n129_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_351_n309# a_n1905_n87# a_255_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_1311_n309# a_n1905_n87# a_1215_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n1281_n309# a_n1905_n87# a_n1377_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_n609_n309# a_n1905_n87# a_n705_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CAF2P9 a_63_n309# a_n1473_n309# a_159_527# a_1215_n309#
++ a_n993_109# a_1215_109# a_n129_n309# a_n513_n309# a_1599_109# a_735_109# a_n1665_527#
++ a_n1281_n727# a_n801_527# a_1023_n727# a_639_n727# a_255_109# a_n1185_527# a_n1377_n309#
++ a_n1949_109# a_1119_n309# a_n1761_n309# a_n321_527# a_1503_n309# a_1407_527# a_n321_n727#
++ a_927_527# a_n1761_109# a_n417_109# a_n417_n309# a_351_n309# a_n801_n309# a_n1905_n505#
++ a_n1281_109# a_n1185_n727# a_447_527# a_1791_527# a_63_109# a_1311_n727# a_927_n727#
++ a_1503_109# a_n1665_n309# a_1407_n309# a_1887_109# a_n225_n727# a_1023_109# a_n609_527#
++ a_543_109# a_255_n309# a_n1473_527# a_n1949_n727# a_1791_n309# a_n705_n309# a_n129_527#
++ a_n1089_n727# a_n1473_n727# a_1215_n727# a_63_n727# a_n993_527# a_n1569_109# a_n1569_n309#
++ a_n705_109# a_1215_527# a_n129_n727# a_n1089_109# a_1599_527# a_n513_n727# a_735_527#
++ a_n225_109# a_1695_n309# a_159_n309# a_n609_n309# a_543_n309# a_255_527# a_n1377_n727#
++ a_n1949_527# a_1119_n727# a_n1761_n727# a_1503_n727# a_1311_109# a_n993_n309# a_1695_109#
++ a_n1857_n309# a_831_109# a_n1761_527# a_n33_109# a_n417_n727# a_n417_527# a_351_109#
++ a_351_n727# a_n801_n727# a_n1281_527# a_n1857_109# a_1599_n309# a_447_n309# a_63_527#
++ a_831_n309# a_1503_527# a_n1377_109# a_n1665_n727# a_1887_527# a_1407_n727# a_n897_n309#
++ a_1023_527# a_n513_109# a_n897_109# a_543_527# a_1791_n727# a_255_n727# a_n705_n727#
++ a_1119_109# a_1887_n309# a_639_109# a_735_n309# a_n33_n309# a_n1569_527# a_n1569_n727#
++ a_n705_527# a_159_109# a_n1089_527# a_n225_527# w_n2087_n937# a_1695_n727# a_159_n727#
++ a_n609_n727# a_543_n727# a_n1665_109# a_n1281_n309# a_1023_n309# a_1311_527# a_n801_109#
++ a_639_n309# a_1695_527# a_n1185_109# a_n993_n727# a_831_527# a_n1857_n727# a_n321_109#
++ a_1407_109# a_n33_527# a_n321_n309# a_351_527# a_927_109# a_1599_n727# a_n1857_527#
++ a_447_n727# a_831_n727# a_447_109# a_n1185_n309# a_n1377_527# a_1791_109# a_1311_n309#
++ a_n897_n727# a_927_n309# a_n513_527# a_n897_527# a_n225_n309# a_n609_109# a_1119_527#
++ a_1887_n727# a_n1949_n309# a_639_527# a_n1473_109# a_n129_109# a_735_n727# a_n33_n727#
++ a_n1089_n309#
+X0 a_927_n309# a_n1905_n505# a_831_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n505# a_n993_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n1569_n309# a_n1905_n505# a_n1665_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n727# a_n1905_n505# a_n225_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n1761_n727# a_n1905_n505# a_n1857_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n505# a_1119_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_255_n309# a_n1905_n505# a_159_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1023_109# a_n1905_n505# a_927_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n1857_n309# a_n1905_n505# a_n1949_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_927_109# a_n1905_n505# a_831_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_n417_n727# a_n1905_n505# a_n513_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_n321_n309# a_n1905_n505# a_n417_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_1599_n727# a_n1905_n505# a_1503_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_63_527# a_n1905_n505# a_n33_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1761_109# a_n1905_n505# a_n1857_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1503_n309# a_n1905_n505# a_1407_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_639_n727# a_n1905_n505# a_543_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_543_n309# a_n1905_n505# a_447_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_n1665_109# a_n1905_n505# a_n1761_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n505# a_n1281_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_n1569_109# a_n1905_n505# a_n1665_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1311_109# a_n1905_n505# a_1215_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1857_109# a_n1905_n505# a_n1949_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1791_109# a_n1905_n505# a_1695_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1503_109# a_n1905_n505# a_1407_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_1215_109# a_n1905_n505# a_1119_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_n705_n727# a_n1905_n505# a_n801_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1119_109# a_n1905_n505# a_1023_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_1695_109# a_n1905_n505# a_1599_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_1407_109# a_n1905_n505# a_1311_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_1599_109# a_n1905_n505# a_1503_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1887_109# a_n1905_n505# a_1791_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_1887_n727# a_n1905_n505# a_1791_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_1791_n309# a_n1905_n505# a_1695_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_831_n309# a_n1905_n505# a_735_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_n1473_n309# a_n1905_n505# a_n1569_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_n33_109# a_n1905_n505# a_n129_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_1023_n727# a_n1905_n505# a_927_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n1665_n727# a_n1905_n505# a_n1761_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_1119_n309# a_n1905_n505# a_1023_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_159_n309# a_n1905_n505# a_63_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_351_109# a_n1905_n505# a_255_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_1311_n727# a_n1905_n505# a_1215_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_255_109# a_n1905_n505# a_159_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_351_n727# a_n1905_n505# a_255_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_831_109# a_n1905_n505# a_735_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_543_109# a_n1905_n505# a_447_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n33_n727# a_n1905_n505# a_n129_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n993_n727# a_n1905_n505# a_n1089_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_159_109# a_n1905_n505# a_63_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n225_n309# a_n1905_n505# a_n321_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_735_109# a_n1905_n505# a_639_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_447_109# a_n1905_n505# a_351_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_639_109# a_n1905_n505# a_543_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_1407_n309# a_n1905_n505# a_1311_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_447_n309# a_n1905_n505# a_351_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n1089_n309# a_n1905_n505# a_n1185_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n1281_109# a_n1905_n505# a_n1377_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n993_109# a_n1905_n505# a_n1089_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_n1473_109# a_n1905_n505# a_n1569_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_n1185_109# a_n1905_n505# a_n1281_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n609_n727# a_n1905_n505# a_n705_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n1377_109# a_n1905_n505# a_n1473_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n1089_109# a_n1905_n505# a_n1185_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n1281_n727# a_n1905_n505# a_n1377_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n513_n309# a_n1905_n505# a_n609_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n321_109# a_n1905_n505# a_n417_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_n309# a_n1905_n505# a_n33_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_n225_109# a_n1905_n505# a_n321_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_n801_109# a_n1905_n505# a_n897_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n513_109# a_n1905_n505# a_n609_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1695_n309# a_n1905_n505# a_1599_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n705_109# a_n1905_n505# a_n801_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_n417_109# a_n1905_n505# a_n513_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n129_109# a_n1905_n505# a_n225_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_735_n309# a_n1905_n505# a_639_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_n1377_n309# a_n1905_n505# a_n1473_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_n897_109# a_n1905_n505# a_n993_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n609_109# a_n1905_n505# a_n705_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_927_n727# a_n1905_n505# a_831_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X80 a_n1569_n727# a_n1905_n505# a_n1665_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X81 a_n897_n727# a_n1905_n505# a_n993_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X82 a_n801_n309# a_n1905_n505# a_n897_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X83 a_1215_n727# a_n1905_n505# a_1119_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X84 a_255_n727# a_n1905_n505# a_159_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X85 a_1023_527# a_n1905_n505# a_927_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X86 a_n129_n309# a_n1905_n505# a_n225_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X87 a_927_527# a_n1905_n505# a_831_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X88 a_n1857_n727# a_n1905_n505# a_n1949_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X89 a_n1761_n309# a_n1905_n505# a_n1857_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X90 a_n321_n727# a_n1905_n505# a_n417_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X91 a_n1761_527# a_n1905_n505# a_n1857_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X92 a_1503_n727# a_n1905_n505# a_1407_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X93 a_n1665_527# a_n1905_n505# a_n1761_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X94 a_543_n727# a_n1905_n505# a_447_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X95 a_n1185_n727# a_n1905_n505# a_n1281_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X96 a_n417_n309# a_n1905_n505# a_n513_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X97 a_n1857_527# a_n1905_n505# a_n1949_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X98 a_n1569_527# a_n1905_n505# a_n1665_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X99 a_1311_527# a_n1905_n505# a_1215_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X100 a_1215_527# a_n1905_n505# a_1119_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X101 a_1503_527# a_n1905_n505# a_1407_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X102 a_1791_527# a_n1905_n505# a_1695_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X103 a_1119_527# a_n1905_n505# a_1023_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X104 a_1407_527# a_n1905_n505# a_1311_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X105 a_1695_527# a_n1905_n505# a_1599_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X106 a_1599_n309# a_n1905_n505# a_1503_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X107 a_63_109# a_n1905_n505# a_n33_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X108 a_639_n309# a_n1905_n505# a_543_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X109 a_1599_527# a_n1905_n505# a_1503_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X110 a_1887_527# a_n1905_n505# a_1791_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X111 a_1791_n727# a_n1905_n505# a_1695_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X112 a_831_n727# a_n1905_n505# a_735_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X113 a_n1473_n727# a_n1905_n505# a_n1569_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X114 a_n705_n309# a_n1905_n505# a_n801_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X115 a_n33_527# a_n1905_n505# a_n129_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X116 a_1887_n309# a_n1905_n505# a_1791_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X117 a_1119_n727# a_n1905_n505# a_1023_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X118 a_159_n727# a_n1905_n505# a_63_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X119 a_351_527# a_n1905_n505# a_255_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X120 a_1023_n309# a_n1905_n505# a_927_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X121 a_n1665_n309# a_n1905_n505# a_n1761_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X122 a_255_527# a_n1905_n505# a_159_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X123 a_543_527# a_n1905_n505# a_447_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X124 a_831_527# a_n1905_n505# a_735_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X125 a_159_527# a_n1905_n505# a_63_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X126 a_447_527# a_n1905_n505# a_351_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X127 a_n225_n727# a_n1905_n505# a_n321_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X128 a_735_527# a_n1905_n505# a_639_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X129 a_639_527# a_n1905_n505# a_543_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X130 a_1407_n727# a_n1905_n505# a_1311_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X131 a_447_n727# a_n1905_n505# a_351_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X132 a_1311_n309# a_n1905_n505# a_1215_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X133 a_n1089_n727# a_n1905_n505# a_n1185_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X134 a_351_n309# a_n1905_n505# a_255_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X135 a_n33_n309# a_n1905_n505# a_n129_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X136 a_n1281_527# a_n1905_n505# a_n1377_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X137 a_n993_527# a_n1905_n505# a_n1089_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X138 a_n993_n309# a_n1905_n505# a_n1089_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X139 a_n1473_527# a_n1905_n505# a_n1569_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X140 a_n1185_527# a_n1905_n505# a_n1281_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X141 a_n1377_527# a_n1905_n505# a_n1473_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X142 a_n1089_527# a_n1905_n505# a_n1185_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X143 a_n513_n727# a_n1905_n505# a_n609_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X144 a_n321_527# a_n1905_n505# a_n417_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X145 a_63_n727# a_n1905_n505# a_n33_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X146 a_n801_527# a_n1905_n505# a_n897_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X147 a_n513_527# a_n1905_n505# a_n609_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X148 a_n225_527# a_n1905_n505# a_n321_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X149 a_1695_n727# a_n1905_n505# a_1599_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X150 a_735_n727# a_n1905_n505# a_639_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X151 a_n705_527# a_n1905_n505# a_n801_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X152 a_n417_527# a_n1905_n505# a_n513_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X153 a_n129_527# a_n1905_n505# a_n225_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X154 a_n1377_n727# a_n1905_n505# a_n1473_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X155 a_n609_n309# a_n1905_n505# a_n705_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X156 a_n1281_n309# a_n1905_n505# a_n1377_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X157 a_n897_527# a_n1905_n505# a_n993_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X158 a_n609_527# a_n1905_n505# a_n705_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X159 a_n801_n727# a_n1905_n505# a_n897_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt source_follower_buff_nmos in avdd1p8 avss1p8 out iref
+Xsky130_fd_pr__nfet_01v8_lvt_CFLRKA_0 avdd1p8 out out out out out avdd1p8 out out
++ out avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8
++ avdd1p8 out avdd1p8 out out avdd1p8 out avdd1p8 out out out avdd1p8 out avdd1p8
++ out avss1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8 out avdd1p8
++ avdd1p8 avdd1p8 out out out out avdd1p8 out out out avdd1p8 out avdd1p8 avdd1p8
++ avdd1p8 avdd1p8 out out out avdd1p8 avdd1p8 out out out out avdd1p8 out out avdd1p8
++ avdd1p8 in avdd1p8 avdd1p8 avdd1p8 out out avdd1p8 out sky130_fd_pr__nfet_01v8_lvt_CFLRKA
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 m1_460_n1129# iref iref iref m1_460_n1129# m1_460_n1129#
++ avss1p8 m1_460_n1129# iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_460_n1129# m1_460_n1129# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_460_n1129# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_CAF2P9_0 out out avss1p8 out avss1p8 out out out out
++ avss1p8 out out avss1p8 out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out
++ avss1p8 out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 iref out avss1p8
++ out out out avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 out avss1p8 avss1p8
++ out out avss1p8 out out out out out out out avss1p8 avss1p8 avss1p8 out out out
++ out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out out out out avss1p8 avss1p8 out avss1p8
++ out out out out out avss1p8 out out out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8
++ avss1p8 out avss1p8 out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out
++ out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8 out out out out avss1p8 out avss1p8
++ avss1p8 out out out out out avss1p8 avss1p8 out avss1p8 out avss1p8 out out avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out avss1p8 avss1p8 out sky130_fd_pr__nfet_01v8_lvt_CAF2P9
+.ends
+
+.subckt source_follower_buff_diff VSUBS avdd1p8 iref1 iref2 iref3 iref4 inn outn inp
++ outp
+Xsource_follower_buff_pmos_0 inn avdd1p8 source_follower_buff_nmos_0/in iref3 VSUBS
++ source_follower_buff_pmos
+Xsource_follower_buff_pmos_1 inp avdd1p8 source_follower_buff_nmos_1/in iref1 VSUBS
++ source_follower_buff_pmos
+Xsource_follower_buff_nmos_0 source_follower_buff_nmos_0/in avdd1p8 VSUBS outn iref4
++ source_follower_buff_nmos
+Xsource_follower_buff_nmos_1 source_follower_buff_nmos_1/in avdd1p8 VSUBS outp iref2
++ source_follower_buff_nmos
+.ends
+
+.subckt res_amp_top iref0 iref1 avss1p8 iref2 iref3 iref4 avdd1p8 res_amp_sync_v2_0/clkp
++ iref_reg0 iref_reg1 iref_reg2 delay_reg0 delay_reg1 inn outn delay_reg2 outp inp
++ clkn
+Xres_amp_sync_v2_0 avss1p8 avdd1p8 res_amp_lin_prog_0/clk clkn res_amp_sync_v2_0/clkp
++ res_amp_sync_v2_0/rst res_amp_sync_v2
+Xres_amp_lin_prog_0 avdd1p8 delay_reg2 res_amp_lin_prog_0/clk avss1p8 res_amp_lin_prog_0/outp_cap
++ iref_reg0 iref_reg1 iref_reg2 iref0 delay_reg0 inn res_amp_lin_prog_0/outn_cap inp
++ delay_reg1 res_amp_sync_v2_0/rst res_amp_lin_prog
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_0 avss1p8 avss1p8 res_amp_lin_prog_0/outp_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_1 avss1p8 avss1p8 res_amp_lin_prog_0/outn_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsource_follower_buff_diff_0 avss1p8 avdd1p8 iref1 iref2 iref3 iref4 res_amp_lin_prog_0/outn_cap
++ outn res_amp_lin_prog_0/outp_cap outp source_follower_buff_diff
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt charge_pump Down out iref pswitch nDown biasp Up nswitch vss vdd nUp
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+.ends
+
+.subckt div_by_2 vss vdd CLK_2 nCLK_2 o1 CLK out_div o2 nout_div
+XDFlipFlop_0 vss nout_div out_div nout_div vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK DFlipFlop
+Xinverter_min_x4_1 vdd o2 vss nCLK_2 inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss CLK_2 inverter_min_x4
+Xclock_inverter_0 vss CLK vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+.ends
+
+.subckt buffer_salida in out vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+*C1 t VSUBS 0.42fF
+*C2 b VSUBS 0.09fF
+.ends
+
+
+.subckt csvco_branch vctrl in vbp D0 out vss vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+.ends
+
+.subckt ring_osc vctrl vdd vss D0 out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp D0 csvco_branch_1/in vss vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp D0 out_vco vss vdd csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp D0 csvco_branch_2/in vss
++ vdd csvco_branch
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_1 vdd out_div vss out_pad inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss out_div inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt div_by_5 nCLK vss vdd Q0 CLK nQ0 CLK_5 nQ2 Q1 Q1_shift
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 vss nQ2 DFlipFlop_0/Q DFlipFlop_0/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ Q1 DFlipFlop_2/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_1 vss nQ0 Q0 DFlipFlop_1/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ Q1_shift Q1 vdd nCLK CLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+.ends
+
+.subckt pfd_cp_interface vss vdd Down QA QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 QB vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS w_n359_n309# a_n63_n116# a_n159_n207#
++ a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt nor_pfd out vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss vdd B A out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+.ends
+
+.subckt dff_pfd vdd vss Q CLK Reset
+Xnor_pfd_0 nor_pfd_2/A vss vdd CLK Q nor_pfd
+Xnor_pfd_1 Q vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_3/A vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_2/B vss vdd nor_pfd_3/A Reset nor_pfd
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt and_pfd vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vdd vss Up A Reset dff_pfd
+Xdff_pfd_1 vdd vss Down B Reset dff_pfd
+Xand_pfd_0 vss Reset vdd Up Down and_pfd
+.ends
+
+.subckt top_pll_v1 vdd in_ref w_13905_n238# vss vco_D0 iref_cp out_to_pad
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
+Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss vco_D0 vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 n_out_by_2 vss vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2
++ div_5_Q1 div_5_Q1_shift div_by_5
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_2_2Y8F6P VSUBS c2_n3251_n3000# m4_n3351_n3100#
+X0 c2_n3251_n3000# m4_n3351_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_8P223X VSUBS a_n2017_n1317# a_n1731_n1219# a_n1879_n1219#
++ a_n2017_n61# w_n2018_n202#
+X0 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X1 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X2 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X3 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X4 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X5 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X6 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X7 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X8 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X9 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X10 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X11 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X12 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X13 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X14 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X15 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X16 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X17 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X18 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X19 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X20 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X21 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X22 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X23 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X24 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X25 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X26 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X27 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X28 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X29 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X30 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X31 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X32 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X33 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X34 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X35 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X36 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X37 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X38 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X39 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X40 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X41 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X42 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X43 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X44 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X45 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X46 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X47 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X48 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+.ends
+
+.subckt bias VSUBS vdd iref_0 iref_1 iref_2 iref_5 iref_6 iref_7 iref_8 iref_9 iref
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_5 VSUBS iref m1_20168_984# iref m1_20168_984#
++ vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_6 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219#
++ iref_5 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_7 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219#
++ iref_6 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_9 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219#
++ iref_8 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_8 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219#
++ iref_7 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_10 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219#
++ iref_9 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_0 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219#
++ iref_0 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_1 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219#
++ iref_1 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_2 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219#
++ iref_2 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_3 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219#
++ iref_3 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_4 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219#
++ iref_4 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+.ends
+
+.subckt mimcap_decoup_1x5 VSUBS t b
+Xdecap[0] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[1] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[2] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[3] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[4] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt top_pll_v2 vdd in_ref w_13905_n238# vss D0_vco iref_cp DO_cap out_to_pad
+Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss D0_vco vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 n_out_by_2 vss vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2
++ div_5_Q1 div_5_Q1_shift div_by_5
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+.ends
+
+*.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
+*+ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
+*+ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
+*+ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
+*+ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
+*+ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
+*+ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
+*+ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7]
+*+ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
+*+ io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
+*+ io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
+*+ io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9]
+*+ io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14]
+*+ io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1]
+*+ io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25]
+*+ io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7]
+*+ io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
+*+ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20]
+*+ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3]
+*+ io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10]
+*+ io_out[11] io_out[12] io_out[13] io_out[14] io_out[15] io_out[16] io_out[17] io_out[18]
+*+ io_out[19] io_out[1] io_out[20] io_out[21] io_out[22] io_out[23] io_out[24] io_out[25]
+*+ io_out[26] io_out[2] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8]
+*+ io_out[9] la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103]
+*+ la_data_in[104] la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108]
+*+ la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113]
+*+ la_data_in[114] la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118]
+*+ la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123]
+*+ la_data_in[124] la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13]
+*+ la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19]
+*+ la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24]
+*+ la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2]
+*+ la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35]
+*+ la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40]
+*+ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46]
+*+ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51]
+*+ la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57]
+*+ la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62]
+*+ la_data_in[63] la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68]
+*+ la_data_in[69] la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73]
+*+ la_data_in[74] la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79]
+*+ la_data_in[7] la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84]
+*+ la_data_in[85] la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8]
+*+ la_data_in[90] la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95]
+*+ la_data_in[96] la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0]
+*+ la_data_out[100] la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104]
+*+ la_data_out[105] la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109]
+*+ la_data_out[10] la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113]
+*+ la_data_out[114] la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118]
+*+ la_data_out[119] la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122]
+*+ la_data_out[123] la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127]
+*+ la_data_out[12] la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16]
+*+ la_data_out[17] la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21]
+*+ la_data_out[22] la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26]
+*+ la_data_out[27] la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31]
+*+ la_data_out[32] la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36]
+*+ la_data_out[37] la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41]
+*+ la_data_out[42] la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46]
+*+ la_data_out[47] la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51]
+*+ la_data_out[52] la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56]
+*+ la_data_out[57] la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61]
+*+ la_data_out[62] la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66]
+*+ la_data_out[67] la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71]
+*+ la_data_out[72] la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76]
+*+ la_data_out[77] la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81]
+*+ la_data_out[82] la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86]
+*+ la_data_out[87] la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91]
+*+ la_data_out[92] la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96]
+*+ la_data_out[97] la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100]
+*+ la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107]
+*+ la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113]
+*+ la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11]
+*+ la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126]
+*+ la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17]
+*+ la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23]
+*+ la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2]
+*+ la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36]
+*+ la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42]
+*+ la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49]
+*+ la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55]
+*+ la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61]
+*+ la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68]
+*+ la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74]
+*+ la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80]
+*+ la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87]
+*+ la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93]
+*+ la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9]
+*+ user_clock2 user_irq[0] user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2
+*+ vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11]
+*+ wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17]
+*+ wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22]
+*+ wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28]
+*+ wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4]
+*+ wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0]
+*+ wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15]
+*+ wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20]
+*+ wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26]
+*+ wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31]
+*+ wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9]
+*+ wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14]
+*+ wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1]
+*+ wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25]
+*+ wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
+*+ wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
+*+ wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+Xres_amp_top_0 bias_0/iref_9 bias_0/iref_8 vssa1 bias_0/iref_6 bias_0/iref_7 bias_0/iref_5
++ vdda1 io_analog[6] gpio_noesd[4] gpio_noesd[5] gpio_noesd[6] gpio_noesd[3] gpio_noesd[2]
++ io_analog[2] io_analog[0] gpio_noesd[1] io_analog[1] io_analog[3] io_analog[4] res_amp_top
+Xtop_pll_v1_0 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_2 io_analog[9]
++ top_pll_v1
+Xtop_pll_v1_1 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_0 io_analog[7]
++ top_pll_v1
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xbias_0 vssa1 vdda1 bias_0/iref_0 bias_0/iref_1 bias_0/iref_2 bias_0/iref_5 bias_0/iref_6
++ bias_0/iref_7 bias_0/iref_8 bias_0/iref_9 io_analog[5] bias
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xmimcap_decoup_1x5_0[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_0[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_0[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xmimcap_decoup_1x5_2[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_2[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_2[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xtop_pll_v2_0 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_1 gpio_noesd[8]
++ io_analog[8] top_pll_v2
+.end
+
diff --git a/mag/extractions/user_analog_project_wrapper_lvs_backup.spice b/mag/extractions/user_analog_project_wrapper_lvs_backup.spice
new file mode 100644
index 0000000..cf6e276
--- /dev/null
+++ b/mag/extractions/user_analog_project_wrapper_lvs_backup.spice
@@ -0,0 +1,1785 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x1 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+.ends
+
+.subckt clock_inverter vss CLK vdd CLK_d nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
+Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt latch_diff nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+.ends
+
+.subckt DFlipFlop vss nQ Q D vdd CLK nCLK
+Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
++ latch_diff
+Xlatch_diff_1 nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D latch_diff
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x4 vdd in vss out
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BDRUME VSUBS a_351_n84# a_n513_n84# a_639_n84# a_159_n84#
++ a_n321_n84# a_447_n84# a_n753_n181# a_n609_n84# w_n935_n303# a_n129_n84# a_735_n84#
++ a_255_n84# a_n417_n84# a_63_n84# a_543_n84# a_n705_n84# a_n225_n84# a_n797_n84#
++ a_n33_n84#
+X0 a_n705_n84# a_n753_n181# a_n797_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n513_n84# a_n753_n181# a_n609_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n417_n84# a_n753_n181# a_n513_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_n321_n84# a_n753_n181# a_n417_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X4 a_n225_n84# a_n753_n181# a_n321_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 a_n129_n84# a_n753_n181# a_n225_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X6 a_n609_n84# a_n753_n181# a_n705_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_63_n84# a_n753_n181# a_n33_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X8 a_n33_n84# a_n753_n181# a_n129_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X9 a_159_n84# a_n753_n181# a_63_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X10 a_255_n84# a_n753_n181# a_159_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X11 a_351_n84# a_n753_n181# a_255_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X12 a_543_n84# a_n753_n181# a_447_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X13 a_447_n84# a_n753_n181# a_351_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X14 a_639_n84# a_n753_n181# a_543_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X15 a_735_n84# a_n753_n181# a_639_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_QQE8KM a_543_n42# a_n705_n42# a_n225_n42# a_n797_n42#
++ a_n33_n42# a_351_n42# a_n513_n42# a_639_n42# a_159_n42# w_n935_n252# a_n757_64#
++ a_n321_n42# a_447_n42# a_n609_n42# a_n129_n42# a_735_n42# a_255_n42# a_n417_n42#
++ a_63_n42#
+X0 a_63_n42# a_n757_64# a_n33_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n757_64# a_n129_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_351_n42# a_n757_64# a_255_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_159_n42# a_n757_64# a_63_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X4 a_255_n42# a_n757_64# a_159_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 a_447_n42# a_n757_64# a_351_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X6 a_543_n42# a_n757_64# a_447_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X7 a_735_n42# a_n757_64# a_639_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X8 a_639_n42# a_n757_64# a_543_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X9 a_n321_n42# a_n757_64# a_n417_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_n705_n42# a_n757_64# a_n797_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 a_n513_n42# a_n757_64# a_n609_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X12 a_n417_n42# a_n757_64# a_n513_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X13 a_n225_n42# a_n757_64# a_n321_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 a_n129_n42# a_n757_64# a_n225_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X15 a_n609_n42# a_n757_64# a_n705_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x16 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_BDRUME_0 vss out vdd vdd out vdd vdd in out vdd vdd out vdd
++ out vdd out vdd out out out sky130_fd_pr__pfet_01v8_BDRUME
+Xsky130_fd_pr__nfet_01v8_QQE8KM_0 out vss out out out out vss vss out vss in vss vss
++ out vss out vss out vss sky130_fd_pr__nfet_01v8_QQE8KM
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_75PKJG VSUBS a_n33_n102# w_n359_n321# a_n177_n199#
++ a_63_n102# a_n129_n102# a_n221_n102# a_25_n199# a_159_n102#
+X0 a_159_n102# a_25_n199# a_63_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_25_n199# a_n33_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X2 a_n129_n102# a_n177_n199# a_n221_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X3 a_n33_n102# a_n177_n199# a_n129_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XRJ78J a_n33_n102# w_n263_n312# a_63_n102# a_n125_n102#
++ a_n81_124#
+X0 a_n33_n102# a_n81_124# a_n125_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_n81_124# a_n33_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+.ends
+
+.subckt nand_logic avss1p8 in1 avdd1p8 in2 out
+Xsky130_fd_pr__pfet_01v8_75PKJG_0 avss1p8 avdd1p8 avdd1p8 in1 out out avdd1p8 in2
++ avdd1p8 sky130_fd_pr__pfet_01v8_75PKJG
+Xsky130_fd_pr__nfet_01v8_XRJ78J_0 m1_21_n341# avss1p8 avss1p8 avss1p8 in1 sky130_fd_pr__nfet_01v8_XRJ78J
+Xsky130_fd_pr__nfet_01v8_XRJ78J_1 out avss1p8 m1_21_n341# m1_21_n341# in2 sky130_fd_pr__nfet_01v8_XRJ78J
+.ends
+
+.subckt res_amp_sync_v2 vss avdd1p8 clk_amp clkn clkp rst
+XDFlipFlop_0 vss DFlipFlop_0/nQ DFlipFlop_0/Q DFlipFlop_3/D avdd1p8 clkp clkn DFlipFlop
+XDFlipFlop_1 vss DFlipFlop_1/nQ DFlipFlop_2/D DFlipFlop_1/D avdd1p8 DFlipFlop_3/D
++ DFlipFlop_0/Q DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ DFlipFlop_2/Q DFlipFlop_2/D avdd1p8 clkp clkn DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ DFlipFlop_3/Q DFlipFlop_3/D avdd1p8 clkp clkn DFlipFlop
+Xinverter_min_x4_0 avdd1p8 DFlipFlop_0/Q vss DFlipFlop_3/D inverter_min_x4
+Xinverter_min_x4_1 avdd1p8 nand_logic_0/out vss DFlipFlop_4/D inverter_min_x4
+XDFlipFlop_4 vss DFlipFlop_4/nQ DFlipFlop_4/Q DFlipFlop_4/D avdd1p8 clkp clkn DFlipFlop
+Xinverter_min_x4_2 avdd1p8 DFlipFlop_2/D vss DFlipFlop_1/D inverter_min_x4
+Xinverter_min_x4_3 avdd1p8 nand_logic_1/out vss rst inverter_min_x4
+Xinverter_min_x4_4 avdd1p8 DFlipFlop_4/Q vss inverter_min_x4_4/out inverter_min_x4
+Xinverter_min_x16_0 inverter_min_x4_4/out clk_amp vss avdd1p8 inverter_min_x16
+Xnand_logic_0 vss DFlipFlop_2/Q avdd1p8 DFlipFlop_3/Q nand_logic_0/out nand_logic
+Xnand_logic_1 vss DFlipFlop_4/D avdd1p8 clkp nand_logic_1/out nand_logic
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_4L9VGG VSUBS a_291_n200# w_n487_n419# a_35_n200#
++ a_n291_n238# a_n93_n200# a_163_n200# a_n349_n200# a_n221_n200#
+X0 a_291_n200# a_n291_n238# a_163_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_n221_n200# a_n291_n238# a_n349_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_35_n200# a_n291_n238# a_n93_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_163_n200# a_n291_n238# a_35_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_n93_n200# a_n291_n238# a_n221_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_L78GGD a_n73_n73# w_n211_n221# a_15_n73# a_n33_33#
+X0 a_15_n73# a_n33_33# a_n73_n73# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_6RX2PQ VSUBS w_n211_n268# a_15_n48# a_n33_n145# a_n73_n48#
+X0 a_15_n48# a_n33_n145# a_n73_n48# w_n211_n268# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min vdd out in vss
+XXM1 vss vss out in sky130_fd_pr__nfet_01v8_L78GGD
+XXM2 vss vdd out in vdd sky130_fd_pr__pfet_01v8_6RX2PQ
+.ends
+
+.subckt buffer_no_inv_x05 VSUBS in avdd1p8 out
+Xinverter_min_1 avdd1p8 out inverter_min_1/in VSUBS inverter_min
+Xinverter_min_0 avdd1p8 inverter_min_1/in in VSUBS inverter_min
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XA7ZMQ VSUBS a_21_142# a_63_n111# a_n87_142# a_n125_n111#
++ w_n263_n330# a_n33_n111#
+X0 a_n33_n111# a_n87_142# a_n125_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+X1 a_63_n111# a_21_142# a_n33_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HAN8QX a_15_n142# a_n33_102# a_n73_n142# w_n211_n290#
+X0 a_15_n142# a_n33_102# a_n73_n142# w_n211_n290# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+.ends
+
+.subckt mux_2to1_logic sel avdd1p8 w_947_n633# avss1p8 out DinA DinB
+Xinverter_min_0 avdd1p8 sel_b sel avss1p8 inverter_min
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_0 avss1p8 sel DinA sel DinA avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_1 avss1p8 sel_b DinB sel_b DinB avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__nfet_01v8_HAN8QX_0 out sel_b DinA avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+Xsky130_fd_pr__nfet_01v8_HAN8QX_1 out sel DinB avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+.ends
+
+.subckt delay_cell_buff clk clk_out avss1p8 avdd1p8 reg0 reg2 reg1 mux_2to1_logic_5/w_947_n633#
+Xbuffer_no_inv_x05_8 avss1p8 mux_2to1_logic_3/DinA avdd1p8 buffer_no_inv_x05_9/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_9 avss1p8 buffer_no_inv_x05_9/in avdd1p8 mux_2to1_logic_3/DinB
++ buffer_no_inv_x05
+Xmux_2to1_logic_0 reg2 avdd1p8 mux_2to1_logic_0/w_947_n633# avss1p8 mux_2to1_logic_0/out
++ clk mux_2to1_logic_0/DinB mux_2to1_logic
+Xmux_2to1_logic_1 reg2 avdd1p8 mux_2to1_logic_1/w_947_n633# avss1p8 mux_2to1_logic_1/out
++ mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB mux_2to1_logic
+Xmux_2to1_logic_2 reg1 avdd1p8 mux_2to1_logic_2/w_947_n633# avss1p8 mux_2to1_logic_2/out
++ mux_2to1_logic_0/out mux_2to1_logic_1/out mux_2to1_logic
+Xmux_2to1_logic_3 reg2 avdd1p8 mux_2to1_logic_3/w_947_n633# avss1p8 mux_2to1_logic_3/out
++ mux_2to1_logic_3/DinA mux_2to1_logic_3/DinB mux_2to1_logic
+Xmux_2to1_logic_4 reg2 avdd1p8 mux_2to1_logic_4/w_947_n633# avss1p8 mux_2to1_logic_4/out
++ mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB mux_2to1_logic
+Xmux_2to1_logic_5 reg1 avdd1p8 mux_2to1_logic_5/w_947_n633# avss1p8 mux_2to1_logic_5/out
++ mux_2to1_logic_3/out mux_2to1_logic_4/out mux_2to1_logic
+Xmux_2to1_logic_6 reg0 avdd1p8 mux_2to1_logic_6/w_947_n633# avss1p8 nand_logic_0/in1
++ mux_2to1_logic_2/out mux_2to1_logic_5/out mux_2to1_logic
+Xbuffer_no_inv_x05_10 avss1p8 mux_2to1_logic_3/DinB avdd1p8 buffer_no_inv_x05_11/in
++ buffer_no_inv_x05
+Xnand_logic_0 avss1p8 nand_logic_0/in1 avdd1p8 clk clk_out nand_logic
+Xbuffer_no_inv_x05_11 avss1p8 buffer_no_inv_x05_11/in avdd1p8 mux_2to1_logic_4/DinA
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_12 avss1p8 mux_2to1_logic_4/DinA avdd1p8 buffer_no_inv_x05_13/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_13 avss1p8 buffer_no_inv_x05_13/in avdd1p8 mux_2to1_logic_4/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_0 avss1p8 clk avdd1p8 buffer_no_inv_x05_1/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_2 avss1p8 mux_2to1_logic_0/DinB avdd1p8 buffer_no_inv_x05_3/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_1 avss1p8 buffer_no_inv_x05_1/in avdd1p8 mux_2to1_logic_0/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_3 avss1p8 buffer_no_inv_x05_3/in avdd1p8 mux_2to1_logic_1/DinA
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_4 avss1p8 mux_2to1_logic_1/DinA avdd1p8 buffer_no_inv_x05_5/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_5 avss1p8 buffer_no_inv_x05_5/in avdd1p8 mux_2to1_logic_1/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_6 avss1p8 mux_2to1_logic_1/DinB avdd1p8 buffer_no_inv_x05_7/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_7 avss1p8 buffer_no_inv_x05_7/in avdd1p8 mux_2to1_logic_3/DinA
++ buffer_no_inv_x05
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_72JNYZ a_n81_n100# w_n311_n310# a_n128_122# a_111_n100#
++ a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n128_122# a_n81_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n81_n100# a_n128_122# a_n173_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n128_122# a_15_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XL9AN VSUBS w_n311_n319# a_n81_n100# a_111_n100#
++ a_n129_131# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_131# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_131# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_131# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XUYGK VSUBS a_n269_n100# a_n81_n100# w_n407_n319#
++ a_111_n100# a_n177_n100# a_15_n100# a_207_n100# a_n225_131#
+X0 a_207_n100# a_n225_131# a_111_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_131# a_n81_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n225_131# a_15_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n225_131# a_n177_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_131# a_n269_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_2AP43D a_15_n81# a_n33_41# w_n211_n229# a_n73_n81#
+X0 a_15_n81# a_n33_41# a_n73_n81# w_n211_n229# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt res_amp_lin clk vctrl avdd1p8 avss1p8 inn outn outp inp
+Xsky130_fd_pr__pfet_01v8_2XL9AN_0 avss1p8 avdd1p8 a_3747_261# a_3747_261# clk avdd1p8
++ avdd1p8 sky130_fd_pr__pfet_01v8_2XL9AN
+Xsky130_fd_pr__pfet_01v8_2XUYGK_0 avss1p8 a_3747_261# a_3747_261# avdd1p8 a_3747_261#
++ vp vp vp vctrl sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_1 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_0 avss1p8 clk avss1p8 outp sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_2 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_1 avss1p8 clk avss1p8 outn sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_3 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_4 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_5 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_6 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_7 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_8 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_595QY5 a_n269_n100# a_n81_n100# a_111_n100# a_n177_n100#
++ a_15_n100# w_n407_n310# a_207_n100# a_n225_n188#
+X0 a_207_n100# a_n225_n188# a_111_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_n188# a_n81_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n225_n188# a_n177_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_111_n100# a_n225_n188# a_15_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_n188# a_n269_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_9B2JY7 a_n317_n100# a_n33_n100# a_n225_n100# a_n271_122#
++ a_63_n100# a_n129_n100# w_n455_n310# a_255_n100# a_159_n100#
+X0 a_63_n100# a_n271_122# a_n33_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n271_122# a_n129_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n271_122# a_63_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n271_122# a_159_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n225_n100# a_n271_122# a_n317_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n129_n100# a_n271_122# a_n225_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_MVT43V a_n33_n100# w_n263_n310# a_63_n100# a_n79_122#
++ a_n125_n100#
+X0 a_63_n100# a_n79_122# a_n33_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n79_122# a_n125_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_NMSMYT a_n33_n100# a_n321_n100# a_n225_n100# w_n551_n310#
++ a_63_n100# a_n368_122# a_n129_n100# a_351_n100# a_255_n100# a_n413_n100# a_159_n100#
+X0 a_63_n100# a_n368_122# a_n33_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n368_122# a_n129_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n368_122# a_63_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n368_122# a_159_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_351_n100# a_n368_122# a_255_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n321_n100# a_n368_122# a_n413_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n225_n100# a_n368_122# a_n321_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n129_n100# a_n368_122# a_n225_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XAYTAL VSUBS w_n311_n319# a_n81_n100# a_n129_n197#
++ a_111_n100# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_n197# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_n197# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_n197# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_B2JNY3 a_n33_n100# a_63_n100# a_n221_n100# a_n129_n100#
++ w_n359_n310# a_n176_122# a_159_n100#
+X0 a_63_n100# a_n176_122# a_n33_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n176_122# a_n129_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n176_122# a_63_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n176_122# a_n221_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XACJHL VSUBS a_n81_n197# w_n263_n319# a_n33_n100#
++ a_63_n100# a_n125_n100#
+X0 a_63_n100# a_n81_n197# a_n33_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_n197# a_n125_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt iref_ctrl_res_amp vctrl avdd1p8 reg0 reg1 reg2 iref avss1p8
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 iref m1_n356_n363# m1_n356_n363# iref iref iref
++ avss1p8 iref m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_n356_n363# m1_n356_n363# avdd1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_0 m1_964_n363# avss1p8 vctrl iref vctrl sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_1 m1_964_n363# avss1p8 avss1p8 reg0 avss1p8 sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_0 vctrl m1_1996_n363# vctrl avss1p8 m1_1996_n363#
++ iref m1_1996_n363# vctrl m1_1996_n363# vctrl vctrl sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_1 avss1p8 m1_1996_n363# avss1p8 avss1p8 m1_1996_n363#
++ reg2 m1_1996_n363# avss1p8 m1_1996_n363# avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 m1_448_n363# avss1p8 iref m1_448_n363# vctrl
++ vctrl sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 m1_448_n363# avss1p8 avdd1p8 m1_448_n363# avss1p8
++ avss1p8 sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__pfet_01v8_XAYTAL_0 avss1p8 avdd1p8 m1_511_801# avss1p8 m1_511_801#
++ avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8_XAYTAL
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_0 vctrl m1_1384_n363# vctrl m1_1384_n363# avss1p8
++ iref vctrl sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_1 avss1p8 m1_1384_n363# avss1p8 m1_1384_n363#
++ avss1p8 reg1 avss1p8 sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__pfet_01v8_XACJHL_0 avss1p8 vctrl avdd1p8 m1_511_801# vctrl vctrl sky130_fd_pr__pfet_01v8_XACJHL
+.ends
+
+.subckt res_amp_lin_prog avdd1p8 delay_reg2 clk avss1p8 outp_cap iref_reg0 iref_reg1
++ iref_reg2 iref delay_reg0 inn outn_cap inp delay_reg1 rst
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_0 avss1p8 outn_cap avdd1p8 outn_cap res_amp_lin_0/clk
++ outn outn outn outn_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_1 avss1p8 outp_cap avdd1p8 outp_cap res_amp_lin_0/clk
++ outp outp outp outp_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xdelay_cell_buff_0 clk res_amp_lin_0/clk avss1p8 avdd1p8 delay_reg0 delay_reg2 delay_reg1
++ avss1p8 delay_cell_buff
+Xinverter_min_x4_0 avdd1p8 res_amp_lin_0/clk avss1p8 inverter_min_x4_0/out inverter_min_x4
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 outn_cap avss1p8 rst outn_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xres_amp_lin_0 res_amp_lin_0/clk res_amp_lin_0/vctrl avdd1p8 avss1p8 inn outn outp
++ inp res_amp_lin
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 outp_cap avss1p8 rst outp_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_0 outn outn outn outn_cap outn_cap avss1p8 outn_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_1 outp outp outp outp_cap outp_cap avss1p8 outp_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xiref_ctrl_res_amp_0 res_amp_lin_0/vctrl avdd1p8 iref_reg0 iref_reg1 iref_reg2 iref
++ avss1p8 iref_ctrl_res_amp
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_D3F744 VSUBS a_n285_n236# a_355_n236# a_n29_n236#
++ a_n413_n236# a_99_n236# a_n611_n262# a_483_n236# a_n669_n236# w_n807_n384# a_n157_n236#
++ a_n541_n236# a_227_n236# a_611_n236#
+X0 a_n157_n236# a_n611_n262# a_n285_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_611_n236# a_n611_n262# a_483_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_227_n236# a_n611_n262# a_99_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_n285_n236# a_n611_n262# a_n413_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_99_n236# a_n611_n262# a_n29_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X5 a_355_n236# a_n611_n262# a_227_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X6 a_483_n236# a_n611_n262# a_355_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X7 a_n29_n236# a_n611_n262# a_n157_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X8 a_n413_n236# a_n611_n262# a_n541_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X9 a_n541_n236# a_n611_n262# a_n669_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_VCU74W VSUBS a_495_n100# a_n81_n100# a_399_n100# a_687_n100#
++ a_n749_n100# a_n273_n100# a_111_n100# a_n177_n100# a_n561_n100# a_15_n100# a_n465_n100#
++ a_n705_n197# a_303_n100# a_n369_n100# w_n887_n319# a_207_n100# a_n657_n100# a_591_n100#
+X0 a_303_n100# a_n705_n197# a_207_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_591_n100# a_n705_n197# a_495_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_207_n100# a_n705_n197# a_111_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_399_n100# a_n705_n197# a_303_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_495_n100# a_n705_n197# a_399_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_687_n100# a_n705_n197# a_591_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n561_n100# a_n705_n197# a_n657_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n465_n100# a_n705_n197# a_n561_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n657_n100# a_n705_n197# a_n749_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n369_n100# a_n705_n197# a_n465_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_15_n100# a_n705_n197# a_n81_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_111_n100# a_n705_n197# a_15_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n273_n100# a_n705_n197# a_n369_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n81_n100# a_n705_n197# a_n177_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n177_n100# a_n705_n197# a_n273_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt source_follower_buff_pmos in avdd1p8 out iref avss1p8
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 avss1p8 iref iref iref avss1p8 avss1p8 avss1p8
++ avss1p8 iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_957_828# m1_957_828# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_957_828# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__pfet_01v8_lvt_D3F744_0 avss1p8 out avss1p8 out avss1p8 avss1p8 in out
++ avss1p8 avdd1p8 avss1p8 out out avss1p8 sky130_fd_pr__pfet_01v8_lvt_D3F744
+Xsky130_fd_pr__pfet_01v8_VCU74W_0 avss1p8 m1_957_828# m1_957_828# avdd1p8 m1_957_828#
++ avdd1p8 m1_957_828# m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# m1_957_828#
++ m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+Xsky130_fd_pr__pfet_01v8_VCU74W_1 avss1p8 out out avdd1p8 out avdd1p8 out out avdd1p8
++ avdd1p8 avdd1p8 out m1_957_828# out avdd1p8 avdd1p8 avdd1p8 out avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CFLRKA a_n993_109# a_n1473_n309# a_63_n309# a_1215_n309#
++ a_1215_109# a_n129_n309# a_735_109# a_1599_109# a_n513_n309# a_255_109# a_n1377_n309#
++ a_n1949_109# a_n1761_n309# a_1119_n309# a_1503_n309# a_n1761_109# a_n417_109# a_n417_n309#
++ a_n1281_109# a_n801_n309# a_351_n309# a_63_109# a_1503_109# a_n1665_n309# a_1023_109#
++ a_1887_109# a_1407_n309# a_543_109# a_n705_n309# a_255_n309# a_1791_n309# a_n1569_109#
++ a_n705_109# a_n1569_n309# a_n1089_109# w_n2087_n519# a_n225_109# a_n609_n309# a_159_n309#
++ a_543_n309# a_1695_n309# a_1311_109# a_831_109# a_1695_109# a_n1857_n309# a_n993_n309#
++ a_n33_109# a_351_109# a_n1857_109# a_447_n309# a_831_n309# a_1599_n309# a_n1377_109#
++ a_n897_n309# a_n897_109# a_n513_109# a_1119_109# a_639_109# a_n33_n309# a_735_n309#
++ a_1887_n309# a_159_109# a_n1665_109# a_n1281_n309# a_1023_n309# a_n1185_109# a_n801_109#
++ a_639_n309# a_n321_109# a_1407_109# a_n321_n309# a_927_109# a_447_109# a_1791_109#
++ a_n1185_n309# a_1311_n309# a_n1905_n87# a_927_n309# a_n609_109# a_n225_n309# a_n1473_109#
++ a_n129_109# a_n1949_n309# a_n1089_n309#
+X0 a_n1569_n309# a_n1905_n87# a_n1665_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n87# a_n993_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_927_n309# a_n1905_n87# a_831_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1023_109# a_n1905_n87# a_927_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_255_n309# a_n1905_n87# a_159_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n87# a_1119_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_927_109# a_n1905_n87# a_831_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n1857_n309# a_n1905_n87# a_n1949_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n321_n309# a_n1905_n87# a_n417_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n1761_109# a_n1905_n87# a_n1857_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_543_n309# a_n1905_n87# a_447_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_1503_n309# a_n1905_n87# a_1407_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n1857_109# a_n1905_n87# a_n1949_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n1665_109# a_n1905_n87# a_n1761_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1569_109# a_n1905_n87# a_n1665_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1215_109# a_n1905_n87# a_1119_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_1311_109# a_n1905_n87# a_1215_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_1503_109# a_n1905_n87# a_1407_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_1791_109# a_n1905_n87# a_1695_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n87# a_n1281_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_1119_109# a_n1905_n87# a_1023_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1407_109# a_n1905_n87# a_1311_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_1599_109# a_n1905_n87# a_1503_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1695_109# a_n1905_n87# a_1599_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1887_109# a_n1905_n87# a_1791_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_n1473_n309# a_n1905_n87# a_n1569_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_831_n309# a_n1905_n87# a_735_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1791_n309# a_n1905_n87# a_1695_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n33_109# a_n1905_n87# a_n129_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_351_109# a_n1905_n87# a_255_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_159_n309# a_n1905_n87# a_63_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1119_n309# a_n1905_n87# a_1023_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_159_109# a_n1905_n87# a_63_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_255_109# a_n1905_n87# a_159_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_447_109# a_n1905_n87# a_351_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_543_109# a_n1905_n87# a_447_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_735_109# a_n1905_n87# a_639_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_831_109# a_n1905_n87# a_735_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n225_n309# a_n1905_n87# a_n321_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_639_109# a_n1905_n87# a_543_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_447_n309# a_n1905_n87# a_351_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_1407_n309# a_n1905_n87# a_1311_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_n1473_109# a_n1905_n87# a_n1569_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_n1281_109# a_n1905_n87# a_n1377_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_n1185_109# a_n1905_n87# a_n1281_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_n993_109# a_n1905_n87# a_n1089_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_n1089_n309# a_n1905_n87# a_n1185_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n1377_109# a_n1905_n87# a_n1473_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n1089_109# a_n1905_n87# a_n1185_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_n321_109# a_n1905_n87# a_n417_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n513_n309# a_n1905_n87# a_n609_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_63_n309# a_n1905_n87# a_n33_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_n801_109# a_n1905_n87# a_n897_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_n705_109# a_n1905_n87# a_n801_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_n513_109# a_n1905_n87# a_n609_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_n417_109# a_n1905_n87# a_n513_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n225_109# a_n1905_n87# a_n321_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n129_109# a_n1905_n87# a_n225_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n1377_n309# a_n1905_n87# a_n1473_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_735_n309# a_n1905_n87# a_639_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_1695_n309# a_n1905_n87# a_1599_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n897_109# a_n1905_n87# a_n993_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n609_109# a_n1905_n87# a_n705_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n801_n309# a_n1905_n87# a_n897_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n129_n309# a_n1905_n87# a_n225_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n1761_n309# a_n1905_n87# a_n1857_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n417_n309# a_n1905_n87# a_n513_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_109# a_n1905_n87# a_n33_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_639_n309# a_n1905_n87# a_543_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_1599_n309# a_n1905_n87# a_1503_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n705_n309# a_n1905_n87# a_n801_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1887_n309# a_n1905_n87# a_1791_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n1665_n309# a_n1905_n87# a_n1761_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_1023_n309# a_n1905_n87# a_927_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n993_n309# a_n1905_n87# a_n1089_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_n33_n309# a_n1905_n87# a_n129_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_351_n309# a_n1905_n87# a_255_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_1311_n309# a_n1905_n87# a_1215_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n1281_n309# a_n1905_n87# a_n1377_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_n609_n309# a_n1905_n87# a_n705_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CAF2P9 a_63_n309# a_n1473_n309# a_159_527# a_1215_n309#
++ a_n993_109# a_1215_109# a_n129_n309# a_n513_n309# a_1599_109# a_735_109# a_n1665_527#
++ a_n1281_n727# a_n801_527# a_1023_n727# a_639_n727# a_255_109# a_n1185_527# a_n1377_n309#
++ a_n1949_109# a_1119_n309# a_n1761_n309# a_n321_527# a_1503_n309# a_1407_527# a_n321_n727#
++ a_927_527# a_n1761_109# a_n417_109# a_n417_n309# a_351_n309# a_n801_n309# a_n1905_n505#
++ a_n1281_109# a_n1185_n727# a_447_527# a_1791_527# a_63_109# a_1311_n727# a_927_n727#
++ a_1503_109# a_n1665_n309# a_1407_n309# a_1887_109# a_n225_n727# a_1023_109# a_n609_527#
++ a_543_109# a_255_n309# a_n1473_527# a_n1949_n727# a_1791_n309# a_n705_n309# a_n129_527#
++ a_n1089_n727# a_n1473_n727# a_1215_n727# a_63_n727# a_n993_527# a_n1569_109# a_n1569_n309#
++ a_n705_109# a_1215_527# a_n129_n727# a_n1089_109# a_1599_527# a_n513_n727# a_735_527#
++ a_n225_109# a_1695_n309# a_159_n309# a_n609_n309# a_543_n309# a_255_527# a_n1377_n727#
++ a_n1949_527# a_1119_n727# a_n1761_n727# a_1503_n727# a_1311_109# a_n993_n309# a_1695_109#
++ a_n1857_n309# a_831_109# a_n1761_527# a_n33_109# a_n417_n727# a_n417_527# a_351_109#
++ a_351_n727# a_n801_n727# a_n1281_527# a_n1857_109# a_1599_n309# a_447_n309# a_63_527#
++ a_831_n309# a_1503_527# a_n1377_109# a_n1665_n727# a_1887_527# a_1407_n727# a_n897_n309#
++ a_1023_527# a_n513_109# a_n897_109# a_543_527# a_1791_n727# a_255_n727# a_n705_n727#
++ a_1119_109# a_1887_n309# a_639_109# a_735_n309# a_n33_n309# a_n1569_527# a_n1569_n727#
++ a_n705_527# a_159_109# a_n1089_527# a_n225_527# w_n2087_n937# a_1695_n727# a_159_n727#
++ a_n609_n727# a_543_n727# a_n1665_109# a_n1281_n309# a_1023_n309# a_1311_527# a_n801_109#
++ a_639_n309# a_1695_527# a_n1185_109# a_n993_n727# a_831_527# a_n1857_n727# a_n321_109#
++ a_1407_109# a_n33_527# a_n321_n309# a_351_527# a_927_109# a_1599_n727# a_n1857_527#
++ a_447_n727# a_831_n727# a_447_109# a_n1185_n309# a_n1377_527# a_1791_109# a_1311_n309#
++ a_n897_n727# a_927_n309# a_n513_527# a_n897_527# a_n225_n309# a_n609_109# a_1119_527#
++ a_1887_n727# a_n1949_n309# a_639_527# a_n1473_109# a_n129_109# a_735_n727# a_n33_n727#
++ a_n1089_n309#
+X0 a_927_n309# a_n1905_n505# a_831_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n505# a_n993_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n1569_n309# a_n1905_n505# a_n1665_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n727# a_n1905_n505# a_n225_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n1761_n727# a_n1905_n505# a_n1857_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n505# a_1119_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_255_n309# a_n1905_n505# a_159_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1023_109# a_n1905_n505# a_927_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n1857_n309# a_n1905_n505# a_n1949_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_927_109# a_n1905_n505# a_831_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_n417_n727# a_n1905_n505# a_n513_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_n321_n309# a_n1905_n505# a_n417_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_1599_n727# a_n1905_n505# a_1503_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_63_527# a_n1905_n505# a_n33_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1761_109# a_n1905_n505# a_n1857_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1503_n309# a_n1905_n505# a_1407_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_639_n727# a_n1905_n505# a_543_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_543_n309# a_n1905_n505# a_447_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_n1665_109# a_n1905_n505# a_n1761_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n505# a_n1281_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_n1569_109# a_n1905_n505# a_n1665_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1311_109# a_n1905_n505# a_1215_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1857_109# a_n1905_n505# a_n1949_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1791_109# a_n1905_n505# a_1695_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1503_109# a_n1905_n505# a_1407_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_1215_109# a_n1905_n505# a_1119_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_n705_n727# a_n1905_n505# a_n801_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1119_109# a_n1905_n505# a_1023_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_1695_109# a_n1905_n505# a_1599_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_1407_109# a_n1905_n505# a_1311_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_1599_109# a_n1905_n505# a_1503_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1887_109# a_n1905_n505# a_1791_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_1887_n727# a_n1905_n505# a_1791_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_1791_n309# a_n1905_n505# a_1695_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_831_n309# a_n1905_n505# a_735_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_n1473_n309# a_n1905_n505# a_n1569_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_n33_109# a_n1905_n505# a_n129_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_1023_n727# a_n1905_n505# a_927_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n1665_n727# a_n1905_n505# a_n1761_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_1119_n309# a_n1905_n505# a_1023_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_159_n309# a_n1905_n505# a_63_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_351_109# a_n1905_n505# a_255_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_1311_n727# a_n1905_n505# a_1215_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_255_109# a_n1905_n505# a_159_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_351_n727# a_n1905_n505# a_255_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_831_109# a_n1905_n505# a_735_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_543_109# a_n1905_n505# a_447_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n33_n727# a_n1905_n505# a_n129_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n993_n727# a_n1905_n505# a_n1089_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_159_109# a_n1905_n505# a_63_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n225_n309# a_n1905_n505# a_n321_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_735_109# a_n1905_n505# a_639_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_447_109# a_n1905_n505# a_351_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_639_109# a_n1905_n505# a_543_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_1407_n309# a_n1905_n505# a_1311_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_447_n309# a_n1905_n505# a_351_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n1089_n309# a_n1905_n505# a_n1185_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n1281_109# a_n1905_n505# a_n1377_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n993_109# a_n1905_n505# a_n1089_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_n1473_109# a_n1905_n505# a_n1569_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_n1185_109# a_n1905_n505# a_n1281_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n609_n727# a_n1905_n505# a_n705_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n1377_109# a_n1905_n505# a_n1473_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n1089_109# a_n1905_n505# a_n1185_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n1281_n727# a_n1905_n505# a_n1377_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n513_n309# a_n1905_n505# a_n609_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n321_109# a_n1905_n505# a_n417_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_n309# a_n1905_n505# a_n33_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_n225_109# a_n1905_n505# a_n321_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_n801_109# a_n1905_n505# a_n897_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n513_109# a_n1905_n505# a_n609_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1695_n309# a_n1905_n505# a_1599_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n705_109# a_n1905_n505# a_n801_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_n417_109# a_n1905_n505# a_n513_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n129_109# a_n1905_n505# a_n225_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_735_n309# a_n1905_n505# a_639_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_n1377_n309# a_n1905_n505# a_n1473_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_n897_109# a_n1905_n505# a_n993_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n609_109# a_n1905_n505# a_n705_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_927_n727# a_n1905_n505# a_831_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X80 a_n1569_n727# a_n1905_n505# a_n1665_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X81 a_n897_n727# a_n1905_n505# a_n993_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X82 a_n801_n309# a_n1905_n505# a_n897_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X83 a_1215_n727# a_n1905_n505# a_1119_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X84 a_255_n727# a_n1905_n505# a_159_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X85 a_1023_527# a_n1905_n505# a_927_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X86 a_n129_n309# a_n1905_n505# a_n225_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X87 a_927_527# a_n1905_n505# a_831_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X88 a_n1857_n727# a_n1905_n505# a_n1949_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X89 a_n1761_n309# a_n1905_n505# a_n1857_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X90 a_n321_n727# a_n1905_n505# a_n417_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X91 a_n1761_527# a_n1905_n505# a_n1857_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X92 a_1503_n727# a_n1905_n505# a_1407_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X93 a_n1665_527# a_n1905_n505# a_n1761_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X94 a_543_n727# a_n1905_n505# a_447_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X95 a_n1185_n727# a_n1905_n505# a_n1281_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X96 a_n417_n309# a_n1905_n505# a_n513_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X97 a_n1857_527# a_n1905_n505# a_n1949_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X98 a_n1569_527# a_n1905_n505# a_n1665_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X99 a_1311_527# a_n1905_n505# a_1215_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X100 a_1215_527# a_n1905_n505# a_1119_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X101 a_1503_527# a_n1905_n505# a_1407_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X102 a_1791_527# a_n1905_n505# a_1695_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X103 a_1119_527# a_n1905_n505# a_1023_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X104 a_1407_527# a_n1905_n505# a_1311_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X105 a_1695_527# a_n1905_n505# a_1599_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X106 a_1599_n309# a_n1905_n505# a_1503_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X107 a_63_109# a_n1905_n505# a_n33_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X108 a_639_n309# a_n1905_n505# a_543_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X109 a_1599_527# a_n1905_n505# a_1503_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X110 a_1887_527# a_n1905_n505# a_1791_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X111 a_1791_n727# a_n1905_n505# a_1695_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X112 a_831_n727# a_n1905_n505# a_735_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X113 a_n1473_n727# a_n1905_n505# a_n1569_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X114 a_n705_n309# a_n1905_n505# a_n801_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X115 a_n33_527# a_n1905_n505# a_n129_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X116 a_1887_n309# a_n1905_n505# a_1791_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X117 a_1119_n727# a_n1905_n505# a_1023_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X118 a_159_n727# a_n1905_n505# a_63_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X119 a_351_527# a_n1905_n505# a_255_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X120 a_1023_n309# a_n1905_n505# a_927_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X121 a_n1665_n309# a_n1905_n505# a_n1761_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X122 a_255_527# a_n1905_n505# a_159_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X123 a_543_527# a_n1905_n505# a_447_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X124 a_831_527# a_n1905_n505# a_735_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X125 a_159_527# a_n1905_n505# a_63_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X126 a_447_527# a_n1905_n505# a_351_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X127 a_n225_n727# a_n1905_n505# a_n321_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X128 a_735_527# a_n1905_n505# a_639_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X129 a_639_527# a_n1905_n505# a_543_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X130 a_1407_n727# a_n1905_n505# a_1311_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X131 a_447_n727# a_n1905_n505# a_351_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X132 a_1311_n309# a_n1905_n505# a_1215_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X133 a_n1089_n727# a_n1905_n505# a_n1185_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X134 a_351_n309# a_n1905_n505# a_255_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X135 a_n33_n309# a_n1905_n505# a_n129_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X136 a_n1281_527# a_n1905_n505# a_n1377_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X137 a_n993_527# a_n1905_n505# a_n1089_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X138 a_n993_n309# a_n1905_n505# a_n1089_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X139 a_n1473_527# a_n1905_n505# a_n1569_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X140 a_n1185_527# a_n1905_n505# a_n1281_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X141 a_n1377_527# a_n1905_n505# a_n1473_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X142 a_n1089_527# a_n1905_n505# a_n1185_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X143 a_n513_n727# a_n1905_n505# a_n609_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X144 a_n321_527# a_n1905_n505# a_n417_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X145 a_63_n727# a_n1905_n505# a_n33_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X146 a_n801_527# a_n1905_n505# a_n897_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X147 a_n513_527# a_n1905_n505# a_n609_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X148 a_n225_527# a_n1905_n505# a_n321_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X149 a_1695_n727# a_n1905_n505# a_1599_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X150 a_735_n727# a_n1905_n505# a_639_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X151 a_n705_527# a_n1905_n505# a_n801_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X152 a_n417_527# a_n1905_n505# a_n513_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X153 a_n129_527# a_n1905_n505# a_n225_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X154 a_n1377_n727# a_n1905_n505# a_n1473_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X155 a_n609_n309# a_n1905_n505# a_n705_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X156 a_n1281_n309# a_n1905_n505# a_n1377_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X157 a_n897_527# a_n1905_n505# a_n993_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X158 a_n609_527# a_n1905_n505# a_n705_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X159 a_n801_n727# a_n1905_n505# a_n897_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt source_follower_buff_nmos in avdd1p8 avss1p8 out iref
+Xsky130_fd_pr__nfet_01v8_lvt_CFLRKA_0 avdd1p8 out out out out out avdd1p8 out out
++ out avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8
++ avdd1p8 out avdd1p8 out out avdd1p8 out avdd1p8 out out out avdd1p8 out avdd1p8
++ out avss1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8 out avdd1p8
++ avdd1p8 avdd1p8 out out out out avdd1p8 out out out avdd1p8 out avdd1p8 avdd1p8
++ avdd1p8 avdd1p8 out out out avdd1p8 avdd1p8 out out out out avdd1p8 out out avdd1p8
++ avdd1p8 in avdd1p8 avdd1p8 avdd1p8 out out avdd1p8 out sky130_fd_pr__nfet_01v8_lvt_CFLRKA
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 m1_460_n1129# iref iref iref m1_460_n1129# m1_460_n1129#
++ avss1p8 m1_460_n1129# iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_460_n1129# m1_460_n1129# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_460_n1129# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_CAF2P9_0 out out avss1p8 out avss1p8 out out out out
++ avss1p8 out out avss1p8 out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out
++ avss1p8 out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 iref out avss1p8
++ out out out avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 out avss1p8 avss1p8
++ out out avss1p8 out out out out out out out avss1p8 avss1p8 avss1p8 out out out
++ out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out out out out avss1p8 avss1p8 out avss1p8
++ out out out out out avss1p8 out out out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8
++ avss1p8 out avss1p8 out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out
++ out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8 out out out out avss1p8 out avss1p8
++ avss1p8 out out out out out avss1p8 avss1p8 out avss1p8 out avss1p8 out out avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out avss1p8 avss1p8 out sky130_fd_pr__nfet_01v8_lvt_CAF2P9
+.ends
+
+.subckt source_follower_buff_diff VSUBS avdd1p8 iref1 iref2 iref3 iref4 inn outn inp
++ outp
+Xsource_follower_buff_pmos_0 inn avdd1p8 source_follower_buff_nmos_0/in iref3 VSUBS
++ source_follower_buff_pmos
+Xsource_follower_buff_pmos_1 inp avdd1p8 source_follower_buff_nmos_1/in iref1 VSUBS
++ source_follower_buff_pmos
+Xsource_follower_buff_nmos_0 source_follower_buff_nmos_0/in avdd1p8 VSUBS outn iref4
++ source_follower_buff_nmos
+Xsource_follower_buff_nmos_1 source_follower_buff_nmos_1/in avdd1p8 VSUBS outp iref2
++ source_follower_buff_nmos
+.ends
+
+.subckt res_amp_top iref0 iref1 avss1p8 iref2 iref3 iref4 avdd1p8 res_amp_sync_v2_0/clkp
++ iref_reg0 iref_reg1 iref_reg2 delay_reg0 delay_reg1 inn outn delay_reg2 outp inp
++ clkn
+Xres_amp_sync_v2_0 avss1p8 avdd1p8 res_amp_lin_prog_0/clk clkn res_amp_sync_v2_0/clkp
++ res_amp_sync_v2_0/rst res_amp_sync_v2
+Xres_amp_lin_prog_0 avdd1p8 delay_reg2 res_amp_lin_prog_0/clk avss1p8 res_amp_lin_prog_0/outp_cap
++ iref_reg0 iref_reg1 iref_reg2 iref0 delay_reg0 inn res_amp_lin_prog_0/outn_cap inp
++ delay_reg1 res_amp_sync_v2_0/rst res_amp_lin_prog
+Xsource_follower_buff_diff_0 avss1p8 avdd1p8 iref1 iref2 iref3 iref4 res_amp_lin_prog_0/outn_cap
++ outn res_amp_lin_prog_0/outp_cap outp source_follower_buff_diff
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt charge_pump Down out iref pswitch nDown biasp Up nswitch vss vdd nUp
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+.ends
+
+.subckt div_by_2 vss vdd CLK_2 nCLK_2 o1 CLK out_div o2 nout_div
+XDFlipFlop_0 vss nout_div out_div nout_div vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK DFlipFlop
+Xinverter_min_x4_1 vdd o2 vss nCLK_2 inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss CLK_2 inverter_min_x4
+Xclock_inverter_0 vss CLK vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+.ends
+
+.subckt buffer_salida in out vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+*C1 t VSUBS 0.42fF
+*C2 b VSUBS 0.09fF
+.ends
+
+
+.subckt csvco_branch vctrl in vbp D0 out vss vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+.ends
+
+.subckt ring_osc vctrl vdd vss D0 out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp D0 csvco_branch_1/in vss vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp D0 out_vco vss vdd csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp D0 csvco_branch_2/in vss
++ vdd csvco_branch
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_1 vdd out_div vss out_pad inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss out_div inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt div_by_5 nCLK vss vdd Q0 CLK nQ0 CLK_5 nQ2 Q1 Q1_shift
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 vss nQ2 DFlipFlop_0/Q DFlipFlop_0/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ Q1 DFlipFlop_2/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_1 vss nQ0 Q0 DFlipFlop_1/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ Q1_shift Q1 vdd nCLK CLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+.ends
+
+.subckt pfd_cp_interface vss vdd Down QA QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 QB vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS w_n359_n309# a_n63_n116# a_n159_n207#
++ a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt nor_pfd out vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss vdd B A out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+.ends
+
+.subckt dff_pfd vdd vss Q CLK Reset
+Xnor_pfd_0 nor_pfd_2/A vss vdd CLK Q nor_pfd
+Xnor_pfd_1 Q vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_3/A vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_2/B vss vdd nor_pfd_3/A Reset nor_pfd
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt and_pfd vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vdd vss Up A Reset dff_pfd
+Xdff_pfd_1 vdd vss Down B Reset dff_pfd
+Xand_pfd_0 vss Reset vdd Up Down and_pfd
+.ends
+
+.subckt top_pll_v1 vdd in_ref w_13905_n238# vss vco_D0 iref_cp out_to_pad
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
+Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss vco_D0 vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 n_out_by_2 vss vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2
++ div_5_Q1 div_5_Q1_shift div_by_5
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_2_2Y8F6P VSUBS c2_n3251_n3000# m4_n3351_n3100#
+X0 c2_n3251_n3000# m4_n3351_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_8P223X VSUBS a_n2017_n1317# a_n1731_n1219# a_n1879_n1219#
++ a_n2017_n61# w_n2018_n202#
+X0 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X1 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X2 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X3 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X4 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X5 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X6 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X7 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X8 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X9 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X10 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X11 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X12 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X13 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X14 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X15 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X16 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X17 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X18 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X19 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X20 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X21 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X22 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X23 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X24 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X25 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X26 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X27 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X28 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X29 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X30 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X31 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X32 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X33 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X34 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X35 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X36 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X37 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X38 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X39 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X40 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X41 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X42 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X43 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X44 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X45 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X46 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X47 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X48 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+.ends
+
+.subckt bias VSUBS vdd iref_0 iref_1 iref_2 iref_5 iref_6 iref_7 iref_8 iref_9 iref
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_5 VSUBS iref m1_20168_984# iref m1_20168_984#
++ vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_6 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219#
++ iref_5 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_7 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219#
++ iref_6 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_9 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219#
++ iref_8 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_8 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219#
++ iref_7 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_10 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219#
++ iref_9 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_0 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219#
++ iref_0 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_1 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219#
++ iref_1 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_2 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219#
++ iref_2 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_3 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219#
++ iref_3 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_4 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219#
++ iref_4 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+.ends
+
+.subckt mimcap_decoup_1x5 VSUBS t b
+Xdecap[0] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[1] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[2] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[3] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[4] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt top_pll_v2 vdd in_ref w_13905_n238# vss D0_vco iref_cp DO_cap out_to_pad
+Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss D0_vco vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 n_out_by_2 vss vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2
++ div_5_Q1 div_5_Q1_shift div_by_5
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+.ends
+
+*.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
+*+ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
+*+ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
+*+ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
+*+ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
+*+ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
+*+ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
+*+ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7]
+*+ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
+*+ io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
+*+ io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
+*+ io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9]
+*+ io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14]
+*+ io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1]
+*+ io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25]
+*+ io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7]
+*+ io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
+*+ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20]
+*+ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3]
+*+ io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10]
+*+ io_out[11] io_out[12] io_out[13] io_out[14] io_out[15] io_out[16] io_out[17] io_out[18]
+*+ io_out[19] io_out[1] io_out[20] io_out[21] io_out[22] io_out[23] io_out[24] io_out[25]
+*+ io_out[26] io_out[2] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8]
+*+ io_out[9] la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103]
+*+ la_data_in[104] la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108]
+*+ la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113]
+*+ la_data_in[114] la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118]
+*+ la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123]
+*+ la_data_in[124] la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13]
+*+ la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19]
+*+ la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24]
+*+ la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2]
+*+ la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35]
+*+ la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40]
+*+ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46]
+*+ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51]
+*+ la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57]
+*+ la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62]
+*+ la_data_in[63] la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68]
+*+ la_data_in[69] la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73]
+*+ la_data_in[74] la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79]
+*+ la_data_in[7] la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84]
+*+ la_data_in[85] la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8]
+*+ la_data_in[90] la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95]
+*+ la_data_in[96] la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0]
+*+ la_data_out[100] la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104]
+*+ la_data_out[105] la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109]
+*+ la_data_out[10] la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113]
+*+ la_data_out[114] la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118]
+*+ la_data_out[119] la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122]
+*+ la_data_out[123] la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127]
+*+ la_data_out[12] la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16]
+*+ la_data_out[17] la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21]
+*+ la_data_out[22] la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26]
+*+ la_data_out[27] la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31]
+*+ la_data_out[32] la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36]
+*+ la_data_out[37] la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41]
+*+ la_data_out[42] la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46]
+*+ la_data_out[47] la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51]
+*+ la_data_out[52] la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56]
+*+ la_data_out[57] la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61]
+*+ la_data_out[62] la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66]
+*+ la_data_out[67] la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71]
+*+ la_data_out[72] la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76]
+*+ la_data_out[77] la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81]
+*+ la_data_out[82] la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86]
+*+ la_data_out[87] la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91]
+*+ la_data_out[92] la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96]
+*+ la_data_out[97] la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100]
+*+ la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107]
+*+ la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113]
+*+ la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11]
+*+ la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126]
+*+ la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17]
+*+ la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23]
+*+ la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2]
+*+ la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36]
+*+ la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42]
+*+ la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49]
+*+ la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55]
+*+ la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61]
+*+ la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68]
+*+ la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74]
+*+ la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80]
+*+ la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87]
+*+ la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93]
+*+ la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9]
+*+ user_clock2 user_irq[0] user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2
+*+ vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11]
+*+ wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17]
+*+ wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22]
+*+ wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28]
+*+ wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4]
+*+ wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0]
+*+ wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15]
+*+ wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20]
+*+ wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26]
+*+ wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31]
+*+ wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9]
+*+ wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14]
+*+ wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1]
+*+ wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25]
+*+ wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
+*+ wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
+*+ wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+Xres_amp_top_0 bias_0/iref_9 bias_0/iref_8 vssa1 bias_0/iref_6 bias_0/iref_7 bias_0/iref_5
++ vdda1 io_analog[6] gpio_noesd[4] gpio_noesd[5] gpio_noesd[6] gpio_noesd[3] gpio_noesd[2]
++ io_analog[2] io_analog[0] gpio_noesd[1] io_analog[1] io_analog[3] io_analog[4] res_amp_top
+Xtop_pll_v1_0 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_2 io_analog[9]
++ top_pll_v1
+Xtop_pll_v1_1 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_0 io_analog[7]
++ top_pll_v1
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xbias_0 vssa1 vdda1 bias_0/iref_0 bias_0/iref_1 bias_0/iref_2 bias_0/iref_5 bias_0/iref_6
++ bias_0/iref_7 bias_0/iref_8 bias_0/iref_9 io_analog[5] bias
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xmimcap_decoup_1x5_0[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_0[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_0[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xmimcap_decoup_1x5_2[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_2[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_2[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xtop_pll_v2_0 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_1 gpio_noesd[8]
++ io_analog[8] top_pll_v2
+.end
+
diff --git a/mag/extractions/user_analog_project_wrapper_pex_c.spice b/mag/extractions/user_analog_project_wrapper_pex_c.spice
new file mode 100644
index 0000000..03ec8de
--- /dev/null
+++ b/mag/extractions/user_analog_project_wrapper_pex_c.spice
@@ -0,0 +1,8669 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n111_n156# a_n15_n156# 0.02fF
+C1 a_n81_n125# a_15_n125# 0.36fF
+C2 a_n81_n125# a_111_n125# 0.13fF
+C3 w_n311_n344# a_n81_n125# 0.09fF
+C4 a_15_n125# a_111_n125# 0.36fF
+C5 w_n311_n344# a_15_n125# 0.09fF
+C6 w_n311_n344# a_111_n125# 0.14fF
+C7 a_n173_n125# a_n81_n125# 0.36fF
+C8 a_n173_n125# a_15_n125# 0.13fF
+C9 a_n173_n125# a_111_n125# 0.08fF
+C10 a_n15_n156# a_81_n156# 0.02fF
+C11 w_n311_n344# a_n173_n125# 0.14fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n173_n125# 0.08fF
+C1 a_111_n125# a_n81_n125# 0.13fF
+C2 a_15_n125# a_n173_n125# 0.13fF
+C3 a_15_n125# a_n81_n125# 0.36fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_81_n151# a_n15_n151# 0.02fF
+C7 a_n111_n151# a_n15_n151# 0.02fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 vdd m1_187_n605# 0.55fF
+C1 vdd m1_45_n513# 0.69fF
+C2 m1_45_n513# m1_187_n605# 0.36fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_15_n125# w_n311_n344# 0.09fF
+C2 a_15_n125# a_111_n125# 0.36fF
+C3 w_n311_n344# a_n81_n125# 0.09fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_n173_n125# a_n81_n125# 0.36fF
+C7 a_15_n125# a_n81_n125# 0.36fF
+C8 w_n311_n344# a_111_n125# 0.14fF
+C9 a_n173_n125# w_n311_n344# 0.14fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n81_n125# 0.36fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_111_n125# a_n81_n125# 0.13fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n173_n125# a_111_n125# 0.08fF
+C5 a_15_n125# a_n81_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 out vdd 0.10fF
+C1 out in 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in CLK 0.31fF
+C1 inverter_cp_x1_2/in CLK_d 0.12fF
+C2 inverter_cp_x1_2/in vdd 0.21fF
+C3 CLK inverter_cp_x1_0/out 0.31fF
+C4 nCLK_d inverter_cp_x1_0/out 0.11fF
+C5 vdd CLK 0.36fF
+C6 vdd nCLK_d 0.03fF
+C7 vdd CLK_d 0.03fF
+C8 vdd inverter_cp_x1_0/out 0.28fF
+C9 inverter_cp_x1_2/in vss 2.01fF
+C10 CLK_d vss 0.96fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_63_n95# w_n263_n314# 0.11fF
+C1 w_n263_n314# a_n125_n95# 0.11fF
+C2 a_n33_n95# a_63_n95# 0.28fF
+C3 a_n33_n95# a_n125_n95# 0.28fF
+C4 a_63_n95# a_n125_n95# 0.10fF
+C5 a_n33_n95# w_n263_n314# 0.08fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_15_n125# a_n173_n125# 0.13fF
+C2 a_n81_n125# a_n173_n125# 0.36fF
+C3 a_n129_n213# a_n173_n125# 0.02fF
+C4 a_15_n125# a_111_n125# 0.36fF
+C5 a_n81_n125# a_111_n125# 0.13fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 a_n129_n213# a_111_n125# 0.01fF
+C8 a_15_n125# a_n129_n213# 0.10fF
+C9 a_n81_n125# a_n129_n213# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n81_n183# a_n33_n95# 0.10fF
+C1 a_n33_n95# a_n125_n95# 0.88fF
+C2 a_n81_n183# a_n125_n95# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 m1_657_280# CLK 0.24fF
+C1 nQ nD 0.05fF
+C2 D Q 0.05fF
+C3 vdd Q 0.16fF
+C4 D nQ 0.05fF
+C5 nQ Q 0.93fF
+C6 nQ vdd 0.16fF
+C7 m1_657_280# Q 0.94fF
+C8 nD Q 0.05fF
+C9 m1_657_280# nQ 1.41fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss vdd latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ latch_diff_0/nD Q latch_diff_1/nD latch_diff_1/m1_657_280# D latch_diff_0/D CLK
++ clock_inverter_0/inverter_cp_x1_0/out nCLK
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C1 latch_diff_1/D latch_diff_0/nD 0.41fF
+C2 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C3 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C4 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C5 nQ latch_diff_1/D 0.11fF
+C6 latch_diff_1/D latch_diff_1/nD 0.33fF
+C7 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C8 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C9 latch_diff_1/D latch_diff_0/D 0.11fF
+C10 latch_diff_1/D vdd 0.03fF
+C11 latch_diff_0/nD vdd 0.14fF
+C12 latch_diff_1/nD Q 0.01fF
+C13 nQ latch_diff_1/nD 0.08fF
+C14 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C15 latch_diff_1/nD latch_diff_0/D 0.04fF
+C16 latch_diff_1/nD vdd 0.02fF
+C17 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C18 latch_diff_0/D vdd 0.09fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C28 latch_diff_0/D vss 1.29fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n129_n84# a_n221_n84# 0.24fF
+C1 a_n221_n84# w_n359_n303# 0.08fF
+C2 a_n129_n84# w_n359_n303# 0.06fF
+C3 a_n33_n84# a_63_n84# 0.24fF
+C4 a_n63_n110# a_33_n110# 0.02fF
+C5 a_63_n84# a_n221_n84# 0.05fF
+C6 a_n129_n84# a_63_n84# 0.09fF
+C7 a_n63_n110# a_n159_n110# 0.02fF
+C8 a_63_n84# w_n359_n303# 0.06fF
+C9 a_n33_n84# a_159_n84# 0.09fF
+C10 a_n221_n84# a_159_n84# 0.04fF
+C11 a_n129_n84# a_159_n84# 0.05fF
+C12 w_n359_n303# a_159_n84# 0.08fF
+C13 a_33_n110# a_129_n110# 0.02fF
+C14 a_63_n84# a_159_n84# 0.24fF
+C15 a_n33_n84# a_n221_n84# 0.09fF
+C16 a_n33_n84# a_n129_n84# 0.24fF
+C17 a_n33_n84# w_n359_n303# 0.05fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n42# a_63_n42# 0.12fF
+C1 a_n33_n42# a_n221_n42# 0.05fF
+C2 a_n221_n42# a_63_n42# 0.03fF
+C3 a_n33_n42# a_n129_n42# 0.12fF
+C4 a_n129_n42# a_63_n42# 0.05fF
+C5 a_n63_n68# a_33_n68# 0.02fF
+C6 a_n129_n42# a_n221_n42# 0.12fF
+C7 a_129_n68# a_33_n68# 0.02fF
+C8 a_n63_n68# a_n159_n68# 0.02fF
+C9 a_n33_n42# a_159_n42# 0.05fF
+C10 a_159_n42# a_63_n42# 0.12fF
+C11 a_159_n42# a_n221_n42# 0.02fF
+C12 a_159_n42# a_n129_n42# 0.03fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 vdd in vss out
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 out vdd 0.62fF
+C1 in vdd 0.33fF
+C2 in out 0.67fF
+C3 in vss 1.89fF
+C4 out vss 0.66fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BDRUME VSUBS a_351_n84# a_n513_n84# a_639_n84# a_159_n84#
++ a_n321_n84# a_447_n84# a_n753_n181# a_n609_n84# w_n935_n303# a_n129_n84# a_735_n84#
++ a_255_n84# a_n417_n84# a_63_n84# a_543_n84# a_n705_n84# a_n225_n84# a_n797_n84#
++ a_n33_n84#
+X0 a_n705_n84# a_n753_n181# a_n797_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n513_n84# a_n753_n181# a_n609_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n417_n84# a_n753_n181# a_n513_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_n321_n84# a_n753_n181# a_n417_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X4 a_n225_n84# a_n753_n181# a_n321_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 a_n129_n84# a_n753_n181# a_n225_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X6 a_n609_n84# a_n753_n181# a_n705_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_63_n84# a_n753_n181# a_n33_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X8 a_n33_n84# a_n753_n181# a_n129_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X9 a_159_n84# a_n753_n181# a_63_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X10 a_255_n84# a_n753_n181# a_159_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X11 a_351_n84# a_n753_n181# a_255_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X12 a_543_n84# a_n753_n181# a_447_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X13 a_447_n84# a_n753_n181# a_351_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X14 a_639_n84# a_n753_n181# a_543_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X15 a_735_n84# a_n753_n181# a_639_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_255_n84# a_351_n84# 0.24fF
+C1 a_n417_n84# a_n705_n84# 0.05fF
+C2 a_639_n84# w_n935_n303# 0.04fF
+C3 a_351_n84# a_159_n84# 0.09fF
+C4 a_n321_n84# a_n705_n84# 0.04fF
+C5 a_n225_n84# a_n513_n84# 0.05fF
+C6 a_n33_n84# a_63_n84# 0.24fF
+C7 a_735_n84# a_543_n84# 0.09fF
+C8 a_n609_n84# a_n705_n84# 0.24fF
+C9 a_543_n84# a_447_n84# 0.24fF
+C10 a_n417_n84# a_n225_n84# 0.09fF
+C11 a_543_n84# a_255_n84# 0.05fF
+C12 a_735_n84# a_447_n84# 0.05fF
+C13 a_n225_n84# a_n129_n84# 0.24fF
+C14 a_n417_n84# a_n513_n84# 0.24fF
+C15 a_159_n84# a_n225_n84# 0.04fF
+C16 a_351_n84# a_63_n84# 0.05fF
+C17 a_n321_n84# a_n225_n84# 0.24fF
+C18 a_255_n84# a_447_n84# 0.09fF
+C19 a_543_n84# a_159_n84# 0.04fF
+C20 w_n935_n303# a_n705_n84# 0.04fF
+C21 a_n129_n84# a_n513_n84# 0.04fF
+C22 a_n225_n84# a_n609_n84# 0.04fF
+C23 a_n321_n84# a_n513_n84# 0.09fF
+C24 a_159_n84# a_447_n84# 0.05fF
+C25 a_255_n84# a_n129_n84# 0.04fF
+C26 a_n417_n84# a_n129_n84# 0.05fF
+C27 a_255_n84# a_159_n84# 0.24fF
+C28 a_n417_n84# a_n321_n84# 0.24fF
+C29 a_n797_n84# a_n705_n84# 0.24fF
+C30 a_n513_n84# a_n609_n84# 0.24fF
+C31 a_351_n84# a_639_n84# 0.05fF
+C32 a_63_n84# a_n225_n84# 0.05fF
+C33 a_159_n84# a_n129_n84# 0.05fF
+C34 a_n417_n84# a_n609_n84# 0.09fF
+C35 a_n321_n84# a_n129_n84# 0.09fF
+C36 a_543_n84# w_n935_n303# 0.03fF
+C37 a_63_n84# a_447_n84# 0.04fF
+C38 a_n321_n84# a_n609_n84# 0.05fF
+C39 a_255_n84# a_63_n84# 0.09fF
+C40 a_735_n84# w_n935_n303# 0.08fF
+C41 a_n513_n84# w_n935_n303# 0.02fF
+C42 a_447_n84# w_n935_n303# 0.02fF
+C43 a_n33_n84# a_351_n84# 0.04fF
+C44 a_63_n84# a_n129_n84# 0.09fF
+C45 a_543_n84# a_639_n84# 0.24fF
+C46 a_n797_n84# a_n513_n84# 0.05fF
+C47 a_159_n84# a_63_n84# 0.24fF
+C48 a_n321_n84# a_63_n84# 0.04fF
+C49 a_n417_n84# a_n797_n84# 0.04fF
+C50 a_735_n84# a_639_n84# 0.24fF
+C51 a_447_n84# a_639_n84# 0.09fF
+C52 a_255_n84# a_639_n84# 0.04fF
+C53 w_n935_n303# a_n609_n84# 0.03fF
+C54 a_n33_n84# a_n225_n84# 0.09fF
+C55 a_n797_n84# a_n609_n84# 0.09fF
+C56 a_n33_n84# a_255_n84# 0.05fF
+C57 a_n417_n84# a_n33_n84# 0.04fF
+C58 a_543_n84# a_351_n84# 0.09fF
+C59 a_n797_n84# w_n935_n303# 0.08fF
+C60 a_n33_n84# a_n129_n84# 0.24fF
+C61 a_735_n84# a_351_n84# 0.04fF
+C62 a_n33_n84# a_159_n84# 0.09fF
+C63 a_n513_n84# a_n705_n84# 0.09fF
+C64 a_n33_n84# a_n321_n84# 0.05fF
+C65 a_351_n84# a_447_n84# 0.24fF
+C66 a_735_n84# VSUBS 0.03fF
+C67 a_639_n84# VSUBS 0.03fF
+C68 a_543_n84# VSUBS 0.03fF
+C69 a_447_n84# VSUBS 0.03fF
+C70 a_351_n84# VSUBS 0.03fF
+C71 a_255_n84# VSUBS 0.03fF
+C72 a_159_n84# VSUBS 0.03fF
+C73 a_63_n84# VSUBS 0.03fF
+C74 a_n33_n84# VSUBS 0.03fF
+C75 a_n129_n84# VSUBS 0.03fF
+C76 a_n225_n84# VSUBS 0.03fF
+C77 a_n321_n84# VSUBS 0.03fF
+C78 a_n417_n84# VSUBS 0.03fF
+C79 a_n513_n84# VSUBS 0.03fF
+C80 a_n609_n84# VSUBS 0.03fF
+C81 a_n705_n84# VSUBS 0.03fF
+C82 a_n797_n84# VSUBS 0.03fF
+C83 a_n753_n181# VSUBS 2.56fF
+C84 w_n935_n303# VSUBS 4.96fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_QQE8KM a_543_n42# a_n705_n42# a_n225_n42# a_n797_n42#
++ a_n33_n42# a_351_n42# a_n513_n42# a_639_n42# a_159_n42# w_n935_n252# a_n757_64#
++ a_n321_n42# a_447_n42# a_n609_n42# a_n129_n42# a_735_n42# a_255_n42# a_n417_n42#
++ a_63_n42#
+X0 a_63_n42# a_n757_64# a_n33_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n757_64# a_n129_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_351_n42# a_n757_64# a_255_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_159_n42# a_n757_64# a_63_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X4 a_255_n42# a_n757_64# a_159_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 a_447_n42# a_n757_64# a_351_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X6 a_543_n42# a_n757_64# a_447_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X7 a_735_n42# a_n757_64# a_639_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X8 a_639_n42# a_n757_64# a_543_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X9 a_n321_n42# a_n757_64# a_n417_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_n705_n42# a_n757_64# a_n797_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 a_n513_n42# a_n757_64# a_n609_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X12 a_n417_n42# a_n757_64# a_n513_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X13 a_n225_n42# a_n757_64# a_n321_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 a_n129_n42# a_n757_64# a_n225_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X15 a_n609_n42# a_n757_64# a_n705_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_351_n42# a_159_n42# 0.05fF
+C1 a_n797_n42# a_n609_n42# 0.05fF
+C2 a_n417_n42# a_n225_n42# 0.05fF
+C3 a_n129_n42# a_255_n42# 0.02fF
+C4 a_n33_n42# a_351_n42# 0.02fF
+C5 a_159_n42# a_255_n42# 0.12fF
+C6 a_n513_n42# a_n417_n42# 0.12fF
+C7 a_n417_n42# a_n705_n42# 0.03fF
+C8 a_351_n42# a_543_n42# 0.05fF
+C9 a_543_n42# a_639_n42# 0.12fF
+C10 a_n129_n42# a_n225_n42# 0.12fF
+C11 a_n33_n42# a_255_n42# 0.03fF
+C12 a_351_n42# a_639_n42# 0.03fF
+C13 a_n225_n42# a_159_n42# 0.02fF
+C14 a_543_n42# a_255_n42# 0.03fF
+C15 a_n129_n42# a_n513_n42# 0.02fF
+C16 a_n129_n42# a_63_n42# 0.05fF
+C17 a_351_n42# a_255_n42# 0.12fF
+C18 a_n417_n42# a_n321_n42# 0.12fF
+C19 a_639_n42# a_255_n42# 0.02fF
+C20 a_n33_n42# a_n225_n42# 0.05fF
+C21 a_n513_n42# a_n797_n42# 0.03fF
+C22 a_n797_n42# a_n705_n42# 0.12fF
+C23 a_159_n42# a_63_n42# 0.12fF
+C24 a_n609_n42# a_n225_n42# 0.02fF
+C25 a_n129_n42# a_n321_n42# 0.05fF
+C26 a_735_n42# a_447_n42# 0.03fF
+C27 a_n33_n42# a_63_n42# 0.12fF
+C28 a_n513_n42# a_n609_n42# 0.12fF
+C29 a_n609_n42# a_n705_n42# 0.12fF
+C30 a_159_n42# a_447_n42# 0.03fF
+C31 a_351_n42# a_63_n42# 0.03fF
+C32 a_n33_n42# a_n321_n42# 0.03fF
+C33 a_543_n42# a_447_n42# 0.12fF
+C34 a_255_n42# a_63_n42# 0.05fF
+C35 a_n129_n42# a_n417_n42# 0.03fF
+C36 a_n609_n42# a_n321_n42# 0.03fF
+C37 a_351_n42# a_447_n42# 0.12fF
+C38 a_639_n42# a_447_n42# 0.05fF
+C39 a_n513_n42# a_n225_n42# 0.03fF
+C40 a_n417_n42# a_n797_n42# 0.02fF
+C41 a_n225_n42# a_63_n42# 0.03fF
+C42 a_n513_n42# a_n705_n42# 0.05fF
+C43 a_447_n42# a_255_n42# 0.05fF
+C44 a_n33_n42# a_n417_n42# 0.02fF
+C45 a_n129_n42# a_159_n42# 0.03fF
+C46 a_n225_n42# a_n321_n42# 0.12fF
+C47 a_n417_n42# a_n609_n42# 0.05fF
+C48 a_n129_n42# a_n33_n42# 0.12fF
+C49 a_543_n42# a_735_n42# 0.05fF
+C50 a_n513_n42# a_n321_n42# 0.05fF
+C51 a_n705_n42# a_n321_n42# 0.02fF
+C52 a_n33_n42# a_159_n42# 0.05fF
+C53 a_n321_n42# a_63_n42# 0.02fF
+C54 a_351_n42# a_735_n42# 0.02fF
+C55 a_735_n42# a_639_n42# 0.12fF
+C56 a_447_n42# a_63_n42# 0.02fF
+C57 a_543_n42# a_159_n42# 0.02fF
+C58 a_735_n42# w_n935_n252# 0.07fF
+C59 a_639_n42# w_n935_n252# 0.05fF
+C60 a_543_n42# w_n935_n252# 0.05fF
+C61 a_447_n42# w_n935_n252# 0.04fF
+C62 a_351_n42# w_n935_n252# 0.04fF
+C63 a_255_n42# w_n935_n252# 0.04fF
+C64 a_159_n42# w_n935_n252# 0.04fF
+C65 a_63_n42# w_n935_n252# 0.04fF
+C66 a_n33_n42# w_n935_n252# 0.04fF
+C67 a_n129_n42# w_n935_n252# 0.04fF
+C68 a_n225_n42# w_n935_n252# 0.04fF
+C69 a_n321_n42# w_n935_n252# 0.04fF
+C70 a_n417_n42# w_n935_n252# 0.04fF
+C71 a_n513_n42# w_n935_n252# 0.04fF
+C72 a_n609_n42# w_n935_n252# 0.05fF
+C73 a_n705_n42# w_n935_n252# 0.05fF
+C74 a_n797_n42# w_n935_n252# 0.07fF
+C75 a_n757_64# w_n935_n252# 2.44fF
+.ends
+
+.subckt inverter_min_x16 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_BDRUME_0 vss out vdd vdd out vdd vdd in out vdd vdd out vdd
++ out vdd out vdd out out out sky130_fd_pr__pfet_01v8_BDRUME
+Xsky130_fd_pr__nfet_01v8_QQE8KM_0 out vss out out out out vss vss out vss in vss vss
++ out vss out vss out vss sky130_fd_pr__nfet_01v8_QQE8KM
+C0 vdd in 1.15fF
+C1 vdd out 1.63fF
+C2 in out 1.40fF
+C3 out vss 0.98fF
+C4 in vss 7.30fF
+C5 vdd vss 10.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_75PKJG VSUBS a_n33_n102# w_n359_n321# a_n177_n199#
++ a_63_n102# a_n129_n102# a_n221_n102# a_25_n199# a_159_n102#
+X0 a_159_n102# a_25_n199# a_63_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_25_n199# a_n33_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X2 a_n129_n102# a_n177_n199# a_n221_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X3 a_n33_n102# a_n177_n199# a_n129_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+C0 a_n129_n102# w_n359_n321# 0.07fF
+C1 a_n33_n102# a_n129_n102# 0.30fF
+C2 a_159_n102# w_n359_n321# 0.10fF
+C3 a_159_n102# a_n33_n102# 0.11fF
+C4 a_63_n102# w_n359_n321# 0.07fF
+C5 a_63_n102# a_n33_n102# 0.30fF
+C6 a_159_n102# a_n129_n102# 0.07fF
+C7 a_63_n102# a_n129_n102# 0.11fF
+C8 a_n177_n199# a_25_n199# 0.07fF
+C9 a_63_n102# a_159_n102# 0.30fF
+C10 a_n221_n102# w_n359_n321# 0.10fF
+C11 a_n221_n102# a_n33_n102# 0.11fF
+C12 a_n221_n102# a_n129_n102# 0.30fF
+C13 a_n33_n102# w_n359_n321# 0.06fF
+C14 a_159_n102# a_n221_n102# 0.05fF
+C15 a_63_n102# a_n221_n102# 0.07fF
+C16 a_159_n102# VSUBS 0.03fF
+C17 a_63_n102# VSUBS 0.03fF
+C18 a_n33_n102# VSUBS 0.03fF
+C19 a_n129_n102# VSUBS 0.03fF
+C20 a_n221_n102# VSUBS 0.03fF
+C21 a_25_n199# VSUBS 0.22fF
+C22 a_n177_n199# VSUBS 0.22fF
+C23 w_n359_n321# VSUBS 2.35fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XRJ78J a_n33_n102# w_n263_n312# a_63_n102# a_n125_n102#
++ a_n81_124#
+X0 a_n33_n102# a_n81_124# a_n125_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_n81_124# a_n33_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+C0 a_n125_n102# a_63_n102# 0.11fF
+C1 a_n125_n102# a_n33_n102# 0.30fF
+C2 a_n33_n102# a_63_n102# 0.30fF
+C3 a_63_n102# w_n263_n312# 0.06fF
+C4 a_n33_n102# w_n263_n312# 0.08fF
+C5 a_n125_n102# w_n263_n312# 0.12fF
+C6 a_n81_124# w_n263_n312# 0.21fF
+.ends
+
+.subckt nand_logic avss1p8 in1 avdd1p8 in2 out m1_21_n341#
+Xsky130_fd_pr__pfet_01v8_75PKJG_0 avss1p8 avdd1p8 avdd1p8 in1 out out avdd1p8 in2
++ avdd1p8 sky130_fd_pr__pfet_01v8_75PKJG
+Xsky130_fd_pr__nfet_01v8_XRJ78J_0 m1_21_n341# avss1p8 avss1p8 avss1p8 in1 sky130_fd_pr__nfet_01v8_XRJ78J
+Xsky130_fd_pr__nfet_01v8_XRJ78J_1 out avss1p8 m1_21_n341# m1_21_n341# in2 sky130_fd_pr__nfet_01v8_XRJ78J
+C0 out m1_21_n341# 0.13fF
+C1 out avdd1p8 0.20fF
+C2 avdd1p8 in2 0.02fF
+C3 out in1 0.10fF
+C4 m1_21_n341# avdd1p8 0.01fF
+C5 in1 in2 0.07fF
+C6 m1_21_n341# in1 0.25fF
+C7 out in2 0.37fF
+C8 m1_21_n341# avss1p8 0.92fF
+C9 out avss1p8 0.47fF
+C10 in2 avss1p8 0.91fF
+C11 in1 avss1p8 0.93fF
+C12 avdd1p8 avss1p8 2.37fF
+.ends
+
+.subckt res_amp_sync_v2 avdd1p8 DFlipFlop_4/Q vss clkn DFlipFlop_4/latch_diff_1/m1_657_280#
++ DFlipFlop_4/nQ DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_0/D DFlipFlop_3/Q
++ DFlipFlop_3/D DFlipFlop_4/D DFlipFlop_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_4/latch_diff_1/D DFlipFlop_4/latch_diff_1/nD DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_4/latch_diff_0/D DFlipFlop_3/latch_diff_1/D clk_amp DFlipFlop_3/nQ clkp
++ rst
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_3/D
++ DFlipFlop_0/latch_diff_0/D clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/nQ DFlipFlop_1/latch_diff_0/nD
++ DFlipFlop_2/D DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D DFlipFlop_3/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/Q DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ DFlipFlop_2/Q DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
++ DFlipFlop_2/latch_diff_0/D clkp DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
++ DFlipFlop_3/Q DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/D
++ DFlipFlop_3/latch_diff_0/D clkp DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+Xinverter_min_x4_0 avdd1p8 DFlipFlop_0/Q vss DFlipFlop_3/D inverter_min_x4
+Xinverter_min_x4_1 avdd1p8 nand_logic_0/out vss DFlipFlop_4/D inverter_min_x4
+XDFlipFlop_4 DFlipFlop_4/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_4/latch_diff_1/D
++ DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_4/nQ DFlipFlop_4/latch_diff_0/nD
++ DFlipFlop_4/Q DFlipFlop_4/latch_diff_1/nD DFlipFlop_4/latch_diff_1/m1_657_280# DFlipFlop_4/D
++ DFlipFlop_4/latch_diff_0/D clkp DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+Xinverter_min_x4_2 avdd1p8 DFlipFlop_2/D vss DFlipFlop_1/D inverter_min_x4
+Xinverter_min_x4_3 avdd1p8 nand_logic_1/out vss rst inverter_min_x4
+Xinverter_min_x4_4 avdd1p8 DFlipFlop_4/Q vss inverter_min_x4_4/out inverter_min_x4
+Xinverter_min_x16_0 inverter_min_x4_4/out clk_amp vss avdd1p8 inverter_min_x16
+Xnand_logic_0 vss DFlipFlop_2/Q avdd1p8 DFlipFlop_3/Q nand_logic_0/out nand_logic_0/m1_21_n341#
++ nand_logic
+Xnand_logic_1 vss DFlipFlop_4/D avdd1p8 clkp nand_logic_1/out nand_logic_1/m1_21_n341#
++ nand_logic
+C0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
+C1 DFlipFlop_1/D DFlipFlop_1/latch_diff_1/D 0.02fF
+C2 clkp avdd1p8 0.53fF
+C3 DFlipFlop_1/latch_diff_0/D DFlipFlop_0/Q 0.74fF
+C4 DFlipFlop_3/Q clkn 0.12fF
+C5 DFlipFlop_2/D DFlipFlop_2/nQ 0.03fF
+C6 nand_logic_1/m1_21_n341# nand_logic_1/out 0.01fF
+C7 DFlipFlop_4/Q avdd1p8 4.03fF
+C8 clkn DFlipFlop_4/latch_diff_1/D 0.08fF
+C9 nand_logic_0/out DFlipFlop_2/Q 0.02fF
+C10 DFlipFlop_0/Q avdd1p8 0.66fF
+C11 clkp DFlipFlop_4/nQ 0.02fF
+C12 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_3/D 0.43fF
+C13 clkp DFlipFlop_2/Q 0.11fF
+C14 clkp DFlipFlop_3/D 0.35fF
+C15 clkp DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C16 DFlipFlop_0/latch_diff_0/D DFlipFlop_3/D 0.31fF
+C17 nand_logic_1/out avdd1p8 0.04fF
+C18 nand_logic_1/m1_21_n341# DFlipFlop_4/D 0.09fF
+C19 DFlipFlop_3/nQ avdd1p8 0.03fF
+C20 DFlipFlop_2/D avdd1p8 4.16fF
+C21 clkp DFlipFlop_4/latch_diff_0/nD 0.08fF
+C22 clk_amp inverter_min_x4_4/out 0.12fF
+C23 clkn DFlipFlop_3/latch_diff_1/nD 0.17fF
+C24 DFlipFlop_3/Q nand_logic_0/out 0.01fF
+C25 DFlipFlop_4/Q DFlipFlop_4/nQ 0.06fF
+C26 DFlipFlop_4/latch_diff_1/nD clkn 0.17fF
+C27 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.03fF
+C28 clkp DFlipFlop_2/latch_diff_0/nD 0.08fF
+C29 DFlipFlop_3/latch_diff_1/m1_657_280# clkn 0.30fF
+C30 clkp DFlipFlop_3/Q 0.17fF
+C31 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/D 0.49fF
+C32 DFlipFlop_1/nQ DFlipFlop_3/D 0.05fF
+C33 clkp DFlipFlop_0/latch_diff_0/nD 0.08fF
+C34 DFlipFlop_3/Q nand_logic_0/m1_21_n341# 0.07fF
+C35 DFlipFlop_4/D avdd1p8 0.52fF
+C36 DFlipFlop_3/D DFlipFlop_0/Q 0.38fF
+C37 clkp DFlipFlop_4/latch_diff_1/D 0.15fF
+C38 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/D 0.10fF
+C39 clkp clkn 0.22fF
+C40 DFlipFlop_0/latch_diff_0/D clkn 0.12fF
+C41 clkp DFlipFlop_2/latch_diff_0/m1_657_280# 0.30fF
+C42 DFlipFlop_4/Q DFlipFlop_3/Q 0.11fF
+C43 DFlipFlop_2/latch_diff_1/D DFlipFlop_3/Q 0.03fF
+C44 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.03fF
+C45 DFlipFlop_3/D DFlipFlop_2/D 0.06fF
+C46 clkp inverter_min_x4_4/out 0.43fF
+C47 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/D 0.54fF
+C48 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.02fF
+C49 clkp clk_amp 0.52fF
+C50 clkp DFlipFlop_3/latch_diff_1/nD 0.10fF
+C51 DFlipFlop_2/latch_diff_1/D clkn 0.08fF
+C52 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
+C53 DFlipFlop_4/latch_diff_1/nD clkp 0.10fF
+C54 DFlipFlop_1/nQ DFlipFlop_1/D 0.02fF
+C55 DFlipFlop_2/latch_diff_0/D clkn 0.12fF
+C56 DFlipFlop_4/Q inverter_min_x4_4/out 0.01fF
+C57 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/nD 0.17fF
+C58 DFlipFlop_0/Q DFlipFlop_1/D 0.72fF
+C59 DFlipFlop_3/nQ clkn 0.10fF
+C60 clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C61 nand_logic_0/out nand_logic_0/m1_21_n341# 0.01fF
+C62 rst nand_logic_1/out 0.04fF
+C63 DFlipFlop_2/D clkn 0.15fF
+C64 DFlipFlop_2/D DFlipFlop_1/D 0.02fF
+C65 DFlipFlop_4/D DFlipFlop_3/Q 0.94fF
+C66 DFlipFlop_0/nQ DFlipFlop_3/D 0.08fF
+C67 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C68 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/nD 0.02fF
+C69 clkp DFlipFlop_3/latch_diff_0/nD 0.08fF
+C70 DFlipFlop_0/latch_diff_1/D DFlipFlop_3/D 0.08fF
+C71 clkp DFlipFlop_4/latch_diff_0/m1_657_280# 0.30fF
+C72 DFlipFlop_4/D clkn 0.15fF
+C73 DFlipFlop_4/Q clkp 0.20fF
+C74 clkp DFlipFlop_2/latch_diff_1/D 0.15fF
+C75 DFlipFlop_0/latch_diff_1/nD clkn 0.17fF
+C76 DFlipFlop_0/latch_diff_1/m1_657_280# clkn 0.30fF
+C77 DFlipFlop_3/Q DFlipFlop_2/latch_diff_1/m1_657_280# 0.04fF
+C78 DFlipFlop_3/Q DFlipFlop_2/nQ 0.02fF
+C79 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/m1_657_280# 0.25fF
+C80 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in clkn -0.33fF
+C81 avdd1p8 DFlipFlop_2/Q 0.05fF
+C82 DFlipFlop_3/D DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C83 DFlipFlop_3/D avdd1p8 4.16fF
+C84 clkp nand_logic_1/out 0.03fF
+C85 DFlipFlop_0/nQ clkn 0.02fF
+C86 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
+C87 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/D 0.41fF
+C88 clkp DFlipFlop_3/nQ 0.13fF
+C89 DFlipFlop_2/latch_diff_1/m1_657_280# clkn 0.30fF
+C90 clkn DFlipFlop_2/nQ 0.02fF
+C91 clkp DFlipFlop_2/D 0.15fF
+C92 DFlipFlop_0/latch_diff_1/D clkn 0.08fF
+C93 clkp DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C94 DFlipFlop_1/nQ DFlipFlop_0/Q 0.01fF
+C95 DFlipFlop_4/D nand_logic_0/out 0.04fF
+C96 DFlipFlop_3/Q avdd1p8 0.76fF
+C97 DFlipFlop_3/latch_diff_1/D clkn 0.08fF
+C98 nand_logic_1/m1_21_n341# rst 0.02fF
+C99 DFlipFlop_4/latch_diff_0/D clkn 0.12fF
+C100 clkp DFlipFlop_4/D 0.24fF
+C101 clkn DFlipFlop_2/latch_diff_1/nD 0.17fF
+C102 DFlipFlop_2/latch_diff_1/D DFlipFlop_2/D 0.03fF
+C103 clkp DFlipFlop_0/latch_diff_0/m1_657_280# 0.32fF
+C104 clkp DFlipFlop_3/latch_diff_0/m1_657_280# 0.30fF
+C105 clkp DFlipFlop_0/latch_diff_1/nD 0.10fF
+C106 DFlipFlop_4/D nand_logic_0/m1_21_n341# 0.02fF
+C107 DFlipFlop_3/latch_diff_0/D clkn 0.12fF
+C108 DFlipFlop_2/D DFlipFlop_2/latch_diff_0/D -0.07fF
+C109 avdd1p8 clkn -1.00fF
+C110 DFlipFlop_1/D avdd1p8 2.55fF
+C111 rst avdd1p8 0.02fF
+C112 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/D 0.03fF
+C113 avdd1p8 inverter_min_x4_4/out 0.09fF
+C114 DFlipFlop_4/Q DFlipFlop_4/D 0.27fF
+C115 clkp DFlipFlop_0/nQ 0.02fF
+C116 clk_amp avdd1p8 0.10fF
+C117 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C118 clkp DFlipFlop_2/nQ 0.13fF
+C119 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C120 clkp DFlipFlop_0/latch_diff_1/D 0.15fF
+C121 DFlipFlop_3/Q DFlipFlop_2/Q 0.09fF
+C122 clkp DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C123 nand_logic_1/m1_21_n341# clkp 0.09fF
+C124 DFlipFlop_4/D nand_logic_1/out 0.01fF
+C125 clkp DFlipFlop_3/latch_diff_1/D 0.15fF
+C126 DFlipFlop_4/nQ clkn 0.02fF
+C127 clkp DFlipFlop_2/latch_diff_1/nD 0.20fF
+C128 DFlipFlop_3/D clkn 0.35fF
+C129 DFlipFlop_3/D DFlipFlop_1/D 0.28fF
+C130 DFlipFlop_0/Q DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.55fF
+C131 avdd1p8 nand_logic_0/out 0.03fF
+C132 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/nD 0.19fF
+C133 DFlipFlop_4/D DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out 0.42fF
+C134 DFlipFlop_4/latch_diff_1/m1_657_280# clkn 0.30fF
+C135 nand_logic_1/m1_21_n341# vss 0.86fF
+C136 nand_logic_0/m1_21_n341# vss 0.90fF
+C137 clk_amp vss 0.43fF
+C138 inverter_min_x4_4/out vss 5.90fF
+C139 nand_logic_1/out vss 1.76fF
+C140 rst vss 0.71fF
+C141 DFlipFlop_4/nQ vss 0.48fF
+C142 DFlipFlop_4/Q vss -2.08fF
+C143 DFlipFlop_4/latch_diff_1/m1_657_280# vss 0.57fF
+C144 DFlipFlop_4/latch_diff_1/nD vss 0.57fF
+C145 DFlipFlop_4/latch_diff_1/D vss -1.73fF
+C146 DFlipFlop_4/latch_diff_0/m1_657_280# vss 0.57fF
+C147 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C148 DFlipFlop_4/latch_diff_0/D vss 0.96fF
+C149 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C150 DFlipFlop_4/D vss 4.59fF
+C151 DFlipFlop_4/latch_diff_0/nD vss 1.14fF
+C152 nand_logic_0/out vss 1.26fF
+C153 DFlipFlop_0/Q vss -3.86fF
+C154 DFlipFlop_3/nQ vss 0.50fF
+C155 DFlipFlop_3/Q vss -2.01fF
+C156 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.72fF
+C157 clkn vss -2.25fF
+C158 DFlipFlop_3/latch_diff_1/nD vss 0.58fF
+C159 DFlipFlop_3/latch_diff_1/D vss -1.72fF
+C160 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C161 clkp vss -22.80fF
+C162 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C163 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C164 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C165 DFlipFlop_3/D vss 1.64fF
+C166 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C167 avdd1p8 vss 196.01fF
+C168 DFlipFlop_2/nQ vss 0.48fF
+C169 DFlipFlop_2/Q vss -1.05fF
+C170 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.65fF
+C171 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C172 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 DFlipFlop_2/D vss -0.35fF
+C178 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C179 DFlipFlop_1/nQ vss 0.48fF
+C180 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.59fF
+C181 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C182 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C183 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C184 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C185 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C186 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C187 DFlipFlop_1/D vss -1.00fF
+C188 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C189 DFlipFlop_0/nQ vss 0.48fF
+C190 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.59fF
+C191 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C192 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C193 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C194 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C195 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C196 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C197 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_4L9VGG VSUBS a_291_n200# w_n487_n419# a_35_n200#
++ a_n291_n238# a_n93_n200# a_163_n200# a_n349_n200# a_n221_n200#
+X0 a_291_n200# a_n291_n238# a_163_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_n221_n200# a_n291_n238# a_n349_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_35_n200# a_n291_n238# a_n93_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_163_n200# a_n291_n238# a_35_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_n93_n200# a_n291_n238# a_n221_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+C0 a_n221_n200# a_35_n200# 0.15fF
+C1 w_n487_n419# a_291_n200# 0.18fF
+C2 a_n93_n200# a_n291_n238# 0.08fF
+C3 a_291_n200# a_163_n200# 0.36fF
+C4 w_n487_n419# a_163_n200# 0.08fF
+C5 a_35_n200# a_n291_n238# 0.08fF
+C6 a_n221_n200# w_n487_n419# 0.08fF
+C7 a_n221_n200# a_163_n200# 0.09fF
+C8 a_n291_n238# w_n487_n419# 0.30fF
+C9 a_n291_n238# a_163_n200# 0.08fF
+C10 a_n93_n200# a_n349_n200# 0.15fF
+C11 a_n221_n200# a_n291_n238# 0.08fF
+C12 a_35_n200# a_n349_n200# 0.09fF
+C13 w_n487_n419# a_n349_n200# 0.18fF
+C14 a_n221_n200# a_n349_n200# 0.36fF
+C15 a_n93_n200# a_35_n200# 0.36fF
+C16 a_n93_n200# a_291_n200# 0.09fF
+C17 a_n93_n200# w_n487_n419# 0.06fF
+C18 a_n93_n200# a_163_n200# 0.15fF
+C19 a_35_n200# a_291_n200# 0.15fF
+C20 a_35_n200# w_n487_n419# 0.06fF
+C21 a_n93_n200# a_n221_n200# 0.36fF
+C22 a_35_n200# a_163_n200# 0.36fF
+C23 a_291_n200# VSUBS 0.03fF
+C24 a_163_n200# VSUBS 0.03fF
+C25 a_35_n200# VSUBS 0.03fF
+C26 a_n93_n200# VSUBS 0.03fF
+C27 a_n221_n200# VSUBS 0.03fF
+C28 a_n349_n200# VSUBS 0.03fF
+C29 a_n291_n238# VSUBS 0.72fF
+C30 w_n487_n419# VSUBS 4.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_L78GGD a_n73_n73# w_n211_n221# a_15_n73# a_n33_33#
+X0 a_15_n73# a_n33_33# a_n73_n73# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n73# a_n33_33# 0.02fF
+C1 a_n33_33# a_15_n73# 0.02fF
+C2 a_n73_n73# a_15_n73# 0.15fF
+C3 a_15_n73# w_n211_n221# 0.11fF
+C4 a_n73_n73# w_n211_n221# 0.11fF
+C5 a_n33_33# w_n211_n221# 0.18fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_6RX2PQ VSUBS w_n211_n268# a_15_n48# a_n33_n145# a_n73_n48#
+X0 a_15_n48# a_n33_n145# a_n73_n48# w_n211_n268# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n73_n48# a_15_n48# 0.29fF
+C1 a_n33_n145# a_n73_n48# 0.01fF
+C2 a_n73_n48# w_n211_n268# 0.13fF
+C3 a_n33_n145# a_15_n48# 0.01fF
+C4 a_15_n48# w_n211_n268# 0.13fF
+C5 a_n33_n145# w_n211_n268# 0.06fF
+C6 a_15_n48# VSUBS 0.03fF
+C7 a_n73_n48# VSUBS 0.03fF
+C8 a_n33_n145# VSUBS 0.12fF
+C9 w_n211_n268# VSUBS 1.50fF
+.ends
+
+.subckt inverter_min vdd out in vss
+XXM1 vss vss out in sky130_fd_pr__nfet_01v8_L78GGD
+XXM2 vss vdd out in vdd sky130_fd_pr__pfet_01v8_6RX2PQ
+C0 vdd out 0.20fF
+C1 vdd in 0.13fF
+C2 out in 0.67fF
+C3 out vss 0.52fF
+C4 in vss 0.72fF
+C5 vdd vss 2.55fF
+.ends
+
+.subckt buffer_no_inv_x05 VSUBS in avdd1p8 inverter_min_1/in out
+Xinverter_min_1 avdd1p8 out inverter_min_1/in VSUBS inverter_min
+Xinverter_min_0 avdd1p8 inverter_min_1/in in VSUBS inverter_min
+C0 out inverter_min_1/in 0.12fF
+C1 inverter_min_1/in avdd1p8 0.09fF
+C2 out avdd1p8 0.02fF
+C3 in inverter_min_1/in 0.07fF
+C4 in VSUBS 0.63fF
+C5 avdd1p8 VSUBS 4.78fF
+C6 out VSUBS 0.45fF
+C7 inverter_min_1/in VSUBS 1.08fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XA7ZMQ VSUBS a_21_142# a_63_n111# a_n87_142# a_n125_n111#
++ w_n263_n330# a_n33_n111#
+X0 a_n33_n111# a_n87_142# a_n125_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+X1 a_63_n111# a_21_142# a_n33_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+C0 a_21_142# a_63_n111# 0.02fF
+C1 a_21_142# w_n263_n330# 0.05fF
+C2 w_n263_n330# a_n87_142# 0.05fF
+C3 a_n125_n111# a_n87_142# 0.02fF
+C4 a_63_n111# w_n263_n330# 0.14fF
+C5 a_n33_n111# a_63_n111# 0.32fF
+C6 a_63_n111# a_n125_n111# 0.12fF
+C7 a_n33_n111# w_n263_n330# 0.10fF
+C8 w_n263_n330# a_n125_n111# 0.14fF
+C9 a_n33_n111# a_n125_n111# 0.32fF
+C10 a_21_142# a_n87_142# 0.14fF
+C11 a_63_n111# VSUBS 0.03fF
+C12 a_n33_n111# VSUBS 0.03fF
+C13 a_n125_n111# VSUBS 0.03fF
+C14 a_21_142# VSUBS 0.16fF
+C15 a_n87_142# VSUBS 0.16fF
+C16 w_n263_n330# VSUBS 2.11fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HAN8QX a_15_n142# a_n33_102# a_n73_n142# w_n211_n290#
+X0 a_15_n142# a_n33_102# a_n73_n142# w_n211_n290# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+C0 a_n73_n142# a_n33_102# 0.03fF
+C1 a_15_n142# a_n73_n142# 0.38fF
+C2 a_15_n142# a_n33_102# 0.03fF
+C3 a_15_n142# w_n211_n290# 0.19fF
+C4 a_n73_n142# w_n211_n290# 0.19fF
+C5 a_n33_102# w_n211_n290# 0.21fF
+.ends
+
+.subckt mux_2to1_logic sel avdd1p8 sel_b w_947_n633# avss1p8 out DinA DinB
+Xinverter_min_0 avdd1p8 sel_b sel avss1p8 inverter_min
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_0 avss1p8 sel DinA sel DinA avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_1 avss1p8 sel_b DinB sel_b DinB avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__nfet_01v8_HAN8QX_0 out sel_b DinA avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+Xsky130_fd_pr__nfet_01v8_HAN8QX_1 out sel DinB avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+C0 DinA DinB 0.07fF
+C1 sel_b DinA 0.56fF
+C2 out DinA 0.30fF
+C3 sel_b DinB 0.27fF
+C4 sel DinA 0.07fF
+C5 out DinB 0.37fF
+C6 out sel_b 0.58fF
+C7 sel DinB 0.02fF
+C8 sel_b sel 0.32fF
+C9 out sel 0.53fF
+C10 avdd1p8 DinA 0.26fF
+C11 avdd1p8 DinB 0.16fF
+C12 sel_b avdd1p8 0.74fF
+C13 out avdd1p8 0.23fF
+C14 avdd1p8 sel 0.72fF
+C15 DinA avss1p8 0.63fF
+C16 sel_b avss1p8 2.16fF
+C17 out avss1p8 1.11fF
+C18 DinB avss1p8 -0.09fF
+C19 sel avss1p8 2.55fF
+C20 avdd1p8 avss1p8 8.26fF
+.ends
+
+.subckt delay_cell_buff buffer_no_inv_x05_2/inverter_min_1/in reg2 avss1p8 mux_2to1_logic_4/DinA
++ avdd1p8 buffer_no_inv_x05_13/in clk mux_2to1_logic_3/DinA clk_out mux_2to1_logic_3/DinB
++ reg0 buffer_no_inv_x05_10/inverter_min_1/in reg1 buffer_no_inv_x05_7/inverter_min_1/in
++ nand_logic_0/in1 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b mux_2to1_logic_4/out
++ mux_2to1_logic_1/DinA mux_2to1_logic_1/sel_b buffer_no_inv_x05_3/in mux_2to1_logic_5/out
++ mux_2to1_logic_0/out mux_2to1_logic_4/DinB mux_2to1_logic_3/out buffer_no_inv_x05_13/inverter_min_1/in
++ mux_2to1_logic_1/out mux_2to1_logic_5/w_947_n633# buffer_no_inv_x05_12/inverter_min_1/in
++ nand_logic_0/m1_21_n341#
+Xbuffer_no_inv_x05_8 avss1p8 mux_2to1_logic_3/DinA avdd1p8 buffer_no_inv_x05_8/inverter_min_1/in
++ buffer_no_inv_x05_9/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_9 avss1p8 buffer_no_inv_x05_9/in avdd1p8 buffer_no_inv_x05_9/inverter_min_1/in
++ mux_2to1_logic_3/DinB buffer_no_inv_x05
+Xmux_2to1_logic_0 reg2 avdd1p8 mux_2to1_logic_0/sel_b mux_2to1_logic_0/w_947_n633#
++ avss1p8 mux_2to1_logic_0/out clk mux_2to1_logic_0/DinB mux_2to1_logic
+Xmux_2to1_logic_1 reg2 avdd1p8 mux_2to1_logic_1/sel_b mux_2to1_logic_1/w_947_n633#
++ avss1p8 mux_2to1_logic_1/out mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB mux_2to1_logic
+Xmux_2to1_logic_2 reg1 avdd1p8 mux_2to1_logic_2/sel_b mux_2to1_logic_2/w_947_n633#
++ avss1p8 mux_2to1_logic_2/out mux_2to1_logic_0/out mux_2to1_logic_1/out mux_2to1_logic
+Xmux_2to1_logic_3 reg2 avdd1p8 mux_2to1_logic_3/sel_b mux_2to1_logic_3/w_947_n633#
++ avss1p8 mux_2to1_logic_3/out mux_2to1_logic_3/DinA mux_2to1_logic_3/DinB mux_2to1_logic
+Xmux_2to1_logic_4 reg2 avdd1p8 mux_2to1_logic_4/sel_b mux_2to1_logic_4/w_947_n633#
++ avss1p8 mux_2to1_logic_4/out mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB mux_2to1_logic
+Xmux_2to1_logic_5 reg1 avdd1p8 mux_2to1_logic_5/sel_b mux_2to1_logic_5/w_947_n633#
++ avss1p8 mux_2to1_logic_5/out mux_2to1_logic_3/out mux_2to1_logic_4/out mux_2to1_logic
+Xmux_2to1_logic_6 reg0 avdd1p8 mux_2to1_logic_6/sel_b mux_2to1_logic_6/w_947_n633#
++ avss1p8 nand_logic_0/in1 mux_2to1_logic_2/out mux_2to1_logic_5/out mux_2to1_logic
+Xbuffer_no_inv_x05_10 avss1p8 mux_2to1_logic_3/DinB avdd1p8 buffer_no_inv_x05_10/inverter_min_1/in
++ buffer_no_inv_x05_11/in buffer_no_inv_x05
+Xnand_logic_0 avss1p8 nand_logic_0/in1 avdd1p8 clk clk_out nand_logic_0/m1_21_n341#
++ nand_logic
+Xbuffer_no_inv_x05_11 avss1p8 buffer_no_inv_x05_11/in avdd1p8 buffer_no_inv_x05_11/inverter_min_1/in
++ mux_2to1_logic_4/DinA buffer_no_inv_x05
+Xbuffer_no_inv_x05_12 avss1p8 mux_2to1_logic_4/DinA avdd1p8 buffer_no_inv_x05_12/inverter_min_1/in
++ buffer_no_inv_x05_13/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_13 avss1p8 buffer_no_inv_x05_13/in avdd1p8 buffer_no_inv_x05_13/inverter_min_1/in
++ mux_2to1_logic_4/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_0 avss1p8 clk avdd1p8 buffer_no_inv_x05_0/inverter_min_1/in buffer_no_inv_x05_1/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_2 avss1p8 mux_2to1_logic_0/DinB avdd1p8 buffer_no_inv_x05_2/inverter_min_1/in
++ buffer_no_inv_x05_3/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_1 avss1p8 buffer_no_inv_x05_1/in avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in
++ mux_2to1_logic_0/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_3 avss1p8 buffer_no_inv_x05_3/in avdd1p8 buffer_no_inv_x05_3/inverter_min_1/in
++ mux_2to1_logic_1/DinA buffer_no_inv_x05
+Xbuffer_no_inv_x05_4 avss1p8 mux_2to1_logic_1/DinA avdd1p8 buffer_no_inv_x05_4/inverter_min_1/in
++ buffer_no_inv_x05_5/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_5 avss1p8 buffer_no_inv_x05_5/in avdd1p8 buffer_no_inv_x05_5/inverter_min_1/in
++ mux_2to1_logic_1/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_6 avss1p8 mux_2to1_logic_1/DinB avdd1p8 buffer_no_inv_x05_6/inverter_min_1/in
++ buffer_no_inv_x05_7/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_7 avss1p8 buffer_no_inv_x05_7/in avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in
++ mux_2to1_logic_3/DinA buffer_no_inv_x05
+C0 mux_2to1_logic_5/out nand_logic_0/in1 0.38fF
+C1 mux_2to1_logic_4/sel_b mux_2to1_logic_4/DinB 0.20fF
+C2 avdd1p8 buffer_no_inv_x05_9/inverter_min_1/in 0.03fF
+C3 reg2 mux_2to1_logic_4/DinB 0.05fF
+C4 buffer_no_inv_x05_8/inverter_min_1/in mux_2to1_logic_4/sel_b 0.01fF
+C5 avdd1p8 mux_2to1_logic_4/DinB 2.49fF
+C6 buffer_no_inv_x05_1/inverter_min_1/in mux_2to1_logic_0/DinB 0.08fF
+C7 mux_2to1_logic_0/out reg1 0.63fF
+C8 avdd1p8 mux_2to1_logic_6/sel_b 0.05fF
+C9 clk mux_2to1_logic_0/out 0.05fF
+C10 avdd1p8 buffer_no_inv_x05_8/inverter_min_1/in 0.03fF
+C11 reg2 mux_2to1_logic_1/DinA 0.18fF
+C12 mux_2to1_logic_4/DinA mux_2to1_logic_4/out 0.27fF
+C13 mux_2to1_logic_4/DinA mux_2to1_logic_3/DinA 0.07fF
+C14 mux_2to1_logic_0/out mux_2to1_logic_0/DinB 0.14fF
+C15 reg1 mux_2to1_logic_4/out 0.37fF
+C16 buffer_no_inv_x05_3/inverter_min_1/in mux_2to1_logic_1/DinA 0.23fF
+C17 reg0 mux_2to1_logic_4/DinB -0.24fF
+C18 clk mux_2to1_logic_4/DinA 0.01fF
+C19 clk mux_2to1_logic_3/DinA 0.01fF
+C20 mux_2to1_logic_5/sel_b mux_2to1_logic_4/out 0.20fF
+C21 avdd1p8 mux_2to1_logic_1/DinA 0.55fF
+C22 reg0 mux_2to1_logic_6/sel_b 0.06fF
+C23 mux_2to1_logic_0/out mux_2to1_logic_1/out 1.27fF
+C24 mux_2to1_logic_5/sel_b reg1 0.06fF
+C25 clk mux_2to1_logic_0/DinB 0.01fF
+C26 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinB 0.03fF
+C27 buffer_no_inv_x05_7/inverter_min_1/in buffer_no_inv_x05_7/in 0.12fF
+C28 reg1 mux_2to1_logic_1/out 0.36fF
+C29 avdd1p8 buffer_no_inv_x05_6/inverter_min_1/in 0.03fF
+C30 mux_2to1_logic_0/out mux_2to1_logic_1/sel_b 0.26fF
+C31 avdd1p8 buffer_no_inv_x05_2/inverter_min_1/in 0.03fF
+C32 mux_2to1_logic_3/DinB buffer_no_inv_x05_9/inverter_min_1/in 0.18fF
+C33 avdd1p8 buffer_no_inv_x05_11/inverter_min_1/in 0.03fF
+C34 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b 0.22fF
+C35 mux_2to1_logic_3/out mux_2to1_logic_4/sel_b 0.23fF
+C36 reg2 mux_2to1_logic_2/out 0.85fF
+C37 reg2 mux_2to1_logic_3/out 0.36fF
+C38 mux_2to1_logic_1/DinB buffer_no_inv_x05_5/inverter_min_1/in 0.23fF
+C39 mux_2to1_logic_3/DinB mux_2to1_logic_4/DinB 0.29fF
+C40 mux_2to1_logic_1/sel_b mux_2to1_logic_0/DinB 0.04fF
+C41 reg2 mux_2to1_logic_0/sel_b 0.14fF
+C42 reg0 buffer_no_inv_x05_11/inverter_min_1/in 0.01fF
+C43 mux_2to1_logic_5/out mux_2to1_logic_4/out 0.45fF
+C44 avdd1p8 mux_2to1_logic_2/out 0.41fF
+C45 avdd1p8 mux_2to1_logic_3/out 0.39fF
+C46 mux_2to1_logic_5/out mux_2to1_logic_4/DinA 0.23fF
+C47 mux_2to1_logic_3/DinB buffer_no_inv_x05_8/inverter_min_1/in 0.10fF
+C48 mux_2to1_logic_3/sel_b mux_2to1_logic_1/out 0.04fF
+C49 avdd1p8 mux_2to1_logic_0/sel_b 0.05fF
+C50 buffer_no_inv_x05_13/inverter_min_1/in mux_2to1_logic_4/DinB 0.11fF
+C51 mux_2to1_logic_1/DinB buffer_no_inv_x05_4/inverter_min_1/in 0.15fF
+C52 mux_2to1_logic_2/out reg0 0.44fF
+C53 buffer_no_inv_x05_9/in buffer_no_inv_x05_9/inverter_min_1/in 0.12fF
+C54 buffer_no_inv_x05_3/inverter_min_1/in buffer_no_inv_x05_3/in 0.12fF
+C55 avdd1p8 buffer_no_inv_x05_3/in 0.11fF
+C56 mux_2to1_logic_3/DinB buffer_no_inv_x05_6/inverter_min_1/in 0.02fF
+C57 avdd1p8 buffer_no_inv_x05_7/in 0.09fF
+C58 buffer_no_inv_x05_9/in buffer_no_inv_x05_8/inverter_min_1/in 0.07fF
+C59 mux_2to1_logic_2/out nand_logic_0/in1 0.06fF
+C60 buffer_no_inv_x05_5/inverter_min_1/in buffer_no_inv_x05_5/in 0.12fF
+C61 avdd1p8 buffer_no_inv_x05_5/inverter_min_1/in 0.03fF
+C62 mux_2to1_logic_3/out mux_2to1_logic_3/DinB 0.13fF
+C63 buffer_no_inv_x05_13/in buffer_no_inv_x05_12/inverter_min_1/in 0.07fF
+C64 avdd1p8 buffer_no_inv_x05_11/in 0.10fF
+C65 mux_2to1_logic_4/out mux_2to1_logic_4/DinB 0.65fF
+C66 mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB 1.68fF
+C67 reg1 mux_2to1_logic_4/DinB 0.40fF
+C68 buffer_no_inv_x05_5/in buffer_no_inv_x05_4/inverter_min_1/in 0.07fF
+C69 avdd1p8 buffer_no_inv_x05_4/inverter_min_1/in 0.03fF
+C70 mux_2to1_logic_4/out mux_2to1_logic_6/sel_b 0.04fF
+C71 mux_2to1_logic_4/DinA mux_2to1_logic_6/sel_b 0.01fF
+C72 clk mux_2to1_logic_4/DinB 0.12fF
+C73 buffer_no_inv_x05_8/inverter_min_1/in mux_2to1_logic_3/DinA 0.12fF
+C74 mux_2to1_logic_0/out mux_2to1_logic_1/DinA 0.12fF
+C75 mux_2to1_logic_5/sel_b mux_2to1_logic_4/DinB 0.31fF
+C76 mux_2to1_logic_3/DinB buffer_no_inv_x05_7/in 0.10fF
+C77 clk mux_2to1_logic_1/DinA 0.01fF
+C78 mux_2to1_logic_1/DinA mux_2to1_logic_0/DinB 0.11fF
+C79 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_3/DinA 0.04fF
+C80 reg2 mux_2to1_logic_1/DinB 0.07fF
+C81 mux_2to1_logic_1/out mux_2to1_logic_1/DinA 0.05fF
+C82 buffer_no_inv_x05_3/inverter_min_1/in mux_2to1_logic_1/DinB 0.15fF
+C83 avdd1p8 buffer_no_inv_x05_0/inverter_min_1/in 0.01fF
+C84 avdd1p8 mux_2to1_logic_1/DinB 1.09fF
+C85 mux_2to1_logic_1/DinB buffer_no_inv_x05_5/in 0.15fF
+C86 mux_2to1_logic_4/DinA buffer_no_inv_x05_11/inverter_min_1/in 0.08fF
+C87 avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in 0.04fF
+C88 avdd1p8 buffer_no_inv_x05_13/in 0.10fF
+C89 mux_2to1_logic_0/sel_b buffer_no_inv_x05_1/inverter_min_1/in 0.01fF
+C90 avdd1p8 buffer_no_inv_x05_12/inverter_min_1/in 0.03fF
+C91 mux_2to1_logic_0/out mux_2to1_logic_2/out 0.05fF
+C92 mux_2to1_logic_5/out mux_2to1_logic_4/DinB 0.52fF
+C93 buffer_no_inv_x05_2/inverter_min_1/in mux_2to1_logic_0/DinB 0.12fF
+C94 mux_2to1_logic_5/out mux_2to1_logic_6/sel_b 0.20fF
+C95 mux_2to1_logic_2/out mux_2to1_logic_4/out 0.26fF
+C96 mux_2to1_logic_3/out mux_2to1_logic_4/out 1.18fF
+C97 mux_2to1_logic_3/out mux_2to1_logic_3/DinA 0.05fF
+C98 mux_2to1_logic_3/out mux_2to1_logic_4/DinA 0.12fF
+C99 reg1 mux_2to1_logic_2/out 1.41fF
+C100 mux_2to1_logic_3/out reg1 0.47fF
+C101 mux_2to1_logic_5/sel_b mux_2to1_logic_2/out 0.20fF
+C102 mux_2to1_logic_5/sel_b mux_2to1_logic_3/out 0.37fF
+C103 mux_2to1_logic_3/sel_b buffer_no_inv_x05_6/inverter_min_1/in 0.01fF
+C104 mux_2to1_logic_0/sel_b mux_2to1_logic_0/DinB 0.06fF
+C105 mux_2to1_logic_2/out mux_2to1_logic_1/out 0.35fF
+C106 mux_2to1_logic_2/sel_b mux_2to1_logic_1/DinB 0.04fF
+C107 reg2 mux_2to1_logic_4/sel_b 0.06fF
+C108 mux_2to1_logic_3/DinA buffer_no_inv_x05_7/in 0.13fF
+C109 avdd1p8 mux_2to1_logic_4/sel_b 0.07fF
+C110 reg2 avdd1p8 0.14fF
+C111 mux_2to1_logic_3/sel_b mux_2to1_logic_2/out 0.33fF
+C112 clk_out nand_logic_0/m1_21_n341# 0.02fF
+C113 buffer_no_inv_x05_3/inverter_min_1/in avdd1p8 0.03fF
+C114 buffer_no_inv_x05_7/inverter_min_1/in mux_2to1_logic_3/DinB 0.10fF
+C115 avdd1p8 buffer_no_inv_x05_5/in 0.09fF
+C116 mux_2to1_logic_5/out mux_2to1_logic_2/out 1.29fF
+C117 mux_2to1_logic_5/out mux_2to1_logic_3/out 0.07fF
+C118 buffer_no_inv_x05_13/in buffer_no_inv_x05_13/inverter_min_1/in 0.12fF
+C119 avdd1p8 reg0 0.05fF
+C120 buffer_no_inv_x05_3/in mux_2to1_logic_1/sel_b 0.01fF
+C121 mux_2to1_logic_6/sel_b mux_2to1_logic_4/DinB 0.28fF
+C122 reg2 mux_2to1_logic_2/sel_b 0.07fF
+C123 reg1 buffer_no_inv_x05_4/inverter_min_1/in 0.01fF
+C124 mux_2to1_logic_2/sel_b buffer_no_inv_x05_5/in 0.01fF
+C125 avdd1p8 mux_2to1_logic_2/sel_b 0.07fF
+C126 buffer_no_inv_x05_10/inverter_min_1/in buffer_no_inv_x05_11/in 0.07fF
+C127 mux_2to1_logic_3/DinB mux_2to1_logic_4/sel_b 0.04fF
+C128 avdd1p8 clk_out 0.04fF
+C129 reg2 mux_2to1_logic_3/DinB 0.08fF
+C130 buffer_no_inv_x05_1/in buffer_no_inv_x05_0/inverter_min_1/in 0.07fF
+C131 avdd1p8 mux_2to1_logic_3/DinB 0.82fF
+C132 mux_2to1_logic_0/out mux_2to1_logic_1/DinB 0.12fF
+C133 mux_2to1_logic_1/DinB mux_2to1_logic_3/DinA 0.07fF
+C134 avdd1p8 buffer_no_inv_x05_13/inverter_min_1/in 0.03fF
+C135 buffer_no_inv_x05_7/inverter_min_1/in mux_2to1_logic_3/DinA 0.21fF
+C136 mux_2to1_logic_4/DinA buffer_no_inv_x05_12/inverter_min_1/in 0.12fF
+C137 clk mux_2to1_logic_1/DinB 0.01fF
+C138 mux_2to1_logic_2/out mux_2to1_logic_4/DinB 0.07fF
+C139 mux_2to1_logic_3/out mux_2to1_logic_4/DinB 0.18fF
+C140 mux_2to1_logic_1/DinA buffer_no_inv_x05_2/inverter_min_1/in 0.10fF
+C141 clk buffer_no_inv_x05_13/in 0.07fF
+C142 mux_2to1_logic_2/out mux_2to1_logic_6/sel_b 0.31fF
+C143 avdd1p8 buffer_no_inv_x05_9/in 0.10fF
+C144 mux_2to1_logic_1/DinB mux_2to1_logic_1/out 0.23fF
+C145 reg2 buffer_no_inv_x05_1/in 0.01fF
+C146 mux_2to1_logic_1/DinB mux_2to1_logic_1/sel_b -0.06fF
+C147 mux_2to1_logic_0/out reg2 0.45fF
+C148 avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in 0.03fF
+C149 avdd1p8 buffer_no_inv_x05_1/in 0.09fF
+C150 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinA 0.16fF
+C151 reg2 mux_2to1_logic_3/DinA 0.33fF
+C152 reg2 mux_2to1_logic_4/DinA 0.31fF
+C153 mux_2to1_logic_0/out avdd1p8 0.43fF
+C154 reg2 reg1 2.15fF
+C155 clk reg2 0.12fF
+C156 avdd1p8 mux_2to1_logic_4/out 0.76fF
+C157 reg2 mux_2to1_logic_0/DinB 0.06fF
+C158 avdd1p8 mux_2to1_logic_3/DinA 0.81fF
+C159 avdd1p8 mux_2to1_logic_4/DinA 1.95fF
+C160 avdd1p8 reg1 0.08fF
+C161 mux_2to1_logic_3/out mux_2to1_logic_2/out 0.99fF
+C162 buffer_no_inv_x05_6/inverter_min_1/in buffer_no_inv_x05_7/in 0.07fF
+C163 clk avdd1p8 1.01fF
+C164 mux_2to1_logic_5/sel_b avdd1p8 0.09fF
+C165 buffer_no_inv_x05_9/in mux_2to1_logic_3/DinB 0.10fF
+C166 avdd1p8 mux_2to1_logic_0/DinB 1.33fF
+C167 reg1 reg0 0.01fF
+C168 buffer_no_inv_x05_3/in buffer_no_inv_x05_2/inverter_min_1/in 0.07fF
+C169 avdd1p8 buffer_no_inv_x05_10/inverter_min_1/in 0.03fF
+C170 avdd1p8 mux_2to1_logic_1/out 0.84fF
+C171 mux_2to1_logic_0/out mux_2to1_logic_2/sel_b 0.15fF
+C172 reg2 mux_2to1_logic_1/sel_b 0.13fF
+C173 reg2 mux_2to1_logic_3/sel_b 0.13fF
+C174 mux_2to1_logic_1/DinA buffer_no_inv_x05_4/inverter_min_1/in 0.12fF
+C175 avdd1p8 mux_2to1_logic_1/sel_b 0.09fF
+C176 avdd1p8 mux_2to1_logic_3/sel_b 0.09fF
+C177 mux_2to1_logic_2/sel_b reg1 0.06fF
+C178 clk clk_out 0.33fF
+C179 mux_2to1_logic_5/out avdd1p8 0.64fF
+C180 mux_2to1_logic_3/DinB mux_2to1_logic_3/DinA 1.18fF
+C181 mux_2to1_logic_2/sel_b mux_2to1_logic_1/out 0.19fF
+C182 mux_2to1_logic_4/DinA mux_2to1_logic_3/DinB 0.90fF
+C183 buffer_no_inv_x05_11/inverter_min_1/in buffer_no_inv_x05_11/in 0.14fF
+C184 buffer_no_inv_x05_13/in mux_2to1_logic_4/DinB 0.11fF
+C185 clk mux_2to1_logic_3/DinB 0.01fF
+C186 buffer_no_inv_x05_12/inverter_min_1/in mux_2to1_logic_4/DinB 0.07fF
+C187 mux_2to1_logic_5/sel_b mux_2to1_logic_3/DinB 0.01fF
+C188 mux_2to1_logic_5/out reg0 0.23fF
+C189 mux_2to1_logic_3/DinB buffer_no_inv_x05_10/inverter_min_1/in 0.12fF
+C190 mux_2to1_logic_1/DinB mux_2to1_logic_1/DinA 0.66fF
+C191 mux_2to1_logic_1/DinB buffer_no_inv_x05_6/inverter_min_1/in 0.12fF
+C192 mux_2to1_logic_3/sel_b mux_2to1_logic_3/DinB 0.21fF
+C193 buffer_no_inv_x05_1/inverter_min_1/in buffer_no_inv_x05_1/in 0.12fF
+C194 buffer_no_inv_x05_7/in avss1p8 1.12fF
+C195 buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.05fF
+C196 buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.04fF
+C197 buffer_no_inv_x05_5/in avss1p8 1.12fF
+C198 buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.04fF
+C199 buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.04fF
+C200 buffer_no_inv_x05_3/in avss1p8 1.13fF
+C201 buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.04fF
+C202 buffer_no_inv_x05_1/in avss1p8 1.12fF
+C203 buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.04fF
+C204 buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.05fF
+C205 clk avss1p8 2.54fF
+C206 buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C207 buffer_no_inv_x05_13/in avss1p8 1.12fF
+C208 mux_2to1_logic_4/DinB avss1p8 -7.83fF
+C209 buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.04fF
+C210 buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.04fF
+C211 buffer_no_inv_x05_11/in avss1p8 1.12fF
+C212 buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.04fF
+C213 nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C214 clk_out avss1p8 0.27fF
+C215 buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.04fF
+C216 mux_2to1_logic_6/sel_b avss1p8 2.08fF
+C217 nand_logic_0/in1 avss1p8 1.63fF
+C218 reg0 avss1p8 3.16fF
+C219 mux_2to1_logic_5/sel_b avss1p8 2.05fF
+C220 mux_2to1_logic_5/out avss1p8 -1.59fF
+C221 mux_2to1_logic_4/DinA avss1p8 -2.53fF
+C222 mux_2to1_logic_4/sel_b avss1p8 2.05fF
+C223 mux_2to1_logic_4/out avss1p8 -2.14fF
+C224 mux_2to1_logic_3/DinA avss1p8 0.02fF
+C225 mux_2to1_logic_3/sel_b avss1p8 2.05fF
+C226 mux_2to1_logic_3/out avss1p8 -2.13fF
+C227 mux_2to1_logic_3/DinB avss1p8 -4.89fF
+C228 mux_2to1_logic_2/sel_b avss1p8 2.05fF
+C229 mux_2to1_logic_2/out avss1p8 -1.34fF
+C230 reg1 avss1p8 4.95fF
+C231 mux_2to1_logic_1/DinA avss1p8 0.68fF
+C232 mux_2to1_logic_1/sel_b avss1p8 2.05fF
+C233 mux_2to1_logic_1/out avss1p8 -2.38fF
+C234 mux_2to1_logic_1/DinB avss1p8 -3.84fF
+C235 reg2 avss1p8 13.29fF
+C236 avdd1p8 avss1p8 125.49fF
+C237 mux_2to1_logic_0/sel_b avss1p8 2.04fF
+C238 mux_2to1_logic_0/out avss1p8 0.32fF
+C239 mux_2to1_logic_0/DinB avss1p8 -0.89fF
+C240 buffer_no_inv_x05_9/in avss1p8 1.12fF
+C241 buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.04fF
+C242 buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.04fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_72JNYZ a_n81_n100# w_n311_n310# a_n128_122# a_111_n100#
++ a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n128_122# a_n81_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n81_n100# a_n128_122# a_n173_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n128_122# a_15_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n81_n100# a_n173_n100# 0.29fF
+C1 a_111_n100# a_15_n100# 0.29fF
+C2 a_n81_n100# a_15_n100# 0.29fF
+C3 a_n128_122# a_15_n100# 0.10fF
+C4 a_n173_n100# a_15_n100# 0.11fF
+C5 a_n81_n100# a_111_n100# 0.11fF
+C6 a_111_n100# a_n173_n100# 0.06fF
+C7 a_n81_n100# a_n128_122# 0.10fF
+C8 a_111_n100# w_n311_n310# 0.15fF
+C9 a_15_n100# w_n311_n310# 0.11fF
+C10 a_n81_n100# w_n311_n310# 0.11fF
+C11 a_n173_n100# w_n311_n310# 0.15fF
+C12 a_n128_122# w_n311_n310# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XL9AN VSUBS w_n311_n319# a_n81_n100# a_111_n100#
++ a_n129_131# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_131# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_131# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_131# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n81_n100# a_15_n100# 0.29fF
+C1 a_n81_n100# a_n173_n100# 0.29fF
+C2 a_n81_n100# w_n311_n319# 0.08fF
+C3 a_n81_n100# a_n129_131# 0.08fF
+C4 a_15_n100# a_n173_n100# 0.11fF
+C5 a_15_n100# w_n311_n319# 0.08fF
+C6 a_15_n100# a_n129_131# 0.08fF
+C7 w_n311_n319# a_n173_n100# 0.12fF
+C8 w_n311_n319# a_n129_131# 0.16fF
+C9 a_n81_n100# a_111_n100# 0.11fF
+C10 a_15_n100# a_111_n100# 0.29fF
+C11 a_111_n100# a_n173_n100# 0.06fF
+C12 w_n311_n319# a_111_n100# 0.12fF
+C13 a_111_n100# VSUBS 0.03fF
+C14 a_15_n100# VSUBS 0.03fF
+C15 a_n81_n100# VSUBS 0.03fF
+C16 a_n173_n100# VSUBS 0.03fF
+C17 a_n129_131# VSUBS 0.32fF
+C18 w_n311_n319# VSUBS 2.34fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XUYGK VSUBS a_n269_n100# a_n81_n100# w_n407_n319#
++ a_111_n100# a_n177_n100# a_15_n100# a_207_n100# a_n225_131#
+X0 a_207_n100# a_n225_131# a_111_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_131# a_n81_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n225_131# a_15_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n225_131# a_n177_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_131# a_n269_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n269_n100# a_111_n100# 0.05fF
+C1 a_111_n100# a_207_n100# 0.29fF
+C2 a_15_n100# a_111_n100# 0.29fF
+C3 a_n225_131# a_n177_n100# 0.08fF
+C4 a_n81_n100# w_n407_n319# 0.06fF
+C5 a_n269_n100# a_15_n100# 0.06fF
+C6 a_n81_n100# a_111_n100# 0.11fF
+C7 a_15_n100# a_207_n100# 0.11fF
+C8 a_n225_131# w_n407_n319# 0.25fF
+C9 a_n177_n100# w_n407_n319# 0.05fF
+C10 a_n225_131# a_111_n100# 0.08fF
+C11 a_n269_n100# a_n81_n100# 0.11fF
+C12 a_n81_n100# a_207_n100# 0.06fF
+C13 a_15_n100# a_n81_n100# 0.29fF
+C14 a_111_n100# a_n177_n100# 0.06fF
+C15 a_15_n100# a_n225_131# 0.08fF
+C16 a_111_n100# w_n407_n319# 0.05fF
+C17 a_n269_n100# a_n177_n100# 0.29fF
+C18 a_207_n100# a_n177_n100# 0.05fF
+C19 a_15_n100# a_n177_n100# 0.11fF
+C20 a_n225_131# a_n81_n100# 0.08fF
+C21 a_n269_n100# w_n407_n319# 0.10fF
+C22 a_207_n100# w_n407_n319# 0.10fF
+C23 a_15_n100# w_n407_n319# 0.06fF
+C24 a_n81_n100# a_n177_n100# 0.29fF
+C25 a_207_n100# VSUBS 0.03fF
+C26 a_111_n100# VSUBS 0.03fF
+C27 a_15_n100# VSUBS 0.03fF
+C28 a_n81_n100# VSUBS 0.03fF
+C29 a_n177_n100# VSUBS 0.03fF
+C30 a_n269_n100# VSUBS 0.03fF
+C31 a_n225_131# VSUBS 0.54fF
+C32 w_n407_n319# VSUBS 2.92fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_2AP43D a_15_n81# a_n33_41# w_n211_n229# a_n73_n81#
+X0 a_15_n81# a_n33_41# a_n73_n81# w_n211_n229# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=500000u l=150000u
+C0 a_15_n81# a_n73_n81# 0.17fF
+C1 a_n73_n81# a_n33_41# 0.02fF
+C2 a_15_n81# a_n33_41# 0.02fF
+C3 a_15_n81# w_n211_n229# 0.12fF
+C4 a_n73_n81# w_n211_n229# 0.12fF
+C5 a_n33_41# w_n211_n229# 0.18fF
+.ends
+
+.subckt res_amp_lin clk vctrl avdd1p8 avss1p8 a_3747_261# vp inn outn outp inp
+Xsky130_fd_pr__pfet_01v8_2XL9AN_0 avss1p8 avdd1p8 a_3747_261# a_3747_261# clk avdd1p8
++ avdd1p8 sky130_fd_pr__pfet_01v8_2XL9AN
+Xsky130_fd_pr__pfet_01v8_2XUYGK_0 avss1p8 a_3747_261# a_3747_261# avdd1p8 a_3747_261#
++ vp vp vp vctrl sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_1 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_0 avss1p8 clk avss1p8 outp sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_2 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_1 avss1p8 clk avss1p8 outn sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_3 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_4 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_5 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_6 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_7 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_8 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+C0 avdd1p8 inn 1.05fF
+C1 vctrl clk 0.02fF
+C2 clk avdd1p8 2.36fF
+C3 vctrl a_3747_261# 0.76fF
+C4 outn avdd1p8 1.33fF
+C5 a_3747_261# avdd1p8 1.24fF
+C6 vp avdd1p8 6.92fF
+C7 avdd1p8 inp 1.02fF
+C8 avdd1p8 outp 1.56fF
+C9 outn inn 1.15fF
+C10 vp inn 0.84fF
+C11 inp inn 2.67fF
+C12 clk outn 0.71fF
+C13 clk a_3747_261# 0.44fF
+C14 vp clk 0.79fF
+C15 clk inp 0.06fF
+C16 vp a_3747_261# 1.08fF
+C17 vp outn 4.23fF
+C18 outn inp 5.59fF
+C19 outp inn 5.76fF
+C20 vp inp 0.78fF
+C21 vctrl avdd1p8 1.19fF
+C22 clk outp 0.56fF
+C23 outn outp 4.18fF
+C24 vp outp 4.81fF
+C25 inp outp 1.28fF
+C26 outn avss1p8 0.69fF
+C27 inp avss1p8 -0.11fF
+C28 outp avss1p8 -0.62fF
+C29 vp avss1p8 -4.89fF
+C30 inn avss1p8 0.23fF
+C31 avdd1p8 avss1p8 31.50fF
+C32 clk avss1p8 1.49fF
+C33 a_3747_261# avss1p8 -0.95fF
+C34 vctrl avss1p8 -0.82fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_595QY5 a_n269_n100# a_n81_n100# a_111_n100# a_n177_n100#
++ a_15_n100# w_n407_n310# a_207_n100# a_n225_n188#
+X0 a_207_n100# a_n225_n188# a_111_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_n188# a_n81_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n225_n188# a_n177_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_111_n100# a_n225_n188# a_15_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_n188# a_n269_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n81_n100# a_n177_n100# 0.29fF
+C1 a_n177_n100# a_n269_n100# 0.29fF
+C2 a_15_n100# a_n81_n100# 0.29fF
+C3 a_15_n100# a_n269_n100# 0.06fF
+C4 a_n225_n188# a_n81_n100# 0.10fF
+C5 a_111_n100# a_n81_n100# 0.11fF
+C6 a_15_n100# a_n177_n100# 0.11fF
+C7 a_111_n100# a_n269_n100# 0.05fF
+C8 a_n225_n188# a_n177_n100# 0.10fF
+C9 a_15_n100# a_n225_n188# 0.10fF
+C10 a_111_n100# a_n177_n100# 0.06fF
+C11 a_15_n100# a_111_n100# 0.29fF
+C12 a_n81_n100# a_207_n100# 0.06fF
+C13 a_n225_n188# a_111_n100# 0.10fF
+C14 a_n177_n100# a_207_n100# 0.05fF
+C15 a_15_n100# a_207_n100# 0.11fF
+C16 a_n81_n100# a_n269_n100# 0.11fF
+C17 a_111_n100# a_207_n100# 0.29fF
+C18 a_207_n100# w_n407_n310# 0.13fF
+C19 a_111_n100# w_n407_n310# 0.08fF
+C20 a_15_n100# w_n407_n310# 0.09fF
+C21 a_n81_n100# w_n407_n310# 0.09fF
+C22 a_n177_n100# w_n407_n310# 0.08fF
+C23 a_n269_n100# w_n407_n310# 0.13fF
+C24 a_n225_n188# w_n407_n310# 0.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_9B2JY7 a_n317_n100# a_n33_n100# a_n225_n100# a_n271_122#
++ a_63_n100# a_n129_n100# w_n455_n310# a_255_n100# a_159_n100#
+X0 a_63_n100# a_n271_122# a_n33_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n271_122# a_n129_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n271_122# a_63_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n271_122# a_159_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n225_n100# a_n271_122# a_n317_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n129_n100# a_n271_122# a_n225_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n129_n100# a_255_n100# 0.05fF
+C1 a_n129_n100# a_n33_n100# 0.29fF
+C2 a_255_n100# a_159_n100# 0.29fF
+C3 a_n33_n100# a_159_n100# 0.11fF
+C4 a_n225_n100# a_n33_n100# 0.11fF
+C5 a_255_n100# a_63_n100# 0.11fF
+C6 a_n33_n100# a_63_n100# 0.29fF
+C7 a_n129_n100# a_159_n100# 0.06fF
+C8 a_n225_n100# a_n129_n100# 0.29fF
+C9 a_n225_n100# a_159_n100# 0.05fF
+C10 a_n129_n100# a_63_n100# 0.11fF
+C11 a_63_n100# a_159_n100# 0.29fF
+C12 a_n225_n100# a_63_n100# 0.06fF
+C13 a_n33_n100# a_n271_122# 0.10fF
+C14 a_n129_n100# a_n271_122# 0.10fF
+C15 a_n271_122# a_159_n100# 0.10fF
+C16 a_n225_n100# a_n271_122# 0.10fF
+C17 a_n33_n100# a_n317_n100# 0.06fF
+C18 a_n271_122# a_63_n100# 0.10fF
+C19 a_n129_n100# a_n317_n100# 0.11fF
+C20 a_n33_n100# a_255_n100# 0.06fF
+C21 a_n225_n100# a_n317_n100# 0.29fF
+C22 a_63_n100# a_n317_n100# 0.05fF
+C23 a_255_n100# w_n455_n310# 0.13fF
+C24 a_159_n100# w_n455_n310# 0.08fF
+C25 a_63_n100# w_n455_n310# 0.07fF
+C26 a_n33_n100# w_n455_n310# 0.08fF
+C27 a_n129_n100# w_n455_n310# 0.07fF
+C28 a_n225_n100# w_n455_n310# 0.08fF
+C29 a_n317_n100# w_n455_n310# 0.13fF
+C30 a_n271_122# w_n455_n310# 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_MVT43V a_n33_n100# w_n263_n310# a_63_n100# a_n79_122#
++ a_n125_n100#
+X0 a_63_n100# a_n79_122# a_n33_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n79_122# a_n125_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n125_n100# a_n33_n100# 0.29fF
+C1 a_n33_n100# a_n79_122# 0.11fF
+C2 a_n33_n100# a_63_n100# 0.29fF
+C3 a_n125_n100# a_n79_122# 0.02fF
+C4 a_n125_n100# a_63_n100# 0.11fF
+C5 a_n79_122# a_63_n100# 0.02fF
+C6 a_63_n100# w_n263_n310# 0.16fF
+C7 a_n33_n100# w_n263_n310# 0.12fF
+C8 a_n125_n100# w_n263_n310# 0.16fF
+C9 a_n79_122# w_n263_n310# 0.37fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_NMSMYT a_n33_n100# a_n321_n100# a_n225_n100# w_n551_n310#
++ a_63_n100# a_n368_122# a_n129_n100# a_351_n100# a_255_n100# a_n413_n100# a_159_n100#
+X0 a_63_n100# a_n368_122# a_n33_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n368_122# a_n129_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n368_122# a_63_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n368_122# a_159_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_351_n100# a_n368_122# a_255_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n321_n100# a_n368_122# a_n413_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n225_n100# a_n368_122# a_n321_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n129_n100# a_n368_122# a_n225_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n225_n100# a_63_n100# 0.06fF
+C1 a_n129_n100# a_n33_n100# 0.29fF
+C2 a_n33_n100# a_255_n100# 0.06fF
+C3 a_n321_n100# a_n129_n100# 0.11fF
+C4 a_351_n100# a_159_n100# 0.11fF
+C5 a_n129_n100# a_n413_n100# 0.06fF
+C6 a_n368_122# a_n33_n100# 0.10fF
+C7 a_n368_122# a_n321_n100# 0.10fF
+C8 a_351_n100# a_63_n100# 0.06fF
+C9 a_n129_n100# a_255_n100# 0.05fF
+C10 a_n33_n100# a_159_n100# 0.11fF
+C11 a_n368_122# a_n129_n100# 0.10fF
+C12 a_n368_122# a_255_n100# 0.10fF
+C13 a_n33_n100# a_n225_n100# 0.11fF
+C14 a_n321_n100# a_n225_n100# 0.29fF
+C15 a_n33_n100# a_63_n100# 0.29fF
+C16 a_n413_n100# a_n225_n100# 0.11fF
+C17 a_n321_n100# a_63_n100# 0.05fF
+C18 a_n129_n100# a_159_n100# 0.06fF
+C19 a_159_n100# a_255_n100# 0.29fF
+C20 a_n129_n100# a_n225_n100# 0.29fF
+C21 a_n33_n100# a_351_n100# 0.05fF
+C22 a_n368_122# a_159_n100# 0.10fF
+C23 a_n129_n100# a_63_n100# 0.11fF
+C24 a_255_n100# a_63_n100# 0.11fF
+C25 a_n368_122# a_n225_n100# 0.10fF
+C26 a_n368_122# a_63_n100# 0.10fF
+C27 a_351_n100# a_255_n100# 0.29fF
+C28 a_n321_n100# a_n33_n100# 0.06fF
+C29 a_n225_n100# a_159_n100# 0.05fF
+C30 a_n413_n100# a_n33_n100# 0.05fF
+C31 a_159_n100# a_63_n100# 0.29fF
+C32 a_n321_n100# a_n413_n100# 0.29fF
+C33 a_351_n100# w_n551_n310# 0.13fF
+C34 a_255_n100# w_n551_n310# 0.08fF
+C35 a_159_n100# w_n551_n310# 0.07fF
+C36 a_63_n100# w_n551_n310# 0.06fF
+C37 a_n33_n100# w_n551_n310# 0.04fF
+C38 a_n129_n100# w_n551_n310# 0.06fF
+C39 a_n225_n100# w_n551_n310# 0.07fF
+C40 a_n321_n100# w_n551_n310# 0.08fF
+C41 a_n413_n100# w_n551_n310# 0.13fF
+C42 a_n368_122# w_n551_n310# 1.26fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XAYTAL VSUBS w_n311_n319# a_n81_n100# a_n129_n197#
++ a_111_n100# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_n197# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_n197# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_n197# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_111_n100# a_n81_n100# 0.11fF
+C1 a_15_n100# a_n81_n100# 0.29fF
+C2 a_111_n100# a_15_n100# 0.29fF
+C3 a_n129_n197# a_n81_n100# 0.08fF
+C4 a_n129_n197# a_15_n100# 0.08fF
+C5 w_n311_n319# a_n81_n100# 0.08fF
+C6 a_111_n100# w_n311_n319# 0.12fF
+C7 a_n173_n100# a_n81_n100# 0.29fF
+C8 a_111_n100# a_n173_n100# 0.06fF
+C9 w_n311_n319# a_15_n100# 0.08fF
+C10 a_n129_n197# w_n311_n319# 0.17fF
+C11 a_n173_n100# a_15_n100# 0.11fF
+C12 a_n173_n100# w_n311_n319# 0.12fF
+C13 a_111_n100# VSUBS 0.03fF
+C14 a_15_n100# VSUBS 0.03fF
+C15 a_n81_n100# VSUBS 0.03fF
+C16 a_n173_n100# VSUBS 0.03fF
+C17 a_n129_n197# VSUBS 0.34fF
+C18 w_n311_n319# VSUBS 2.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_B2JNY3 a_n33_n100# a_63_n100# a_n221_n100# a_n129_n100#
++ w_n359_n310# a_n176_122# a_159_n100#
+X0 a_63_n100# a_n176_122# a_n33_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n176_122# a_n129_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n176_122# a_63_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n176_122# a_n221_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n129_n100# a_n33_n100# 0.29fF
+C1 a_n129_n100# a_159_n100# 0.06fF
+C2 a_n129_n100# a_n221_n100# 0.29fF
+C3 a_159_n100# a_n33_n100# 0.11fF
+C4 a_n129_n100# a_63_n100# 0.11fF
+C5 a_n33_n100# a_n221_n100# 0.11fF
+C6 a_n129_n100# a_n176_122# 0.10fF
+C7 a_159_n100# a_n221_n100# 0.05fF
+C8 a_63_n100# a_n33_n100# 0.29fF
+C9 a_159_n100# a_63_n100# 0.29fF
+C10 a_n176_122# a_n33_n100# 0.10fF
+C11 a_63_n100# a_n221_n100# 0.06fF
+C12 a_63_n100# a_n176_122# 0.10fF
+C13 a_159_n100# w_n359_n310# 0.13fF
+C14 a_63_n100# w_n359_n310# 0.10fF
+C15 a_n33_n100# w_n359_n310# 0.10fF
+C16 a_n129_n100# w_n359_n310# 0.10fF
+C17 a_n221_n100# w_n359_n310# 0.13fF
+C18 a_n176_122# w_n359_n310# 0.64fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XACJHL VSUBS a_n81_n197# w_n263_n319# a_n33_n100#
++ a_63_n100# a_n125_n100#
+X0 a_63_n100# a_n81_n197# a_n33_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_n197# a_n125_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n33_n100# w_n263_n319# 0.09fF
+C1 a_n81_n197# w_n263_n319# 0.11fF
+C2 a_63_n100# a_n125_n100# 0.11fF
+C3 a_n33_n100# a_n125_n100# 0.29fF
+C4 a_n33_n100# a_63_n100# 0.29fF
+C5 a_n33_n100# a_n81_n197# 0.08fF
+C6 w_n263_n319# a_n125_n100# 0.13fF
+C7 w_n263_n319# a_63_n100# 0.13fF
+C8 a_63_n100# VSUBS 0.03fF
+C9 a_n33_n100# VSUBS 0.03fF
+C10 a_n125_n100# VSUBS 0.03fF
+C11 a_n81_n197# VSUBS 0.23fF
+C12 w_n263_n319# VSUBS 2.05fF
+.ends
+
+.subckt iref_ctrl_res_amp m1_n356_n363# avss1p8 vctrl reg2 avdd1p8 reg0 m1_1996_n363#
++ reg1 iref m1_964_n363# m1_511_801# m1_1384_n363#
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 iref m1_n356_n363# m1_n356_n363# iref iref iref
++ avss1p8 iref m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_n356_n363# m1_n356_n363# avdd1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_0 m1_964_n363# avss1p8 vctrl iref vctrl sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_1 m1_964_n363# avss1p8 avss1p8 reg0 avss1p8 sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_0 vctrl m1_1996_n363# vctrl avss1p8 m1_1996_n363#
++ iref m1_1996_n363# vctrl m1_1996_n363# vctrl vctrl sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_1 avss1p8 m1_1996_n363# avss1p8 avss1p8 m1_1996_n363#
++ reg2 m1_1996_n363# avss1p8 m1_1996_n363# avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 m1_448_n363# avss1p8 iref m1_448_n363# vctrl
++ vctrl sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 m1_448_n363# avss1p8 avdd1p8 m1_448_n363# avss1p8
++ avss1p8 sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__pfet_01v8_XAYTAL_0 avss1p8 avdd1p8 m1_511_801# avss1p8 m1_511_801#
++ avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8_XAYTAL
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_0 vctrl m1_1384_n363# vctrl m1_1384_n363# avss1p8
++ iref vctrl sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_1 avss1p8 m1_1384_n363# avss1p8 m1_1384_n363#
++ avss1p8 reg1 avss1p8 sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__pfet_01v8_XACJHL_0 avss1p8 vctrl avdd1p8 m1_511_801# vctrl vctrl sky130_fd_pr__pfet_01v8_XACJHL
+C0 m1_448_n363# m1_964_n363# 0.24fF
+C1 m1_1996_n363# m1_1384_n363# 0.18fF
+C2 m1_964_n363# reg0 0.47fF
+C3 iref reg2 0.03fF
+C4 m1_448_n363# vctrl 1.16fF
+C5 reg1 m1_1384_n363# 0.85fF
+C6 vctrl reg0 0.04fF
+C7 m1_448_n363# m1_n356_n363# 0.17fF
+C8 m1_448_n363# avdd1p8 0.77fF
+C9 m1_511_801# vctrl 1.08fF
+C10 avdd1p8 reg0 0.03fF
+C11 iref m1_1384_n363# 0.22fF
+C12 m1_511_801# avdd1p8 1.05fF
+C13 vctrl m1_964_n363# 0.52fF
+C14 reg1 reg0 0.04fF
+C15 vctrl m1_n356_n363# 0.08fF
+C16 vctrl avdd1p8 0.52fF
+C17 iref m1_448_n363# 0.29fF
+C18 avdd1p8 m1_n356_n363# 1.41fF
+C19 iref reg0 0.02fF
+C20 vctrl m1_1996_n363# 1.72fF
+C21 iref m1_511_801# 0.05fF
+C22 iref m1_964_n363# 0.11fF
+C23 vctrl reg1 0.06fF
+C24 m1_1384_n363# reg0 0.06fF
+C25 m1_1996_n363# reg1 0.06fF
+C26 iref vctrl 2.27fF
+C27 vctrl reg2 0.07fF
+C28 iref m1_n356_n363# 1.89fF
+C29 iref avdd1p8 0.32fF
+C30 m1_1384_n363# m1_964_n363# 0.18fF
+C31 iref m1_1996_n363# 0.41fF
+C32 m1_1996_n363# reg2 1.30fF
+C33 vctrl m1_1384_n363# 0.95fF
+C34 iref reg1 0.03fF
+C35 reg1 reg2 0.04fF
+C36 m1_511_801# avss1p8 -1.62fF
+C37 m1_1384_n363# avss1p8 1.30fF
+C38 reg1 avss1p8 1.36fF
+C39 m1_448_n363# avss1p8 -0.27fF
+C40 vctrl avss1p8 2.17fF
+C41 m1_1996_n363# avss1p8 -0.61fF
+C42 reg2 avss1p8 1.98fF
+C43 reg0 avss1p8 0.44fF
+C44 m1_964_n363# avss1p8 -0.38fF
+C45 avdd1p8 avss1p8 6.02fF
+C46 m1_n356_n363# avss1p8 1.89fF
+C47 iref avss1p8 2.30fF
+.ends
+
+.subckt res_amp_lin_prog delay_cell_buff_0/mux_2to1_logic_0/out iref_ctrl_res_amp_0/m1_964_n363#
++ delay_reg2 avdd1p8 inp delay_cell_buff_0/mux_2to1_logic_3/DinA delay_cell_buff_0/mux_2to1_logic_3/out
++ res_amp_lin_0/vctrl iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_0/clk delay_cell_buff_0/nand_logic_0/in1
++ outp_cap avss1p8 outn_cap clk delay_cell_buff_0/mux_2to1_logic_1/sel_b delay_reg0
++ delay_cell_buff_0/mux_2to1_logic_4/DinA delay_cell_buff_0/mux_2to1_logic_4/DinB
++ outn delay_cell_buff_0/mux_2to1_logic_1/DinA outp delay_cell_buff_0/mux_2to1_logic_5/out
++ delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in delay_cell_buff_0/mux_2to1_logic_3/DinB
++ iref_reg0 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in iref_reg1 iref_reg2
++ iref_ctrl_res_amp_0/m1_1384_n363# delay_cell_buff_0/buffer_no_inv_x05_3/in res_amp_lin_0/vp
++ delay_cell_buff_0/nand_logic_0/m1_21_n341# delay_cell_buff_0/mux_2to1_logic_1/out
++ delay_cell_buff_0/mux_2to1_logic_2/out delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ iref delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in iref_ctrl_res_amp_0/m1_n356_n363#
++ res_amp_lin_0/a_3747_261# delay_reg1 delay_cell_buff_0/buffer_no_inv_x05_13/in inn
++ delay_cell_buff_0/mux_2to1_logic_4/out iref_ctrl_res_amp_0/m1_1996_n363# delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in
++ inverter_min_x4_0/out delay_cell_buff_0/mux_2to1_logic_4/sel_b rst
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_0 avss1p8 outn_cap avdd1p8 outn_cap res_amp_lin_0/clk
++ outn outn outn outn_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_1 avss1p8 outp_cap avdd1p8 outp_cap res_amp_lin_0/clk
++ outp outp outp outp_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xdelay_cell_buff_0 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in delay_reg2
++ avss1p8 delay_cell_buff_0/mux_2to1_logic_4/DinA avdd1p8 delay_cell_buff_0/buffer_no_inv_x05_13/in
++ clk delay_cell_buff_0/mux_2to1_logic_3/DinA res_amp_lin_0/clk delay_cell_buff_0/mux_2to1_logic_3/DinB
++ delay_reg0 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in delay_reg1 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ delay_cell_buff_0/nand_logic_0/in1 delay_cell_buff_0/mux_2to1_logic_2/out delay_cell_buff_0/mux_2to1_logic_4/sel_b
++ delay_cell_buff_0/mux_2to1_logic_4/out delay_cell_buff_0/mux_2to1_logic_1/DinA delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ delay_cell_buff_0/buffer_no_inv_x05_3/in delay_cell_buff_0/mux_2to1_logic_5/out
++ delay_cell_buff_0/mux_2to1_logic_0/out delay_cell_buff_0/mux_2to1_logic_4/DinB delay_cell_buff_0/mux_2to1_logic_3/out
++ delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in delay_cell_buff_0/mux_2to1_logic_1/out
++ avss1p8 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ delay_cell_buff
+Xinverter_min_x4_0 avdd1p8 res_amp_lin_0/clk avss1p8 inverter_min_x4_0/out inverter_min_x4
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 outn_cap avss1p8 rst outn_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xres_amp_lin_0 res_amp_lin_0/clk res_amp_lin_0/vctrl avdd1p8 avss1p8 res_amp_lin_0/a_3747_261#
++ res_amp_lin_0/vp inn outn outp inp res_amp_lin
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 outp_cap avss1p8 rst outp_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_0 outn outn outn outn_cap outn_cap avss1p8 outn_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_1 outp outp outp outp_cap outp_cap avss1p8 outp_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xiref_ctrl_res_amp_0 iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 res_amp_lin_0/vctrl
++ iref_reg2 avdd1p8 iref_reg0 iref_ctrl_res_amp_0/m1_1996_n363# iref_reg1 iref iref_ctrl_res_amp_0/m1_964_n363#
++ iref_ctrl_res_amp_0/m1_511_801# iref_ctrl_res_amp_0/m1_1384_n363# iref_ctrl_res_amp
+C0 outn_cap outn 1.90fF
+C1 inverter_min_x4_0/out rst 0.01fF
+C2 res_amp_lin_0/clk avdd1p8 1.99fF
+C3 outn_cap inverter_min_x4_0/out 0.57fF
+C4 outn_cap avdd1p8 0.26fF
+C5 res_amp_lin_0/vctrl avdd1p8 1.42fF
+C6 outp outp_cap 1.90fF
+C7 res_amp_lin_0/vctrl iref 0.10fF
+C8 res_amp_lin_0/clk outn_cap 1.04fF
+C9 inverter_min_x4_0/out outp_cap 0.57fF
+C10 outn_cap rst 0.34fF
+C11 outn inverter_min_x4_0/out 0.32fF
+C12 inverter_min_x4_0/out outp 0.32fF
+C13 avdd1p8 outp_cap 0.25fF
+C14 outn avdd1p8 0.36fF
+C15 res_amp_lin_0/clk outp_cap 1.04fF
+C16 outp avdd1p8 0.34fF
+C17 res_amp_lin_0/clk outn 0.09fF
+C18 res_amp_lin_0/clk outp 0.09fF
+C19 rst outp_cap 0.34fF
+C20 res_amp_lin_0/clk inverter_min_x4_0/out 0.14fF
+C21 iref_ctrl_res_amp_0/m1_511_801# avss1p8 -1.87fF
+C22 iref_ctrl_res_amp_0/m1_1384_n363# avss1p8 0.47fF
+C23 iref_reg1 avss1p8 0.47fF
+C24 iref_ctrl_res_amp_0/m1_448_n363# avss1p8 -1.10fF
+C25 res_amp_lin_0/vctrl avss1p8 -1.88fF
+C26 iref_ctrl_res_amp_0/m1_1996_n363# avss1p8 -2.23fF
+C27 iref_reg2 avss1p8 -0.15fF
+C28 iref_reg0 avss1p8 -0.42fF
+C29 iref_ctrl_res_amp_0/m1_964_n363# avss1p8 -1.03fF
+C30 iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 0.51fF
+C31 iref avss1p8 0.07fF
+C32 outn avss1p8 1.87fF
+C33 inp avss1p8 -0.35fF
+C34 outp avss1p8 -4.58fF
+C35 res_amp_lin_0/vp avss1p8 -4.89fF
+C36 inn avss1p8 0.17fF
+C37 res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
+C38 outn_cap avss1p8 -1.33fF
+C39 rst avss1p8 0.58fF
+C40 res_amp_lin_0/clk avss1p8 5.34fF
+C41 inverter_min_x4_0/out avss1p8 7.53fF
+C42 delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
+C43 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C44 delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C45 delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C46 delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C47 delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C48 delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C49 delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C50 delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C51 delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C52 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C53 clk avss1p8 -4.09fF
+C54 delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C55 delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C56 delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C57 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C58 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C59 delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C60 delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C61 delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C62 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
+C63 delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C64 delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
+C65 delay_reg0 avss1p8 2.77fF
+C66 delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C67 delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
+C68 delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
+C69 delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C70 delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
+C71 delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C72 delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C73 delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C74 delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C75 delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
+C76 delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C77 delay_reg1 avss1p8 3.80fF
+C78 delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
+C79 delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
+C80 delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C81 delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C82 delay_reg2 avss1p8 11.07fF
+C83 avdd1p8 avss1p8 177.60fF
+C84 delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.03fF
+C85 delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C86 delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C87 delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
+C88 delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
+C89 delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
+C90 outp_cap avss1p8 -6.93fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_U5ZKVF VSUBS m3_n700_n850# c1_n600_n750#
+X0 c1_n600_n750# m3_n700_n850# sky130_fd_pr__cap_mim_m3_1 l=7.5e+06u w=5.5e+06u
+C0 m3_n700_n850# c1_n600_n750# 5.48fF
+C1 m3_n700_n850# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_D3F744 VSUBS a_n285_n236# a_355_n236# a_n29_n236#
++ a_n413_n236# a_99_n236# a_n611_n262# a_483_n236# a_n669_n236# w_n807_n384# a_n157_n236#
++ a_n541_n236# a_227_n236# a_611_n236#
+X0 a_n157_n236# a_n611_n262# a_n285_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_611_n236# a_n611_n262# a_483_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_227_n236# a_n611_n262# a_99_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_n285_n236# a_n611_n262# a_n413_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_99_n236# a_n611_n262# a_n29_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X5 a_355_n236# a_n611_n262# a_227_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X6 a_483_n236# a_n611_n262# a_355_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X7 a_n29_n236# a_n611_n262# a_n157_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X8 a_n413_n236# a_n611_n262# a_n541_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X9 a_n541_n236# a_n611_n262# a_n669_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+C0 a_611_n236# a_355_n236# 0.15fF
+C1 a_n413_n236# a_n157_n236# 0.15fF
+C2 a_n29_n236# a_n157_n236# 0.36fF
+C3 a_n541_n236# a_n157_n236# 0.09fF
+C4 a_99_n236# w_n807_n384# 0.02fF
+C5 a_483_n236# a_611_n236# 0.36fF
+C6 a_n285_n236# a_n157_n236# 0.36fF
+C7 a_355_n236# w_n807_n384# 0.06fF
+C8 a_n611_n262# w_n807_n384# 0.60fF
+C9 a_355_n236# a_99_n236# 0.15fF
+C10 a_n611_n262# a_99_n236# 0.08fF
+C11 a_483_n236# w_n807_n384# 0.09fF
+C12 a_483_n236# a_99_n236# 0.09fF
+C13 a_n611_n262# a_355_n236# 0.08fF
+C14 a_227_n236# a_n157_n236# 0.09fF
+C15 a_n413_n236# w_n807_n384# 0.06fF
+C16 a_n29_n236# w_n807_n384# 0.02fF
+C17 a_n541_n236# w_n807_n384# 0.09fF
+C18 a_n29_n236# a_99_n236# 0.36fF
+C19 a_483_n236# a_355_n236# 0.36fF
+C20 a_n285_n236# w_n807_n384# 0.02fF
+C21 a_483_n236# a_n611_n262# 0.08fF
+C22 a_n285_n236# a_99_n236# 0.09fF
+C23 a_227_n236# a_611_n236# 0.09fF
+C24 a_n29_n236# a_355_n236# 0.09fF
+C25 a_n611_n262# a_n413_n236# 0.08fF
+C26 a_n29_n236# a_n611_n262# 0.08fF
+C27 a_n669_n236# w_n807_n384# 0.19fF
+C28 a_n611_n262# a_n541_n236# 0.08fF
+C29 a_n611_n262# a_n285_n236# 0.08fF
+C30 a_227_n236# w_n807_n384# 0.02fF
+C31 a_n29_n236# a_n413_n236# 0.09fF
+C32 a_227_n236# a_99_n236# 0.36fF
+C33 a_n413_n236# a_n541_n236# 0.36fF
+C34 a_n157_n236# w_n807_n384# 0.02fF
+C35 a_n413_n236# a_n285_n236# 0.36fF
+C36 a_n29_n236# a_n285_n236# 0.15fF
+C37 a_n285_n236# a_n541_n236# 0.15fF
+C38 a_99_n236# a_n157_n236# 0.15fF
+C39 a_227_n236# a_355_n236# 0.36fF
+C40 a_227_n236# a_n611_n262# 0.08fF
+C41 a_n413_n236# a_n669_n236# 0.15fF
+C42 a_611_n236# w_n807_n384# 0.19fF
+C43 a_n541_n236# a_n669_n236# 0.36fF
+C44 a_227_n236# a_483_n236# 0.15fF
+C45 a_n611_n262# a_n157_n236# 0.08fF
+C46 a_n285_n236# a_n669_n236# 0.09fF
+C47 a_n29_n236# a_227_n236# 0.15fF
+C48 a_611_n236# VSUBS 0.03fF
+C49 a_483_n236# VSUBS 0.03fF
+C50 a_355_n236# VSUBS 0.03fF
+C51 a_227_n236# VSUBS 0.03fF
+C52 a_99_n236# VSUBS 0.03fF
+C53 a_n29_n236# VSUBS 0.03fF
+C54 a_n157_n236# VSUBS 0.03fF
+C55 a_n285_n236# VSUBS 0.03fF
+C56 a_n413_n236# VSUBS 0.03fF
+C57 a_n541_n236# VSUBS 0.03fF
+C58 a_n669_n236# VSUBS 0.03fF
+C59 a_n611_n262# VSUBS 1.37fF
+C60 w_n807_n384# VSUBS 6.11fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_VCU74W VSUBS a_495_n100# a_n81_n100# a_399_n100# a_687_n100#
++ a_n749_n100# a_n273_n100# a_111_n100# a_n177_n100# a_n561_n100# a_15_n100# a_n465_n100#
++ a_n705_n197# a_303_n100# a_n369_n100# w_n887_n319# a_207_n100# a_n657_n100# a_591_n100#
+X0 a_303_n100# a_n705_n197# a_207_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_591_n100# a_n705_n197# a_495_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_207_n100# a_n705_n197# a_111_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_399_n100# a_n705_n197# a_303_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_495_n100# a_n705_n197# a_399_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_687_n100# a_n705_n197# a_591_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n561_n100# a_n705_n197# a_n657_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n465_n100# a_n705_n197# a_n561_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n657_n100# a_n705_n197# a_n749_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n369_n100# a_n705_n197# a_n465_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_15_n100# a_n705_n197# a_n81_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_111_n100# a_n705_n197# a_15_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n273_n100# a_n705_n197# a_n369_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n81_n100# a_n705_n197# a_n177_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n177_n100# a_n705_n197# a_n273_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_495_n100# a_399_n100# 0.29fF
+C1 a_495_n100# a_591_n100# 0.29fF
+C2 a_303_n100# a_n705_n197# 0.08fF
+C3 a_303_n100# a_n81_n100# 0.05fF
+C4 a_15_n100# w_n887_n319# 0.02fF
+C5 a_n273_n100# a_15_n100# 0.06fF
+C6 w_n887_n319# a_111_n100# 0.02fF
+C7 a_n273_n100# a_111_n100# 0.05fF
+C8 a_303_n100# a_399_n100# 0.29fF
+C9 a_303_n100# a_591_n100# 0.06fF
+C10 a_111_n100# a_495_n100# 0.05fF
+C11 a_n369_n100# a_n749_n100# 0.05fF
+C12 w_n887_n319# a_n465_n100# 0.03fF
+C13 a_n273_n100# w_n887_n319# 0.02fF
+C14 a_n273_n100# a_n465_n100# 0.11fF
+C15 a_303_n100# a_15_n100# 0.06fF
+C16 w_n887_n319# a_495_n100# 0.04fF
+C17 a_303_n100# a_111_n100# 0.11fF
+C18 a_n369_n100# a_n177_n100# 0.11fF
+C19 a_n369_n100# a_n561_n100# 0.11fF
+C20 w_n887_n319# a_n657_n100# 0.05fF
+C21 a_n369_n100# a_n705_n197# 0.08fF
+C22 a_n465_n100# a_n657_n100# 0.11fF
+C23 a_n273_n100# a_n657_n100# 0.05fF
+C24 a_n177_n100# a_207_n100# 0.05fF
+C25 a_n369_n100# a_n81_n100# 0.06fF
+C26 a_n749_n100# a_n561_n100# 0.11fF
+C27 a_207_n100# a_n705_n197# 0.08fF
+C28 a_207_n100# a_n81_n100# 0.06fF
+C29 a_303_n100# w_n887_n319# 0.02fF
+C30 a_303_n100# a_495_n100# 0.11fF
+C31 a_207_n100# a_399_n100# 0.11fF
+C32 a_207_n100# a_591_n100# 0.05fF
+C33 a_687_n100# a_399_n100# 0.06fF
+C34 a_n177_n100# a_n561_n100# 0.05fF
+C35 a_687_n100# a_591_n100# 0.29fF
+C36 a_n177_n100# a_n705_n197# 0.08fF
+C37 a_n705_n197# a_n561_n100# 0.08fF
+C38 a_15_n100# a_n369_n100# 0.05fF
+C39 a_n177_n100# a_n81_n100# 0.29fF
+C40 a_n81_n100# a_n705_n197# 0.08fF
+C41 a_15_n100# a_207_n100# 0.11fF
+C42 a_111_n100# a_207_n100# 0.29fF
+C43 a_n705_n197# a_399_n100# 0.08fF
+C44 a_591_n100# a_n705_n197# 0.08fF
+C45 w_n887_n319# a_n369_n100# 0.02fF
+C46 a_n369_n100# a_n465_n100# 0.29fF
+C47 a_n273_n100# a_n369_n100# 0.29fF
+C48 a_591_n100# a_399_n100# 0.11fF
+C49 w_n887_n319# a_207_n100# 0.02fF
+C50 w_n887_n319# a_n749_n100# 0.10fF
+C51 a_15_n100# a_n177_n100# 0.11fF
+C52 a_n465_n100# a_n749_n100# 0.06fF
+C53 a_15_n100# a_n705_n197# 0.08fF
+C54 a_207_n100# a_495_n100# 0.06fF
+C55 a_n177_n100# a_111_n100# 0.06fF
+C56 a_15_n100# a_n81_n100# 0.29fF
+C57 w_n887_n319# a_687_n100# 0.10fF
+C58 a_111_n100# a_n705_n197# 0.08fF
+C59 a_n369_n100# a_n657_n100# 0.06fF
+C60 a_111_n100# a_n81_n100# 0.11fF
+C61 a_687_n100# a_495_n100# 0.11fF
+C62 a_15_n100# a_399_n100# 0.05fF
+C63 a_n749_n100# a_n657_n100# 0.29fF
+C64 a_111_n100# a_399_n100# 0.06fF
+C65 w_n887_n319# a_n177_n100# 0.02fF
+C66 a_n177_n100# a_n465_n100# 0.06fF
+C67 a_n273_n100# a_n177_n100# 0.29fF
+C68 w_n887_n319# a_n561_n100# 0.04fF
+C69 a_n465_n100# a_n561_n100# 0.29fF
+C70 a_303_n100# a_207_n100# 0.29fF
+C71 a_n273_n100# a_n561_n100# 0.06fF
+C72 w_n887_n319# a_n705_n197# 0.82fF
+C73 a_n465_n100# a_n705_n197# 0.08fF
+C74 a_n273_n100# a_n705_n197# 0.08fF
+C75 w_n887_n319# a_n81_n100# 0.02fF
+C76 a_n465_n100# a_n81_n100# 0.05fF
+C77 a_n273_n100# a_n81_n100# 0.11fF
+C78 a_495_n100# a_n705_n197# 0.08fF
+C79 a_303_n100# a_687_n100# 0.05fF
+C80 w_n887_n319# a_399_n100# 0.03fF
+C81 w_n887_n319# a_591_n100# 0.05fF
+C82 a_15_n100# a_111_n100# 0.29fF
+C83 a_n657_n100# a_n561_n100# 0.29fF
+C84 a_n657_n100# a_n705_n197# 0.08fF
+C85 a_687_n100# VSUBS 0.03fF
+C86 a_591_n100# VSUBS 0.03fF
+C87 a_495_n100# VSUBS 0.03fF
+C88 a_399_n100# VSUBS 0.03fF
+C89 a_303_n100# VSUBS 0.03fF
+C90 a_207_n100# VSUBS 0.03fF
+C91 a_111_n100# VSUBS 0.03fF
+C92 a_15_n100# VSUBS 0.03fF
+C93 a_n81_n100# VSUBS 0.03fF
+C94 a_n177_n100# VSUBS 0.03fF
+C95 a_n273_n100# VSUBS 0.03fF
+C96 a_n369_n100# VSUBS 0.03fF
+C97 a_n465_n100# VSUBS 0.03fF
+C98 a_n561_n100# VSUBS 0.03fF
+C99 a_n657_n100# VSUBS 0.03fF
+C100 a_n749_n100# VSUBS 0.03fF
+C101 a_n705_n197# VSUBS 1.60fF
+C102 w_n887_n319# VSUBS 5.82fF
+.ends
+
+.subckt source_follower_buff_pmos m1_957_828# in avss1p8 avdd1p8 out iref
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 avss1p8 iref iref iref avss1p8 avss1p8 avss1p8
++ avss1p8 iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_957_828# m1_957_828# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_957_828# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__pfet_01v8_lvt_D3F744_0 avss1p8 out avss1p8 out avss1p8 avss1p8 in out
++ avss1p8 avdd1p8 avss1p8 out out avss1p8 sky130_fd_pr__pfet_01v8_lvt_D3F744
+Xsky130_fd_pr__pfet_01v8_VCU74W_0 avss1p8 m1_957_828# m1_957_828# avdd1p8 m1_957_828#
++ avdd1p8 m1_957_828# m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# m1_957_828#
++ m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+Xsky130_fd_pr__pfet_01v8_VCU74W_1 avss1p8 out out avdd1p8 out avdd1p8 out out avdd1p8
++ avdd1p8 avdd1p8 out m1_957_828# out avdd1p8 avdd1p8 avdd1p8 out avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+C0 m1_957_828# iref 0.88fF
+C1 m1_957_828# in 0.52fF
+C2 avdd1p8 iref 0.29fF
+C3 avdd1p8 m1_957_828# 1.12fF
+C4 m1_957_828# out 1.52fF
+C5 avdd1p8 in 0.32fF
+C6 out in 1.16fF
+C7 avdd1p8 out 3.96fF
+C8 out avss1p8 -1.64fF
+C9 in avss1p8 1.94fF
+C10 avdd1p8 avss1p8 15.90fF
+C11 m1_957_828# avss1p8 -34.25fF
+C12 iref avss1p8 4.22fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CFLRKA a_n993_109# a_n1473_n309# a_63_n309# a_1215_n309#
++ a_1215_109# a_n129_n309# a_735_109# a_1599_109# a_n513_n309# a_255_109# a_n1377_n309#
++ a_n1949_109# a_n1761_n309# a_1119_n309# a_1503_n309# a_n1761_109# a_n417_109# a_n417_n309#
++ a_n1281_109# a_n801_n309# a_351_n309# a_63_109# a_1503_109# a_n1665_n309# a_1023_109#
++ a_1887_109# a_1407_n309# a_543_109# a_n705_n309# a_255_n309# a_1791_n309# a_n1569_109#
++ a_n705_109# a_n1569_n309# a_n1089_109# w_n2087_n519# a_n225_109# a_n609_n309# a_159_n309#
++ a_543_n309# a_1695_n309# a_1311_109# a_831_109# a_1695_109# a_n1857_n309# a_n993_n309#
++ a_n33_109# a_351_109# a_n1857_109# a_447_n309# a_831_n309# a_1599_n309# a_n1377_109#
++ a_n897_n309# a_n897_109# a_n513_109# a_1119_109# a_639_109# a_n33_n309# a_735_n309#
++ a_1887_n309# a_159_109# a_n1665_109# a_n1281_n309# a_1023_n309# a_n1185_109# a_n801_109#
++ a_639_n309# a_n321_109# a_1407_109# a_n321_n309# a_927_109# a_447_109# a_1791_109#
++ a_n1185_n309# a_1311_n309# a_n1905_n87# a_927_n309# a_n609_109# a_n225_n309# a_n1473_109#
++ a_n129_109# a_n1949_n309# a_n1089_n309#
+X0 a_n1569_n309# a_n1905_n87# a_n1665_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n87# a_n993_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_927_n309# a_n1905_n87# a_831_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1023_109# a_n1905_n87# a_927_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_255_n309# a_n1905_n87# a_159_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n87# a_1119_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_927_109# a_n1905_n87# a_831_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n1857_n309# a_n1905_n87# a_n1949_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n321_n309# a_n1905_n87# a_n417_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n1761_109# a_n1905_n87# a_n1857_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_543_n309# a_n1905_n87# a_447_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_1503_n309# a_n1905_n87# a_1407_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n1857_109# a_n1905_n87# a_n1949_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n1665_109# a_n1905_n87# a_n1761_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1569_109# a_n1905_n87# a_n1665_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1215_109# a_n1905_n87# a_1119_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_1311_109# a_n1905_n87# a_1215_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_1503_109# a_n1905_n87# a_1407_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_1791_109# a_n1905_n87# a_1695_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n87# a_n1281_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_1119_109# a_n1905_n87# a_1023_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1407_109# a_n1905_n87# a_1311_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_1599_109# a_n1905_n87# a_1503_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1695_109# a_n1905_n87# a_1599_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1887_109# a_n1905_n87# a_1791_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_n1473_n309# a_n1905_n87# a_n1569_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_831_n309# a_n1905_n87# a_735_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1791_n309# a_n1905_n87# a_1695_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n33_109# a_n1905_n87# a_n129_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_351_109# a_n1905_n87# a_255_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_159_n309# a_n1905_n87# a_63_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1119_n309# a_n1905_n87# a_1023_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_159_109# a_n1905_n87# a_63_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_255_109# a_n1905_n87# a_159_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_447_109# a_n1905_n87# a_351_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_543_109# a_n1905_n87# a_447_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_735_109# a_n1905_n87# a_639_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_831_109# a_n1905_n87# a_735_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n225_n309# a_n1905_n87# a_n321_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_639_109# a_n1905_n87# a_543_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_447_n309# a_n1905_n87# a_351_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_1407_n309# a_n1905_n87# a_1311_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_n1473_109# a_n1905_n87# a_n1569_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_n1281_109# a_n1905_n87# a_n1377_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_n1185_109# a_n1905_n87# a_n1281_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_n993_109# a_n1905_n87# a_n1089_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_n1089_n309# a_n1905_n87# a_n1185_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n1377_109# a_n1905_n87# a_n1473_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n1089_109# a_n1905_n87# a_n1185_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_n321_109# a_n1905_n87# a_n417_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n513_n309# a_n1905_n87# a_n609_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_63_n309# a_n1905_n87# a_n33_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_n801_109# a_n1905_n87# a_n897_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_n705_109# a_n1905_n87# a_n801_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_n513_109# a_n1905_n87# a_n609_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_n417_109# a_n1905_n87# a_n513_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n225_109# a_n1905_n87# a_n321_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n129_109# a_n1905_n87# a_n225_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n1377_n309# a_n1905_n87# a_n1473_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_735_n309# a_n1905_n87# a_639_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_1695_n309# a_n1905_n87# a_1599_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n897_109# a_n1905_n87# a_n993_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n609_109# a_n1905_n87# a_n705_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n801_n309# a_n1905_n87# a_n897_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n129_n309# a_n1905_n87# a_n225_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n1761_n309# a_n1905_n87# a_n1857_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n417_n309# a_n1905_n87# a_n513_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_109# a_n1905_n87# a_n33_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_639_n309# a_n1905_n87# a_543_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_1599_n309# a_n1905_n87# a_1503_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n705_n309# a_n1905_n87# a_n801_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1887_n309# a_n1905_n87# a_1791_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n1665_n309# a_n1905_n87# a_n1761_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_1023_n309# a_n1905_n87# a_927_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n993_n309# a_n1905_n87# a_n1089_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_n33_n309# a_n1905_n87# a_n129_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_351_n309# a_n1905_n87# a_255_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_1311_n309# a_n1905_n87# a_1215_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n1281_n309# a_n1905_n87# a_n1377_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_n609_n309# a_n1905_n87# a_n705_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_1599_109# a_1215_109# 0.05fF
+C1 a_n801_n309# a_n705_n309# 0.29fF
+C2 a_n801_109# a_n897_109# 0.29fF
+C3 a_n1089_n309# a_n705_n309# 0.05fF
+C4 a_1599_109# a_1791_109# 0.11fF
+C5 a_n801_n309# a_n897_n309# 0.29fF
+C6 a_n1089_n309# a_n897_n309# 0.11fF
+C7 a_n321_109# a_n609_109# 0.06fF
+C8 a_543_109# a_831_109# 0.06fF
+C9 a_255_109# a_n129_109# 0.05fF
+C10 a_735_109# a_1023_109# 0.06fF
+C11 a_831_109# a_1215_109# 0.05fF
+C12 a_n609_109# a_n897_109# 0.06fF
+C13 a_63_109# a_447_109# 0.05fF
+C14 a_1887_109# a_1887_n309# 0.01fF
+C15 a_n801_109# a_n801_n309# 0.01fF
+C16 a_1311_n309# a_1599_n309# 0.06fF
+C17 a_639_109# a_351_109# 0.06fF
+C18 a_n1089_n309# a_n1473_n309# 0.05fF
+C19 a_1407_109# a_1407_n309# 0.01fF
+C20 a_n225_109# a_n609_109# 0.05fF
+C21 a_n1665_109# a_n1377_109# 0.06fF
+C22 a_1119_109# a_1407_109# 0.06fF
+C23 a_n1569_n309# a_n1761_n309# 0.11fF
+C24 a_927_109# a_927_n309# 0.01fF
+C25 a_n1857_n309# a_n1761_n309# 0.29fF
+C26 a_1023_n309# a_831_n309# 0.11fF
+C27 a_1695_n309# a_1599_n309# 0.29fF
+C28 a_n993_109# a_n993_n309# 0.01fF
+C29 a_n609_n309# a_n225_n309# 0.05fF
+C30 a_n321_n309# a_n321_109# 0.01fF
+C31 a_1695_n309# a_1887_n309# 0.11fF
+C32 a_255_109# a_159_109# 0.29fF
+C33 a_n1473_n309# a_n1761_n309# 0.06fF
+C34 a_n33_n309# a_n321_n309# 0.06fF
+C35 a_927_109# a_1311_109# 0.05fF
+C36 a_n321_109# a_n513_109# 0.11fF
+C37 a_n801_109# a_n1185_109# 0.05fF
+C38 a_639_109# a_1023_109# 0.05fF
+C39 a_1791_n309# a_1503_n309# 0.06fF
+C40 a_n1473_109# a_n1089_109# 0.05fF
+C41 a_n1473_109# a_n1761_109# 0.06fF
+C42 a_n897_109# a_n513_109# 0.05fF
+C43 a_1695_109# a_1599_109# 0.29fF
+C44 a_831_109# a_831_n309# 0.01fF
+C45 a_n1665_n309# a_n1761_n309# 0.29fF
+C46 a_n33_n309# a_n417_n309# 0.05fF
+C47 a_n609_n309# a_n705_n309# 0.29fF
+C48 a_543_109# a_159_109# 0.05fF
+C49 a_n225_109# a_n513_109# 0.06fF
+C50 a_n1281_109# a_n1569_109# 0.06fF
+C51 a_n609_n309# a_n897_n309# 0.06fF
+C52 a_n321_109# a_63_109# 0.05fF
+C53 a_1503_109# a_1887_109# 0.05fF
+C54 a_735_109# a_831_109# 0.29fF
+C55 a_n1185_109# a_n1569_109# 0.05fF
+C56 a_447_n309# a_735_n309# 0.06fF
+C57 a_1503_109# a_1311_109# 0.11fF
+C58 a_n705_109# a_n705_n309# 0.01fF
+C59 a_1407_109# a_1215_109# 0.11fF
+C60 a_n417_n309# a_n801_n309# 0.05fF
+C61 a_n129_n309# a_n129_109# 0.01fF
+C62 a_1407_109# a_1791_109# 0.05fF
+C63 a_n225_109# a_63_109# 0.06fF
+C64 a_n1949_n309# a_n1949_109# 0.01fF
+C65 a_63_n309# a_447_n309# 0.05fF
+C66 a_n1665_109# a_n1949_109# 0.06fF
+C67 a_n1089_n309# a_n1377_n309# 0.06fF
+C68 a_351_109# a_447_109# 0.29fF
+C69 a_n801_109# a_n705_109# 0.29fF
+C70 a_n609_n309# a_n609_109# 0.01fF
+C71 a_n897_109# a_n1089_109# 0.11fF
+C72 a_1119_109# a_1215_109# 0.29fF
+C73 a_n993_n309# a_n1185_n309# 0.11fF
+C74 a_1791_n309# a_1407_n309# 0.05fF
+C75 a_927_109# a_1023_109# 0.29fF
+C76 a_1215_n309# a_927_n309# 0.06fF
+C77 a_n609_109# a_n705_109# 0.29fF
+C78 a_63_109# a_351_109# 0.06fF
+C79 a_1599_109# a_1599_n309# 0.01fF
+C80 a_639_n309# a_927_n309# 0.06fF
+C81 a_n1089_n309# a_n1089_109# 0.01fF
+C82 a_n1281_n309# a_n1185_n309# 0.29fF
+C83 a_639_109# a_831_109# 0.11fF
+C84 a_n1377_n309# a_n1761_n309# 0.05fF
+C85 a_n33_n309# a_159_n309# 0.11fF
+C86 a_255_109# a_543_109# 0.06fF
+C87 a_n225_109# a_n321_109# 0.29fF
+C88 a_1215_n309# a_1311_n309# 0.29fF
+C89 a_n609_n309# a_n321_n309# 0.06fF
+C90 a_n1281_109# a_n1473_109# 0.11fF
+C91 a_927_n309# a_1311_n309# 0.05fF
+C92 a_n1473_109# a_n1185_109# 0.06fF
+C93 a_1695_109# a_1407_109# 0.06fF
+C94 a_n1281_109# a_n1089_109# 0.11fF
+C95 a_n1761_109# a_n1761_n309# 0.01fF
+C96 a_n609_n309# a_n417_n309# 0.11fF
+C97 a_n993_109# a_n801_109# 0.11fF
+C98 a_n1185_109# a_n1089_109# 0.29fF
+C99 a_1215_n309# a_1119_n309# 0.29fF
+C100 a_831_n309# a_735_n309# 0.29fF
+C101 a_n705_109# a_n513_109# 0.11fF
+C102 a_n33_109# a_63_109# 0.29fF
+C103 a_735_109# a_1119_109# 0.05fF
+C104 a_735_109# a_735_n309# 0.01fF
+C105 a_1119_n309# a_927_n309# 0.11fF
+C106 a_n1089_n309# a_n801_n309# 0.06fF
+C107 a_1503_n309# a_1599_n309# 0.29fF
+C108 a_n993_109# a_n609_109# 0.05fF
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+C431 a_n1905_n87# w_n2087_n519# 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CAF2P9 a_63_n309# a_n1473_n309# a_159_527# a_1215_n309#
++ a_n993_109# a_1215_109# a_n129_n309# a_n513_n309# a_1599_109# a_735_109# a_n1665_527#
++ a_n1281_n727# a_n801_527# a_1023_n727# a_639_n727# a_255_109# a_n1185_527# a_n1377_n309#
++ a_n1949_109# a_1119_n309# a_n1761_n309# a_n321_527# a_1503_n309# a_1407_527# a_n321_n727#
++ a_927_527# a_n1761_109# a_n417_109# a_n417_n309# a_351_n309# a_n801_n309# a_n1905_n505#
++ a_n1281_109# a_n1185_n727# a_447_527# a_1791_527# a_63_109# a_1311_n727# a_927_n727#
++ a_1503_109# a_n1665_n309# a_1407_n309# a_1887_109# a_n225_n727# a_1023_109# a_n609_527#
++ a_543_109# a_255_n309# a_n1473_527# a_n1949_n727# a_1791_n309# a_n705_n309# a_n129_527#
++ a_n1089_n727# a_n1473_n727# a_1215_n727# a_63_n727# a_n993_527# a_n1569_109# a_n1569_n309#
++ a_n705_109# a_1215_527# a_n129_n727# a_n1089_109# a_1599_527# a_n513_n727# a_735_527#
++ a_n225_109# a_1695_n309# a_159_n309# a_n609_n309# a_543_n309# a_255_527# a_n1377_n727#
++ a_n1949_527# a_1119_n727# a_n1761_n727# a_1503_n727# a_1311_109# a_n993_n309# a_1695_109#
++ a_n1857_n309# a_831_109# a_n1761_527# a_n33_109# a_n417_n727# a_n417_527# a_351_109#
++ a_351_n727# a_n801_n727# a_n1281_527# a_n1857_109# a_1599_n309# a_447_n309# a_63_527#
++ a_831_n309# a_1503_527# a_n1377_109# a_n1665_n727# a_1887_527# a_1407_n727# a_n897_n309#
++ a_1023_527# a_n513_109# a_n897_109# a_543_527# a_1791_n727# a_255_n727# a_n705_n727#
++ a_1119_109# a_1887_n309# a_639_109# a_735_n309# a_n33_n309# a_n1569_527# a_n1569_n727#
++ a_n705_527# a_159_109# a_n1089_527# a_n225_527# w_n2087_n937# a_1695_n727# a_159_n727#
++ a_n609_n727# a_543_n727# a_n1665_109# a_n1281_n309# a_1023_n309# a_1311_527# a_n801_109#
++ a_639_n309# a_1695_527# a_n1185_109# a_n993_n727# a_831_527# a_n1857_n727# a_n321_109#
++ a_1407_109# a_n33_527# a_n321_n309# a_351_527# a_927_109# a_1599_n727# a_n1857_527#
++ a_447_n727# a_831_n727# a_447_109# a_n1185_n309# a_n1377_527# a_1791_109# a_1311_n309#
++ a_n897_n727# a_927_n309# a_n513_527# a_n897_527# a_n225_n309# a_n609_109# a_1119_527#
++ a_1887_n727# a_n1949_n309# a_639_527# a_n1473_109# a_n129_109# a_735_n727# a_n33_n727#
++ a_n1089_n309#
+X0 a_927_n309# a_n1905_n505# a_831_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n505# a_n993_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n1569_n309# a_n1905_n505# a_n1665_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n727# a_n1905_n505# a_n225_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n1761_n727# a_n1905_n505# a_n1857_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n505# a_1119_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_255_n309# a_n1905_n505# a_159_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1023_109# a_n1905_n505# a_927_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n1857_n309# a_n1905_n505# a_n1949_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_927_109# a_n1905_n505# a_831_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_n417_n727# a_n1905_n505# a_n513_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_n321_n309# a_n1905_n505# a_n417_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_1599_n727# a_n1905_n505# a_1503_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_63_527# a_n1905_n505# a_n33_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1761_109# a_n1905_n505# a_n1857_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1503_n309# a_n1905_n505# a_1407_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_639_n727# a_n1905_n505# a_543_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_543_n309# a_n1905_n505# a_447_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_n1665_109# a_n1905_n505# a_n1761_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n505# a_n1281_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_n1569_109# a_n1905_n505# a_n1665_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1311_109# a_n1905_n505# a_1215_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1857_109# a_n1905_n505# a_n1949_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1791_109# a_n1905_n505# a_1695_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1503_109# a_n1905_n505# a_1407_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_1215_109# a_n1905_n505# a_1119_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_n705_n727# a_n1905_n505# a_n801_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1119_109# a_n1905_n505# a_1023_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_1695_109# a_n1905_n505# a_1599_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_1407_109# a_n1905_n505# a_1311_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_1599_109# a_n1905_n505# a_1503_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1887_109# a_n1905_n505# a_1791_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_1887_n727# a_n1905_n505# a_1791_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_1791_n309# a_n1905_n505# a_1695_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_831_n309# a_n1905_n505# a_735_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_n1473_n309# a_n1905_n505# a_n1569_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_n33_109# a_n1905_n505# a_n129_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_1023_n727# a_n1905_n505# a_927_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n1665_n727# a_n1905_n505# a_n1761_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_1119_n309# a_n1905_n505# a_1023_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_159_n309# a_n1905_n505# a_63_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_351_109# a_n1905_n505# a_255_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_1311_n727# a_n1905_n505# a_1215_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_255_109# a_n1905_n505# a_159_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_351_n727# a_n1905_n505# a_255_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_831_109# a_n1905_n505# a_735_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_543_109# a_n1905_n505# a_447_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n33_n727# a_n1905_n505# a_n129_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n993_n727# a_n1905_n505# a_n1089_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_159_109# a_n1905_n505# a_63_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n225_n309# a_n1905_n505# a_n321_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_735_109# a_n1905_n505# a_639_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_447_109# a_n1905_n505# a_351_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_639_109# a_n1905_n505# a_543_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_1407_n309# a_n1905_n505# a_1311_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_447_n309# a_n1905_n505# a_351_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n1089_n309# a_n1905_n505# a_n1185_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n1281_109# a_n1905_n505# a_n1377_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n993_109# a_n1905_n505# a_n1089_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_n1473_109# a_n1905_n505# a_n1569_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_n1185_109# a_n1905_n505# a_n1281_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n609_n727# a_n1905_n505# a_n705_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n1377_109# a_n1905_n505# a_n1473_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n1089_109# a_n1905_n505# a_n1185_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n1281_n727# a_n1905_n505# a_n1377_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n513_n309# a_n1905_n505# a_n609_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n321_109# a_n1905_n505# a_n417_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_n309# a_n1905_n505# a_n33_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_n225_109# a_n1905_n505# a_n321_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_n801_109# a_n1905_n505# a_n897_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n513_109# a_n1905_n505# a_n609_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1695_n309# a_n1905_n505# a_1599_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n705_109# a_n1905_n505# a_n801_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_n417_109# a_n1905_n505# a_n513_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n129_109# a_n1905_n505# a_n225_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_735_n309# a_n1905_n505# a_639_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_n1377_n309# a_n1905_n505# a_n1473_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_n897_109# a_n1905_n505# a_n993_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n609_109# a_n1905_n505# a_n705_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_927_n727# a_n1905_n505# a_831_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X80 a_n1569_n727# a_n1905_n505# a_n1665_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X81 a_n897_n727# a_n1905_n505# a_n993_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X82 a_n801_n309# a_n1905_n505# a_n897_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X83 a_1215_n727# a_n1905_n505# a_1119_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X84 a_255_n727# a_n1905_n505# a_159_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X85 a_1023_527# a_n1905_n505# a_927_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X86 a_n129_n309# a_n1905_n505# a_n225_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X87 a_927_527# a_n1905_n505# a_831_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X88 a_n1857_n727# a_n1905_n505# a_n1949_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X89 a_n1761_n309# a_n1905_n505# a_n1857_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X90 a_n321_n727# a_n1905_n505# a_n417_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X91 a_n1761_527# a_n1905_n505# a_n1857_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X92 a_1503_n727# a_n1905_n505# a_1407_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X93 a_n1665_527# a_n1905_n505# a_n1761_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X94 a_543_n727# a_n1905_n505# a_447_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X95 a_n1185_n727# a_n1905_n505# a_n1281_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X96 a_n417_n309# a_n1905_n505# a_n513_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X97 a_n1857_527# a_n1905_n505# a_n1949_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X98 a_n1569_527# a_n1905_n505# a_n1665_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X99 a_1311_527# a_n1905_n505# a_1215_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X100 a_1215_527# a_n1905_n505# a_1119_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X101 a_1503_527# a_n1905_n505# a_1407_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X102 a_1791_527# a_n1905_n505# a_1695_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X103 a_1119_527# a_n1905_n505# a_1023_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X104 a_1407_527# a_n1905_n505# a_1311_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X105 a_1695_527# a_n1905_n505# a_1599_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X106 a_1599_n309# a_n1905_n505# a_1503_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X107 a_63_109# a_n1905_n505# a_n33_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X108 a_639_n309# a_n1905_n505# a_543_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X109 a_1599_527# a_n1905_n505# a_1503_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X110 a_1887_527# a_n1905_n505# a_1791_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X111 a_1791_n727# a_n1905_n505# a_1695_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X112 a_831_n727# a_n1905_n505# a_735_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X113 a_n1473_n727# a_n1905_n505# a_n1569_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X114 a_n705_n309# a_n1905_n505# a_n801_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X115 a_n33_527# a_n1905_n505# a_n129_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X116 a_1887_n309# a_n1905_n505# a_1791_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X117 a_1119_n727# a_n1905_n505# a_1023_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X118 a_159_n727# a_n1905_n505# a_63_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X119 a_351_527# a_n1905_n505# a_255_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X120 a_1023_n309# a_n1905_n505# a_927_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X121 a_n1665_n309# a_n1905_n505# a_n1761_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X122 a_255_527# a_n1905_n505# a_159_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X123 a_543_527# a_n1905_n505# a_447_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X124 a_831_527# a_n1905_n505# a_735_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X125 a_159_527# a_n1905_n505# a_63_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X126 a_447_527# a_n1905_n505# a_351_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X127 a_n225_n727# a_n1905_n505# a_n321_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X128 a_735_527# a_n1905_n505# a_639_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X129 a_639_527# a_n1905_n505# a_543_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X130 a_1407_n727# a_n1905_n505# a_1311_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X131 a_447_n727# a_n1905_n505# a_351_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X132 a_1311_n309# a_n1905_n505# a_1215_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X133 a_n1089_n727# a_n1905_n505# a_n1185_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X134 a_351_n309# a_n1905_n505# a_255_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X135 a_n33_n309# a_n1905_n505# a_n129_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X136 a_n1281_527# a_n1905_n505# a_n1377_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X137 a_n993_527# a_n1905_n505# a_n1089_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X138 a_n993_n309# a_n1905_n505# a_n1089_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X139 a_n1473_527# a_n1905_n505# a_n1569_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X140 a_n1185_527# a_n1905_n505# a_n1281_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X141 a_n1377_527# a_n1905_n505# a_n1473_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X142 a_n1089_527# a_n1905_n505# a_n1185_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X143 a_n513_n727# a_n1905_n505# a_n609_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X144 a_n321_527# a_n1905_n505# a_n417_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X145 a_63_n727# a_n1905_n505# a_n33_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X146 a_n801_527# a_n1905_n505# a_n897_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X147 a_n513_527# a_n1905_n505# a_n609_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X148 a_n225_527# a_n1905_n505# a_n321_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X149 a_1695_n727# a_n1905_n505# a_1599_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X150 a_735_n727# a_n1905_n505# a_639_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X151 a_n705_527# a_n1905_n505# a_n801_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X152 a_n417_527# a_n1905_n505# a_n513_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X153 a_n129_527# a_n1905_n505# a_n225_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X154 a_n1377_n727# a_n1905_n505# a_n1473_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X155 a_n609_n309# a_n1905_n505# a_n705_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X156 a_n1281_n309# a_n1905_n505# a_n1377_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X157 a_n897_527# a_n1905_n505# a_n993_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X158 a_n609_527# a_n1905_n505# a_n705_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X159 a_n801_n727# a_n1905_n505# a_n897_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n897_109# a_n1185_109# 0.06fF
+C1 a_1311_109# a_1599_109# 0.06fF
+C2 a_n1949_n727# a_n1569_n727# 0.05fF
+C3 a_447_n309# a_351_n309# 0.29fF
+C4 a_447_n727# a_543_n727# 0.29fF
+C5 a_735_n309# a_351_n309# 0.05fF
+C6 a_1119_527# a_1023_527# 0.29fF
+C7 a_447_n309# a_543_n309# 0.29fF
+C8 a_n897_109# a_n993_109# 0.29fF
+C9 a_735_n309# a_543_n309# 0.11fF
+C10 a_n1665_527# a_n1949_527# 0.06fF
+C11 a_n33_n727# a_255_n727# 0.06fF
+C12 a_n897_n727# a_n1185_n727# 0.06fF
+C13 a_n801_527# a_n417_527# 0.05fF
+C14 a_n609_n727# a_n225_n727# 0.05fF
+C15 a_n1089_n727# a_n1377_n727# 0.06fF
+C16 a_n1185_n727# a_n1569_n727# 0.05fF
+C17 a_447_527# a_63_527# 0.05fF
+C18 a_1503_527# a_1503_109# 0.01fF
+C19 a_1791_527# a_1695_527# 0.29fF
+C20 a_255_n727# a_543_n727# 0.06fF
+C21 a_n33_109# a_351_109# 0.05fF
+C22 a_n417_n727# a_n801_n727# 0.05fF
+C23 a_1695_n309# a_1695_109# 0.01fF
+C24 a_1119_109# a_735_109# 0.05fF
+C25 a_n1089_527# a_n705_527# 0.05fF
+C26 a_1503_n309# a_1503_109# 0.01fF
+C27 a_447_n727# a_447_n309# 0.01fF
+C28 a_n1665_n309# a_n1949_n309# 0.06fF
+C29 a_n993_n727# a_n705_n727# 0.06fF
+C30 a_735_n309# a_1119_n309# 0.05fF
+C31 a_831_527# a_639_527# 0.11fF
+C32 a_n1761_n727# a_n1761_n309# 0.01fF
+C33 a_n321_109# a_n609_109# 0.06fF
+C34 a_n129_n727# a_255_n727# 0.05fF
+C35 a_1311_n727# a_1023_n727# 0.06fF
+C36 a_831_109# a_927_109# 0.29fF
+C37 a_n1089_109# a_n801_109# 0.06fF
+C38 a_n1089_109# a_n705_109# 0.05fF
+C39 a_1695_n309# a_1311_n309# 0.05fF
+C40 a_n1473_n727# a_n1761_n727# 0.06fF
+C41 a_1215_n309# a_1407_n309# 0.11fF
+C42 a_n1281_n727# a_n1281_n309# 0.01fF
+C43 a_1503_n309# a_1407_n309# 0.29fF
+C44 a_n33_527# a_n417_527# 0.05fF
+C45 a_n1377_n309# a_n1185_n309# 0.11fF
+C46 a_1023_109# a_735_109# 0.06fF
+C47 a_n1473_109# a_n1569_109# 0.29fF
+C48 a_1695_527# a_1503_527# 0.11fF
+C49 a_n1949_527# a_n1949_109# 0.01fF
+C50 a_159_n309# a_159_109# 0.01fF
+C51 a_255_527# a_n33_527# 0.06fF
+C52 a_639_n727# a_639_n309# 0.01fF
+C53 a_n1377_n309# a_n1377_109# 0.01fF
+C54 a_1503_109# a_1695_109# 0.11fF
+C55 a_255_n309# a_n129_n309# 0.05fF
+C56 a_n1377_109# a_n1761_109# 0.05fF
+C57 a_1119_527# a_1215_527# 0.29fF
+C58 a_n33_n309# a_n33_n727# 0.01fF
+C59 a_1887_109# a_1695_109# 0.11fF
+C60 a_n1185_109# a_n993_109# 0.11fF
+C61 a_n1665_527# a_n1377_527# 0.06fF
+C62 a_n609_n727# a_n513_n727# 0.29fF
+C63 a_1311_527# a_1503_527# 0.11fF
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+C714 a_n801_109# a_n993_109# 0.11fF
+C715 a_63_n727# a_n225_n727# 0.06fF
+C716 a_1599_109# a_1215_109# 0.05fF
+C717 a_1119_n727# a_1215_n727# 0.29fF
+C718 a_n705_109# a_n993_109# 0.06fF
+C719 a_1887_109# a_1887_n309# 0.01fF
+C720 a_n993_527# a_n801_527# 0.11fF
+C721 a_n1569_n309# a_n1949_n309# 0.05fF
+C722 a_n1569_109# a_n1569_527# 0.01fF
+C723 a_831_109# a_543_109# 0.06fF
+C724 a_n1857_n309# a_n1761_n309# 0.29fF
+C725 a_1119_527# a_1311_527# 0.11fF
+C726 a_n993_n727# a_n993_n309# 0.01fF
+C727 a_n1569_109# a_n1761_109# 0.11fF
+C728 a_543_n727# a_543_n309# 0.01fF
+C729 a_1599_527# a_1599_109# 0.01fF
+C730 a_n33_n309# a_63_n309# 0.29fF
+C731 a_n1281_109# a_n1089_109# 0.11fF
+C732 a_n705_n309# a_n609_n309# 0.29fF
+C733 a_1215_n727# a_1407_n727# 0.11fF
+C734 a_1503_n309# a_1695_n309# 0.11fF
+C735 a_1023_527# a_735_527# 0.06fF
+C736 a_351_527# a_63_527# 0.06fF
+C737 a_n609_527# a_n417_527# 0.11fF
+C738 a_n705_n309# a_n897_n309# 0.11fF
+C739 a_1887_n727# w_n2087_n937# 0.12fF
+C740 a_1791_n727# w_n2087_n937# 0.08fF
+C741 a_1695_n727# w_n2087_n937# 0.06fF
+C742 a_1599_n727# w_n2087_n937# 0.06fF
+C743 a_1503_n727# w_n2087_n937# 0.04fF
+C744 a_1407_n727# w_n2087_n937# 0.04fF
+C745 a_1311_n727# w_n2087_n937# 0.04fF
+C746 a_1215_n727# w_n2087_n937# 0.04fF
+C747 a_1119_n727# w_n2087_n937# 0.04fF
+C748 a_1023_n727# w_n2087_n937# 0.04fF
+C749 a_927_n727# w_n2087_n937# 0.04fF
+C750 a_831_n727# w_n2087_n937# 0.04fF
+C751 a_735_n727# w_n2087_n937# 0.04fF
+C752 a_639_n727# w_n2087_n937# 0.04fF
+C753 a_543_n727# w_n2087_n937# 0.04fF
+C754 a_447_n727# w_n2087_n937# 0.04fF
+C755 a_351_n727# w_n2087_n937# 0.04fF
+C756 a_255_n727# w_n2087_n937# 0.04fF
+C757 a_159_n727# w_n2087_n937# 0.04fF
+C758 a_63_n727# w_n2087_n937# 0.04fF
+C759 a_n33_n727# w_n2087_n937# 0.04fF
+C760 a_n129_n727# w_n2087_n937# 0.04fF
+C761 a_n225_n727# w_n2087_n937# 0.04fF
+C762 a_n321_n727# w_n2087_n937# 0.04fF
+C763 a_n417_n727# w_n2087_n937# 0.04fF
+C764 a_n513_n727# w_n2087_n937# 0.04fF
+C765 a_n609_n727# w_n2087_n937# 0.04fF
+C766 a_n705_n727# w_n2087_n937# 0.04fF
+C767 a_n801_n727# w_n2087_n937# 0.04fF
+C768 a_n897_n727# w_n2087_n937# 0.04fF
+C769 a_n993_n727# w_n2087_n937# 0.04fF
+C770 a_n1089_n727# w_n2087_n937# 0.04fF
+C771 a_n1185_n727# w_n2087_n937# 0.04fF
+C772 a_n1281_n727# w_n2087_n937# 0.04fF
+C773 a_n1377_n727# w_n2087_n937# 0.04fF
+C774 a_n1473_n727# w_n2087_n937# 0.04fF
+C775 a_n1569_n727# w_n2087_n937# 0.04fF
+C776 a_n1665_n727# w_n2087_n937# 0.04fF
+C777 a_n1761_n727# w_n2087_n937# 0.04fF
+C778 a_n1857_n727# w_n2087_n937# 0.04fF
+C779 a_n1949_n727# w_n2087_n937# 0.04fF
+C780 a_1887_n309# w_n2087_n937# 0.11fF
+C781 a_1791_n309# w_n2087_n937# 0.07fF
+C782 a_1695_n309# w_n2087_n937# 0.05fF
+C783 a_1599_n309# w_n2087_n937# 0.05fF
+C784 a_1503_n309# w_n2087_n937# 0.03fF
+C785 a_1407_n309# w_n2087_n937# 0.03fF
+C786 a_1311_n309# w_n2087_n937# 0.03fF
+C787 a_1215_n309# w_n2087_n937# 0.03fF
+C788 a_1119_n309# w_n2087_n937# 0.03fF
+C789 a_1023_n309# w_n2087_n937# 0.03fF
+C790 a_927_n309# w_n2087_n937# 0.03fF
+C791 a_831_n309# w_n2087_n937# 0.03fF
+C792 a_735_n309# w_n2087_n937# 0.03fF
+C793 a_639_n309# w_n2087_n937# 0.03fF
+C794 a_543_n309# w_n2087_n937# 0.03fF
+C795 a_447_n309# w_n2087_n937# 0.03fF
+C796 a_351_n309# w_n2087_n937# 0.03fF
+C797 a_255_n309# w_n2087_n937# 0.03fF
+C798 a_159_n309# w_n2087_n937# 0.03fF
+C799 a_63_n309# w_n2087_n937# 0.03fF
+C800 a_n33_n309# w_n2087_n937# 0.03fF
+C801 a_n129_n309# w_n2087_n937# 0.03fF
+C802 a_n225_n309# w_n2087_n937# 0.03fF
+C803 a_n321_n309# w_n2087_n937# 0.03fF
+C804 a_n417_n309# w_n2087_n937# 0.03fF
+C805 a_n513_n309# w_n2087_n937# 0.03fF
+C806 a_n609_n309# w_n2087_n937# 0.03fF
+C807 a_n705_n309# w_n2087_n937# 0.03fF
+C808 a_n801_n309# w_n2087_n937# 0.03fF
+C809 a_n897_n309# w_n2087_n937# 0.03fF
+C810 a_n993_n309# w_n2087_n937# 0.03fF
+C811 a_n1089_n309# w_n2087_n937# 0.03fF
+C812 a_n1185_n309# w_n2087_n937# 0.03fF
+C813 a_n1281_n309# w_n2087_n937# 0.03fF
+C814 a_n1377_n309# w_n2087_n937# 0.03fF
+C815 a_n1473_n309# w_n2087_n937# 0.03fF
+C816 a_n1569_n309# w_n2087_n937# 0.03fF
+C817 a_n1665_n309# w_n2087_n937# 0.03fF
+C818 a_n1761_n309# w_n2087_n937# 0.03fF
+C819 a_n1857_n309# w_n2087_n937# 0.03fF
+C820 a_n1949_n309# w_n2087_n937# 0.03fF
+C821 a_1887_109# w_n2087_n937# 0.11fF
+C822 a_1791_109# w_n2087_n937# 0.07fF
+C823 a_1695_109# w_n2087_n937# 0.05fF
+C824 a_1599_109# w_n2087_n937# 0.05fF
+C825 a_1503_109# w_n2087_n937# 0.03fF
+C826 a_1407_109# w_n2087_n937# 0.03fF
+C827 a_1311_109# w_n2087_n937# 0.03fF
+C828 a_1215_109# w_n2087_n937# 0.03fF
+C829 a_1119_109# w_n2087_n937# 0.03fF
+C830 a_1023_109# w_n2087_n937# 0.03fF
+C831 a_927_109# w_n2087_n937# 0.03fF
+C832 a_831_109# w_n2087_n937# 0.03fF
+C833 a_735_109# w_n2087_n937# 0.03fF
+C834 a_639_109# w_n2087_n937# 0.03fF
+C835 a_543_109# w_n2087_n937# 0.03fF
+C836 a_447_109# w_n2087_n937# 0.03fF
+C837 a_351_109# w_n2087_n937# 0.03fF
+C838 a_255_109# w_n2087_n937# 0.03fF
+C839 a_159_109# w_n2087_n937# 0.03fF
+C840 a_63_109# w_n2087_n937# 0.03fF
+C841 a_n33_109# w_n2087_n937# 0.03fF
+C842 a_n129_109# w_n2087_n937# 0.03fF
+C843 a_n225_109# w_n2087_n937# 0.03fF
+C844 a_n321_109# w_n2087_n937# 0.03fF
+C845 a_n417_109# w_n2087_n937# 0.03fF
+C846 a_n513_109# w_n2087_n937# 0.03fF
+C847 a_n609_109# w_n2087_n937# 0.03fF
+C848 a_n705_109# w_n2087_n937# 0.03fF
+C849 a_n801_109# w_n2087_n937# 0.03fF
+C850 a_n897_109# w_n2087_n937# 0.03fF
+C851 a_n993_109# w_n2087_n937# 0.03fF
+C852 a_n1089_109# w_n2087_n937# 0.03fF
+C853 a_n1185_109# w_n2087_n937# 0.03fF
+C854 a_n1281_109# w_n2087_n937# 0.03fF
+C855 a_n1377_109# w_n2087_n937# 0.03fF
+C856 a_n1473_109# w_n2087_n937# 0.03fF
+C857 a_n1569_109# w_n2087_n937# 0.03fF
+C858 a_n1665_109# w_n2087_n937# 0.03fF
+C859 a_n1761_109# w_n2087_n937# 0.03fF
+C860 a_n1857_109# w_n2087_n937# 0.03fF
+C861 a_n1949_109# w_n2087_n937# 0.03fF
+C862 a_1887_527# w_n2087_n937# 0.12fF
+C863 a_1791_527# w_n2087_n937# 0.08fF
+C864 a_1695_527# w_n2087_n937# 0.06fF
+C865 a_1599_527# w_n2087_n937# 0.06fF
+C866 a_1503_527# w_n2087_n937# 0.04fF
+C867 a_1407_527# w_n2087_n937# 0.04fF
+C868 a_1311_527# w_n2087_n937# 0.04fF
+C869 a_1215_527# w_n2087_n937# 0.04fF
+C870 a_1119_527# w_n2087_n937# 0.04fF
+C871 a_1023_527# w_n2087_n937# 0.04fF
+C872 a_927_527# w_n2087_n937# 0.04fF
+C873 a_831_527# w_n2087_n937# 0.04fF
+C874 a_735_527# w_n2087_n937# 0.04fF
+C875 a_639_527# w_n2087_n937# 0.04fF
+C876 a_543_527# w_n2087_n937# 0.04fF
+C877 a_447_527# w_n2087_n937# 0.04fF
+C878 a_351_527# w_n2087_n937# 0.04fF
+C879 a_255_527# w_n2087_n937# 0.04fF
+C880 a_159_527# w_n2087_n937# 0.04fF
+C881 a_63_527# w_n2087_n937# 0.04fF
+C882 a_n33_527# w_n2087_n937# 0.04fF
+C883 a_n129_527# w_n2087_n937# 0.04fF
+C884 a_n225_527# w_n2087_n937# 0.04fF
+C885 a_n321_527# w_n2087_n937# 0.04fF
+C886 a_n417_527# w_n2087_n937# 0.04fF
+C887 a_n513_527# w_n2087_n937# 0.04fF
+C888 a_n609_527# w_n2087_n937# 0.04fF
+C889 a_n705_527# w_n2087_n937# 0.04fF
+C890 a_n801_527# w_n2087_n937# 0.04fF
+C891 a_n897_527# w_n2087_n937# 0.04fF
+C892 a_n993_527# w_n2087_n937# 0.04fF
+C893 a_n1089_527# w_n2087_n937# 0.04fF
+C894 a_n1185_527# w_n2087_n937# 0.04fF
+C895 a_n1281_527# w_n2087_n937# 0.04fF
+C896 a_n1377_527# w_n2087_n937# 0.04fF
+C897 a_n1473_527# w_n2087_n937# 0.04fF
+C898 a_n1569_527# w_n2087_n937# 0.04fF
+C899 a_n1665_527# w_n2087_n937# 0.04fF
+C900 a_n1761_527# w_n2087_n937# 0.04fF
+C901 a_n1857_527# w_n2087_n937# 0.04fF
+C902 a_n1949_527# w_n2087_n937# 0.04fF
+C903 a_n1905_n505# w_n2087_n937# 14.96fF
+.ends
+
+.subckt source_follower_buff_nmos w_2250_n1147# out avdd1p8 avss1p8 in m1_460_n1129#
++ iref w_2049_850# w_2250_1287# w_2250_355#
+Xsky130_fd_pr__nfet_01v8_lvt_CFLRKA_0 avdd1p8 out out out out out avdd1p8 out out
++ out avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8
++ avdd1p8 out avdd1p8 out out avdd1p8 out avdd1p8 out out out avdd1p8 out avdd1p8
++ out avss1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8 out avdd1p8
++ avdd1p8 avdd1p8 out out out out avdd1p8 out out out avdd1p8 out avdd1p8 avdd1p8
++ avdd1p8 avdd1p8 out out out avdd1p8 avdd1p8 out out out out avdd1p8 out out avdd1p8
++ avdd1p8 in avdd1p8 avdd1p8 avdd1p8 out out avdd1p8 out sky130_fd_pr__nfet_01v8_lvt_CFLRKA
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 m1_460_n1129# iref iref iref m1_460_n1129# m1_460_n1129#
++ avss1p8 m1_460_n1129# iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_460_n1129# m1_460_n1129# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_460_n1129# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_CAF2P9_0 out out avss1p8 out avss1p8 out out out out
++ avss1p8 out out avss1p8 out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out
++ avss1p8 out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 iref out avss1p8
++ out out out avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 out avss1p8 avss1p8
++ out out avss1p8 out out out out out out out avss1p8 avss1p8 avss1p8 out out out
++ out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out out out out avss1p8 avss1p8 out avss1p8
++ out out out out out avss1p8 out out out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8
++ avss1p8 out avss1p8 out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out
++ out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8 out out out out avss1p8 out avss1p8
++ avss1p8 out out out out out avss1p8 avss1p8 out avss1p8 out avss1p8 out out avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out avss1p8 avss1p8 out sky130_fd_pr__nfet_01v8_lvt_CAF2P9
+C0 iref out 22.08fF
+C1 in out 10.03fF
+C2 in iref 0.11fF
+C3 out avdd1p8 9.98fF
+C4 in avdd1p8 2.17fF
+C5 iref m1_460_n1129# 2.64fF
+C6 iref avss1p8 18.70fF
+C7 in avss1p8 -31.17fF
+C8 out avss1p8 -28.37fF
+C9 m1_460_n1129# avss1p8 2.61fF
+C10 avdd1p8 avss1p8 2.63fF
+.ends
+
+.subckt source_follower_buff_diff outn VSUBS avdd1p8 inp source_follower_buff_pmos_0/m1_957_828#
++ iref1 outp iref2 iref3 iref4 source_follower_buff_nmos_1/m1_460_n1129# source_follower_buff_pmos_1/m1_957_828#
++ source_follower_buff_nmos_0/in source_follower_buff_nmos_0/m1_460_n1129# source_follower_buff_nmos_1/in
++ source_follower_buff_nmos_0/w_2250_355# inn
+Xsource_follower_buff_pmos_0 source_follower_buff_pmos_0/m1_957_828# inn VSUBS avdd1p8
++ source_follower_buff_nmos_0/in iref3 source_follower_buff_pmos
+Xsource_follower_buff_pmos_1 source_follower_buff_pmos_1/m1_957_828# inp VSUBS avdd1p8
++ source_follower_buff_nmos_1/in iref1 source_follower_buff_pmos
+Xsource_follower_buff_nmos_0 source_follower_buff_nmos_0/w_2250_n1147# outn avdd1p8
++ VSUBS source_follower_buff_nmos_0/in source_follower_buff_nmos_0/m1_460_n1129# iref4
++ source_follower_buff_nmos_0/w_2049_850# source_follower_buff_nmos_0/w_2250_1287#
++ source_follower_buff_nmos_0/w_2250_355# source_follower_buff_nmos
+Xsource_follower_buff_nmos_1 source_follower_buff_nmos_1/w_2250_n1147# outp avdd1p8
++ VSUBS source_follower_buff_nmos_1/in source_follower_buff_nmos_1/m1_460_n1129# iref2
++ source_follower_buff_nmos_1/w_2049_850# source_follower_buff_nmos_1/w_2250_1287#
++ source_follower_buff_nmos_1/w_2250_355# source_follower_buff_nmos
+C0 avdd1p8 source_follower_buff_nmos_0/in 0.63fF
+C1 inn source_follower_buff_pmos_0/m1_957_828# 0.08fF
+C2 iref3 inn 0.01fF
+C3 source_follower_buff_nmos_0/in outn 0.11fF
+C4 source_follower_buff_nmos_1/w_2250_n1147# outp 0.09fF
+C5 avdd1p8 source_follower_buff_nmos_1/in 0.63fF
+C6 source_follower_buff_nmos_0/in inn -0.25fF
+C7 inp iref1 0.01fF
+C8 avdd1p8 outn 0.18fF
+C9 avdd1p8 inn 0.07fF
+C10 avdd1p8 source_follower_buff_nmos_0/w_2049_850# 0.16fF
+C11 avdd1p8 source_follower_buff_nmos_0/w_2250_1287# 0.18fF
+C12 source_follower_buff_nmos_1/in outp 0.11fF
+C13 inp source_follower_buff_nmos_1/in -0.25fF
+C14 avdd1p8 inp 0.07fF
+C15 inp source_follower_buff_pmos_1/m1_957_828# 0.08fF
+C16 iref2 VSUBS 11.84fF
+C17 source_follower_buff_nmos_1/in VSUBS -32.98fF
+C18 outp VSUBS 0.56fF
+C19 source_follower_buff_nmos_1/m1_460_n1129# VSUBS 1.47fF
+C20 iref4 VSUBS 12.04fF
+C21 source_follower_buff_nmos_0/in VSUBS -32.98fF
+C22 outn VSUBS 2.12fF
+C23 source_follower_buff_nmos_0/m1_460_n1129# VSUBS 1.50fF
+C24 avdd1p8 VSUBS 35.96fF
+C25 inp VSUBS 2.70fF
+C26 source_follower_buff_pmos_1/m1_957_828# VSUBS -35.44fF
+C27 iref1 VSUBS 3.02fF
+C28 inn VSUBS 4.09fF
+C29 source_follower_buff_pmos_0/m1_957_828# VSUBS -35.44fF
+C30 iref3 VSUBS 3.13fF
+.ends
+
+.subckt res_amp_top avss1p8 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ avdd1p8 iref0 res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# iref1 res_amp_lin_prog_0/res_amp_lin_0/vp
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out iref2 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1
++ res_amp_lin_prog_0/outn iref3 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ delay_reg0 iref4 res_amp_lin_prog_0/outp res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB
++ inn source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# inp res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ res_amp_lin_prog_0/res_amp_lin_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA delay_reg2 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out
++ res_amp_lin_prog_0/outp_cap iref_reg0 res_amp_lin_prog_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ source_follower_buff_diff_0/source_follower_buff_nmos_1/in res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA
++ res_amp_sync_v2_0/clkp iref_reg1 source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out iref_reg2 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out
++ res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ delay_reg1 outn source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ outp clkn res_amp_sync_v2_0/rst
+Xres_amp_sync_v2_0 avdd1p8 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 clkn res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280#
++ res_amp_sync_v2_0/DFlipFlop_4/nQ res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D
++ res_amp_sync_v2_0/DFlipFlop_3/Q res_amp_sync_v2_0/DFlipFlop_3/D res_amp_sync_v2_0/DFlipFlop_4/D
++ res_amp_sync_v2_0/DFlipFlop_1/D res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD
++ res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D
++ res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/nQ
++ res_amp_sync_v2_0/clkp res_amp_sync_v2_0/rst res_amp_sync_v2
+Xres_amp_lin_prog_0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363#
++ delay_reg2 avdd1p8 inp res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_prog_0/res_amp_lin_0/clk
++ res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 res_amp_lin_prog_0/outp_cap
++ avss1p8 res_amp_lin_prog_0/outn_cap res_amp_lin_prog_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB
++ res_amp_lin_prog_0/outn res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA
++ res_amp_lin_prog_0/outp res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ iref_reg0 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in
++ iref_reg1 iref_reg2 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ res_amp_lin_prog_0/res_amp_lin_0/vp res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in iref0
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363#
++ res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# delay_reg1 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ inn res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in res_amp_lin_prog_0/inverter_min_x4_0/out
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b res_amp_sync_v2_0/rst
++ res_amp_lin_prog
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_0 avss1p8 avss1p8 res_amp_lin_prog_0/outp_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_1 avss1p8 avss1p8 res_amp_lin_prog_0/outn_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsource_follower_buff_diff_0 outn avss1p8 avdd1p8 res_amp_lin_prog_0/outp_cap source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ iref1 outp iref2 iref3 iref4 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# source_follower_buff_diff_0/source_follower_buff_nmos_1/in
++ source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# res_amp_lin_prog_0/outn_cap
++ source_follower_buff_diff
+C0 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# avdd1p8 1.10fF
+C1 inn inp 1.68fF
+C2 res_amp_sync_v2_0/rst inn 0.09fF
+C3 iref0 res_amp_lin_prog_0/res_amp_lin_0/vctrl -0.03fF
+C4 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# iref4 0.13fF
+C5 res_amp_sync_v2_0/DFlipFlop_3/D avdd1p8 0.89fF
+C6 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/Q 0.44fF
+C7 source_follower_buff_diff_0/source_follower_buff_nmos_0/in avdd1p8 0.39fF
+C8 iref2 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# 0.12fF
+C9 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/D 0.08fF
+C10 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D 0.20fF
+C11 res_amp_lin_prog_0/clk avdd1p8 9.77fF
+C12 res_amp_sync_v2_0/DFlipFlop_1/D avdd1p8 0.29fF
+C13 delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.04fF
+C14 outn avdd1p8 0.30fF
+C15 delay_reg1 delay_reg2 0.23fF
+C16 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/nQ 0.20fF
+C17 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D 0.47fF
+C18 source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# outn 0.15fF
+C19 delay_reg2 avdd1p8 0.08fF
+C20 iref0 avdd1p8 -0.63fF
+C21 iref_reg2 avdd1p8 -0.57fF
+C22 res_amp_sync_v2_0/clkp clkn 0.06fF
+C23 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# iref1 0.10fF
+C24 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/Q 0.25fF
+C25 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/D 0.07fF
+C26 inp avdd1p8 0.46fF
+C27 res_amp_sync_v2_0/rst avdd1p8 0.80fF
+C28 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D 0.47fF
+C29 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD 0.25fF
+C30 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in res_amp_lin_prog_0/clk 0.48fF
+C31 outp avdd1p8 0.31fF
+C32 res_amp_lin_prog_0/outn_cap res_amp_sync_v2_0/rst 0.06fF
+C33 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# 0.06fF
+C34 inn avdd1p8 0.46fF
+C35 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD 0.28fF
+C36 iref0 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.02fF
+C37 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D 0.23fF
+C38 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/nQ 0.22fF
+C39 res_amp_lin_prog_0/res_amp_lin_0/vctrl avdd1p8 0.03fF
+C40 clkn avdd1p8 0.74fF
+C41 res_amp_sync_v2_0/clkp avdd1p8 1.19fF
+C42 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# iref3 0.10fF
+C43 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# avdd1p8 0.02fF
+C44 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# avdd1p8 0.02fF
+C45 iref_reg1 avdd1p8 0.05fF
+C46 delay_reg2 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out 0.03fF
+C47 delay_reg1 avdd1p8 0.04fF
+C48 res_amp_sync_v2_0/rst res_amp_lin_prog_0/outp_cap 0.13fF
+C49 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in 0.48fF
+C50 res_amp_sync_v2_0/rst inp 0.09fF
+C51 res_amp_lin_prog_0/clk clkn 0.07fF
+C52 source_follower_buff_diff_0/source_follower_buff_nmos_1/in avdd1p8 0.40fF
+C53 iref2 avss1p8 12.17fF
+C54 source_follower_buff_diff_0/source_follower_buff_nmos_1/in avss1p8 -32.88fF
+C55 outp avss1p8 -1.74fF
+C56 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# avss1p8 1.82fF
+C57 iref4 avss1p8 12.36fF
+C58 source_follower_buff_diff_0/source_follower_buff_nmos_0/in avss1p8 -32.87fF
+C59 source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# avss1p8 0.08fF
+C60 outn avss1p8 -1.13fF
+C61 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# avss1p8 1.84fF
+C62 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# avss1p8 -35.44fF
+C63 iref1 avss1p8 3.33fF
+C64 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# avss1p8 -35.44fF
+C65 iref3 avss1p8 3.02fF
+C66 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# avss1p8 -1.87fF
+C67 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# avss1p8 0.47fF
+C68 iref_reg1 avss1p8 0.41fF
+C69 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# avss1p8 -1.10fF
+C70 res_amp_lin_prog_0/res_amp_lin_0/vctrl avss1p8 -1.99fF
+C71 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# avss1p8 -2.18fF
+C72 iref_reg2 avss1p8 0.06fF
+C73 iref_reg0 avss1p8 -0.21fF
+C74 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# avss1p8 -1.03fF
+C75 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 0.55fF
+C76 iref0 avss1p8 0.37fF
+C77 res_amp_lin_prog_0/outn avss1p8 1.55fF
+C78 inp avss1p8 0.21fF
+C79 res_amp_lin_prog_0/outp avss1p8 -4.89fF
+C80 res_amp_lin_prog_0/res_amp_lin_0/vp avss1p8 -4.89fF
+C81 inn avss1p8 -6.68fF
+C82 res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
+C83 res_amp_lin_prog_0/outn_cap avss1p8 1.00fF
+C84 res_amp_lin_prog_0/res_amp_lin_0/clk avss1p8 4.30fF
+C85 res_amp_lin_prog_0/inverter_min_x4_0/out avss1p8 4.87fF
+C86 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
+C87 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C88 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C89 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C90 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C91 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C92 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C93 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C94 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C95 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C96 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C97 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.04fF
+C98 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C99 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C100 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C101 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C102 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C103 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C104 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C105 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
+C106 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C107 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
+C108 delay_reg0 avss1p8 2.90fF
+C109 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C110 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
+C111 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
+C112 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C113 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
+C114 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C115 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C116 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C117 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C118 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
+C119 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C120 delay_reg1 avss1p8 3.97fF
+C121 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
+C122 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
+C123 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C124 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C125 delay_reg2 avss1p8 11.33fF
+C126 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.04fF
+C127 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C128 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C129 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
+C130 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
+C131 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
+C132 res_amp_lin_prog_0/outp_cap avss1p8 -6.67fF
+C133 res_amp_sync_v2_0/nand_logic_1/m1_21_n341# avss1p8 0.72fF
+C134 res_amp_sync_v2_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C135 res_amp_lin_prog_0/clk avss1p8 -6.90fF
+C136 res_amp_sync_v2_0/inverter_min_x4_4/out avss1p8 5.85fF
+C137 res_amp_sync_v2_0/nand_logic_1/out avss1p8 1.70fF
+C138 res_amp_sync_v2_0/rst avss1p8 -3.03fF
+C139 res_amp_sync_v2_0/DFlipFlop_4/nQ avss1p8 0.48fF
+C140 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 -2.08fF
+C141 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C142 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD avss1p8 0.57fF
+C143 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D avss1p8 -1.73fF
+C144 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C145 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C146 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D avss1p8 0.96fF
+C147 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C148 res_amp_sync_v2_0/DFlipFlop_4/D avss1p8 1.83fF
+C149 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD avss1p8 1.14fF
+C150 res_amp_sync_v2_0/nand_logic_0/out avss1p8 1.20fF
+C151 res_amp_sync_v2_0/DFlipFlop_0/Q avss1p8 -4.73fF
+C152 res_amp_sync_v2_0/DFlipFlop_3/nQ avss1p8 0.48fF
+C153 res_amp_sync_v2_0/DFlipFlop_3/Q avss1p8 -2.94fF
+C154 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C155 clkn avss1p8 -7.50fF
+C156 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD avss1p8 0.57fF
+C157 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D avss1p8 -1.73fF
+C158 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C159 res_amp_sync_v2_0/clkp avss1p8 -28.00fF
+C160 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C161 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D avss1p8 0.96fF
+C162 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C163 res_amp_sync_v2_0/DFlipFlop_3/D avss1p8 1.33fF
+C164 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD avss1p8 1.14fF
+C165 avdd1p8 avss1p8 415.30fF
+C166 res_amp_sync_v2_0/DFlipFlop_2/nQ avss1p8 0.48fF
+C167 res_amp_sync_v2_0/DFlipFlop_2/Q avss1p8 -1.08fF
+C168 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C169 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD avss1p8 0.57fF
+C170 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D avss1p8 -1.73fF
+C171 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C172 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C173 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D avss1p8 0.96fF
+C174 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C175 res_amp_sync_v2_0/DFlipFlop_2/D avss1p8 -0.38fF
+C176 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD avss1p8 1.14fF
+C177 res_amp_sync_v2_0/DFlipFlop_1/nQ avss1p8 0.48fF
+C178 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C179 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD avss1p8 0.57fF
+C180 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D avss1p8 -1.73fF
+C181 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C182 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C183 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D avss1p8 0.96fF
+C184 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C185 res_amp_sync_v2_0/DFlipFlop_1/D avss1p8 -1.02fF
+C186 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD avss1p8 1.14fF
+C187 res_amp_sync_v2_0/DFlipFlop_0/nQ avss1p8 0.48fF
+C188 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C189 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD avss1p8 0.57fF
+C190 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D avss1p8 -1.73fF
+C191 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C192 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C193 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D avss1p8 0.96fF
+C194 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C195 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD avss1p8 1.14fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C1 m3_2669_n13200# m3_7988_n13200# 2.73fF
+C2 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C3 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C4 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C5 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C6 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C7 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C8 m3_2669_2700# m3_n2650_2700# 2.73fF
+C9 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C10 m3_7988_2700# m3_7988_8000# 3.39fF
+C11 m3_n2650_8000# m3_2669_8000# 2.73fF
+C12 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C13 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C14 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C15 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C16 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C17 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C18 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C19 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C20 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C21 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C22 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C23 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C24 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C25 m3_2669_n13200# m3_n2650_n13200# 2.73fF
+C26 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C27 m3_2669_2700# m3_7988_2700# 2.73fF
+C28 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C29 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C30 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C31 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C32 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C33 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C34 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C35 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C36 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C37 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C38 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C39 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C40 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C41 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C42 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C43 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C44 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C45 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C46 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C47 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C48 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C49 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C50 m3_2669_2700# m3_2669_n2600# 3.28fF
+C51 m3_2669_8000# c1_n13188_n13100# 58.61fF
+C52 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C53 m3_7988_8000# m3_2669_8000# 2.73fF
+C54 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C55 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C56 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C57 m3_7988_n2600# m3_7988_2700# 3.39fF
+C58 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C59 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C60 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C61 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C62 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C63 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C64 m3_2669_2700# m3_2669_8000# 3.28fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C1 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C2 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C3 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C4 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C5 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C6 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C7 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C8 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C9 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C10 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
+C11 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
+C12 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C13 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C14 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C15 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C16 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C17 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C18 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 vc_pex in 0.18fF
+C1 vc_pex vss -38.13fF
+C2 res_loop_filter_2/out vss 8.49fF
+C3 in vss -18.79fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 w_n2457_n634# a_1345_n486# 0.02fF
+C1 w_n2457_n634# a_n1861_n486# 0.02fF
+C2 a_n29_n486# w_n2457_n634# 0.02fF
+C3 a_2261_n486# w_n2457_n634# 0.02fF
+C4 w_n2457_n634# a_n945_n486# 0.02fF
+C5 a_887_n486# w_n2457_n634# 0.02fF
+C6 w_n2457_n634# a_n1403_n486# 0.02fF
+C7 w_n2457_n634# a_1803_n486# 0.02fF
+C8 a_n2319_n486# w_n2457_n634# 0.02fF
+C9 a_n487_n486# w_n2457_n634# 0.02fF
+C10 w_n2457_n634# a_429_n486# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n1229_n75# a_n1041_n75# 0.08fF
+C1 a_1071_n75# a_1167_n75# 0.22fF
+C2 a_n753_n75# a_n1137_n75# 0.03fF
+C3 a_591_n75# a_783_n75# 0.08fF
+C4 a_1167_n75# a_879_n75# 0.05fF
+C5 a_n753_n75# a_n945_n75# 0.08fF
+C6 a_n1229_n75# a_n1137_n75# 0.22fF
+C7 a_n177_n75# a_111_n75# 0.05fF
+C8 a_n1229_n75# a_n945_n75# 0.05fF
+C9 a_n753_n75# a_n561_n75# 0.08fF
+C10 a_n465_n75# a_n369_n75# 0.22fF
+C11 a_n849_n75# a_n657_n75# 0.08fF
+C12 a_n849_n75# a_n1041_n75# 0.08fF
+C13 a_783_n75# a_399_n75# 0.03fF
+C14 a_1071_n75# a_975_n75# 0.22fF
+C15 a_879_n75# a_495_n75# 0.03fF
+C16 a_n1041_n75# a_n657_n75# 0.03fF
+C17 a_303_n75# a_591_n75# 0.05fF
+C18 a_975_n75# a_879_n75# 0.22fF
+C19 a_15_n75# a_399_n75# 0.03fF
+C20 a_n465_n75# a_n273_n75# 0.08fF
+C21 a_783_n75# a_687_n75# 0.22fF
+C22 a_n849_n75# a_n1137_n75# 0.05fF
+C23 a_591_n75# a_207_n75# 0.03fF
+C24 a_n849_n75# a_n945_n75# 0.22fF
+C25 a_303_n75# a_399_n75# 0.22fF
+C26 a_n369_n75# a_n177_n75# 0.08fF
+C27 a_n849_n75# a_n561_n75# 0.05fF
+C28 a_591_n75# a_495_n75# 0.22fF
+C29 a_n657_n75# a_n945_n75# 0.05fF
+C30 a_n1041_n75# a_n1137_n75# 0.22fF
+C31 a_15_n75# a_111_n75# 0.22fF
+C32 a_n1041_n75# a_n945_n75# 0.22fF
+C33 a_n561_n75# a_n657_n75# 0.22fF
+C34 a_591_n75# a_975_n75# 0.03fF
+C35 a_15_n75# a_n177_n75# 0.08fF
+C36 a_207_n75# a_399_n75# 0.08fF
+C37 a_303_n75# a_687_n75# 0.03fF
+C38 a_n273_n75# a_111_n75# 0.03fF
+C39 a_n753_n75# a_n465_n75# 0.05fF
+C40 a_303_n75# a_111_n75# 0.08fF
+C41 a_n273_n75# a_n177_n75# 0.22fF
+C42 a_399_n75# a_495_n75# 0.22fF
+C43 a_n1137_n75# a_n945_n75# 0.08fF
+C44 a_207_n75# a_111_n75# 0.22fF
+C45 a_n81_n75# a_n465_n75# 0.03fF
+C46 a_687_n75# a_495_n75# 0.08fF
+C47 a_n561_n75# a_n945_n75# 0.03fF
+C48 a_207_n75# a_n177_n75# 0.03fF
+C49 a_975_n75# a_687_n75# 0.05fF
+C50 a_495_n75# a_111_n75# 0.03fF
+C51 a_15_n75# a_n369_n75# 0.03fF
+C52 a_n849_n75# a_n465_n75# 0.03fF
+C53 a_n369_n75# a_n273_n75# 0.22fF
+C54 a_1071_n75# a_879_n75# 0.08fF
+C55 a_n465_n75# a_n657_n75# 0.08fF
+C56 a_783_n75# a_1167_n75# 0.03fF
+C57 a_n81_n75# a_111_n75# 0.08fF
+C58 a_15_n75# a_n273_n75# 0.05fF
+C59 a_n81_n75# a_n177_n75# 0.22fF
+C60 a_303_n75# a_15_n75# 0.05fF
+C61 a_n753_n75# a_n369_n75# 0.03fF
+C62 a_783_n75# a_495_n75# 0.05fF
+C63 a_15_n75# a_207_n75# 0.08fF
+C64 a_975_n75# a_783_n75# 0.08fF
+C65 a_n561_n75# a_n465_n75# 0.22fF
+C66 a_591_n75# a_879_n75# 0.05fF
+C67 a_303_n75# a_207_n75# 0.22fF
+C68 a_n81_n75# a_n369_n75# 0.05fF
+C69 a_303_n75# a_495_n75# 0.08fF
+C70 a_n81_n75# a_15_n75# 0.22fF
+C71 a_975_n75# a_1167_n75# 0.08fF
+C72 a_1071_n75# a_687_n75# 0.03fF
+C73 a_207_n75# a_495_n75# 0.05fF
+C74 a_n81_n75# a_n273_n75# 0.08fF
+C75 a_n369_n75# a_n657_n75# 0.05fF
+C76 a_687_n75# a_879_n75# 0.08fF
+C77 a_n561_n75# a_n177_n75# 0.03fF
+C78 a_303_n75# a_n81_n75# 0.03fF
+C79 a_591_n75# a_399_n75# 0.08fF
+C80 a_n81_n75# a_207_n75# 0.05fF
+C81 a_n657_n75# a_n273_n75# 0.03fF
+C82 a_591_n75# a_687_n75# 0.22fF
+C83 a_n561_n75# a_n369_n75# 0.08fF
+C84 a_1071_n75# a_783_n75# 0.05fF
+C85 a_n753_n75# a_n849_n75# 0.22fF
+C86 a_399_n75# a_687_n75# 0.05fF
+C87 a_n849_n75# a_n1229_n75# 0.03fF
+C88 a_783_n75# a_879_n75# 0.22fF
+C89 a_n753_n75# a_n657_n75# 0.22fF
+C90 a_399_n75# a_111_n75# 0.05fF
+C91 a_n465_n75# a_n177_n75# 0.05fF
+C92 a_n753_n75# a_n1041_n75# 0.05fF
+C93 a_n561_n75# a_n273_n75# 0.05fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n417_n75# a_n801_n75# 0.03fF
+C1 a_735_n75# a_447_n75# 0.05fF
+C2 a_n321_n75# a_n33_n75# 0.05fF
+C3 a_543_n75# a_351_n75# 0.08fF
+C4 a_n801_n75# a_n705_n75# 0.22fF
+C5 a_n225_n75# a_n33_n75# 0.08fF
+C6 a_543_n75# a_639_n75# 0.22fF
+C7 a_159_n75# a_n33_n75# 0.08fF
+C8 a_n927_n101# a_33_n101# 0.08fF
+C9 a_n417_n75# a_n321_n75# 0.22fF
+C10 a_n417_n75# a_n225_n75# 0.08fF
+C11 a_n129_n75# a_n321_n75# 0.08fF
+C12 a_n321_n75# a_n705_n75# 0.03fF
+C13 a_255_n75# a_543_n75# 0.05fF
+C14 a_n129_n75# a_n225_n75# 0.22fF
+C15 a_n33_n75# a_351_n75# 0.03fF
+C16 a_n897_n75# a_n705_n75# 0.08fF
+C17 a_n321_n75# a_63_n75# 0.03fF
+C18 a_n225_n75# a_63_n75# 0.05fF
+C19 a_543_n75# a_831_n75# 0.05fF
+C20 a_n129_n75# a_159_n75# 0.05fF
+C21 a_159_n75# a_63_n75# 0.22fF
+C22 a_n801_n75# a_n609_n75# 0.08fF
+C23 a_255_n75# a_n33_n75# 0.05fF
+C24 a_63_n75# a_351_n75# 0.05fF
+C25 a_735_n75# a_351_n75# 0.03fF
+C26 a_n417_n75# a_n513_n75# 0.22fF
+C27 a_n321_n75# a_n609_n75# 0.05fF
+C28 a_n225_n75# a_n609_n75# 0.03fF
+C29 a_n129_n75# a_n513_n75# 0.03fF
+C30 a_n705_n75# a_n513_n75# 0.08fF
+C31 a_n897_n75# a_n609_n75# 0.05fF
+C32 a_n129_n75# a_255_n75# 0.03fF
+C33 a_639_n75# a_735_n75# 0.22fF
+C34 a_n989_n75# a_n705_n75# 0.05fF
+C35 a_255_n75# a_63_n75# 0.08fF
+C36 a_639_n75# a_927_n75# 0.05fF
+C37 a_159_n75# a_447_n75# 0.05fF
+C38 a_735_n75# a_831_n75# 0.22fF
+C39 a_n897_n75# a_n801_n75# 0.22fF
+C40 a_831_n75# a_927_n75# 0.22fF
+C41 a_447_n75# a_351_n75# 0.22fF
+C42 a_n609_n75# a_n513_n75# 0.22fF
+C43 a_639_n75# a_447_n75# 0.08fF
+C44 a_n225_n75# a_n321_n75# 0.22fF
+C45 a_n989_n75# a_n609_n75# 0.03fF
+C46 a_n225_n75# a_159_n75# 0.03fF
+C47 a_255_n75# a_447_n75# 0.08fF
+C48 a_543_n75# a_735_n75# 0.08fF
+C49 a_447_n75# a_831_n75# 0.03fF
+C50 a_n801_n75# a_n513_n75# 0.05fF
+C51 a_543_n75# a_927_n75# 0.03fF
+C52 a_n417_n75# a_n33_n75# 0.03fF
+C53 a_n129_n75# a_n33_n75# 0.22fF
+C54 a_n989_n75# a_n801_n75# 0.08fF
+C55 a_63_n75# a_n33_n75# 0.22fF
+C56 a_159_n75# a_351_n75# 0.08fF
+C57 a_n321_n75# a_n513_n75# 0.08fF
+C58 a_n225_n75# a_n513_n75# 0.05fF
+C59 a_n417_n75# a_n129_n75# 0.05fF
+C60 a_n417_n75# a_n705_n75# 0.05fF
+C61 a_n897_n75# a_n513_n75# 0.03fF
+C62 a_543_n75# a_447_n75# 0.22fF
+C63 a_n129_n75# a_63_n75# 0.08fF
+C64 a_n989_n75# a_n897_n75# 0.22fF
+C65 a_255_n75# a_159_n75# 0.22fF
+C66 a_639_n75# a_351_n75# 0.05fF
+C67 a_255_n75# a_351_n75# 0.22fF
+C68 a_735_n75# a_927_n75# 0.08fF
+C69 a_255_n75# a_639_n75# 0.03fF
+C70 a_n417_n75# a_n609_n75# 0.08fF
+C71 a_n609_n75# a_n705_n75# 0.22fF
+C72 a_639_n75# a_831_n75# 0.08fF
+C73 a_543_n75# a_159_n75# 0.03fF
+C74 a_63_n75# a_447_n75# 0.03fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_255_n150# a_n129_n150# 0.07fF
+C1 a_n417_n150# a_n801_n150# 0.07fF
+C2 a_n705_n150# a_n897_n150# 0.16fF
+C3 a_351_n150# a_n33_n150# 0.07fF
+C4 a_735_n150# a_447_n150# 0.10fF
+C5 a_927_n150# a_543_n150# 0.07fF
+C6 a_159_n150# a_n225_n150# 0.07fF
+C7 a_n225_n150# a_63_n150# 0.10fF
+C8 a_63_n150# a_n321_n150# 0.07fF
+C9 a_n417_n150# a_n225_n150# 0.16fF
+C10 a_255_n150# a_351_n150# 0.43fF
+C11 a_639_n150# a_351_n150# 0.10fF
+C12 a_n417_n150# a_n321_n150# 0.43fF
+C13 a_735_n150# a_831_n150# 0.43fF
+C14 a_159_n150# a_n33_n150# 0.16fF
+C15 a_n417_n150# a_n513_n150# 0.43fF
+C16 a_63_n150# a_n33_n150# 0.43fF
+C17 a_n801_n150# a_n513_n150# 0.10fF
+C18 a_447_n150# a_831_n150# 0.07fF
+C19 a_n417_n150# a_n33_n150# 0.07fF
+C20 a_n225_n150# a_n321_n150# 0.43fF
+C21 a_n609_n150# a_n417_n150# 0.16fF
+C22 a_255_n150# a_159_n150# 0.43fF
+C23 a_n609_n150# a_n801_n150# 0.16fF
+C24 a_255_n150# a_63_n150# 0.16fF
+C25 a_n225_n150# a_n513_n150# 0.10fF
+C26 a_735_n150# a_351_n150# 0.07fF
+C27 a_n801_n150# a_n989_n150# 0.16fF
+C28 a_n513_n150# a_n321_n150# 0.16fF
+C29 a_n225_n150# a_n33_n150# 0.16fF
+C30 a_255_n150# a_543_n150# 0.10fF
+C31 a_639_n150# a_543_n150# 0.43fF
+C32 a_n801_n150# a_n897_n150# 0.43fF
+C33 a_n321_n150# a_n33_n150# 0.10fF
+C34 a_927_n150# a_639_n150# 0.10fF
+C35 a_447_n150# a_351_n150# 0.43fF
+C36 a_n609_n150# a_n225_n150# 0.07fF
+C37 a_n609_n150# a_n321_n150# 0.10fF
+C38 a_n609_n150# a_n513_n150# 0.43fF
+C39 a_n927_n247# a_33_n247# 0.09fF
+C40 a_n897_n150# a_n513_n150# 0.07fF
+C41 a_159_n150# a_447_n150# 0.10fF
+C42 a_735_n150# a_543_n150# 0.16fF
+C43 a_447_n150# a_63_n150# 0.07fF
+C44 a_735_n150# a_927_n150# 0.16fF
+C45 a_255_n150# a_n33_n150# 0.10fF
+C46 a_n609_n150# a_n989_n150# 0.07fF
+C47 a_447_n150# a_543_n150# 0.43fF
+C48 a_n609_n150# a_n897_n150# 0.10fF
+C49 a_n897_n150# a_n989_n150# 0.43fF
+C50 a_159_n150# a_n129_n150# 0.10fF
+C51 a_63_n150# a_n129_n150# 0.16fF
+C52 a_255_n150# a_639_n150# 0.07fF
+C53 a_831_n150# a_543_n150# 0.10fF
+C54 a_n417_n150# a_n129_n150# 0.10fF
+C55 a_927_n150# a_831_n150# 0.43fF
+C56 a_n417_n150# a_n705_n150# 0.10fF
+C57 a_n705_n150# a_n801_n150# 0.43fF
+C58 a_159_n150# a_351_n150# 0.16fF
+C59 a_63_n150# a_351_n150# 0.10fF
+C60 a_n225_n150# a_n129_n150# 0.43fF
+C61 a_735_n150# a_639_n150# 0.43fF
+C62 a_n129_n150# a_n321_n150# 0.16fF
+C63 a_n705_n150# a_n321_n150# 0.07fF
+C64 a_543_n150# a_351_n150# 0.16fF
+C65 a_n513_n150# a_n129_n150# 0.07fF
+C66 a_n705_n150# a_n513_n150# 0.16fF
+C67 a_255_n150# a_447_n150# 0.16fF
+C68 a_639_n150# a_447_n150# 0.16fF
+C69 a_n129_n150# a_n33_n150# 0.43fF
+C70 a_159_n150# a_63_n150# 0.43fF
+C71 a_n609_n150# a_n705_n150# 0.43fF
+C72 a_n705_n150# a_n989_n150# 0.10fF
+C73 a_159_n150# a_543_n150# 0.07fF
+C74 a_639_n150# a_831_n150# 0.16fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_1403_n44# a_1045_n44# 0.04fF
+C1 a_n1819_n44# a_n1461_n44# 0.04fF
+C2 a_1045_n44# a_687_n44# 0.04fF
+C3 a_n745_n44# a_n1103_n44# 0.04fF
+C4 a_1403_n44# a_1761_n44# 0.04fF
+C5 a_687_n44# a_329_n44# 0.04fF
+C6 a_n387_n44# a_n29_n44# 0.04fF
+C7 a_n387_n44# a_n745_n44# 0.04fF
+C8 a_n29_n44# a_329_n44# 0.04fF
+C9 a_n1103_n44# a_n1461_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n465_n150# a_n273_n150# 0.16fF
+C1 a_n465_n150# a_n369_n150# 0.43fF
+C2 a_n753_n150# a_n849_n150# 0.43fF
+C3 a_n177_n150# a_n465_n150# 0.10fF
+C4 a_n273_n150# a_n657_n150# 0.07fF
+C5 a_n1229_n150# a_n849_n150# 0.07fF
+C6 a_n657_n150# a_n369_n150# 0.10fF
+C7 a_1071_n150# a_879_n150# 0.16fF
+C8 a_n81_n150# a_n273_n150# 0.16fF
+C9 a_n81_n150# a_n369_n150# 0.10fF
+C10 a_n177_n150# a_n81_n150# 0.43fF
+C11 a_n945_n150# a_n657_n150# 0.10fF
+C12 a_495_n150# a_783_n150# 0.10fF
+C13 a_591_n150# a_879_n150# 0.10fF
+C14 a_207_n150# a_111_n150# 0.43fF
+C15 a_n1137_n150# a_n1041_n150# 0.43fF
+C16 a_n273_n150# a_n561_n150# 0.10fF
+C17 a_207_n150# a_495_n150# 0.10fF
+C18 a_n561_n150# a_n369_n150# 0.16fF
+C19 a_111_n150# a_15_n150# 0.43fF
+C20 a_n753_n150# a_n465_n150# 0.10fF
+C21 a_n177_n150# a_n561_n150# 0.07fF
+C22 a_399_n150# a_591_n150# 0.16fF
+C23 a_n753_n150# a_n657_n150# 0.43fF
+C24 a_687_n150# a_879_n150# 0.16fF
+C25 a_n945_n150# a_n1041_n150# 0.43fF
+C26 a_n945_n150# a_n561_n150# 0.07fF
+C27 a_n81_n150# a_207_n150# 0.10fF
+C28 a_687_n150# a_399_n150# 0.10fF
+C29 a_687_n150# a_1071_n150# 0.07fF
+C30 a_n81_n150# a_15_n150# 0.43fF
+C31 a_975_n150# a_879_n150# 0.43fF
+C32 a_n753_n150# a_n1041_n150# 0.10fF
+C33 a_n753_n150# a_n561_n150# 0.16fF
+C34 a_111_n150# a_303_n150# 0.16fF
+C35 a_n1229_n150# a_n1041_n150# 0.16fF
+C36 a_687_n150# a_591_n150# 0.43fF
+C37 a_783_n150# a_879_n150# 0.43fF
+C38 a_495_n150# a_303_n150# 0.16fF
+C39 a_975_n150# a_1071_n150# 0.43fF
+C40 a_n273_n150# a_n369_n150# 0.43fF
+C41 a_n177_n150# a_n273_n150# 0.43fF
+C42 a_783_n150# a_399_n150# 0.07fF
+C43 a_n177_n150# a_n369_n150# 0.16fF
+C44 a_783_n150# a_1071_n150# 0.10fF
+C45 a_591_n150# a_975_n150# 0.07fF
+C46 a_207_n150# a_399_n150# 0.16fF
+C47 a_n81_n150# a_303_n150# 0.07fF
+C48 a_399_n150# a_15_n150# 0.07fF
+C49 a_n1137_n150# a_n945_n150# 0.16fF
+C50 a_783_n150# a_591_n150# 0.16fF
+C51 a_n465_n150# a_n849_n150# 0.07fF
+C52 w_n1367_n369# a_879_n150# 0.04fF
+C53 a_687_n150# a_975_n150# 0.10fF
+C54 a_1167_n150# a_879_n150# 0.10fF
+C55 a_n657_n150# a_n849_n150# 0.16fF
+C56 a_207_n150# a_591_n150# 0.07fF
+C57 a_783_n150# a_687_n150# 0.43fF
+C58 w_n1367_n369# a_1071_n150# 0.07fF
+C59 a_495_n150# a_111_n150# 0.07fF
+C60 a_n753_n150# a_n369_n150# 0.07fF
+C61 a_n1137_n150# a_n753_n150# 0.07fF
+C62 a_1071_n150# a_1167_n150# 0.43fF
+C63 a_n1137_n150# a_n1229_n150# 0.43fF
+C64 a_n177_n150# a_207_n150# 0.07fF
+C65 a_n273_n150# a_15_n150# 0.10fF
+C66 a_n369_n150# a_15_n150# 0.07fF
+C67 a_n177_n150# a_15_n150# 0.16fF
+C68 a_n1041_n150# a_n849_n150# 0.16fF
+C69 a_399_n150# a_303_n150# 0.43fF
+C70 a_n945_n150# a_n753_n150# 0.16fF
+C71 a_783_n150# a_975_n150# 0.16fF
+C72 a_n561_n150# a_n849_n150# 0.10fF
+C73 a_n1229_n150# a_n945_n150# 0.10fF
+C74 a_n81_n150# a_111_n150# 0.16fF
+C75 a_n465_n150# a_n657_n150# 0.16fF
+C76 a_591_n150# a_303_n150# 0.10fF
+C77 a_n81_n150# a_n465_n150# 0.07fF
+C78 a_687_n150# a_303_n150# 0.07fF
+C79 a_975_n150# w_n1367_n369# 0.05fF
+C80 a_207_n150# a_15_n150# 0.16fF
+C81 a_495_n150# a_879_n150# 0.07fF
+C82 a_n465_n150# a_n561_n150# 0.43fF
+C83 a_975_n150# a_1167_n150# 0.16fF
+C84 a_n1041_n150# a_n657_n150# 0.07fF
+C85 a_n657_n150# a_n561_n150# 0.43fF
+C86 a_399_n150# a_111_n150# 0.10fF
+C87 a_495_n150# a_399_n150# 0.43fF
+C88 a_783_n150# a_1167_n150# 0.07fF
+C89 a_n1137_n150# a_n849_n150# 0.10fF
+C90 a_495_n150# a_591_n150# 0.43fF
+C91 a_n945_n150# a_n849_n150# 0.43fF
+C92 a_207_n150# a_303_n150# 0.43fF
+C93 a_n273_n150# a_111_n150# 0.07fF
+C94 a_303_n150# a_15_n150# 0.10fF
+C95 a_n177_n150# a_111_n150# 0.10fF
+C96 w_n1367_n369# a_1167_n150# 0.14fF
+C97 a_495_n150# a_687_n150# 0.16fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump vss pswitch nswitch out vdd biasp nUp Down w_2544_775# iref nDown
++ Up w_1008_774#
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 out vdd 6.66fF
+C1 Down nswitch 2.27fF
+C2 pswitch Up 0.70fF
+C3 biasp iref 0.80fF
+C4 Down nUp 0.25fF
+C5 vdd biasp 2.64fF
+C6 pswitch nswitch 0.06fF
+C7 Up nUp 0.15fF
+C8 pswitch nUp 5.66fF
+C9 out pswitch 4.91fF
+C10 out nswitch 1.28fF
+C11 pswitch biasp 3.11fF
+C12 Down nDown 0.13fF
+C13 out nUp 0.31fF
+C14 biasp nswitch 0.03fF
+C15 pswitch vdd 3.98fF
+C16 iref nswitch 1.91fF
+C17 vdd nswitch 0.07fF
+C18 nswitch nDown 0.31fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_n33_n42# a_n125_n42# 0.12fF
+C2 a_n33_n42# a_63_n42# 0.12fF
+C3 a_n125_n42# a_63_n42# 0.05fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n33_n84# a_n125_n84# 0.24fF
+C1 a_n125_n84# a_63_n84# 0.09fF
+C2 a_n33_n84# w_n263_n303# 0.07fF
+C3 a_33_n110# a_n63_n110# 0.02fF
+C4 w_n263_n303# a_63_n84# 0.10fF
+C5 a_n125_n84# w_n263_n303# 0.10fF
+C6 a_n33_n84# a_63_n84# 0.24fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 vdd in 0.01fF
+C1 out in 0.30fF
+C2 out vdd 0.15fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 nout_div clock_inverter_0/inverter_cp_x1_0/out
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/latch_diff_0/nD
++ out_div DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# nout_div
++ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop
+Xinverter_min_x4_1 vdd o2 vss nCLK_2 inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss CLK_2 inverter_min_x4
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 nout_div vdd 0.16fF
+C1 o1 vdd 0.14fF
+C2 o2 vdd 0.14fF
+C3 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C4 nout_div out_div 0.22fF
+C5 DFlipFlop_0/CLK vdd 0.40fF
+C6 DFlipFlop_0/nCLK nout_div 0.43fF
+C7 o1 out_div 0.01fF
+C8 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C9 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C10 nout_div DFlipFlop_0/latch_diff_1/m1_657_280# 0.21fF
+C11 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C12 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C13 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
+C14 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C15 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C16 o1 CLK_2 0.11fF
+C17 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/nD 0.11fF
+C18 o2 nCLK_2 0.11fF
+C19 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C20 vdd out_div 0.03fF
+C21 DFlipFlop_0/nCLK vdd 0.30fF
+C22 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C23 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C24 nout_div DFlipFlop_0/CLK 0.42fF
+C25 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C26 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C27 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
+C28 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C29 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C30 CLK_2 vdd 0.08fF
+C31 vdd nCLK_2 0.08fF
+C32 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C33 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C34 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C35 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C36 DFlipFlop_0/CLK vss 1.03fF
+C37 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C38 CLK vss 3.27fF
+C39 DFlipFlop_0/nCLK vss 1.76fF
+C40 o1 vss 2.21fF
+C41 CLK_2 vss 1.08fF
+C42 o2 vss 2.21fF
+C43 nCLK_2 vss 1.08fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C50 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n129_n600# a_n221_n600# 7.87fF
+C1 a_n221_n600# a_n257_n777# 0.25fF
+C2 a_n129_n600# a_n257_n777# 0.29fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n129_n300# a_n221_n300# 4.05fF
+C1 a_n257_n404# a_n221_n300# 0.21fF
+C2 a_n129_n300# a_n257_n404# 0.30fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in a_3996_n100# vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 vdd in 0.02fF
+C1 vdd a_678_n100# 0.08fF
+C2 a_678_n100# a_3996_n100# 6.52fF
+C3 vdd a_3996_n100# 3.68fF
+C4 out vdd 47.17fF
+C5 out a_3996_n100# 55.19fF
+C6 a_678_n100# in 0.81fF
+C7 a_3996_n100# vss 49.53fF
+C8 vdd vss 20.93fF
+C9 out vss 35.17fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n33_n238# 0.02fF
+C1 a_n73_n150# a_n33_n238# 0.02fF
+C2 a_n73_n150# a_15_n150# 0.51fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# w_n211_n369# 0.20fF
+C1 a_n73_n150# a_n33_181# 0.01fF
+C2 a_15_n150# w_n211_n369# 0.20fF
+C3 a_15_n150# a_n33_181# 0.01fF
+C4 a_n73_n150# a_15_n150# 0.51fF
+C5 a_n33_181# w_n211_n369# 0.05fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n321_n150# a_n417_n150# 0.43fF
+C1 a_n321_n150# a_n33_n150# 0.10fF
+C2 a_159_n150# a_n129_n150# 0.10fF
+C3 a_n465_172# a_63_n150# 0.10fF
+C4 a_n509_n150# a_n465_172# 0.01fF
+C5 a_63_n150# a_447_n150# 0.07fF
+C6 a_n225_n150# a_159_n150# 0.07fF
+C7 a_n465_172# a_447_n150# 0.01fF
+C8 a_n129_n150# a_63_n150# 0.16fF
+C9 a_n129_n150# a_n465_172# 0.10fF
+C10 a_n509_n150# a_n129_n150# 0.07fF
+C11 a_n225_n150# a_63_n150# 0.10fF
+C12 a_n225_n150# a_n465_172# 0.10fF
+C13 a_n509_n150# a_n225_n150# 0.10fF
+C14 a_255_n150# a_n33_n150# 0.10fF
+C15 a_n321_n150# a_63_n150# 0.07fF
+C16 a_n321_n150# a_n465_172# 0.10fF
+C17 a_n509_n150# a_n321_n150# 0.16fF
+C18 a_n225_n150# a_n129_n150# 0.43fF
+C19 a_159_n150# a_255_n150# 0.43fF
+C20 a_351_n150# a_255_n150# 0.43fF
+C21 a_n321_n150# a_n129_n150# 0.16fF
+C22 a_n321_n150# a_n225_n150# 0.43fF
+C23 a_n33_n150# a_n417_n150# 0.07fF
+C24 a_63_n150# a_255_n150# 0.16fF
+C25 a_n465_172# a_255_n150# 0.10fF
+C26 a_255_n150# a_447_n150# 0.16fF
+C27 a_n129_n150# a_255_n150# 0.07fF
+C28 a_159_n150# a_n33_n150# 0.16fF
+C29 a_351_n150# a_n33_n150# 0.07fF
+C30 a_n465_172# a_n417_n150# 0.10fF
+C31 a_159_n150# a_351_n150# 0.16fF
+C32 a_n509_n150# a_n417_n150# 0.43fF
+C33 a_63_n150# a_n33_n150# 0.43fF
+C34 a_n465_172# a_n33_n150# 0.10fF
+C35 a_n129_n150# a_n417_n150# 0.10fF
+C36 a_n129_n150# a_n33_n150# 0.43fF
+C37 a_159_n150# a_63_n150# 0.43fF
+C38 a_63_n150# a_351_n150# 0.10fF
+C39 a_159_n150# a_n465_172# 0.10fF
+C40 a_n465_172# a_351_n150# 0.10fF
+C41 a_n225_n150# a_n417_n150# 0.16fF
+C42 a_159_n150# a_447_n150# 0.10fF
+C43 a_351_n150# a_447_n150# 0.43fF
+C44 a_n225_n150# a_n33_n150# 0.16fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n647_n369# a_n129_n150# 0.02fF
+C1 a_n225_n150# w_n647_n369# 0.04fF
+C2 a_n33_n150# a_n465_n247# 0.08fF
+C3 a_n33_n150# a_n417_n150# 0.07fF
+C4 a_255_n150# a_n465_n247# 0.08fF
+C5 a_n321_n150# a_63_n150# 0.07fF
+C6 a_159_n150# a_n465_n247# 0.08fF
+C7 w_n647_n369# a_n465_n247# 0.47fF
+C8 a_n417_n150# w_n647_n369# 0.07fF
+C9 a_n321_n150# a_n129_n150# 0.16fF
+C10 a_n225_n150# a_n321_n150# 0.43fF
+C11 a_n509_n150# a_n129_n150# 0.07fF
+C12 a_n33_n150# a_255_n150# 0.10fF
+C13 a_n509_n150# a_n225_n150# 0.10fF
+C14 a_n33_n150# a_159_n150# 0.16fF
+C15 a_255_n150# a_447_n150# 0.16fF
+C16 a_351_n150# a_63_n150# 0.10fF
+C17 a_159_n150# a_447_n150# 0.10fF
+C18 a_159_n150# a_255_n150# 0.43fF
+C19 a_n33_n150# w_n647_n369# 0.02fF
+C20 a_n321_n150# a_n465_n247# 0.08fF
+C21 a_63_n150# a_n129_n150# 0.16fF
+C22 a_n417_n150# a_n321_n150# 0.43fF
+C23 w_n647_n369# a_447_n150# 0.14fF
+C24 a_255_n150# w_n647_n369# 0.05fF
+C25 a_n225_n150# a_63_n150# 0.10fF
+C26 a_159_n150# w_n647_n369# 0.04fF
+C27 a_n509_n150# a_n417_n150# 0.43fF
+C28 a_n225_n150# a_n129_n150# 0.43fF
+C29 a_n33_n150# a_n321_n150# 0.10fF
+C30 a_63_n150# a_n465_n247# 0.08fF
+C31 a_351_n150# a_n465_n247# 0.08fF
+C32 a_n129_n150# a_n465_n247# 0.08fF
+C33 a_n417_n150# a_n129_n150# 0.10fF
+C34 w_n647_n369# a_n321_n150# 0.05fF
+C35 a_n225_n150# a_n465_n247# 0.08fF
+C36 a_n417_n150# a_n225_n150# 0.16fF
+C37 a_n33_n150# a_63_n150# 0.43fF
+C38 a_n509_n150# w_n647_n369# 0.14fF
+C39 a_n33_n150# a_351_n150# 0.07fF
+C40 a_447_n150# a_63_n150# 0.07fF
+C41 a_255_n150# a_63_n150# 0.16fF
+C42 a_159_n150# a_63_n150# 0.43fF
+C43 a_447_n150# a_351_n150# 0.43fF
+C44 a_255_n150# a_351_n150# 0.43fF
+C45 a_n33_n150# a_n129_n150# 0.43fF
+C46 a_159_n150# a_351_n150# 0.16fF
+C47 a_n417_n150# a_n465_n247# 0.08fF
+C48 w_n647_n369# a_63_n150# 0.02fF
+C49 a_n33_n150# a_n225_n150# 0.16fF
+C50 a_255_n150# a_n129_n150# 0.07fF
+C51 w_n647_n369# a_351_n150# 0.07fF
+C52 a_159_n150# a_n129_n150# 0.10fF
+C53 a_n509_n150# a_n321_n150# 0.16fF
+C54 a_159_n150# a_n225_n150# 0.07fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n99# a_15_n11# 0.02fF
+C1 a_n73_n11# a_15_n11# 0.15fF
+C2 a_n33_n99# a_n73_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_n78_n114# 0.20fF
+C1 w_n216_n334# a_20_n114# 0.20fF
+C2 a_n78_n114# a_20_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 out vbulkp 0.08fF
+C1 in vdd 0.01fF
+C2 vdd vbulkp 0.04fF
+C3 in vss 0.01fF
+C4 in out 0.11fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch vctrl inverter_csvco_0/vdd in vbp cap_vco_0/t D0 out inverter_csvco_0/vss
++ vss vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 inverter_csvco_0/vdd vdd 1.89fF
+C1 inverter_csvco_0/vdd out 0.02fF
+C2 inverter_csvco_0/vdd in 0.01fF
+C3 inverter_csvco_0/vss out 0.03fF
+C4 inverter_csvco_0/vss in 0.01fF
+C5 D0 inverter_csvco_0/vss 0.02fF
+C6 out in 0.06fF
+C7 D0 out 0.09fF
+C8 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C9 inverter_csvco_0/vdd vbp 0.75fF
+C10 cap_vco_0/t vdd 0.04fF
+C11 vdd vbp 1.21fF
+C12 cap_vco_0/t out 0.70fF
+C13 inverter_csvco_0/vss vctrl 0.87fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc csvco_branch_0/inverter_csvco_0/vdd vctrl csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch_2/inverter_csvco_0/vdd vdd vss csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl csvco_branch_0/inverter_csvco_0/vdd out_vco csvco_branch_2/vbp
++ csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in csvco_branch_0/inverter_csvco_0/vss
++ vss vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/inverter_csvco_0/vdd csvco_branch_2/in csvco_branch_2/vbp
++ csvco_branch_2/cap_vco_0/t D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/inverter_csvco_0/vdd csvco_branch_1/in csvco_branch_2/vbp
++ csvco_branch_1/cap_vco_0/t D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss
++ vss vdd csvco_branch
+C0 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
+C1 D0 vctrl 4.41fF
+C2 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C3 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C4 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
+C5 vdd csvco_branch_2/vbp 1.49fF
+C6 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C7 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
+C8 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C9 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C10 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C11 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C12 out_vco csvco_branch_2/in 0.58fF
+C13 csvco_branch_2/vbp vctrl 0.06fF
+C14 out_vco csvco_branch_1/in 0.76fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_1 vdd out_div vss out_pad inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss out_div inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 vdd o1 0.09fF
+C1 vdd out_div 0.17fF
+C2 o1 out_div 0.11fF
+C3 out_pad vdd 0.10fF
+C4 out_pad out_div 0.15fF
+C5 in_vco vss 0.83fF
+C6 o1 vss 2.72fF
+C7 vdd vss 14.54fF
+C8 out_div vss 3.00fF
+C9 out_pad vss 0.70fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_355_368# VPWR 0.37fF
+C1 a_355_368# B 0.08fF
+C2 a_355_368# X 0.17fF
+C3 a_194_125# a_158_392# 0.06fF
+C4 a_194_125# A 0.18fF
+C5 VPWR A 0.15fF
+C6 B A 0.28fF
+C7 a_194_125# VPWR 0.33fF
+C8 B a_194_125# 0.57fF
+C9 a_194_125# X 0.29fF
+C10 VGND A 0.31fF
+C11 a_194_125# VGND 0.25fF
+C12 a_355_368# A 0.02fF
+C13 a_355_368# a_194_125# 0.51fF
+C14 B VPWR 0.09fF
+C15 VPWR X 0.07fF
+C16 B X 0.13fF
+C17 VPB VPWR 0.06fF
+C18 VGND VPWR 0.01fF
+C19 B VGND 0.10fF
+C20 VGND X 0.28fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 X VGND 0.15fF
+C1 B VGND 0.03fF
+C2 a_56_136# VPWR 0.57fF
+C3 A VPWR 0.07fF
+C4 X VPWR 0.20fF
+C5 B VPWR 0.02fF
+C6 VPB VPWR 0.04fF
+C7 A a_56_136# 0.17fF
+C8 X a_56_136# 0.26fF
+C9 B a_56_136# 0.30fF
+C10 A B 0.08fF
+C11 a_56_136# VGND 0.06fF
+C12 A VGND 0.21fF
+C13 B X 0.02fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VPB VPWR 0.04fF
+C1 X VPWR 0.18fF
+C2 A B 0.10fF
+C3 VGND B 0.11fF
+C4 A X 0.02fF
+C5 VGND X 0.16fF
+C6 a_63_368# VPWR 0.29fF
+C7 A a_63_368# 0.28fF
+C8 VGND a_63_368# 0.27fF
+C9 A VPWR 0.05fF
+C10 a_63_368# a_152_368# 0.03fF
+C11 B a_63_368# 0.14fF
+C12 X a_63_368# 0.33fF
+C13 B VPWR 0.01fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK DFlipFlop_0/latch_diff_1/nD
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vdd vss Q0 CLK DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ DFlipFlop_3/latch_diff_0/D nQ0 DFlipFlop_1/latch_diff_0/nD DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/D CLK_5 nQ2 Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D DFlipFlop_2/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/latch_diff_0/nD sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_1/D
++ DFlipFlop_2/nQ DFlipFlop_3/latch_diff_0/nD DFlipFlop_2/latch_diff_0/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_0/D sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D
++ sky130_fd_sc_hs__or2_1_0/a_63_368# DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# sky130_fd_sc_hs__and2_1_0/a_143_136# DFlipFlop_2/latch_diff_0/nD
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/D
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss vdd DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss vdd DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# Q1 DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out CLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C1 DFlipFlop_1/D nQ0 0.12fF
+C2 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C3 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
+C4 nCLK DFlipFlop_0/Q 0.11fF
+C5 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C6 vdd CLK_5 0.15fF
+C7 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C8 Q1 nCLK -0.01fF
+C9 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C10 DFlipFlop_0/Q CLK 0.08fF
+C11 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
+C12 Q1 CLK -0.10fF
+C13 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
+C14 vdd Q1 9.49fF
+C15 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C16 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C17 vdd Q1_shift 0.10fF
+C18 DFlipFlop_2/nQ Q1 0.31fF
+C19 nQ2 nQ0 0.03fF
+C20 Q0 DFlipFlop_0/D 0.39fF
+C21 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
+C22 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C23 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
+C24 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C25 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C26 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C27 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C28 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C29 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C30 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C31 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C32 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
+C33 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C34 DFlipFlop_0/D Q1 0.13fF
+C35 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C36 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C37 nCLK nQ0 0.09fF
+C38 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C39 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C40 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C41 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
+C42 DFlipFlop_3/nQ Q1 0.10fF
+C43 nQ0 CLK 0.19fF
+C44 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C45 vdd nQ0 0.11fF
+C46 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C47 DFlipFlop_2/D Q0 0.25fF
+C48 DFlipFlop_3/nQ Q1_shift 0.04fF
+C49 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
+C50 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C51 DFlipFlop_1/D nCLK 0.14fF
+C52 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C53 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C54 DFlipFlop_1/D CLK 0.21fF
+C55 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C56 vdd DFlipFlop_1/D 0.25fF
+C57 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.08fF
+C58 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q0 0.42fF
+C59 sky130_fd_sc_hs__and2_1_1/a_56_136# CLK 0.06fF
+C60 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C61 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C62 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C63 DFlipFlop_2/D Q1 0.10fF
+C64 Q0 sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.26fF
+C65 Q0 DFlipFlop_0/Q 0.21fF
+C66 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
+C67 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C68 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C69 Q0 Q1 9.65fF
+C70 nQ2 nCLK 0.10fF
+C71 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C72 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C73 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
+C74 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C75 nQ2 CLK 0.17fF
+C76 vdd nQ2 0.04fF
+C77 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C78 DFlipFlop_2/latch_diff_0/D nCLK 0.11fF
+C79 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C80 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q1 0.21fF
+C81 Q0 DFlipFlop_0/latch_diff_1/D 0.23fF
+C82 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
+C83 Q1 DFlipFlop_0/Q 0.13fF
+C84 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C85 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C86 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C87 Q1_shift Q1 0.36fF
+C88 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C89 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C90 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C91 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C92 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C93 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C94 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.08fF
+C95 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
+C96 vdd nCLK 0.34fF
+C97 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C98 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C99 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C100 DFlipFlop_2/nQ nCLK 0.09fF
+C101 DFlipFlop_2/latch_diff_1/nD CLK 0.09fF
+C102 vdd CLK 0.41fF
+C103 Q0 nQ0 0.33fF
+C104 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C105 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C106 DFlipFlop_1/latch_diff_0/nD CLK 0.08fF
+C107 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C108 DFlipFlop_2/nQ CLK 0.13fF
+C109 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C110 vdd DFlipFlop_2/nQ 0.02fF
+C111 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C112 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C113 Q0 DFlipFlop_1/D 0.07fF
+C114 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C115 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C116 sky130_fd_sc_hs__and2_1_0/a_56_136# Q1 0.14fF
+C117 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C118 Q1 nQ0 0.06fF
+C119 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C120 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
+C121 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C122 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C123 vdd DFlipFlop_0/D 0.19fF
+C124 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C125 DFlipFlop_3/nQ nCLK 0.02fF
+C126 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C127 DFlipFlop_1/D Q1 0.03fF
+C128 nQ2 Q0 0.23fF
+C129 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C130 DFlipFlop_3/nQ CLK 0.01fF
+C131 vdd DFlipFlop_3/nQ 0.02fF
+C132 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C133 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
+C134 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C135 sky130_fd_sc_hs__and2_1_1/a_143_136# CLK 0.03fF
+C136 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q1 0.09fF
+C137 DFlipFlop_3/latch_diff_0/D CLK 0.11fF
+C138 nQ2 DFlipFlop_0/Q 0.09fF
+C139 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
+C140 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C141 DFlipFlop_2/D nCLK 0.41fF
+C142 nQ2 Q1 0.07fF
+C143 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C144 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C145 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C146 Q0 nCLK 0.20fF
+C147 DFlipFlop_2/D CLK 0.14fF
+C148 vdd DFlipFlop_2/D 0.07fF
+C149 DFlipFlop_1/latch_diff_1/m1_657_280# nQ0 0.21fF
+C150 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C151 DFlipFlop_2/latch_diff_0/D Q1 0.42fF
+C152 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C153 Q0 CLK 0.08fF
+C154 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
+C155 vdd Q0 5.33fF
+C156 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK 0.14fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C168 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 Q1 vss 8.55fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C172 nQ0 vss 3.42fF
+C173 Q0 vss 0.53fF
+C174 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C175 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C176 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C177 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C178 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C179 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C180 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C181 DFlipFlop_1/D vss 3.72fF
+C182 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C183 DFlipFlop_2/nQ vss 0.50fF
+C184 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C185 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C186 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C187 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C189 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C190 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C191 DFlipFlop_2/D vss 5.34fF
+C192 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C202 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n317_n125# a_63_n125# 0.06fF
+C1 a_159_n125# a_63_n125# 0.36fF
+C2 a_255_n125# a_63_n125# 0.13fF
+C3 a_n33_n125# a_n129_n125# 0.36fF
+C4 a_n129_n125# a_n225_n125# 0.36fF
+C5 a_255_n125# a_159_n125# 0.36fF
+C6 a_n159_n151# a_n255_n151# 0.02fF
+C7 a_n33_n125# a_63_n125# 0.36fF
+C8 a_63_n125# a_n225_n125# 0.08fF
+C9 a_n317_n125# a_n33_n125# 0.08fF
+C10 a_n317_n125# a_n225_n125# 0.36fF
+C11 a_n33_n125# a_159_n125# 0.13fF
+C12 a_159_n125# a_n225_n125# 0.06fF
+C13 a_n33_n125# a_255_n125# 0.08fF
+C14 a_n129_n125# a_63_n125# 0.13fF
+C15 a_225_n151# a_129_n151# 0.02fF
+C16 a_n317_n125# a_n129_n125# 0.13fF
+C17 a_n33_n125# a_n225_n125# 0.13fF
+C18 a_159_n125# a_n129_n125# 0.08fF
+C19 a_33_n151# a_n63_n151# 0.02fF
+C20 a_255_n125# a_n129_n125# 0.06fF
+C21 a_33_n151# a_129_n151# 0.02fF
+C22 a_n63_n151# a_n159_n151# 0.02fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n159_n154# a_n255_n154# 0.02fF
+C1 w_n455_n344# a_63_n125# 0.04fF
+C2 a_n129_n125# a_n33_n125# 0.36fF
+C3 a_n317_n125# w_n455_n344# 0.11fF
+C4 a_n317_n125# a_63_n125# 0.06fF
+C5 a_255_n125# w_n455_n344# 0.11fF
+C6 a_255_n125# a_63_n125# 0.13fF
+C7 a_n225_n125# a_n33_n125# 0.13fF
+C8 a_159_n125# a_n33_n125# 0.13fF
+C9 a_n129_n125# w_n455_n344# 0.04fF
+C10 a_n129_n125# a_63_n125# 0.13fF
+C11 a_33_n154# a_129_n154# 0.02fF
+C12 a_225_n154# a_129_n154# 0.02fF
+C13 a_n317_n125# a_n129_n125# 0.13fF
+C14 a_n129_n125# a_255_n125# 0.06fF
+C15 a_n159_n154# a_n63_n154# 0.02fF
+C16 a_n225_n125# w_n455_n344# 0.06fF
+C17 a_n225_n125# a_63_n125# 0.08fF
+C18 a_159_n125# w_n455_n344# 0.06fF
+C19 a_159_n125# a_63_n125# 0.36fF
+C20 a_n317_n125# a_n225_n125# 0.36fF
+C21 a_159_n125# a_255_n125# 0.36fF
+C22 a_n63_n154# a_33_n154# 0.02fF
+C23 a_n129_n125# a_n225_n125# 0.36fF
+C24 a_159_n125# a_n129_n125# 0.08fF
+C25 w_n455_n344# a_n33_n125# 0.05fF
+C26 a_63_n125# a_n33_n125# 0.36fF
+C27 a_n317_n125# a_n33_n125# 0.08fF
+C28 a_255_n125# a_n33_n125# 0.08fF
+C29 a_159_n125# a_n225_n125# 0.06fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 out vdd 0.29fF
+C1 out in 0.85fF
+C2 in vdd 0.04fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss vdd inverter_cp_x1_0/out inverter_cp_x1_2/in Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in vdd 0.42fF
+C1 Down vdd 0.09fF
+C2 vdd nUp 0.14fF
+C3 Down inverter_cp_x1_0/out 0.12fF
+C4 inverter_cp_x1_2/in Up 0.12fF
+C5 nDown Down 0.23fF
+C6 vdd inverter_cp_x1_0/out 0.25fF
+C7 nDown vdd 0.80fF
+C8 nUp Up 0.20fF
+C9 vdd Up 0.60fF
+C10 vdd QB 0.02fF
+C11 nDown inverter_cp_x1_0/out 0.11fF
+C12 QA vdd 0.02fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n33_n90# a_63_n90# 0.26fF
+C1 a_159_n90# a_n129_n90# 0.06fF
+C2 a_n221_n90# w_n359_n309# 0.09fF
+C3 a_n33_n90# a_159_n90# 0.09fF
+C4 a_n221_n90# a_63_n90# 0.06fF
+C5 w_n359_n309# a_63_n90# 0.06fF
+C6 a_n221_n90# a_159_n90# 0.04fF
+C7 a_159_n90# w_n359_n309# 0.09fF
+C8 a_n33_n90# a_n129_n90# 0.26fF
+C9 a_159_n90# a_63_n90# 0.26fF
+C10 a_n221_n90# a_n129_n90# 0.26fF
+C11 a_n159_n207# a_n63_n116# 0.12fF
+C12 a_n129_n90# w_n359_n309# 0.06fF
+C13 a_n221_n90# a_n33_n90# 0.09fF
+C14 a_n33_n90# w_n359_n309# 0.05fF
+C15 a_n129_n90# a_63_n90# 0.09fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n33_n45# a_n125_n45# 0.13fF
+C1 a_33_n71# a_n129_71# 0.04fF
+C2 a_n33_n45# a_63_n45# 0.13fF
+C3 a_n125_n45# a_63_n45# 0.05fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 out vdd 0.11fF
+C1 A out 0.06fF
+C2 A vdd 0.09fF
+C3 B out 0.40fF
+C4 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C5 A B 0.24fF
+C6 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C7 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vdd vss nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 Reset Q 0.14fF
+C1 Reset nor_pfd_3/A 0.12fF
+C2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C3 CLK Q 0.04fF
+C4 nor_pfd_2/B Q 2.22fF
+C5 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C6 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C7 nor_pfd_2/B vdd 0.02fF
+C8 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C9 nor_pfd_2/B nor_pfd_3/A 0.58fF
+C10 vdd Q 0.08fF
+C11 nor_pfd_3/A Q 0.98fF
+C12 nor_pfd_3/A vdd 0.09fF
+C13 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C14 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C15 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C16 nor_pfd_2/A Q 1.38fF
+C17 nor_pfd_2/A vdd -0.01fF
+C18 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C19 Reset nor_pfd_2/B 0.43fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 Reset vss 1.48fF
+C24 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 nor_pfd_2/A vss 2.56fF
+C27 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 Q vss 2.77fF
+C29 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 nor_pfd_3/A vss 3.16fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_n45# a_n221_n45# 0.13fF
+C1 a_n159_n173# a_n63_n71# 0.10fF
+C2 a_n129_n45# a_159_n45# 0.03fF
+C3 a_n33_n45# a_n221_n45# 0.05fF
+C4 a_n33_n45# a_159_n45# 0.05fF
+C5 a_63_n45# a_n129_n45# 0.05fF
+C6 a_159_n45# a_n221_n45# 0.02fF
+C7 a_63_n45# a_n33_n45# 0.13fF
+C8 a_63_n45# a_n221_n45# 0.03fF
+C9 a_63_n45# a_159_n45# 0.13fF
+C10 a_n129_n45# a_n33_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n33_n90# a_63_n90# 0.26fF
+C1 a_n33_n90# a_n125_n90# 0.26fF
+C2 a_n99_n187# a_33_n187# 0.04fF
+C3 a_n125_n90# a_63_n90# 0.09fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_15_n45# a_n73_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 w_n211_n309# a_n73_n90# 0.04fF
+C1 w_n211_n309# a_15_n90# 0.09fF
+C2 a_n73_n90# a_15_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 vdd A 0.05fF
+C1 a_656_410# A 0.04fF
+C2 B A 0.33fF
+C3 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
+C4 out sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.03fF
+C5 a_656_410# vdd 0.20fF
+C6 a_656_410# B 0.30fF
+C7 out vdd 0.10fF
+C8 out a_656_410# 0.20fF
+C9 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vdd vss dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vdd vss dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C1 vdd Reset 0.02fF
+C2 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C3 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C4 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
+C5 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
+C6 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
+C7 Up vdd 1.62fF
+C8 Down vdd 0.08fF
+C9 Down Up 0.06fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C19 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C20 Down vss 3.74fF
+C21 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C22 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C23 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C25 B vss 1.07fF
+C26 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C27 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C28 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C29 Reset vss 3.85fF
+C30 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C31 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C32 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C33 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C34 Up vss 3.18fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C36 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C37 vdd vss 44.73fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v1 vco_vctrl vdd pswitch ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ charge_pump_0/w_2544_775# ring_osc_0/csvco_branch_2/vbp biasp in_ref Down vss w_13905_n238#
++ vco_D0 buffer_salida_0/a_3996_n100# ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ QA charge_pump_0/w_1008_774# iref_cp ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
++ out_to_div nDown out_to_pad Up nUp
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
++ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
++ vss vdd buffer_salida
+Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd vss ring_osc_0/csvco_branch_2/vbp
++ ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t
++ vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
++ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
++ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
++ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C1 div_5_nQ2 out_by_2 0.16fF
+C2 Up biasp 0.26fF
+C3 QA vdd -0.04fF
+C4 Down iref_cp 0.09fF
+C5 div_5_Q1 vco_vctrl 0.14fF
+C6 vco_vctrl div_5_Q0 0.48fF
+C7 div_5_Q1 out_div_by_5 0.01fF
+C8 vco_vctrl nswitch -0.06fF
+C9 nUp vdd 0.05fF
+C10 nDown vdd 0.22fF
+C11 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C12 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C13 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C14 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C15 vco_D0 vdd 0.03fF
+C16 pswitch Up 1.98fF
+C17 nDown nUp -0.09fF
+C18 n_out_by_2 vco_vctrl 0.52fF
+C19 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
+C20 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C21 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C22 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
+C23 div_by_5_0/DFlipFlop_3/latch_diff_0/D out_by_2 0.11fF
+C24 buffer_salida_0/a_678_n100# out_to_buffer 0.22fF
+C25 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
+C26 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C27 out_to_div out_to_buffer 0.13fF
+C28 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
+C29 Up vdd 0.28fF
+C30 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C31 nDown Down 2.55fF
+C32 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C33 out_by_2 vco_vctrl 0.53fF
+C34 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
+C35 Up nUp 2.72fF
+C36 nswitch nDown 0.76fF
+C37 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C38 vdd lf_vc 0.02fF
+C39 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
+C40 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
+C41 n_out_by_2 vdd 1.03fF
+C42 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
+C43 out_div_by_5 div_5_Q1_shift 0.05fF
+C44 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C45 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C46 buffer_salida_0/a_678_n100# vdd 0.24fF
+C47 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
+C48 nswitch Down 0.54fF
+C49 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C50 out_to_div vdd 0.21fF
+C51 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
+C52 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
+C53 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C54 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C55 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C56 out_by_2 vdd 0.97fF
+C57 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C58 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C59 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C60 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C61 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C62 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 0.27fF
+C63 n_out_by_2 div_5_nQ0 0.10fF
+C64 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C65 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C66 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
+C67 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C68 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
+C69 div_5_Q1 n_out_by_2 1.04fF
+C70 n_out_by_2 div_5_Q0 -0.12fF
+C71 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C72 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C73 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.17fF
+C74 vdd out_to_buffer 0.07fF
+C75 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C76 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C77 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C78 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C79 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
+C80 vco_vctrl vdd -1.02fF
+C81 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
+C82 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
+C83 out_div_by_5 vdd 0.28fF
+C84 nUp biasp -0.17fF
+C85 nDown biasp 0.26fF
+C86 vdd iref_cp 0.15fF
+C87 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C88 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C89 out_by_2 div_5_nQ0 0.32fF
+C90 vco_vctrl nUp 0.02fF
+C91 n_out_by_2 div_5_nQ2 0.10fF
+C92 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C93 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C94 div_by_5_0/DFlipFlop_0/Q out_by_2 0.09fF
+C95 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
+C96 div_5_Q1 out_by_2 0.42fF
+C97 out_by_2 div_5_Q0 0.09fF
+C98 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C99 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C100 pswitch nUp 0.85fF
+C101 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
+C102 pswitch nDown 0.53fF
+C103 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
+C104 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C105 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
+C106 Down biasp 1.24fF
+C107 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C118 QB vss 4.46fF
+C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss -0.40fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 pfd_reset vss 2.17fF
+C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C132 QA vss 4.31fF
+C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 5.50fF
+C141 Up vss 2.37fF
+C142 Down vss 7.92fF
+C143 nDown vss -2.20fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_5_Q1 vss 4.28fF
+C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C158 div_5_nQ0 vss 0.59fF
+C159 div_5_Q0 vss 0.01fF
+C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_first_buffer vss 2.88fF
+C196 out_to_div vss 4.46fF
+C197 out_to_buffer vss 1.57fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 vco_D0 vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 buffer_salida_0/a_3996_n100# vss 48.29fF
+C213 out_to_pad vss 7.50fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C217 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C218 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C219 out_buffer_div_2 vss 1.60fF
+C220 n_out_buffer_div_2 vss 1.63fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 nswitch vss 3.73fF
+C232 biasp vss 5.44fF
+C233 iref_cp vss 2.81fF
+C234 vco_vctrl vss -19.28fF
+C235 pswitch vss 3.57fF
+C236 lf_vc vss -59.89fF
+C237 loop_filter_0/res_loop_filter_2/out vss 7.90fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_2_2Y8F6P VSUBS c2_n3251_n3000# m4_n3351_n3100#
+X0 c2_n3251_n3000# m4_n3351_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+C0 m4_n3351_n3100# c2_n3251_n3000# 72.82fF
+C1 m4_n3351_n3100# VSUBS 14.58fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_8P223X VSUBS a_n2017_n1317# a_n1731_n1219# a_n1879_n1219#
++ a_n2017_n61# w_n2018_n202#
+X0 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X1 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X2 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X3 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X4 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X5 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X6 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X7 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X8 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X9 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X10 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X11 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X12 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X13 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X14 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X15 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X16 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X17 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X18 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X19 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X20 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X21 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X22 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X23 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X24 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X25 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X26 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X27 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X28 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X29 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X30 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X31 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X32 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X33 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X34 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X35 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X36 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X37 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X38 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X39 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X40 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X41 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X42 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X43 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X44 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X45 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X46 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X47 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X48 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+C0 a_n2017_n61# w_n2018_n202# 1.37fF
+C1 a_n1879_n1219# a_n1731_n1219# 19.29fF
+C2 a_n2017_n1317# a_n1731_n1219# 4.73fF
+C3 a_n2017_n1317# a_n1879_n1219# 2.66fF
+C4 a_n2017_n61# a_n1731_n1219# 5.23fF
+C5 a_n2017_n61# a_n1879_n1219# 0.16fF
+C6 a_n2017_n61# a_n2017_n1317# 2.88fF
+C7 w_n2018_n202# a_n1731_n1219# 19.90fF
+C8 w_n2018_n202# a_n1879_n1219# 0.25fF
+C9 w_n2018_n202# a_n2017_n1317# 0.16fF
+C10 a_n1879_n1219# VSUBS 1.53fF
+C11 a_n2017_n1317# VSUBS 5.03fF
+C12 a_n1731_n1219# VSUBS 2.60fF
+C13 a_n2017_n61# VSUBS 5.10fF
+C14 w_n2018_n202# VSUBS 37.43fF
+.ends
+
+.subckt bias VSUBS vdd iref_0 iref_1 iref_2 iref_5 iref_6 iref_7 iref_8 iref_9 iref
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_5 VSUBS iref m1_20168_984# iref m1_20168_984#
++ vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_6 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219#
++ iref_5 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_7 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219#
++ iref_6 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_9 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219#
++ iref_8 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_8 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219#
++ iref_7 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_10 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219#
++ iref_9 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_0 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219#
++ iref_0 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_1 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219#
++ iref_1 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_2 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219#
++ iref_2 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_3 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219#
++ iref_3 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_4 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219#
++ iref_4 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+C0 iref_2 iref_3 0.05fF
+C1 iref_5 iref_6 0.05fF
+C2 iref_9 iref -0.01fF
+C3 iref_7 iref_6 0.05fF
+C4 vdd iref -0.07fF
+C5 iref_5 iref 0.05fF
+C6 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# 0.24fF
+C7 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# m1_20168_984# 0.01fF
+C8 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vdd 0.24fF
+C9 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# iref -0.15fF
+C10 iref_2 iref_1 0.05fF
+C11 iref_9 iref_8 0.05fF
+C12 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vdd 0.24fF
+C13 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# iref_6 0.24fF
+C14 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# 0.67fF
+C15 iref_1 iref_0 0.05fF
+C16 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# iref_5 0.24fF
+C17 iref_4 iref 0.30fF
+C18 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C19 iref_8 iref_7 0.05fF
+C20 vdd m1_20168_984# 0.25fF
+C21 iref_3 iref_4 0.05fF
+C22 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# iref_1 0.24fF
+C23 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# iref_8 0.24fF
+C24 sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# m1_20168_984# 0.54fF
+C25 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.01fF
+C26 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# iref_7 0.24fF
+C27 iref_2 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
+C28 iref_8 iref -0.03fF
+C29 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref 0.02fF
+C30 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# m1_20168_984# -0.39fF
+C31 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# 0.24fF
+C32 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
+C33 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref_3 0.24fF
+C34 iref_1 iref -0.02fF
+C35 m1_20168_984# iref 0.07fF
+C36 iref_2 iref -0.01fF
+C37 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vdd 0.24fF
+C38 iref VSUBS 32.42fF
+C39 iref_4 VSUBS 1.17fF
+C40 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# VSUBS 2.60fF
+C41 iref_3 VSUBS 0.64fF
+C42 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# VSUBS 2.60fF
+C43 iref_2 VSUBS -1.26fF
+C44 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# VSUBS 2.60fF
+C45 iref_1 VSUBS -0.80fF
+C46 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# VSUBS 2.60fF
+C47 m1_20168_984# VSUBS 56.92fF
+C48 vdd VSUBS 416.01fF
+C49 iref_0 VSUBS 1.88fF
+C50 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# VSUBS 2.60fF
+C51 iref_9 VSUBS -1.13fF
+C52 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# VSUBS 2.60fF
+C53 iref_7 VSUBS -1.38fF
+C54 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# VSUBS 2.60fF
+C55 iref_8 VSUBS -1.19fF
+C56 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# VSUBS 2.60fF
+C57 iref_6 VSUBS -1.00fF
+C58 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# VSUBS 2.60fF
+C59 iref_5 VSUBS 1.40fF
+C60 sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# VSUBS 2.60fF
+.ends
+
+.subckt mimcap_decoup_1x5 VSUBS t b
+Xdecap[0] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[1] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[2] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[3] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[4] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+C0 b VSUBS 68.24fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
+C1 m3_n4309_50# m3_10_n4250# 1.75fF
+C2 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C3 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C4 c1_110_n4150# m3_10_n4250# 81.11fF
+C5 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C6 m3_n4309_n4250# m3_10_n4250# 1.75fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 in out 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_n118_n388# a_n88_n300# 0.11fF
+C1 a_n88_n300# a_30_n300# 0.61fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 cap3_loop_filter_0/in in 0.79fF
+C2 in D0_cap 0.07fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt top_pll_v2 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd pswitch vdd charge_pump_0/w_2544_775#
++ ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd in_ref
++ vco_vctrl Down w_13905_n238# vss D0_vco iref_cp ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
++ out_to_div DO_cap nDown biasp out_to_pad Up nUp
+Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
++ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
++ vss vdd buffer_salida
+Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd vss ring_osc_0/csvco_branch_2/vbp
++ ring_osc_0/csvco_branch_0/inverter_csvco_0/vss D0_vco ring_osc_0/csvco_branch_2/cap_vco_0/t
++ vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
++ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
++ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
++ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 nUp biasp -0.17fF
+C1 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C2 Down biasp 1.24fF
+C3 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C4 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C5 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C6 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
+C7 nDown nswitch 0.76fF
+C8 nUp pswitch 0.85fF
+C9 vdd buffer_salida_0/a_678_n100# 0.24fF
+C10 div_5_Q1 out_by_2 0.42fF
+C11 nswitch vco_vctrl -0.06fF
+C12 out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.09fF
+C13 vdd out_to_buffer 0.07fF
+C14 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C15 div_5_Q1 out_div_by_5 0.01fF
+C16 nDown nUp -0.09fF
+C17 vdd out_by_2 0.97fF
+C18 nDown Down 2.55fF
+C19 out_by_2 div_5_Q0 0.09fF
+C20 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# n_out_by_2 0.01fF
+C21 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C22 vdd out_div_by_5 0.28fF
+C23 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C24 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C25 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
+C26 vco_vctrl nUp 0.02fF
+C27 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
+C28 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_out_by_2 0.12fF
+C29 vdd nDown 0.22fF
+C30 div_5_Q1 vco_vctrl 0.14fF
+C31 div_5_nQ2 out_by_2 0.16fF
+C32 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
+C33 div_5_Q1_shift out_div_by_5 0.05fF
+C34 Up nUp 2.72fF
+C35 div_5_Q1 n_out_by_2 1.04fF
+C36 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
+C37 vdd vco_vctrl -1.02fF
+C38 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
+C39 nDown biasp 0.26fF
+C40 Down iref_cp 0.09fF
+C41 div_5_Q0 vco_vctrl 0.48fF
+C42 vdd n_out_by_2 1.03fF
+C43 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C44 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
+C45 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C46 div_5_Q0 n_out_by_2 -0.12fF
+C47 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
+C48 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C49 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
+C50 vdd Up 0.28fF
+C51 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C52 nDown pswitch 0.53fF
+C53 vdd iref_cp 0.15fF
+C54 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C55 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.33fF
+C56 out_by_2 vco_vctrl 0.53fF
+C57 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C58 Up biasp 0.26fF
+C59 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C60 div_by_5_0/DFlipFlop_2/latch_diff_0/D n_out_by_2 0.12fF
+C61 div_5_nQ2 n_out_by_2 0.10fF
+C62 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
+C63 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C64 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C65 vdd out_to_div 0.21fF
+C66 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C67 Up pswitch 1.98fF
+C68 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C69 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C70 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C71 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C72 out_to_div out_to_buffer 0.13fF
+C73 n_out_by_2 vco_vctrl 0.52fF
+C74 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C75 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
+C76 div_5_nQ0 out_by_2 0.32fF
+C77 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
+C78 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C79 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C80 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C81 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
+C82 Down nswitch 0.54fF
+C83 vdd QA -0.04fF
+C84 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C85 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C86 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C87 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C88 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C89 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
+C90 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
+C91 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C92 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
+C93 vdd D0_vco 0.03fF
+C94 vdd lf_vc 0.02fF
+C95 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C96 div_5_nQ0 n_out_by_2 0.10fF
+C97 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
+C98 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# n_out_by_2 -0.05fF
+C99 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C100 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
+C101 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
+C102 vdd nUp 0.05fF
+C103 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C104 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C105 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C106 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
+C107 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C118 QB vss 4.46fF
+C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss -0.40fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 pfd_reset vss 2.17fF
+C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C132 QA vss 4.31fF
+C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 5.50fF
+C141 Up vss 2.37fF
+C142 Down vss 7.92fF
+C143 nDown vss -2.20fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_5_Q1 vss 4.28fF
+C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C158 div_5_nQ0 vss 0.59fF
+C159 div_5_Q0 vss 0.01fF
+C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_first_buffer vss 2.88fF
+C196 out_to_div vss 4.46fF
+C197 out_to_buffer vss 1.57fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 D0_vco vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 buffer_salida_0/a_3996_n100# vss 48.29fF
+C213 out_to_pad vss 7.50fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C217 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C218 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C219 out_buffer_div_2 vss 1.60fF
+C220 n_out_buffer_div_2 vss 1.63fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 lf_vc vss -59.89fF
+C232 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C233 DO_cap vss 0.01fF
+C234 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C235 nswitch vss 3.73fF
+C236 biasp vss 5.44fF
+C237 iref_cp vss 2.81fF
+C238 vco_vctrl vss -21.20fF
+C239 pswitch vss 3.57fF
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7]
++ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
++ io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
++ io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
++ io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9]
++ io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14]
++ io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1]
++ io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25]
++ io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7]
++ io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
++ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20]
++ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3]
++ io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10]
++ io_out[11] io_out[12] io_out[13] io_out[14] io_out[15] io_out[16] io_out[17] io_out[18]
++ io_out[19] io_out[1] io_out[20] io_out[21] io_out[22] io_out[23] io_out[24] io_out[25]
++ io_out[26] io_out[2] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8]
++ io_out[9] la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103]
++ la_data_in[104] la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108]
++ la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113]
++ la_data_in[114] la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118]
++ la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123]
++ la_data_in[124] la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13]
++ la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19]
++ la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24]
++ la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2]
++ la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35]
++ la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40]
++ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46]
++ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51]
++ la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57]
++ la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62]
++ la_data_in[63] la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68]
++ la_data_in[69] la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73]
++ la_data_in[74] la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79]
++ la_data_in[7] la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84]
++ la_data_in[85] la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8]
++ la_data_in[90] la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95]
++ la_data_in[96] la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0]
++ la_data_out[100] la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104]
++ la_data_out[105] la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109]
++ la_data_out[10] la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113]
++ la_data_out[114] la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118]
++ la_data_out[119] la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122]
++ la_data_out[123] la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127]
++ la_data_out[12] la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16]
++ la_data_out[17] la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21]
++ la_data_out[22] la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26]
++ la_data_out[27] la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31]
++ la_data_out[32] la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36]
++ la_data_out[37] la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41]
++ la_data_out[42] la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46]
++ la_data_out[47] la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51]
++ la_data_out[52] la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56]
++ la_data_out[57] la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61]
++ la_data_out[62] la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66]
++ la_data_out[67] la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71]
++ la_data_out[72] la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76]
++ la_data_out[77] la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81]
++ la_data_out[82] la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86]
++ la_data_out[87] la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91]
++ la_data_out[92] la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96]
++ la_data_out[97] la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100]
++ la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107]
++ la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113]
++ la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11]
++ la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126]
++ la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17]
++ la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23]
++ la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2]
++ la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36]
++ la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42]
++ la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49]
++ la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55]
++ la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61]
++ la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68]
++ la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74]
++ la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80]
++ la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87]
++ la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93]
++ la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9]
++ user_clock2 user_irq[0] user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2
++ vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11]
++ wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17]
++ wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22]
++ wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28]
++ wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4]
++ wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0]
++ wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15]
++ wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20]
++ wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26]
++ wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31]
++ wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9]
++ wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14]
++ wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1]
++ wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25]
++ wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
++ wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
++ wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+Xres_amp_top_0 vssa1 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ vdda1 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# bias_0/iref_8
++ res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out
++ bias_0/iref_6 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1
++ res_amp_top_0/res_amp_lin_prog_0/outn bias_0/iref_7 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363#
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ gpio_noesd[3] bias_0/iref_5 res_amp_top_0/res_amp_lin_prog_0/outp res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB io_analog[2]
++ res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828#
++ io_analog[3] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA gpio_noesd[1]
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out res_amp_top_0/res_amp_lin_prog_0/outp_cap
++ gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/clk res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA io_analog[6]
++ gpio_noesd[5] res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out gpio_noesd[6]
++ res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ gpio_noesd[2] io_analog[0] res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ io_analog[1] io_analog[4] res_amp_top_0/res_amp_sync_v2_0/rst res_amp_top
+Xtop_pll_v1_0 top_pll_v1_0/vco_vctrl vdda1 top_pll_v1_0/pswitch top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ top_pll_v1_0/charge_pump_0/w_2544_775# top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp
++ top_pll_v1_0/biasp io_analog[10] top_pll_v1_0/Down vssa1 vssa1 gpio_noesd[7] top_pll_v1_0/buffer_salida_0/a_3996_n100#
++ top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v1_0/QA top_pll_v1_0/charge_pump_0/w_1008_774#
++ bias_0/iref_2 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd top_pll_v1_0/out_to_div
++ top_pll_v1_0/nDown io_analog[9] top_pll_v1_0/Up top_pll_v1_0/nUp top_pll_v1
+Xtop_pll_v1_1 top_pll_v1_1/vco_vctrl vdda1 top_pll_v1_1/pswitch top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ top_pll_v1_1/charge_pump_0/w_2544_775# top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp
++ top_pll_v1_1/biasp io_analog[10] top_pll_v1_1/Down vssa1 vssa1 gpio_noesd[7] top_pll_v1_1/buffer_salida_0/a_3996_n100#
++ top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v1_1/QA top_pll_v1_1/charge_pump_0/w_1008_774#
++ bias_0/iref_0 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd top_pll_v1_1/out_to_div
++ top_pll_v1_1/nDown io_analog[7] top_pll_v1_1/Up top_pll_v1_1/nUp top_pll_v1
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xbias_0 vssa1 vdda1 bias_0/iref_0 bias_0/iref_1 bias_0/iref_2 bias_0/iref_5 bias_0/iref_6
++ bias_0/iref_7 bias_0/iref_8 bias_0/iref_9 io_analog[5] bias
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xmimcap_decoup_1x5_0[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_0[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_0[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xmimcap_decoup_1x5_2[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_2[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_2[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xtop_pll_v2_0 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v2_0/pswitch
++ vdda1 top_pll_v2_0/charge_pump_0/w_2544_775# top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp
++ top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd io_analog[10] top_pll_v2_0/vco_vctrl
++ top_pll_v2_0/Down vssa1 vssa1 gpio_noesd[7] bias_0/iref_1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
++ top_pll_v2_0/out_to_div gpio_noesd[8] top_pll_v2_0/nDown top_pll_v2_0/biasp io_analog[8]
++ top_pll_v2_0/Up top_pll_v2_0/nUp top_pll_v2
+C0 gpio_noesd[4] gpio_noesd[5] 4.67fF
+C1 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[5] 0.44fF
+C2 bias_0/iref_9 gpio_noesd[4] -0.25fF
+C3 bias_0/iref_8 bias_0/iref_5 10.19fF
+C4 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in gpio_noesd[5] 0.05fF
+C5 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outp -0.31fF
+C6 io_analog[7] bias_0/iref_1 13.22fF
+C7 io_analog[6] io_clamp_high[2] 0.53fF
+C8 vdda1 io_analog[2] 25.90fF
+C9 gpio_noesd[6] gpio_noesd[5] 0.05fF
+C10 io_analog[6] vdda1 124.15fF
+C11 bias_0/iref_9 io_analog[4] 15.97fF
+C12 bias_0/iref_8 io_analog[3] 13.88fF
+C13 gpio_noesd[7] top_pll_v2_0/out_to_div 0.23fF
+C14 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outp 0.61fF
+C15 bias_0/iref_2 io_analog[8] 14.44fF
+C16 gpio_noesd[7] io_analog[10] 29.88fF
+C17 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.07fF
+C18 io_analog[2] bias_0/iref_6 13.88fF
+C19 io_analog[5] m3_226242_702300# 0.53fF
+C20 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_1008_774# 0.21fF
+C21 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.22fF
+C22 io_analog[4] io_clamp_high[0] 0.53fF
+C23 vdda1 top_pll_v1_0/nUp 0.01fF
+C24 vdda1 top_pll_v2_0/pswitch 0.34fF
+C25 io_analog[4] bias_0/iref_8 15.97fF
+C26 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# bias_0/iref_7 0.09fF
+C27 bias_0/iref_9 gpio_noesd[5] 1.30fF
+C28 bias_0/iref_8 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.34fF
+C29 bias_0/iref_1 top_pll_v2_0/nUp 0.22fF
+C30 res_amp_top_0/res_amp_lin_prog_0/outp gpio_noesd[5] 0.44fF
+C31 gpio_noesd[7] top_pll_v2_0/vco_vctrl 0.05fF
+C32 bias_0/iref_1 top_pll_v2_0/charge_pump_0/w_2544_775# 0.09fF
+C33 top_pll_v1_0/vco_vctrl gpio_noesd[7] 0.05fF
+C34 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.04fF
+C35 vdda1 bias_0/iref_6 29.75fF
+C36 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.17fF
+C37 io_analog[2] bias_0/iref_7 13.88fF
+C38 gpio_noesd[7] top_pll_v1_1/vco_vctrl 0.04fF
+C39 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.72fF
+C40 gpio_noesd[7] gpio_noesd[8] 1.88fF
+C41 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl gpio_noesd[5] 0.33fF
+C42 vdda1 top_pll_v2_0/biasp 0.03fF
+C43 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.42fF
+C44 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# 0.18fF
+C45 bias_0/iref_1 top_pll_v2_0/nDown 0.54fF
+C46 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_2544_775# 0.21fF
+C47 vdda1 io_analog[9] 30.05fF
+C48 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.94fF
+C49 top_pll_v1_0/QA io_analog[10] 0.03fF
+C50 bias_0/iref_9 bias_0/iref_8 9.89fF
+C51 bias_0/iref_2 top_pll_v1_0/nDown 0.70fF
+C52 bias_0/iref_0 top_pll_v1_1/Down 1.08fF
+C53 io_analog[6] bias_0/iref_1 13.22fF
+C54 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA gpio_noesd[3] 0.01fF
+C55 vdda1 bias_0/iref_7 33.08fF
+C56 gpio_noesd[7] top_pll_v1_0/out_to_div 0.23fF
+C57 io_analog[2] bias_0/iref_5 13.88fF
+C58 io_analog[6] bias_0/iref_0 6.93fF
+C59 bias_0/iref_2 top_pll_v1_0/Down 1.11fF
+C60 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA gpio_noesd[4] 0.42fF
+C61 io_analog[2] io_analog[3] 0.14fF
+C62 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.17fF
+C63 vdda1 bias_0/iref_1 15.26fF
+C64 bias_0/iref_7 bias_0/iref_6 17.40fF
+C65 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_6 0.15fF
+C66 gpio_noesd[1] vdda1 214.54fF
+C67 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in bias_0/iref_5 0.46fF
+C68 io_analog[10] gpio_noesd[8] 20.65fF
+C69 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_7 0.37fF
+C70 bias_0/iref_2 io_analog[7] 13.22fF
+C71 gpio_noesd[2] vdda1 214.16fF
+C72 vdda1 bias_0/iref_0 15.18fF
+C73 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_8 0.11fF
+C74 gpio_noesd[4] io_analog[2] -0.21fF
+C75 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in 0.23fF
+C76 bias_0/iref_0 top_pll_v1_1/nUp 0.74fF
+C77 vdda1 bias_0/iref_5 30.67fF
+C78 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp 1.01fF
+C79 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA 0.29fF
+C80 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out 0.21fF
+C81 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.17fF
+C82 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outn -1.06fF
+C83 bias_0/iref_0 top_pll_v1_1/Up 0.74fF
+C84 vdda1 io_analog[3] 25.90fF
+C85 io_analog[4] io_analog[6] 0.59fF
+C86 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/clk 0.39fF
+C87 vdda1 gpio_noesd[3] 120.88fF
+C88 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_7 0.45fF
+C89 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/clk 0.37fF
+C90 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outn 0.45fF
+C91 bias_0/iref_5 bias_0/iref_6 29.11fF
+C92 bias_0/iref_1 top_pll_v2_0/biasp 2.20fF
+C93 bias_0/iref_0 top_pll_v1_1/nDown 0.74fF
+C94 vdda1 gpio_noesd[4] 117.64fF
+C95 top_pll_v1_0/biasp bias_0/iref_2 3.20fF
+C96 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp 0.17fF
+C97 vdda1 io_analog[8] 29.93fF
+C98 io_analog[6] io_clamp_low[2] 0.53fF
+C99 io_analog[3] bias_0/iref_6 13.88fF
+C100 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[2] 0.21fF
+C101 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.12fF
+C102 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[4] -0.05fF
+C103 vdda1 gpio_noesd[6] 53.94fF
+C104 io_analog[4] vdda1 182.26fF
+C105 vdda1 top_pll_v1_1/pswitch 0.48fF
+C106 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[3] 0.21fF
+C107 vdda1 gpio_noesd[7] 120.83fF
+C108 bias_0/iref_9 res_amp_top_0/res_amp_sync_v2_0/rst 0.39fF
+C109 bias_0/iref_0 top_pll_v1_1/biasp 3.13fF
+C110 io_analog[2] gpio_noesd[5] 0.09fF
+C111 top_pll_v1_0/charge_pump_0/w_2544_775# bias_0/iref_2 0.02fF
+C112 bias_0/iref_9 io_analog[2] 13.88fF
+C113 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB 0.19fF
+C114 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C115 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_5 0.45fF
+C116 bias_0/iref_7 bias_0/iref_5 10.35fF
+C117 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[4] -0.01fF
+C118 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in -0.70fF
+C119 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[3] 0.03fF
+C120 io_analog[4] io_clamp_low[0] 0.53fF
+C121 res_amp_top_0/res_amp_lin_prog_0/outn gpio_noesd[5] 1.42fF
+C122 io_analog[4] bias_0/iref_6 15.97fF
+C123 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in 0.18fF
+C124 bias_0/iref_5 io_analog[5] 0.09fF
+C125 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b 0.31fF
+C126 io_analog[3] bias_0/iref_7 13.88fF
+C127 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in gpio_noesd[4] 0.12fF
+C128 gpio_noesd[2] gpio_noesd[1] 0.30fF
+C129 io_analog[6] bias_0/iref_2 54.67fF
+C130 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# -0.08fF
+C131 io_analog[5] m3_222594_702300# 0.53fF
+C132 vdda1 io_analog[1] 76.56fF
+C133 vdda1 gpio_noesd[5] 124.75fF
+C134 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp gpio_noesd[5] 0.54fF
+C135 bias_0/iref_9 vdda1 30.24fF
+C136 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp 2.10fF
+C137 io_analog[2] bias_0/iref_8 13.88fF
+C138 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out 0.21fF
+C139 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out 0.38fF
+C140 bias_0/iref_1 top_pll_v2_0/Up 0.54fF
+C141 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b gpio_noesd[1] 0.23fF
+C142 vdda1 io_analog[10] 0.01fF
+C143 vdda1 io_analog[0] 76.77fF
+C144 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.12fF
+C145 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in 0.20fF
+C146 vdda1 top_pll_v1_0/buffer_salida_0/a_3996_n100# 0.06fF
+C147 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[5] 0.26fF
+C148 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out gpio_noesd[3] 0.33fF
+C149 io_analog[4] bias_0/iref_7 15.97fF
+C150 vdda1 bias_0/iref_2 3.90fF
+C151 vdda1 top_pll_v1_0/pswitch 0.38fF
+C152 bias_0/iref_2 top_pll_v1_0/nUp 0.70fF
+C153 io_analog[3] bias_0/iref_5 13.88fF
+C154 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out gpio_noesd[4] 0.19fF
+C155 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.46fF
+C156 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[5] 0.68fF
+C157 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out gpio_noesd[1] 0.57fF
+C158 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.12fF
+C159 vdda1 bias_0/iref_8 31.37fF
+C160 bias_0/iref_1 top_pll_v2_0/Down 0.91fF
+C161 bias_0/iref_2 top_pll_v1_0/Up 0.70fF
+C162 vdda1 top_pll_v2_0/vco_vctrl 0.59fF
+C163 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C164 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[5] 0.14fF
+C165 vdda1 top_pll_v1_0/vco_vctrl 0.43fF
+C166 gpio_noesd[5] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.32fF
+C167 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# gpio_noesd[5] 0.16fF
+C168 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.78fF
+C169 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.01fF
+C170 vdda1 io_analog[7] 29.48fF
+C171 io_analog[4] bias_0/iref_5 15.97fF
+C172 gpio_noesd[4] io_analog[3] -0.78fF
+C173 vdda1 top_pll_v1_1/vco_vctrl 0.54fF
+C174 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_8 0.37fF
+C175 bias_0/iref_5 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.46fF
+C176 vdda1 gpio_noesd[8] 76.96fF
+C177 bias_0/iref_2 io_analog[9] 14.44fF
+C178 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.08fF
+C179 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[4] -0.13fF
+C180 gpio_noesd[7] top_pll_v1_1/out_to_div 0.15fF
+C181 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA 0.49fF
+C182 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[6] 2.12fF
+C183 io_analog[7] top_pll_v1_1/buffer_salida_0/a_3996_n100# -0.08fF
+C184 vdda1 top_pll_v1_0/biasp 0.03fF
+C185 bias_0/iref_8 bias_0/iref_7 13.23fF
+C186 vdda1 top_pll_v2_0/buffer_salida_0/a_3996_n100# 0.05fF
+C187 vdda1 top_pll_v2_0/nUp 0.01fF
+C188 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.04fF
+C189 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_7 0.40fF
+C190 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp 1.14fF
+C191 io_analog[3] gpio_noesd[5] 0.12fF
+C192 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in gpio_noesd[5] 0.47fF
+C193 bias_0/iref_9 io_analog[3] 13.88fF
+C194 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.04fF
+C195 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# -0.11fF
+C196 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB gpio_noesd[5] 0.14fF
+C197 io_in_3v3[0] vssa1 0.41fF
+C198 io_oeb[26] vssa1 0.61fF
+C199 io_in[0] vssa1 0.41fF
+C200 io_out[26] vssa1 0.61fF
+C201 io_out[0] vssa1 0.41fF
+C202 io_in[26] vssa1 0.61fF
+C203 io_oeb[0] vssa1 0.41fF
+C204 io_in_3v3[26] vssa1 0.61fF
+C205 io_in_3v3[1] vssa1 0.41fF
+C206 io_oeb[25] vssa1 0.61fF
+C207 io_in[1] vssa1 0.41fF
+C208 io_out[25] vssa1 0.61fF
+C209 io_out[1] vssa1 0.41fF
+C210 io_in[25] vssa1 0.61fF
+C211 io_oeb[1] vssa1 0.41fF
+C212 io_in_3v3[25] vssa1 0.61fF
+C213 io_in_3v3[2] vssa1 0.41fF
+C214 io_oeb[24] vssa1 0.61fF
+C215 io_in[2] vssa1 0.41fF
+C216 io_out[24] vssa1 0.61fF
+C217 io_out[2] vssa1 0.41fF
+C218 io_in[24] vssa1 0.61fF
+C219 io_oeb[2] vssa1 -0.20fF
+C220 io_in_3v3[3] vssa1 0.41fF
+C221 gpio_noesd[17] vssa1 0.61fF
+C222 io_in[3] vssa1 0.41fF
+C223 gpio_analog[17] vssa1 0.61fF
+C224 io_out[3] vssa1 0.41fF
+C225 io_oeb[3] vssa1 0.41fF
+C226 io_in_3v3[4] vssa1 0.41fF
+C227 io_in[4] vssa1 0.41fF
+C228 io_out[4] vssa1 0.41fF
+C229 io_oeb[4] vssa1 0.41fF
+C230 io_oeb[23] vssa1 0.61fF
+C231 io_out[23] vssa1 0.61fF
+C232 io_in[23] vssa1 0.61fF
+C233 io_in_3v3[23] vssa1 0.61fF
+C234 gpio_noesd[16] vssa1 0.61fF
+C235 io_in_3v3[5] vssa1 0.41fF
+C236 io_in[5] vssa1 -0.20fF
+C237 io_out[5] vssa1 0.41fF
+C238 io_oeb[5] vssa1 0.41fF
+C239 io_oeb[22] vssa1 0.61fF
+C240 io_out[22] vssa1 0.61fF
+C241 io_in[22] vssa1 0.61fF
+C242 io_in_3v3[22] vssa1 0.61fF
+C243 gpio_analog[15] vssa1 0.61fF
+C244 io_in_3v3[6] vssa1 -0.20fF
+C245 io_in[6] vssa1 0.41fF
+C246 io_out[6] vssa1 0.41fF
+C247 io_oeb[6] vssa1 0.41fF
+C248 io_oeb[21] vssa1 0.61fF
+C249 io_out[21] vssa1 0.61fF
+C250 io_in[21] vssa1 0.61fF
+C251 io_in_3v3[21] vssa1 0.61fF
+C252 gpio_noesd[14] vssa1 0.61fF
+C253 gpio_analog[14] vssa1 0.61fF
+C254 vssd2 vssa1 -5.19fF
+C255 vssd1 vssa1 1.13fF
+C256 vdda2 vssa1 -5.19fF
+C257 io_oeb[20] vssa1 0.61fF
+C258 io_out[20] vssa1 0.61fF
+C259 io_in[20] vssa1 0.61fF
+C260 io_in_3v3[20] vssa1 0.61fF
+C261 gpio_noesd[13] vssa1 0.61fF
+C262 gpio_analog[13] vssa1 0.61fF
+C263 gpio_analog[0] vssa1 0.41fF
+C264 gpio_noesd[0] vssa1 0.41fF
+C265 io_in_3v3[7] vssa1 0.41fF
+C266 io_in[7] vssa1 0.41fF
+C267 io_out[7] vssa1 0.41fF
+C268 io_oeb[7] vssa1 0.41fF
+C269 io_oeb[19] vssa1 0.61fF
+C270 io_out[19] vssa1 0.61fF
+C271 io_in[19] vssa1 0.61fF
+C272 io_in_3v3[19] vssa1 0.61fF
+C273 gpio_noesd[12] vssa1 0.61fF
+C274 gpio_analog[12] vssa1 0.61fF
+C275 gpio_analog[1] vssa1 0.41fF
+C276 io_in_3v3[8] vssa1 0.41fF
+C277 io_in[8] vssa1 0.41fF
+C278 io_out[8] vssa1 -0.20fF
+C279 io_oeb[8] vssa1 0.41fF
+C280 gpio_analog[2] vssa1 0.41fF
+C281 io_in_3v3[9] vssa1 0.41fF
+C282 io_in[9] vssa1 0.41fF
+C283 io_out[9] vssa1 0.41fF
+C284 io_oeb[9] vssa1 0.41fF
+C285 gpio_analog[3] vssa1 0.41fF
+C286 io_in_3v3[10] vssa1 0.41fF
+C287 io_in[10] vssa1 0.41fF
+C288 io_out[10] vssa1 0.41fF
+C289 io_oeb[10] vssa1 0.41fF
+C290 gpio_analog[4] vssa1 0.41fF
+C291 io_in_3v3[11] vssa1 0.41fF
+C292 io_in[11] vssa1 0.41fF
+C293 io_out[11] vssa1 0.41fF
+C294 io_oeb[11] vssa1 0.41fF
+C295 gpio_analog[5] vssa1 0.41fF
+C296 io_in_3v3[12] vssa1 0.41fF
+C297 io_in[12] vssa1 0.41fF
+C298 io_out[12] vssa1 0.41fF
+C299 io_oeb[12] vssa1 0.41fF
+C300 gpio_analog[6] vssa1 0.60fF
+C301 io_in_3v3[13] vssa1 0.60fF
+C302 io_in[13] vssa1 0.60fF
+C303 io_out[13] vssa1 0.60fF
+C304 io_oeb[13] vssa1 0.60fF
+C305 io_oeb[18] vssa1 0.61fF
+C306 io_out[18] vssa1 0.61fF
+C307 io_in_3v3[18] vssa1 0.61fF
+C308 gpio_noesd[11] vssa1 0.61fF
+C309 gpio_analog[11] vssa1 0.61fF
+C310 io_oeb[17] vssa1 0.61fF
+C311 io_in[17] vssa1 0.61fF
+C312 io_in_3v3[17] vssa1 0.61fF
+C313 gpio_noesd[10] vssa1 0.61fF
+C314 gpio_analog[10] vssa1 0.61fF
+C315 io_out[16] vssa1 0.61fF
+C316 io_in[16] vssa1 0.61fF
+C317 io_in_3v3[16] vssa1 0.61fF
+C318 gpio_noesd[9] vssa1 0.61fF
+C319 gpio_analog[9] vssa1 0.61fF
+C320 io_oeb[15] vssa1 0.61fF
+C321 io_out[15] vssa1 0.61fF
+C322 io_in[15] vssa1 0.61fF
+C323 io_in_3v3[15] vssa1 0.61fF
+C324 vccd1 vssa1 0.85fF
+C325 gpio_analog[8] vssa1 0.61fF
+C326 io_oeb[14] vssa1 0.61fF
+C327 io_out[14] vssa1 0.61fF
+C328 io_in[14] vssa1 0.61fF
+C329 io_in_3v3[14] vssa1 0.61fF
+C330 vssa2 vssa1 1.66fF
+C331 vccd2 vssa1 0.91fF
+C332 io_clamp_high[0] vssa1 -2.60fF
+C333 io_clamp_low[0] vssa1 0.82fF
+C334 io_clamp_high[2] vssa1 0.66fF
+C335 io_clamp_low[2] vssa1 0.50fF
+C336 user_irq[2] vssa1 0.63fF
+C337 user_irq[1] vssa1 0.63fF
+C338 user_irq[0] vssa1 0.63fF
+C339 user_clock2 vssa1 0.63fF
+C340 la_oenb[127] vssa1 0.63fF
+C341 la_data_in[127] vssa1 0.63fF
+C342 la_oenb[126] vssa1 0.63fF
+C343 la_data_out[126] vssa1 0.63fF
+C344 la_data_in[126] vssa1 0.63fF
+C345 la_oenb[125] vssa1 0.63fF
+C346 la_data_out[125] vssa1 0.63fF
+C347 la_data_in[125] vssa1 0.63fF
+C348 la_oenb[124] vssa1 0.63fF
+C349 la_data_out[124] vssa1 0.63fF
+C350 la_data_in[124] vssa1 0.63fF
+C351 la_oenb[123] vssa1 0.63fF
+C352 la_data_out[123] vssa1 0.63fF
+C353 la_oenb[122] vssa1 0.63fF
+C354 la_data_out[122] vssa1 0.63fF
+C355 la_data_in[122] vssa1 0.63fF
+C356 la_oenb[121] vssa1 0.63fF
+C357 la_data_out[121] vssa1 0.63fF
+C358 la_data_in[121] vssa1 0.63fF
+C359 la_oenb[120] vssa1 0.63fF
+C360 la_data_out[120] vssa1 0.63fF
+C361 la_data_in[120] vssa1 0.63fF
+C362 la_oenb[119] vssa1 0.63fF
+C363 la_data_out[119] vssa1 0.63fF
+C364 la_data_in[119] vssa1 0.63fF
+C365 la_oenb[118] vssa1 0.63fF
+C366 la_data_out[118] vssa1 0.63fF
+C367 la_data_in[118] vssa1 0.63fF
+C368 la_oenb[117] vssa1 0.63fF
+C369 la_data_out[117] vssa1 0.63fF
+C370 la_data_in[117] vssa1 0.63fF
+C371 la_data_out[116] vssa1 0.63fF
+C372 la_data_in[116] vssa1 0.63fF
+C373 la_oenb[115] vssa1 0.63fF
+C374 la_data_out[115] vssa1 0.63fF
+C375 la_data_in[115] vssa1 0.63fF
+C376 la_oenb[114] vssa1 0.63fF
+C377 la_data_out[114] vssa1 0.63fF
+C378 la_data_in[114] vssa1 0.63fF
+C379 la_oenb[113] vssa1 0.63fF
+C380 la_data_out[113] vssa1 0.63fF
+C381 la_data_in[113] vssa1 0.63fF
+C382 la_oenb[112] vssa1 0.63fF
+C383 la_data_in[112] vssa1 0.63fF
+C384 la_oenb[111] vssa1 0.63fF
+C385 la_data_out[111] vssa1 0.63fF
+C386 la_data_in[111] vssa1 0.63fF
+C387 la_oenb[110] vssa1 0.63fF
+C388 la_data_out[110] vssa1 0.63fF
+C389 la_data_in[110] vssa1 0.63fF
+C390 la_oenb[109] vssa1 0.63fF
+C391 la_data_out[109] vssa1 0.63fF
+C392 la_data_in[109] vssa1 0.63fF
+C393 la_oenb[108] vssa1 0.63fF
+C394 la_data_out[108] vssa1 0.63fF
+C395 la_oenb[107] vssa1 0.63fF
+C396 la_data_out[107] vssa1 0.63fF
+C397 la_data_in[107] vssa1 0.63fF
+C398 la_oenb[106] vssa1 0.63fF
+C399 la_data_out[106] vssa1 0.63fF
+C400 la_oenb[105] vssa1 0.63fF
+C401 la_data_out[105] vssa1 0.63fF
+C402 la_data_in[105] vssa1 0.63fF
+C403 la_oenb[104] vssa1 0.63fF
+C404 la_data_out[104] vssa1 0.63fF
+C405 la_data_in[104] vssa1 0.63fF
+C406 la_oenb[103] vssa1 0.63fF
+C407 la_data_out[103] vssa1 0.63fF
+C408 la_data_in[103] vssa1 0.63fF
+C409 la_oenb[102] vssa1 0.63fF
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+C772 wbs_sel_i[3] vssa1 0.63fF
+C773 wbs_dat_o[3] vssa1 0.63fF
+C774 wbs_adr_i[3] vssa1 0.63fF
+C775 wbs_sel_i[2] vssa1 0.63fF
+C776 wbs_dat_o[2] vssa1 0.63fF
+C777 wbs_dat_i[2] vssa1 0.63fF
+C778 wbs_adr_i[2] vssa1 0.63fF
+C779 wbs_dat_o[1] vssa1 0.63fF
+C780 wbs_dat_i[1] vssa1 0.63fF
+C781 wbs_adr_i[1] vssa1 0.63fF
+C782 wbs_sel_i[0] vssa1 0.63fF
+C783 wbs_dat_o[0] vssa1 0.63fF
+C784 wbs_dat_i[0] vssa1 0.63fF
+C785 wbs_adr_i[0] vssa1 0.63fF
+C786 wbs_we_i vssa1 0.63fF
+C787 wbs_stb_i vssa1 0.63fF
+C788 wbs_cyc_i vssa1 0.63fF
+C789 wbs_ack_o vssa1 0.63fF
+C790 wb_rst_i vssa1 0.63fF
+C791 m3_226242_702300# vssa1 -1.31fF
+C792 m3_222594_702300# vssa1 0.55fF
+C793 top_pll_v2_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C794 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C795 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C796 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C797 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C798 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C799 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C800 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C801 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C802 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C803 top_pll_v2_0/QB vssa1 4.35fF
+C804 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C805 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C806 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C807 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C808 top_pll_v2_0/out_div_by_5 vssa1 -0.40fF
+C809 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C810 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C811 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C812 top_pll_v2_0/pfd_reset vssa1 2.17fF
+C813 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C814 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C815 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C816 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C817 top_pll_v2_0/QA vssa1 4.22fF
+C818 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C819 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C820 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C821 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C822 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C823 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C824 top_pll_v2_0/nUp vssa1 5.39fF
+C825 top_pll_v2_0/Up vssa1 1.85fF
+C826 top_pll_v2_0/Down vssa1 6.19fF
+C827 top_pll_v2_0/nDown vssa1 -3.53fF
+C828 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C829 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C830 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C831 top_pll_v2_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C832 top_pll_v2_0/div_5_Q1_shift vssa1 -0.14fF
+C833 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C834 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C835 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C836 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C837 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C838 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C839 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C840 top_pll_v2_0/div_5_Q1 vssa1 4.25fF
+C841 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C842 top_pll_v2_0/div_5_nQ0 vssa1 0.59fF
+C843 top_pll_v2_0/div_5_Q0 vssa1 0.01fF
+C844 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C845 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C846 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C847 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C848 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C849 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C850 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C851 top_pll_v2_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C852 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C853 top_pll_v2_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C854 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C855 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C856 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C857 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C858 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C859 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C860 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C861 top_pll_v2_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C862 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C863 top_pll_v2_0/div_5_nQ2 vssa1 1.24fF
+C864 top_pll_v2_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C865 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C866 top_pll_v2_0/n_out_by_2 vssa1 -2.75fF
+C867 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C868 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C869 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C870 top_pll_v2_0/out_by_2 vssa1 -5.01fF
+C871 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C872 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C873 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C874 top_pll_v2_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C875 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C876 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C877 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C878 top_pll_v2_0/out_first_buffer vssa1 2.88fF
+C879 top_pll_v2_0/out_to_div vssa1 4.23fF
+C880 top_pll_v2_0/out_to_buffer vssa1 1.54fF
+C881 top_pll_v2_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C882 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C883 top_pll_v2_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C884 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C885 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C886 top_pll_v2_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C887 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C888 top_pll_v2_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C889 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C890 top_pll_v2_0/vco_out vssa1 1.01fF
+C891 top_pll_v2_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C892 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C893 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C894 top_pll_v2_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C895 io_analog[8] vssa1 13.78fF
+C896 top_pll_v2_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C897 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C898 top_pll_v2_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C899 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C900 top_pll_v2_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C901 top_pll_v2_0/out_buffer_div_2 vssa1 1.60fF
+C902 top_pll_v2_0/n_out_buffer_div_2 vssa1 1.63fF
+C903 top_pll_v2_0/out_div_2 vssa1 -1.30fF
+C904 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C905 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C906 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C907 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C908 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C909 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C910 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C911 top_pll_v2_0/n_out_div_2 vssa1 1.95fF
+C912 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C913 top_pll_v2_0/lf_vc vssa1 -59.89fF
+C914 top_pll_v2_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
+C915 gpio_noesd[8] vssa1 210.79fF
+C916 top_pll_v2_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
+C917 top_pll_v2_0/nswitch vssa1 3.73fF
+C918 top_pll_v2_0/biasp vssa1 5.44fF
+C919 bias_0/iref_1 vssa1 -91.53fF
+C920 top_pll_v2_0/vco_vctrl vssa1 -20.08fF
+C921 top_pll_v2_0/pswitch vssa1 3.57fF
+C922 io_analog[5] vssa1 33.29fF
+C923 bias_0/iref_4 vssa1 1.17fF
+C924 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vssa1 2.60fF
+C925 bias_0/iref_3 vssa1 0.64fF
+C926 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vssa1 2.60fF
+C927 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vssa1 2.60fF
+C928 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vssa1 2.60fF
+C929 bias_0/m1_20168_984# vssa1 56.92fF
+C930 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vssa1 2.60fF
+C931 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vssa1 2.60fF
+C932 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vssa1 2.60fF
+C933 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vssa1 2.60fF
+C934 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vssa1 2.60fF
+C935 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vssa1 2.60fF
+C936 top_pll_v1_1/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C937 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C938 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C939 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C940 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C941 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C942 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C943 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C944 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C945 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C946 top_pll_v1_1/QB vssa1 4.35fF
+C947 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C948 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C949 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C950 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C951 top_pll_v1_1/out_div_by_5 vssa1 -0.40fF
+C952 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C953 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C954 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C955 top_pll_v1_1/pfd_reset vssa1 2.17fF
+C956 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C957 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C958 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C959 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C960 top_pll_v1_1/QA vssa1 4.22fF
+C961 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C962 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C963 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C964 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C965 io_analog[10] vssa1 503.33fF
+C966 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C967 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C968 top_pll_v1_1/nUp vssa1 5.39fF
+C969 top_pll_v1_1/Up vssa1 1.85fF
+C970 top_pll_v1_1/Down vssa1 6.19fF
+C971 top_pll_v1_1/nDown vssa1 -3.53fF
+C972 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C973 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C974 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C975 top_pll_v1_1/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C976 top_pll_v1_1/div_5_Q1_shift vssa1 -0.14fF
+C977 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C978 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C979 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C980 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C981 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C982 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C983 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C984 top_pll_v1_1/div_5_Q1 vssa1 4.25fF
+C985 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C986 top_pll_v1_1/div_5_nQ0 vssa1 0.59fF
+C987 top_pll_v1_1/div_5_Q0 vssa1 0.01fF
+C988 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C989 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C990 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C991 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C992 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C993 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C994 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C995 top_pll_v1_1/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C996 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C997 top_pll_v1_1/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C998 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C999 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1000 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1001 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1002 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1003 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1004 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1005 top_pll_v1_1/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1006 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1007 top_pll_v1_1/div_5_nQ2 vssa1 1.24fF
+C1008 top_pll_v1_1/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1009 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1010 top_pll_v1_1/n_out_by_2 vssa1 -2.75fF
+C1011 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1012 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1013 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1014 top_pll_v1_1/out_by_2 vssa1 -5.01fF
+C1015 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1016 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1017 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1018 top_pll_v1_1/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1019 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1020 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1021 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1022 top_pll_v1_1/out_first_buffer vssa1 2.88fF
+C1023 top_pll_v1_1/out_to_div vssa1 4.23fF
+C1024 top_pll_v1_1/out_to_buffer vssa1 1.54fF
+C1025 top_pll_v1_1/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1026 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1027 top_pll_v1_1/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1028 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1029 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1030 top_pll_v1_1/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1031 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1032 top_pll_v1_1/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1033 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1034 top_pll_v1_1/vco_out vssa1 1.01fF
+C1035 top_pll_v1_1/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1036 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1037 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1038 top_pll_v1_1/buffer_salida_0/a_3996_n100# vssa1 48.11fF
+C1039 io_analog[7] vssa1 24.61fF
+C1040 top_pll_v1_1/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1041 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1042 top_pll_v1_1/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1043 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1044 top_pll_v1_1/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1045 top_pll_v1_1/out_buffer_div_2 vssa1 1.60fF
+C1046 top_pll_v1_1/n_out_buffer_div_2 vssa1 1.63fF
+C1047 top_pll_v1_1/out_div_2 vssa1 -1.30fF
+C1048 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1049 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1050 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1051 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1052 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1053 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1054 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1055 top_pll_v1_1/n_out_div_2 vssa1 1.95fF
+C1056 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1057 top_pll_v1_1/nswitch vssa1 3.73fF
+C1058 top_pll_v1_1/biasp vssa1 5.44fF
+C1059 bias_0/iref_0 vssa1 -81.35fF
+C1060 top_pll_v1_1/vco_vctrl vssa1 -18.17fF
+C1061 top_pll_v1_1/pswitch vssa1 3.57fF
+C1062 top_pll_v1_1/lf_vc vssa1 -59.89fF
+C1063 top_pll_v1_1/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C1064 top_pll_v1_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C1065 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C1066 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C1067 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1068 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C1069 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1070 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1071 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1072 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C1073 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1074 top_pll_v1_0/QB vssa1 4.35fF
+C1075 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1076 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C1077 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1078 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1079 top_pll_v1_0/out_div_by_5 vssa1 -0.40fF
+C1080 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1081 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C1082 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1083 top_pll_v1_0/pfd_reset vssa1 2.17fF
+C1084 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1085 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1086 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C1087 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1088 top_pll_v1_0/QA vssa1 4.22fF
+C1089 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1090 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C1091 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1092 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1093 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C1094 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C1095 top_pll_v1_0/nUp vssa1 5.39fF
+C1096 top_pll_v1_0/Up vssa1 1.85fF
+C1097 top_pll_v1_0/Down vssa1 6.19fF
+C1098 top_pll_v1_0/nDown vssa1 -3.53fF
+C1099 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C1100 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C1101 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C1102 top_pll_v1_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1103 top_pll_v1_0/div_5_Q1_shift vssa1 -0.14fF
+C1104 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1105 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1106 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1107 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1108 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1109 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1110 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1111 top_pll_v1_0/div_5_Q1 vssa1 4.25fF
+C1112 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1113 top_pll_v1_0/div_5_nQ0 vssa1 0.59fF
+C1114 top_pll_v1_0/div_5_Q0 vssa1 0.01fF
+C1115 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1116 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1117 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1118 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1119 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1120 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1121 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1122 top_pll_v1_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C1123 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1124 top_pll_v1_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1125 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1126 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1127 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1128 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1129 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1130 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1131 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1132 top_pll_v1_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1133 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1134 top_pll_v1_0/div_5_nQ2 vssa1 1.24fF
+C1135 top_pll_v1_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1136 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1137 top_pll_v1_0/n_out_by_2 vssa1 -2.75fF
+C1138 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1139 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1140 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1141 top_pll_v1_0/out_by_2 vssa1 -5.01fF
+C1142 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1143 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1144 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1145 top_pll_v1_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1146 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1147 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1148 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1149 top_pll_v1_0/out_first_buffer vssa1 2.88fF
+C1150 top_pll_v1_0/out_to_div vssa1 4.23fF
+C1151 top_pll_v1_0/out_to_buffer vssa1 1.54fF
+C1152 top_pll_v1_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1153 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1154 top_pll_v1_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1155 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1156 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1157 top_pll_v1_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1158 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1159 top_pll_v1_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1160 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1161 top_pll_v1_0/vco_out vssa1 1.01fF
+C1162 gpio_noesd[7] vssa1 272.21fF
+C1163 top_pll_v1_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1164 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1165 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1166 top_pll_v1_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C1167 io_analog[9] vssa1 7.89fF
+C1168 top_pll_v1_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1169 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1170 top_pll_v1_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1171 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1172 top_pll_v1_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1173 top_pll_v1_0/out_buffer_div_2 vssa1 1.60fF
+C1174 top_pll_v1_0/n_out_buffer_div_2 vssa1 1.63fF
+C1175 top_pll_v1_0/out_div_2 vssa1 -1.30fF
+C1176 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1177 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1178 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1179 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1180 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1181 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1182 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1183 top_pll_v1_0/n_out_div_2 vssa1 1.95fF
+C1184 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1185 top_pll_v1_0/nswitch vssa1 3.73fF
+C1186 top_pll_v1_0/biasp vssa1 5.44fF
+C1187 bias_0/iref_2 vssa1 -178.91fF
+C1188 top_pll_v1_0/vco_vctrl vssa1 -18.17fF
+C1189 top_pll_v1_0/pswitch vssa1 3.57fF
+C1190 top_pll_v1_0/lf_vc vssa1 -59.89fF
+C1191 top_pll_v1_0/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C1192 bias_0/iref_6 vssa1 -645.65fF
+C1193 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in vssa1 -32.98fF
+C1194 io_analog[1] vssa1 74.58fF
+C1195 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# vssa1 1.29fF
+C1196 bias_0/iref_5 vssa1 -623.45fF
+C1197 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in vssa1 -32.98fF
+C1198 io_analog[0] vssa1 -154.61fF
+C1199 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# vssa1 1.29fF
+C1200 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# vssa1 -35.44fF
+C1201 bias_0/iref_8 vssa1 -189.06fF
+C1202 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# vssa1 -35.44fF
+C1203 bias_0/iref_7 vssa1 -205.18fF
+C1204 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# vssa1 -1.87fF
+C1205 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# vssa1 0.47fF
+C1206 gpio_noesd[5] vssa1 122.09fF
+C1207 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# vssa1 -1.10fF
+C1208 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl vssa1 -2.03fF
+C1209 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# vssa1 -2.23fF
+C1210 gpio_noesd[6] vssa1 325.91fF
+C1211 gpio_noesd[4] vssa1 116.78fF
+C1212 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# vssa1 -1.03fF
+C1213 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# vssa1 0.51fF
+C1214 bias_0/iref_9 vssa1 -181.57fF
+C1215 res_amp_top_0/res_amp_lin_prog_0/outn vssa1 1.55fF
+C1216 io_analog[3] vssa1 -119.52fF
+C1217 res_amp_top_0/res_amp_lin_prog_0/outp vssa1 -4.89fF
+C1218 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp vssa1 -4.89fF
+C1219 io_analog[2] vssa1 -131.04fF
+C1220 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# vssa1 -0.95fF
+C1221 res_amp_top_0/res_amp_lin_prog_0/outn_cap vssa1 -0.01fF
+C1222 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk vssa1 4.27fF
+C1223 res_amp_top_0/res_amp_lin_prog_0/inverter_min_x4_0/out vssa1 4.60fF
+C1224 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in vssa1 1.07fF
+C1225 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in vssa1 1.03fF
+C1226 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in vssa1 1.03fF
+C1227 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in vssa1 1.07fF
+C1228 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in vssa1 1.03fF
+C1229 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in vssa1 1.03fF
+C1230 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in vssa1 1.07fF
+C1231 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in vssa1 1.03fF
+C1232 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in vssa1 1.07fF
+C1233 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in vssa1 1.03fF
+C1234 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in vssa1 1.03fF
+C1235 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in vssa1 1.03fF
+C1236 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in vssa1 1.07fF
+C1237 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB vssa1 -7.88fF
+C1238 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in vssa1 1.03fF
+C1239 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in vssa1 1.03fF
+C1240 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in vssa1 1.07fF
+C1241 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in vssa1 1.03fF
+C1242 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1243 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in vssa1 1.03fF
+C1244 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b vssa1 2.03fF
+C1245 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 vssa1 1.54fF
+C1246 gpio_noesd[3] vssa1 213.06fF
+C1247 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b vssa1 2.03fF
+C1248 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out vssa1 -1.67fF
+C1249 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA vssa1 -2.58fF
+C1250 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b vssa1 2.03fF
+C1251 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out vssa1 -2.25fF
+C1252 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA vssa1 -0.04fF
+C1253 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b vssa1 2.03fF
+C1254 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out vssa1 -2.69fF
+C1255 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB vssa1 -4.96fF
+C1256 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b vssa1 2.03fF
+C1257 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out vssa1 -4.71fF
+C1258 gpio_noesd[2] vssa1 216.13fF
+C1259 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA vssa1 0.63fF
+C1260 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b vssa1 2.03fF
+C1261 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out vssa1 -2.49fF
+C1262 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB vssa1 -3.92fF
+C1263 gpio_noesd[1] vssa1 230.09fF
+C1264 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b vssa1 2.03fF
+C1265 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out vssa1 -0.27fF
+C1266 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB vssa1 -0.97fF
+C1267 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in vssa1 1.07fF
+C1268 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in vssa1 1.03fF
+C1269 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in vssa1 1.03fF
+C1270 res_amp_top_0/res_amp_lin_prog_0/outp_cap vssa1 -7.66fF
+C1271 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/m1_21_n341# vssa1 0.72fF
+C1272 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1273 res_amp_top_0/res_amp_lin_prog_0/clk vssa1 -8.26fF
+C1274 res_amp_top_0/res_amp_sync_v2_0/inverter_min_x4_4/out vssa1 5.85fF
+C1275 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/out vssa1 1.70fF
+C1276 res_amp_top_0/res_amp_sync_v2_0/rst vssa1 -7.88fF
+C1277 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/nQ vssa1 0.48fF
+C1278 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/Q vssa1 -2.08fF
+C1279 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1280 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD vssa1 0.57fF
+C1281 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D vssa1 -1.73fF
+C1282 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1283 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1284 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D vssa1 0.96fF
+C1285 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1286 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/D vssa1 1.83fF
+C1287 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD vssa1 1.14fF
+C1288 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/out vssa1 1.20fF
+C1289 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/Q vssa1 -4.73fF
+C1290 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1291 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/Q vssa1 -2.94fF
+C1292 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1293 io_analog[4] vssa1 -253.69fF
+C1294 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1295 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1296 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1297 io_analog[6] vssa1 -26.69fF
+C1298 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1299 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1300 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1301 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/D vssa1 0.79fF
+C1302 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1303 vdda1 vssa1 7275.97fF
+C1304 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1305 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/Q vssa1 -1.08fF
+C1306 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1307 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1308 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1309 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1310 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1311 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1312 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1313 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/D vssa1 -0.38fF
+C1314 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1315 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/nQ vssa1 0.48fF
+C1316 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1317 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1318 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1319 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1320 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1321 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1322 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1323 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/D vssa1 -1.04fF
+C1324 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1325 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/nQ vssa1 0.48fF
+C1326 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1327 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1328 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1329 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1330 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1331 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1332 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1333 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+.ends
+
diff --git a/mag/extractions/user_analog_project_wrapper_pex_rc.spice b/mag/extractions/user_analog_project_wrapper_pex_rc.spice
new file mode 100644
index 0000000..73f3f79
--- /dev/null
+++ b/mag/extractions/user_analog_project_wrapper_pex_rc.spice
@@ -0,0 +1,8669 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_111_n125# 0.13fF
+C1 a_81_n156# a_n15_n156# 0.02fF
+C2 w_n311_n344# a_15_n125# 0.09fF
+C3 a_15_n125# a_n173_n125# 0.13fF
+C4 a_n81_n125# a_15_n125# 0.36fF
+C5 w_n311_n344# a_n173_n125# 0.14fF
+C6 a_111_n125# a_15_n125# 0.36fF
+C7 a_n81_n125# w_n311_n344# 0.09fF
+C8 a_111_n125# w_n311_n344# 0.14fF
+C9 a_n15_n156# a_n111_n156# 0.02fF
+C10 a_n81_n125# a_n173_n125# 0.36fF
+C11 a_111_n125# a_n173_n125# 0.08fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n111_n151# a_n15_n151# 0.02fF
+C2 a_n81_n125# a_n173_n125# 0.36fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n15_n151# a_81_n151# 0.02fF
+C5 a_n81_n125# a_15_n125# 0.36fF
+C6 a_n81_n125# a_111_n125# 0.13fF
+C7 a_n173_n125# a_15_n125# 0.13fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_45_n513# vdd 0.69fF
+C1 m1_187_n605# vdd 0.55fF
+C2 m1_187_n605# m1_45_n513# 0.36fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_15_n125# 0.36fF
+C1 a_n173_n125# a_n81_n125# 0.36fF
+C2 a_n81_n125# w_n311_n344# 0.09fF
+C3 a_15_n125# a_111_n125# 0.36fF
+C4 a_n173_n125# a_111_n125# 0.08fF
+C5 w_n311_n344# a_111_n125# 0.14fF
+C6 a_n81_n125# a_111_n125# 0.13fF
+C7 a_n173_n125# a_15_n125# 0.13fF
+C8 w_n311_n344# a_15_n125# 0.09fF
+C9 a_n173_n125# w_n311_n344# 0.14fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_n173_n125# 0.36fF
+C1 a_n173_n125# a_111_n125# 0.08fF
+C2 a_n81_n125# a_15_n125# 0.36fF
+C3 a_15_n125# a_111_n125# 0.36fF
+C4 a_15_n125# a_n173_n125# 0.13fF
+C5 a_n81_n125# a_111_n125# 0.13fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 out vdd 0.10fF
+C1 out in 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+C0 nCLK_d vdd 0.03fF
+C1 inverter_cp_x1_2/in vdd 0.21fF
+C2 CLK_d vdd 0.03fF
+C3 inverter_cp_x1_0/out CLK 0.31fF
+C4 CLK_d inverter_cp_x1_2/in 0.12fF
+C5 inverter_cp_x1_0/out nCLK_d 0.11fF
+C6 inverter_cp_x1_0/out vdd 0.28fF
+C7 CLK vdd 0.36fF
+C8 inverter_cp_x1_2/in CLK 0.31fF
+C9 inverter_cp_x1_2/in vss 2.01fF
+C10 CLK_d vss 0.96fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_n33_n95# 0.08fF
+C1 a_63_n95# a_n33_n95# 0.28fF
+C2 w_n263_n314# a_63_n95# 0.11fF
+C3 a_n125_n95# a_n33_n95# 0.28fF
+C4 a_n125_n95# w_n263_n314# 0.11fF
+C5 a_n125_n95# a_63_n95# 0.10fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n81_n125# 0.36fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 a_15_n125# a_n129_n213# 0.10fF
+C3 a_n81_n125# a_n173_n125# 0.36fF
+C4 a_111_n125# a_n173_n125# 0.08fF
+C5 a_n129_n213# a_n173_n125# 0.02fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_n129_n213# a_n81_n125# 0.10fF
+C8 a_111_n125# a_n129_n213# 0.01fF
+C9 a_15_n125# a_n173_n125# 0.13fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n33_n95# 0.88fF
+C1 a_n125_n95# a_n81_n183# 0.16fF
+C2 a_n33_n95# a_n81_n183# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 m1_657_280# Q 0.94fF
+C1 m1_657_280# nQ 1.41fF
+C2 Q nD 0.05fF
+C3 nD nQ 0.05fF
+C4 Q nQ 0.93fF
+C5 m1_657_280# CLK 0.24fF
+C6 Q D 0.05fF
+C7 nQ D 0.05fF
+C8 Q vdd 0.16fF
+C9 vdd nQ 0.16fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss vdd latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ latch_diff_0/nD Q latch_diff_1/nD latch_diff_1/m1_657_280# D latch_diff_0/D CLK
++ clock_inverter_0/inverter_cp_x1_0/out nCLK
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C1 latch_diff_1/D latch_diff_1/nD 0.33fF
+C2 vdd latch_diff_0/D 0.09fF
+C3 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C4 vdd latch_diff_1/D 0.03fF
+C5 latch_diff_0/nD vdd 0.14fF
+C6 latch_diff_0/D latch_diff_1/D 0.11fF
+C7 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C8 nQ latch_diff_1/nD 0.08fF
+C9 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C10 latch_diff_0/nD latch_diff_1/D 0.41fF
+C11 Q latch_diff_1/nD 0.01fF
+C12 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C13 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C14 nQ latch_diff_1/D 0.11fF
+C15 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C16 vdd latch_diff_1/nD 0.02fF
+C17 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C18 latch_diff_0/D latch_diff_1/nD 0.04fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C28 latch_diff_0/D vss 1.29fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n221_n84# w_n359_n303# 0.08fF
+C1 a_63_n84# w_n359_n303# 0.06fF
+C2 w_n359_n303# a_n33_n84# 0.05fF
+C3 a_n129_n84# w_n359_n303# 0.06fF
+C4 a_n221_n84# a_63_n84# 0.05fF
+C5 a_n221_n84# a_n33_n84# 0.09fF
+C6 a_n129_n84# a_n221_n84# 0.24fF
+C7 a_63_n84# a_n33_n84# 0.24fF
+C8 a_159_n84# w_n359_n303# 0.08fF
+C9 a_n129_n84# a_63_n84# 0.09fF
+C10 a_n159_n110# a_n63_n110# 0.02fF
+C11 a_n129_n84# a_n33_n84# 0.24fF
+C12 a_159_n84# a_n221_n84# 0.04fF
+C13 a_159_n84# a_63_n84# 0.24fF
+C14 a_159_n84# a_n33_n84# 0.09fF
+C15 a_n129_n84# a_159_n84# 0.05fF
+C16 a_33_n110# a_n63_n110# 0.02fF
+C17 a_33_n110# a_129_n110# 0.02fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n42# a_n129_n42# 0.12fF
+C1 a_n159_n68# a_n63_n68# 0.02fF
+C2 a_n33_n42# a_n221_n42# 0.05fF
+C3 a_63_n42# a_n33_n42# 0.12fF
+C4 a_159_n42# a_n33_n42# 0.05fF
+C5 a_n129_n42# a_n221_n42# 0.12fF
+C6 a_63_n42# a_n129_n42# 0.05fF
+C7 a_159_n42# a_n129_n42# 0.03fF
+C8 a_63_n42# a_n221_n42# 0.03fF
+C9 a_159_n42# a_n221_n42# 0.02fF
+C10 a_63_n42# a_159_n42# 0.12fF
+C11 a_129_n68# a_33_n68# 0.02fF
+C12 a_33_n68# a_n63_n68# 0.02fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 vdd in vss out
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 in out 0.67fF
+C1 out vdd 0.62fF
+C2 in vdd 0.33fF
+C3 in vss 1.89fF
+C4 out vss 0.66fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BDRUME VSUBS a_351_n84# a_n513_n84# a_639_n84# a_159_n84#
++ a_n321_n84# a_447_n84# a_n753_n181# a_n609_n84# w_n935_n303# a_n129_n84# a_735_n84#
++ a_255_n84# a_n417_n84# a_63_n84# a_543_n84# a_n705_n84# a_n225_n84# a_n797_n84#
++ a_n33_n84#
+X0 a_n705_n84# a_n753_n181# a_n797_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n513_n84# a_n753_n181# a_n609_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n417_n84# a_n753_n181# a_n513_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_n321_n84# a_n753_n181# a_n417_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X4 a_n225_n84# a_n753_n181# a_n321_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 a_n129_n84# a_n753_n181# a_n225_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X6 a_n609_n84# a_n753_n181# a_n705_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_63_n84# a_n753_n181# a_n33_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X8 a_n33_n84# a_n753_n181# a_n129_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X9 a_159_n84# a_n753_n181# a_63_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X10 a_255_n84# a_n753_n181# a_159_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X11 a_351_n84# a_n753_n181# a_255_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X12 a_543_n84# a_n753_n181# a_447_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X13 a_447_n84# a_n753_n181# a_351_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X14 a_639_n84# a_n753_n181# a_543_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X15 a_735_n84# a_n753_n181# a_639_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_543_n84# a_639_n84# 0.24fF
+C1 a_n417_n84# a_n321_n84# 0.24fF
+C2 a_447_n84# a_639_n84# 0.09fF
+C3 a_n129_n84# a_n417_n84# 0.05fF
+C4 a_n129_n84# a_159_n84# 0.05fF
+C5 a_n33_n84# a_n225_n84# 0.09fF
+C6 a_159_n84# a_63_n84# 0.24fF
+C7 w_n935_n303# a_n797_n84# 0.08fF
+C8 a_255_n84# a_159_n84# 0.24fF
+C9 a_735_n84# w_n935_n303# 0.08fF
+C10 a_351_n84# a_735_n84# 0.04fF
+C11 a_n513_n84# a_n705_n84# 0.09fF
+C12 a_n417_n84# a_n225_n84# 0.09fF
+C13 a_159_n84# a_n225_n84# 0.04fF
+C14 a_351_n84# a_63_n84# 0.05fF
+C15 a_n609_n84# a_n705_n84# 0.24fF
+C16 a_n513_n84# a_n417_n84# 0.24fF
+C17 a_255_n84# a_351_n84# 0.24fF
+C18 a_n129_n84# a_n321_n84# 0.09fF
+C19 a_n609_n84# a_n417_n84# 0.09fF
+C20 a_n321_n84# a_63_n84# 0.04fF
+C21 a_543_n84# a_159_n84# 0.04fF
+C22 a_n129_n84# a_63_n84# 0.09fF
+C23 a_447_n84# a_159_n84# 0.05fF
+C24 a_n129_n84# a_255_n84# 0.04fF
+C25 a_n513_n84# w_n935_n303# 0.02fF
+C26 a_255_n84# a_63_n84# 0.09fF
+C27 a_n513_n84# a_n797_n84# 0.05fF
+C28 a_n609_n84# w_n935_n303# 0.03fF
+C29 a_n609_n84# a_n797_n84# 0.09fF
+C30 a_n321_n84# a_n225_n84# 0.24fF
+C31 a_543_n84# w_n935_n303# 0.03fF
+C32 a_351_n84# a_543_n84# 0.09fF
+C33 a_n129_n84# a_n225_n84# 0.24fF
+C34 a_n513_n84# a_n321_n84# 0.09fF
+C35 a_447_n84# w_n935_n303# 0.02fF
+C36 a_447_n84# a_351_n84# 0.24fF
+C37 a_n129_n84# a_n513_n84# 0.04fF
+C38 a_735_n84# a_543_n84# 0.09fF
+C39 a_n225_n84# a_63_n84# 0.05fF
+C40 a_n609_n84# a_n321_n84# 0.05fF
+C41 a_447_n84# a_735_n84# 0.05fF
+C42 a_639_n84# w_n935_n303# 0.04fF
+C43 a_351_n84# a_639_n84# 0.05fF
+C44 a_735_n84# a_639_n84# 0.24fF
+C45 a_n33_n84# a_n417_n84# 0.04fF
+C46 a_n33_n84# a_159_n84# 0.09fF
+C47 a_255_n84# a_543_n84# 0.05fF
+C48 a_447_n84# a_63_n84# 0.04fF
+C49 a_447_n84# a_255_n84# 0.09fF
+C50 a_n513_n84# a_n225_n84# 0.05fF
+C51 a_n417_n84# a_n705_n84# 0.05fF
+C52 a_n609_n84# a_n225_n84# 0.04fF
+C53 a_255_n84# a_639_n84# 0.04fF
+C54 a_n513_n84# a_n609_n84# 0.24fF
+C55 a_n33_n84# a_351_n84# 0.04fF
+C56 w_n935_n303# a_n705_n84# 0.04fF
+C57 a_n33_n84# a_n321_n84# 0.05fF
+C58 a_n797_n84# a_n705_n84# 0.24fF
+C59 a_n129_n84# a_n33_n84# 0.24fF
+C60 a_447_n84# a_543_n84# 0.24fF
+C61 a_351_n84# a_159_n84# 0.09fF
+C62 a_n417_n84# a_n797_n84# 0.04fF
+C63 a_n33_n84# a_63_n84# 0.24fF
+C64 a_n33_n84# a_255_n84# 0.05fF
+C65 a_n321_n84# a_n705_n84# 0.04fF
+C66 a_735_n84# VSUBS 0.03fF
+C67 a_639_n84# VSUBS 0.03fF
+C68 a_543_n84# VSUBS 0.03fF
+C69 a_447_n84# VSUBS 0.03fF
+C70 a_351_n84# VSUBS 0.03fF
+C71 a_255_n84# VSUBS 0.03fF
+C72 a_159_n84# VSUBS 0.03fF
+C73 a_63_n84# VSUBS 0.03fF
+C74 a_n33_n84# VSUBS 0.03fF
+C75 a_n129_n84# VSUBS 0.03fF
+C76 a_n225_n84# VSUBS 0.03fF
+C77 a_n321_n84# VSUBS 0.03fF
+C78 a_n417_n84# VSUBS 0.03fF
+C79 a_n513_n84# VSUBS 0.03fF
+C80 a_n609_n84# VSUBS 0.03fF
+C81 a_n705_n84# VSUBS 0.03fF
+C82 a_n797_n84# VSUBS 0.03fF
+C83 a_n753_n181# VSUBS 2.56fF
+C84 w_n935_n303# VSUBS 4.96fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_QQE8KM a_543_n42# a_n705_n42# a_n225_n42# a_n797_n42#
++ a_n33_n42# a_351_n42# a_n513_n42# a_639_n42# a_159_n42# w_n935_n252# a_n757_64#
++ a_n321_n42# a_447_n42# a_n609_n42# a_n129_n42# a_735_n42# a_255_n42# a_n417_n42#
++ a_63_n42#
+X0 a_63_n42# a_n757_64# a_n33_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n757_64# a_n129_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_351_n42# a_n757_64# a_255_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_159_n42# a_n757_64# a_63_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X4 a_255_n42# a_n757_64# a_159_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 a_447_n42# a_n757_64# a_351_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X6 a_543_n42# a_n757_64# a_447_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X7 a_735_n42# a_n757_64# a_639_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X8 a_639_n42# a_n757_64# a_543_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X9 a_n321_n42# a_n757_64# a_n417_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_n705_n42# a_n757_64# a_n797_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 a_n513_n42# a_n757_64# a_n609_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X12 a_n417_n42# a_n757_64# a_n513_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X13 a_n225_n42# a_n757_64# a_n321_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 a_n129_n42# a_n757_64# a_n225_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X15 a_n609_n42# a_n757_64# a_n705_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_159_n42# a_543_n42# 0.02fF
+C1 a_n705_n42# a_n417_n42# 0.03fF
+C2 a_n129_n42# a_n321_n42# 0.05fF
+C3 a_n797_n42# a_n513_n42# 0.03fF
+C4 a_n321_n42# a_63_n42# 0.02fF
+C5 a_639_n42# a_543_n42# 0.12fF
+C6 a_n321_n42# a_n225_n42# 0.12fF
+C7 a_735_n42# a_351_n42# 0.02fF
+C8 a_n321_n42# a_n417_n42# 0.12fF
+C9 a_n705_n42# a_n513_n42# 0.05fF
+C10 a_n797_n42# a_n705_n42# 0.12fF
+C11 a_447_n42# a_159_n42# 0.03fF
+C12 a_255_n42# a_543_n42# 0.03fF
+C13 a_447_n42# a_639_n42# 0.05fF
+C14 a_n321_n42# a_n513_n42# 0.05fF
+C15 a_159_n42# a_n33_n42# 0.05fF
+C16 a_351_n42# a_543_n42# 0.05fF
+C17 a_447_n42# a_63_n42# 0.02fF
+C18 a_n225_n42# a_n609_n42# 0.02fF
+C19 a_n129_n42# a_n33_n42# 0.12fF
+C20 a_n129_n42# a_159_n42# 0.03fF
+C21 a_n417_n42# a_n609_n42# 0.05fF
+C22 a_n33_n42# a_63_n42# 0.12fF
+C23 a_159_n42# a_63_n42# 0.12fF
+C24 a_n321_n42# a_n705_n42# 0.02fF
+C25 a_n225_n42# a_n33_n42# 0.05fF
+C26 a_159_n42# a_n225_n42# 0.02fF
+C27 a_735_n42# a_543_n42# 0.05fF
+C28 a_255_n42# a_447_n42# 0.05fF
+C29 a_n417_n42# a_n33_n42# 0.02fF
+C30 a_n129_n42# a_63_n42# 0.05fF
+C31 a_n129_n42# a_n225_n42# 0.12fF
+C32 a_447_n42# a_351_n42# 0.12fF
+C33 a_n225_n42# a_63_n42# 0.03fF
+C34 a_n513_n42# a_n609_n42# 0.12fF
+C35 a_n797_n42# a_n609_n42# 0.05fF
+C36 a_n129_n42# a_n417_n42# 0.03fF
+C37 a_255_n42# a_n33_n42# 0.03fF
+C38 a_255_n42# a_159_n42# 0.12fF
+C39 a_351_n42# a_n33_n42# 0.02fF
+C40 a_351_n42# a_159_n42# 0.05fF
+C41 a_n417_n42# a_n225_n42# 0.05fF
+C42 a_255_n42# a_639_n42# 0.02fF
+C43 a_735_n42# a_447_n42# 0.03fF
+C44 a_255_n42# a_n129_n42# 0.02fF
+C45 a_n705_n42# a_n609_n42# 0.12fF
+C46 a_255_n42# a_63_n42# 0.05fF
+C47 a_351_n42# a_639_n42# 0.03fF
+C48 a_n129_n42# a_n513_n42# 0.02fF
+C49 a_351_n42# a_63_n42# 0.03fF
+C50 a_n513_n42# a_n225_n42# 0.03fF
+C51 a_n321_n42# a_n609_n42# 0.03fF
+C52 a_n513_n42# a_n417_n42# 0.12fF
+C53 a_735_n42# a_639_n42# 0.12fF
+C54 a_n797_n42# a_n417_n42# 0.02fF
+C55 a_447_n42# a_543_n42# 0.12fF
+C56 a_255_n42# a_351_n42# 0.12fF
+C57 a_n321_n42# a_n33_n42# 0.03fF
+C58 a_735_n42# w_n935_n252# 0.07fF
+C59 a_639_n42# w_n935_n252# 0.05fF
+C60 a_543_n42# w_n935_n252# 0.05fF
+C61 a_447_n42# w_n935_n252# 0.04fF
+C62 a_351_n42# w_n935_n252# 0.04fF
+C63 a_255_n42# w_n935_n252# 0.04fF
+C64 a_159_n42# w_n935_n252# 0.04fF
+C65 a_63_n42# w_n935_n252# 0.04fF
+C66 a_n33_n42# w_n935_n252# 0.04fF
+C67 a_n129_n42# w_n935_n252# 0.04fF
+C68 a_n225_n42# w_n935_n252# 0.04fF
+C69 a_n321_n42# w_n935_n252# 0.04fF
+C70 a_n417_n42# w_n935_n252# 0.04fF
+C71 a_n513_n42# w_n935_n252# 0.04fF
+C72 a_n609_n42# w_n935_n252# 0.05fF
+C73 a_n705_n42# w_n935_n252# 0.05fF
+C74 a_n797_n42# w_n935_n252# 0.07fF
+C75 a_n757_64# w_n935_n252# 2.44fF
+.ends
+
+.subckt inverter_min_x16 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_BDRUME_0 vss out vdd vdd out vdd vdd in out vdd vdd out vdd
++ out vdd out vdd out out out sky130_fd_pr__pfet_01v8_BDRUME
+Xsky130_fd_pr__nfet_01v8_QQE8KM_0 out vss out out out out vss vss out vss in vss vss
++ out vss out vss out vss sky130_fd_pr__nfet_01v8_QQE8KM
+C0 vdd in 1.15fF
+C1 in out 1.40fF
+C2 vdd out 1.63fF
+C3 out vss 0.98fF
+C4 in vss 7.30fF
+C5 vdd vss 10.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_75PKJG VSUBS a_n33_n102# w_n359_n321# a_n177_n199#
++ a_63_n102# a_n129_n102# a_n221_n102# a_25_n199# a_159_n102#
+X0 a_159_n102# a_25_n199# a_63_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_25_n199# a_n33_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X2 a_n129_n102# a_n177_n199# a_n221_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X3 a_n33_n102# a_n177_n199# a_n129_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+C0 a_159_n102# a_n33_n102# 0.11fF
+C1 w_n359_n321# a_n33_n102# 0.06fF
+C2 a_n129_n102# a_63_n102# 0.11fF
+C3 a_159_n102# a_n221_n102# 0.05fF
+C4 w_n359_n321# a_n221_n102# 0.10fF
+C5 a_63_n102# a_n33_n102# 0.30fF
+C6 w_n359_n321# a_159_n102# 0.10fF
+C7 a_n129_n102# a_n33_n102# 0.30fF
+C8 a_63_n102# a_n221_n102# 0.07fF
+C9 a_25_n199# a_n177_n199# 0.07fF
+C10 a_63_n102# a_159_n102# 0.30fF
+C11 a_n129_n102# a_n221_n102# 0.30fF
+C12 a_63_n102# w_n359_n321# 0.07fF
+C13 a_n129_n102# a_159_n102# 0.07fF
+C14 a_n33_n102# a_n221_n102# 0.11fF
+C15 a_n129_n102# w_n359_n321# 0.07fF
+C16 a_159_n102# VSUBS 0.03fF
+C17 a_63_n102# VSUBS 0.03fF
+C18 a_n33_n102# VSUBS 0.03fF
+C19 a_n129_n102# VSUBS 0.03fF
+C20 a_n221_n102# VSUBS 0.03fF
+C21 a_25_n199# VSUBS 0.22fF
+C22 a_n177_n199# VSUBS 0.22fF
+C23 w_n359_n321# VSUBS 2.35fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XRJ78J a_n33_n102# w_n263_n312# a_63_n102# a_n125_n102#
++ a_n81_124#
+X0 a_n33_n102# a_n81_124# a_n125_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_n81_124# a_n33_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+C0 a_n33_n102# a_n125_n102# 0.30fF
+C1 a_n125_n102# a_63_n102# 0.11fF
+C2 a_n33_n102# a_63_n102# 0.30fF
+C3 a_63_n102# w_n263_n312# 0.06fF
+C4 a_n33_n102# w_n263_n312# 0.08fF
+C5 a_n125_n102# w_n263_n312# 0.12fF
+C6 a_n81_124# w_n263_n312# 0.21fF
+.ends
+
+.subckt nand_logic avss1p8 in1 avdd1p8 in2 out m1_21_n341#
+Xsky130_fd_pr__pfet_01v8_75PKJG_0 avss1p8 avdd1p8 avdd1p8 in1 out out avdd1p8 in2
++ avdd1p8 sky130_fd_pr__pfet_01v8_75PKJG
+Xsky130_fd_pr__nfet_01v8_XRJ78J_0 m1_21_n341# avss1p8 avss1p8 avss1p8 in1 sky130_fd_pr__nfet_01v8_XRJ78J
+Xsky130_fd_pr__nfet_01v8_XRJ78J_1 out avss1p8 m1_21_n341# m1_21_n341# in2 sky130_fd_pr__nfet_01v8_XRJ78J
+C0 m1_21_n341# avdd1p8 0.01fF
+C1 in2 out 0.37fF
+C2 in1 in2 0.07fF
+C3 in2 avdd1p8 0.02fF
+C4 m1_21_n341# out 0.13fF
+C5 in1 out 0.10fF
+C6 out avdd1p8 0.20fF
+C7 in1 m1_21_n341# 0.25fF
+C8 m1_21_n341# avss1p8 0.92fF
+C9 out avss1p8 0.47fF
+C10 in2 avss1p8 0.91fF
+C11 in1 avss1p8 0.93fF
+C12 avdd1p8 avss1p8 2.37fF
+.ends
+
+.subckt res_amp_sync_v2 avdd1p8 DFlipFlop_4/Q vss clkn DFlipFlop_4/latch_diff_1/m1_657_280#
++ DFlipFlop_4/nQ DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_0/D DFlipFlop_3/Q
++ DFlipFlop_3/D DFlipFlop_4/D DFlipFlop_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_4/latch_diff_1/D DFlipFlop_4/latch_diff_1/nD DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_4/latch_diff_0/D DFlipFlop_3/latch_diff_1/D clk_amp DFlipFlop_3/nQ clkp
++ rst
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_3/D
++ DFlipFlop_0/latch_diff_0/D clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/nQ DFlipFlop_1/latch_diff_0/nD
++ DFlipFlop_2/D DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D DFlipFlop_3/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/Q DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ DFlipFlop_2/Q DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
++ DFlipFlop_2/latch_diff_0/D clkp DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
++ DFlipFlop_3/Q DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/D
++ DFlipFlop_3/latch_diff_0/D clkp DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+Xinverter_min_x4_0 avdd1p8 DFlipFlop_0/Q vss DFlipFlop_3/D inverter_min_x4
+Xinverter_min_x4_1 avdd1p8 nand_logic_0/out vss DFlipFlop_4/D inverter_min_x4
+XDFlipFlop_4 DFlipFlop_4/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_4/latch_diff_1/D
++ DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_4/nQ DFlipFlop_4/latch_diff_0/nD
++ DFlipFlop_4/Q DFlipFlop_4/latch_diff_1/nD DFlipFlop_4/latch_diff_1/m1_657_280# DFlipFlop_4/D
++ DFlipFlop_4/latch_diff_0/D clkp DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+Xinverter_min_x4_2 avdd1p8 DFlipFlop_2/D vss DFlipFlop_1/D inverter_min_x4
+Xinverter_min_x4_3 avdd1p8 nand_logic_1/out vss rst inverter_min_x4
+Xinverter_min_x4_4 avdd1p8 DFlipFlop_4/Q vss inverter_min_x4_4/out inverter_min_x4
+Xinverter_min_x16_0 inverter_min_x4_4/out clk_amp vss avdd1p8 inverter_min_x16
+Xnand_logic_0 vss DFlipFlop_2/Q avdd1p8 DFlipFlop_3/Q nand_logic_0/out nand_logic_0/m1_21_n341#
++ nand_logic
+Xnand_logic_1 vss DFlipFlop_4/D avdd1p8 clkp nand_logic_1/out nand_logic_1/m1_21_n341#
++ nand_logic
+C0 DFlipFlop_2/latch_diff_1/nD clkn 0.17fF
+C1 clkp DFlipFlop_2/latch_diff_1/D 0.15fF
+C2 DFlipFlop_3/latch_diff_1/D clkp 0.15fF
+C3 clkp DFlipFlop_4/Q 0.20fF
+C4 nand_logic_0/m1_21_n341# DFlipFlop_3/Q 0.07fF
+C5 DFlipFlop_0/latch_diff_0/D clkn 0.12fF
+C6 DFlipFlop_2/latch_diff_1/D clkn 0.08fF
+C7 DFlipFlop_3/latch_diff_1/D clkn 0.08fF
+C8 DFlipFlop_2/latch_diff_1/D DFlipFlop_3/Q 0.03fF
+C9 avdd1p8 DFlipFlop_2/D 4.16fF
+C10 DFlipFlop_3/Q DFlipFlop_4/Q 0.11fF
+C11 inverter_min_x4_4/out clk_amp 0.12fF
+C12 DFlipFlop_3/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.54fF
+C13 DFlipFlop_3/D avdd1p8 4.16fF
+C14 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out clkp -0.31fF
+C15 avdd1p8 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.01fF
+C16 nand_logic_1/out nand_logic_1/m1_21_n341# 0.01fF
+C17 DFlipFlop_3/nQ avdd1p8 0.03fF
+C18 avdd1p8 DFlipFlop_4/D 0.52fF
+C19 DFlipFlop_0/Q DFlipFlop_1/latch_diff_0/D 0.74fF
+C20 DFlipFlop_1/D DFlipFlop_1/latch_diff_1/D 0.02fF
+C21 DFlipFlop_2/D DFlipFlop_2/latch_diff_1/D 0.03fF
+C22 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/Q 0.55fF
+C23 DFlipFlop_3/D DFlipFlop_0/latch_diff_0/D 0.31fF
+C24 nand_logic_0/out avdd1p8 0.03fF
+C25 nand_logic_0/m1_21_n341# DFlipFlop_4/D 0.02fF
+C26 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in clkn -0.33fF
+C27 DFlipFlop_4/D DFlipFlop_4/Q 0.27fF
+C28 DFlipFlop_4/latch_diff_0/m1_657_280# clkp 0.30fF
+C29 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
+C30 clkp clkn 0.22fF
+C31 clkp DFlipFlop_3/Q 0.17fF
+C32 nand_logic_0/out nand_logic_0/m1_21_n341# 0.01fF
+C33 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out clkp 0.16fF
+C34 DFlipFlop_2/Q clkp 0.11fF
+C35 avdd1p8 inverter_min_x4_4/out 0.09fF
+C36 clkp DFlipFlop_0/latch_diff_0/nD 0.08fF
+C37 DFlipFlop_3/Q clkn 0.12fF
+C38 nand_logic_1/out avdd1p8 0.04fF
+C39 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_4/D 0.42fF
+C40 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/D 0.03fF
+C41 clkp DFlipFlop_0/latch_diff_0/m1_657_280# 0.32fF
+C42 DFlipFlop_0/Q avdd1p8 0.66fF
+C43 DFlipFlop_2/Q DFlipFlop_3/Q 0.09fF
+C44 clkp DFlipFlop_3/latch_diff_0/m1_657_280# 0.30fF
+C45 clkn DFlipFlop_2/latch_diff_0/D 0.12fF
+C46 DFlipFlop_1/D DFlipFlop_2/D 0.02fF
+C47 DFlipFlop_3/D DFlipFlop_1/D 0.28fF
+C48 DFlipFlop_2/D clkp 0.15fF
+C49 DFlipFlop_3/D clkp 0.35fF
+C50 inverter_min_x4_4/out DFlipFlop_4/Q 0.01fF
+C51 DFlipFlop_2/D clkn 0.15fF
+C52 clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C53 DFlipFlop_3/D clkn 0.35fF
+C54 avdd1p8 clk_amp 0.10fF
+C55 DFlipFlop_3/nQ clkp 0.13fF
+C56 DFlipFlop_4/D clkp 0.24fF
+C57 clkn DFlipFlop_3/latch_diff_0/D 0.12fF
+C58 DFlipFlop_4/latch_diff_0/D clkn 0.12fF
+C59 clkp DFlipFlop_4/latch_diff_0/nD 0.08fF
+C60 DFlipFlop_3/nQ clkn 0.10fF
+C61 clkp DFlipFlop_0/latch_diff_1/nD 0.10fF
+C62 DFlipFlop_4/D clkn 0.15fF
+C63 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.02fF
+C64 DFlipFlop_2/D DFlipFlop_2/latch_diff_0/D -0.07fF
+C65 DFlipFlop_1/D DFlipFlop_1/nQ 0.02fF
+C66 DFlipFlop_4/D DFlipFlop_3/Q 0.94fF
+C67 clkn DFlipFlop_0/latch_diff_1/nD 0.17fF
+C68 DFlipFlop_2/latch_diff_0/nD clkp 0.08fF
+C69 DFlipFlop_3/D DFlipFlop_2/D 0.06fF
+C70 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/nD 0.02fF
+C71 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out clkp 0.16fF
+C72 nand_logic_0/out DFlipFlop_3/Q 0.01fF
+C73 nand_logic_0/out DFlipFlop_2/Q 0.02fF
+C74 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/D 0.10fF
+C75 DFlipFlop_3/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.43fF
+C76 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/m1_657_280# 0.25fF
+C77 clkp inverter_min_x4_4/out 0.43fF
+C78 nand_logic_1/out clkp 0.03fF
+C79 DFlipFlop_0/Q DFlipFlop_1/D 0.72fF
+C80 DFlipFlop_2/latch_diff_1/m1_657_280# clkn 0.30fF
+C81 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/nD 0.17fF
+C82 DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_3/Q 0.04fF
+C83 DFlipFlop_4/nQ DFlipFlop_4/Q 0.06fF
+C84 DFlipFlop_3/D DFlipFlop_1/nQ 0.05fF
+C85 DFlipFlop_0/nQ clkp 0.02fF
+C86 DFlipFlop_4/latch_diff_1/D clkp 0.15fF
+C87 DFlipFlop_0/latch_diff_1/m1_657_280# clkn 0.30fF
+C88 DFlipFlop_2/nQ clkp 0.13fF
+C89 DFlipFlop_0/nQ clkn 0.02fF
+C90 DFlipFlop_4/latch_diff_1/D clkn 0.08fF
+C91 nand_logic_1/out rst 0.04fF
+C92 clkp DFlipFlop_4/latch_diff_1/nD 0.10fF
+C93 DFlipFlop_2/nQ clkn 0.02fF
+C94 DFlipFlop_2/nQ DFlipFlop_3/Q 0.02fF
+C95 nand_logic_0/out DFlipFlop_4/D 0.04fF
+C96 clkp clk_amp 0.52fF
+C97 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C98 DFlipFlop_4/latch_diff_1/nD clkn 0.17fF
+C99 avdd1p8 DFlipFlop_4/Q 4.03fF
+C100 nand_logic_1/m1_21_n341# clkp 0.09fF
+C101 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/D 0.41fF
+C102 DFlipFlop_3/D DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C103 DFlipFlop_2/latch_diff_0/m1_657_280# clkp 0.30fF
+C104 DFlipFlop_3/D DFlipFlop_0/Q 0.38fF
+C105 DFlipFlop_3/latch_diff_1/m1_657_280# clkn 0.30fF
+C106 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/nD 0.19fF
+C107 DFlipFlop_0/latch_diff_1/D clkp 0.15fF
+C108 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.03fF
+C109 DFlipFlop_3/D DFlipFlop_0/nQ 0.08fF
+C110 DFlipFlop_2/nQ DFlipFlop_2/D 0.03fF
+C111 nand_logic_1/m1_21_n341# rst 0.02fF
+C112 nand_logic_1/out DFlipFlop_4/D 0.01fF
+C113 DFlipFlop_0/latch_diff_1/D clkn 0.08fF
+C114 DFlipFlop_4/nQ clkp 0.02fF
+C115 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/D 0.49fF
+C116 DFlipFlop_4/nQ clkn 0.02fF
+C117 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.03fF
+C118 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C119 DFlipFlop_0/Q DFlipFlop_1/nQ 0.01fF
+C120 DFlipFlop_3/latch_diff_0/nD clkp 0.08fF
+C121 DFlipFlop_1/D avdd1p8 2.55fF
+C122 avdd1p8 clkp 0.53fF
+C123 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/D 0.08fF
+C124 clkp DFlipFlop_3/latch_diff_1/nD 0.10fF
+C125 nand_logic_1/m1_21_n341# DFlipFlop_4/D 0.09fF
+C126 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C127 avdd1p8 clkn -1.00fF
+C128 clkn DFlipFlop_4/latch_diff_1/m1_657_280# 0.30fF
+C129 avdd1p8 DFlipFlop_3/Q 0.76fF
+C130 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
+C131 DFlipFlop_2/latch_diff_1/nD clkp 0.20fF
+C132 clkn DFlipFlop_3/latch_diff_1/nD 0.17fF
+C133 avdd1p8 DFlipFlop_2/Q 0.05fF
+C134 avdd1p8 rst 0.02fF
+C135 nand_logic_1/m1_21_n341# vss 0.86fF
+C136 nand_logic_0/m1_21_n341# vss 0.90fF
+C137 clk_amp vss 0.43fF
+C138 inverter_min_x4_4/out vss 5.90fF
+C139 nand_logic_1/out vss 1.76fF
+C140 rst vss 0.71fF
+C141 DFlipFlop_4/nQ vss 0.48fF
+C142 DFlipFlop_4/Q vss -2.08fF
+C143 DFlipFlop_4/latch_diff_1/m1_657_280# vss 0.57fF
+C144 DFlipFlop_4/latch_diff_1/nD vss 0.57fF
+C145 DFlipFlop_4/latch_diff_1/D vss -1.73fF
+C146 DFlipFlop_4/latch_diff_0/m1_657_280# vss 0.57fF
+C147 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C148 DFlipFlop_4/latch_diff_0/D vss 0.96fF
+C149 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C150 DFlipFlop_4/D vss 4.59fF
+C151 DFlipFlop_4/latch_diff_0/nD vss 1.14fF
+C152 nand_logic_0/out vss 1.26fF
+C153 DFlipFlop_0/Q vss -3.86fF
+C154 DFlipFlop_3/nQ vss 0.50fF
+C155 DFlipFlop_3/Q vss -2.01fF
+C156 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.72fF
+C157 clkn vss -2.25fF
+C158 DFlipFlop_3/latch_diff_1/nD vss 0.58fF
+C159 DFlipFlop_3/latch_diff_1/D vss -1.72fF
+C160 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C161 clkp vss -22.80fF
+C162 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C163 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C164 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C165 DFlipFlop_3/D vss 1.64fF
+C166 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C167 avdd1p8 vss 196.01fF
+C168 DFlipFlop_2/nQ vss 0.48fF
+C169 DFlipFlop_2/Q vss -1.05fF
+C170 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.65fF
+C171 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C172 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 DFlipFlop_2/D vss -0.35fF
+C178 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C179 DFlipFlop_1/nQ vss 0.48fF
+C180 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.59fF
+C181 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C182 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C183 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C184 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C185 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C186 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C187 DFlipFlop_1/D vss -1.00fF
+C188 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C189 DFlipFlop_0/nQ vss 0.48fF
+C190 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.59fF
+C191 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C192 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C193 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C194 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C195 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C196 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C197 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_4L9VGG VSUBS a_291_n200# w_n487_n419# a_35_n200#
++ a_n291_n238# a_n93_n200# a_163_n200# a_n349_n200# a_n221_n200#
+X0 a_291_n200# a_n291_n238# a_163_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_n221_n200# a_n291_n238# a_n349_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_35_n200# a_n291_n238# a_n93_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_163_n200# a_n291_n238# a_35_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_n93_n200# a_n291_n238# a_n221_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+C0 a_163_n200# a_n221_n200# 0.09fF
+C1 a_n349_n200# a_n221_n200# 0.36fF
+C2 a_n221_n200# a_n291_n238# 0.08fF
+C3 w_n487_n419# a_n221_n200# 0.08fF
+C4 a_35_n200# a_n221_n200# 0.15fF
+C5 a_n93_n200# a_n221_n200# 0.36fF
+C6 a_163_n200# a_n291_n238# 0.08fF
+C7 a_163_n200# w_n487_n419# 0.08fF
+C8 a_163_n200# a_291_n200# 0.36fF
+C9 a_n349_n200# w_n487_n419# 0.18fF
+C10 w_n487_n419# a_n291_n238# 0.30fF
+C11 a_163_n200# a_35_n200# 0.36fF
+C12 a_291_n200# w_n487_n419# 0.18fF
+C13 a_n349_n200# a_35_n200# 0.09fF
+C14 a_35_n200# a_n291_n238# 0.08fF
+C15 a_163_n200# a_n93_n200# 0.15fF
+C16 a_35_n200# w_n487_n419# 0.06fF
+C17 a_35_n200# a_291_n200# 0.15fF
+C18 a_n349_n200# a_n93_n200# 0.15fF
+C19 a_n93_n200# a_n291_n238# 0.08fF
+C20 a_n93_n200# w_n487_n419# 0.06fF
+C21 a_n93_n200# a_291_n200# 0.09fF
+C22 a_n93_n200# a_35_n200# 0.36fF
+C23 a_291_n200# VSUBS 0.03fF
+C24 a_163_n200# VSUBS 0.03fF
+C25 a_35_n200# VSUBS 0.03fF
+C26 a_n93_n200# VSUBS 0.03fF
+C27 a_n221_n200# VSUBS 0.03fF
+C28 a_n349_n200# VSUBS 0.03fF
+C29 a_n291_n238# VSUBS 0.72fF
+C30 w_n487_n419# VSUBS 4.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_L78GGD a_n73_n73# w_n211_n221# a_15_n73# a_n33_33#
+X0 a_15_n73# a_n33_33# a_n73_n73# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n73# a_n33_33# 0.02fF
+C1 a_15_n73# a_n73_n73# 0.15fF
+C2 a_15_n73# a_n33_33# 0.02fF
+C3 a_15_n73# w_n211_n221# 0.11fF
+C4 a_n73_n73# w_n211_n221# 0.11fF
+C5 a_n33_33# w_n211_n221# 0.18fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_6RX2PQ VSUBS w_n211_n268# a_15_n48# a_n33_n145# a_n73_n48#
+X0 a_15_n48# a_n33_n145# a_n73_n48# w_n211_n268# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n73_n48# a_15_n48# 0.29fF
+C1 w_n211_n268# a_n33_n145# 0.06fF
+C2 a_n73_n48# a_n33_n145# 0.01fF
+C3 a_n73_n48# w_n211_n268# 0.13fF
+C4 a_n33_n145# a_15_n48# 0.01fF
+C5 w_n211_n268# a_15_n48# 0.13fF
+C6 a_15_n48# VSUBS 0.03fF
+C7 a_n73_n48# VSUBS 0.03fF
+C8 a_n33_n145# VSUBS 0.12fF
+C9 w_n211_n268# VSUBS 1.50fF
+.ends
+
+.subckt inverter_min vdd out in vss
+XXM1 vss vss out in sky130_fd_pr__nfet_01v8_L78GGD
+XXM2 vss vdd out in vdd sky130_fd_pr__pfet_01v8_6RX2PQ
+C0 vdd in 0.13fF
+C1 vdd out 0.20fF
+C2 in out 0.67fF
+C3 out vss 0.52fF
+C4 in vss 0.72fF
+C5 vdd vss 2.55fF
+.ends
+
+.subckt buffer_no_inv_x05 VSUBS in avdd1p8 inverter_min_1/in out
+Xinverter_min_1 avdd1p8 out inverter_min_1/in VSUBS inverter_min
+Xinverter_min_0 avdd1p8 inverter_min_1/in in VSUBS inverter_min
+C0 inverter_min_1/in out 0.12fF
+C1 avdd1p8 inverter_min_1/in 0.09fF
+C2 inverter_min_1/in in 0.07fF
+C3 avdd1p8 out 0.02fF
+C4 in VSUBS 0.63fF
+C5 avdd1p8 VSUBS 4.78fF
+C6 out VSUBS 0.45fF
+C7 inverter_min_1/in VSUBS 1.08fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XA7ZMQ VSUBS a_21_142# a_63_n111# a_n87_142# a_n125_n111#
++ w_n263_n330# a_n33_n111#
+X0 a_n33_n111# a_n87_142# a_n125_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+X1 a_63_n111# a_21_142# a_n33_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+C0 a_n125_n111# a_n87_142# 0.02fF
+C1 a_21_142# a_63_n111# 0.02fF
+C2 a_n125_n111# w_n263_n330# 0.14fF
+C3 a_n87_142# w_n263_n330# 0.05fF
+C4 a_n125_n111# a_n33_n111# 0.32fF
+C5 a_n125_n111# a_63_n111# 0.12fF
+C6 w_n263_n330# a_n33_n111# 0.10fF
+C7 w_n263_n330# a_63_n111# 0.14fF
+C8 a_n87_142# a_21_142# 0.14fF
+C9 a_n33_n111# a_63_n111# 0.32fF
+C10 w_n263_n330# a_21_142# 0.05fF
+C11 a_63_n111# VSUBS 0.03fF
+C12 a_n33_n111# VSUBS 0.03fF
+C13 a_n125_n111# VSUBS 0.03fF
+C14 a_21_142# VSUBS 0.16fF
+C15 a_n87_142# VSUBS 0.16fF
+C16 w_n263_n330# VSUBS 2.11fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HAN8QX a_15_n142# a_n33_102# a_n73_n142# w_n211_n290#
+X0 a_15_n142# a_n33_102# a_n73_n142# w_n211_n290# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+C0 a_n33_102# a_n73_n142# 0.03fF
+C1 a_n33_102# a_15_n142# 0.03fF
+C2 a_15_n142# a_n73_n142# 0.38fF
+C3 a_15_n142# w_n211_n290# 0.19fF
+C4 a_n73_n142# w_n211_n290# 0.19fF
+C5 a_n33_102# w_n211_n290# 0.21fF
+.ends
+
+.subckt mux_2to1_logic sel avdd1p8 sel_b w_947_n633# avss1p8 out DinA DinB
+Xinverter_min_0 avdd1p8 sel_b sel avss1p8 inverter_min
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_0 avss1p8 sel DinA sel DinA avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_1 avss1p8 sel_b DinB sel_b DinB avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__nfet_01v8_HAN8QX_0 out sel_b DinA avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+Xsky130_fd_pr__nfet_01v8_HAN8QX_1 out sel DinB avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+C0 out DinB 0.37fF
+C1 avdd1p8 DinA 0.26fF
+C2 out sel 0.53fF
+C3 out sel_b 0.58fF
+C4 out DinA 0.30fF
+C5 DinB sel 0.02fF
+C6 DinB sel_b 0.27fF
+C7 out avdd1p8 0.23fF
+C8 sel sel_b 0.32fF
+C9 DinB DinA 0.07fF
+C10 avdd1p8 DinB 0.16fF
+C11 sel DinA 0.07fF
+C12 DinA sel_b 0.56fF
+C13 avdd1p8 sel 0.72fF
+C14 avdd1p8 sel_b 0.74fF
+C15 DinA avss1p8 0.63fF
+C16 sel_b avss1p8 2.16fF
+C17 out avss1p8 1.11fF
+C18 DinB avss1p8 -0.09fF
+C19 sel avss1p8 2.55fF
+C20 avdd1p8 avss1p8 8.26fF
+.ends
+
+.subckt delay_cell_buff buffer_no_inv_x05_2/inverter_min_1/in reg2 avss1p8 mux_2to1_logic_4/DinA
++ avdd1p8 buffer_no_inv_x05_13/in clk mux_2to1_logic_3/DinA clk_out mux_2to1_logic_3/DinB
++ reg0 buffer_no_inv_x05_10/inverter_min_1/in reg1 buffer_no_inv_x05_7/inverter_min_1/in
++ nand_logic_0/in1 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b mux_2to1_logic_4/out
++ mux_2to1_logic_1/DinA mux_2to1_logic_1/sel_b buffer_no_inv_x05_3/in mux_2to1_logic_5/out
++ mux_2to1_logic_0/out mux_2to1_logic_4/DinB mux_2to1_logic_3/out buffer_no_inv_x05_13/inverter_min_1/in
++ mux_2to1_logic_1/out mux_2to1_logic_5/w_947_n633# buffer_no_inv_x05_12/inverter_min_1/in
++ nand_logic_0/m1_21_n341#
+Xbuffer_no_inv_x05_8 avss1p8 mux_2to1_logic_3/DinA avdd1p8 buffer_no_inv_x05_8/inverter_min_1/in
++ buffer_no_inv_x05_9/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_9 avss1p8 buffer_no_inv_x05_9/in avdd1p8 buffer_no_inv_x05_9/inverter_min_1/in
++ mux_2to1_logic_3/DinB buffer_no_inv_x05
+Xmux_2to1_logic_0 reg2 avdd1p8 mux_2to1_logic_0/sel_b mux_2to1_logic_0/w_947_n633#
++ avss1p8 mux_2to1_logic_0/out clk mux_2to1_logic_0/DinB mux_2to1_logic
+Xmux_2to1_logic_1 reg2 avdd1p8 mux_2to1_logic_1/sel_b mux_2to1_logic_1/w_947_n633#
++ avss1p8 mux_2to1_logic_1/out mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB mux_2to1_logic
+Xmux_2to1_logic_2 reg1 avdd1p8 mux_2to1_logic_2/sel_b mux_2to1_logic_2/w_947_n633#
++ avss1p8 mux_2to1_logic_2/out mux_2to1_logic_0/out mux_2to1_logic_1/out mux_2to1_logic
+Xmux_2to1_logic_3 reg2 avdd1p8 mux_2to1_logic_3/sel_b mux_2to1_logic_3/w_947_n633#
++ avss1p8 mux_2to1_logic_3/out mux_2to1_logic_3/DinA mux_2to1_logic_3/DinB mux_2to1_logic
+Xmux_2to1_logic_4 reg2 avdd1p8 mux_2to1_logic_4/sel_b mux_2to1_logic_4/w_947_n633#
++ avss1p8 mux_2to1_logic_4/out mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB mux_2to1_logic
+Xmux_2to1_logic_5 reg1 avdd1p8 mux_2to1_logic_5/sel_b mux_2to1_logic_5/w_947_n633#
++ avss1p8 mux_2to1_logic_5/out mux_2to1_logic_3/out mux_2to1_logic_4/out mux_2to1_logic
+Xmux_2to1_logic_6 reg0 avdd1p8 mux_2to1_logic_6/sel_b mux_2to1_logic_6/w_947_n633#
++ avss1p8 nand_logic_0/in1 mux_2to1_logic_2/out mux_2to1_logic_5/out mux_2to1_logic
+Xbuffer_no_inv_x05_10 avss1p8 mux_2to1_logic_3/DinB avdd1p8 buffer_no_inv_x05_10/inverter_min_1/in
++ buffer_no_inv_x05_11/in buffer_no_inv_x05
+Xnand_logic_0 avss1p8 nand_logic_0/in1 avdd1p8 clk clk_out nand_logic_0/m1_21_n341#
++ nand_logic
+Xbuffer_no_inv_x05_11 avss1p8 buffer_no_inv_x05_11/in avdd1p8 buffer_no_inv_x05_11/inverter_min_1/in
++ mux_2to1_logic_4/DinA buffer_no_inv_x05
+Xbuffer_no_inv_x05_12 avss1p8 mux_2to1_logic_4/DinA avdd1p8 buffer_no_inv_x05_12/inverter_min_1/in
++ buffer_no_inv_x05_13/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_13 avss1p8 buffer_no_inv_x05_13/in avdd1p8 buffer_no_inv_x05_13/inverter_min_1/in
++ mux_2to1_logic_4/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_0 avss1p8 clk avdd1p8 buffer_no_inv_x05_0/inverter_min_1/in buffer_no_inv_x05_1/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_2 avss1p8 mux_2to1_logic_0/DinB avdd1p8 buffer_no_inv_x05_2/inverter_min_1/in
++ buffer_no_inv_x05_3/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_1 avss1p8 buffer_no_inv_x05_1/in avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in
++ mux_2to1_logic_0/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_3 avss1p8 buffer_no_inv_x05_3/in avdd1p8 buffer_no_inv_x05_3/inverter_min_1/in
++ mux_2to1_logic_1/DinA buffer_no_inv_x05
+Xbuffer_no_inv_x05_4 avss1p8 mux_2to1_logic_1/DinA avdd1p8 buffer_no_inv_x05_4/inverter_min_1/in
++ buffer_no_inv_x05_5/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_5 avss1p8 buffer_no_inv_x05_5/in avdd1p8 buffer_no_inv_x05_5/inverter_min_1/in
++ mux_2to1_logic_1/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_6 avss1p8 mux_2to1_logic_1/DinB avdd1p8 buffer_no_inv_x05_6/inverter_min_1/in
++ buffer_no_inv_x05_7/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_7 avss1p8 buffer_no_inv_x05_7/in avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in
++ mux_2to1_logic_3/DinA buffer_no_inv_x05
+C0 reg0 mux_2to1_logic_2/out 0.44fF
+C1 mux_2to1_logic_4/sel_b buffer_no_inv_x05_8/inverter_min_1/in 0.01fF
+C2 reg0 mux_2to1_logic_5/out 0.23fF
+C3 buffer_no_inv_x05_0/inverter_min_1/in buffer_no_inv_x05_1/in 0.07fF
+C4 buffer_no_inv_x05_12/inverter_min_1/in buffer_no_inv_x05_13/in 0.07fF
+C5 reg1 reg2 2.15fF
+C6 buffer_no_inv_x05_2/inverter_min_1/in mux_2to1_logic_1/DinA 0.10fF
+C7 buffer_no_inv_x05_1/in buffer_no_inv_x05_1/inverter_min_1/in 0.12fF
+C8 avdd1p8 reg2 0.14fF
+C9 mux_2to1_logic_3/DinA reg2 0.33fF
+C10 buffer_no_inv_x05_1/inverter_min_1/in mux_2to1_logic_0/DinB 0.08fF
+C11 clk mux_2to1_logic_0/DinB 0.01fF
+C12 mux_2to1_logic_0/out reg1 0.63fF
+C13 mux_2to1_logic_2/out nand_logic_0/in1 0.06fF
+C14 clk mux_2to1_logic_1/DinB 0.01fF
+C15 mux_2to1_logic_5/out mux_2to1_logic_2/out 1.29fF
+C16 reg2 mux_2to1_logic_2/sel_b 0.07fF
+C17 buffer_no_inv_x05_2/inverter_min_1/in buffer_no_inv_x05_3/in 0.07fF
+C18 mux_2to1_logic_0/out avdd1p8 0.43fF
+C19 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_3/DinB 0.02fF
+C20 mux_2to1_logic_0/out mux_2to1_logic_1/out 1.27fF
+C21 mux_2to1_logic_5/out nand_logic_0/in1 0.38fF
+C22 buffer_no_inv_x05_9/in mux_2to1_logic_3/DinB 0.10fF
+C23 mux_2to1_logic_3/out mux_2to1_logic_5/sel_b 0.37fF
+C24 buffer_no_inv_x05_7/in buffer_no_inv_x05_6/inverter_min_1/in 0.07fF
+C25 mux_2to1_logic_1/DinA mux_2to1_logic_0/DinB 0.11fF
+C26 mux_2to1_logic_4/sel_b mux_2to1_logic_3/DinB 0.04fF
+C27 mux_2to1_logic_4/DinA mux_2to1_logic_6/sel_b 0.01fF
+C28 mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB 0.66fF
+C29 mux_2to1_logic_0/sel_b mux_2to1_logic_0/DinB 0.06fF
+C30 mux_2to1_logic_0/out mux_2to1_logic_2/sel_b 0.15fF
+C31 mux_2to1_logic_3/out mux_2to1_logic_4/DinA 0.12fF
+C32 avdd1p8 buffer_no_inv_x05_6/inverter_min_1/in 0.03fF
+C33 mux_2to1_logic_3/DinA buffer_no_inv_x05_6/inverter_min_1/in 0.04fF
+C34 buffer_no_inv_x05_2/inverter_min_1/in avdd1p8 0.03fF
+C35 avdd1p8 buffer_no_inv_x05_9/in 0.10fF
+C36 avdd1p8 buffer_no_inv_x05_5/inverter_min_1/in 0.03fF
+C37 avdd1p8 mux_2to1_logic_4/sel_b 0.07fF
+C38 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinB 0.03fF
+C39 mux_2to1_logic_2/out reg2 0.85fF
+C40 buffer_no_inv_x05_3/inverter_min_1/in mux_2to1_logic_1/DinB 0.15fF
+C41 mux_2to1_logic_4/DinB mux_2to1_logic_6/sel_b 0.28fF
+C42 mux_2to1_logic_3/out mux_2to1_logic_4/DinB 0.18fF
+C43 mux_2to1_logic_4/DinB mux_2to1_logic_5/sel_b 0.31fF
+C44 avdd1p8 buffer_no_inv_x05_1/in 0.09fF
+C45 mux_2to1_logic_0/out mux_2to1_logic_2/out 0.05fF
+C46 avdd1p8 mux_2to1_logic_0/DinB 1.33fF
+C47 mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB 1.68fF
+C48 buffer_no_inv_x05_4/inverter_min_1/in mux_2to1_logic_1/DinB 0.15fF
+C49 buffer_no_inv_x05_3/in mux_2to1_logic_1/sel_b 0.01fF
+C50 avdd1p8 mux_2to1_logic_1/DinB 1.09fF
+C51 mux_2to1_logic_3/DinA mux_2to1_logic_1/DinB 0.07fF
+C52 mux_2to1_logic_1/out mux_2to1_logic_1/DinB 0.23fF
+C53 clk mux_2to1_logic_4/DinA 0.01fF
+C54 mux_2to1_logic_4/DinB buffer_no_inv_x05_13/inverter_min_1/in 0.11fF
+C55 buffer_no_inv_x05_9/inverter_min_1/in buffer_no_inv_x05_9/in 0.12fF
+C56 mux_2to1_logic_2/sel_b mux_2to1_logic_1/DinB 0.04fF
+C57 buffer_no_inv_x05_7/inverter_min_1/in mux_2to1_logic_3/DinB 0.10fF
+C58 avdd1p8 mux_2to1_logic_1/sel_b 0.09fF
+C59 buffer_no_inv_x05_7/inverter_min_1/in buffer_no_inv_x05_7/in 0.12fF
+C60 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b 0.22fF
+C61 clk mux_2to1_logic_4/DinB 0.12fF
+C62 mux_2to1_logic_3/out mux_2to1_logic_3/DinB 0.13fF
+C63 mux_2to1_logic_3/DinB mux_2to1_logic_5/sel_b 0.01fF
+C64 avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in 0.04fF
+C65 mux_2to1_logic_3/DinA buffer_no_inv_x05_7/inverter_min_1/in 0.21fF
+C66 buffer_no_inv_x05_11/inverter_min_1/in mux_2to1_logic_4/DinA 0.08fF
+C67 mux_2to1_logic_0/out reg2 0.45fF
+C68 mux_2to1_logic_3/DinB mux_2to1_logic_3/sel_b 0.21fF
+C69 mux_2to1_logic_4/DinA mux_2to1_logic_3/DinB 0.90fF
+C70 buffer_no_inv_x05_4/inverter_min_1/in buffer_no_inv_x05_5/in 0.07fF
+C71 reg1 mux_2to1_logic_3/out 0.47fF
+C72 reg1 mux_2to1_logic_5/sel_b 0.06fF
+C73 avdd1p8 mux_2to1_logic_6/sel_b 0.05fF
+C74 avdd1p8 buffer_no_inv_x05_5/in 0.09fF
+C75 mux_2to1_logic_4/out mux_2to1_logic_6/sel_b 0.04fF
+C76 mux_2to1_logic_3/out avdd1p8 0.39fF
+C77 mux_2to1_logic_1/DinA clk 0.01fF
+C78 mux_2to1_logic_3/out mux_2to1_logic_3/DinA 0.05fF
+C79 avdd1p8 mux_2to1_logic_5/sel_b 0.09fF
+C80 mux_2to1_logic_3/out mux_2to1_logic_4/out 1.18fF
+C81 mux_2to1_logic_4/out mux_2to1_logic_5/sel_b 0.20fF
+C82 mux_2to1_logic_0/sel_b buffer_no_inv_x05_1/inverter_min_1/in 0.01fF
+C83 avdd1p8 mux_2to1_logic_3/sel_b 0.09fF
+C84 mux_2to1_logic_1/out mux_2to1_logic_3/sel_b 0.04fF
+C85 avdd1p8 mux_2to1_logic_4/DinA 1.95fF
+C86 mux_2to1_logic_3/DinA mux_2to1_logic_4/DinA 0.07fF
+C87 buffer_no_inv_x05_5/in mux_2to1_logic_2/sel_b 0.01fF
+C88 mux_2to1_logic_4/out mux_2to1_logic_4/DinA 0.27fF
+C89 mux_2to1_logic_4/DinB mux_2to1_logic_3/DinB 0.29fF
+C90 reg2 mux_2to1_logic_4/sel_b 0.06fF
+C91 mux_2to1_logic_3/DinB buffer_no_inv_x05_8/inverter_min_1/in 0.10fF
+C92 clk mux_2to1_logic_3/DinB 0.01fF
+C93 reg0 mux_2to1_logic_6/sel_b 0.06fF
+C94 avdd1p8 buffer_no_inv_x05_13/inverter_min_1/in 0.03fF
+C95 reg1 mux_2to1_logic_4/DinB 0.40fF
+C96 clk clk_out 0.33fF
+C97 reg2 buffer_no_inv_x05_1/in 0.01fF
+C98 buffer_no_inv_x05_0/inverter_min_1/in avdd1p8 0.01fF
+C99 avdd1p8 mux_2to1_logic_4/DinB 2.49fF
+C100 reg2 mux_2to1_logic_0/DinB 0.06fF
+C101 mux_2to1_logic_4/out mux_2to1_logic_4/DinB 0.65fF
+C102 nand_logic_0/m1_21_n341# clk_out 0.02fF
+C103 mux_2to1_logic_1/DinA buffer_no_inv_x05_3/in 0.16fF
+C104 mux_2to1_logic_1/DinA buffer_no_inv_x05_3/inverter_min_1/in 0.23fF
+C105 reg2 mux_2to1_logic_1/DinB 0.07fF
+C106 avdd1p8 buffer_no_inv_x05_8/inverter_min_1/in 0.03fF
+C107 avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in 0.03fF
+C108 mux_2to1_logic_3/DinA buffer_no_inv_x05_8/inverter_min_1/in 0.12fF
+C109 avdd1p8 clk 1.01fF
+C110 clk mux_2to1_logic_3/DinA 0.01fF
+C111 mux_2to1_logic_2/out mux_2to1_logic_6/sel_b 0.31fF
+C112 mux_2to1_logic_3/out mux_2to1_logic_2/out 0.99fF
+C113 mux_2to1_logic_2/out mux_2to1_logic_5/sel_b 0.20fF
+C114 mux_2to1_logic_0/out mux_2to1_logic_0/DinB 0.14fF
+C115 mux_2to1_logic_5/out mux_2to1_logic_6/sel_b 0.20fF
+C116 mux_2to1_logic_3/DinB buffer_no_inv_x05_10/inverter_min_1/in 0.12fF
+C117 mux_2to1_logic_3/out mux_2to1_logic_5/out 0.07fF
+C118 mux_2to1_logic_1/DinA buffer_no_inv_x05_4/inverter_min_1/in 0.12fF
+C119 mux_2to1_logic_0/out mux_2to1_logic_1/DinB 0.12fF
+C120 buffer_no_inv_x05_13/in buffer_no_inv_x05_13/inverter_min_1/in 0.12fF
+C121 mux_2to1_logic_2/out mux_2to1_logic_3/sel_b 0.33fF
+C122 buffer_no_inv_x05_3/in buffer_no_inv_x05_3/inverter_min_1/in 0.12fF
+C123 mux_2to1_logic_1/DinA avdd1p8 0.55fF
+C124 mux_2to1_logic_1/out mux_2to1_logic_1/DinA 0.05fF
+C125 reg2 mux_2to1_logic_1/sel_b 0.13fF
+C126 buffer_no_inv_x05_12/inverter_min_1/in mux_2to1_logic_4/DinA 0.12fF
+C127 reg0 mux_2to1_logic_4/DinB -0.24fF
+C128 mux_2to1_logic_0/sel_b avdd1p8 0.05fF
+C129 mux_2to1_logic_5/out mux_2to1_logic_4/DinA 0.23fF
+C130 buffer_no_inv_x05_13/in mux_2to1_logic_4/DinB 0.11fF
+C131 buffer_no_inv_x05_7/in mux_2to1_logic_3/DinB 0.10fF
+C132 buffer_no_inv_x05_11/in buffer_no_inv_x05_10/inverter_min_1/in 0.07fF
+C133 buffer_no_inv_x05_2/inverter_min_1/in mux_2to1_logic_0/DinB 0.12fF
+C134 avdd1p8 buffer_no_inv_x05_10/inverter_min_1/in 0.03fF
+C135 buffer_no_inv_x05_11/inverter_min_1/in buffer_no_inv_x05_11/in 0.14fF
+C136 clk buffer_no_inv_x05_13/in 0.07fF
+C137 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_1/DinB 0.12fF
+C138 buffer_no_inv_x05_11/inverter_min_1/in avdd1p8 0.03fF
+C139 mux_2to1_logic_0/out mux_2to1_logic_1/sel_b 0.26fF
+C140 avdd1p8 buffer_no_inv_x05_3/in 0.11fF
+C141 avdd1p8 buffer_no_inv_x05_3/inverter_min_1/in 0.03fF
+C142 avdd1p8 mux_2to1_logic_3/DinB 0.82fF
+C143 mux_2to1_logic_3/DinA mux_2to1_logic_3/DinB 1.18fF
+C144 mux_2to1_logic_2/out mux_2to1_logic_4/DinB 0.07fF
+C145 buffer_no_inv_x05_5/inverter_min_1/in mux_2to1_logic_1/DinB 0.23fF
+C146 buffer_no_inv_x05_12/inverter_min_1/in mux_2to1_logic_4/DinB 0.07fF
+C147 avdd1p8 buffer_no_inv_x05_7/in 0.09fF
+C148 mux_2to1_logic_3/DinA buffer_no_inv_x05_7/in 0.13fF
+C149 avdd1p8 clk_out 0.04fF
+C150 mux_2to1_logic_5/out mux_2to1_logic_4/DinB 0.52fF
+C151 reg1 buffer_no_inv_x05_4/inverter_min_1/in 0.01fF
+C152 mux_2to1_logic_3/out reg2 0.36fF
+C153 reg1 avdd1p8 0.08fF
+C154 mux_2to1_logic_1/out reg1 0.36fF
+C155 avdd1p8 buffer_no_inv_x05_4/inverter_min_1/in 0.03fF
+C156 reg1 mux_2to1_logic_4/out 0.37fF
+C157 avdd1p8 buffer_no_inv_x05_11/in 0.10fF
+C158 reg2 mux_2to1_logic_3/sel_b 0.13fF
+C159 avdd1p8 mux_2to1_logic_3/DinA 0.81fF
+C160 mux_2to1_logic_1/out avdd1p8 0.84fF
+C161 reg2 mux_2to1_logic_4/DinA 0.31fF
+C162 avdd1p8 mux_2to1_logic_4/out 0.76fF
+C163 reg0 buffer_no_inv_x05_11/inverter_min_1/in 0.01fF
+C164 reg1 mux_2to1_logic_2/sel_b 0.06fF
+C165 avdd1p8 mux_2to1_logic_2/sel_b 0.07fF
+C166 mux_2to1_logic_1/out mux_2to1_logic_2/sel_b 0.19fF
+C167 reg0 reg1 0.01fF
+C168 mux_2to1_logic_1/sel_b mux_2to1_logic_0/DinB 0.04fF
+C169 reg2 mux_2to1_logic_4/DinB 0.05fF
+C170 buffer_no_inv_x05_9/inverter_min_1/in mux_2to1_logic_3/DinB 0.18fF
+C171 reg0 avdd1p8 0.05fF
+C172 mux_2to1_logic_1/sel_b mux_2to1_logic_1/DinB -0.06fF
+C173 buffer_no_inv_x05_5/in buffer_no_inv_x05_5/inverter_min_1/in 0.12fF
+C174 avdd1p8 buffer_no_inv_x05_13/in 0.10fF
+C175 clk reg2 0.12fF
+C176 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_3/sel_b 0.01fF
+C177 mux_2to1_logic_3/out mux_2to1_logic_4/sel_b 0.23fF
+C178 reg1 mux_2to1_logic_2/out 1.41fF
+C179 avdd1p8 buffer_no_inv_x05_9/inverter_min_1/in 0.03fF
+C180 mux_2to1_logic_0/out clk 0.05fF
+C181 avdd1p8 mux_2to1_logic_2/out 0.41fF
+C182 mux_2to1_logic_1/out mux_2to1_logic_2/out 0.35fF
+C183 mux_2to1_logic_1/DinA reg2 0.18fF
+C184 mux_2to1_logic_2/out mux_2to1_logic_4/out 0.26fF
+C185 buffer_no_inv_x05_12/inverter_min_1/in avdd1p8 0.03fF
+C186 mux_2to1_logic_0/sel_b reg2 0.14fF
+C187 avdd1p8 mux_2to1_logic_5/out 0.64fF
+C188 mux_2to1_logic_5/out mux_2to1_logic_4/out 0.45fF
+C189 buffer_no_inv_x05_5/in mux_2to1_logic_1/DinB 0.15fF
+C190 mux_2to1_logic_0/out mux_2to1_logic_1/DinA 0.12fF
+C191 buffer_no_inv_x05_9/in buffer_no_inv_x05_8/inverter_min_1/in 0.07fF
+C192 mux_2to1_logic_4/sel_b mux_2to1_logic_4/DinB 0.20fF
+C193 reg2 mux_2to1_logic_3/DinB 0.08fF
+C194 buffer_no_inv_x05_7/in avss1p8 1.12fF
+C195 buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.05fF
+C196 buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.04fF
+C197 buffer_no_inv_x05_5/in avss1p8 1.12fF
+C198 buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.04fF
+C199 buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.04fF
+C200 buffer_no_inv_x05_3/in avss1p8 1.13fF
+C201 buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.04fF
+C202 buffer_no_inv_x05_1/in avss1p8 1.12fF
+C203 buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.04fF
+C204 buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.05fF
+C205 clk avss1p8 2.54fF
+C206 buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C207 buffer_no_inv_x05_13/in avss1p8 1.12fF
+C208 mux_2to1_logic_4/DinB avss1p8 -7.83fF
+C209 buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.04fF
+C210 buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.04fF
+C211 buffer_no_inv_x05_11/in avss1p8 1.12fF
+C212 buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.04fF
+C213 nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C214 clk_out avss1p8 0.27fF
+C215 buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.04fF
+C216 mux_2to1_logic_6/sel_b avss1p8 2.08fF
+C217 nand_logic_0/in1 avss1p8 1.63fF
+C218 reg0 avss1p8 3.16fF
+C219 mux_2to1_logic_5/sel_b avss1p8 2.05fF
+C220 mux_2to1_logic_5/out avss1p8 -1.59fF
+C221 mux_2to1_logic_4/DinA avss1p8 -2.53fF
+C222 mux_2to1_logic_4/sel_b avss1p8 2.05fF
+C223 mux_2to1_logic_4/out avss1p8 -2.14fF
+C224 mux_2to1_logic_3/DinA avss1p8 0.02fF
+C225 mux_2to1_logic_3/sel_b avss1p8 2.05fF
+C226 mux_2to1_logic_3/out avss1p8 -2.13fF
+C227 mux_2to1_logic_3/DinB avss1p8 -4.89fF
+C228 mux_2to1_logic_2/sel_b avss1p8 2.05fF
+C229 mux_2to1_logic_2/out avss1p8 -1.34fF
+C230 reg1 avss1p8 4.95fF
+C231 mux_2to1_logic_1/DinA avss1p8 0.68fF
+C232 mux_2to1_logic_1/sel_b avss1p8 2.05fF
+C233 mux_2to1_logic_1/out avss1p8 -2.38fF
+C234 mux_2to1_logic_1/DinB avss1p8 -3.84fF
+C235 reg2 avss1p8 13.29fF
+C236 avdd1p8 avss1p8 125.49fF
+C237 mux_2to1_logic_0/sel_b avss1p8 2.04fF
+C238 mux_2to1_logic_0/out avss1p8 0.32fF
+C239 mux_2to1_logic_0/DinB avss1p8 -0.89fF
+C240 buffer_no_inv_x05_9/in avss1p8 1.12fF
+C241 buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.04fF
+C242 buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.04fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_72JNYZ a_n81_n100# w_n311_n310# a_n128_122# a_111_n100#
++ a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n128_122# a_n81_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n81_n100# a_n128_122# a_n173_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n128_122# a_15_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n81_n100# a_n128_122# 0.10fF
+C1 a_n128_122# a_15_n100# 0.10fF
+C2 a_n81_n100# a_n173_n100# 0.29fF
+C3 a_n81_n100# a_15_n100# 0.29fF
+C4 a_n81_n100# a_111_n100# 0.11fF
+C5 a_n173_n100# a_15_n100# 0.11fF
+C6 a_111_n100# a_n173_n100# 0.06fF
+C7 a_111_n100# a_15_n100# 0.29fF
+C8 a_111_n100# w_n311_n310# 0.15fF
+C9 a_15_n100# w_n311_n310# 0.11fF
+C10 a_n81_n100# w_n311_n310# 0.11fF
+C11 a_n173_n100# w_n311_n310# 0.15fF
+C12 a_n128_122# w_n311_n310# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XL9AN VSUBS w_n311_n319# a_n81_n100# a_111_n100#
++ a_n129_131# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_131# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_131# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_131# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_15_n100# a_n81_n100# 0.29fF
+C1 a_111_n100# a_n173_n100# 0.06fF
+C2 a_15_n100# w_n311_n319# 0.08fF
+C3 a_n173_n100# a_n81_n100# 0.29fF
+C4 a_n173_n100# w_n311_n319# 0.12fF
+C5 a_n173_n100# a_15_n100# 0.11fF
+C6 a_111_n100# a_n81_n100# 0.11fF
+C7 a_n81_n100# a_n129_131# 0.08fF
+C8 a_111_n100# w_n311_n319# 0.12fF
+C9 w_n311_n319# a_n129_131# 0.16fF
+C10 a_n81_n100# w_n311_n319# 0.08fF
+C11 a_111_n100# a_15_n100# 0.29fF
+C12 a_15_n100# a_n129_131# 0.08fF
+C13 a_111_n100# VSUBS 0.03fF
+C14 a_15_n100# VSUBS 0.03fF
+C15 a_n81_n100# VSUBS 0.03fF
+C16 a_n173_n100# VSUBS 0.03fF
+C17 a_n129_131# VSUBS 0.32fF
+C18 w_n311_n319# VSUBS 2.34fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XUYGK VSUBS a_n269_n100# a_n81_n100# w_n407_n319#
++ a_111_n100# a_n177_n100# a_15_n100# a_207_n100# a_n225_131#
+X0 a_207_n100# a_n225_131# a_111_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_131# a_n81_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n225_131# a_15_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n225_131# a_n177_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_131# a_n269_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n269_n100# a_111_n100# 0.05fF
+C1 w_n407_n319# a_n81_n100# 0.06fF
+C2 a_15_n100# a_n177_n100# 0.11fF
+C3 w_n407_n319# a_n269_n100# 0.10fF
+C4 a_n177_n100# a_111_n100# 0.06fF
+C5 a_15_n100# a_n225_131# 0.08fF
+C6 a_n225_131# a_111_n100# 0.08fF
+C7 a_15_n100# a_207_n100# 0.11fF
+C8 a_207_n100# a_111_n100# 0.29fF
+C9 w_n407_n319# a_n177_n100# 0.05fF
+C10 w_n407_n319# a_n225_131# 0.25fF
+C11 a_n81_n100# a_n269_n100# 0.11fF
+C12 w_n407_n319# a_207_n100# 0.10fF
+C13 a_15_n100# a_111_n100# 0.29fF
+C14 a_n81_n100# a_n177_n100# 0.29fF
+C15 a_n81_n100# a_n225_131# 0.08fF
+C16 w_n407_n319# a_15_n100# 0.06fF
+C17 a_n81_n100# a_207_n100# 0.06fF
+C18 w_n407_n319# a_111_n100# 0.05fF
+C19 a_n269_n100# a_n177_n100# 0.29fF
+C20 a_n81_n100# a_15_n100# 0.29fF
+C21 a_n225_131# a_n177_n100# 0.08fF
+C22 a_n81_n100# a_111_n100# 0.11fF
+C23 a_207_n100# a_n177_n100# 0.05fF
+C24 a_15_n100# a_n269_n100# 0.06fF
+C25 a_207_n100# VSUBS 0.03fF
+C26 a_111_n100# VSUBS 0.03fF
+C27 a_15_n100# VSUBS 0.03fF
+C28 a_n81_n100# VSUBS 0.03fF
+C29 a_n177_n100# VSUBS 0.03fF
+C30 a_n269_n100# VSUBS 0.03fF
+C31 a_n225_131# VSUBS 0.54fF
+C32 w_n407_n319# VSUBS 2.92fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_2AP43D a_15_n81# a_n33_41# w_n211_n229# a_n73_n81#
+X0 a_15_n81# a_n33_41# a_n73_n81# w_n211_n229# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=500000u l=150000u
+C0 a_n73_n81# a_n33_41# 0.02fF
+C1 a_n33_41# a_15_n81# 0.02fF
+C2 a_n73_n81# a_15_n81# 0.17fF
+C3 a_15_n81# w_n211_n229# 0.12fF
+C4 a_n73_n81# w_n211_n229# 0.12fF
+C5 a_n33_41# w_n211_n229# 0.18fF
+.ends
+
+.subckt res_amp_lin clk vctrl avdd1p8 avss1p8 a_3747_261# vp inn outn outp inp
+Xsky130_fd_pr__pfet_01v8_2XL9AN_0 avss1p8 avdd1p8 a_3747_261# a_3747_261# clk avdd1p8
++ avdd1p8 sky130_fd_pr__pfet_01v8_2XL9AN
+Xsky130_fd_pr__pfet_01v8_2XUYGK_0 avss1p8 a_3747_261# a_3747_261# avdd1p8 a_3747_261#
++ vp vp vp vctrl sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_1 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_0 avss1p8 clk avss1p8 outp sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_2 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_1 avss1p8 clk avss1p8 outn sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_3 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_4 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_5 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_6 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_7 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_8 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+C0 avdd1p8 outn 1.33fF
+C1 vp avdd1p8 6.92fF
+C2 inn inp 2.67fF
+C3 clk inp 0.06fF
+C4 vp outn 4.23fF
+C5 outp inp 1.28fF
+C6 avdd1p8 inp 1.02fF
+C7 vctrl a_3747_261# 0.76fF
+C8 inp outn 5.59fF
+C9 vp inp 0.78fF
+C10 vctrl clk 0.02fF
+C11 clk a_3747_261# 0.44fF
+C12 vctrl avdd1p8 1.19fF
+C13 inn outp 5.76fF
+C14 clk outp 0.56fF
+C15 avdd1p8 a_3747_261# 1.24fF
+C16 avdd1p8 inn 1.05fF
+C17 clk avdd1p8 2.36fF
+C18 vp a_3747_261# 1.08fF
+C19 avdd1p8 outp 1.56fF
+C20 inn outn 1.15fF
+C21 vp inn 0.84fF
+C22 clk outn 0.71fF
+C23 clk vp 0.79fF
+C24 outp outn 4.18fF
+C25 vp outp 4.81fF
+C26 outn avss1p8 0.69fF
+C27 inp avss1p8 -0.11fF
+C28 outp avss1p8 -0.62fF
+C29 vp avss1p8 -4.89fF
+C30 inn avss1p8 0.23fF
+C31 avdd1p8 avss1p8 31.50fF
+C32 clk avss1p8 1.49fF
+C33 a_3747_261# avss1p8 -0.95fF
+C34 vctrl avss1p8 -0.82fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_595QY5 a_n269_n100# a_n81_n100# a_111_n100# a_n177_n100#
++ a_15_n100# w_n407_n310# a_207_n100# a_n225_n188#
+X0 a_207_n100# a_n225_n188# a_111_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_n188# a_n81_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n225_n188# a_n177_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_111_n100# a_n225_n188# a_15_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_n188# a_n269_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n269_n100# a_15_n100# 0.06fF
+C1 a_15_n100# a_207_n100# 0.11fF
+C2 a_111_n100# a_15_n100# 0.29fF
+C3 a_n225_n188# a_n81_n100# 0.10fF
+C4 a_n81_n100# a_n177_n100# 0.29fF
+C5 a_n81_n100# a_n269_n100# 0.11fF
+C6 a_n81_n100# a_207_n100# 0.06fF
+C7 a_n225_n188# a_n177_n100# 0.10fF
+C8 a_111_n100# a_n81_n100# 0.11fF
+C9 a_n177_n100# a_n269_n100# 0.29fF
+C10 a_n225_n188# a_111_n100# 0.10fF
+C11 a_n81_n100# a_15_n100# 0.29fF
+C12 a_n177_n100# a_207_n100# 0.05fF
+C13 a_111_n100# a_n177_n100# 0.06fF
+C14 a_111_n100# a_n269_n100# 0.05fF
+C15 a_n225_n188# a_15_n100# 0.10fF
+C16 a_111_n100# a_207_n100# 0.29fF
+C17 a_n177_n100# a_15_n100# 0.11fF
+C18 a_207_n100# w_n407_n310# 0.13fF
+C19 a_111_n100# w_n407_n310# 0.08fF
+C20 a_15_n100# w_n407_n310# 0.09fF
+C21 a_n81_n100# w_n407_n310# 0.09fF
+C22 a_n177_n100# w_n407_n310# 0.08fF
+C23 a_n269_n100# w_n407_n310# 0.13fF
+C24 a_n225_n188# w_n407_n310# 0.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_9B2JY7 a_n317_n100# a_n33_n100# a_n225_n100# a_n271_122#
++ a_63_n100# a_n129_n100# w_n455_n310# a_255_n100# a_159_n100#
+X0 a_63_n100# a_n271_122# a_n33_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n271_122# a_n129_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n271_122# a_63_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n271_122# a_159_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n225_n100# a_n271_122# a_n317_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n129_n100# a_n271_122# a_n225_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n33_n100# a_n317_n100# 0.06fF
+C1 a_n33_n100# a_63_n100# 0.29fF
+C2 a_n129_n100# a_159_n100# 0.06fF
+C3 a_159_n100# a_255_n100# 0.29fF
+C4 a_n129_n100# a_n271_122# 0.10fF
+C5 a_159_n100# a_63_n100# 0.29fF
+C6 a_n129_n100# a_n225_n100# 0.29fF
+C7 a_n317_n100# a_n225_n100# 0.29fF
+C8 a_n271_122# a_63_n100# 0.10fF
+C9 a_63_n100# a_n225_n100# 0.06fF
+C10 a_159_n100# a_n33_n100# 0.11fF
+C11 a_n129_n100# a_255_n100# 0.05fF
+C12 a_n271_122# a_n33_n100# 0.10fF
+C13 a_n129_n100# a_n317_n100# 0.11fF
+C14 a_n33_n100# a_n225_n100# 0.11fF
+C15 a_n129_n100# a_63_n100# 0.11fF
+C16 a_63_n100# a_255_n100# 0.11fF
+C17 a_159_n100# a_n271_122# 0.10fF
+C18 a_63_n100# a_n317_n100# 0.05fF
+C19 a_159_n100# a_n225_n100# 0.05fF
+C20 a_n271_122# a_n225_n100# 0.10fF
+C21 a_n129_n100# a_n33_n100# 0.29fF
+C22 a_n33_n100# a_255_n100# 0.06fF
+C23 a_255_n100# w_n455_n310# 0.13fF
+C24 a_159_n100# w_n455_n310# 0.08fF
+C25 a_63_n100# w_n455_n310# 0.07fF
+C26 a_n33_n100# w_n455_n310# 0.08fF
+C27 a_n129_n100# w_n455_n310# 0.07fF
+C28 a_n225_n100# w_n455_n310# 0.08fF
+C29 a_n317_n100# w_n455_n310# 0.13fF
+C30 a_n271_122# w_n455_n310# 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_MVT43V a_n33_n100# w_n263_n310# a_63_n100# a_n79_122#
++ a_n125_n100#
+X0 a_63_n100# a_n79_122# a_n33_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n79_122# a_n125_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_63_n100# a_n125_n100# 0.11fF
+C1 a_n125_n100# a_n33_n100# 0.29fF
+C2 a_n125_n100# a_n79_122# 0.02fF
+C3 a_63_n100# a_n33_n100# 0.29fF
+C4 a_63_n100# a_n79_122# 0.02fF
+C5 a_n33_n100# a_n79_122# 0.11fF
+C6 a_63_n100# w_n263_n310# 0.16fF
+C7 a_n33_n100# w_n263_n310# 0.12fF
+C8 a_n125_n100# w_n263_n310# 0.16fF
+C9 a_n79_122# w_n263_n310# 0.37fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_NMSMYT a_n33_n100# a_n321_n100# a_n225_n100# w_n551_n310#
++ a_63_n100# a_n368_122# a_n129_n100# a_351_n100# a_255_n100# a_n413_n100# a_159_n100#
+X0 a_63_n100# a_n368_122# a_n33_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n368_122# a_n129_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n368_122# a_63_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n368_122# a_159_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_351_n100# a_n368_122# a_255_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n321_n100# a_n368_122# a_n413_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n225_n100# a_n368_122# a_n321_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n129_n100# a_n368_122# a_n225_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n33_n100# a_n368_122# 0.10fF
+C1 a_n129_n100# a_n33_n100# 0.29fF
+C2 a_159_n100# a_351_n100# 0.11fF
+C3 a_n321_n100# a_n33_n100# 0.06fF
+C4 a_63_n100# a_159_n100# 0.29fF
+C5 a_n225_n100# a_n413_n100# 0.11fF
+C6 a_159_n100# a_n368_122# 0.10fF
+C7 a_n129_n100# a_159_n100# 0.06fF
+C8 a_n225_n100# a_63_n100# 0.06fF
+C9 a_255_n100# a_351_n100# 0.29fF
+C10 a_63_n100# a_255_n100# 0.11fF
+C11 a_n225_n100# a_n368_122# 0.10fF
+C12 a_n225_n100# a_n129_n100# 0.29fF
+C13 a_255_n100# a_n368_122# 0.10fF
+C14 a_n225_n100# a_n321_n100# 0.29fF
+C15 a_255_n100# a_n129_n100# 0.05fF
+C16 a_159_n100# a_n33_n100# 0.11fF
+C17 a_n225_n100# a_n33_n100# 0.11fF
+C18 a_255_n100# a_n33_n100# 0.06fF
+C19 a_63_n100# a_351_n100# 0.06fF
+C20 a_n225_n100# a_159_n100# 0.05fF
+C21 a_255_n100# a_159_n100# 0.29fF
+C22 a_n129_n100# a_n413_n100# 0.06fF
+C23 a_n321_n100# a_n413_n100# 0.29fF
+C24 a_63_n100# a_n368_122# 0.10fF
+C25 a_63_n100# a_n129_n100# 0.11fF
+C26 a_63_n100# a_n321_n100# 0.05fF
+C27 a_n129_n100# a_n368_122# 0.10fF
+C28 a_n33_n100# a_n413_n100# 0.05fF
+C29 a_n321_n100# a_n368_122# 0.10fF
+C30 a_n321_n100# a_n129_n100# 0.11fF
+C31 a_n33_n100# a_351_n100# 0.05fF
+C32 a_63_n100# a_n33_n100# 0.29fF
+C33 a_351_n100# w_n551_n310# 0.13fF
+C34 a_255_n100# w_n551_n310# 0.08fF
+C35 a_159_n100# w_n551_n310# 0.07fF
+C36 a_63_n100# w_n551_n310# 0.06fF
+C37 a_n33_n100# w_n551_n310# 0.04fF
+C38 a_n129_n100# w_n551_n310# 0.06fF
+C39 a_n225_n100# w_n551_n310# 0.07fF
+C40 a_n321_n100# w_n551_n310# 0.08fF
+C41 a_n413_n100# w_n551_n310# 0.13fF
+C42 a_n368_122# w_n551_n310# 1.26fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XAYTAL VSUBS w_n311_n319# a_n81_n100# a_n129_n197#
++ a_111_n100# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_n197# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_n197# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_n197# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n129_n197# w_n311_n319# 0.17fF
+C1 a_15_n100# a_111_n100# 0.29fF
+C2 a_15_n100# w_n311_n319# 0.08fF
+C3 a_n173_n100# a_15_n100# 0.11fF
+C4 a_111_n100# a_n81_n100# 0.11fF
+C5 w_n311_n319# a_n81_n100# 0.08fF
+C6 a_15_n100# a_n129_n197# 0.08fF
+C7 a_n173_n100# a_n81_n100# 0.29fF
+C8 a_n129_n197# a_n81_n100# 0.08fF
+C9 a_111_n100# w_n311_n319# 0.12fF
+C10 a_n173_n100# a_111_n100# 0.06fF
+C11 a_n173_n100# w_n311_n319# 0.12fF
+C12 a_15_n100# a_n81_n100# 0.29fF
+C13 a_111_n100# VSUBS 0.03fF
+C14 a_15_n100# VSUBS 0.03fF
+C15 a_n81_n100# VSUBS 0.03fF
+C16 a_n173_n100# VSUBS 0.03fF
+C17 a_n129_n197# VSUBS 0.34fF
+C18 w_n311_n319# VSUBS 2.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_B2JNY3 a_n33_n100# a_63_n100# a_n221_n100# a_n129_n100#
++ w_n359_n310# a_n176_122# a_159_n100#
+X0 a_63_n100# a_n176_122# a_n33_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n176_122# a_n129_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n176_122# a_63_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n176_122# a_n221_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n129_n100# a_n176_122# 0.10fF
+C1 a_n221_n100# a_n33_n100# 0.11fF
+C2 a_63_n100# a_159_n100# 0.29fF
+C3 a_n33_n100# a_n176_122# 0.10fF
+C4 a_n129_n100# a_63_n100# 0.11fF
+C5 a_n129_n100# a_159_n100# 0.06fF
+C6 a_63_n100# a_n33_n100# 0.29fF
+C7 a_n33_n100# a_159_n100# 0.11fF
+C8 a_n129_n100# a_n33_n100# 0.29fF
+C9 a_63_n100# a_n221_n100# 0.06fF
+C10 a_n221_n100# a_159_n100# 0.05fF
+C11 a_63_n100# a_n176_122# 0.10fF
+C12 a_n129_n100# a_n221_n100# 0.29fF
+C13 a_159_n100# w_n359_n310# 0.13fF
+C14 a_63_n100# w_n359_n310# 0.10fF
+C15 a_n33_n100# w_n359_n310# 0.10fF
+C16 a_n129_n100# w_n359_n310# 0.10fF
+C17 a_n221_n100# w_n359_n310# 0.13fF
+C18 a_n176_122# w_n359_n310# 0.64fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XACJHL VSUBS a_n81_n197# w_n263_n319# a_n33_n100#
++ a_63_n100# a_n125_n100#
+X0 a_63_n100# a_n81_n197# a_n33_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_n197# a_n125_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 w_n263_n319# a_63_n100# 0.13fF
+C1 a_n33_n100# a_n81_n197# 0.08fF
+C2 a_n33_n100# a_n125_n100# 0.29fF
+C3 a_n81_n197# w_n263_n319# 0.11fF
+C4 a_63_n100# a_n125_n100# 0.11fF
+C5 w_n263_n319# a_n125_n100# 0.13fF
+C6 a_n33_n100# a_63_n100# 0.29fF
+C7 a_n33_n100# w_n263_n319# 0.09fF
+C8 a_63_n100# VSUBS 0.03fF
+C9 a_n33_n100# VSUBS 0.03fF
+C10 a_n125_n100# VSUBS 0.03fF
+C11 a_n81_n197# VSUBS 0.23fF
+C12 w_n263_n319# VSUBS 2.05fF
+.ends
+
+.subckt iref_ctrl_res_amp m1_n356_n363# avss1p8 vctrl reg2 avdd1p8 reg0 m1_1996_n363#
++ reg1 iref m1_964_n363# m1_511_801# m1_1384_n363#
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 iref m1_n356_n363# m1_n356_n363# iref iref iref
++ avss1p8 iref m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_n356_n363# m1_n356_n363# avdd1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_0 m1_964_n363# avss1p8 vctrl iref vctrl sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_1 m1_964_n363# avss1p8 avss1p8 reg0 avss1p8 sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_0 vctrl m1_1996_n363# vctrl avss1p8 m1_1996_n363#
++ iref m1_1996_n363# vctrl m1_1996_n363# vctrl vctrl sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_1 avss1p8 m1_1996_n363# avss1p8 avss1p8 m1_1996_n363#
++ reg2 m1_1996_n363# avss1p8 m1_1996_n363# avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 m1_448_n363# avss1p8 iref m1_448_n363# vctrl
++ vctrl sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 m1_448_n363# avss1p8 avdd1p8 m1_448_n363# avss1p8
++ avss1p8 sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__pfet_01v8_XAYTAL_0 avss1p8 avdd1p8 m1_511_801# avss1p8 m1_511_801#
++ avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8_XAYTAL
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_0 vctrl m1_1384_n363# vctrl m1_1384_n363# avss1p8
++ iref vctrl sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_1 avss1p8 m1_1384_n363# avss1p8 m1_1384_n363#
++ avss1p8 reg1 avss1p8 sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__pfet_01v8_XACJHL_0 avss1p8 vctrl avdd1p8 m1_511_801# vctrl vctrl sky130_fd_pr__pfet_01v8_XACJHL
+C0 reg1 vctrl 0.06fF
+C1 iref avdd1p8 0.32fF
+C2 iref m1_n356_n363# 1.89fF
+C3 iref vctrl 2.27fF
+C4 reg0 m1_964_n363# 0.47fF
+C5 m1_1384_n363# vctrl 0.95fF
+C6 reg2 reg1 0.04fF
+C7 m1_1996_n363# vctrl 1.72fF
+C8 reg2 iref 0.03fF
+C9 reg0 avdd1p8 0.03fF
+C10 reg0 vctrl 0.04fF
+C11 iref m1_448_n363# 0.29fF
+C12 iref reg1 0.03fF
+C13 m1_511_801# avdd1p8 1.05fF
+C14 m1_511_801# vctrl 1.08fF
+C15 m1_1996_n363# reg2 1.30fF
+C16 m1_1384_n363# reg1 0.85fF
+C17 iref m1_1384_n363# 0.22fF
+C18 m1_964_n363# vctrl 0.52fF
+C19 m1_1996_n363# reg1 0.06fF
+C20 m1_1996_n363# iref 0.41fF
+C21 reg0 reg1 0.04fF
+C22 reg0 iref 0.02fF
+C23 avdd1p8 m1_n356_n363# 1.41fF
+C24 avdd1p8 vctrl 0.52fF
+C25 m1_n356_n363# vctrl 0.08fF
+C26 m1_1996_n363# m1_1384_n363# 0.18fF
+C27 reg0 m1_1384_n363# 0.06fF
+C28 m1_511_801# iref 0.05fF
+C29 m1_448_n363# m1_964_n363# 0.24fF
+C30 iref m1_964_n363# 0.11fF
+C31 reg2 vctrl 0.07fF
+C32 avdd1p8 m1_448_n363# 0.77fF
+C33 m1_448_n363# m1_n356_n363# 0.17fF
+C34 m1_448_n363# vctrl 1.16fF
+C35 m1_1384_n363# m1_964_n363# 0.18fF
+C36 m1_511_801# avss1p8 -1.62fF
+C37 m1_1384_n363# avss1p8 1.30fF
+C38 reg1 avss1p8 1.36fF
+C39 m1_448_n363# avss1p8 -0.27fF
+C40 vctrl avss1p8 2.17fF
+C41 m1_1996_n363# avss1p8 -0.61fF
+C42 reg2 avss1p8 1.98fF
+C43 reg0 avss1p8 0.44fF
+C44 m1_964_n363# avss1p8 -0.38fF
+C45 avdd1p8 avss1p8 6.02fF
+C46 m1_n356_n363# avss1p8 1.89fF
+C47 iref avss1p8 2.30fF
+.ends
+
+.subckt res_amp_lin_prog delay_cell_buff_0/mux_2to1_logic_0/out iref_ctrl_res_amp_0/m1_964_n363#
++ delay_reg2 avdd1p8 inp delay_cell_buff_0/mux_2to1_logic_3/DinA delay_cell_buff_0/mux_2to1_logic_3/out
++ res_amp_lin_0/vctrl iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_0/clk delay_cell_buff_0/nand_logic_0/in1
++ outp_cap avss1p8 outn_cap clk delay_cell_buff_0/mux_2to1_logic_1/sel_b delay_reg0
++ delay_cell_buff_0/mux_2to1_logic_4/DinA delay_cell_buff_0/mux_2to1_logic_4/DinB
++ outn delay_cell_buff_0/mux_2to1_logic_1/DinA outp delay_cell_buff_0/mux_2to1_logic_5/out
++ delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in delay_cell_buff_0/mux_2to1_logic_3/DinB
++ iref_reg0 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in iref_reg1 iref_reg2
++ iref_ctrl_res_amp_0/m1_1384_n363# delay_cell_buff_0/buffer_no_inv_x05_3/in res_amp_lin_0/vp
++ delay_cell_buff_0/nand_logic_0/m1_21_n341# delay_cell_buff_0/mux_2to1_logic_1/out
++ delay_cell_buff_0/mux_2to1_logic_2/out delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ iref delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in iref_ctrl_res_amp_0/m1_n356_n363#
++ res_amp_lin_0/a_3747_261# delay_reg1 delay_cell_buff_0/buffer_no_inv_x05_13/in inn
++ delay_cell_buff_0/mux_2to1_logic_4/out iref_ctrl_res_amp_0/m1_1996_n363# delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in
++ inverter_min_x4_0/out delay_cell_buff_0/mux_2to1_logic_4/sel_b rst
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_0 avss1p8 outn_cap avdd1p8 outn_cap res_amp_lin_0/clk
++ outn outn outn outn_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_1 avss1p8 outp_cap avdd1p8 outp_cap res_amp_lin_0/clk
++ outp outp outp outp_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xdelay_cell_buff_0 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in delay_reg2
++ avss1p8 delay_cell_buff_0/mux_2to1_logic_4/DinA avdd1p8 delay_cell_buff_0/buffer_no_inv_x05_13/in
++ clk delay_cell_buff_0/mux_2to1_logic_3/DinA res_amp_lin_0/clk delay_cell_buff_0/mux_2to1_logic_3/DinB
++ delay_reg0 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in delay_reg1 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ delay_cell_buff_0/nand_logic_0/in1 delay_cell_buff_0/mux_2to1_logic_2/out delay_cell_buff_0/mux_2to1_logic_4/sel_b
++ delay_cell_buff_0/mux_2to1_logic_4/out delay_cell_buff_0/mux_2to1_logic_1/DinA delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ delay_cell_buff_0/buffer_no_inv_x05_3/in delay_cell_buff_0/mux_2to1_logic_5/out
++ delay_cell_buff_0/mux_2to1_logic_0/out delay_cell_buff_0/mux_2to1_logic_4/DinB delay_cell_buff_0/mux_2to1_logic_3/out
++ delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in delay_cell_buff_0/mux_2to1_logic_1/out
++ avss1p8 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ delay_cell_buff
+Xinverter_min_x4_0 avdd1p8 res_amp_lin_0/clk avss1p8 inverter_min_x4_0/out inverter_min_x4
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 outn_cap avss1p8 rst outn_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xres_amp_lin_0 res_amp_lin_0/clk res_amp_lin_0/vctrl avdd1p8 avss1p8 res_amp_lin_0/a_3747_261#
++ res_amp_lin_0/vp inn outn outp inp res_amp_lin
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 outp_cap avss1p8 rst outp_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_0 outn outn outn outn_cap outn_cap avss1p8 outn_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_1 outp outp outp outp_cap outp_cap avss1p8 outp_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xiref_ctrl_res_amp_0 iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 res_amp_lin_0/vctrl
++ iref_reg2 avdd1p8 iref_reg0 iref_ctrl_res_amp_0/m1_1996_n363# iref_reg1 iref iref_ctrl_res_amp_0/m1_964_n363#
++ iref_ctrl_res_amp_0/m1_511_801# iref_ctrl_res_amp_0/m1_1384_n363# iref_ctrl_res_amp
+C0 rst outn_cap 0.34fF
+C1 inverter_min_x4_0/out res_amp_lin_0/clk 0.14fF
+C2 outp_cap avdd1p8 0.25fF
+C3 iref res_amp_lin_0/vctrl 0.10fF
+C4 outn res_amp_lin_0/clk 0.09fF
+C5 outp_cap outp 1.90fF
+C6 inverter_min_x4_0/out outn_cap 0.57fF
+C7 outp_cap rst 0.34fF
+C8 outn avdd1p8 0.36fF
+C9 outp inverter_min_x4_0/out 0.32fF
+C10 rst inverter_min_x4_0/out 0.01fF
+C11 outn outn_cap 1.90fF
+C12 outp_cap inverter_min_x4_0/out 0.57fF
+C13 res_amp_lin_0/clk avdd1p8 1.99fF
+C14 outn_cap res_amp_lin_0/clk 1.04fF
+C15 outp res_amp_lin_0/clk 0.09fF
+C16 outn_cap avdd1p8 0.26fF
+C17 outn inverter_min_x4_0/out 0.32fF
+C18 outp avdd1p8 0.34fF
+C19 outp_cap res_amp_lin_0/clk 1.04fF
+C20 res_amp_lin_0/vctrl avdd1p8 1.42fF
+C21 iref_ctrl_res_amp_0/m1_511_801# avss1p8 -1.87fF
+C22 iref_ctrl_res_amp_0/m1_1384_n363# avss1p8 0.47fF
+C23 iref_reg1 avss1p8 0.47fF
+C24 iref_ctrl_res_amp_0/m1_448_n363# avss1p8 -1.10fF
+C25 res_amp_lin_0/vctrl avss1p8 -1.88fF
+C26 iref_ctrl_res_amp_0/m1_1996_n363# avss1p8 -2.23fF
+C27 iref_reg2 avss1p8 -0.15fF
+C28 iref_reg0 avss1p8 -0.42fF
+C29 iref_ctrl_res_amp_0/m1_964_n363# avss1p8 -1.03fF
+C30 iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 0.51fF
+C31 iref avss1p8 0.07fF
+C32 outn avss1p8 1.87fF
+C33 inp avss1p8 -0.35fF
+C34 outp avss1p8 -4.58fF
+C35 res_amp_lin_0/vp avss1p8 -4.89fF
+C36 inn avss1p8 0.17fF
+C37 res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
+C38 outn_cap avss1p8 -1.33fF
+C39 rst avss1p8 0.58fF
+C40 res_amp_lin_0/clk avss1p8 5.34fF
+C41 inverter_min_x4_0/out avss1p8 7.53fF
+C42 delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
+C43 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C44 delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C45 delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C46 delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C47 delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C48 delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C49 delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C50 delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C51 delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C52 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C53 clk avss1p8 -4.09fF
+C54 delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C55 delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C56 delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C57 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C58 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C59 delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C60 delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C61 delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C62 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
+C63 delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C64 delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
+C65 delay_reg0 avss1p8 2.77fF
+C66 delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C67 delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
+C68 delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
+C69 delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C70 delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
+C71 delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C72 delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C73 delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C74 delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C75 delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
+C76 delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C77 delay_reg1 avss1p8 3.80fF
+C78 delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
+C79 delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
+C80 delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C81 delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C82 delay_reg2 avss1p8 11.07fF
+C83 avdd1p8 avss1p8 177.60fF
+C84 delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.03fF
+C85 delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C86 delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C87 delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
+C88 delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
+C89 delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
+C90 outp_cap avss1p8 -6.93fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_U5ZKVF VSUBS m3_n700_n850# c1_n600_n750#
+X0 c1_n600_n750# m3_n700_n850# sky130_fd_pr__cap_mim_m3_1 l=7.5e+06u w=5.5e+06u
+C0 m3_n700_n850# c1_n600_n750# 5.48fF
+C1 m3_n700_n850# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_D3F744 VSUBS a_n285_n236# a_355_n236# a_n29_n236#
++ a_n413_n236# a_99_n236# a_n611_n262# a_483_n236# a_n669_n236# w_n807_n384# a_n157_n236#
++ a_n541_n236# a_227_n236# a_611_n236#
+X0 a_n157_n236# a_n611_n262# a_n285_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_611_n236# a_n611_n262# a_483_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_227_n236# a_n611_n262# a_99_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_n285_n236# a_n611_n262# a_n413_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_99_n236# a_n611_n262# a_n29_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X5 a_355_n236# a_n611_n262# a_227_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X6 a_483_n236# a_n611_n262# a_355_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X7 a_n29_n236# a_n611_n262# a_n157_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X8 a_n413_n236# a_n611_n262# a_n541_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X9 a_n541_n236# a_n611_n262# a_n669_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+C0 a_n611_n262# w_n807_n384# 0.60fF
+C1 a_483_n236# a_355_n236# 0.36fF
+C2 a_227_n236# a_483_n236# 0.15fF
+C3 a_n157_n236# a_n29_n236# 0.36fF
+C4 a_99_n236# a_n29_n236# 0.36fF
+C5 a_n157_n236# a_n541_n236# 0.09fF
+C6 a_n413_n236# a_n29_n236# 0.09fF
+C7 a_n413_n236# a_n541_n236# 0.36fF
+C8 a_355_n236# a_n29_n236# 0.09fF
+C9 a_611_n236# w_n807_n384# 0.19fF
+C10 a_227_n236# a_n29_n236# 0.15fF
+C11 a_n285_n236# a_n29_n236# 0.15fF
+C12 a_n285_n236# a_n541_n236# 0.15fF
+C13 a_n157_n236# w_n807_n384# 0.02fF
+C14 a_99_n236# w_n807_n384# 0.02fF
+C15 a_n413_n236# w_n807_n384# 0.06fF
+C16 a_355_n236# w_n807_n384# 0.06fF
+C17 a_227_n236# w_n807_n384# 0.02fF
+C18 a_n285_n236# w_n807_n384# 0.02fF
+C19 a_n413_n236# a_n669_n236# 0.15fF
+C20 a_483_n236# w_n807_n384# 0.09fF
+C21 a_n669_n236# a_n285_n236# 0.09fF
+C22 a_n157_n236# a_n611_n262# 0.08fF
+C23 a_n611_n262# a_99_n236# 0.08fF
+C24 a_n413_n236# a_n611_n262# 0.08fF
+C25 a_n611_n262# a_355_n236# 0.08fF
+C26 a_227_n236# a_n611_n262# 0.08fF
+C27 a_n285_n236# a_n611_n262# 0.08fF
+C28 a_n29_n236# w_n807_n384# 0.02fF
+C29 a_483_n236# a_n611_n262# 0.08fF
+C30 a_n541_n236# w_n807_n384# 0.09fF
+C31 a_n669_n236# a_n541_n236# 0.36fF
+C32 a_355_n236# a_611_n236# 0.15fF
+C33 a_227_n236# a_611_n236# 0.09fF
+C34 a_n157_n236# a_99_n236# 0.15fF
+C35 a_n413_n236# a_n157_n236# 0.15fF
+C36 a_n611_n262# a_n29_n236# 0.08fF
+C37 a_n611_n262# a_n541_n236# 0.08fF
+C38 a_355_n236# a_99_n236# 0.15fF
+C39 a_483_n236# a_611_n236# 0.36fF
+C40 a_n669_n236# w_n807_n384# 0.19fF
+C41 a_n157_n236# a_227_n236# 0.09fF
+C42 a_227_n236# a_99_n236# 0.36fF
+C43 a_n157_n236# a_n285_n236# 0.36fF
+C44 a_n285_n236# a_99_n236# 0.09fF
+C45 a_n413_n236# a_n285_n236# 0.36fF
+C46 a_227_n236# a_355_n236# 0.36fF
+C47 a_483_n236# a_99_n236# 0.09fF
+C48 a_611_n236# VSUBS 0.03fF
+C49 a_483_n236# VSUBS 0.03fF
+C50 a_355_n236# VSUBS 0.03fF
+C51 a_227_n236# VSUBS 0.03fF
+C52 a_99_n236# VSUBS 0.03fF
+C53 a_n29_n236# VSUBS 0.03fF
+C54 a_n157_n236# VSUBS 0.03fF
+C55 a_n285_n236# VSUBS 0.03fF
+C56 a_n413_n236# VSUBS 0.03fF
+C57 a_n541_n236# VSUBS 0.03fF
+C58 a_n669_n236# VSUBS 0.03fF
+C59 a_n611_n262# VSUBS 1.37fF
+C60 w_n807_n384# VSUBS 6.11fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_VCU74W VSUBS a_495_n100# a_n81_n100# a_399_n100# a_687_n100#
++ a_n749_n100# a_n273_n100# a_111_n100# a_n177_n100# a_n561_n100# a_15_n100# a_n465_n100#
++ a_n705_n197# a_303_n100# a_n369_n100# w_n887_n319# a_207_n100# a_n657_n100# a_591_n100#
+X0 a_303_n100# a_n705_n197# a_207_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_591_n100# a_n705_n197# a_495_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_207_n100# a_n705_n197# a_111_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_399_n100# a_n705_n197# a_303_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_495_n100# a_n705_n197# a_399_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_687_n100# a_n705_n197# a_591_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n561_n100# a_n705_n197# a_n657_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n465_n100# a_n705_n197# a_n561_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n657_n100# a_n705_n197# a_n749_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n369_n100# a_n705_n197# a_n465_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_15_n100# a_n705_n197# a_n81_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_111_n100# a_n705_n197# a_15_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n273_n100# a_n705_n197# a_n369_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n81_n100# a_n705_n197# a_n177_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n177_n100# a_n705_n197# a_n273_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_303_n100# a_n705_n197# 0.08fF
+C1 a_n177_n100# a_n273_n100# 0.29fF
+C2 a_n81_n100# a_303_n100# 0.05fF
+C3 a_399_n100# a_303_n100# 0.29fF
+C4 a_207_n100# a_495_n100# 0.06fF
+C5 w_n887_n319# a_303_n100# 0.02fF
+C6 a_n465_n100# a_n705_n197# 0.08fF
+C7 a_n465_n100# a_n81_n100# 0.05fF
+C8 a_n465_n100# w_n887_n319# 0.03fF
+C9 a_303_n100# a_15_n100# 0.06fF
+C10 a_n465_n100# a_n657_n100# 0.11fF
+C11 a_n81_n100# a_n705_n197# 0.08fF
+C12 a_399_n100# a_n705_n197# 0.08fF
+C13 w_n887_n319# a_n705_n197# 0.82fF
+C14 a_n81_n100# w_n887_n319# 0.02fF
+C15 a_399_n100# w_n887_n319# 0.03fF
+C16 a_303_n100# a_687_n100# 0.05fF
+C17 a_n657_n100# a_n705_n197# 0.08fF
+C18 w_n887_n319# a_n657_n100# 0.05fF
+C19 a_n705_n197# a_15_n100# 0.08fF
+C20 a_n81_n100# a_15_n100# 0.29fF
+C21 a_111_n100# a_495_n100# 0.05fF
+C22 a_399_n100# a_15_n100# 0.05fF
+C23 a_n465_n100# a_n749_n100# 0.06fF
+C24 w_n887_n319# a_15_n100# 0.02fF
+C25 a_207_n100# a_591_n100# 0.05fF
+C26 a_399_n100# a_687_n100# 0.06fF
+C27 w_n887_n319# a_687_n100# 0.10fF
+C28 a_n465_n100# a_n177_n100# 0.06fF
+C29 w_n887_n319# a_n749_n100# 0.10fF
+C30 a_n561_n100# a_n273_n100# 0.06fF
+C31 a_n657_n100# a_n749_n100# 0.29fF
+C32 a_n705_n197# a_n177_n100# 0.08fF
+C33 a_n81_n100# a_n177_n100# 0.29fF
+C34 w_n887_n319# a_n177_n100# 0.02fF
+C35 a_n369_n100# a_n273_n100# 0.29fF
+C36 a_n177_n100# a_15_n100# 0.11fF
+C37 a_303_n100# a_495_n100# 0.11fF
+C38 a_207_n100# a_111_n100# 0.29fF
+C39 a_n465_n100# a_n561_n100# 0.29fF
+C40 a_n705_n197# a_495_n100# 0.08fF
+C41 a_399_n100# a_495_n100# 0.29fF
+C42 w_n887_n319# a_495_n100# 0.04fF
+C43 a_n465_n100# a_n369_n100# 0.29fF
+C44 a_n705_n197# a_n561_n100# 0.08fF
+C45 w_n887_n319# a_n561_n100# 0.04fF
+C46 a_n657_n100# a_n561_n100# 0.29fF
+C47 a_n705_n197# a_n369_n100# 0.08fF
+C48 a_303_n100# a_591_n100# 0.06fF
+C49 a_n81_n100# a_n369_n100# 0.06fF
+C50 w_n887_n319# a_n369_n100# 0.02fF
+C51 a_687_n100# a_495_n100# 0.11fF
+C52 a_n657_n100# a_n369_n100# 0.06fF
+C53 a_111_n100# a_n273_n100# 0.05fF
+C54 a_n369_n100# a_15_n100# 0.05fF
+C55 a_n705_n197# a_591_n100# 0.08fF
+C56 a_399_n100# a_591_n100# 0.11fF
+C57 a_n561_n100# a_n749_n100# 0.11fF
+C58 w_n887_n319# a_591_n100# 0.05fF
+C59 a_207_n100# a_303_n100# 0.29fF
+C60 a_n369_n100# a_n749_n100# 0.05fF
+C61 a_n177_n100# a_n561_n100# 0.05fF
+C62 a_687_n100# a_591_n100# 0.29fF
+C63 a_207_n100# a_n705_n197# 0.08fF
+C64 a_n369_n100# a_n177_n100# 0.11fF
+C65 a_207_n100# a_n81_n100# 0.06fF
+C66 a_399_n100# a_207_n100# 0.11fF
+C67 a_207_n100# w_n887_n319# 0.02fF
+C68 a_111_n100# a_303_n100# 0.11fF
+C69 a_207_n100# a_15_n100# 0.11fF
+C70 a_111_n100# a_n705_n197# 0.08fF
+C71 a_n81_n100# a_111_n100# 0.11fF
+C72 a_399_n100# a_111_n100# 0.06fF
+C73 a_n465_n100# a_n273_n100# 0.11fF
+C74 w_n887_n319# a_111_n100# 0.02fF
+C75 a_207_n100# a_n177_n100# 0.05fF
+C76 a_111_n100# a_15_n100# 0.29fF
+C77 a_n705_n197# a_n273_n100# 0.08fF
+C78 a_n81_n100# a_n273_n100# 0.11fF
+C79 w_n887_n319# a_n273_n100# 0.02fF
+C80 a_n369_n100# a_n561_n100# 0.11fF
+C81 a_n657_n100# a_n273_n100# 0.05fF
+C82 a_n273_n100# a_15_n100# 0.06fF
+C83 a_591_n100# a_495_n100# 0.29fF
+C84 a_111_n100# a_n177_n100# 0.06fF
+C85 a_687_n100# VSUBS 0.03fF
+C86 a_591_n100# VSUBS 0.03fF
+C87 a_495_n100# VSUBS 0.03fF
+C88 a_399_n100# VSUBS 0.03fF
+C89 a_303_n100# VSUBS 0.03fF
+C90 a_207_n100# VSUBS 0.03fF
+C91 a_111_n100# VSUBS 0.03fF
+C92 a_15_n100# VSUBS 0.03fF
+C93 a_n81_n100# VSUBS 0.03fF
+C94 a_n177_n100# VSUBS 0.03fF
+C95 a_n273_n100# VSUBS 0.03fF
+C96 a_n369_n100# VSUBS 0.03fF
+C97 a_n465_n100# VSUBS 0.03fF
+C98 a_n561_n100# VSUBS 0.03fF
+C99 a_n657_n100# VSUBS 0.03fF
+C100 a_n749_n100# VSUBS 0.03fF
+C101 a_n705_n197# VSUBS 1.60fF
+C102 w_n887_n319# VSUBS 5.82fF
+.ends
+
+.subckt source_follower_buff_pmos m1_957_828# in avss1p8 avdd1p8 out iref
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 avss1p8 iref iref iref avss1p8 avss1p8 avss1p8
++ avss1p8 iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_957_828# m1_957_828# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_957_828# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__pfet_01v8_lvt_D3F744_0 avss1p8 out avss1p8 out avss1p8 avss1p8 in out
++ avss1p8 avdd1p8 avss1p8 out out avss1p8 sky130_fd_pr__pfet_01v8_lvt_D3F744
+Xsky130_fd_pr__pfet_01v8_VCU74W_0 avss1p8 m1_957_828# m1_957_828# avdd1p8 m1_957_828#
++ avdd1p8 m1_957_828# m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# m1_957_828#
++ m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+Xsky130_fd_pr__pfet_01v8_VCU74W_1 avss1p8 out out avdd1p8 out avdd1p8 out out avdd1p8
++ avdd1p8 avdd1p8 out m1_957_828# out avdd1p8 avdd1p8 avdd1p8 out avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+C0 out avdd1p8 3.96fF
+C1 out m1_957_828# 1.52fF
+C2 iref avdd1p8 0.29fF
+C3 in avdd1p8 0.32fF
+C4 m1_957_828# iref 0.88fF
+C5 m1_957_828# in 0.52fF
+C6 out in 1.16fF
+C7 m1_957_828# avdd1p8 1.12fF
+C8 out avss1p8 -1.64fF
+C9 in avss1p8 1.94fF
+C10 avdd1p8 avss1p8 15.90fF
+C11 m1_957_828# avss1p8 -34.25fF
+C12 iref avss1p8 4.22fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CFLRKA a_n993_109# a_n1473_n309# a_63_n309# a_1215_n309#
++ a_1215_109# a_n129_n309# a_735_109# a_1599_109# a_n513_n309# a_255_109# a_n1377_n309#
++ a_n1949_109# a_n1761_n309# a_1119_n309# a_1503_n309# a_n1761_109# a_n417_109# a_n417_n309#
++ a_n1281_109# a_n801_n309# a_351_n309# a_63_109# a_1503_109# a_n1665_n309# a_1023_109#
++ a_1887_109# a_1407_n309# a_543_109# a_n705_n309# a_255_n309# a_1791_n309# a_n1569_109#
++ a_n705_109# a_n1569_n309# a_n1089_109# w_n2087_n519# a_n225_109# a_n609_n309# a_159_n309#
++ a_543_n309# a_1695_n309# a_1311_109# a_831_109# a_1695_109# a_n1857_n309# a_n993_n309#
++ a_n33_109# a_351_109# a_n1857_109# a_447_n309# a_831_n309# a_1599_n309# a_n1377_109#
++ a_n897_n309# a_n897_109# a_n513_109# a_1119_109# a_639_109# a_n33_n309# a_735_n309#
++ a_1887_n309# a_159_109# a_n1665_109# a_n1281_n309# a_1023_n309# a_n1185_109# a_n801_109#
++ a_639_n309# a_n321_109# a_1407_109# a_n321_n309# a_927_109# a_447_109# a_1791_109#
++ a_n1185_n309# a_1311_n309# a_n1905_n87# a_927_n309# a_n609_109# a_n225_n309# a_n1473_109#
++ a_n129_109# a_n1949_n309# a_n1089_n309#
+X0 a_n1569_n309# a_n1905_n87# a_n1665_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n87# a_n993_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_927_n309# a_n1905_n87# a_831_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1023_109# a_n1905_n87# a_927_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_255_n309# a_n1905_n87# a_159_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n87# a_1119_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_927_109# a_n1905_n87# a_831_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n1857_n309# a_n1905_n87# a_n1949_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n321_n309# a_n1905_n87# a_n417_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n1761_109# a_n1905_n87# a_n1857_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_543_n309# a_n1905_n87# a_447_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_1503_n309# a_n1905_n87# a_1407_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n1857_109# a_n1905_n87# a_n1949_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n1665_109# a_n1905_n87# a_n1761_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1569_109# a_n1905_n87# a_n1665_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1215_109# a_n1905_n87# a_1119_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_1311_109# a_n1905_n87# a_1215_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_1503_109# a_n1905_n87# a_1407_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_1791_109# a_n1905_n87# a_1695_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n87# a_n1281_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_1119_109# a_n1905_n87# a_1023_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1407_109# a_n1905_n87# a_1311_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_1599_109# a_n1905_n87# a_1503_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1695_109# a_n1905_n87# a_1599_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1887_109# a_n1905_n87# a_1791_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_n1473_n309# a_n1905_n87# a_n1569_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_831_n309# a_n1905_n87# a_735_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1791_n309# a_n1905_n87# a_1695_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n33_109# a_n1905_n87# a_n129_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_351_109# a_n1905_n87# a_255_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_159_n309# a_n1905_n87# a_63_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1119_n309# a_n1905_n87# a_1023_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_159_109# a_n1905_n87# a_63_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_255_109# a_n1905_n87# a_159_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_447_109# a_n1905_n87# a_351_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_543_109# a_n1905_n87# a_447_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_735_109# a_n1905_n87# a_639_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_831_109# a_n1905_n87# a_735_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n225_n309# a_n1905_n87# a_n321_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_639_109# a_n1905_n87# a_543_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_447_n309# a_n1905_n87# a_351_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_1407_n309# a_n1905_n87# a_1311_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_n1473_109# a_n1905_n87# a_n1569_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_n1281_109# a_n1905_n87# a_n1377_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_n1185_109# a_n1905_n87# a_n1281_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_n993_109# a_n1905_n87# a_n1089_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_n1089_n309# a_n1905_n87# a_n1185_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n1377_109# a_n1905_n87# a_n1473_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n1089_109# a_n1905_n87# a_n1185_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_n321_109# a_n1905_n87# a_n417_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n513_n309# a_n1905_n87# a_n609_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_63_n309# a_n1905_n87# a_n33_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_n801_109# a_n1905_n87# a_n897_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_n705_109# a_n1905_n87# a_n801_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_n513_109# a_n1905_n87# a_n609_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_n417_109# a_n1905_n87# a_n513_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n225_109# a_n1905_n87# a_n321_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n129_109# a_n1905_n87# a_n225_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n1377_n309# a_n1905_n87# a_n1473_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_735_n309# a_n1905_n87# a_639_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_1695_n309# a_n1905_n87# a_1599_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n897_109# a_n1905_n87# a_n993_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n609_109# a_n1905_n87# a_n705_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n801_n309# a_n1905_n87# a_n897_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n129_n309# a_n1905_n87# a_n225_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n1761_n309# a_n1905_n87# a_n1857_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n417_n309# a_n1905_n87# a_n513_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_109# a_n1905_n87# a_n33_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_639_n309# a_n1905_n87# a_543_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_1599_n309# a_n1905_n87# a_1503_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n705_n309# a_n1905_n87# a_n801_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1887_n309# a_n1905_n87# a_1791_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n1665_n309# a_n1905_n87# a_n1761_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_1023_n309# a_n1905_n87# a_927_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n993_n309# a_n1905_n87# a_n1089_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_n33_n309# a_n1905_n87# a_n129_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_351_n309# a_n1905_n87# a_255_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_1311_n309# a_n1905_n87# a_1215_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n1281_n309# a_n1905_n87# a_n1377_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_n609_n309# a_n1905_n87# a_n705_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n1089_109# a_n1473_109# 0.05fF
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+C3 a_1407_109# a_1407_n309# 0.01fF
+C4 a_543_109# a_543_n309# 0.01fF
+C5 a_1503_109# a_1695_109# 0.11fF
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+C8 a_n993_n309# a_n801_n309# 0.11fF
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+C10 a_n609_n309# a_n513_n309# 0.29fF
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+C18 a_n993_n309# a_n705_n309# 0.06fF
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+C256 a_n1569_109# a_n1569_n309# 0.01fF
+C257 a_1119_109# a_1215_109# 0.29fF
+C258 a_n1857_n309# a_n1665_n309# 0.11fF
+C259 a_n1761_n309# a_n1949_n309# 0.11fF
+C260 a_n1281_n309# a_n1569_n309# 0.06fF
+C261 a_255_n309# a_63_n309# 0.11fF
+C262 a_n1949_n309# a_n1569_n309# 0.05fF
+C263 a_n33_109# a_n417_109# 0.05fF
+C264 a_159_109# a_n129_109# 0.06fF
+C265 a_n897_n309# a_n609_n309# 0.06fF
+C266 a_927_109# a_735_109# 0.11fF
+C267 a_n33_n309# a_63_n309# 0.29fF
+C268 a_447_109# a_447_n309# 0.01fF
+C269 a_351_n309# a_63_n309# 0.06fF
+C270 a_351_109# a_n33_109# 0.05fF
+C271 a_n1761_109# a_n1665_109# 0.29fF
+C272 a_1599_n309# a_1215_n309# 0.05fF
+C273 a_n1281_109# a_n1665_109# 0.05fF
+C274 a_n1185_109# a_n1569_109# 0.05fF
+C275 a_831_109# a_639_109# 0.11fF
+C276 a_n321_109# a_n33_109# 0.06fF
+C277 a_639_n309# a_447_n309# 0.11fF
+C278 a_n129_n309# a_n417_n309# 0.06fF
+C279 a_735_n309# a_735_109# 0.01fF
+C280 a_1119_109# a_735_109# 0.05fF
+C281 a_831_n309# a_639_n309# 0.11fF
+C282 a_831_n309# a_447_n309# 0.05fF
+C283 a_n129_n309# a_n321_n309# 0.11fF
+C284 a_n1857_109# a_n1857_n309# 0.01fF
+C285 a_159_n309# a_159_109# 0.01fF
+C286 a_n609_n309# a_n801_n309# 0.11fF
+C287 a_255_109# a_351_109# 0.29fF
+C288 a_1119_n309# a_927_n309# 0.11fF
+C289 a_639_n309# a_255_n309# 0.05fF
+C290 a_255_n309# a_447_n309# 0.11fF
+C291 a_n1377_n309# a_n1089_n309# 0.06fF
+C292 a_159_n309# a_63_n309# 0.29fF
+C293 a_1119_109# a_1407_109# 0.06fF
+C294 a_1023_n309# a_1023_109# 0.01fF
+C295 a_543_109# a_639_109# 0.29fF
+C296 a_n897_n309# a_n1089_n309# 0.11fF
+C297 a_n1761_109# a_n1949_109# 0.11fF
+C298 a_n609_n309# a_n705_n309# 0.29fF
+C299 a_n1665_109# a_n1473_109# 0.11fF
+C300 a_n897_n309# a_n897_109# 0.01fF
+C301 a_1311_109# a_1023_109# 0.06fF
+C302 a_639_n309# a_351_n309# 0.06fF
+C303 a_1023_n309# a_1215_n309# 0.11fF
+C304 a_351_n309# a_447_n309# 0.29fF
+C305 a_n1377_n309# a_n1185_n309# 0.11fF
+C306 a_n1377_n309# a_n1377_109# 0.01fF
+C307 a_n1473_n309# a_n1089_n309# 0.05fF
+C308 a_n897_n309# a_n1185_n309# 0.06fF
+C309 a_n801_109# a_n513_109# 0.06fF
+C310 a_639_n309# a_735_n309# 0.29fF
+C311 a_n609_n309# a_n417_n309# 0.11fF
+C312 a_735_n309# a_447_n309# 0.06fF
+C313 a_1503_n309# a_1599_n309# 0.29fF
+C314 a_n1281_109# a_n897_109# 0.05fF
+C315 a_n1281_109# a_n1089_109# 0.11fF
+C316 a_1311_109# a_1503_109# 0.11fF
+C317 a_n1665_n309# a_n1281_n309# 0.05fF
+C318 a_n1473_n309# a_n1185_n309# 0.06fF
+C319 a_n1377_n309# a_n993_n309# 0.05fF
+C320 a_n321_n309# a_n609_n309# 0.06fF
+C321 a_n1761_109# a_n1377_109# 0.05fF
+C322 a_n1857_n309# a_n1949_n309# 0.29fF
+C323 a_n1665_n309# a_n1949_n309# 0.06fF
+C324 a_n897_n309# a_n993_n309# 0.29fF
+C325 a_n129_n309# a_n513_n309# 0.05fF
+C326 a_1503_n309# a_1215_n309# 0.06fF
+C327 a_1599_109# a_1599_n309# 0.01fF
+C328 a_831_n309# a_735_n309# 0.29fF
+C329 a_n1281_109# a_n1377_109# 0.29fF
+C330 a_n33_n309# a_255_n309# 0.06fF
+C331 a_255_109# a_n33_109# 0.06fF
+C332 a_351_n309# a_255_n309# 0.29fF
+C333 a_927_109# a_1119_109# 0.11fF
+C334 a_n129_n309# a_63_n309# 0.11fF
+C335 a_n33_n309# a_351_n309# 0.05fF
+C336 a_n801_n309# a_n1089_n309# 0.06fF
+C337 a_1503_109# a_1503_n309# 0.01fF
+C338 a_639_109# a_735_109# 0.29fF
+C339 a_n609_109# a_n609_n309# 0.01fF
+C340 a_n225_109# a_n513_109# 0.06fF
+C341 a_159_n309# a_447_n309# 0.06fF
+C342 a_1599_109# a_1503_109# 0.29fF
+C343 a_n801_109# a_n897_109# 0.29fF
+C344 a_735_n309# a_351_n309# 0.05fF
+C345 a_n1089_n309# a_n705_n309# 0.05fF
+C346 a_n1185_n309# a_n801_n309# 0.05fF
+C347 a_n801_109# a_n1089_109# 0.06fF
+C348 a_n801_109# a_n417_109# 0.05fF
+C349 a_1887_n309# w_n2087_n519# 0.12fF
+C350 a_1791_n309# w_n2087_n519# 0.08fF
+C351 a_1695_n309# w_n2087_n519# 0.06fF
+C352 a_1599_n309# w_n2087_n519# 0.06fF
+C353 a_1503_n309# w_n2087_n519# 0.04fF
+C354 a_1407_n309# w_n2087_n519# 0.04fF
+C355 a_1311_n309# w_n2087_n519# 0.04fF
+C356 a_1215_n309# w_n2087_n519# 0.04fF
+C357 a_1119_n309# w_n2087_n519# 0.04fF
+C358 a_1023_n309# w_n2087_n519# 0.04fF
+C359 a_927_n309# w_n2087_n519# 0.04fF
+C360 a_831_n309# w_n2087_n519# 0.04fF
+C361 a_735_n309# w_n2087_n519# 0.04fF
+C362 a_639_n309# w_n2087_n519# 0.04fF
+C363 a_543_n309# w_n2087_n519# 0.04fF
+C364 a_447_n309# w_n2087_n519# 0.04fF
+C365 a_351_n309# w_n2087_n519# 0.04fF
+C366 a_255_n309# w_n2087_n519# 0.04fF
+C367 a_159_n309# w_n2087_n519# 0.04fF
+C368 a_63_n309# w_n2087_n519# 0.04fF
+C369 a_n33_n309# w_n2087_n519# 0.04fF
+C370 a_n129_n309# w_n2087_n519# 0.04fF
+C371 a_n225_n309# w_n2087_n519# 0.04fF
+C372 a_n321_n309# w_n2087_n519# 0.04fF
+C373 a_n417_n309# w_n2087_n519# 0.04fF
+C374 a_n513_n309# w_n2087_n519# 0.04fF
+C375 a_n609_n309# w_n2087_n519# 0.04fF
+C376 a_n705_n309# w_n2087_n519# 0.04fF
+C377 a_n801_n309# w_n2087_n519# 0.04fF
+C378 a_n897_n309# w_n2087_n519# 0.04fF
+C379 a_n993_n309# w_n2087_n519# 0.04fF
+C380 a_n1089_n309# w_n2087_n519# 0.04fF
+C381 a_n1185_n309# w_n2087_n519# 0.04fF
+C382 a_n1281_n309# w_n2087_n519# 0.04fF
+C383 a_n1377_n309# w_n2087_n519# 0.04fF
+C384 a_n1473_n309# w_n2087_n519# 0.04fF
+C385 a_n1569_n309# w_n2087_n519# 0.04fF
+C386 a_n1665_n309# w_n2087_n519# 0.04fF
+C387 a_n1761_n309# w_n2087_n519# 0.04fF
+C388 a_n1857_n309# w_n2087_n519# 0.04fF
+C389 a_n1949_n309# w_n2087_n519# 0.04fF
+C390 a_1887_109# w_n2087_n519# 0.12fF
+C391 a_1791_109# w_n2087_n519# 0.08fF
+C392 a_1695_109# w_n2087_n519# 0.06fF
+C393 a_1599_109# w_n2087_n519# 0.06fF
+C394 a_1503_109# w_n2087_n519# 0.04fF
+C395 a_1407_109# w_n2087_n519# 0.04fF
+C396 a_1311_109# w_n2087_n519# 0.04fF
+C397 a_1215_109# w_n2087_n519# 0.04fF
+C398 a_1119_109# w_n2087_n519# 0.04fF
+C399 a_1023_109# w_n2087_n519# 0.04fF
+C400 a_927_109# w_n2087_n519# 0.04fF
+C401 a_831_109# w_n2087_n519# 0.04fF
+C402 a_735_109# w_n2087_n519# 0.04fF
+C403 a_639_109# w_n2087_n519# 0.04fF
+C404 a_543_109# w_n2087_n519# 0.04fF
+C405 a_447_109# w_n2087_n519# 0.04fF
+C406 a_351_109# w_n2087_n519# 0.04fF
+C407 a_255_109# w_n2087_n519# 0.04fF
+C408 a_159_109# w_n2087_n519# 0.04fF
+C409 a_63_109# w_n2087_n519# 0.04fF
+C410 a_n33_109# w_n2087_n519# 0.04fF
+C411 a_n129_109# w_n2087_n519# 0.04fF
+C412 a_n225_109# w_n2087_n519# 0.04fF
+C413 a_n321_109# w_n2087_n519# 0.04fF
+C414 a_n417_109# w_n2087_n519# 0.04fF
+C415 a_n513_109# w_n2087_n519# 0.04fF
+C416 a_n609_109# w_n2087_n519# 0.04fF
+C417 a_n705_109# w_n2087_n519# 0.04fF
+C418 a_n801_109# w_n2087_n519# 0.04fF
+C419 a_n897_109# w_n2087_n519# 0.04fF
+C420 a_n993_109# w_n2087_n519# 0.04fF
+C421 a_n1089_109# w_n2087_n519# 0.04fF
+C422 a_n1185_109# w_n2087_n519# 0.04fF
+C423 a_n1281_109# w_n2087_n519# 0.04fF
+C424 a_n1377_109# w_n2087_n519# 0.04fF
+C425 a_n1473_109# w_n2087_n519# 0.04fF
+C426 a_n1569_109# w_n2087_n519# 0.04fF
+C427 a_n1665_109# w_n2087_n519# 0.04fF
+C428 a_n1761_109# w_n2087_n519# 0.04fF
+C429 a_n1857_109# w_n2087_n519# 0.04fF
+C430 a_n1949_109# w_n2087_n519# 0.04fF
+C431 a_n1905_n87# w_n2087_n519# 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CAF2P9 a_63_n309# a_n1473_n309# a_159_527# a_1215_n309#
++ a_n993_109# a_1215_109# a_n129_n309# a_n513_n309# a_1599_109# a_735_109# a_n1665_527#
++ a_n1281_n727# a_n801_527# a_1023_n727# a_639_n727# a_255_109# a_n1185_527# a_n1377_n309#
++ a_n1949_109# a_1119_n309# a_n1761_n309# a_n321_527# a_1503_n309# a_1407_527# a_n321_n727#
++ a_927_527# a_n1761_109# a_n417_109# a_n417_n309# a_351_n309# a_n801_n309# a_n1905_n505#
++ a_n1281_109# a_n1185_n727# a_447_527# a_1791_527# a_63_109# a_1311_n727# a_927_n727#
++ a_1503_109# a_n1665_n309# a_1407_n309# a_1887_109# a_n225_n727# a_1023_109# a_n609_527#
++ a_543_109# a_255_n309# a_n1473_527# a_n1949_n727# a_1791_n309# a_n705_n309# a_n129_527#
++ a_n1089_n727# a_n1473_n727# a_1215_n727# a_63_n727# a_n993_527# a_n1569_109# a_n1569_n309#
++ a_n705_109# a_1215_527# a_n129_n727# a_n1089_109# a_1599_527# a_n513_n727# a_735_527#
++ a_n225_109# a_1695_n309# a_159_n309# a_n609_n309# a_543_n309# a_255_527# a_n1377_n727#
++ a_n1949_527# a_1119_n727# a_n1761_n727# a_1503_n727# a_1311_109# a_n993_n309# a_1695_109#
++ a_n1857_n309# a_831_109# a_n1761_527# a_n33_109# a_n417_n727# a_n417_527# a_351_109#
++ a_351_n727# a_n801_n727# a_n1281_527# a_n1857_109# a_1599_n309# a_447_n309# a_63_527#
++ a_831_n309# a_1503_527# a_n1377_109# a_n1665_n727# a_1887_527# a_1407_n727# a_n897_n309#
++ a_1023_527# a_n513_109# a_n897_109# a_543_527# a_1791_n727# a_255_n727# a_n705_n727#
++ a_1119_109# a_1887_n309# a_639_109# a_735_n309# a_n33_n309# a_n1569_527# a_n1569_n727#
++ a_n705_527# a_159_109# a_n1089_527# a_n225_527# w_n2087_n937# a_1695_n727# a_159_n727#
++ a_n609_n727# a_543_n727# a_n1665_109# a_n1281_n309# a_1023_n309# a_1311_527# a_n801_109#
++ a_639_n309# a_1695_527# a_n1185_109# a_n993_n727# a_831_527# a_n1857_n727# a_n321_109#
++ a_1407_109# a_n33_527# a_n321_n309# a_351_527# a_927_109# a_1599_n727# a_n1857_527#
++ a_447_n727# a_831_n727# a_447_109# a_n1185_n309# a_n1377_527# a_1791_109# a_1311_n309#
++ a_n897_n727# a_927_n309# a_n513_527# a_n897_527# a_n225_n309# a_n609_109# a_1119_527#
++ a_1887_n727# a_n1949_n309# a_639_527# a_n1473_109# a_n129_109# a_735_n727# a_n33_n727#
++ a_n1089_n309#
+X0 a_927_n309# a_n1905_n505# a_831_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n505# a_n993_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n1569_n309# a_n1905_n505# a_n1665_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n727# a_n1905_n505# a_n225_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n1761_n727# a_n1905_n505# a_n1857_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n505# a_1119_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_255_n309# a_n1905_n505# a_159_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1023_109# a_n1905_n505# a_927_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n1857_n309# a_n1905_n505# a_n1949_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_927_109# a_n1905_n505# a_831_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_n417_n727# a_n1905_n505# a_n513_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_n321_n309# a_n1905_n505# a_n417_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_1599_n727# a_n1905_n505# a_1503_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_63_527# a_n1905_n505# a_n33_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1761_109# a_n1905_n505# a_n1857_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1503_n309# a_n1905_n505# a_1407_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_639_n727# a_n1905_n505# a_543_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_543_n309# a_n1905_n505# a_447_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_n1665_109# a_n1905_n505# a_n1761_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n505# a_n1281_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_n1569_109# a_n1905_n505# a_n1665_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1311_109# a_n1905_n505# a_1215_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1857_109# a_n1905_n505# a_n1949_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1791_109# a_n1905_n505# a_1695_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1503_109# a_n1905_n505# a_1407_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_1215_109# a_n1905_n505# a_1119_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_n705_n727# a_n1905_n505# a_n801_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1119_109# a_n1905_n505# a_1023_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_1695_109# a_n1905_n505# a_1599_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_1407_109# a_n1905_n505# a_1311_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_1599_109# a_n1905_n505# a_1503_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1887_109# a_n1905_n505# a_1791_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_1887_n727# a_n1905_n505# a_1791_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_1791_n309# a_n1905_n505# a_1695_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_831_n309# a_n1905_n505# a_735_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_n1473_n309# a_n1905_n505# a_n1569_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_n33_109# a_n1905_n505# a_n129_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_1023_n727# a_n1905_n505# a_927_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n1665_n727# a_n1905_n505# a_n1761_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_1119_n309# a_n1905_n505# a_1023_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_159_n309# a_n1905_n505# a_63_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_351_109# a_n1905_n505# a_255_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_1311_n727# a_n1905_n505# a_1215_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_255_109# a_n1905_n505# a_159_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_351_n727# a_n1905_n505# a_255_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_831_109# a_n1905_n505# a_735_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_543_109# a_n1905_n505# a_447_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n33_n727# a_n1905_n505# a_n129_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n993_n727# a_n1905_n505# a_n1089_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_159_109# a_n1905_n505# a_63_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n225_n309# a_n1905_n505# a_n321_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_735_109# a_n1905_n505# a_639_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_447_109# a_n1905_n505# a_351_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_639_109# a_n1905_n505# a_543_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_1407_n309# a_n1905_n505# a_1311_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_447_n309# a_n1905_n505# a_351_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n1089_n309# a_n1905_n505# a_n1185_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n1281_109# a_n1905_n505# a_n1377_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n993_109# a_n1905_n505# a_n1089_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_n1473_109# a_n1905_n505# a_n1569_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_n1185_109# a_n1905_n505# a_n1281_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n609_n727# a_n1905_n505# a_n705_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n1377_109# a_n1905_n505# a_n1473_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n1089_109# a_n1905_n505# a_n1185_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n1281_n727# a_n1905_n505# a_n1377_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n513_n309# a_n1905_n505# a_n609_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n321_109# a_n1905_n505# a_n417_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_n309# a_n1905_n505# a_n33_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_n225_109# a_n1905_n505# a_n321_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_n801_109# a_n1905_n505# a_n897_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n513_109# a_n1905_n505# a_n609_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1695_n309# a_n1905_n505# a_1599_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n705_109# a_n1905_n505# a_n801_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_n417_109# a_n1905_n505# a_n513_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n129_109# a_n1905_n505# a_n225_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_735_n309# a_n1905_n505# a_639_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_n1377_n309# a_n1905_n505# a_n1473_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_n897_109# a_n1905_n505# a_n993_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n609_109# a_n1905_n505# a_n705_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_927_n727# a_n1905_n505# a_831_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X80 a_n1569_n727# a_n1905_n505# a_n1665_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X81 a_n897_n727# a_n1905_n505# a_n993_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X82 a_n801_n309# a_n1905_n505# a_n897_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X83 a_1215_n727# a_n1905_n505# a_1119_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X84 a_255_n727# a_n1905_n505# a_159_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X85 a_1023_527# a_n1905_n505# a_927_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X86 a_n129_n309# a_n1905_n505# a_n225_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X87 a_927_527# a_n1905_n505# a_831_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X88 a_n1857_n727# a_n1905_n505# a_n1949_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X89 a_n1761_n309# a_n1905_n505# a_n1857_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X90 a_n321_n727# a_n1905_n505# a_n417_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X91 a_n1761_527# a_n1905_n505# a_n1857_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X92 a_1503_n727# a_n1905_n505# a_1407_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X93 a_n1665_527# a_n1905_n505# a_n1761_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X94 a_543_n727# a_n1905_n505# a_447_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X95 a_n1185_n727# a_n1905_n505# a_n1281_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X96 a_n417_n309# a_n1905_n505# a_n513_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X97 a_n1857_527# a_n1905_n505# a_n1949_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X98 a_n1569_527# a_n1905_n505# a_n1665_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X99 a_1311_527# a_n1905_n505# a_1215_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X100 a_1215_527# a_n1905_n505# a_1119_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X101 a_1503_527# a_n1905_n505# a_1407_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X102 a_1791_527# a_n1905_n505# a_1695_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X103 a_1119_527# a_n1905_n505# a_1023_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X104 a_1407_527# a_n1905_n505# a_1311_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X105 a_1695_527# a_n1905_n505# a_1599_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X106 a_1599_n309# a_n1905_n505# a_1503_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X107 a_63_109# a_n1905_n505# a_n33_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X108 a_639_n309# a_n1905_n505# a_543_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X109 a_1599_527# a_n1905_n505# a_1503_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X110 a_1887_527# a_n1905_n505# a_1791_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X111 a_1791_n727# a_n1905_n505# a_1695_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X112 a_831_n727# a_n1905_n505# a_735_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X113 a_n1473_n727# a_n1905_n505# a_n1569_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X114 a_n705_n309# a_n1905_n505# a_n801_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X115 a_n33_527# a_n1905_n505# a_n129_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X116 a_1887_n309# a_n1905_n505# a_1791_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X117 a_1119_n727# a_n1905_n505# a_1023_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X118 a_159_n727# a_n1905_n505# a_63_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X119 a_351_527# a_n1905_n505# a_255_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X120 a_1023_n309# a_n1905_n505# a_927_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X121 a_n1665_n309# a_n1905_n505# a_n1761_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X122 a_255_527# a_n1905_n505# a_159_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X123 a_543_527# a_n1905_n505# a_447_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X124 a_831_527# a_n1905_n505# a_735_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X125 a_159_527# a_n1905_n505# a_63_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X126 a_447_527# a_n1905_n505# a_351_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X127 a_n225_n727# a_n1905_n505# a_n321_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X128 a_735_527# a_n1905_n505# a_639_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X129 a_639_527# a_n1905_n505# a_543_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X130 a_1407_n727# a_n1905_n505# a_1311_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X131 a_447_n727# a_n1905_n505# a_351_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X132 a_1311_n309# a_n1905_n505# a_1215_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X133 a_n1089_n727# a_n1905_n505# a_n1185_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X134 a_351_n309# a_n1905_n505# a_255_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X135 a_n33_n309# a_n1905_n505# a_n129_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X136 a_n1281_527# a_n1905_n505# a_n1377_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X137 a_n993_527# a_n1905_n505# a_n1089_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X138 a_n993_n309# a_n1905_n505# a_n1089_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X139 a_n1473_527# a_n1905_n505# a_n1569_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X140 a_n1185_527# a_n1905_n505# a_n1281_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X141 a_n1377_527# a_n1905_n505# a_n1473_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X142 a_n1089_527# a_n1905_n505# a_n1185_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X143 a_n513_n727# a_n1905_n505# a_n609_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X144 a_n321_527# a_n1905_n505# a_n417_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X145 a_63_n727# a_n1905_n505# a_n33_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X146 a_n801_527# a_n1905_n505# a_n897_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X147 a_n513_527# a_n1905_n505# a_n609_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X148 a_n225_527# a_n1905_n505# a_n321_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X149 a_1695_n727# a_n1905_n505# a_1599_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X150 a_735_n727# a_n1905_n505# a_639_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X151 a_n705_527# a_n1905_n505# a_n801_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X152 a_n417_527# a_n1905_n505# a_n513_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X153 a_n129_527# a_n1905_n505# a_n225_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X154 a_n1377_n727# a_n1905_n505# a_n1473_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X155 a_n609_n309# a_n1905_n505# a_n705_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X156 a_n1281_n309# a_n1905_n505# a_n1377_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X157 a_n897_527# a_n1905_n505# a_n993_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X158 a_n609_527# a_n1905_n505# a_n705_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X159 a_n801_n727# a_n1905_n505# a_n897_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n225_n309# a_n609_n309# 0.05fF
+C1 a_n321_527# a_n417_527# 0.29fF
+C2 a_1311_109# a_1503_109# 0.11fF
+C3 a_1311_109# a_1695_109# 0.05fF
+C4 a_n225_n309# a_63_n309# 0.06fF
+C5 a_1599_n727# a_1407_n727# 0.11fF
+C6 a_1215_527# a_1311_527# 0.29fF
+C7 a_639_n727# a_639_n309# 0.01fF
+C8 a_n129_527# a_255_527# 0.05fF
+C9 a_63_109# a_63_527# 0.01fF
+C10 a_n1857_527# a_n1761_527# 0.29fF
+C11 a_1503_n727# a_1503_n309# 0.01fF
+C12 a_543_n727# a_351_n727# 0.11fF
+C13 a_1311_527# a_1503_527# 0.11fF
+C14 a_351_n309# a_255_n309# 0.29fF
+C15 a_n1377_527# a_n993_527# 0.05fF
+C16 a_n1281_n309# a_n1665_n309# 0.05fF
+C17 a_n897_n727# a_n1089_n727# 0.11fF
+C18 a_927_n309# a_831_n309# 0.29fF
+C19 a_n1281_n727# a_n1377_n727# 0.29fF
+C20 a_n33_527# a_n33_109# 0.01fF
+C21 a_n801_n309# a_n705_n309# 0.29fF
+C22 a_159_n309# a_447_n309# 0.06fF
+C23 a_n1569_527# a_n1185_527# 0.05fF
+C24 a_n1569_n727# a_n1569_n309# 0.01fF
+C25 a_n1569_n309# a_n1665_n309# 0.29fF
+C26 a_n801_n309# a_n801_n727# 0.01fF
+C27 a_n1569_527# a_n1949_527# 0.05fF
+C28 a_1791_109# a_1503_109# 0.06fF
+C29 a_1791_109# a_1695_109# 0.29fF
+C30 a_n1473_n309# a_n1473_n727# 0.01fF
+C31 a_n225_109# a_159_109# 0.05fF
+C32 a_63_109# a_n321_109# 0.05fF
+C33 a_1407_n309# a_1407_n727# 0.01fF
+C34 a_n33_527# a_159_527# 0.11fF
+C35 a_1887_n309# a_1791_n309# 0.29fF
+C36 a_n897_n727# a_n1185_n727# 0.06fF
+C37 a_n1761_n309# a_n1377_n309# 0.05fF
+C38 a_735_n727# a_447_n727# 0.06fF
+C39 a_n129_109# a_n513_109# 0.05fF
+C40 a_n321_n309# a_n513_n309# 0.11fF
+C41 a_351_527# a_639_527# 0.06fF
+C42 a_927_527# a_1311_527# 0.05fF
+C43 a_159_n309# a_n33_n309# 0.11fF
+C44 a_n1473_n309# a_n1473_109# 0.01fF
+C45 a_n1857_527# a_n1857_109# 0.01fF
+C46 a_n33_527# a_n417_527# 0.05fF
+C47 a_1119_527# a_831_527# 0.06fF
+C48 a_1695_n309# a_1887_n309# 0.11fF
+C49 a_n801_109# a_n705_109# 0.29fF
+C50 a_n1473_n309# a_n1665_n309# 0.11fF
+C51 a_n1377_n309# a_n1377_109# 0.01fF
+C52 a_n1761_n309# a_n1857_n309# 0.29fF
+C53 a_n417_109# a_n129_109# 0.06fF
+C54 a_1215_109# a_1503_109# 0.06fF
+C55 a_n1569_527# a_n1377_527# 0.11fF
+C56 a_735_n727# a_351_n727# 0.05fF
+C57 a_255_109# a_n129_109# 0.05fF
+C58 a_n609_527# a_n705_527# 0.29fF
+C59 a_n1281_n309# a_n1377_n309# 0.29fF
+C60 a_447_109# a_447_n309# 0.01fF
+C61 a_351_n309# a_735_n309# 0.05fF
+C62 a_1119_n727# a_1407_n727# 0.06fF
+C63 a_n705_n727# a_n321_n727# 0.05fF
+C64 a_735_527# a_735_109# 0.01fF
+C65 a_n609_n309# a_n897_n309# 0.06fF
+C66 a_63_527# a_n321_527# 0.05fF
+C67 a_n801_527# a_n417_527# 0.05fF
+C68 a_n1089_109# a_n1473_109# 0.05fF
+C69 a_1887_n309# a_1887_109# 0.01fF
+C70 a_n1377_n309# a_n1569_n309# 0.11fF
+C71 a_n129_n309# a_n129_109# 0.01fF
+C72 a_1215_n727# a_1023_n727# 0.11fF
+C73 a_1023_n309# a_927_n309# 0.29fF
+C74 a_543_527# a_735_527# 0.11fF
+C75 a_n1761_n309# a_n1761_109# 0.01fF
+C76 a_n1089_527# a_n1185_527# 0.29fF
+C77 a_n609_527# a_n897_527# 0.06fF
+C78 a_n993_527# a_n1281_527# 0.06fF
+C79 a_n33_n309# a_n33_109# 0.01fF
+C80 a_n1569_527# a_n1569_109# 0.01fF
+C81 a_255_n309# a_639_n309# 0.05fF
+C82 a_n321_527# a_n321_109# 0.01fF
+C83 a_1599_109# a_1311_109# 0.06fF
+C84 a_n1761_109# a_n1377_109# 0.05fF
+C85 a_n1665_109# a_n1473_109# 0.11fF
+C86 a_255_n309# a_63_n309# 0.11fF
+C87 a_n1569_n309# a_n1857_n309# 0.06fF
+C88 a_n609_109# a_n609_527# 0.01fF
+C89 a_1695_527# a_1695_109# 0.01fF
+C90 a_543_n727# a_255_n727# 0.06fF
+C91 a_1599_527# a_1791_527# 0.11fF
+C92 a_n1377_527# a_n1185_527# 0.11fF
+C93 a_n1473_n309# a_n1377_n309# 0.29fF
+C94 a_n1185_109# a_n801_109# 0.05fF
+C95 a_n1665_109# a_n1665_n309# 0.01fF
+C96 a_n705_109# a_n513_109# 0.11fF
+C97 a_n417_n309# a_n225_n309# 0.11fF
+C98 a_n321_527# a_n513_527# 0.11fF
+C99 a_n1473_527# a_n1473_109# 0.01fF
+C100 a_n1761_n309# a_n1949_n309# 0.11fF
+C101 a_1503_n727# a_1695_n727# 0.11fF
+C102 a_447_n727# a_351_n727# 0.29fF
+C103 a_n129_n309# a_63_n309# 0.11fF
+C104 a_n1761_n727# a_n1857_n727# 0.29fF
+C105 a_n417_n727# a_n513_n727# 0.29fF
+C106 a_n1089_527# a_n1377_527# 0.06fF
+C107 a_n33_527# a_63_527# 0.29fF
+C108 a_927_n309# a_543_n309# 0.05fF
+C109 a_1599_527# a_1407_527# 0.11fF
+C110 a_1599_109# a_1791_109# 0.11fF
+C111 a_n1473_n309# a_n1857_n309# 0.05fF
+C112 a_n1281_n309# a_n1089_n309# 0.11fF
+C113 a_n417_109# a_n705_109# 0.06fF
+C114 a_n801_109# a_n897_109# 0.29fF
+C115 a_n513_n727# a_n513_n309# 0.01fF
+C116 a_n993_n727# a_n993_n309# 0.01fF
+C117 a_927_527# a_543_527# 0.05fF
+C118 a_831_n727# a_1023_n727# 0.11fF
+C119 a_n1569_527# a_n1281_527# 0.06fF
+C120 a_1695_n727# a_1887_n727# 0.11fF
+C121 a_447_527# a_735_527# 0.06fF
+C122 a_n1089_n309# a_n705_n309# 0.05fF
+C123 a_159_n309# a_543_n309# 0.05fF
+C124 a_1503_527# a_1791_527# 0.06fF
+C125 a_927_527# a_927_109# 0.01fF
+C126 a_n225_109# a_n33_109# 0.11fF
+C127 a_831_n727# a_831_n309# 0.01fF
+C128 a_1407_n309# a_1503_n309# 0.29fF
+C129 a_1599_n309# a_1503_n309# 0.29fF
+C130 a_735_n309# a_639_n309# 0.29fF
+C131 a_n1569_n309# a_n1949_n309# 0.05fF
+C132 a_n705_527# a_n417_527# 0.06fF
+C133 a_n129_527# a_n129_109# 0.01fF
+C134 a_n801_109# a_n993_109# 0.11fF
+C135 a_1695_n309# a_1695_109# 0.01fF
+C136 a_1599_109# a_1215_109# 0.05fF
+C137 a_n321_n309# a_n321_n727# 0.01fF
+C138 a_1215_527# a_1407_527# 0.11fF
+C139 a_159_527# a_351_527# 0.11fF
+C140 a_159_n309# a_159_109# 0.01fF
+C141 a_351_n309# a_639_n309# 0.06fF
+C142 a_n609_n727# a_n609_n309# 0.01fF
+C143 a_1503_527# a_1407_527# 0.29fF
+C144 a_1407_n309# a_1119_n309# 0.06fF
+C145 a_351_n309# a_63_n309# 0.06fF
+C146 a_n1473_n309# a_n1089_n309# 0.05fF
+C147 a_543_n727# a_831_n727# 0.06fF
+C148 a_1215_527# a_1215_109# 0.01fF
+C149 a_1599_527# a_1695_527# 0.29fF
+C150 a_1215_n309# a_1503_n309# 0.06fF
+C151 a_1407_109# a_1311_109# 0.29fF
+C152 a_1119_109# a_735_109# 0.05fF
+C153 a_63_109# a_255_109# 0.11fF
+C154 a_n225_527# a_n321_527# 0.29fF
+C155 a_63_n727# a_63_n309# 0.01fF
+C156 a_n1185_527# a_n1281_527# 0.29fF
+C157 a_n993_n727# a_n1089_n727# 0.29fF
+C158 a_n1569_527# a_n1857_527# 0.06fF
+C159 a_1695_n727# a_1311_n727# 0.05fF
+C160 a_1887_109# a_1503_109# 0.05fF
+C161 a_1887_109# a_1695_109# 0.11fF
+C162 a_1599_109# a_1599_n309# 0.01fF
+C163 a_n801_527# a_n513_527# 0.06fF
+C164 a_n897_109# a_n513_109# 0.05fF
+C165 a_n897_n309# a_n897_109# 0.01fF
+C166 a_n1665_n727# a_n1473_n727# 0.11fF
+C167 a_1119_109# a_927_109# 0.11fF
+C168 a_1215_n309# a_1119_n309# 0.29fF
+C169 a_n1089_527# a_n1281_527# 0.11fF
+C170 a_1791_n309# a_1503_n309# 0.06fF
+C171 a_n1089_n309# a_n1089_109# 0.01fF
+C172 a_1119_109# a_1311_109# 0.11fF
+C173 a_735_527# a_1023_527# 0.06fF
+C174 a_n993_n727# a_n1185_n727# 0.11fF
+C175 a_1119_n727# a_1119_n309# 0.01fF
+C176 a_1407_109# a_1791_109# 0.05fF
+C177 a_n993_109# a_n993_527# 0.01fF
+C178 a_n1665_109# a_n1761_109# 0.29fF
+C179 a_n1473_527# a_n1761_527# 0.06fF
+C180 a_n417_109# a_n417_n309# 0.01fF
+C181 a_447_n727# a_255_n727# 0.11fF
+C182 a_n33_109# a_159_109# 0.11fF
+C183 a_n1185_n309# a_n993_n309# 0.11fF
+C184 a_447_109# a_159_109# 0.06fF
+C185 a_n1569_n727# a_n1665_n727# 0.29fF
+C186 a_1695_n309# a_1503_n309# 0.11fF
+C187 a_1215_527# a_1023_527# 0.11fF
+C188 a_n1665_n727# a_n1665_n309# 0.01fF
+C189 a_1503_527# a_1695_527# 0.11fF
+C190 a_1023_n727# a_1311_n727# 0.06fF
+C191 a_n1377_527# a_n1281_527# 0.29fF
+C192 a_1599_n727# a_1695_n727# 0.29fF
+C193 a_159_527# a_159_109# 0.01fF
+C194 a_n417_n309# a_n129_n309# 0.06fF
+C195 a_735_n727# a_831_n727# 0.29fF
+C196 a_1407_109# a_1407_527# 0.01fF
+C197 a_n33_527# a_n225_527# 0.11fF
+C198 a_n1949_527# a_n1857_527# 0.29fF
+C199 a_351_109# a_351_527# 0.01fF
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+C842 a_n129_109# w_n2087_n937# 0.03fF
+C843 a_n225_109# w_n2087_n937# 0.03fF
+C844 a_n321_109# w_n2087_n937# 0.03fF
+C845 a_n417_109# w_n2087_n937# 0.03fF
+C846 a_n513_109# w_n2087_n937# 0.03fF
+C847 a_n609_109# w_n2087_n937# 0.03fF
+C848 a_n705_109# w_n2087_n937# 0.03fF
+C849 a_n801_109# w_n2087_n937# 0.03fF
+C850 a_n897_109# w_n2087_n937# 0.03fF
+C851 a_n993_109# w_n2087_n937# 0.03fF
+C852 a_n1089_109# w_n2087_n937# 0.03fF
+C853 a_n1185_109# w_n2087_n937# 0.03fF
+C854 a_n1281_109# w_n2087_n937# 0.03fF
+C855 a_n1377_109# w_n2087_n937# 0.03fF
+C856 a_n1473_109# w_n2087_n937# 0.03fF
+C857 a_n1569_109# w_n2087_n937# 0.03fF
+C858 a_n1665_109# w_n2087_n937# 0.03fF
+C859 a_n1761_109# w_n2087_n937# 0.03fF
+C860 a_n1857_109# w_n2087_n937# 0.03fF
+C861 a_n1949_109# w_n2087_n937# 0.03fF
+C862 a_1887_527# w_n2087_n937# 0.12fF
+C863 a_1791_527# w_n2087_n937# 0.08fF
+C864 a_1695_527# w_n2087_n937# 0.06fF
+C865 a_1599_527# w_n2087_n937# 0.06fF
+C866 a_1503_527# w_n2087_n937# 0.04fF
+C867 a_1407_527# w_n2087_n937# 0.04fF
+C868 a_1311_527# w_n2087_n937# 0.04fF
+C869 a_1215_527# w_n2087_n937# 0.04fF
+C870 a_1119_527# w_n2087_n937# 0.04fF
+C871 a_1023_527# w_n2087_n937# 0.04fF
+C872 a_927_527# w_n2087_n937# 0.04fF
+C873 a_831_527# w_n2087_n937# 0.04fF
+C874 a_735_527# w_n2087_n937# 0.04fF
+C875 a_639_527# w_n2087_n937# 0.04fF
+C876 a_543_527# w_n2087_n937# 0.04fF
+C877 a_447_527# w_n2087_n937# 0.04fF
+C878 a_351_527# w_n2087_n937# 0.04fF
+C879 a_255_527# w_n2087_n937# 0.04fF
+C880 a_159_527# w_n2087_n937# 0.04fF
+C881 a_63_527# w_n2087_n937# 0.04fF
+C882 a_n33_527# w_n2087_n937# 0.04fF
+C883 a_n129_527# w_n2087_n937# 0.04fF
+C884 a_n225_527# w_n2087_n937# 0.04fF
+C885 a_n321_527# w_n2087_n937# 0.04fF
+C886 a_n417_527# w_n2087_n937# 0.04fF
+C887 a_n513_527# w_n2087_n937# 0.04fF
+C888 a_n609_527# w_n2087_n937# 0.04fF
+C889 a_n705_527# w_n2087_n937# 0.04fF
+C890 a_n801_527# w_n2087_n937# 0.04fF
+C891 a_n897_527# w_n2087_n937# 0.04fF
+C892 a_n993_527# w_n2087_n937# 0.04fF
+C893 a_n1089_527# w_n2087_n937# 0.04fF
+C894 a_n1185_527# w_n2087_n937# 0.04fF
+C895 a_n1281_527# w_n2087_n937# 0.04fF
+C896 a_n1377_527# w_n2087_n937# 0.04fF
+C897 a_n1473_527# w_n2087_n937# 0.04fF
+C898 a_n1569_527# w_n2087_n937# 0.04fF
+C899 a_n1665_527# w_n2087_n937# 0.04fF
+C900 a_n1761_527# w_n2087_n937# 0.04fF
+C901 a_n1857_527# w_n2087_n937# 0.04fF
+C902 a_n1949_527# w_n2087_n937# 0.04fF
+C903 a_n1905_n505# w_n2087_n937# 14.96fF
+.ends
+
+.subckt source_follower_buff_nmos w_2250_n1147# out avdd1p8 avss1p8 in m1_460_n1129#
++ iref w_2049_850# w_2250_1287# w_2250_355#
+Xsky130_fd_pr__nfet_01v8_lvt_CFLRKA_0 avdd1p8 out out out out out avdd1p8 out out
++ out avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8
++ avdd1p8 out avdd1p8 out out avdd1p8 out avdd1p8 out out out avdd1p8 out avdd1p8
++ out avss1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8 out avdd1p8
++ avdd1p8 avdd1p8 out out out out avdd1p8 out out out avdd1p8 out avdd1p8 avdd1p8
++ avdd1p8 avdd1p8 out out out avdd1p8 avdd1p8 out out out out avdd1p8 out out avdd1p8
++ avdd1p8 in avdd1p8 avdd1p8 avdd1p8 out out avdd1p8 out sky130_fd_pr__nfet_01v8_lvt_CFLRKA
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 m1_460_n1129# iref iref iref m1_460_n1129# m1_460_n1129#
++ avss1p8 m1_460_n1129# iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_460_n1129# m1_460_n1129# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_460_n1129# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_CAF2P9_0 out out avss1p8 out avss1p8 out out out out
++ avss1p8 out out avss1p8 out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out
++ avss1p8 out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 iref out avss1p8
++ out out out avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 out avss1p8 avss1p8
++ out out avss1p8 out out out out out out out avss1p8 avss1p8 avss1p8 out out out
++ out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out out out out avss1p8 avss1p8 out avss1p8
++ out out out out out avss1p8 out out out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8
++ avss1p8 out avss1p8 out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out
++ out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8 out out out out avss1p8 out avss1p8
++ avss1p8 out out out out out avss1p8 avss1p8 out avss1p8 out avss1p8 out out avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out avss1p8 avss1p8 out sky130_fd_pr__nfet_01v8_lvt_CAF2P9
+C0 in out 10.03fF
+C1 iref in 0.11fF
+C2 in avdd1p8 2.17fF
+C3 iref m1_460_n1129# 2.64fF
+C4 iref out 22.08fF
+C5 avdd1p8 out 9.98fF
+C6 iref avss1p8 18.70fF
+C7 in avss1p8 -31.17fF
+C8 out avss1p8 -28.37fF
+C9 m1_460_n1129# avss1p8 2.61fF
+C10 avdd1p8 avss1p8 2.63fF
+.ends
+
+.subckt source_follower_buff_diff outn VSUBS avdd1p8 inp source_follower_buff_pmos_0/m1_957_828#
++ iref1 outp iref2 iref3 iref4 source_follower_buff_nmos_1/m1_460_n1129# source_follower_buff_pmos_1/m1_957_828#
++ source_follower_buff_nmos_0/in source_follower_buff_nmos_0/m1_460_n1129# source_follower_buff_nmos_1/in
++ source_follower_buff_nmos_0/w_2250_355# inn
+Xsource_follower_buff_pmos_0 source_follower_buff_pmos_0/m1_957_828# inn VSUBS avdd1p8
++ source_follower_buff_nmos_0/in iref3 source_follower_buff_pmos
+Xsource_follower_buff_pmos_1 source_follower_buff_pmos_1/m1_957_828# inp VSUBS avdd1p8
++ source_follower_buff_nmos_1/in iref1 source_follower_buff_pmos
+Xsource_follower_buff_nmos_0 source_follower_buff_nmos_0/w_2250_n1147# outn avdd1p8
++ VSUBS source_follower_buff_nmos_0/in source_follower_buff_nmos_0/m1_460_n1129# iref4
++ source_follower_buff_nmos_0/w_2049_850# source_follower_buff_nmos_0/w_2250_1287#
++ source_follower_buff_nmos_0/w_2250_355# source_follower_buff_nmos
+Xsource_follower_buff_nmos_1 source_follower_buff_nmos_1/w_2250_n1147# outp avdd1p8
++ VSUBS source_follower_buff_nmos_1/in source_follower_buff_nmos_1/m1_460_n1129# iref2
++ source_follower_buff_nmos_1/w_2049_850# source_follower_buff_nmos_1/w_2250_1287#
++ source_follower_buff_nmos_1/w_2250_355# source_follower_buff_nmos
+C0 avdd1p8 outn 0.18fF
+C1 inn avdd1p8 0.07fF
+C2 source_follower_buff_nmos_1/in outp 0.11fF
+C3 source_follower_buff_nmos_1/w_2250_n1147# outp 0.09fF
+C4 avdd1p8 source_follower_buff_nmos_0/w_2049_850# 0.16fF
+C5 inp source_follower_buff_pmos_1/m1_957_828# 0.08fF
+C6 avdd1p8 inp 0.07fF
+C7 source_follower_buff_nmos_0/w_2250_1287# avdd1p8 0.18fF
+C8 avdd1p8 source_follower_buff_nmos_1/in 0.63fF
+C9 inp iref1 0.01fF
+C10 inp source_follower_buff_nmos_1/in -0.25fF
+C11 source_follower_buff_nmos_0/in outn 0.11fF
+C12 source_follower_buff_nmos_0/in inn -0.25fF
+C13 source_follower_buff_nmos_0/in avdd1p8 0.63fF
+C14 inn source_follower_buff_pmos_0/m1_957_828# 0.08fF
+C15 inn iref3 0.01fF
+C16 iref2 VSUBS 11.84fF
+C17 source_follower_buff_nmos_1/in VSUBS -32.98fF
+C18 outp VSUBS 0.56fF
+C19 source_follower_buff_nmos_1/m1_460_n1129# VSUBS 1.47fF
+C20 iref4 VSUBS 12.04fF
+C21 source_follower_buff_nmos_0/in VSUBS -32.98fF
+C22 outn VSUBS 2.12fF
+C23 source_follower_buff_nmos_0/m1_460_n1129# VSUBS 1.50fF
+C24 avdd1p8 VSUBS 35.96fF
+C25 inp VSUBS 2.70fF
+C26 source_follower_buff_pmos_1/m1_957_828# VSUBS -35.44fF
+C27 iref1 VSUBS 3.02fF
+C28 inn VSUBS 4.09fF
+C29 source_follower_buff_pmos_0/m1_957_828# VSUBS -35.44fF
+C30 iref3 VSUBS 3.13fF
+.ends
+
+.subckt res_amp_top avss1p8 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ avdd1p8 iref0 res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# iref1 res_amp_lin_prog_0/res_amp_lin_0/vp
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out iref2 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1
++ res_amp_lin_prog_0/outn iref3 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ delay_reg0 iref4 res_amp_lin_prog_0/outp res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB
++ inn source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# inp res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ res_amp_lin_prog_0/res_amp_lin_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA delay_reg2 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out
++ res_amp_lin_prog_0/outp_cap iref_reg0 res_amp_lin_prog_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ source_follower_buff_diff_0/source_follower_buff_nmos_1/in res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA
++ res_amp_sync_v2_0/clkp iref_reg1 source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out iref_reg2 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out
++ res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ delay_reg1 outn source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ outp clkn res_amp_sync_v2_0/rst
+Xres_amp_sync_v2_0 avdd1p8 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 clkn res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280#
++ res_amp_sync_v2_0/DFlipFlop_4/nQ res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D
++ res_amp_sync_v2_0/DFlipFlop_3/Q res_amp_sync_v2_0/DFlipFlop_3/D res_amp_sync_v2_0/DFlipFlop_4/D
++ res_amp_sync_v2_0/DFlipFlop_1/D res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD
++ res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D
++ res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/nQ
++ res_amp_sync_v2_0/clkp res_amp_sync_v2_0/rst res_amp_sync_v2
+Xres_amp_lin_prog_0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363#
++ delay_reg2 avdd1p8 inp res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_prog_0/res_amp_lin_0/clk
++ res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 res_amp_lin_prog_0/outp_cap
++ avss1p8 res_amp_lin_prog_0/outn_cap res_amp_lin_prog_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB
++ res_amp_lin_prog_0/outn res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA
++ res_amp_lin_prog_0/outp res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ iref_reg0 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in
++ iref_reg1 iref_reg2 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ res_amp_lin_prog_0/res_amp_lin_0/vp res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in iref0
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363#
++ res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# delay_reg1 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ inn res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in res_amp_lin_prog_0/inverter_min_x4_0/out
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b res_amp_sync_v2_0/rst
++ res_amp_lin_prog
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_0 avss1p8 avss1p8 res_amp_lin_prog_0/outp_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_1 avss1p8 avss1p8 res_amp_lin_prog_0/outn_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsource_follower_buff_diff_0 outn avss1p8 avdd1p8 res_amp_lin_prog_0/outp_cap source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ iref1 outp iref2 iref3 iref4 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# source_follower_buff_diff_0/source_follower_buff_nmos_1/in
++ source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# res_amp_lin_prog_0/outn_cap
++ source_follower_buff_diff
+C0 res_amp_lin_prog_0/outn_cap res_amp_sync_v2_0/rst 0.06fF
+C1 clkn res_amp_lin_prog_0/clk 0.07fF
+C2 res_amp_sync_v2_0/DFlipFlop_3/D avdd1p8 0.89fF
+C3 avdd1p8 iref0 -0.63fF
+C4 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in res_amp_lin_prog_0/clk 0.48fF
+C5 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# res_amp_lin_prog_0/clk 0.06fF
+C6 avdd1p8 delay_reg2 0.08fF
+C7 res_amp_sync_v2_0/DFlipFlop_3/Q res_amp_lin_prog_0/clk 0.25fF
+C8 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in res_amp_lin_prog_0/clk 0.48fF
+C9 res_amp_sync_v2_0/clkp avdd1p8 1.19fF
+C10 avdd1p8 clkn 0.74fF
+C11 avdd1p8 outp 0.31fF
+C12 delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.04fF
+C13 iref1 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# 0.10fF
+C14 res_amp_sync_v2_0/rst res_amp_lin_prog_0/outp_cap 0.13fF
+C15 avdd1p8 source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.39fF
+C16 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/nQ 0.20fF
+C17 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D res_amp_lin_prog_0/clk 0.47fF
+C18 res_amp_sync_v2_0/rst inp 0.09fF
+C19 avdd1p8 iref_reg1 0.05fF
+C20 iref4 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# 0.13fF
+C21 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D res_amp_lin_prog_0/clk 0.23fF
+C22 avdd1p8 res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.03fF
+C23 avdd1p8 res_amp_lin_prog_0/clk 9.77fF
+C24 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D res_amp_lin_prog_0/clk 0.20fF
+C25 avdd1p8 inp 0.46fF
+C26 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD 0.25fF
+C27 delay_reg1 avdd1p8 0.04fF
+C28 avdd1p8 iref_reg2 -0.57fF
+C29 avdd1p8 res_amp_sync_v2_0/rst 0.80fF
+C30 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# avdd1p8 0.02fF
+C31 res_amp_sync_v2_0/DFlipFlop_4/Q res_amp_lin_prog_0/clk 0.44fF
+C32 res_amp_sync_v2_0/DFlipFlop_4/D res_amp_lin_prog_0/clk 0.08fF
+C33 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out delay_reg2 0.03fF
+C34 outn source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# 0.15fF
+C35 inn inp 1.68fF
+C36 avdd1p8 res_amp_sync_v2_0/DFlipFlop_1/D 0.29fF
+C37 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# iref3 0.10fF
+C38 outn avdd1p8 0.30fF
+C39 res_amp_sync_v2_0/clkp clkn 0.06fF
+C40 res_amp_sync_v2_0/DFlipFlop_3/D res_amp_lin_prog_0/clk 0.07fF
+C41 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D res_amp_lin_prog_0/clk 0.47fF
+C42 res_amp_lin_prog_0/res_amp_lin_0/vctrl iref0 -0.03fF
+C43 res_amp_sync_v2_0/rst inn 0.09fF
+C44 iref0 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.02fF
+C45 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD res_amp_lin_prog_0/clk 0.28fF
+C46 avdd1p8 source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.40fF
+C47 avdd1p8 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# 1.10fF
+C48 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/nQ 0.22fF
+C49 avdd1p8 inn 0.46fF
+C50 avdd1p8 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# 0.02fF
+C51 iref2 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# 0.12fF
+C52 delay_reg1 delay_reg2 0.23fF
+C53 iref2 avss1p8 12.17fF
+C54 source_follower_buff_diff_0/source_follower_buff_nmos_1/in avss1p8 -32.88fF
+C55 outp avss1p8 -1.74fF
+C56 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# avss1p8 1.82fF
+C57 iref4 avss1p8 12.36fF
+C58 source_follower_buff_diff_0/source_follower_buff_nmos_0/in avss1p8 -32.87fF
+C59 source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# avss1p8 0.08fF
+C60 outn avss1p8 -1.13fF
+C61 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# avss1p8 1.84fF
+C62 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# avss1p8 -35.44fF
+C63 iref1 avss1p8 3.33fF
+C64 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# avss1p8 -35.44fF
+C65 iref3 avss1p8 3.02fF
+C66 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# avss1p8 -1.87fF
+C67 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# avss1p8 0.47fF
+C68 iref_reg1 avss1p8 0.41fF
+C69 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# avss1p8 -1.10fF
+C70 res_amp_lin_prog_0/res_amp_lin_0/vctrl avss1p8 -1.99fF
+C71 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# avss1p8 -2.18fF
+C72 iref_reg2 avss1p8 0.06fF
+C73 iref_reg0 avss1p8 -0.21fF
+C74 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# avss1p8 -1.03fF
+C75 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 0.55fF
+C76 iref0 avss1p8 0.37fF
+C77 res_amp_lin_prog_0/outn avss1p8 1.55fF
+C78 inp avss1p8 0.21fF
+C79 res_amp_lin_prog_0/outp avss1p8 -4.89fF
+C80 res_amp_lin_prog_0/res_amp_lin_0/vp avss1p8 -4.89fF
+C81 inn avss1p8 -6.68fF
+C82 res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
+C83 res_amp_lin_prog_0/outn_cap avss1p8 1.00fF
+C84 res_amp_lin_prog_0/res_amp_lin_0/clk avss1p8 4.30fF
+C85 res_amp_lin_prog_0/inverter_min_x4_0/out avss1p8 4.87fF
+C86 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
+C87 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C88 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C89 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C90 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C91 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C92 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C93 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C94 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C95 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C96 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C97 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.04fF
+C98 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C99 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C100 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C101 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C102 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C103 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C104 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C105 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
+C106 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C107 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
+C108 delay_reg0 avss1p8 2.90fF
+C109 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C110 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
+C111 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
+C112 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C113 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
+C114 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C115 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C116 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C117 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C118 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
+C119 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C120 delay_reg1 avss1p8 3.97fF
+C121 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
+C122 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
+C123 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C124 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C125 delay_reg2 avss1p8 11.33fF
+C126 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.04fF
+C127 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C128 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C129 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
+C130 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
+C131 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
+C132 res_amp_lin_prog_0/outp_cap avss1p8 -6.67fF
+C133 res_amp_sync_v2_0/nand_logic_1/m1_21_n341# avss1p8 0.72fF
+C134 res_amp_sync_v2_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C135 res_amp_lin_prog_0/clk avss1p8 -6.90fF
+C136 res_amp_sync_v2_0/inverter_min_x4_4/out avss1p8 5.85fF
+C137 res_amp_sync_v2_0/nand_logic_1/out avss1p8 1.70fF
+C138 res_amp_sync_v2_0/rst avss1p8 -3.03fF
+C139 res_amp_sync_v2_0/DFlipFlop_4/nQ avss1p8 0.48fF
+C140 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 -2.08fF
+C141 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C142 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD avss1p8 0.57fF
+C143 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D avss1p8 -1.73fF
+C144 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C145 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C146 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D avss1p8 0.96fF
+C147 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C148 res_amp_sync_v2_0/DFlipFlop_4/D avss1p8 1.83fF
+C149 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD avss1p8 1.14fF
+C150 res_amp_sync_v2_0/nand_logic_0/out avss1p8 1.20fF
+C151 res_amp_sync_v2_0/DFlipFlop_0/Q avss1p8 -4.73fF
+C152 res_amp_sync_v2_0/DFlipFlop_3/nQ avss1p8 0.48fF
+C153 res_amp_sync_v2_0/DFlipFlop_3/Q avss1p8 -2.94fF
+C154 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C155 clkn avss1p8 -7.50fF
+C156 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD avss1p8 0.57fF
+C157 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D avss1p8 -1.73fF
+C158 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C159 res_amp_sync_v2_0/clkp avss1p8 -28.00fF
+C160 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C161 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D avss1p8 0.96fF
+C162 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C163 res_amp_sync_v2_0/DFlipFlop_3/D avss1p8 1.33fF
+C164 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD avss1p8 1.14fF
+C165 avdd1p8 avss1p8 415.30fF
+C166 res_amp_sync_v2_0/DFlipFlop_2/nQ avss1p8 0.48fF
+C167 res_amp_sync_v2_0/DFlipFlop_2/Q avss1p8 -1.08fF
+C168 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C169 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD avss1p8 0.57fF
+C170 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D avss1p8 -1.73fF
+C171 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C172 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C173 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D avss1p8 0.96fF
+C174 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C175 res_amp_sync_v2_0/DFlipFlop_2/D avss1p8 -0.38fF
+C176 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD avss1p8 1.14fF
+C177 res_amp_sync_v2_0/DFlipFlop_1/nQ avss1p8 0.48fF
+C178 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C179 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD avss1p8 0.57fF
+C180 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D avss1p8 -1.73fF
+C181 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C182 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C183 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D avss1p8 0.96fF
+C184 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C185 res_amp_sync_v2_0/DFlipFlop_1/D avss1p8 -1.02fF
+C186 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD avss1p8 1.14fF
+C187 res_amp_sync_v2_0/DFlipFlop_0/nQ avss1p8 0.48fF
+C188 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C189 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD avss1p8 0.57fF
+C190 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D avss1p8 -1.73fF
+C191 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C192 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C193 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D avss1p8 0.96fF
+C194 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C195 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD avss1p8 1.14fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C1 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C2 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C3 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C4 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C5 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C6 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C7 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C8 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C9 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C10 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C11 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C12 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C13 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C14 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C15 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C16 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C17 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C18 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C19 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C20 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C21 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C22 m3_n7969_2700# m3_n7969_8000# 3.28fF
+C23 m3_n2650_8000# m3_2669_8000# 2.73fF
+C24 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C25 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C26 m3_2669_8000# m3_2669_2700# 3.28fF
+C27 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C28 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C29 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C30 m3_7988_2700# m3_7988_n2600# 3.39fF
+C31 m3_n2650_n2600# m3_n2650_n7900# 3.28fF
+C32 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C33 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
+C34 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C35 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C36 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C37 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C38 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C39 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C40 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C41 m3_2669_n2600# m3_2669_2700# 3.28fF
+C42 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C43 m3_7988_2700# m3_2669_2700# 2.73fF
+C44 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C45 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C46 m3_n2650_2700# m3_2669_2700# 2.73fF
+C47 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C48 m3_2669_8000# m3_7988_8000# 2.73fF
+C49 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C50 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C51 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C52 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C53 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C54 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C55 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C56 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C57 m3_7988_2700# m3_7988_8000# 3.39fF
+C58 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C59 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C60 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C61 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C62 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C63 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C64 m3_n2650_n2600# m3_n2650_2700# 3.28fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C1 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C2 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C3 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C4 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C5 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C6 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C7 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
+C8 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C9 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C10 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C11 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C12 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C13 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C14 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C15 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C16 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C17 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C18 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 out in 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 vc_pex vss -38.13fF
+C2 res_loop_filter_2/out vss 8.49fF
+C3 in vss -18.79fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 w_n2457_n634# a_887_n486# 0.02fF
+C1 w_n2457_n634# a_n29_n486# 0.02fF
+C2 w_n2457_n634# a_2261_n486# 0.02fF
+C3 a_1803_n486# w_n2457_n634# 0.02fF
+C4 w_n2457_n634# a_n1861_n486# 0.02fF
+C5 w_n2457_n634# a_n945_n486# 0.02fF
+C6 w_n2457_n634# a_429_n486# 0.02fF
+C7 w_n2457_n634# a_n487_n486# 0.02fF
+C8 w_n2457_n634# a_n2319_n486# 0.02fF
+C9 w_n2457_n634# a_n1403_n486# 0.02fF
+C10 w_n2457_n634# a_1345_n486# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n1229_n75# a_n1041_n75# 0.08fF
+C1 a_n273_n75# a_n561_n75# 0.05fF
+C2 a_591_n75# a_303_n75# 0.05fF
+C3 a_399_n75# a_495_n75# 0.22fF
+C4 a_n945_n75# a_n657_n75# 0.05fF
+C5 a_n273_n75# a_n369_n75# 0.22fF
+C6 a_n849_n75# a_n753_n75# 0.22fF
+C7 a_111_n75# a_303_n75# 0.08fF
+C8 a_879_n75# a_783_n75# 0.22fF
+C9 a_n177_n75# a_n81_n75# 0.22fF
+C10 a_n657_n75# a_n849_n75# 0.08fF
+C11 a_495_n75# a_591_n75# 0.22fF
+C12 a_n561_n75# a_n369_n75# 0.08fF
+C13 a_783_n75# a_687_n75# 0.22fF
+C14 a_n1137_n75# a_n1041_n75# 0.22fF
+C15 a_n945_n75# a_n1229_n75# 0.05fF
+C16 a_111_n75# a_495_n75# 0.03fF
+C17 a_783_n75# a_399_n75# 0.03fF
+C18 a_975_n75# a_1167_n75# 0.08fF
+C19 a_15_n75# a_207_n75# 0.08fF
+C20 a_n177_n75# a_111_n75# 0.05fF
+C21 a_n849_n75# a_n1229_n75# 0.03fF
+C22 a_n273_n75# a_n177_n75# 0.22fF
+C23 a_783_n75# a_591_n75# 0.08fF
+C24 a_n945_n75# a_n561_n75# 0.03fF
+C25 a_1167_n75# a_1071_n75# 0.22fF
+C26 a_n945_n75# a_n1137_n75# 0.08fF
+C27 a_n945_n75# a_n1041_n75# 0.22fF
+C28 a_15_n75# a_399_n75# 0.03fF
+C29 a_15_n75# a_n81_n75# 0.22fF
+C30 a_975_n75# a_1071_n75# 0.22fF
+C31 a_n177_n75# a_n561_n75# 0.03fF
+C32 a_n753_n75# a_n465_n75# 0.05fF
+C33 a_n177_n75# a_n369_n75# 0.08fF
+C34 a_n849_n75# a_n561_n75# 0.05fF
+C35 a_n1137_n75# a_n849_n75# 0.05fF
+C36 a_n849_n75# a_n1041_n75# 0.08fF
+C37 a_495_n75# a_303_n75# 0.08fF
+C38 a_879_n75# a_687_n75# 0.08fF
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+C40 a_n657_n75# a_n465_n75# 0.08fF
+C41 a_399_n75# a_207_n75# 0.08fF
+C42 a_n81_n75# a_207_n75# 0.05fF
+C43 a_15_n75# a_111_n75# 0.22fF
+C44 a_1167_n75# a_783_n75# 0.03fF
+C45 a_n657_n75# a_n753_n75# 0.22fF
+C46 a_n273_n75# a_15_n75# 0.05fF
+C47 a_207_n75# a_591_n75# 0.03fF
+C48 a_399_n75# a_687_n75# 0.05fF
+C49 a_879_n75# a_591_n75# 0.05fF
+C50 a_975_n75# a_783_n75# 0.08fF
+C51 a_n945_n75# a_n849_n75# 0.22fF
+C52 a_111_n75# a_207_n75# 0.22fF
+C53 a_687_n75# a_591_n75# 0.22fF
+C54 a_n273_n75# a_n465_n75# 0.08fF
+C55 a_15_n75# a_n369_n75# 0.03fF
+C56 a_1071_n75# a_783_n75# 0.05fF
+C57 a_399_n75# a_591_n75# 0.08fF
+C58 a_783_n75# a_495_n75# 0.05fF
+C59 a_n561_n75# a_n465_n75# 0.22fF
+C60 a_n465_n75# a_n369_n75# 0.22fF
+C61 a_111_n75# a_399_n75# 0.05fF
+C62 a_111_n75# a_n81_n75# 0.08fF
+C63 a_15_n75# a_303_n75# 0.05fF
+C64 a_n273_n75# a_n81_n75# 0.08fF
+C65 a_879_n75# a_1167_n75# 0.05fF
+C66 a_n657_n75# a_n273_n75# 0.03fF
+C67 a_n561_n75# a_n753_n75# 0.08fF
+C68 a_975_n75# a_879_n75# 0.22fF
+C69 a_n1137_n75# a_n753_n75# 0.03fF
+C70 a_n753_n75# a_n369_n75# 0.03fF
+C71 a_n753_n75# a_n1041_n75# 0.05fF
+C72 a_207_n75# a_303_n75# 0.22fF
+C73 a_n657_n75# a_n561_n75# 0.22fF
+C74 a_n177_n75# a_15_n75# 0.08fF
+C75 a_975_n75# a_687_n75# 0.05fF
+C76 a_n657_n75# a_n369_n75# 0.05fF
+C77 a_n81_n75# a_n369_n75# 0.05fF
+C78 a_n657_n75# a_n1041_n75# 0.03fF
+C79 a_n273_n75# a_111_n75# 0.03fF
+C80 a_687_n75# a_303_n75# 0.03fF
+C81 a_879_n75# a_1071_n75# 0.08fF
+C82 a_207_n75# a_495_n75# 0.05fF
+C83 a_879_n75# a_495_n75# 0.03fF
+C84 a_n177_n75# a_n465_n75# 0.05fF
+C85 a_399_n75# a_303_n75# 0.22fF
+C86 a_n81_n75# a_303_n75# 0.03fF
+C87 a_n849_n75# a_n465_n75# 0.03fF
+C88 a_n177_n75# a_207_n75# 0.03fF
+C89 a_1071_n75# a_687_n75# 0.03fF
+C90 a_n945_n75# a_n753_n75# 0.08fF
+C91 a_687_n75# a_495_n75# 0.08fF
+C92 a_n1137_n75# a_n1229_n75# 0.22fF
+C93 a_975_n75# a_591_n75# 0.03fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_255_n75# a_n33_n75# 0.05fF
+C1 a_n321_n75# a_n513_n75# 0.08fF
+C2 a_351_n75# a_735_n75# 0.03fF
+C3 a_33_n101# a_n927_n101# 0.08fF
+C4 a_n801_n75# a_n705_n75# 0.22fF
+C5 a_n609_n75# a_n705_n75# 0.22fF
+C6 a_351_n75# a_63_n75# 0.05fF
+C7 a_n129_n75# a_159_n75# 0.05fF
+C8 a_543_n75# a_351_n75# 0.08fF
+C9 a_n513_n75# a_n705_n75# 0.08fF
+C10 a_735_n75# a_831_n75# 0.22fF
+C11 a_n801_n75# a_n417_n75# 0.03fF
+C12 a_n609_n75# a_n225_n75# 0.03fF
+C13 a_n609_n75# a_n417_n75# 0.08fF
+C14 a_n989_n75# a_n801_n75# 0.08fF
+C15 a_n225_n75# a_n513_n75# 0.05fF
+C16 a_n129_n75# a_n321_n75# 0.08fF
+C17 a_n513_n75# a_n417_n75# 0.22fF
+C18 a_543_n75# a_831_n75# 0.05fF
+C19 a_n989_n75# a_n609_n75# 0.03fF
+C20 a_255_n75# a_63_n75# 0.08fF
+C21 a_n33_n75# a_159_n75# 0.08fF
+C22 a_255_n75# a_543_n75# 0.05fF
+C23 a_927_n75# a_735_n75# 0.08fF
+C24 a_447_n75# a_735_n75# 0.05fF
+C25 a_255_n75# a_351_n75# 0.22fF
+C26 a_n129_n75# a_n33_n75# 0.22fF
+C27 a_447_n75# a_63_n75# 0.03fF
+C28 a_n225_n75# a_159_n75# 0.03fF
+C29 a_n897_n75# a_n705_n75# 0.08fF
+C30 a_927_n75# a_543_n75# 0.03fF
+C31 a_n321_n75# a_n33_n75# 0.05fF
+C32 a_543_n75# a_447_n75# 0.22fF
+C33 a_639_n75# a_735_n75# 0.22fF
+C34 a_n321_n75# a_n705_n75# 0.03fF
+C35 a_351_n75# a_447_n75# 0.22fF
+C36 a_n129_n75# a_n225_n75# 0.22fF
+C37 a_n129_n75# a_n417_n75# 0.05fF
+C38 a_n321_n75# a_n225_n75# 0.22fF
+C39 a_543_n75# a_639_n75# 0.22fF
+C40 a_n321_n75# a_n417_n75# 0.22fF
+C41 a_63_n75# a_159_n75# 0.22fF
+C42 a_n897_n75# a_n989_n75# 0.22fF
+C43 a_543_n75# a_159_n75# 0.03fF
+C44 a_927_n75# a_831_n75# 0.22fF
+C45 a_639_n75# a_351_n75# 0.05fF
+C46 a_447_n75# a_831_n75# 0.03fF
+C47 a_n609_n75# a_n801_n75# 0.08fF
+C48 a_n129_n75# a_63_n75# 0.08fF
+C49 a_351_n75# a_159_n75# 0.08fF
+C50 a_n225_n75# a_n33_n75# 0.08fF
+C51 a_255_n75# a_447_n75# 0.08fF
+C52 a_n417_n75# a_n33_n75# 0.03fF
+C53 a_n321_n75# a_63_n75# 0.03fF
+C54 a_n417_n75# a_n705_n75# 0.05fF
+C55 a_n513_n75# a_n801_n75# 0.05fF
+C56 a_n609_n75# a_n513_n75# 0.22fF
+C57 a_639_n75# a_831_n75# 0.08fF
+C58 a_255_n75# a_639_n75# 0.03fF
+C59 a_n989_n75# a_n705_n75# 0.05fF
+C60 a_n225_n75# a_n417_n75# 0.08fF
+C61 a_63_n75# a_n33_n75# 0.22fF
+C62 a_255_n75# a_159_n75# 0.22fF
+C63 a_927_n75# a_639_n75# 0.05fF
+C64 a_639_n75# a_447_n75# 0.08fF
+C65 a_351_n75# a_n33_n75# 0.03fF
+C66 a_n129_n75# a_255_n75# 0.03fF
+C67 a_63_n75# a_n225_n75# 0.05fF
+C68 a_447_n75# a_159_n75# 0.05fF
+C69 a_n897_n75# a_n801_n75# 0.22fF
+C70 a_n897_n75# a_n609_n75# 0.05fF
+C71 a_n321_n75# a_n609_n75# 0.05fF
+C72 a_n897_n75# a_n513_n75# 0.03fF
+C73 a_543_n75# a_735_n75# 0.08fF
+C74 a_n129_n75# a_n513_n75# 0.03fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n225_n150# a_n33_n150# 0.16fF
+C1 a_n417_n150# a_n33_n150# 0.07fF
+C2 a_n417_n150# a_n801_n150# 0.07fF
+C3 a_n129_n150# a_n33_n150# 0.43fF
+C4 a_543_n150# a_735_n150# 0.16fF
+C5 a_n989_n150# a_n705_n150# 0.10fF
+C6 a_543_n150# a_927_n150# 0.07fF
+C7 a_63_n150# a_n321_n150# 0.07fF
+C8 a_n989_n150# a_n801_n150# 0.16fF
+C9 a_n897_n150# a_n705_n150# 0.16fF
+C10 a_n705_n150# a_n513_n150# 0.16fF
+C11 a_n801_n150# a_n897_n150# 0.43fF
+C12 a_n801_n150# a_n513_n150# 0.10fF
+C13 a_159_n150# a_63_n150# 0.43fF
+C14 a_n609_n150# a_n321_n150# 0.10fF
+C15 a_831_n150# a_543_n150# 0.10fF
+C16 a_n927_n247# a_33_n247# 0.09fF
+C17 a_543_n150# a_255_n150# 0.10fF
+C18 a_63_n150# a_n33_n150# 0.43fF
+C19 a_63_n150# a_351_n150# 0.10fF
+C20 a_447_n150# a_159_n150# 0.10fF
+C21 a_639_n150# a_447_n150# 0.16fF
+C22 a_n609_n150# a_n705_n150# 0.43fF
+C23 a_n129_n150# a_255_n150# 0.07fF
+C24 a_n609_n150# a_n801_n150# 0.16fF
+C25 a_447_n150# a_351_n150# 0.43fF
+C26 a_n321_n150# a_n705_n150# 0.07fF
+C27 a_n321_n150# a_n33_n150# 0.10fF
+C28 a_n225_n150# a_n417_n150# 0.16fF
+C29 a_447_n150# a_735_n150# 0.10fF
+C30 a_n225_n150# a_n129_n150# 0.43fF
+C31 a_n417_n150# a_n129_n150# 0.10fF
+C32 a_159_n150# a_n33_n150# 0.16fF
+C33 a_255_n150# a_63_n150# 0.16fF
+C34 a_159_n150# a_351_n150# 0.16fF
+C35 a_639_n150# a_351_n150# 0.10fF
+C36 a_n225_n150# a_n513_n150# 0.10fF
+C37 a_n801_n150# a_n705_n150# 0.43fF
+C38 a_n417_n150# a_n513_n150# 0.43fF
+C39 a_831_n150# a_447_n150# 0.07fF
+C40 a_351_n150# a_n33_n150# 0.07fF
+C41 a_255_n150# a_447_n150# 0.16fF
+C42 a_n129_n150# a_n513_n150# 0.07fF
+C43 a_n989_n150# a_n897_n150# 0.43fF
+C44 a_639_n150# a_735_n150# 0.43fF
+C45 a_n225_n150# a_63_n150# 0.10fF
+C46 a_639_n150# a_927_n150# 0.10fF
+C47 a_n897_n150# a_n513_n150# 0.07fF
+C48 a_543_n150# a_447_n150# 0.43fF
+C49 a_n129_n150# a_63_n150# 0.16fF
+C50 a_735_n150# a_351_n150# 0.07fF
+C51 a_n225_n150# a_n609_n150# 0.07fF
+C52 a_n417_n150# a_n609_n150# 0.16fF
+C53 a_255_n150# a_159_n150# 0.43fF
+C54 a_831_n150# a_639_n150# 0.16fF
+C55 a_639_n150# a_255_n150# 0.07fF
+C56 a_927_n150# a_735_n150# 0.16fF
+C57 a_n609_n150# a_n989_n150# 0.07fF
+C58 a_n225_n150# a_n321_n150# 0.43fF
+C59 a_n417_n150# a_n321_n150# 0.43fF
+C60 a_255_n150# a_n33_n150# 0.10fF
+C61 a_n609_n150# a_n897_n150# 0.10fF
+C62 a_543_n150# a_159_n150# 0.07fF
+C63 a_255_n150# a_351_n150# 0.43fF
+C64 a_n609_n150# a_n513_n150# 0.43fF
+C65 a_n129_n150# a_n321_n150# 0.16fF
+C66 a_543_n150# a_639_n150# 0.43fF
+C67 a_n225_n150# a_159_n150# 0.07fF
+C68 a_831_n150# a_735_n150# 0.43fF
+C69 a_543_n150# a_351_n150# 0.16fF
+C70 a_831_n150# a_927_n150# 0.43fF
+C71 a_n129_n150# a_159_n150# 0.10fF
+C72 a_n417_n150# a_n705_n150# 0.10fF
+C73 a_447_n150# a_63_n150# 0.07fF
+C74 a_n321_n150# a_n513_n150# 0.16fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_1045_n44# a_687_n44# 0.04fF
+C1 a_329_n44# a_n29_n44# 0.04fF
+C2 a_n745_n44# a_n387_n44# 0.04fF
+C3 a_n1461_n44# a_n1819_n44# 0.04fF
+C4 a_n745_n44# a_n1103_n44# 0.04fF
+C5 a_n387_n44# a_n29_n44# 0.04fF
+C6 a_1403_n44# a_1761_n44# 0.04fF
+C7 a_n1461_n44# a_n1103_n44# 0.04fF
+C8 a_1045_n44# a_1403_n44# 0.04fF
+C9 a_329_n44# a_687_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n81_n150# a_n177_n150# 0.43fF
+C1 a_n561_n150# a_n945_n150# 0.07fF
+C2 a_n1229_n150# a_n945_n150# 0.10fF
+C3 a_1071_n150# w_n1367_n369# 0.07fF
+C4 a_n657_n150# a_n465_n150# 0.16fF
+C5 a_111_n150# a_n177_n150# 0.10fF
+C6 a_15_n150# a_207_n150# 0.16fF
+C7 a_495_n150# a_591_n150# 0.43fF
+C8 a_15_n150# a_n369_n150# 0.07fF
+C9 a_n465_n150# a_n369_n150# 0.43fF
+C10 a_399_n150# a_687_n150# 0.10fF
+C11 a_n81_n150# a_n273_n150# 0.16fF
+C12 a_495_n150# a_303_n150# 0.16fF
+C13 a_n753_n150# a_n1137_n150# 0.07fF
+C14 a_111_n150# a_399_n150# 0.10fF
+C15 a_1071_n150# a_975_n150# 0.43fF
+C16 a_111_n150# a_n273_n150# 0.07fF
+C17 a_207_n150# a_n177_n150# 0.07fF
+C18 a_n657_n150# a_n753_n150# 0.43fF
+C19 a_n369_n150# a_n177_n150# 0.16fF
+C20 a_879_n150# w_n1367_n369# 0.04fF
+C21 a_n1137_n150# a_n849_n150# 0.10fF
+C22 a_591_n150# a_687_n150# 0.43fF
+C23 a_n753_n150# a_n369_n150# 0.07fF
+C24 a_n1041_n150# a_n753_n150# 0.10fF
+C25 a_n657_n150# a_n273_n150# 0.07fF
+C26 a_399_n150# a_207_n150# 0.16fF
+C27 a_1167_n150# w_n1367_n369# 0.14fF
+C28 a_n81_n150# a_303_n150# 0.07fF
+C29 a_15_n150# a_n177_n150# 0.16fF
+C30 a_n657_n150# a_n849_n150# 0.16fF
+C31 a_n465_n150# a_n177_n150# 0.10fF
+C32 a_879_n150# a_591_n150# 0.10fF
+C33 a_303_n150# a_687_n150# 0.07fF
+C34 a_687_n150# a_975_n150# 0.10fF
+C35 a_n273_n150# a_n369_n150# 0.43fF
+C36 a_783_n150# a_399_n150# 0.07fF
+C37 a_111_n150# a_303_n150# 0.16fF
+C38 a_n465_n150# a_n753_n150# 0.10fF
+C39 a_n1041_n150# a_n849_n150# 0.16fF
+C40 a_879_n150# a_975_n150# 0.43fF
+C41 a_n1229_n150# a_n1137_n150# 0.43fF
+C42 a_399_n150# a_15_n150# 0.07fF
+C43 a_n1137_n150# a_n945_n150# 0.16fF
+C44 a_n273_n150# a_15_n150# 0.10fF
+C45 a_n465_n150# a_n273_n150# 0.16fF
+C46 a_207_n150# a_591_n150# 0.07fF
+C47 a_1167_n150# a_975_n150# 0.16fF
+C48 a_n657_n150# a_n561_n150# 0.43fF
+C49 a_n465_n150# a_n849_n150# 0.07fF
+C50 a_495_n150# a_687_n150# 0.16fF
+C51 a_n657_n150# a_n945_n150# 0.10fF
+C52 a_1071_n150# a_687_n150# 0.07fF
+C53 a_303_n150# a_207_n150# 0.43fF
+C54 a_783_n150# a_591_n150# 0.16fF
+C55 a_495_n150# a_111_n150# 0.07fF
+C56 a_n561_n150# a_n369_n150# 0.16fF
+C57 a_n1229_n150# a_n1041_n150# 0.16fF
+C58 a_879_n150# a_495_n150# 0.07fF
+C59 a_n1041_n150# a_n945_n150# 0.43fF
+C60 a_879_n150# a_1071_n150# 0.16fF
+C61 a_n273_n150# a_n177_n150# 0.43fF
+C62 a_783_n150# a_975_n150# 0.16fF
+C63 a_n561_n150# a_n465_n150# 0.43fF
+C64 a_303_n150# a_15_n150# 0.10fF
+C65 a_1167_n150# a_1071_n150# 0.43fF
+C66 a_n753_n150# a_n849_n150# 0.43fF
+C67 a_495_n150# a_207_n150# 0.10fF
+C68 a_n81_n150# a_111_n150# 0.16fF
+C69 a_879_n150# a_687_n150# 0.16fF
+C70 a_783_n150# a_495_n150# 0.10fF
+C71 a_n561_n150# a_n177_n150# 0.07fF
+C72 a_783_n150# a_1071_n150# 0.10fF
+C73 a_399_n150# a_591_n150# 0.16fF
+C74 a_n561_n150# a_n753_n150# 0.16fF
+C75 a_n753_n150# a_n945_n150# 0.16fF
+C76 a_n81_n150# a_207_n150# 0.10fF
+C77 a_399_n150# a_303_n150# 0.43fF
+C78 a_n81_n150# a_n369_n150# 0.10fF
+C79 a_879_n150# a_1167_n150# 0.10fF
+C80 a_n561_n150# a_n273_n150# 0.10fF
+C81 a_111_n150# a_207_n150# 0.43fF
+C82 a_n561_n150# a_n849_n150# 0.10fF
+C83 a_n1229_n150# a_n849_n150# 0.07fF
+C84 w_n1367_n369# a_975_n150# 0.05fF
+C85 a_783_n150# a_687_n150# 0.43fF
+C86 a_n849_n150# a_n945_n150# 0.43fF
+C87 a_n81_n150# a_15_n150# 0.43fF
+C88 a_n1041_n150# a_n1137_n150# 0.43fF
+C89 a_n81_n150# a_n465_n150# 0.07fF
+C90 a_879_n150# a_783_n150# 0.43fF
+C91 a_495_n150# a_399_n150# 0.43fF
+C92 a_303_n150# a_591_n150# 0.10fF
+C93 a_111_n150# a_15_n150# 0.43fF
+C94 a_591_n150# a_975_n150# 0.07fF
+C95 a_n657_n150# a_n369_n150# 0.10fF
+C96 a_n657_n150# a_n1041_n150# 0.07fF
+C97 a_783_n150# a_1167_n150# 0.07fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump vss pswitch nswitch out vdd biasp nUp Down w_2544_775# iref nDown
++ Up w_1008_774#
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 nswitch biasp 0.03fF
+C1 nswitch iref 1.91fF
+C2 nswitch vdd 0.07fF
+C3 Down nUp 0.25fF
+C4 nUp pswitch 5.66fF
+C5 Up pswitch 0.70fF
+C6 out pswitch 4.91fF
+C7 nDown Down 0.13fF
+C8 Up nUp 0.15fF
+C9 out nUp 0.31fF
+C10 biasp pswitch 3.11fF
+C11 nswitch Down 2.27fF
+C12 vdd pswitch 3.98fF
+C13 nswitch pswitch 0.06fF
+C14 out vdd 6.66fF
+C15 out nswitch 1.28fF
+C16 iref biasp 0.80fF
+C17 vdd biasp 2.64fF
+C18 nDown nswitch 0.31fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n42# a_n125_n42# 0.12fF
+C1 a_63_n42# a_n125_n42# 0.05fF
+C2 a_33_n68# a_n63_n68# 0.02fF
+C3 a_n33_n42# a_63_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_63_n84# a_n33_n84# 0.24fF
+C1 a_33_n110# a_n63_n110# 0.02fF
+C2 w_n263_n303# a_n125_n84# 0.10fF
+C3 w_n263_n303# a_n33_n84# 0.07fF
+C4 a_n33_n84# a_n125_n84# 0.24fF
+C5 a_63_n84# w_n263_n303# 0.10fF
+C6 a_63_n84# a_n125_n84# 0.09fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 vdd out 0.15fF
+C1 vdd in 0.01fF
+C2 in out 0.30fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 nout_div clock_inverter_0/inverter_cp_x1_0/out
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/latch_diff_0/nD
++ out_div DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# nout_div
++ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop
+Xinverter_min_x4_1 vdd o2 vss nCLK_2 inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss CLK_2 inverter_min_x4
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 nout_div out_div 0.22fF
+C1 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C2 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C3 nout_div DFlipFlop_0/nCLK 0.43fF
+C4 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C5 nout_div DFlipFlop_0/CLK 0.42fF
+C6 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C7 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C8 vdd out_div 0.03fF
+C9 DFlipFlop_0/nCLK vdd 0.30fF
+C10 o2 nCLK_2 0.11fF
+C11 o1 out_div 0.01fF
+C12 vdd DFlipFlop_0/CLK 0.40fF
+C13 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C14 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C15 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C16 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C17 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C18 nCLK_2 vdd 0.08fF
+C19 nout_div vdd 0.16fF
+C20 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C21 o2 vdd 0.14fF
+C22 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
+C23 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C24 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C25 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C26 vdd CLK_2 0.08fF
+C27 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C28 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C29 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C30 o1 CLK_2 0.11fF
+C31 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C32 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C33 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C34 vdd o1 0.14fF
+C35 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C36 DFlipFlop_0/CLK vss 1.03fF
+C37 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C38 CLK vss 3.27fF
+C39 DFlipFlop_0/nCLK vss 1.76fF
+C40 o1 vss 2.21fF
+C41 CLK_2 vss 1.08fF
+C42 o2 vss 2.21fF
+C43 nCLK_2 vss 1.08fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C50 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n129_n600# a_n257_n777# 0.29fF
+C1 a_n129_n600# a_n221_n600# 7.87fF
+C2 a_n221_n600# a_n257_n777# 0.25fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n129_n300# a_n257_n404# 0.30fF
+C1 a_n129_n300# a_n221_n300# 4.05fF
+C2 a_n257_n404# a_n221_n300# 0.21fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in a_3996_n100# vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 a_678_n100# vdd 0.08fF
+C1 out vdd 47.17fF
+C2 a_3996_n100# a_678_n100# 6.52fF
+C3 a_3996_n100# out 55.19fF
+C4 a_678_n100# in 0.81fF
+C5 a_3996_n100# vdd 3.68fF
+C6 vdd in 0.02fF
+C7 a_3996_n100# vss 49.53fF
+C8 vdd vss 20.93fF
+C9 out vss 35.17fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n33_n238# 0.02fF
+C1 a_n73_n150# a_n33_n238# 0.02fF
+C2 a_15_n150# a_n73_n150# 0.51fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n369# a_n73_n150# 0.20fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 w_n211_n369# a_n33_181# 0.05fF
+C3 a_n33_181# a_15_n150# 0.01fF
+C4 a_n33_181# a_n73_n150# 0.01fF
+C5 w_n211_n369# a_15_n150# 0.20fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_63_n150# a_255_n150# 0.16fF
+C1 a_63_n150# a_n129_n150# 0.16fF
+C2 a_n417_n150# a_n509_n150# 0.43fF
+C3 a_n509_n150# a_n225_n150# 0.10fF
+C4 a_255_n150# a_351_n150# 0.43fF
+C5 a_n417_n150# a_n129_n150# 0.10fF
+C6 a_n129_n150# a_n225_n150# 0.43fF
+C7 a_n33_n150# a_n321_n150# 0.10fF
+C8 a_63_n150# a_n225_n150# 0.10fF
+C9 a_63_n150# a_351_n150# 0.10fF
+C10 a_n417_n150# a_n225_n150# 0.16fF
+C11 a_159_n150# a_n465_172# 0.10fF
+C12 a_n33_n150# a_n465_172# 0.10fF
+C13 a_447_n150# a_n465_172# 0.01fF
+C14 a_159_n150# a_255_n150# 0.43fF
+C15 a_n33_n150# a_255_n150# 0.10fF
+C16 a_159_n150# a_n129_n150# 0.10fF
+C17 a_447_n150# a_255_n150# 0.16fF
+C18 a_n33_n150# a_n129_n150# 0.43fF
+C19 a_n465_172# a_n321_n150# 0.10fF
+C20 a_63_n150# a_159_n150# 0.43fF
+C21 a_159_n150# a_n225_n150# 0.07fF
+C22 a_63_n150# a_n33_n150# 0.43fF
+C23 a_159_n150# a_351_n150# 0.16fF
+C24 a_n33_n150# a_n417_n150# 0.07fF
+C25 a_63_n150# a_447_n150# 0.07fF
+C26 a_n33_n150# a_n225_n150# 0.16fF
+C27 a_n509_n150# a_n321_n150# 0.16fF
+C28 a_n33_n150# a_351_n150# 0.07fF
+C29 a_n129_n150# a_n321_n150# 0.16fF
+C30 a_447_n150# a_351_n150# 0.43fF
+C31 a_63_n150# a_n321_n150# 0.07fF
+C32 a_n417_n150# a_n321_n150# 0.43fF
+C33 a_n321_n150# a_n225_n150# 0.43fF
+C34 a_n465_172# a_255_n150# 0.10fF
+C35 a_n465_172# a_n509_n150# 0.01fF
+C36 a_n465_172# a_n129_n150# 0.10fF
+C37 a_255_n150# a_n129_n150# 0.07fF
+C38 a_63_n150# a_n465_172# 0.10fF
+C39 a_n509_n150# a_n129_n150# 0.07fF
+C40 a_159_n150# a_n33_n150# 0.16fF
+C41 a_n417_n150# a_n465_172# 0.10fF
+C42 a_n465_172# a_n225_n150# 0.10fF
+C43 a_159_n150# a_447_n150# 0.10fF
+C44 a_n465_172# a_351_n150# 0.10fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n150# a_63_n150# 0.43fF
+C1 a_n225_n150# a_n465_n247# 0.08fF
+C2 a_n225_n150# a_159_n150# 0.07fF
+C3 w_n647_n369# a_n509_n150# 0.14fF
+C4 w_n647_n369# a_447_n150# 0.14fF
+C5 a_n225_n150# a_63_n150# 0.10fF
+C6 a_n33_n150# a_n129_n150# 0.43fF
+C7 a_n225_n150# a_n129_n150# 0.43fF
+C8 w_n647_n369# a_n465_n247# 0.47fF
+C9 w_n647_n369# a_159_n150# 0.04fF
+C10 a_447_n150# a_255_n150# 0.16fF
+C11 a_n225_n150# a_n33_n150# 0.16fF
+C12 a_n417_n150# a_n321_n150# 0.43fF
+C13 w_n647_n369# a_63_n150# 0.02fF
+C14 a_n465_n247# a_255_n150# 0.08fF
+C15 a_255_n150# a_159_n150# 0.43fF
+C16 a_n509_n150# a_n321_n150# 0.16fF
+C17 w_n647_n369# a_n129_n150# 0.02fF
+C18 w_n647_n369# a_n33_n150# 0.02fF
+C19 a_255_n150# a_63_n150# 0.16fF
+C20 w_n647_n369# a_n225_n150# 0.04fF
+C21 a_255_n150# a_n129_n150# 0.07fF
+C22 a_n465_n247# a_n321_n150# 0.08fF
+C23 a_n33_n150# a_255_n150# 0.10fF
+C24 a_63_n150# a_n321_n150# 0.07fF
+C25 a_447_n150# a_351_n150# 0.43fF
+C26 a_n129_n150# a_n321_n150# 0.16fF
+C27 a_n509_n150# a_n417_n150# 0.43fF
+C28 a_n33_n150# a_n321_n150# 0.10fF
+C29 a_n465_n247# a_351_n150# 0.08fF
+C30 a_351_n150# a_159_n150# 0.16fF
+C31 a_351_n150# a_63_n150# 0.10fF
+C32 a_n225_n150# a_n321_n150# 0.43fF
+C33 w_n647_n369# a_255_n150# 0.05fF
+C34 a_n465_n247# a_n417_n150# 0.08fF
+C35 a_n33_n150# a_351_n150# 0.07fF
+C36 w_n647_n369# a_n321_n150# 0.05fF
+C37 a_447_n150# a_159_n150# 0.10fF
+C38 a_n417_n150# a_n129_n150# 0.10fF
+C39 a_n33_n150# a_n417_n150# 0.07fF
+C40 a_447_n150# a_63_n150# 0.07fF
+C41 a_n465_n247# a_159_n150# 0.08fF
+C42 a_n225_n150# a_n417_n150# 0.16fF
+C43 a_n509_n150# a_n129_n150# 0.07fF
+C44 a_n465_n247# a_63_n150# 0.08fF
+C45 a_63_n150# a_159_n150# 0.43fF
+C46 w_n647_n369# a_351_n150# 0.07fF
+C47 a_n225_n150# a_n509_n150# 0.10fF
+C48 a_n465_n247# a_n129_n150# 0.08fF
+C49 a_159_n150# a_n129_n150# 0.10fF
+C50 a_n33_n150# a_n465_n247# 0.08fF
+C51 a_n33_n150# a_159_n150# 0.16fF
+C52 w_n647_n369# a_n417_n150# 0.07fF
+C53 a_255_n150# a_351_n150# 0.43fF
+C54 a_63_n150# a_n129_n150# 0.16fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n99# a_n73_n11# 0.02fF
+C1 a_n73_n11# a_15_n11# 0.15fF
+C2 a_n33_n99# a_15_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_n78_n114# 0.20fF
+C1 w_n216_n334# a_20_n114# 0.20fF
+C2 a_20_n114# a_n78_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vdd 0.01fF
+C1 vss in 0.01fF
+C2 out vbulkp 0.08fF
+C3 out in 0.11fF
+C4 vbulkp vdd 0.04fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch vctrl inverter_csvco_0/vdd in vbp cap_vco_0/t D0 out inverter_csvco_0/vss
++ vss vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 vbp inverter_csvco_0/vdd 0.75fF
+C1 in inverter_csvco_0/vdd 0.01fF
+C2 in inverter_csvco_0/vss 0.01fF
+C3 vdd cap_vco_0/t 0.04fF
+C4 vctrl inverter_csvco_0/vss 0.87fF
+C5 D0 out 0.09fF
+C6 cap_vco_0/t out 0.70fF
+C7 vdd vbp 1.21fF
+C8 vdd inverter_csvco_0/vdd 1.89fF
+C9 D0 inverter_csvco_0/vss 0.02fF
+C10 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C11 inverter_csvco_0/vdd out 0.02fF
+C12 inverter_csvco_0/vss out 0.03fF
+C13 in out 0.06fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc csvco_branch_0/inverter_csvco_0/vdd vctrl csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch_2/inverter_csvco_0/vdd vdd vss csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl csvco_branch_0/inverter_csvco_0/vdd out_vco csvco_branch_2/vbp
++ csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in csvco_branch_0/inverter_csvco_0/vss
++ vss vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/inverter_csvco_0/vdd csvco_branch_2/in csvco_branch_2/vbp
++ csvco_branch_2/cap_vco_0/t D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/inverter_csvco_0/vdd csvco_branch_1/in csvco_branch_2/vbp
++ csvco_branch_1/cap_vco_0/t D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss
++ vss vdd csvco_branch
+C0 vctrl csvco_branch_2/vbp 0.06fF
+C1 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C2 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C3 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
+C4 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
+C5 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C6 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C7 out_vco csvco_branch_2/in 0.58fF
+C8 D0 csvco_branch_1/inverter_csvco_0/vss 0.68fF
+C9 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C10 out_vco csvco_branch_1/in 0.76fF
+C11 vdd csvco_branch_2/vbp 1.49fF
+C12 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C13 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
+C14 D0 vctrl 4.41fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_1 vdd out_div vss out_pad inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss out_div inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 vdd o1 0.09fF
+C1 out_div vdd 0.17fF
+C2 vdd out_pad 0.10fF
+C3 out_div o1 0.11fF
+C4 out_div out_pad 0.15fF
+C5 in_vco vss 0.83fF
+C6 o1 vss 2.72fF
+C7 vdd vss 14.54fF
+C8 out_div vss 3.00fF
+C9 out_pad vss 0.70fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 X B 0.13fF
+C1 B a_355_368# 0.08fF
+C2 B VGND 0.10fF
+C3 VPWR B 0.09fF
+C4 B A 0.28fF
+C5 B a_194_125# 0.57fF
+C6 a_194_125# a_158_392# 0.06fF
+C7 X a_355_368# 0.17fF
+C8 X VGND 0.28fF
+C9 VPWR X 0.07fF
+C10 VPWR a_355_368# 0.37fF
+C11 VPWR VGND 0.01fF
+C12 a_355_368# A 0.02fF
+C13 X a_194_125# 0.29fF
+C14 a_355_368# a_194_125# 0.51fF
+C15 VPWR VPB 0.06fF
+C16 VGND A 0.31fF
+C17 VPWR A 0.15fF
+C18 VGND a_194_125# 0.25fF
+C19 VPWR a_194_125# 0.33fF
+C20 a_194_125# A 0.18fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 a_56_136# VPWR 0.57fF
+C1 A VPWR 0.07fF
+C2 B VGND 0.03fF
+C3 VPB VPWR 0.04fF
+C4 a_56_136# B 0.30fF
+C5 a_56_136# VGND 0.06fF
+C6 B A 0.08fF
+C7 VGND A 0.21fF
+C8 VPWR X 0.20fF
+C9 a_56_136# A 0.17fF
+C10 B X 0.02fF
+C11 B VPWR 0.02fF
+C12 VGND X 0.15fF
+C13 a_56_136# X 0.26fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 A a_63_368# 0.28fF
+C1 VGND a_63_368# 0.27fF
+C2 X VPWR 0.18fF
+C3 X a_63_368# 0.33fF
+C4 X A 0.02fF
+C5 VGND X 0.16fF
+C6 VPWR VPB 0.04fF
+C7 B VPWR 0.01fF
+C8 B a_63_368# 0.14fF
+C9 B A 0.10fF
+C10 VGND B 0.11fF
+C11 a_152_368# a_63_368# 0.03fF
+C12 VPWR a_63_368# 0.29fF
+C13 VPWR A 0.05fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK DFlipFlop_0/latch_diff_1/nD
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vdd vss Q0 CLK DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ DFlipFlop_3/latch_diff_0/D nQ0 DFlipFlop_1/latch_diff_0/nD DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/D CLK_5 nQ2 Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D DFlipFlop_2/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/latch_diff_0/nD sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_1/D
++ DFlipFlop_2/nQ DFlipFlop_3/latch_diff_0/nD DFlipFlop_2/latch_diff_0/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_0/D sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D
++ sky130_fd_sc_hs__or2_1_0/a_63_368# DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# sky130_fd_sc_hs__and2_1_0/a_143_136# DFlipFlop_2/latch_diff_0/nD
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/D
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss vdd DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss vdd DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# Q1 DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out CLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C1 DFlipFlop_0/Q Q1 0.13fF
+C2 nQ0 Q0 0.33fF
+C3 nQ0 DFlipFlop_1/latch_diff_0/D 0.09fF
+C4 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C5 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C6 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C7 Q0 DFlipFlop_0/latch_diff_1/D 0.23fF
+C8 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C9 Q0 nQ2 0.23fF
+C10 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C11 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C12 Q0 nCLK 0.20fF
+C13 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
+C14 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C15 nQ0 DFlipFlop_1/latch_diff_0/m1_657_280# 0.25fF
+C16 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C17 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C18 Q0 vdd 5.33fF
+C19 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C20 Q0 Q1 9.65fF
+C21 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
+C22 nQ0 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.04fF
+C23 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
+C24 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C25 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C26 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C27 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C28 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C29 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C30 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C31 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C32 CLK DFlipFlop_1/D 0.21fF
+C33 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
+C34 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C35 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C36 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
+C37 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C38 vdd DFlipFlop_0/D 0.19fF
+C39 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C40 nQ0 CLK 0.19fF
+C41 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
+C42 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C43 Q0 DFlipFlop_2/D 0.25fF
+C44 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C45 Q1 DFlipFlop_0/D 0.13fF
+C46 nQ0 DFlipFlop_1/D 0.12fF
+C47 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
+C48 Q0 DFlipFlop_0/Q 0.21fF
+C49 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
+C50 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C51 CLK nQ2 0.17fF
+C52 CLK_5 vdd 0.15fF
+C53 DFlipFlop_3/nQ CLK 0.01fF
+C54 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
+C55 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
+C56 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C57 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C58 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C59 DFlipFlop_1/D nCLK 0.14fF
+C60 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C61 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C62 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C63 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C64 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C65 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C66 CLK vdd 0.41fF
+C67 DFlipFlop_2/nQ CLK 0.13fF
+C68 nQ0 nQ2 0.03fF
+C69 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C70 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C71 nQ0 nCLK 0.09fF
+C72 vdd DFlipFlop_1/D 0.25fF
+C73 CLK Q1 -0.10fF
+C74 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C75 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C76 DFlipFlop_3/nQ Q1_shift 0.04fF
+C77 nCLK nQ2 0.10fF
+C78 DFlipFlop_1/D Q1 0.03fF
+C79 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C80 DFlipFlop_3/nQ nCLK 0.02fF
+C81 Q1_shift sky130_fd_sc_hs__or2_1_0/a_63_368# -0.27fF
+C82 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C83 nQ0 vdd 0.11fF
+C84 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
+C85 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C86 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C87 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
+C88 DFlipFlop_2/latch_diff_1/m1_657_280# Q1 0.03fF
+C89 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C90 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C91 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C92 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C93 nQ0 Q1 0.06fF
+C94 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C95 vdd Q1_shift 0.10fF
+C96 vdd nQ2 0.04fF
+C97 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C98 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C99 DFlipFlop_3/nQ vdd 0.02fF
+C100 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C101 DFlipFlop_2/nQ nCLK 0.09fF
+C102 vdd nCLK 0.34fF
+C103 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C104 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C105 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C106 Q1 Q1_shift 0.36fF
+C107 Q1 nQ2 0.07fF
+C108 CLK DFlipFlop_2/D 0.14fF
+C109 DFlipFlop_3/nQ Q1 0.10fF
+C110 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C111 nCLK Q1 -0.01fF
+C112 nQ0 DFlipFlop_1/latch_diff_0/nD 0.08fF
+C113 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
+C114 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C115 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C116 CLK DFlipFlop_0/Q 0.08fF
+C117 DFlipFlop_2/nQ vdd 0.02fF
+C118 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C119 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C120 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C121 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C122 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C123 Q0 DFlipFlop_0/D 0.39fF
+C124 vdd Q1 9.49fF
+C125 DFlipFlop_2/nQ Q1 0.31fF
+C126 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C127 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C128 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C129 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C130 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C131 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C132 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C133 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C134 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C135 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C136 Q0 sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.26fF
+C137 nCLK DFlipFlop_2/D 0.41fF
+C138 DFlipFlop_0/latch_diff_1/nD Q1 0.10fF
+C139 DFlipFlop_0/Q nQ2 0.09fF
+C140 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C141 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C142 DFlipFlop_0/Q nCLK 0.11fF
+C143 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C144 Q0 CLK 0.08fF
+C145 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C146 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C147 vdd DFlipFlop_2/D 0.07fF
+C148 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
+C149 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C150 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
+C151 Q0 DFlipFlop_1/D 0.07fF
+C152 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C153 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C154 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C155 Q1 DFlipFlop_2/D 0.10fF
+C156 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C168 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 Q1 vss 8.55fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C172 nQ0 vss 3.42fF
+C173 Q0 vss 0.53fF
+C174 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C175 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C176 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C177 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C178 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C179 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C180 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C181 DFlipFlop_1/D vss 3.72fF
+C182 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C183 DFlipFlop_2/nQ vss 0.50fF
+C184 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C185 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C186 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C187 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C189 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C190 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C191 DFlipFlop_2/D vss 5.34fF
+C192 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C202 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_63_n125# a_n33_n125# 0.36fF
+C1 a_n255_n151# a_n159_n151# 0.02fF
+C2 a_n225_n125# a_n129_n125# 0.36fF
+C3 a_129_n151# a_225_n151# 0.02fF
+C4 a_255_n125# a_63_n125# 0.13fF
+C5 a_n129_n125# a_n33_n125# 0.36fF
+C6 a_33_n151# a_n63_n151# 0.02fF
+C7 a_63_n125# a_n317_n125# 0.06fF
+C8 a_129_n151# a_33_n151# 0.02fF
+C9 a_255_n125# a_n129_n125# 0.06fF
+C10 a_n225_n125# a_159_n125# 0.06fF
+C11 a_n33_n125# a_159_n125# 0.13fF
+C12 a_n129_n125# a_n317_n125# 0.13fF
+C13 a_n129_n125# a_63_n125# 0.13fF
+C14 a_n225_n125# a_n33_n125# 0.13fF
+C15 a_255_n125# a_159_n125# 0.36fF
+C16 a_63_n125# a_159_n125# 0.36fF
+C17 a_255_n125# a_n33_n125# 0.08fF
+C18 a_n225_n125# a_n317_n125# 0.36fF
+C19 a_n159_n151# a_n63_n151# 0.02fF
+C20 a_n33_n125# a_n317_n125# 0.08fF
+C21 a_n225_n125# a_63_n125# 0.08fF
+C22 a_n129_n125# a_159_n125# 0.08fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n455_n344# a_n33_n125# 0.05fF
+C1 a_159_n125# a_63_n125# 0.36fF
+C2 a_n225_n125# a_159_n125# 0.06fF
+C3 a_255_n125# a_159_n125# 0.36fF
+C4 a_n225_n125# a_63_n125# 0.08fF
+C5 a_255_n125# a_63_n125# 0.13fF
+C6 w_n455_n344# a_n317_n125# 0.11fF
+C7 a_n129_n125# a_n33_n125# 0.36fF
+C8 a_n33_n125# a_159_n125# 0.13fF
+C9 a_n129_n125# a_n317_n125# 0.13fF
+C10 a_n33_n125# a_63_n125# 0.36fF
+C11 a_n225_n125# a_n33_n125# 0.13fF
+C12 w_n455_n344# a_n129_n125# 0.04fF
+C13 a_255_n125# a_n33_n125# 0.08fF
+C14 a_n317_n125# a_63_n125# 0.06fF
+C15 w_n455_n344# a_159_n125# 0.06fF
+C16 a_n225_n125# a_n317_n125# 0.36fF
+C17 a_n159_n154# a_n63_n154# 0.02fF
+C18 w_n455_n344# a_63_n125# 0.04fF
+C19 a_n225_n125# w_n455_n344# 0.06fF
+C20 w_n455_n344# a_255_n125# 0.11fF
+C21 a_129_n154# a_33_n154# 0.02fF
+C22 a_n159_n154# a_n255_n154# 0.02fF
+C23 a_n129_n125# a_159_n125# 0.08fF
+C24 a_n129_n125# a_63_n125# 0.13fF
+C25 a_33_n154# a_n63_n154# 0.02fF
+C26 a_n225_n125# a_n129_n125# 0.36fF
+C27 a_n317_n125# a_n33_n125# 0.08fF
+C28 a_225_n154# a_129_n154# 0.02fF
+C29 a_255_n125# a_n129_n125# 0.06fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 in vdd 0.04fF
+C1 out vdd 0.29fF
+C2 out in 0.85fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss vdd inverter_cp_x1_0/out inverter_cp_x1_2/in Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd Down 0.09fF
+C1 nDown inverter_cp_x1_0/out 0.11fF
+C2 nDown vdd 0.80fF
+C3 vdd inverter_cp_x1_0/out 0.25fF
+C4 vdd QB 0.02fF
+C5 vdd inverter_cp_x1_2/in 0.42fF
+C6 vdd Up 0.60fF
+C7 inverter_cp_x1_2/in Up 0.12fF
+C8 nUp vdd 0.14fF
+C9 nUp Up 0.20fF
+C10 vdd QA 0.02fF
+C11 nDown Down 0.23fF
+C12 Down inverter_cp_x1_0/out 0.12fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n129_n90# a_63_n90# 0.09fF
+C1 a_n221_n90# a_159_n90# 0.04fF
+C2 w_n359_n309# a_n221_n90# 0.09fF
+C3 a_n221_n90# a_n33_n90# 0.09fF
+C4 a_n221_n90# a_n129_n90# 0.26fF
+C5 a_n221_n90# a_63_n90# 0.06fF
+C6 a_n33_n90# a_159_n90# 0.09fF
+C7 w_n359_n309# a_159_n90# 0.09fF
+C8 a_n129_n90# a_159_n90# 0.06fF
+C9 a_63_n90# a_159_n90# 0.26fF
+C10 a_n63_n116# a_n159_n207# 0.12fF
+C11 w_n359_n309# a_n33_n90# 0.05fF
+C12 a_n129_n90# a_n33_n90# 0.26fF
+C13 w_n359_n309# a_n129_n90# 0.06fF
+C14 a_n33_n90# a_63_n90# 0.26fF
+C15 w_n359_n309# a_63_n90# 0.06fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n33_n45# 0.13fF
+C1 a_n129_71# a_33_n71# 0.04fF
+C2 a_n125_n45# a_n33_n45# 0.13fF
+C3 a_63_n45# a_n125_n45# 0.05fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 out vdd 0.11fF
+C1 out A 0.06fF
+C2 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C3 A vdd 0.09fF
+C4 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C5 B out 0.40fF
+C6 B A 0.24fF
+C7 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vdd vss nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C1 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C2 nor_pfd_3/A vdd 0.09fF
+C3 Reset nor_pfd_2/B 0.43fF
+C4 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C5 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C6 vdd Q 0.08fF
+C7 nor_pfd_2/B Q 2.22fF
+C8 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C9 nor_pfd_2/A Q 1.38fF
+C10 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C11 CLK Q 0.04fF
+C12 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C13 nor_pfd_3/A Reset 0.12fF
+C14 nor_pfd_2/B vdd 0.02fF
+C15 nor_pfd_2/A vdd -0.01fF
+C16 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C17 Reset Q 0.14fF
+C18 nor_pfd_3/A Q 0.98fF
+C19 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 Reset vss 1.48fF
+C24 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 nor_pfd_2/A vss 2.56fF
+C27 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 Q vss 2.77fF
+C29 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 nor_pfd_3/A vss 3.16fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_159_n45# a_n221_n45# 0.02fF
+C1 a_63_n45# a_n33_n45# 0.13fF
+C2 a_n129_n45# a_63_n45# 0.05fF
+C3 a_n129_n45# a_n33_n45# 0.13fF
+C4 a_n221_n45# a_63_n45# 0.03fF
+C5 a_n221_n45# a_n33_n45# 0.05fF
+C6 a_n129_n45# a_n221_n45# 0.13fF
+C7 a_159_n45# a_63_n45# 0.13fF
+C8 a_159_n45# a_n33_n45# 0.05fF
+C9 a_159_n45# a_n129_n45# 0.03fF
+C10 a_n63_n71# a_n159_n173# 0.10fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n99_n187# a_33_n187# 0.04fF
+C1 a_n125_n90# a_63_n90# 0.09fF
+C2 a_n33_n90# a_63_n90# 0.26fF
+C3 a_n33_n90# a_n125_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_15_n45# a_n73_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n73_n90# a_15_n90# 0.31fF
+C1 a_15_n90# w_n211_n309# 0.09fF
+C2 a_n73_n90# w_n211_n309# 0.04fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 A vdd 0.05fF
+C1 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C2 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C3 out vdd 0.10fF
+C4 B A 0.33fF
+C5 A a_656_410# 0.04fF
+C6 vdd a_656_410# 0.20fF
+C7 out a_656_410# 0.20fF
+C8 B a_656_410# 0.30fF
+C9 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vdd vss dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vdd vss dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
+C1 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C2 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C3 vdd Up 1.62fF
+C4 Down vdd 0.08fF
+C5 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C6 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C7 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C8 Down Up 0.06fF
+C9 vdd Reset 0.02fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C19 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C20 Down vss 3.74fF
+C21 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C22 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C23 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C25 B vss 1.07fF
+C26 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C27 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C28 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C29 Reset vss 3.85fF
+C30 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C31 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C32 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C33 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C34 Up vss 3.18fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C36 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C37 vdd vss 44.73fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v1 vco_vctrl vdd pswitch ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ charge_pump_0/w_2544_775# ring_osc_0/csvco_branch_2/vbp biasp in_ref Down vss w_13905_n238#
++ vco_D0 buffer_salida_0/a_3996_n100# ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ QA charge_pump_0/w_1008_774# iref_cp ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
++ out_to_div nDown out_to_pad Up nUp
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
++ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
++ vss vdd buffer_salida
+Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd vss ring_osc_0/csvco_branch_2/vbp
++ ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t
++ vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
++ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
++ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
++ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 vco_vctrl nswitch -0.06fF
+C1 vco_D0 vdd 0.03fF
+C2 Up vdd 0.28fF
+C3 iref_cp vdd 0.15fF
+C4 Down iref_cp 0.09fF
+C5 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C6 out_to_buffer vdd 0.07fF
+C7 out_div_by_5 div_5_Q1_shift 0.05fF
+C8 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C9 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
+C10 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C11 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
+C12 Up pswitch 1.98fF
+C13 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
+C14 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
+C15 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C16 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C17 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C18 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C19 vdd out_to_div 0.21fF
+C20 Up nUp 2.72fF
+C21 div_by_5_0/DFlipFlop_2/latch_diff_1/D n_out_by_2 0.10fF
+C22 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C23 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
+C24 n_out_by_2 div_5_nQ0 0.10fF
+C25 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C26 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
+C27 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
+C28 out_by_2 div_5_nQ0 0.32fF
+C29 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C30 Down biasp 1.24fF
+C31 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C32 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C33 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C34 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C35 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
+C36 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.17fF
+C37 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C38 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C39 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C40 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
+C41 biasp nUp -0.17fF
+C42 nDown biasp 0.26fF
+C43 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C44 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C45 vdd lf_vc 0.02fF
+C46 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C47 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
+C48 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C49 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C50 n_out_by_2 div_5_nQ2 0.10fF
+C51 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C52 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C53 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
+C54 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
+C55 buffer_salida_0/a_678_n100# vdd 0.24fF
+C56 out_by_2 div_5_nQ2 0.16fF
+C57 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C58 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C59 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C60 n_out_by_2 div_5_Q1 1.04fF
+C61 vco_vctrl div_5_Q1 0.14fF
+C62 n_out_by_2 vdd 1.03fF
+C63 nUp vdd 0.05fF
+C64 nDown vdd 0.22fF
+C65 vco_vctrl vdd -1.02fF
+C66 div_5_Q1 out_by_2 0.42fF
+C67 Down nDown 2.55fF
+C68 out_by_2 vdd 0.97fF
+C69 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
+C70 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C71 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
+C72 pswitch nUp 0.85fF
+C73 nDown pswitch 0.53fF
+C74 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
+C75 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C76 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
+C77 out_to_buffer out_to_div 0.13fF
+C78 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
+C79 n_out_by_2 vco_vctrl 0.52fF
+C80 nDown nUp -0.09fF
+C81 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
+C82 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C83 vco_vctrl nUp 0.02fF
+C84 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C85 n_out_by_2 div_5_Q0 -0.12fF
+C86 vco_vctrl div_5_Q0 0.48fF
+C87 vco_vctrl out_by_2 0.53fF
+C88 QA vdd -0.04fF
+C89 Up biasp 0.26fF
+C90 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C91 div_5_Q1 out_div_by_5 0.01fF
+C92 out_by_2 div_5_Q0 0.09fF
+C93 out_div_by_5 vdd 0.28fF
+C94 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C95 Down nswitch 0.54fF
+C96 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C97 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C98 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C99 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C100 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C101 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C102 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_to_div -0.16fF
+C103 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C104 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C105 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C106 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
+C107 nDown nswitch 0.76fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C118 QB vss 4.46fF
+C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss -0.40fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 pfd_reset vss 2.17fF
+C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C132 QA vss 4.31fF
+C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 5.50fF
+C141 Up vss 2.37fF
+C142 Down vss 7.92fF
+C143 nDown vss -2.20fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_5_Q1 vss 4.28fF
+C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C158 div_5_nQ0 vss 0.59fF
+C159 div_5_Q0 vss 0.01fF
+C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_first_buffer vss 2.88fF
+C196 out_to_div vss 4.46fF
+C197 out_to_buffer vss 1.57fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 vco_D0 vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 buffer_salida_0/a_3996_n100# vss 48.29fF
+C213 out_to_pad vss 7.50fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C217 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C218 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C219 out_buffer_div_2 vss 1.60fF
+C220 n_out_buffer_div_2 vss 1.63fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 nswitch vss 3.73fF
+C232 biasp vss 5.44fF
+C233 iref_cp vss 2.81fF
+C234 vco_vctrl vss -19.28fF
+C235 pswitch vss 3.57fF
+C236 lf_vc vss -59.89fF
+C237 loop_filter_0/res_loop_filter_2/out vss 7.90fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_2_2Y8F6P VSUBS c2_n3251_n3000# m4_n3351_n3100#
+X0 c2_n3251_n3000# m4_n3351_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+C0 m4_n3351_n3100# c2_n3251_n3000# 72.82fF
+C1 m4_n3351_n3100# VSUBS 14.58fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_8P223X VSUBS a_n2017_n1317# a_n1731_n1219# a_n1879_n1219#
++ a_n2017_n61# w_n2018_n202#
+X0 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X1 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X2 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X3 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X4 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X5 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X6 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X7 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X8 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X9 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X10 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X11 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X12 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X13 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X14 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X15 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X16 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X17 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X18 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X19 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X20 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X21 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X22 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X23 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X24 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X25 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X26 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X27 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X28 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X29 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X30 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X31 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X32 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X33 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X34 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X35 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X36 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X37 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X38 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X39 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X40 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X41 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X42 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X43 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X44 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X45 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X46 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X47 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X48 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+C0 w_n2018_n202# a_n2017_n61# 1.37fF
+C1 w_n2018_n202# a_n1879_n1219# 0.25fF
+C2 a_n2017_n61# a_n1879_n1219# 0.16fF
+C3 a_n2017_n1317# a_n1731_n1219# 4.73fF
+C4 w_n2018_n202# a_n1731_n1219# 19.90fF
+C5 a_n2017_n61# a_n1731_n1219# 5.23fF
+C6 a_n1879_n1219# a_n1731_n1219# 19.29fF
+C7 w_n2018_n202# a_n2017_n1317# 0.16fF
+C8 a_n2017_n61# a_n2017_n1317# 2.88fF
+C9 a_n2017_n1317# a_n1879_n1219# 2.66fF
+C10 a_n1879_n1219# VSUBS 1.53fF
+C11 a_n2017_n1317# VSUBS 5.03fF
+C12 a_n1731_n1219# VSUBS 2.60fF
+C13 a_n2017_n61# VSUBS 5.10fF
+C14 w_n2018_n202# VSUBS 37.43fF
+.ends
+
+.subckt bias VSUBS vdd iref_0 iref_1 iref_2 iref_5 iref_6 iref_7 iref_8 iref_9 iref
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_5 VSUBS iref m1_20168_984# iref m1_20168_984#
++ vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_6 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219#
++ iref_5 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_7 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219#
++ iref_6 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_9 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219#
++ iref_8 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_8 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219#
++ iref_7 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_10 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219#
++ iref_9 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_0 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219#
++ iref_0 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_1 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219#
++ iref_1 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_2 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219#
++ iref_2 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_3 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219#
++ iref_3 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_4 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219#
++ iref_4 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+C0 iref_4 iref_3 0.05fF
+C1 iref_5 iref_6 0.05fF
+C2 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# 0.24fF
+C3 iref_3 iref_2 0.05fF
+C4 iref_9 iref_8 0.05fF
+C5 iref_5 iref 0.05fF
+C6 iref_7 iref_6 0.05fF
+C7 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vdd 0.24fF
+C8 iref_7 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C9 iref_2 iref_1 0.05fF
+C10 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# iref -0.15fF
+C11 iref_8 iref -0.03fF
+C12 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# iref_6 0.24fF
+C13 iref_3 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.24fF
+C14 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.01fF
+C15 iref_4 iref 0.30fF
+C16 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vdd 0.24fF
+C17 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# 0.24fF
+C18 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.01fF
+C19 m1_20168_984# iref 0.07fF
+C20 iref_2 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
+C21 m1_20168_984# vdd 0.25fF
+C22 iref iref_2 -0.01fF
+C23 iref_8 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# 0.24fF
+C24 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# 0.67fF
+C25 iref iref_1 -0.02fF
+C26 iref_8 iref_7 0.05fF
+C27 iref_0 iref_1 0.05fF
+C28 iref_5 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# 0.24fF
+C29 iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.02fF
+C30 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# iref_1 0.24fF
+C31 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vdd 0.24fF
+C32 iref_9 iref -0.01fF
+C33 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# m1_20168_984# -0.39fF
+C34 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C35 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# 0.54fF
+C36 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
+C37 iref vdd -0.07fF
+C38 iref VSUBS 32.42fF
+C39 iref_4 VSUBS 1.17fF
+C40 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# VSUBS 2.60fF
+C41 iref_3 VSUBS 0.64fF
+C42 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# VSUBS 2.60fF
+C43 iref_2 VSUBS -1.26fF
+C44 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# VSUBS 2.60fF
+C45 iref_1 VSUBS -0.80fF
+C46 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# VSUBS 2.60fF
+C47 m1_20168_984# VSUBS 56.92fF
+C48 vdd VSUBS 416.01fF
+C49 iref_0 VSUBS 1.88fF
+C50 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# VSUBS 2.60fF
+C51 iref_9 VSUBS -1.13fF
+C52 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# VSUBS 2.60fF
+C53 iref_7 VSUBS -1.38fF
+C54 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# VSUBS 2.60fF
+C55 iref_8 VSUBS -1.19fF
+C56 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# VSUBS 2.60fF
+C57 iref_6 VSUBS -1.00fF
+C58 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# VSUBS 2.60fF
+C59 iref_5 VSUBS 1.40fF
+C60 sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# VSUBS 2.60fF
+.ends
+
+.subckt mimcap_decoup_1x5 VSUBS t b
+Xdecap[0] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[1] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[2] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[3] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[4] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+C0 b VSUBS 68.24fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C1 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C2 c1_110_n4150# m3_10_n4250# 81.11fF
+C3 m3_n4309_50# m3_10_n4250# 1.75fF
+C4 m3_n4309_n4250# m3_10_n4250# 1.75fF
+C5 c1_n4209_n4150# c1_110_n4150# 1.32fF
+C6 c1_n4209_n4150# m3_n4309_50# 38.10fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 in out 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_30_n300# a_n88_n300# 0.61fF
+C1 a_n88_n300# a_n118_n388# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in cap3_loop_filter_0/in 0.79fF
+C1 in vc_pex 0.18fF
+C2 in D0_cap 0.07fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt top_pll_v2 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd pswitch vdd charge_pump_0/w_2544_775#
++ ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd in_ref
++ vco_vctrl Down w_13905_n238# vss D0_vco iref_cp ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
++ out_to_div DO_cap nDown biasp out_to_pad Up nUp
+Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
++ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
++ vss vdd buffer_salida
+Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd vss ring_osc_0/csvco_branch_2/vbp
++ ring_osc_0/csvco_branch_0/inverter_csvco_0/vss D0_vco ring_osc_0/csvco_branch_2/cap_vco_0/t
++ vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
++ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
++ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
++ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 pswitch nDown 0.53fF
+C1 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
+C2 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C3 div_5_nQ0 out_by_2 0.32fF
+C4 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C5 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C6 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
+C7 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C8 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C9 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
+C10 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C11 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.33fF
+C12 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
+C13 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C14 nDown nUp -0.09fF
+C15 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# n_out_by_2 0.01fF
+C16 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C17 vdd nUp 0.05fF
+C18 Down nDown 2.55fF
+C19 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
+C20 vdd Up 0.28fF
+C21 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C22 pswitch nUp 0.85fF
+C23 nDown biasp 0.26fF
+C24 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C25 vdd iref_cp 0.15fF
+C26 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C27 pswitch Up 1.98fF
+C28 div_5_Q1_shift out_div_by_5 0.05fF
+C29 nswitch nDown 0.76fF
+C30 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C31 out_by_2 vdd 0.97fF
+C32 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
+C33 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C34 div_5_Q1 n_out_by_2 1.04fF
+C35 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C36 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
+C37 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C38 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
+C39 Up nUp 2.72fF
+C40 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C41 vco_vctrl n_out_by_2 0.52fF
+C42 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C43 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
+C44 div_5_Q0 n_out_by_2 -0.12fF
+C45 vdd out_div_by_5 0.28fF
+C46 div_5_nQ2 n_out_by_2 0.10fF
+C47 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C48 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C49 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C50 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C51 vdd vco_vctrl -1.02fF
+C52 biasp nUp -0.17fF
+C53 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C54 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
+C55 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C56 Down iref_cp 0.09fF
+C57 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C58 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
+C59 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
+C60 out_to_buffer out_to_div 0.13fF
+C61 Up biasp 0.26fF
+C62 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C63 Down biasp 1.24fF
+C64 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
+C65 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C66 Down nswitch 0.54fF
+C67 div_5_nQ0 n_out_by_2 0.10fF
+C68 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
+C69 out_to_div vdd 0.21fF
+C70 div_by_5_0/DFlipFlop_2/latch_diff_1/nD n_out_by_2 0.24fF
+C71 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C72 vco_vctrl nUp 0.02fF
+C73 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C74 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C75 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C76 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C77 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C78 vdd buffer_salida_0/a_678_n100# 0.24fF
+C79 vdd lf_vc 0.02fF
+C80 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C81 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C82 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
+C83 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
+C84 out_by_2 div_5_Q1 0.42fF
+C85 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C86 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
+C87 out_by_2 vco_vctrl 0.53fF
+C88 out_by_2 div_5_Q0 0.09fF
+C89 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C90 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C91 div_5_nQ2 out_by_2 0.16fF
+C92 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C93 nswitch vco_vctrl -0.06fF
+C94 div_5_Q1 out_div_by_5 0.01fF
+C95 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
+C96 out_to_buffer vdd 0.07fF
+C97 vdd n_out_by_2 1.03fF
+C98 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
+C99 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
+C100 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
+C101 vco_vctrl div_5_Q1 0.14fF
+C102 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C103 vdd nDown 0.22fF
+C104 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C105 vdd QA -0.04fF
+C106 div_5_Q0 vco_vctrl 0.48fF
+C107 D0_vco vdd 0.03fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C118 QB vss 4.46fF
+C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss -0.40fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 pfd_reset vss 2.17fF
+C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C132 QA vss 4.31fF
+C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 5.50fF
+C141 Up vss 2.37fF
+C142 Down vss 7.92fF
+C143 nDown vss -2.20fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_5_Q1 vss 4.28fF
+C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C158 div_5_nQ0 vss 0.59fF
+C159 div_5_Q0 vss 0.01fF
+C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_first_buffer vss 2.88fF
+C196 out_to_div vss 4.46fF
+C197 out_to_buffer vss 1.57fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 D0_vco vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 buffer_salida_0/a_3996_n100# vss 48.29fF
+C213 out_to_pad vss 7.50fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C217 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C218 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C219 out_buffer_div_2 vss 1.60fF
+C220 n_out_buffer_div_2 vss 1.63fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 lf_vc vss -59.89fF
+C232 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C233 DO_cap vss 0.01fF
+C234 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C235 nswitch vss 3.73fF
+C236 biasp vss 5.44fF
+C237 iref_cp vss 2.81fF
+C238 vco_vctrl vss -21.20fF
+C239 pswitch vss 3.57fF
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7]
++ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
++ io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
++ io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
++ io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9]
++ io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14]
++ io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1]
++ io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25]
++ io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7]
++ io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
++ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20]
++ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3]
++ io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10]
++ io_out[11] io_out[12] io_out[13] io_out[14] io_out[15] io_out[16] io_out[17] io_out[18]
++ io_out[19] io_out[1] io_out[20] io_out[21] io_out[22] io_out[23] io_out[24] io_out[25]
++ io_out[26] io_out[2] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8]
++ io_out[9] la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103]
++ la_data_in[104] la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108]
++ la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113]
++ la_data_in[114] la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118]
++ la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123]
++ la_data_in[124] la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13]
++ la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19]
++ la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24]
++ la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2]
++ la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35]
++ la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40]
++ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46]
++ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51]
++ la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57]
++ la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62]
++ la_data_in[63] la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68]
++ la_data_in[69] la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73]
++ la_data_in[74] la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79]
++ la_data_in[7] la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84]
++ la_data_in[85] la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8]
++ la_data_in[90] la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95]
++ la_data_in[96] la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0]
++ la_data_out[100] la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104]
++ la_data_out[105] la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109]
++ la_data_out[10] la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113]
++ la_data_out[114] la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118]
++ la_data_out[119] la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122]
++ la_data_out[123] la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127]
++ la_data_out[12] la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16]
++ la_data_out[17] la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21]
++ la_data_out[22] la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26]
++ la_data_out[27] la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31]
++ la_data_out[32] la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36]
++ la_data_out[37] la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41]
++ la_data_out[42] la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46]
++ la_data_out[47] la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51]
++ la_data_out[52] la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56]
++ la_data_out[57] la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61]
++ la_data_out[62] la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66]
++ la_data_out[67] la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71]
++ la_data_out[72] la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76]
++ la_data_out[77] la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81]
++ la_data_out[82] la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86]
++ la_data_out[87] la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91]
++ la_data_out[92] la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96]
++ la_data_out[97] la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100]
++ la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107]
++ la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113]
++ la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11]
++ la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126]
++ la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17]
++ la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23]
++ la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2]
++ la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36]
++ la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42]
++ la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49]
++ la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55]
++ la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61]
++ la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68]
++ la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74]
++ la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80]
++ la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87]
++ la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93]
++ la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9]
++ user_clock2 user_irq[0] user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2
++ vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11]
++ wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17]
++ wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22]
++ wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28]
++ wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4]
++ wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0]
++ wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15]
++ wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20]
++ wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26]
++ wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31]
++ wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9]
++ wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14]
++ wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1]
++ wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25]
++ wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
++ wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
++ wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+Xres_amp_top_0 vssa1 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ vdda1 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# bias_0/iref_8
++ res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out
++ bias_0/iref_6 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1
++ res_amp_top_0/res_amp_lin_prog_0/outn bias_0/iref_7 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363#
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ gpio_noesd[3] bias_0/iref_5 res_amp_top_0/res_amp_lin_prog_0/outp res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB io_analog[2]
++ res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828#
++ io_analog[3] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA gpio_noesd[1]
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out res_amp_top_0/res_amp_lin_prog_0/outp_cap
++ gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/clk res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA io_analog[6]
++ gpio_noesd[5] res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out gpio_noesd[6]
++ res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ gpio_noesd[2] io_analog[0] res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ io_analog[1] io_analog[4] res_amp_top_0/res_amp_sync_v2_0/rst res_amp_top
+Xtop_pll_v1_0 top_pll_v1_0/vco_vctrl vdda1 top_pll_v1_0/pswitch top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ top_pll_v1_0/charge_pump_0/w_2544_775# top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp
++ top_pll_v1_0/biasp io_analog[10] top_pll_v1_0/Down vssa1 vssa1 gpio_noesd[7] top_pll_v1_0/buffer_salida_0/a_3996_n100#
++ top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v1_0/QA top_pll_v1_0/charge_pump_0/w_1008_774#
++ bias_0/iref_2 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd top_pll_v1_0/out_to_div
++ top_pll_v1_0/nDown io_analog[9] top_pll_v1_0/Up top_pll_v1_0/nUp top_pll_v1
+Xtop_pll_v1_1 top_pll_v1_1/vco_vctrl vdda1 top_pll_v1_1/pswitch top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ top_pll_v1_1/charge_pump_0/w_2544_775# top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp
++ top_pll_v1_1/biasp io_analog[10] top_pll_v1_1/Down vssa1 vssa1 gpio_noesd[7] top_pll_v1_1/buffer_salida_0/a_3996_n100#
++ top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v1_1/QA top_pll_v1_1/charge_pump_0/w_1008_774#
++ bias_0/iref_0 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd top_pll_v1_1/out_to_div
++ top_pll_v1_1/nDown io_analog[7] top_pll_v1_1/Up top_pll_v1_1/nUp top_pll_v1
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xbias_0 vssa1 vdda1 bias_0/iref_0 bias_0/iref_1 bias_0/iref_2 bias_0/iref_5 bias_0/iref_6
++ bias_0/iref_7 bias_0/iref_8 bias_0/iref_9 io_analog[5] bias
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xmimcap_decoup_1x5_0[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_0[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_0[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xmimcap_decoup_1x5_2[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_2[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_2[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xtop_pll_v2_0 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v2_0/pswitch
++ vdda1 top_pll_v2_0/charge_pump_0/w_2544_775# top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp
++ top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd io_analog[10] top_pll_v2_0/vco_vctrl
++ top_pll_v2_0/Down vssa1 vssa1 gpio_noesd[7] bias_0/iref_1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
++ top_pll_v2_0/out_to_div gpio_noesd[8] top_pll_v2_0/nDown top_pll_v2_0/biasp io_analog[8]
++ top_pll_v2_0/Up top_pll_v2_0/nUp top_pll_v2
+C0 bias_0/iref_7 bias_0/iref_5 10.35fF
+C1 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.21fF
+C2 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/clk 0.39fF
+C3 io_analog[4] bias_0/iref_9 15.97fF
+C4 bias_0/iref_8 bias_0/iref_7 13.23fF
+C5 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp 1.14fF
+C6 bias_0/iref_7 bias_0/iref_6 17.40fF
+C7 io_analog[10] gpio_noesd[8] 20.65fF
+C8 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_7 0.40fF
+C9 bias_0/iref_1 top_pll_v2_0/nUp 0.22fF
+C10 vdda1 io_analog[1] 76.56fF
+C11 vdda1 gpio_noesd[5] 124.75fF
+C12 io_analog[5] m3_222594_702300# 0.53fF
+C13 io_analog[3] gpio_noesd[5] 0.12fF
+C14 vdda1 top_pll_v1_0/nUp 0.01fF
+C15 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.72fF
+C16 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in 0.18fF
+C17 vdda1 bias_0/iref_2 3.90fF
+C18 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# gpio_noesd[5] 0.16fF
+C19 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_8 0.37fF
+C20 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[5] 0.26fF
+C21 bias_0/iref_1 top_pll_v2_0/Up 0.54fF
+C22 vdda1 top_pll_v1_0/pswitch 0.38fF
+C23 vdda1 bias_0/iref_5 30.67fF
+C24 vdda1 gpio_noesd[3] 120.88fF
+C25 vdda1 bias_0/iref_8 31.37fF
+C26 gpio_noesd[6] gpio_noesd[5] 0.05fF
+C27 bias_0/iref_2 io_analog[7] 13.22fF
+C28 vdda1 bias_0/iref_6 29.75fF
+C29 io_analog[3] bias_0/iref_5 13.88fF
+C30 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b gpio_noesd[1] 0.23fF
+C31 bias_0/iref_8 io_analog[3] 13.88fF
+C32 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outp 0.61fF
+C33 io_analog[3] bias_0/iref_6 13.88fF
+C34 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.78fF
+C35 top_pll_v1_0/charge_pump_0/w_2544_775# bias_0/iref_2 0.02fF
+C36 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_7 0.45fF
+C37 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in -0.70fF
+C38 vdda1 top_pll_v1_0/vco_vctrl 0.43fF
+C39 gpio_noesd[4] vdda1 117.64fF
+C40 vdda1 top_pll_v2_0/pswitch 0.34fF
+C41 gpio_noesd[4] io_analog[3] -0.78fF
+C42 vdda1 io_analog[9] 30.05fF
+C43 gpio_noesd[2] gpio_noesd[1] 0.30fF
+C44 bias_0/iref_0 top_pll_v1_1/nDown 0.74fF
+C45 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.22fF
+C46 top_pll_v1_0/QA io_analog[10] 0.03fF
+C47 io_analog[6] bias_0/iref_1 13.22fF
+C48 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out gpio_noesd[1] 0.21fF
+C49 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 -0.05fF
+C50 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA 0.49fF
+C51 io_analog[4] io_clamp_low[0] 0.53fF
+C52 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.17fF
+C53 io_analog[6] bias_0/iref_0 6.93fF
+C54 res_amp_top_0/res_amp_lin_prog_0/outp gpio_noesd[5] 0.44fF
+C55 vdda1 top_pll_v2_0/biasp 0.03fF
+C56 vdda1 top_pll_v1_0/biasp 0.03fF
+C57 io_analog[2] bias_0/iref_7 13.88fF
+C58 io_analog[6] io_clamp_high[2] 0.53fF
+C59 vdda1 bias_0/iref_9 30.24fF
+C60 io_analog[7] top_pll_v1_1/buffer_salida_0/a_3996_n100# -0.08fF
+C61 io_analog[6] io_analog[4] 0.59fF
+C62 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB 0.19fF
+C63 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl gpio_noesd[5] 0.33fF
+C64 bias_0/iref_9 io_analog[3] 13.88fF
+C65 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in 0.20fF
+C66 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.94fF
+C67 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp 1.01fF
+C68 bias_0/iref_2 top_pll_v1_0/nUp 0.70fF
+C69 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# -0.11fF
+C70 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.46fF
+C71 io_analog[4] bias_0/iref_7 15.97fF
+C72 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.12fF
+C73 gpio_noesd[4] gpio_noesd[5] 4.67fF
+C74 bias_0/iref_0 top_pll_v1_1/Up 0.74fF
+C75 vdda1 bias_0/iref_1 15.26fF
+C76 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outp -0.31fF
+C77 vdda1 top_pll_v2_0/nUp 0.01fF
+C78 vdda1 io_analog[2] 25.90fF
+C79 bias_0/iref_8 bias_0/iref_5 10.19fF
+C80 vdda1 bias_0/iref_0 15.18fF
+C81 bias_0/iref_5 bias_0/iref_6 29.11fF
+C82 io_analog[2] io_analog[3] 0.14fF
+C83 io_analog[7] bias_0/iref_1 13.22fF
+C84 gpio_noesd[2] vdda1 214.16fF
+C85 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_8 0.11fF
+C86 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.07fF
+C87 bias_0/iref_1 top_pll_v2_0/nDown 0.54fF
+C88 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[5] 0.68fF
+C89 vdda1 gpio_noesd[7] 120.83fF
+C90 bias_0/iref_2 io_analog[9] 14.44fF
+C91 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.17fF
+C92 gpio_noesd[7] top_pll_v2_0/vco_vctrl 0.05fF
+C93 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out 0.33fF
+C94 io_analog[4] vdda1 182.26fF
+C95 gpio_noesd[7] top_pll_v1_0/out_to_div 0.23fF
+C96 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA gpio_noesd[1] 0.29fF
+C97 io_analog[5] m3_226242_702300# 0.53fF
+C98 gpio_noesd[7] top_pll_v1_1/vco_vctrl 0.04fF
+C99 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_1008_774# 0.21fF
+C100 bias_0/iref_9 gpio_noesd[5] 1.30fF
+C101 vdda1 io_analog[8] 29.93fF
+C102 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out 0.19fF
+C103 gpio_noesd[7] gpio_noesd[8] 1.88fF
+C104 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.12fF
+C105 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.17fF
+C106 gpio_noesd[1] vdda1 214.54fF
+C107 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[6] 2.12fF
+C108 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outn 0.45fF
+C109 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.12fF
+C110 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/clk 0.21fF
+C111 top_pll_v1_0/biasp bias_0/iref_2 3.20fF
+C112 top_pll_v1_1/pswitch vdda1 0.48fF
+C113 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_5 0.45fF
+C114 bias_0/iref_1 top_pll_v2_0/charge_pump_0/w_2544_775# 0.09fF
+C115 gpio_noesd[7] top_pll_v1_1/out_to_div 0.15fF
+C116 gpio_noesd[7] top_pll_v2_0/out_to_div 0.23fF
+C117 gpio_noesd[7] io_analog[10] 29.88fF
+C118 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.42fF
+C119 res_amp_top_0/res_amp_sync_v2_0/rst bias_0/iref_9 0.39fF
+C120 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_6 0.15fF
+C121 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/clk -0.01fF
+C122 vdda1 top_pll_v1_0/buffer_salida_0/a_3996_n100# 0.06fF
+C123 io_analog[6] vdda1 124.15fF
+C124 bias_0/iref_9 bias_0/iref_8 9.89fF
+C125 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# 0.18fF
+C126 io_analog[2] gpio_noesd[5] 0.09fF
+C127 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C128 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_7 0.37fF
+C129 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in gpio_noesd[5] 0.47fF
+C130 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[3] 0.03fF
+C131 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_2544_775# 0.21fF
+C132 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[5] 0.44fF
+C133 res_amp_top_0/res_amp_lin_prog_0/outn gpio_noesd[5] 1.42fF
+C134 gpio_noesd[4] bias_0/iref_9 -0.25fF
+C135 vdda1 bias_0/iref_7 33.08fF
+C136 bias_0/iref_5 io_analog[5] 0.09fF
+C137 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB gpio_noesd[5] 0.14fF
+C138 bias_0/iref_0 top_pll_v1_1/nUp 0.74fF
+C139 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp 2.10fF
+C140 io_analog[3] bias_0/iref_7 13.88fF
+C141 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in gpio_noesd[5] 0.05fF
+C142 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.04fF
+C143 io_analog[2] bias_0/iref_5 13.88fF
+C144 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp gpio_noesd[5] 0.54fF
+C145 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out 0.57fF
+C146 io_analog[2] bias_0/iref_8 13.88fF
+C147 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[5] 0.14fF
+C148 io_analog[2] bias_0/iref_6 13.88fF
+C149 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.01fF
+C150 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out 0.21fF
+C151 io_analog[6] io_clamp_low[2] 0.53fF
+C152 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.01fF
+C153 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in bias_0/iref_5 0.46fF
+C154 io_analog[4] io_clamp_high[0] 0.53fF
+C155 gpio_noesd[4] io_analog[2] -0.21fF
+C156 bias_0/iref_5 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.46fF
+C157 io_analog[4] bias_0/iref_5 15.97fF
+C158 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.42fF
+C159 bias_0/iref_8 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.34fF
+C160 io_analog[4] bias_0/iref_8 15.97fF
+C161 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk -0.13fF
+C162 bias_0/iref_2 io_analog[8] 14.44fF
+C163 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outn -1.06fF
+C164 vdda1 top_pll_v2_0/vco_vctrl 0.59fF
+C165 io_analog[4] bias_0/iref_6 15.97fF
+C166 vdda1 io_analog[0] 76.77fF
+C167 vdda1 io_analog[3] 25.90fF
+C168 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.08fF
+C169 top_pll_v1_0/vco_vctrl gpio_noesd[7] 0.05fF
+C170 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# bias_0/iref_7 0.09fF
+C171 vdda1 io_analog[7] 29.48fF
+C172 bias_0/iref_2 top_pll_v1_0/Up 0.70fF
+C173 vdda1 top_pll_v1_1/vco_vctrl 0.54fF
+C174 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C175 bias_0/iref_0 top_pll_v1_1/Down 1.08fF
+C176 gpio_noesd[5] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.32fF
+C177 vdda1 gpio_noesd[8] 76.96fF
+C178 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp 0.17fF
+C179 bias_0/iref_1 top_pll_v2_0/biasp 2.20fF
+C180 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b 0.31fF
+C181 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[4] -0.08fF
+C182 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.04fF
+C183 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in 0.23fF
+C184 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/clk 0.37fF
+C185 bias_0/iref_2 top_pll_v1_0/nDown 0.70fF
+C186 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.04fF
+C187 io_analog[6] bias_0/iref_2 54.67fF
+C188 vdda1 gpio_noesd[6] 53.94fF
+C189 bias_0/iref_1 top_pll_v2_0/Down 0.91fF
+C190 bias_0/iref_9 io_analog[2] 13.88fF
+C191 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in 0.12fF
+C192 vdda1 io_analog[10] 0.01fF
+C193 bias_0/iref_0 top_pll_v1_1/biasp 3.13fF
+C194 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out 0.38fF
+C195 vdda1 top_pll_v2_0/buffer_salida_0/a_3996_n100# 0.05fF
+C196 bias_0/iref_2 top_pll_v1_0/Down 1.11fF
+C197 io_in_3v3[0] vssa1 0.41fF
+C198 io_oeb[26] vssa1 0.61fF
+C199 io_in[0] vssa1 0.41fF
+C200 io_out[26] vssa1 0.61fF
+C201 io_out[0] vssa1 0.41fF
+C202 io_in[26] vssa1 0.61fF
+C203 io_oeb[0] vssa1 0.41fF
+C204 io_in_3v3[26] vssa1 0.61fF
+C205 io_in_3v3[1] vssa1 0.41fF
+C206 io_oeb[25] vssa1 0.61fF
+C207 io_in[1] vssa1 0.41fF
+C208 io_out[25] vssa1 0.61fF
+C209 io_out[1] vssa1 0.41fF
+C210 io_in[25] vssa1 0.61fF
+C211 io_oeb[1] vssa1 0.41fF
+C212 io_in_3v3[25] vssa1 0.61fF
+C213 io_in_3v3[2] vssa1 0.41fF
+C214 io_oeb[24] vssa1 0.61fF
+C215 io_in[2] vssa1 0.41fF
+C216 io_out[24] vssa1 0.61fF
+C217 io_out[2] vssa1 0.41fF
+C218 io_in[24] vssa1 0.61fF
+C219 io_oeb[2] vssa1 -0.20fF
+C220 io_in_3v3[3] vssa1 0.41fF
+C221 gpio_noesd[17] vssa1 0.61fF
+C222 io_in[3] vssa1 0.41fF
+C223 gpio_analog[17] vssa1 0.61fF
+C224 io_out[3] vssa1 0.41fF
+C225 io_oeb[3] vssa1 0.41fF
+C226 io_in_3v3[4] vssa1 0.41fF
+C227 io_in[4] vssa1 0.41fF
+C228 io_out[4] vssa1 0.41fF
+C229 io_oeb[4] vssa1 0.41fF
+C230 io_oeb[23] vssa1 0.61fF
+C231 io_out[23] vssa1 0.61fF
+C232 io_in[23] vssa1 0.61fF
+C233 io_in_3v3[23] vssa1 0.61fF
+C234 gpio_noesd[16] vssa1 0.61fF
+C235 io_in_3v3[5] vssa1 0.41fF
+C236 io_in[5] vssa1 -0.20fF
+C237 io_out[5] vssa1 0.41fF
+C238 io_oeb[5] vssa1 0.41fF
+C239 io_oeb[22] vssa1 0.61fF
+C240 io_out[22] vssa1 0.61fF
+C241 io_in[22] vssa1 0.61fF
+C242 io_in_3v3[22] vssa1 0.61fF
+C243 gpio_analog[15] vssa1 0.61fF
+C244 io_in_3v3[6] vssa1 -0.20fF
+C245 io_in[6] vssa1 0.41fF
+C246 io_out[6] vssa1 0.41fF
+C247 io_oeb[6] vssa1 0.41fF
+C248 io_oeb[21] vssa1 0.61fF
+C249 io_out[21] vssa1 0.61fF
+C250 io_in[21] vssa1 0.61fF
+C251 io_in_3v3[21] vssa1 0.61fF
+C252 gpio_noesd[14] vssa1 0.61fF
+C253 gpio_analog[14] vssa1 0.61fF
+C254 vssd2 vssa1 -5.19fF
+C255 vssd1 vssa1 1.13fF
+C256 vdda2 vssa1 -5.19fF
+C257 io_oeb[20] vssa1 0.61fF
+C258 io_out[20] vssa1 0.61fF
+C259 io_in[20] vssa1 0.61fF
+C260 io_in_3v3[20] vssa1 0.61fF
+C261 gpio_noesd[13] vssa1 0.61fF
+C262 gpio_analog[13] vssa1 0.61fF
+C263 gpio_analog[0] vssa1 0.41fF
+C264 gpio_noesd[0] vssa1 0.41fF
+C265 io_in_3v3[7] vssa1 0.41fF
+C266 io_in[7] vssa1 0.41fF
+C267 io_out[7] vssa1 0.41fF
+C268 io_oeb[7] vssa1 0.41fF
+C269 io_oeb[19] vssa1 0.61fF
+C270 io_out[19] vssa1 0.61fF
+C271 io_in[19] vssa1 0.61fF
+C272 io_in_3v3[19] vssa1 0.61fF
+C273 gpio_noesd[12] vssa1 0.61fF
+C274 gpio_analog[12] vssa1 0.61fF
+C275 gpio_analog[1] vssa1 0.41fF
+C276 io_in_3v3[8] vssa1 0.41fF
+C277 io_in[8] vssa1 0.41fF
+C278 io_out[8] vssa1 -0.20fF
+C279 io_oeb[8] vssa1 0.41fF
+C280 gpio_analog[2] vssa1 0.41fF
+C281 io_in_3v3[9] vssa1 0.41fF
+C282 io_in[9] vssa1 0.41fF
+C283 io_out[9] vssa1 0.41fF
+C284 io_oeb[9] vssa1 0.41fF
+C285 gpio_analog[3] vssa1 0.41fF
+C286 io_in_3v3[10] vssa1 0.41fF
+C287 io_in[10] vssa1 0.41fF
+C288 io_out[10] vssa1 0.41fF
+C289 io_oeb[10] vssa1 0.41fF
+C290 gpio_analog[4] vssa1 0.41fF
+C291 io_in_3v3[11] vssa1 0.41fF
+C292 io_in[11] vssa1 0.41fF
+C293 io_out[11] vssa1 0.41fF
+C294 io_oeb[11] vssa1 0.41fF
+C295 gpio_analog[5] vssa1 0.41fF
+C296 io_in_3v3[12] vssa1 0.41fF
+C297 io_in[12] vssa1 0.41fF
+C298 io_out[12] vssa1 0.41fF
+C299 io_oeb[12] vssa1 0.41fF
+C300 gpio_analog[6] vssa1 0.60fF
+C301 io_in_3v3[13] vssa1 0.60fF
+C302 io_in[13] vssa1 0.60fF
+C303 io_out[13] vssa1 0.60fF
+C304 io_oeb[13] vssa1 0.60fF
+C305 io_oeb[18] vssa1 0.61fF
+C306 io_out[18] vssa1 0.61fF
+C307 io_in_3v3[18] vssa1 0.61fF
+C308 gpio_noesd[11] vssa1 0.61fF
+C309 gpio_analog[11] vssa1 0.61fF
+C310 io_oeb[17] vssa1 0.61fF
+C311 io_in[17] vssa1 0.61fF
+C312 io_in_3v3[17] vssa1 0.61fF
+C313 gpio_noesd[10] vssa1 0.61fF
+C314 gpio_analog[10] vssa1 0.61fF
+C315 io_out[16] vssa1 0.61fF
+C316 io_in[16] vssa1 0.61fF
+C317 io_in_3v3[16] vssa1 0.61fF
+C318 gpio_noesd[9] vssa1 0.61fF
+C319 gpio_analog[9] vssa1 0.61fF
+C320 io_oeb[15] vssa1 0.61fF
+C321 io_out[15] vssa1 0.61fF
+C322 io_in[15] vssa1 0.61fF
+C323 io_in_3v3[15] vssa1 0.61fF
+C324 vccd1 vssa1 0.85fF
+C325 gpio_analog[8] vssa1 0.61fF
+C326 io_oeb[14] vssa1 0.61fF
+C327 io_out[14] vssa1 0.61fF
+C328 io_in[14] vssa1 0.61fF
+C329 io_in_3v3[14] vssa1 0.61fF
+C330 vssa2 vssa1 1.66fF
+C331 vccd2 vssa1 0.91fF
+C332 io_clamp_high[0] vssa1 -2.60fF
+C333 io_clamp_low[0] vssa1 0.82fF
+C334 io_clamp_high[2] vssa1 0.66fF
+C335 io_clamp_low[2] vssa1 0.50fF
+C336 user_irq[2] vssa1 0.63fF
+C337 user_irq[1] vssa1 0.63fF
+C338 user_irq[0] vssa1 0.63fF
+C339 user_clock2 vssa1 0.63fF
+C340 la_oenb[127] vssa1 0.63fF
+C341 la_data_in[127] vssa1 0.63fF
+C342 la_oenb[126] vssa1 0.63fF
+C343 la_data_out[126] vssa1 0.63fF
+C344 la_data_in[126] vssa1 0.63fF
+C345 la_oenb[125] vssa1 0.63fF
+C346 la_data_out[125] vssa1 0.63fF
+C347 la_data_in[125] vssa1 0.63fF
+C348 la_oenb[124] vssa1 0.63fF
+C349 la_data_out[124] vssa1 0.63fF
+C350 la_data_in[124] vssa1 0.63fF
+C351 la_oenb[123] vssa1 0.63fF
+C352 la_data_out[123] vssa1 0.63fF
+C353 la_oenb[122] vssa1 0.63fF
+C354 la_data_out[122] vssa1 0.63fF
+C355 la_data_in[122] vssa1 0.63fF
+C356 la_oenb[121] vssa1 0.63fF
+C357 la_data_out[121] vssa1 0.63fF
+C358 la_data_in[121] vssa1 0.63fF
+C359 la_oenb[120] vssa1 0.63fF
+C360 la_data_out[120] vssa1 0.63fF
+C361 la_data_in[120] vssa1 0.63fF
+C362 la_oenb[119] vssa1 0.63fF
+C363 la_data_out[119] vssa1 0.63fF
+C364 la_data_in[119] vssa1 0.63fF
+C365 la_oenb[118] vssa1 0.63fF
+C366 la_data_out[118] vssa1 0.63fF
+C367 la_data_in[118] vssa1 0.63fF
+C368 la_oenb[117] vssa1 0.63fF
+C369 la_data_out[117] vssa1 0.63fF
+C370 la_data_in[117] vssa1 0.63fF
+C371 la_data_out[116] vssa1 0.63fF
+C372 la_data_in[116] vssa1 0.63fF
+C373 la_oenb[115] vssa1 0.63fF
+C374 la_data_out[115] vssa1 0.63fF
+C375 la_data_in[115] vssa1 0.63fF
+C376 la_oenb[114] vssa1 0.63fF
+C377 la_data_out[114] vssa1 0.63fF
+C378 la_data_in[114] vssa1 0.63fF
+C379 la_oenb[113] vssa1 0.63fF
+C380 la_data_out[113] vssa1 0.63fF
+C381 la_data_in[113] vssa1 0.63fF
+C382 la_oenb[112] vssa1 0.63fF
+C383 la_data_in[112] vssa1 0.63fF
+C384 la_oenb[111] vssa1 0.63fF
+C385 la_data_out[111] vssa1 0.63fF
+C386 la_data_in[111] vssa1 0.63fF
+C387 la_oenb[110] vssa1 0.63fF
+C388 la_data_out[110] vssa1 0.63fF
+C389 la_data_in[110] vssa1 0.63fF
+C390 la_oenb[109] vssa1 0.63fF
+C391 la_data_out[109] vssa1 0.63fF
+C392 la_data_in[109] vssa1 0.63fF
+C393 la_oenb[108] vssa1 0.63fF
+C394 la_data_out[108] vssa1 0.63fF
+C395 la_oenb[107] vssa1 0.63fF
+C396 la_data_out[107] vssa1 0.63fF
+C397 la_data_in[107] vssa1 0.63fF
+C398 la_oenb[106] vssa1 0.63fF
+C399 la_data_out[106] vssa1 0.63fF
+C400 la_oenb[105] vssa1 0.63fF
+C401 la_data_out[105] vssa1 0.63fF
+C402 la_data_in[105] vssa1 0.63fF
+C403 la_oenb[104] vssa1 0.63fF
+C404 la_data_out[104] vssa1 0.63fF
+C405 la_data_in[104] vssa1 0.63fF
+C406 la_oenb[103] vssa1 0.63fF
+C407 la_data_out[103] vssa1 0.63fF
+C408 la_data_in[103] vssa1 0.63fF
+C409 la_oenb[102] vssa1 0.63fF
+C410 la_data_out[102] vssa1 0.63fF
+C411 la_data_in[102] vssa1 0.63fF
+C412 la_data_out[101] vssa1 0.63fF
+C413 la_data_in[101] vssa1 0.63fF
+C414 la_oenb[100] vssa1 0.63fF
+C415 la_data_out[100] vssa1 0.63fF
+C416 la_data_in[100] vssa1 0.63fF
+C417 la_oenb[99] vssa1 0.63fF
+C418 la_data_out[99] vssa1 0.63fF
+C419 la_data_in[99] vssa1 0.63fF
+C420 la_oenb[98] vssa1 0.63fF
+C421 la_data_out[98] vssa1 0.63fF
+C422 la_data_in[98] vssa1 0.63fF
+C423 la_oenb[97] vssa1 0.63fF
+C424 la_data_in[97] vssa1 0.63fF
+C425 la_oenb[96] vssa1 0.63fF
+C426 la_data_out[96] vssa1 0.63fF
+C427 la_data_in[96] vssa1 0.63fF
+C428 la_oenb[95] vssa1 0.63fF
+C429 la_data_out[95] vssa1 0.63fF
+C430 la_data_in[95] vssa1 0.63fF
+C431 la_oenb[94] vssa1 0.63fF
+C432 la_data_out[94] vssa1 0.63fF
+C433 la_data_in[94] vssa1 0.63fF
+C434 la_oenb[93] vssa1 0.63fF
+C435 la_data_out[93] vssa1 0.63fF
+C436 la_oenb[92] vssa1 0.63fF
+C437 la_data_out[92] vssa1 0.63fF
+C438 la_data_in[92] vssa1 0.63fF
+C439 la_oenb[91] vssa1 0.63fF
+C440 la_data_out[91] vssa1 0.63fF
+C441 la_oenb[90] vssa1 0.63fF
+C442 la_data_out[90] vssa1 0.63fF
+C443 la_data_in[90] vssa1 0.63fF
+C444 la_oenb[89] vssa1 0.63fF
+C445 la_data_out[89] vssa1 0.63fF
+C446 la_data_in[89] vssa1 0.63fF
+C447 la_oenb[88] vssa1 0.63fF
+C448 la_data_out[88] vssa1 0.63fF
+C449 la_data_in[88] vssa1 0.63fF
+C450 la_oenb[87] vssa1 0.63fF
+C451 la_data_out[87] vssa1 0.63fF
+C452 la_data_in[87] vssa1 0.63fF
+C453 la_data_out[86] vssa1 0.63fF
+C454 la_data_in[86] vssa1 0.63fF
+C455 la_oenb[85] vssa1 0.63fF
+C456 la_data_out[85] vssa1 0.63fF
+C457 la_data_in[85] vssa1 0.63fF
+C458 la_oenb[84] vssa1 0.63fF
+C459 la_data_out[84] vssa1 0.63fF
+C460 la_data_in[84] vssa1 0.63fF
+C461 la_oenb[83] vssa1 0.63fF
+C462 la_data_out[83] vssa1 0.63fF
+C463 la_data_in[83] vssa1 0.63fF
+C464 la_oenb[82] vssa1 0.63fF
+C465 la_data_in[82] vssa1 0.63fF
+C466 la_oenb[81] vssa1 0.63fF
+C467 la_data_out[81] vssa1 0.63fF
+C468 la_data_in[81] vssa1 0.63fF
+C469 la_oenb[80] vssa1 0.63fF
+C470 la_data_out[80] vssa1 0.63fF
+C471 la_data_in[80] vssa1 0.63fF
+C472 la_oenb[79] vssa1 0.63fF
+C473 la_data_out[79] vssa1 0.63fF
+C474 la_data_in[79] vssa1 0.63fF
+C475 la_oenb[78] vssa1 0.63fF
+C476 la_data_out[78] vssa1 0.63fF
+C477 la_data_in[78] vssa1 0.63fF
+C478 la_oenb[77] vssa1 0.63fF
+C479 la_data_out[77] vssa1 0.63fF
+C480 la_data_in[77] vssa1 0.63fF
+C481 la_oenb[76] vssa1 0.63fF
+C482 la_data_out[76] vssa1 0.63fF
+C483 la_oenb[75] vssa1 0.63fF
+C484 la_data_out[75] vssa1 0.63fF
+C485 la_data_in[75] vssa1 0.63fF
+C486 la_oenb[74] vssa1 0.63fF
+C487 la_data_out[74] vssa1 0.63fF
+C488 la_data_in[74] vssa1 0.63fF
+C489 la_oenb[73] vssa1 0.63fF
+C490 la_data_out[73] vssa1 0.63fF
+C491 la_data_in[73] vssa1 0.63fF
+C492 la_oenb[72] vssa1 0.63fF
+C493 la_data_out[72] vssa1 0.63fF
+C494 la_data_in[72] vssa1 0.63fF
+C495 la_data_out[71] vssa1 0.63fF
+C496 la_data_in[71] vssa1 0.63fF
+C497 la_oenb[70] vssa1 0.63fF
+C498 la_data_out[70] vssa1 0.63fF
+C499 la_data_in[70] vssa1 0.63fF
+C500 la_oenb[69] vssa1 0.63fF
+C501 la_data_out[69] vssa1 0.63fF
+C502 la_data_in[69] vssa1 0.63fF
+C503 la_oenb[68] vssa1 0.63fF
+C504 la_data_out[68] vssa1 0.63fF
+C505 la_data_in[68] vssa1 0.63fF
+C506 la_oenb[67] vssa1 0.63fF
+C507 la_data_in[67] vssa1 0.63fF
+C508 la_oenb[66] vssa1 0.63fF
+C509 la_data_out[66] vssa1 0.63fF
+C510 la_data_in[66] vssa1 0.63fF
+C511 la_oenb[65] vssa1 0.63fF
+C512 la_data_out[65] vssa1 0.26fF
+C513 la_data_in[65] vssa1 0.63fF
+C514 la_oenb[64] vssa1 0.63fF
+C515 la_data_out[64] vssa1 0.63fF
+C516 la_data_in[64] vssa1 0.63fF
+C517 la_oenb[63] vssa1 0.63fF
+C518 la_data_out[63] vssa1 0.63fF
+C519 la_data_in[63] vssa1 0.63fF
+C520 la_oenb[62] vssa1 0.63fF
+C521 la_data_out[62] vssa1 0.63fF
+C522 la_data_in[62] vssa1 0.63fF
+C523 la_oenb[61] vssa1 0.63fF
+C524 la_data_out[61] vssa1 0.63fF
+C525 la_oenb[60] vssa1 0.63fF
+C526 la_data_out[60] vssa1 0.63fF
+C527 la_data_in[60] vssa1 0.63fF
+C528 la_oenb[59] vssa1 0.63fF
+C529 la_data_out[59] vssa1 0.63fF
+C530 la_data_in[59] vssa1 0.63fF
+C531 la_oenb[58] vssa1 0.63fF
+C532 la_data_out[58] vssa1 0.63fF
+C533 la_data_in[58] vssa1 0.63fF
+C534 la_oenb[57] vssa1 0.63fF
+C535 la_data_out[57] vssa1 0.63fF
+C536 la_data_in[57] vssa1 0.63fF
+C537 la_data_out[56] vssa1 0.63fF
+C538 la_data_in[56] vssa1 0.63fF
+C539 la_oenb[55] vssa1 0.63fF
+C540 la_data_out[55] vssa1 0.63fF
+C541 la_data_in[55] vssa1 0.63fF
+C542 la_oenb[54] vssa1 0.63fF
+C543 la_data_out[54] vssa1 0.63fF
+C544 la_data_in[54] vssa1 0.63fF
+C545 la_oenb[53] vssa1 0.63fF
+C546 la_data_out[53] vssa1 0.63fF
+C547 la_data_in[53] vssa1 0.63fF
+C548 la_oenb[52] vssa1 0.63fF
+C549 la_data_in[52] vssa1 0.63fF
+C550 la_oenb[51] vssa1 0.63fF
+C551 la_data_out[51] vssa1 0.63fF
+C552 la_data_in[51] vssa1 0.63fF
+C553 la_oenb[50] vssa1 0.63fF
+C554 la_data_in[50] vssa1 0.63fF
+C555 la_oenb[49] vssa1 0.63fF
+C556 la_data_out[49] vssa1 0.63fF
+C557 la_data_in[49] vssa1 0.63fF
+C558 la_oenb[48] vssa1 0.63fF
+C559 la_data_out[48] vssa1 0.63fF
+C560 la_data_in[48] vssa1 0.63fF
+C561 la_oenb[47] vssa1 0.63fF
+C562 la_data_out[47] vssa1 0.63fF
+C563 la_data_in[47] vssa1 0.63fF
+C564 la_oenb[46] vssa1 0.63fF
+C565 la_data_out[46] vssa1 0.63fF
+C566 la_oenb[45] vssa1 0.63fF
+C567 la_data_out[45] vssa1 0.63fF
+C568 la_data_in[45] vssa1 0.63fF
+C569 la_oenb[44] vssa1 0.63fF
+C570 la_data_out[44] vssa1 0.63fF
+C571 la_data_in[44] vssa1 0.63fF
+C572 la_oenb[43] vssa1 0.63fF
+C573 la_data_out[43] vssa1 0.63fF
+C574 la_data_in[43] vssa1 0.63fF
+C575 la_oenb[42] vssa1 0.63fF
+C576 la_data_out[42] vssa1 0.63fF
+C577 la_data_in[42] vssa1 0.63fF
+C578 la_data_out[41] vssa1 0.63fF
+C579 la_data_in[41] vssa1 0.63fF
+C580 la_oenb[40] vssa1 0.63fF
+C581 la_data_out[40] vssa1 0.63fF
+C582 la_data_in[40] vssa1 0.63fF
+C583 la_oenb[39] vssa1 0.63fF
+C584 la_data_out[39] vssa1 0.63fF
+C585 la_data_in[39] vssa1 0.63fF
+C586 la_oenb[38] vssa1 0.63fF
+C587 la_data_out[38] vssa1 0.63fF
+C588 la_data_in[38] vssa1 0.63fF
+C589 la_oenb[37] vssa1 0.63fF
+C590 la_data_out[37] vssa1 0.26fF
+C591 la_data_in[37] vssa1 0.63fF
+C592 la_oenb[36] vssa1 0.63fF
+C593 la_data_out[36] vssa1 0.63fF
+C594 la_data_in[36] vssa1 0.63fF
+C595 la_oenb[35] vssa1 0.63fF
+C596 la_data_in[35] vssa1 0.63fF
+C597 la_oenb[34] vssa1 0.63fF
+C598 la_data_out[34] vssa1 0.63fF
+C599 la_data_in[34] vssa1 0.63fF
+C600 la_oenb[33] vssa1 0.63fF
+C601 la_data_out[33] vssa1 0.63fF
+C602 la_data_in[33] vssa1 0.63fF
+C603 la_oenb[32] vssa1 0.63fF
+C604 la_data_out[32] vssa1 0.63fF
+C605 la_data_in[32] vssa1 0.63fF
+C606 la_oenb[31] vssa1 0.63fF
+C607 la_data_out[31] vssa1 0.63fF
+C608 la_oenb[30] vssa1 0.63fF
+C609 la_data_out[30] vssa1 0.63fF
+C610 la_data_in[30] vssa1 0.63fF
+C611 la_oenb[29] vssa1 0.63fF
+C612 la_data_out[29] vssa1 0.63fF
+C613 la_data_in[29] vssa1 0.63fF
+C614 la_oenb[28] vssa1 0.63fF
+C615 la_data_out[28] vssa1 0.63fF
+C616 la_data_in[28] vssa1 0.63fF
+C617 la_oenb[27] vssa1 0.63fF
+C618 la_data_out[27] vssa1 0.63fF
+C619 la_data_in[27] vssa1 0.63fF
+C620 la_data_out[26] vssa1 0.63fF
+C621 la_data_in[26] vssa1 0.63fF
+C622 la_oenb[25] vssa1 0.63fF
+C623 la_data_out[25] vssa1 0.63fF
+C624 la_data_in[25] vssa1 0.63fF
+C625 la_oenb[24] vssa1 0.63fF
+C626 la_data_out[24] vssa1 0.63fF
+C627 la_data_in[24] vssa1 0.63fF
+C628 la_oenb[23] vssa1 0.63fF
+C629 la_data_out[23] vssa1 0.63fF
+C630 la_data_in[23] vssa1 0.63fF
+C631 la_oenb[22] vssa1 0.63fF
+C632 la_data_out[22] vssa1 0.63fF
+C633 la_data_in[22] vssa1 0.63fF
+C634 la_oenb[21] vssa1 0.63fF
+C635 la_data_out[21] vssa1 0.63fF
+C636 la_data_in[21] vssa1 0.63fF
+C637 la_oenb[20] vssa1 0.63fF
+C638 la_data_in[20] vssa1 0.63fF
+C639 la_oenb[19] vssa1 0.63fF
+C640 la_data_out[19] vssa1 0.63fF
+C641 la_data_in[19] vssa1 0.63fF
+C642 la_oenb[18] vssa1 0.63fF
+C643 la_data_out[18] vssa1 0.63fF
+C644 la_data_in[18] vssa1 0.63fF
+C645 la_oenb[17] vssa1 0.63fF
+C646 la_data_out[17] vssa1 0.63fF
+C647 la_data_in[17] vssa1 0.63fF
+C648 la_oenb[16] vssa1 0.63fF
+C649 la_data_out[16] vssa1 0.63fF
+C650 la_oenb[15] vssa1 0.63fF
+C651 la_data_out[15] vssa1 0.63fF
+C652 la_data_in[15] vssa1 0.63fF
+C653 la_oenb[14] vssa1 0.63fF
+C654 la_data_out[14] vssa1 0.63fF
+C655 la_data_in[14] vssa1 0.63fF
+C656 la_oenb[13] vssa1 0.63fF
+C657 la_data_out[13] vssa1 0.63fF
+C658 la_data_in[13] vssa1 0.63fF
+C659 la_oenb[12] vssa1 0.63fF
+C660 la_data_out[12] vssa1 0.63fF
+C661 la_data_in[12] vssa1 0.63fF
+C662 la_data_out[11] vssa1 0.63fF
+C663 la_data_in[11] vssa1 0.63fF
+C664 la_oenb[10] vssa1 0.63fF
+C665 la_data_out[10] vssa1 0.63fF
+C666 la_data_in[10] vssa1 0.63fF
+C667 la_data_out[9] vssa1 0.63fF
+C668 la_data_in[9] vssa1 0.63fF
+C669 la_oenb[8] vssa1 0.63fF
+C670 la_data_out[8] vssa1 0.63fF
+C671 la_data_in[8] vssa1 0.63fF
+C672 la_oenb[7] vssa1 0.63fF
+C673 la_data_out[7] vssa1 0.63fF
+C674 la_data_in[7] vssa1 0.63fF
+C675 la_oenb[6] vssa1 0.63fF
+C676 la_data_out[6] vssa1 0.63fF
+C677 la_data_in[6] vssa1 0.63fF
+C678 la_oenb[5] vssa1 0.63fF
+C679 la_data_in[5] vssa1 0.63fF
+C680 la_oenb[4] vssa1 0.63fF
+C681 la_data_out[4] vssa1 0.63fF
+C682 la_data_in[4] vssa1 0.63fF
+C683 la_oenb[3] vssa1 0.63fF
+C684 la_data_out[3] vssa1 0.63fF
+C685 la_data_in[3] vssa1 0.63fF
+C686 la_oenb[2] vssa1 0.63fF
+C687 la_data_out[2] vssa1 0.63fF
+C688 la_data_in[2] vssa1 0.63fF
+C689 la_oenb[1] vssa1 0.63fF
+C690 la_data_out[1] vssa1 0.63fF
+C691 la_oenb[0] vssa1 0.63fF
+C692 la_data_out[0] vssa1 0.63fF
+C693 la_data_in[0] vssa1 0.63fF
+C694 wbs_dat_o[31] vssa1 0.63fF
+C695 wbs_dat_i[31] vssa1 0.63fF
+C696 wbs_adr_i[31] vssa1 0.63fF
+C697 wbs_dat_o[30] vssa1 0.63fF
+C698 wbs_dat_i[30] vssa1 0.63fF
+C699 wbs_adr_i[30] vssa1 0.63fF
+C700 wbs_dat_o[29] vssa1 0.63fF
+C701 wbs_dat_i[29] vssa1 0.63fF
+C702 wbs_adr_i[29] vssa1 0.63fF
+C703 wbs_dat_i[28] vssa1 0.63fF
+C704 wbs_adr_i[28] vssa1 0.63fF
+C705 wbs_dat_o[27] vssa1 0.63fF
+C706 wbs_dat_i[27] vssa1 0.63fF
+C707 wbs_adr_i[27] vssa1 0.63fF
+C708 wbs_dat_i[26] vssa1 0.63fF
+C709 wbs_adr_i[26] vssa1 0.63fF
+C710 wbs_dat_o[25] vssa1 0.63fF
+C711 wbs_dat_i[25] vssa1 0.63fF
+C712 wbs_adr_i[25] vssa1 0.63fF
+C713 wbs_dat_o[24] vssa1 0.63fF
+C714 wbs_dat_i[24] vssa1 0.63fF
+C715 wbs_adr_i[24] vssa1 0.63fF
+C716 wbs_dat_o[23] vssa1 0.63fF
+C717 wbs_dat_i[23] vssa1 0.63fF
+C718 wbs_adr_i[23] vssa1 0.63fF
+C719 wbs_dat_o[22] vssa1 0.63fF
+C720 wbs_adr_i[22] vssa1 0.63fF
+C721 wbs_dat_o[21] vssa1 0.63fF
+C722 wbs_dat_i[21] vssa1 0.63fF
+C723 wbs_adr_i[21] vssa1 0.63fF
+C724 wbs_dat_o[20] vssa1 0.63fF
+C725 wbs_dat_i[20] vssa1 0.63fF
+C726 wbs_adr_i[20] vssa1 0.63fF
+C727 wbs_dat_o[19] vssa1 0.63fF
+C728 wbs_dat_i[19] vssa1 0.63fF
+C729 wbs_adr_i[19] vssa1 0.63fF
+C730 wbs_dat_o[18] vssa1 0.63fF
+C731 wbs_dat_i[18] vssa1 0.63fF
+C732 wbs_dat_o[17] vssa1 0.63fF
+C733 wbs_dat_i[17] vssa1 0.63fF
+C734 wbs_adr_i[17] vssa1 0.63fF
+C735 wbs_dat_o[16] vssa1 0.63fF
+C736 wbs_dat_i[16] vssa1 0.63fF
+C737 wbs_adr_i[16] vssa1 0.63fF
+C738 wbs_dat_o[15] vssa1 0.63fF
+C739 wbs_dat_i[15] vssa1 0.63fF
+C740 wbs_adr_i[15] vssa1 0.63fF
+C741 wbs_dat_o[14] vssa1 0.63fF
+C742 wbs_dat_i[14] vssa1 0.63fF
+C743 wbs_adr_i[14] vssa1 0.63fF
+C744 wbs_dat_o[13] vssa1 0.63fF
+C745 wbs_dat_i[13] vssa1 0.63fF
+C746 wbs_adr_i[13] vssa1 0.63fF
+C747 wbs_dat_o[12] vssa1 0.63fF
+C748 wbs_dat_i[12] vssa1 0.63fF
+C749 wbs_adr_i[12] vssa1 0.63fF
+C750 wbs_dat_i[11] vssa1 0.63fF
+C751 wbs_adr_i[11] vssa1 0.63fF
+C752 wbs_dat_o[10] vssa1 0.63fF
+C753 wbs_dat_i[10] vssa1 0.63fF
+C754 wbs_adr_i[10] vssa1 0.63fF
+C755 wbs_dat_o[9] vssa1 0.63fF
+C756 wbs_dat_i[9] vssa1 0.63fF
+C757 wbs_adr_i[9] vssa1 0.63fF
+C758 wbs_dat_o[8] vssa1 0.63fF
+C759 wbs_dat_i[8] vssa1 0.63fF
+C760 wbs_adr_i[8] vssa1 0.63fF
+C761 wbs_dat_o[7] vssa1 0.63fF
+C762 wbs_adr_i[7] vssa1 0.63fF
+C763 wbs_dat_o[6] vssa1 0.63fF
+C764 wbs_dat_i[6] vssa1 0.63fF
+C765 wbs_adr_i[6] vssa1 0.63fF
+C766 wbs_dat_o[5] vssa1 0.63fF
+C767 wbs_dat_i[5] vssa1 0.63fF
+C768 wbs_adr_i[5] vssa1 0.63fF
+C769 wbs_dat_o[4] vssa1 0.63fF
+C770 wbs_dat_i[4] vssa1 0.63fF
+C771 wbs_adr_i[4] vssa1 0.63fF
+C772 wbs_sel_i[3] vssa1 0.63fF
+C773 wbs_dat_o[3] vssa1 0.63fF
+C774 wbs_adr_i[3] vssa1 0.63fF
+C775 wbs_sel_i[2] vssa1 0.63fF
+C776 wbs_dat_o[2] vssa1 0.63fF
+C777 wbs_dat_i[2] vssa1 0.63fF
+C778 wbs_adr_i[2] vssa1 0.63fF
+C779 wbs_dat_o[1] vssa1 0.63fF
+C780 wbs_dat_i[1] vssa1 0.63fF
+C781 wbs_adr_i[1] vssa1 0.63fF
+C782 wbs_sel_i[0] vssa1 0.63fF
+C783 wbs_dat_o[0] vssa1 0.63fF
+C784 wbs_dat_i[0] vssa1 0.63fF
+C785 wbs_adr_i[0] vssa1 0.63fF
+C786 wbs_we_i vssa1 0.63fF
+C787 wbs_stb_i vssa1 0.63fF
+C788 wbs_cyc_i vssa1 0.63fF
+C789 wbs_ack_o vssa1 0.63fF
+C790 wb_rst_i vssa1 0.63fF
+C791 m3_226242_702300# vssa1 -1.31fF
+C792 m3_222594_702300# vssa1 0.55fF
+C793 top_pll_v2_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C794 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C795 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C796 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C797 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C798 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C799 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C800 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C801 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C802 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C803 top_pll_v2_0/QB vssa1 4.35fF
+C804 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C805 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C806 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C807 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C808 top_pll_v2_0/out_div_by_5 vssa1 -0.40fF
+C809 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C810 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C811 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C812 top_pll_v2_0/pfd_reset vssa1 2.17fF
+C813 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C814 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C815 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C816 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C817 top_pll_v2_0/QA vssa1 4.22fF
+C818 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C819 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C820 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C821 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C822 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C823 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C824 top_pll_v2_0/nUp vssa1 5.39fF
+C825 top_pll_v2_0/Up vssa1 1.85fF
+C826 top_pll_v2_0/Down vssa1 6.19fF
+C827 top_pll_v2_0/nDown vssa1 -3.53fF
+C828 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C829 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C830 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C831 top_pll_v2_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C832 top_pll_v2_0/div_5_Q1_shift vssa1 -0.14fF
+C833 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C834 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C835 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C836 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C837 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C838 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C839 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C840 top_pll_v2_0/div_5_Q1 vssa1 4.25fF
+C841 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C842 top_pll_v2_0/div_5_nQ0 vssa1 0.59fF
+C843 top_pll_v2_0/div_5_Q0 vssa1 0.01fF
+C844 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C845 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C846 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C847 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C848 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C849 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C850 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C851 top_pll_v2_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C852 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C853 top_pll_v2_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C854 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C855 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C856 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C857 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C858 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C859 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C860 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C861 top_pll_v2_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C862 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C863 top_pll_v2_0/div_5_nQ2 vssa1 1.24fF
+C864 top_pll_v2_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C865 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C866 top_pll_v2_0/n_out_by_2 vssa1 -2.75fF
+C867 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C868 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C869 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C870 top_pll_v2_0/out_by_2 vssa1 -5.01fF
+C871 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C872 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C873 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C874 top_pll_v2_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C875 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C876 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C877 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C878 top_pll_v2_0/out_first_buffer vssa1 2.88fF
+C879 top_pll_v2_0/out_to_div vssa1 4.23fF
+C880 top_pll_v2_0/out_to_buffer vssa1 1.54fF
+C881 top_pll_v2_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C882 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C883 top_pll_v2_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C884 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C885 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C886 top_pll_v2_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C887 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C888 top_pll_v2_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C889 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C890 top_pll_v2_0/vco_out vssa1 1.01fF
+C891 top_pll_v2_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C892 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C893 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C894 top_pll_v2_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C895 io_analog[8] vssa1 13.78fF
+C896 top_pll_v2_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C897 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C898 top_pll_v2_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C899 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C900 top_pll_v2_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C901 top_pll_v2_0/out_buffer_div_2 vssa1 1.60fF
+C902 top_pll_v2_0/n_out_buffer_div_2 vssa1 1.63fF
+C903 top_pll_v2_0/out_div_2 vssa1 -1.30fF
+C904 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C905 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C906 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C907 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C908 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C909 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C910 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C911 top_pll_v2_0/n_out_div_2 vssa1 1.95fF
+C912 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C913 top_pll_v2_0/lf_vc vssa1 -59.89fF
+C914 top_pll_v2_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
+C915 gpio_noesd[8] vssa1 210.79fF
+C916 top_pll_v2_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
+C917 top_pll_v2_0/nswitch vssa1 3.73fF
+C918 top_pll_v2_0/biasp vssa1 5.44fF
+C919 bias_0/iref_1 vssa1 -91.53fF
+C920 top_pll_v2_0/vco_vctrl vssa1 -20.08fF
+C921 top_pll_v2_0/pswitch vssa1 3.57fF
+C922 io_analog[5] vssa1 33.29fF
+C923 bias_0/iref_4 vssa1 1.17fF
+C924 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vssa1 2.60fF
+C925 bias_0/iref_3 vssa1 0.64fF
+C926 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vssa1 2.60fF
+C927 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vssa1 2.60fF
+C928 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vssa1 2.60fF
+C929 bias_0/m1_20168_984# vssa1 56.92fF
+C930 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vssa1 2.60fF
+C931 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vssa1 2.60fF
+C932 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vssa1 2.60fF
+C933 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vssa1 2.60fF
+C934 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vssa1 2.60fF
+C935 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vssa1 2.60fF
+C936 top_pll_v1_1/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C937 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C938 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C939 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C940 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C941 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C942 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C943 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C944 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C945 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C946 top_pll_v1_1/QB vssa1 4.35fF
+C947 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C948 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C949 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C950 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C951 top_pll_v1_1/out_div_by_5 vssa1 -0.40fF
+C952 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C953 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C954 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C955 top_pll_v1_1/pfd_reset vssa1 2.17fF
+C956 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C957 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C958 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C959 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C960 top_pll_v1_1/QA vssa1 4.22fF
+C961 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C962 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C963 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C964 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C965 io_analog[10] vssa1 503.33fF
+C966 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C967 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C968 top_pll_v1_1/nUp vssa1 5.39fF
+C969 top_pll_v1_1/Up vssa1 1.85fF
+C970 top_pll_v1_1/Down vssa1 6.19fF
+C971 top_pll_v1_1/nDown vssa1 -3.53fF
+C972 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C973 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C974 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C975 top_pll_v1_1/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C976 top_pll_v1_1/div_5_Q1_shift vssa1 -0.14fF
+C977 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C978 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C979 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C980 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C981 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C982 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C983 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C984 top_pll_v1_1/div_5_Q1 vssa1 4.25fF
+C985 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C986 top_pll_v1_1/div_5_nQ0 vssa1 0.59fF
+C987 top_pll_v1_1/div_5_Q0 vssa1 0.01fF
+C988 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C989 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C990 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C991 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C992 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C993 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C994 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C995 top_pll_v1_1/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C996 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C997 top_pll_v1_1/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C998 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C999 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1000 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1001 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1002 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1003 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1004 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1005 top_pll_v1_1/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1006 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1007 top_pll_v1_1/div_5_nQ2 vssa1 1.24fF
+C1008 top_pll_v1_1/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1009 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1010 top_pll_v1_1/n_out_by_2 vssa1 -2.75fF
+C1011 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1012 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1013 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1014 top_pll_v1_1/out_by_2 vssa1 -5.01fF
+C1015 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1016 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1017 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1018 top_pll_v1_1/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1019 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1020 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1021 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1022 top_pll_v1_1/out_first_buffer vssa1 2.88fF
+C1023 top_pll_v1_1/out_to_div vssa1 4.23fF
+C1024 top_pll_v1_1/out_to_buffer vssa1 1.54fF
+C1025 top_pll_v1_1/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1026 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1027 top_pll_v1_1/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1028 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1029 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1030 top_pll_v1_1/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1031 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1032 top_pll_v1_1/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1033 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1034 top_pll_v1_1/vco_out vssa1 1.01fF
+C1035 top_pll_v1_1/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1036 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1037 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1038 top_pll_v1_1/buffer_salida_0/a_3996_n100# vssa1 48.11fF
+C1039 io_analog[7] vssa1 24.61fF
+C1040 top_pll_v1_1/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1041 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1042 top_pll_v1_1/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1043 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1044 top_pll_v1_1/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1045 top_pll_v1_1/out_buffer_div_2 vssa1 1.60fF
+C1046 top_pll_v1_1/n_out_buffer_div_2 vssa1 1.63fF
+C1047 top_pll_v1_1/out_div_2 vssa1 -1.30fF
+C1048 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1049 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1050 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1051 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1052 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1053 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1054 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1055 top_pll_v1_1/n_out_div_2 vssa1 1.95fF
+C1056 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1057 top_pll_v1_1/nswitch vssa1 3.73fF
+C1058 top_pll_v1_1/biasp vssa1 5.44fF
+C1059 bias_0/iref_0 vssa1 -81.35fF
+C1060 top_pll_v1_1/vco_vctrl vssa1 -18.17fF
+C1061 top_pll_v1_1/pswitch vssa1 3.57fF
+C1062 top_pll_v1_1/lf_vc vssa1 -59.89fF
+C1063 top_pll_v1_1/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C1064 top_pll_v1_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C1065 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C1066 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C1067 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1068 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C1069 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1070 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1071 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1072 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C1073 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1074 top_pll_v1_0/QB vssa1 4.35fF
+C1075 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1076 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C1077 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1078 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1079 top_pll_v1_0/out_div_by_5 vssa1 -0.40fF
+C1080 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1081 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C1082 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1083 top_pll_v1_0/pfd_reset vssa1 2.17fF
+C1084 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1085 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1086 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C1087 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1088 top_pll_v1_0/QA vssa1 4.22fF
+C1089 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1090 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C1091 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1092 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1093 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C1094 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C1095 top_pll_v1_0/nUp vssa1 5.39fF
+C1096 top_pll_v1_0/Up vssa1 1.85fF
+C1097 top_pll_v1_0/Down vssa1 6.19fF
+C1098 top_pll_v1_0/nDown vssa1 -3.53fF
+C1099 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C1100 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C1101 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C1102 top_pll_v1_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1103 top_pll_v1_0/div_5_Q1_shift vssa1 -0.14fF
+C1104 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1105 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1106 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1107 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1108 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1109 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1110 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1111 top_pll_v1_0/div_5_Q1 vssa1 4.25fF
+C1112 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1113 top_pll_v1_0/div_5_nQ0 vssa1 0.59fF
+C1114 top_pll_v1_0/div_5_Q0 vssa1 0.01fF
+C1115 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1116 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1117 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1118 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1119 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1120 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1121 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1122 top_pll_v1_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C1123 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1124 top_pll_v1_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1125 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1126 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1127 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1128 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1129 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1130 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1131 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1132 top_pll_v1_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1133 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1134 top_pll_v1_0/div_5_nQ2 vssa1 1.24fF
+C1135 top_pll_v1_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1136 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1137 top_pll_v1_0/n_out_by_2 vssa1 -2.75fF
+C1138 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1139 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1140 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1141 top_pll_v1_0/out_by_2 vssa1 -5.01fF
+C1142 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1143 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1144 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1145 top_pll_v1_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1146 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1147 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1148 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1149 top_pll_v1_0/out_first_buffer vssa1 2.88fF
+C1150 top_pll_v1_0/out_to_div vssa1 4.23fF
+C1151 top_pll_v1_0/out_to_buffer vssa1 1.54fF
+C1152 top_pll_v1_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1153 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1154 top_pll_v1_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1155 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1156 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1157 top_pll_v1_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1158 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1159 top_pll_v1_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1160 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1161 top_pll_v1_0/vco_out vssa1 1.01fF
+C1162 gpio_noesd[7] vssa1 272.21fF
+C1163 top_pll_v1_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1164 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1165 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1166 top_pll_v1_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C1167 io_analog[9] vssa1 7.89fF
+C1168 top_pll_v1_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1169 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1170 top_pll_v1_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1171 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1172 top_pll_v1_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1173 top_pll_v1_0/out_buffer_div_2 vssa1 1.60fF
+C1174 top_pll_v1_0/n_out_buffer_div_2 vssa1 1.63fF
+C1175 top_pll_v1_0/out_div_2 vssa1 -1.30fF
+C1176 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1177 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1178 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1179 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1180 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1181 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1182 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1183 top_pll_v1_0/n_out_div_2 vssa1 1.95fF
+C1184 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1185 top_pll_v1_0/nswitch vssa1 3.73fF
+C1186 top_pll_v1_0/biasp vssa1 5.44fF
+C1187 bias_0/iref_2 vssa1 -178.91fF
+C1188 top_pll_v1_0/vco_vctrl vssa1 -18.17fF
+C1189 top_pll_v1_0/pswitch vssa1 3.57fF
+C1190 top_pll_v1_0/lf_vc vssa1 -59.89fF
+C1191 top_pll_v1_0/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C1192 bias_0/iref_6 vssa1 -645.65fF
+C1193 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in vssa1 -32.98fF
+C1194 io_analog[1] vssa1 74.58fF
+C1195 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# vssa1 1.29fF
+C1196 bias_0/iref_5 vssa1 -623.45fF
+C1197 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in vssa1 -32.98fF
+C1198 io_analog[0] vssa1 -154.61fF
+C1199 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# vssa1 1.29fF
+C1200 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# vssa1 -35.44fF
+C1201 bias_0/iref_8 vssa1 -189.06fF
+C1202 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# vssa1 -35.44fF
+C1203 bias_0/iref_7 vssa1 -205.18fF
+C1204 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# vssa1 -1.87fF
+C1205 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# vssa1 0.47fF
+C1206 gpio_noesd[5] vssa1 122.09fF
+C1207 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# vssa1 -1.10fF
+C1208 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl vssa1 -2.03fF
+C1209 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# vssa1 -2.23fF
+C1210 gpio_noesd[6] vssa1 325.91fF
+C1211 gpio_noesd[4] vssa1 116.78fF
+C1212 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# vssa1 -1.03fF
+C1213 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# vssa1 0.51fF
+C1214 bias_0/iref_9 vssa1 -181.57fF
+C1215 res_amp_top_0/res_amp_lin_prog_0/outn vssa1 1.55fF
+C1216 io_analog[3] vssa1 -119.52fF
+C1217 res_amp_top_0/res_amp_lin_prog_0/outp vssa1 -4.89fF
+C1218 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp vssa1 -4.89fF
+C1219 io_analog[2] vssa1 -131.04fF
+C1220 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# vssa1 -0.95fF
+C1221 res_amp_top_0/res_amp_lin_prog_0/outn_cap vssa1 -0.01fF
+C1222 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk vssa1 4.27fF
+C1223 res_amp_top_0/res_amp_lin_prog_0/inverter_min_x4_0/out vssa1 4.60fF
+C1224 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in vssa1 1.07fF
+C1225 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in vssa1 1.03fF
+C1226 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in vssa1 1.03fF
+C1227 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in vssa1 1.07fF
+C1228 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in vssa1 1.03fF
+C1229 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in vssa1 1.03fF
+C1230 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in vssa1 1.07fF
+C1231 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in vssa1 1.03fF
+C1232 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in vssa1 1.07fF
+C1233 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in vssa1 1.03fF
+C1234 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in vssa1 1.03fF
+C1235 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in vssa1 1.03fF
+C1236 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in vssa1 1.07fF
+C1237 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB vssa1 -7.88fF
+C1238 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in vssa1 1.03fF
+C1239 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in vssa1 1.03fF
+C1240 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in vssa1 1.07fF
+C1241 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in vssa1 1.03fF
+C1242 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1243 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in vssa1 1.03fF
+C1244 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b vssa1 2.03fF
+C1245 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 vssa1 1.54fF
+C1246 gpio_noesd[3] vssa1 213.06fF
+C1247 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b vssa1 2.03fF
+C1248 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out vssa1 -1.67fF
+C1249 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA vssa1 -2.58fF
+C1250 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b vssa1 2.03fF
+C1251 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out vssa1 -2.25fF
+C1252 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA vssa1 -0.04fF
+C1253 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b vssa1 2.03fF
+C1254 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out vssa1 -2.69fF
+C1255 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB vssa1 -4.96fF
+C1256 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b vssa1 2.03fF
+C1257 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out vssa1 -4.71fF
+C1258 gpio_noesd[2] vssa1 216.13fF
+C1259 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA vssa1 0.63fF
+C1260 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b vssa1 2.03fF
+C1261 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out vssa1 -2.49fF
+C1262 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB vssa1 -3.92fF
+C1263 gpio_noesd[1] vssa1 230.09fF
+C1264 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b vssa1 2.03fF
+C1265 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out vssa1 -0.27fF
+C1266 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB vssa1 -0.97fF
+C1267 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in vssa1 1.07fF
+C1268 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in vssa1 1.03fF
+C1269 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in vssa1 1.03fF
+C1270 res_amp_top_0/res_amp_lin_prog_0/outp_cap vssa1 -7.66fF
+C1271 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/m1_21_n341# vssa1 0.72fF
+C1272 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1273 res_amp_top_0/res_amp_lin_prog_0/clk vssa1 -8.26fF
+C1274 res_amp_top_0/res_amp_sync_v2_0/inverter_min_x4_4/out vssa1 5.85fF
+C1275 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/out vssa1 1.70fF
+C1276 res_amp_top_0/res_amp_sync_v2_0/rst vssa1 -7.88fF
+C1277 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/nQ vssa1 0.48fF
+C1278 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/Q vssa1 -2.08fF
+C1279 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1280 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD vssa1 0.57fF
+C1281 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D vssa1 -1.73fF
+C1282 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1283 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1284 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D vssa1 0.96fF
+C1285 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1286 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/D vssa1 1.83fF
+C1287 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD vssa1 1.14fF
+C1288 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/out vssa1 1.20fF
+C1289 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/Q vssa1 -4.73fF
+C1290 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1291 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/Q vssa1 -2.94fF
+C1292 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1293 io_analog[4] vssa1 -253.69fF
+C1294 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1295 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1296 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1297 io_analog[6] vssa1 -26.69fF
+C1298 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1299 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1300 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1301 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/D vssa1 0.79fF
+C1302 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1303 vdda1 vssa1 7275.97fF
+C1304 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1305 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/Q vssa1 -1.08fF
+C1306 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1307 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1308 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1309 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1310 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1311 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1312 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1313 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/D vssa1 -0.38fF
+C1314 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1315 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/nQ vssa1 0.48fF
+C1316 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1317 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1318 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1319 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1320 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1321 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1322 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1323 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/D vssa1 -1.04fF
+C1324 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1325 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/nQ vssa1 0.48fF
+C1326 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1327 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1328 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1329 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1330 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1331 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1332 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1333 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+.ends
+
diff --git a/mag/inverter_cp_x1.mag b/mag/inverter_cp_x1.mag
new file mode 100644
index 0000000..37f87cc
--- /dev/null
+++ b/mag/inverter_cp_x1.mag
@@ -0,0 +1,87 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect 0 688 622 776
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+<< psubdiff >>
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+<< metal1 >>
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+use sky130_fd_pr__pfet_01v8_7KT7MH sky130_fd_pr__pfet_01v8_7KT7MH_0
+timestamp 1624049879
+transform 1 0 311 0 1 344
+box -311 -344 311 344
+use sky130_fd_pr__nfet_01v8_2BS6QM sky130_fd_pr__nfet_01v8_2BS6QM_0
+timestamp 1624049879
+transform 1 0 311 0 1 -335
+box -311 -335 311 335
+<< labels >>
+rlabel metal1 0 652 622 706 1 vdd
+rlabel metal1 0 -688 622 -634 1 vss
+rlabel metal1 210 -33 226 33 1 in
+rlabel metal1 432 -210 478 222 1 out
+<< end >>
diff --git a/mag/inverter_cp_x2.mag b/mag/inverter_cp_x2.mag
new file mode 100644
index 0000000..5d508f5
--- /dev/null
+++ b/mag/inverter_cp_x2.mag
@@ -0,0 +1,96 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
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+<< pwell >>
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+<< psubdiff >>
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+<< metal1 >>
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+rect 874 -634 910 -600
+rect 0 -688 910 -634
+rect 0 -722 36 -688
+rect 874 -722 910 -688
+rect 0 -728 910 -722
+use sky130_fd_pr__pfet_01v8_XJXT7S sky130_fd_pr__pfet_01v8_XJXT7S_0
+timestamp 1624049879
+transform 1 0 455 0 1 344
+box -455 -344 455 344
+use sky130_fd_pr__nfet_01v8_AZESM8 sky130_fd_pr__nfet_01v8_AZESM8_0
+timestamp 1624049879
+transform 1 0 455 0 1 -335
+box -455 -335 455 335
+<< labels >>
+rlabel metal1 0 -33 428 33 1 in
+rlabel metal1 720 -33 910 33 1 out
+rlabel metal1 0 -688 910 -634 1 vss
+rlabel metal1 0 652 910 706 1 vdd
+<< end >>
diff --git a/mag/inverter_csvco.mag b/mag/inverter_csvco.mag
new file mode 100644
index 0000000..635401a
--- /dev/null
+++ b/mag/inverter_csvco.mag
@@ -0,0 +1,82 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect 0 668 432 757
+rect 197 47 231 131
+<< pwell >>
+rect 0 -508 430 -438
+rect 0 -597 432 -508
+<< psubdiff >>
+rect 108 -561 132 -527
+rect 300 -561 324 -527
+<< nsubdiff >>
+rect 108 687 132 721
+rect 300 687 324 721
+<< psubdiffcont >>
+rect 132 -561 300 -527
+<< nsubdiffcont >>
+rect 132 687 300 721
+<< poly >>
+rect 183 51 249 131
+rect 183 -51 197 51
+rect 231 -51 249 51
+rect 183 -122 249 -51
+<< polycont >>
+rect 197 -51 231 51
+<< locali >>
+rect 197 51 231 67
+rect 197 -67 231 -51
+<< viali >>
+rect 35 687 132 721
+rect 132 687 300 721
+rect 300 687 395 721
+rect 36 598 396 632
+rect 197 -51 231 51
+rect 36 -472 396 -438
+rect 36 -561 132 -527
+rect 132 -561 300 -527
+rect 300 -561 396 -527
+<< metal1 >>
+rect 0 721 432 727
+rect 0 687 35 721
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+rect 0 632 432 687
+rect 0 598 36 632
+rect 396 598 432 632
+rect 0 592 432 598
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+rect 185 26 197 51
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+rect 0 -472 36 -438
+rect 396 -472 432 -438
+rect 0 -527 432 -472
+rect 0 -561 36 -527
+rect 396 -561 432 -527
+rect 0 -567 432 -561
+use sky130_fd_pr__nfet_01v8_AQR2CW sky130_fd_pr__nfet_01v8_AQR2CW_0
+timestamp 1624049879
+transform 1 0 216 0 1 -254
+box -216 -254 216 254
+use sky130_fd_pr__pfet_01v8_HRYSXS sky130_fd_pr__pfet_01v8_HRYSXS_0
+timestamp 1624049879
+transform 1 0 216 0 1 334
+box -216 -334 216 334
+<< labels >>
+rlabel metal1 0 -26 197 26 1 in
+rlabel metal1 288 -26 432 26 1 out
+rlabel metal1 0 632 432 687 1 vbulkp
+rlabel metal1 0 -527 432 -472 1 vbulkn
+rlabel metal1 144 220 190 520 1 vdd
+rlabel metal1 144 -360 190 -210 1 vss
+<< end >>
diff --git a/mag/inverter_min_x2.mag b/mag/inverter_min_x2.mag
new file mode 100644
index 0000000..00186eb
--- /dev/null
+++ b/mag/inverter_min_x2.mag
@@ -0,0 +1,88 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -53 551 473 655
+rect 24 543 385 551
+rect 29 539 371 543
+<< psubdiff >>
+rect 55 -609 79 -575
+rect 341 -609 365 -575
+<< nsubdiff >>
+rect 55 571 79 605
+rect 341 571 365 605
+<< psubdiffcont >>
+rect 79 -609 341 -575
+<< nsubdiffcont >>
+rect 79 571 341 605
+<< poly >>
+rect 147 91 273 140
+rect 147 -8 206 91
+rect 147 -94 159 -8
+rect 194 -94 206 -8
+rect 147 -188 206 -94
+rect 147 -237 273 -188
+<< polycont >>
+rect 159 -94 194 -8
+<< locali >>
+rect 143 -8 210 8
+rect 143 -94 159 -8
+rect 194 -94 210 -8
+rect 143 -110 210 -94
+<< viali >>
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+rect 79 571 341 605
+rect 341 571 437 605
+rect -17 483 437 517
+rect 159 -94 194 -8
+rect -17 -521 437 -487
+rect -17 -609 79 -575
+rect 79 -609 341 -575
+rect 341 -609 437 -575
+<< metal1 >>
+rect -53 605 473 611
+rect -53 571 -17 605
+rect 437 571 473 605
+rect -53 517 473 571
+rect -53 483 -17 517
+rect 437 483 473 517
+rect -53 476 473 483
+rect 91 128 137 334
+rect 186 166 233 476
+rect 315 128 363 334
+rect 91 74 363 128
+rect 153 -8 200 4
+rect 153 -26 159 -8
+rect -53 -80 159 -26
+rect 153 -94 159 -80
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+rect 153 -106 200 -94
+rect 315 -26 363 74
+rect 315 -80 473 -26
+rect 315 -166 363 -80
+rect 91 -220 363 -166
+rect 91 -347 137 -220
+rect 186 -481 233 -262
+rect 315 -351 363 -220
+rect -53 -487 473 -481
+rect -53 -521 -17 -487
+rect 437 -521 473 -487
+rect -53 -575 473 -521
+rect -53 -609 -17 -575
+rect 437 -609 473 -575
+rect -53 -615 473 -609
+use sky130_fd_pr__pfet_01v8_ZPB9BB sky130_fd_pr__pfet_01v8_ZPB9BB_0
+timestamp 1624049879
+transform 1 0 210 0 1 250
+box -263 -303 263 303
+use sky130_fd_pr__nfet_01v8_5RJ8EK sky130_fd_pr__nfet_01v8_5RJ8EK_0
+timestamp 1624049879
+transform 1 0 210 0 1 -305
+box -263 -252 263 252
+<< labels >>
+rlabel metal1 -53 -80 159 -26 1 in
+rlabel metal1 315 -80 473 -26 1 out
+rlabel metal1 -53 517 473 571 1 vdd
+rlabel metal1 -53 -575 473 -521 1 vss
+<< end >>
diff --git a/mag/inverter_min_x4.mag b/mag/inverter_min_x4.mag
new file mode 100644
index 0000000..f936d5b
--- /dev/null
+++ b/mag/inverter_min_x4.mag
@@ -0,0 +1,92 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -53 531 665 643
+<< psubdiff >>
+rect 55 -610 79 -576
+rect 533 -610 557 -576
+<< nsubdiff >>
+rect 55 571 79 605
+rect 533 571 557 605
+<< psubdiffcont >>
+rect 79 -610 533 -576
+<< nsubdiffcont >>
+rect 79 571 533 605
+<< poly >>
+rect 147 360 465 417
+rect 147 83 465 140
+rect 147 10 300 83
+rect 147 -123 190 10
+rect 258 -123 300 10
+rect 147 -181 300 -123
+rect 147 -238 465 -181
+rect 147 -430 465 -373
+<< polycont >>
+rect 190 -123 258 10
+<< locali >>
+rect 174 10 274 26
+rect 174 -123 190 10
+rect 258 -123 274 10
+rect 174 -139 274 -123
+<< viali >>
+rect -17 571 79 605
+rect 79 571 533 605
+rect 533 571 629 605
+rect -17 483 629 517
+rect 190 -123 258 10
+rect -18 -521 629 -487
+rect -18 -610 79 -576
+rect 79 -610 533 -576
+rect 533 -610 629 -576
+<< metal1 >>
+rect -53 605 665 611
+rect -53 571 -17 605
+rect 629 571 665 605
+rect -53 517 665 571
+rect -53 483 -17 517
+rect 629 483 665 517
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+rect 184 10 264 22
+rect 184 -13 190 10
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+rect 498 -19 574 59
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+rect 364 -481 440 -263
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+rect -53 -487 665 -481
+rect -53 -521 -18 -487
+rect 629 -521 665 -487
+rect -53 -576 665 -521
+rect -53 -610 -18 -576
+rect 629 -610 665 -576
+rect -53 -616 665 -610
+use sky130_fd_pr__nfet_01v8_DXA56D sky130_fd_pr__nfet_01v8_DXA56D_0
+timestamp 1624049879
+transform 1 0 306 0 1 -305
+box -359 -252 359 252
+use sky130_fd_pr__pfet_01v8_ZP3U9B sky130_fd_pr__pfet_01v8_ZP3U9B_0
+timestamp 1624049879
+transform 1 0 306 0 1 250
+box -359 -303 359 303
+<< labels >>
+rlabel metal1 -53 -576 665 -521 1 vss
+rlabel metal1 -53 -93 190 -13 1 in
+rlabel metal1 498 -97 665 -19 1 out
+rlabel metal1 -53 517 665 571 1 vdd
+<< end >>
diff --git a/mag/latch_diff.mag b/mag/latch_diff.mag
new file mode 100644
index 0000000..535f0d6
--- /dev/null
+++ b/mag/latch_diff.mag
@@ -0,0 +1,251 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -33 2264 526 2352
+rect -33 2261 525 2264
+rect -33 2137 307 2261
+rect -33 1900 340 2137
+rect -33 1576 526 1900
+rect -33 -1 526 60
+rect -33 -628 0 -1
+rect -33 -716 526 -628
+<< pwell >>
+rect -33 1030 0 1576
+rect -33 967 503 1030
+rect -33 669 526 967
+rect -33 668 503 669
+rect -33 60 0 668
+<< psubdiff >>
+rect 36 1506 434 1540
+rect 36 563 70 1027
+rect 453 1002 555 1036
+rect 424 600 633 634
+rect 36 130 70 182
+rect 36 96 613 130
+<< nsubdiff >>
+rect 107 2282 131 2316
+rect 393 2282 417 2316
+rect 108 -680 132 -646
+rect 394 -680 418 -646
+<< nsubdiffcont >>
+rect 131 2282 393 2316
+rect 132 -680 394 -646
+<< poly >>
+rect 99 1807 230 1824
+rect 99 1773 124 1807
+rect 192 1773 230 1807
+rect 99 1758 230 1773
+rect 296 -137 427 -122
+rect 296 -171 334 -137
+rect 402 -171 427 -137
+rect 296 -188 427 -171
+<< polycont >>
+rect 124 1773 192 1807
+rect 334 -171 402 -137
+<< locali >>
+rect 108 1773 124 1807
+rect 192 1773 208 1807
+rect 70 1506 434 1540
+rect 70 96 434 130
+rect 318 -171 334 -137
+rect 402 -171 418 -137
+<< viali >>
+rect 36 2282 131 2316
+rect 131 2282 393 2316
+rect 393 2282 490 2316
+rect 36 2194 490 2228
+rect 124 1773 192 1807
+rect 36 1036 70 1540
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+rect 434 96 1112 130
+rect 334 -171 402 -137
+rect 36 -592 490 -558
+rect 36 -680 132 -646
+rect 132 -680 394 -646
+rect 394 -680 490 -646
+<< metal1 >>
+rect -33 2316 526 2322
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+rect -33 -558 526 -552
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+rect 490 -592 526 -558
+rect -33 -646 526 -592
+rect -33 -680 36 -646
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+rect -33 -686 526 -680
+<< via1 >>
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+rect 237 1547 289 1651
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+rect 237 -15 289 89
+rect 332 -137 414 -125
+rect 332 -171 334 -137
+rect 334 -171 402 -137
+rect 402 -171 414 -137
+rect 332 -177 414 -171
+<< metal2 >>
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+rect 237 1651 289 1661
+rect 340 1653 396 1663
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+rect 237 1537 289 1547
+rect 396 1570 398 1629
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+rect 130 94 186 104
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+rect 237 89 289 99
+rect 186 7 237 66
+rect 130 -26 186 -17
+rect 237 -25 289 -15
+rect 312 -122 424 -112
+rect 312 -188 424 -178
+<< via2 >>
+rect 102 1813 214 1814
+rect 102 1761 112 1813
+rect 112 1761 194 1813
+rect 194 1761 214 1813
+rect 102 1758 214 1761
+rect 340 1542 396 1653
+rect 497 1211 553 1323
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+rect 130 -17 186 94
+rect 312 -125 424 -122
+rect 312 -177 332 -125
+rect 332 -177 414 -125
+rect 414 -177 424 -125
+rect 312 -178 424 -177
+<< metal3 >>
+rect 92 1814 224 1819
+rect 92 1758 102 1814
+rect 214 1758 224 1814
+rect 92 1753 224 1758
+rect 128 99 188 1753
+rect 330 1653 406 1658
+rect 330 1542 340 1653
+rect 396 1542 406 1653
+rect 330 1537 406 1542
+rect 120 94 196 99
+rect 120 -17 130 94
+rect 186 -17 196 94
+rect 120 -22 196 -17
+rect 338 -117 398 1537
+rect 495 1328 555 1333
+rect 487 1323 563 1328
+rect 487 1211 497 1323
+rect 553 1211 563 1323
+rect 487 1206 563 1211
+rect 495 399 555 1206
+rect 460 394 592 399
+rect 460 338 470 394
+rect 582 338 592 394
+rect 460 333 592 338
+rect 495 323 555 333
+rect 302 -122 434 -117
+rect 302 -178 312 -122
+rect 424 -178 434 -122
+rect 302 -183 434 -178
+use sky130_fd_pr__nfet_01v8_2BS854 sky130_fd_pr__nfet_01v8_2BS854_0
+timestamp 1624049879
+transform 1 0 836 0 1 395
+box -311 -335 311 335
+use sky130_fd_pr__pfet_01v8_MJG8BZ sky130_fd_pr__pfet_01v8_MJG8BZ_0
+timestamp 1624049879
+transform 1 0 263 0 1 1950
+box -263 -314 263 314
+use sky130_fd_pr__pfet_01v8_MJG8BZ sky130_fd_pr__pfet_01v8_MJG8BZ_1
+timestamp 1624049879
+transform -1 0 263 0 -1 -314
+box -263 -314 263 314
+use sky130_fd_pr__nfet_01v8_KU9PSX sky130_fd_pr__nfet_01v8_KU9PSX_1
+timestamp 1624049879
+transform 1 0 263 0 1 1271
+box -263 -305 263 305
+use sky130_fd_pr__nfet_01v8_KU9PSX sky130_fd_pr__nfet_01v8_KU9PSX_0
+timestamp 1624049879
+transform 1 0 263 0 -1 365
+box -263 -305 263 305
+<< labels >>
+rlabel metal1 -33 654 36 982 1 vss
+rlabel metal1 -33 2228 526 2282 1 vdd
+rlabel metal3 128 94 188 1758 1 Q
+rlabel metal3 338 -122 398 1542 1 nQ
+rlabel metal1 198 1104 328 1138 1 D
+rlabel metal1 198 498 328 532 1 nD
+rlabel metal1 -33 -646 526 -592 1 vdd
+rlabel metal1 714 192 954 232 1 CLK
+<< end >>
diff --git a/mag/loop_filter.mag b/mag/loop_filter.mag
new file mode 100644
index 0000000..b2e7fdf
--- /dev/null
+++ b/mag/loop_filter.mag
@@ -0,0 +1,140 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -16462 -24206 34360 5780
+<< psubdiff >>
+rect -16450 4360 -14850 4384
+rect -16450 -21664 -14850 -21640
+rect 32749 4360 34349 4384
+rect -16450 -22594 -14851 -21664
+rect 32749 -22593 34349 -21640
+rect 32749 -22594 34348 -22593
+rect -16450 -24194 -11039 -22594
+rect 28961 -24194 34348 -22594
+<< psubdiffcont >>
+rect -16450 -21640 -14850 4360
+rect 32749 -21640 34349 4360
+rect -11039 -24194 28961 -22594
+<< locali >>
+rect -16450 4360 -14850 4376
+rect 32749 4360 34349 4376
+rect -14851 -21656 -14850 -21640
+rect 34348 -21656 34349 -21640
+<< viali >>
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+rect 135 -119 4328 -40
+rect -16450 -22594 -14851 -21640
+rect 32749 -21640 34349 4360
+rect 32749 -22594 34348 -21640
+rect -16450 -24194 -11039 -22594
+rect -11039 -24194 28961 -22594
+rect 28961 -24194 34348 -22594
+<< metal1 >>
+rect -370 5080 -360 5680
+rect 640 5614 650 5680
+rect 2456 5614 2466 5680
+rect 640 5182 1312 5614
+rect 1560 5182 2466 5614
+rect 640 5080 650 5182
+rect 2456 5080 2466 5182
+rect 3866 5614 3876 5680
+rect 3866 5182 4100 5614
+rect 3866 5080 3876 5182
+rect -16456 4360 -14844 4372
+rect -16456 -21634 -16450 4360
+rect -16462 -24194 -16450 -21634
+rect -14850 -21634 -14844 4360
+rect 32743 4360 34355 4372
+rect 166 166 3245 598
+rect 40 -40 4361 83
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+rect 4328 -119 4361 -40
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+rect 1312 -1221 2954 -213
+rect 1312 -1273 2955 -1221
+rect 1313 -2326 2955 -1273
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+rect -14851 -22588 -14839 -21640
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+rect 34348 -22588 34354 -21652
+rect 34348 -24194 34360 -22588
+rect -16462 -24200 34360 -24194
+rect 32743 -24206 34354 -24200
+<< via1 >>
+rect -360 5080 640 5680
+rect 2466 5080 3866 5680
+rect -16353 -24105 34174 -22697
+<< metal2 >>
+rect -360 5680 640 5690
+rect -360 5070 640 5080
+rect 2466 5680 3866 5690
+rect 2466 5070 3866 5080
+rect -16353 -22697 34174 -22687
+rect -16353 -24115 34174 -24105
+<< via2 >>
+rect -360 5080 640 5680
+rect 2466 5080 3866 5680
+rect -16353 -24105 34174 -22697
+<< metal3 >>
+rect -370 5680 650 5685
+rect -370 5080 -360 5680
+rect 640 5080 650 5680
+rect -370 5075 650 5080
+rect 2456 5680 3876 5685
+rect 2456 5080 2466 5680
+rect 3866 5080 3876 5680
+rect 2456 5075 3876 5080
+rect -10059 -22692 -4267 -9184
+rect 4852 -21602 9433 4898
+rect 10833 -21602 14842 4898
+rect 16242 -21602 20055 4898
+rect 21455 -21602 25394 4898
+rect 26794 -21602 31427 4898
+rect 30027 -22692 31427 -21602
+rect -16363 -22697 34184 -22692
+rect -16363 -24105 -16353 -22697
+rect 34174 -24105 34184 -22697
+rect -16363 -24110 34184 -24105
+<< via3 >>
+rect -360 5080 640 5680
+rect 2466 5080 3866 5680
+<< metal4 >>
+rect -10754 5680 740 5780
+rect -10754 5080 -360 5680
+rect 640 5080 740 5680
+rect -10754 4980 740 5080
+rect 2066 5680 28119 5780
+rect 2066 5080 2466 5680
+rect 3866 5080 28119 5680
+rect 2066 4980 28119 5080
+use cap2_loop_filter cap2_loop_filter_0
+timestamp 1624049879
+transform 1 0 -4885 0 1 288
+box -8638 -9892 4299 5492
+use cap1_loop_filter cap1_loop_filter_0
+timestamp 1624049879
+transform 1 0 47404 0 1 20622
+box -42552 -43690 -15977 -14842
+use res_loop_filter res_loop_filter_0
+timestamp 1624049879
+transform 1 0 0 0 1 0
+box 0 0 1478 5780
+use res_loop_filter res_loop_filter_1
+timestamp 1624049879
+transform 1 0 1478 0 1 0
+box 0 0 1478 5780
+use res_loop_filter res_loop_filter_2
+timestamp 1624049879
+transform 1 0 2956 0 1 0
+box 0 0 1478 5780
+<< labels >>
+rlabel pwell 1313 -22594 2954 -168 1 vss
+rlabel metal4 -10754 4980 -360 5780 1 in
+rlabel metal4 3866 4980 28119 5780 1 vc_pex
+<< end >>
diff --git a/mag/loop_filter_v2.mag b/mag/loop_filter_v2.mag
new file mode 100644
index 0000000..d2fded5
--- /dev/null
+++ b/mag/loop_filter_v2.mag
@@ -0,0 +1,222 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624053471
+<< pwell >>
+rect -16462 -24206 34360 5780
+<< psubdiff >>
+rect -16450 4360 -14850 4384
+rect -16450 -21664 -14850 -21640
+rect 32749 4360 34349 4384
+rect -16450 -22594 -14851 -21664
+rect 32749 -22593 34349 -21640
+rect 32749 -22594 34348 -22593
+rect -16450 -24194 -11039 -22594
+rect 28961 -24194 34348 -22594
+<< psubdiffcont >>
+rect -16450 -21640 -14850 4360
+rect 32749 -21640 34349 4360
+rect -11039 -24194 28961 -22594
+<< locali >>
+rect -16450 4360 -14850 4376
+rect 32749 4360 34349 4376
+rect -14851 -21656 -14850 -21640
+rect 34348 -21656 34349 -21640
+<< viali >>
+rect -16450 -21640 -14850 4360
+rect 135 -119 4328 -40
+rect -7307 -9814 -6904 -9752
+rect -7302 -10770 -6916 -10690
+rect -16450 -22594 -14851 -21640
+rect 32749 -21640 34349 4360
+rect 32749 -22594 34348 -21640
+rect -16450 -24194 -11039 -22594
+rect -11039 -24194 28961 -22594
+rect 28961 -24194 34348 -22594
+<< metal1 >>
+rect -370 5080 -360 5680
+rect 640 5614 650 5680
+rect 2456 5614 2466 5680
+rect 640 5182 1312 5614
+rect 1560 5182 2466 5614
+rect 640 5080 650 5182
+rect 2456 5080 2466 5182
+rect 3866 5614 3876 5680
+rect 3866 5182 4100 5614
+rect 3866 5080 3876 5182
+rect -16456 4360 -14844 4372
+rect -16456 -21634 -16450 4360
+rect -16462 -24194 -16450 -21634
+rect -14850 -21634 -14844 4360
+rect 32743 4360 34355 4372
+rect 166 166 3245 598
+rect 40 -40 4361 83
+rect 40 -119 135 -40
+rect 4328 -119 4361 -40
+rect 40 -213 4361 -119
+rect 1312 -1221 2954 -213
+rect 1312 -1273 2955 -1221
+rect 1313 -2326 2955 -1273
+rect 1313 -9453 2954 -2326
+rect -6504 -9727 2954 -9453
+rect -6991 -9746 2954 -9727
+rect -7319 -9752 2954 -9746
+rect -7319 -9814 -7307 -9752
+rect -6904 -9814 2954 -9752
+rect -7319 -9820 2954 -9814
+rect -6991 -9828 2954 -9820
+rect -6504 -9899 2954 -9828
+rect -7439 -10421 -7429 -9948
+rect -7166 -10421 -7156 -9948
+rect -7058 -10418 -7048 -9951
+rect -6795 -10418 -6785 -9951
+rect -6504 -10023 -5622 -9899
+rect -5632 -10420 -5622 -10023
+rect -6603 -10492 -5622 -10420
+rect -3065 -10023 2954 -9899
+rect -3065 -10420 -3055 -10023
+rect 1313 -10420 2954 -10023
+rect -3065 -10492 2954 -10420
+rect -8110 -10653 -7078 -10573
+rect -6603 -10638 2954 -10492
+rect -7010 -10684 2954 -10638
+rect -7314 -10690 2954 -10684
+rect -7314 -10770 -7302 -10690
+rect -6916 -10770 2954 -10690
+rect -7314 -10776 2954 -10770
+rect -7010 -10794 2954 -10776
+rect -6603 -10990 2954 -10794
+rect -14850 -21640 -14839 -21634
+rect -14851 -22588 -14839 -21640
+rect 1313 -22588 2954 -10990
+rect 32743 -22588 32749 4360
+rect 34349 -21640 34355 4360
+rect -14851 -22594 32749 -22588
+rect 34348 -21652 34355 -21640
+rect 34348 -22588 34354 -21652
+rect 34348 -24194 34360 -22588
+rect -16462 -24200 34360 -24194
+rect 32743 -24206 34354 -24200
+<< via1 >>
+rect -360 5080 640 5680
+rect 2466 5080 3866 5680
+rect -7429 -10421 -7166 -9948
+rect -7048 -10418 -6795 -9951
+rect -5622 -10492 -3065 -9899
+rect -16353 -24105 34174 -22697
+<< metal2 >>
+rect -360 5680 640 5690
+rect -360 5070 640 5080
+rect 2466 5680 3866 5690
+rect 2466 5070 3866 5080
+rect -5622 -9899 -3065 -9889
+rect -7429 -9948 -7166 -9938
+rect -7429 -10431 -7166 -10421
+rect -7048 -9951 -6795 -9941
+rect -7048 -10428 -6795 -10418
+rect -5622 -10502 -3065 -10492
+rect -16353 -22697 34174 -22687
+rect -16353 -24115 34174 -24105
+<< via2 >>
+rect -360 5080 640 5680
+rect 2466 5080 3866 5680
+rect -7429 -10421 -7166 -9948
+rect -7048 -10418 -6795 -9951
+rect -5622 -10492 -3065 -9899
+rect -16353 -24105 34174 -22697
+<< metal3 >>
+rect -370 5680 650 5685
+rect -370 5080 -360 5680
+rect 640 5080 650 5680
+rect -370 5075 650 5080
+rect 2456 5680 3876 5685
+rect 2456 5080 2466 5680
+rect 3866 5080 3876 5680
+rect 2456 5075 3876 5080
+rect -11495 -12561 -8154 -8870
+rect -5655 -9894 -3064 -9027
+rect -5655 -9899 -3055 -9894
+rect -7439 -9948 -7156 -9943
+rect -7439 -10421 -7429 -9948
+rect -7166 -10421 -7156 -9948
+rect -7439 -10426 -7156 -10421
+rect -7058 -9951 -6785 -9946
+rect -7058 -10418 -7048 -9951
+rect -6795 -10418 -6785 -9951
+rect -7058 -10423 -6785 -10418
+rect -5655 -10492 -5622 -9899
+rect -3065 -10492 -3055 -9899
+rect -5655 -10497 -3055 -10492
+rect -5655 -12561 -3064 -10497
+rect -11495 -12710 -3064 -12561
+rect -11495 -12749 -4228 -12710
+rect -10301 -22692 -4228 -12749
+rect 4852 -21602 9433 4898
+rect 10833 -21602 14842 4898
+rect 16242 -21602 20055 4898
+rect 21455 -21602 25394 4898
+rect 26794 -21602 31427 4898
+rect 30027 -22692 31427 -21602
+rect -16363 -22697 34184 -22692
+rect -16363 -24105 -16353 -22697
+rect 34174 -24105 34184 -22697
+rect -16363 -24110 34184 -24105
+<< via3 >>
+rect -360 5080 640 5680
+rect 2466 5080 3866 5680
+rect -7429 -10421 -7166 -9948
+rect -7048 -10418 -6795 -9951
+<< metal4 >>
+rect -10754 5680 740 5780
+rect -10754 5080 -360 5680
+rect 640 5080 740 5680
+rect -10754 4980 740 5080
+rect 2066 5680 28119 5780
+rect 2066 5080 2466 5680
+rect 3866 5080 28119 5680
+rect 2066 4980 28119 5080
+rect -7435 -9947 -7175 -7442
+rect -7435 -9948 -7165 -9947
+rect -7435 -10418 -7429 -9948
+rect -7430 -10421 -7429 -10418
+rect -7166 -10421 -7165 -9948
+rect -7049 -9951 -6794 -9950
+rect -7049 -10418 -7048 -9951
+rect -6795 -10418 -6794 -9951
+rect -7049 -10419 -6794 -10418
+rect -7430 -10422 -7165 -10421
+rect -7025 -11171 -6797 -10419
+use sky130_fd_pr__nfet_01v8_U2JGXT sky130_fd_pr__nfet_01v8_U2JGXT_0
+timestamp 1624053471
+transform 1 0 -7109 0 1 -10245
+box -226 -510 226 510
+use cap3_loop_filter cap3_loop_filter_0
+timestamp 1624020278
+transform 1 0 -16372 0 1 -14182
+box 4830 -7521 13448 3227
+use res_loop_filter res_loop_filter_2
+timestamp 1624049879
+transform 1 0 2956 0 1 0
+box 0 0 1478 5780
+use res_loop_filter res_loop_filter_1
+timestamp 1624049879
+transform 1 0 1478 0 1 0
+box 0 0 1478 5780
+use res_loop_filter res_loop_filter_0
+timestamp 1624049879
+transform 1 0 0 0 1 0
+box 0 0 1478 5780
+use cap1_loop_filter cap1_loop_filter_0
+timestamp 1624049879
+transform 1 0 47404 0 1 20622
+box -42552 -43690 -15977 -14842
+use cap2_loop_filter cap2_loop_filter_0
+timestamp 1624049879
+transform 1 0 -4885 0 1 288
+box -8638 -9892 4299 5492
+<< labels >>
+rlabel pwell 1313 -22594 2954 -168 1 vss
+rlabel metal4 -10754 4980 -360 5780 1 in
+rlabel metal4 3866 4980 28119 5780 1 vc_pex
+rlabel metal1 -8110 -10653 -7078 -10573 1 D0_cap
+<< end >>
diff --git a/mag/magicrc b/mag/magicrc
new file mode 100644
index 0000000..7901958
--- /dev/null
+++ b/mag/magicrc
@@ -0,0 +1,82 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "~/skywater/pdk/skywater130/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/mimcap_decoup_1x5.mag b/mag/mimcap_decoup_1x5.mag
new file mode 100644
index 0000000..6709076
--- /dev/null
+++ b/mag/mimcap_decoup_1x5.mag
@@ -0,0 +1,32 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624376995
+<< metal5 >>
+rect 42 43 278 6161
+rect 664 142 6584 6062
+rect 6986 43 7222 6161
+rect 7608 142 13528 6062
+rect 13930 43 14166 6161
+rect 14552 142 20472 6062
+rect 20874 43 21110 6161
+rect 21496 142 27416 6062
+rect 27818 43 28054 6161
+rect 28440 142 34360 6062
+use sky130_fd_pr__cap_mim_m3_2_2Y8F6P decap
+array 0 4 -6944 0 0 -991
+timestamp 1624129585
+transform -1 0 3373 0 -1 3102
+box -3351 -3261 3373 3261
+<< labels >>
+rlabel metal5 27818 43 28054 6161 1 b
+rlabel metal5 20874 43 21110 6161 1 b
+rlabel metal5 13930 43 14166 6161 1 b
+rlabel metal5 6986 43 7222 6161 1 b
+rlabel metal5 42 43 278 6161 1 b
+rlabel metal5 664 142 6584 6062 1 t
+rlabel metal5 7608 142 13528 6062 1 t
+rlabel metal5 14552 142 20472 6062 1 t
+rlabel metal5 21496 142 27416 6062 1 t
+rlabel metal5 28440 142 34360 6062 1 t
+<< end >>
diff --git a/mag/nor_pfd.mag b/mag/nor_pfd.mag
new file mode 100644
index 0000000..b54607b
--- /dev/null
+++ b/mag/nor_pfd.mag
@@ -0,0 +1,119 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -235 1684 483 1772
+<< pwell >>
+rect -235 1054 -139 1066
+rect 409 1064 483 1066
+rect -235 922 -131 1054
+rect -235 556 -139 922
+rect 387 556 483 1064
+rect -235 468 483 556
+<< psubdiff >>
+rect -199 861 -165 934
+rect -199 626 -165 655
+rect 413 872 447 934
+rect 413 626 447 666
+rect -199 592 -23 626
+rect 255 592 447 626
+rect -31 504 -7 538
+rect 255 504 279 538
+<< nsubdiff >>
+rect -127 1702 -103 1736
+rect 351 1702 375 1736
+<< psubdiffcont >>
+rect -199 655 -165 861
+rect 413 666 447 872
+rect -7 504 255 538
+<< nsubdiffcont >>
+rect -103 1702 351 1736
+<< poly >>
+rect -35 1193 31 1217
+rect -35 1111 -25 1193
+rect 9 1111 31 1193
+rect 253 1125 319 1259
+rect -35 948 31 1111
+rect 157 1059 319 1125
+rect 157 1053 223 1059
+rect 157 971 172 1053
+rect 206 971 223 1053
+rect -35 882 61 948
+rect 157 878 223 971
+<< polycont >>
+rect -25 1111 9 1193
+rect 172 971 206 1053
+<< locali >>
+rect -25 1193 9 1209
+rect -25 1095 9 1111
+rect 172 1053 206 1069
+rect 172 955 206 971
+rect -199 861 -165 934
+rect -199 626 -165 655
+rect 413 872 447 934
+rect 413 626 447 666
+rect -199 592 -103 626
+rect 351 592 447 626
+<< viali >>
+rect -199 1702 -103 1736
+rect -103 1702 351 1736
+rect 351 1702 447 1736
+rect -199 1614 447 1648
+rect -25 1111 9 1193
+rect 172 971 206 1053
+rect -103 592 351 626
+rect -103 504 -7 538
+rect -7 504 255 538
+rect 255 504 351 538
+<< metal1 >>
+rect -235 1736 483 1742
+rect -235 1702 -199 1736
+rect 447 1702 483 1736
+rect -235 1648 483 1702
+rect -235 1614 -199 1648
+rect 447 1614 483 1648
+rect -235 1608 483 1614
+rect -91 1463 -45 1608
+rect 293 1463 339 1608
+rect 293 1375 329 1463
+rect 101 1256 147 1297
+rect 101 1210 337 1256
+rect -31 1193 15 1205
+rect -31 1186 -25 1193
+rect -235 1120 -25 1186
+rect -31 1111 -25 1120
+rect 9 1111 15 1193
+rect -31 1099 15 1111
+rect 166 1053 212 1065
+rect 166 1025 172 1053
+rect -235 971 172 1025
+rect 206 971 212 1053
+rect -235 959 212 971
+rect 291 931 337 1210
+rect 101 885 337 931
+rect 101 855 147 885
+rect 5 632 51 774
+rect 197 632 243 776
+rect -235 626 483 632
+rect -235 592 -103 626
+rect 351 592 483 626
+rect -235 538 483 592
+rect -235 504 -103 538
+rect 351 504 483 538
+rect -235 498 483 504
+use sky130_fd_pr__nfet_01v8_C3YG4M sky130_fd_pr__nfet_01v8_C3YG4M_0
+timestamp 1624049879
+transform 1 0 124 0 1 811
+box -263 -255 263 255
+use sky130_fd_pr__pfet_01v8_4F35BC sky130_fd_pr__pfet_01v8_4F35BC_0
+timestamp 1624049879
+transform 1 0 124 0 1 1375
+box -359 -309 359 309
+<< labels >>
+rlabel metal1 -235 1648 483 1702 1 vdd
+rlabel metal1 -235 538 483 592 1 vss
+rlabel metal1 -235 1120 -25 1186 1 A
+rlabel metal1 -235 959 172 1025 1 B
+rlabel metal1 291 885 337 1256 1 out
+<< end >>
diff --git a/mag/pfd_cp_interface.mag b/mag/pfd_cp_interface.mag
new file mode 100644
index 0000000..f157ae0
--- /dev/null
+++ b/mag/pfd_cp_interface.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< metal1 >>
+rect 983 2998 993 3026
+rect 0 2944 993 2998
+rect 983 2914 993 2944
+rect 1161 2998 1171 3026
+rect 1161 2944 2154 2998
+rect 1161 2914 1171 2944
+rect 0 2259 226 2325
+rect 442 2259 832 2325
+rect 1054 2259 1672 2325
+rect 1964 2259 2154 2325
+rect 0 1564 2143 1570
+rect 0 1504 2154 1564
+rect 0 1498 2143 1504
+rect 0 743 226 809
+rect 478 742 720 809
+rect 1094 743 1672 809
+rect 1964 743 2154 809
+rect 983 124 993 152
+rect 0 108 993 124
+rect 0 70 979 108
+rect 983 40 993 108
+rect 1161 124 1171 152
+rect 1161 108 2154 124
+rect 1161 40 1171 108
+rect 1176 70 2154 108
+<< via1 >>
+rect 993 2914 1161 3026
+rect 993 40 1161 152
+<< metal2 >>
+rect 993 3026 1161 3036
+rect 993 2904 1161 2914
+rect 993 152 1161 162
+rect 993 30 1161 40
+<< via2 >>
+rect 993 2914 1161 3026
+rect 993 40 1161 152
+<< metal3 >>
+rect 983 3026 1171 3031
+rect 983 2914 993 3026
+rect 1161 2914 1171 3026
+rect 983 2909 1171 2914
+rect 1017 157 1137 2909
+rect 983 152 1171 157
+rect 983 40 993 152
+rect 1161 40 1171 152
+rect 983 35 1171 40
+use trans_gate trans_gate_0
+timestamp 1624049879
+transform 1 0 675 0 -1 723
+box -53 -811 569 723
+use inverter_cp_x2 inverter_cp_x2_0
+timestamp 1624049879
+transform 1 0 1244 0 -1 776
+box 0 -758 910 776
+use inverter_cp_x2 inverter_cp_x2_1
+timestamp 1624049879
+transform 1 0 1244 0 1 2292
+box 0 -758 910 776
+use inverter_cp_x1 inverter_cp_x1_0
+timestamp 1624049879
+transform 1 0 0 0 -1 776
+box 0 -758 622 776
+use inverter_cp_x1 inverter_cp_x1_2
+timestamp 1624049879
+transform 1 0 622 0 1 2292
+box 0 -758 622 776
+use inverter_cp_x1 inverter_cp_x1_1
+timestamp 1624049879
+transform 1 0 0 0 1 2292
+box 0 -758 622 776
+<< labels >>
+rlabel metal1 0 1498 2143 1570 1 vss
+rlabel metal1 0 2259 226 2325 1 QA
+rlabel metal1 0 743 226 809 1 QB
+rlabel metal1 1054 2259 1672 2325 1 Up
+rlabel metal1 1094 743 1672 809 1 nDown
+rlabel metal1 1964 743 2154 809 1 Down
+rlabel metal1 1964 2259 2154 2325 1 nUp
+rlabel metal1 0 2944 2154 2998 1 vdd
+<< end >>
diff --git a/mag/res_loop_filter.mag b/mag/res_loop_filter.mag
new file mode 100644
index 0000000..6fc3e7c
--- /dev/null
+++ b/mag/res_loop_filter.mag
@@ -0,0 +1,22 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< viali >>
+rect 126 34 1358 84
+<< metal1 >>
+rect 144 5172 1336 5636
+rect 148 158 1340 622
+rect 114 84 1370 90
+rect 114 34 126 84
+rect 1358 34 1370 84
+rect 114 28 1370 34
+use sky130_fd_pr__res_high_po_5p73_X44RQA *sky130_fd_pr__res_high_po_5p73_X44RQA_0
+timestamp 1624049879
+transform 1 0 739 0 1 2890
+box -739 -2890 739 2890
+<< labels >>
+rlabel metal1 144 5172 1336 5636 1 in
+rlabel viali 126 34 1358 84 1 vss
+rlabel metal1 148 158 1340 622 1 out
+<< end >>
diff --git a/mag/ring_osc.mag b/mag/ring_osc.mag
new file mode 100644
index 0000000..64e387b
--- /dev/null
+++ b/mag/ring_osc.mag
@@ -0,0 +1,166 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -422 2867 0 2956
+<< pwell >>
+rect 1294 809 1725 1389
+rect 2588 809 3019 1389
+rect -422 165 -411 166
+rect -422 0 0 165
+<< psubdiff >>
+rect -314 36 -290 70
+rect -132 36 -108 70
+<< nsubdiff >>
+rect -314 2886 -290 2920
+rect -132 2886 -108 2920
+<< psubdiffcont >>
+rect -290 36 -132 70
+<< nsubdiffcont >>
+rect -290 2886 -132 2920
+<< viali >>
+rect -386 2886 -290 2920
+rect -290 2886 -132 2920
+rect -132 2886 -36 2920
+rect -386 2797 -36 2831
+rect -386 125 -36 159
+rect -386 36 -290 70
+rect -290 36 -132 70
+rect -132 36 -36 70
+<< metal1 >>
+rect -422 2920 0 2926
+rect -422 2886 -386 2920
+rect -36 2886 0 2920
+rect -422 2831 0 2886
+rect -422 2797 -386 2831
+rect -36 2797 0 2831
+rect -422 2791 0 2797
+rect -324 2348 -278 2791
+rect -243 2695 -233 2747
+rect -129 2695 -119 2747
+rect -243 2686 -144 2695
+rect -190 2646 -144 2686
+rect -190 2199 -144 2353
+rect -236 739 -98 2199
+rect 1294 779 1725 957
+rect 2588 779 3019 957
+rect -324 165 -278 599
+rect -190 597 -144 739
+rect -243 261 -119 270
+rect -243 209 -233 261
+rect -129 209 -119 261
+rect -422 159 0 165
+rect -422 125 -386 159
+rect -36 125 0 159
+rect -422 70 0 125
+rect -422 36 -386 70
+rect -36 36 0 70
+rect -422 30 0 36
+<< via1 >>
+rect -233 2695 -129 2747
+rect -233 209 -129 261
+<< metal2 >>
+rect -233 2747 3061 2757
+rect -129 2695 3061 2747
+rect -233 2685 3061 2695
+rect 440 1417 608 1427
+rect 3316 1417 3440 1427
+rect 1255 1363 1757 1415
+rect 2557 1363 3030 1415
+rect 440 1351 608 1361
+rect 3651 1363 3882 1415
+rect 3316 1351 3440 1361
+rect -233 261 2860 271
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+rect 2365 103 3603 159
+rect 3659 103 3669 159
+rect 1015 94 1071 103
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+<< via2 >>
+rect 440 1361 608 1417
+rect 3316 1361 3440 1417
+rect 1015 103 1071 159
+rect 2309 103 2365 159
+rect 3603 103 3659 159
+<< metal3 >>
+rect 430 1421 618 1422
+rect 430 1417 441 1421
+rect 607 1417 618 1421
+rect 430 1361 440 1417
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+rect 430 1357 441 1361
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+rect 3593 159 3669 164
+rect 3593 103 3603 159
+rect 3659 103 3669 159
+rect 3593 98 3669 103
+rect 1013 94 1073 98
+rect 2307 90 2367 98
+<< via3 >>
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+rect 441 1361 607 1417
+rect 441 1357 607 1361
+rect 3317 1417 3440 1421
+rect 3317 1361 3440 1417
+rect 3317 1357 3440 1361
+<< metal4 >>
+rect 440 1421 608 1422
+rect 3316 1421 3441 1422
+rect 440 1357 441 1421
+rect 607 1357 3317 1421
+rect 3440 1357 3441 1421
+rect 440 1356 608 1357
+rect 3316 1356 3441 1357
+use csvco_branch csvco_branch_2
+timestamp 1624049879
+transform 1 0 2951 0 1 1002
+box -363 -1002 931 1954
+use csvco_branch csvco_branch_1
+timestamp 1624049879
+transform 1 0 1657 0 1 1002
+box -363 -1002 931 1954
+use csvco_branch csvco_branch_0
+timestamp 1624049879
+transform 1 0 363 0 1 1002
+box -363 -1002 931 1954
+use sky130_fd_pr__pfet_01v8_4757AC sky130_fd_pr__pfet_01v8_4757AC_0
+timestamp 1624049879
+transform 1 0 -211 0 1 2498
+box -211 -369 211 369
+use sky130_fd_pr__nfet_01v8_CBAU6Y sky130_fd_pr__nfet_01v8_CBAU6Y_0
+timestamp 1624049879
+transform 1 0 -211 0 1 449
+box -211 -360 211 360
+<< labels >>
+rlabel metal2 -77 211 -25 263 1 vctrl
+rlabel metal1 -422 70 0 125 1 vss
+rlabel metal1 -422 2831 0 2886 1 vdd
+rlabel metal2 3651 1363 3882 1415 1 out_vco
+rlabel via2 2309 103 2365 159 1 D0
+<< end >>
diff --git a/mag/ring_osc_buffer.mag b/mag/ring_osc_buffer.mag
new file mode 100644
index 0000000..6244cdd
--- /dev/null
+++ b/mag/ring_osc_buffer.mag
@@ -0,0 +1,36 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624402156
+<< nwell >>
+rect 1 1259 1963 1270
+rect 1 744 1961 1259
+<< metal1 >>
+rect 491 1186 1963 1187
+rect 1 1133 1963 1186
+rect 1 1132 1954 1133
+rect 1 535 213 589
+rect 397 523 639 603
+rect 1078 519 1490 603
+rect 1796 519 1963 597
+rect 0 40 1963 94
+use inverter_min_x4 inverter_min_x4_0
+timestamp 1624049879
+transform 1 0 580 0 1 616
+box -53 -616 665 643
+use inverter_min_x4 inverter_min_x4_1
+timestamp 1624049879
+transform 1 0 1298 0 1 616
+box -53 -616 665 643
+use inverter_min_x2 inverter_min_x2_0
+timestamp 1624049879
+transform 1 0 54 0 1 615
+box -53 -615 473 655
+<< labels >>
+rlabel metal1 1 535 213 589 1 in_vco
+rlabel metal1 397 523 639 603 1 o1
+rlabel metal1 1078 519 1490 603 1 out_div
+rlabel metal1 1796 519 1963 597 1 out_pad
+rlabel metal1 491 1132 1954 1187 1 vdd
+rlabel metal1 0 40 1963 94 1 vss
+<< end >>
diff --git a/mag/ring_osc_v2.mag b/mag/ring_osc_v2.mag
new file mode 100644
index 0000000..c130acd
--- /dev/null
+++ b/mag/ring_osc_v2.mag
@@ -0,0 +1,178 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624065706
+<< nwell >>
+rect -422 2867 0 2956
+<< pwell >>
+rect 1294 809 1725 1389
+rect 2588 809 3019 1389
+rect -422 165 -411 166
+rect -422 0 0 165
+<< psubdiff >>
+rect -314 36 -290 70
+rect -132 36 -108 70
+<< nsubdiff >>
+rect -314 2886 -290 2920
+rect -132 2886 -108 2920
+<< psubdiffcont >>
+rect -290 36 -132 70
+<< nsubdiffcont >>
+rect -290 2886 -132 2920
+<< viali >>
+rect -386 2886 -290 2920
+rect -290 2886 -132 2920
+rect -132 2886 -36 2920
+rect -386 2797 -36 2831
+rect -386 125 -36 159
+rect -386 36 -290 70
+rect -290 36 -132 70
+rect -132 36 -36 70
+<< metal1 >>
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+rect -36 2898 3882 2920
+rect -36 2886 0 2898
+rect -422 2831 0 2886
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+rect -36 36 0 70
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+<< via1 >>
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+rect -233 2747 3266 2757
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+<< via2 >>
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+<< via3 >>
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+rect 3317 1357 3440 1361
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+<< metal4 >>
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+rect 2377 799 3594 866
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+rect 1100 798 3680 799
+rect 1100 797 1101 798
+rect 992 796 1101 797
+use csvco_branch_v2 csvco_branch_v2_1
+timestamp 1624064496
+transform 1 0 1657 0 1 1002
+box -363 -1002 932 1955
+use csvco_branch_v2 csvco_branch_v2_2
+timestamp 1624064496
+transform 1 0 2951 0 1 1002
+box -363 -1002 932 1955
+use sky130_fd_pr__pfet_01v8_4757AC sky130_fd_pr__pfet_01v8_4757AC_0
+timestamp 1624049879
+transform 1 0 -211 0 1 2498
+box -211 -369 211 369
+use sky130_fd_pr__nfet_01v8_CBAU6Y sky130_fd_pr__nfet_01v8_CBAU6Y_0
+timestamp 1624049879
+transform 1 0 -211 0 1 449
+box -211 -360 211 360
+use csvco_branch_v2 csvco_branch_v2_0
+timestamp 1624064496
+transform 1 0 363 0 1 1002
+box -363 -1002 932 1955
+<< labels >>
+rlabel metal1 -422 70 0 125 1 vss
+rlabel metal1 -422 2831 0 2886 1 vdd
+rlabel metal2 3651 1363 3882 1415 1 out_vco
+rlabel metal3 3601 88 3661 148 1 D0
+rlabel metal2 -105 212 -39 260 1 vctrl
+rlabel metal2 41 2699 69 2726 1 vbp
+<< end >>
diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_MACBVW.mag b/mag/sky130_fd_pr__cap_mim_m3_1_MACBVW.mag
new file mode 100644
index 0000000..6b1cd42
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_1_MACBVW.mag
@@ -0,0 +1,385 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< metal3 >>
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+rect 2808 -7761 7730 -7760
+rect 8127 -7760 8128 -5800
+rect 13048 -7760 13049 -2840
+rect 8127 -7761 13049 -7760
+rect -11188 -8139 -10188 -7761
+rect -5869 -8139 -4869 -7761
+rect -551 -8139 449 -7761
+rect 4767 -8139 5767 -7761
+rect 10085 -8139 11085 -7761
+rect 13187 -7872 13203 -2728
+rect 13267 -7872 13283 -2728
+rect 13187 -7888 13283 -7872
+rect 13187 -8028 13283 -8012
+rect -13149 -8140 -8227 -8139
+rect -13149 -13060 -13148 -8140
+rect -8228 -10100 -8227 -8140
+rect -7830 -8140 -2908 -8139
+rect -7830 -10100 -7829 -8140
+rect -8228 -11100 -7829 -10100
+rect -8228 -13060 -8227 -11100
+rect -13149 -13061 -8227 -13060
+rect -7830 -13060 -7829 -11100
+rect -2909 -10100 -2908 -8140
+rect -2511 -8140 2411 -8139
+rect -2511 -10100 -2510 -8140
+rect -2909 -11100 -2510 -10100
+rect -2909 -13060 -2908 -11100
+rect -7830 -13061 -2908 -13060
+rect -2511 -13060 -2510 -11100
+rect 2410 -10100 2411 -8140
+rect 2808 -8140 7730 -8139
+rect 2808 -10100 2809 -8140
+rect 2410 -11100 2809 -10100
+rect 2410 -13060 2411 -11100
+rect -2511 -13061 2411 -13060
+rect 2808 -13060 2809 -11100
+rect 7729 -10100 7730 -8140
+rect 8127 -8140 13049 -8139
+rect 8127 -10100 8128 -8140
+rect 7729 -11100 8128 -10100
+rect 7729 -13060 7730 -11100
+rect 2808 -13061 7730 -13060
+rect 8127 -13060 8128 -11100
+rect 13048 -13060 13049 -8140
+rect 8127 -13061 13049 -13060
+rect 13187 -13172 13203 -8028
+rect 13267 -13172 13283 -8028
+rect 13187 -13188 13283 -13172
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_1
+string FIXED_BBOX 7988 8000 13188 13200
+string parameters w 25 l 25 val 1.269k carea 2.00 cperi 0.19 nx 5 ny 5 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 0 tconnect 0 ccov 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_W3JTNJ.mag b/mag/sky130_fd_pr__cap_mim_m3_1_W3JTNJ.mag
new file mode 100644
index 0000000..fc6bee6
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_1_W3JTNJ.mag
@@ -0,0 +1,145 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< metal3 >>
+rect -6469 2200 -2301 6400
+rect -2150 2200 2018 6400
+rect 2169 6372 6468 6400
+rect 2169 2228 6384 6372
+rect 6448 2228 6468 6372
+rect 2169 2200 6468 2228
+rect -6469 -2100 -2301 2100
+rect -2150 -2100 2018 2100
+rect 2169 2072 6468 2100
+rect 2169 -2072 6384 2072
+rect 6448 -2072 6468 2072
+rect 2169 -2100 6468 -2072
+rect -6469 -6400 -2301 -2200
+rect -2150 -6400 2018 -2200
+rect 2169 -2228 6468 -2200
+rect 2169 -6372 6384 -2228
+rect 6448 -6372 6468 -2228
+rect 2169 -6400 6468 -6372
+<< via3 >>
+rect 6384 2228 6448 6372
+rect 6384 -2072 6448 2072
+rect 6384 -6372 6448 -2228
+<< mimcap >>
+rect -6369 6260 -2369 6300
+rect -6369 2340 -6329 6260
+rect -2409 2340 -2369 6260
+rect -6369 2300 -2369 2340
+rect -2050 6260 1950 6300
+rect -2050 2340 -2010 6260
+rect 1910 2340 1950 6260
+rect -2050 2300 1950 2340
+rect 2269 6260 6269 6300
+rect 2269 2340 2309 6260
+rect 6229 2340 6269 6260
+rect 2269 2300 6269 2340
+rect -6369 1960 -2369 2000
+rect -6369 -1960 -6329 1960
+rect -2409 -1960 -2369 1960
+rect -6369 -2000 -2369 -1960
+rect -2050 1960 1950 2000
+rect -2050 -1960 -2010 1960
+rect 1910 -1960 1950 1960
+rect -2050 -2000 1950 -1960
+rect 2269 1960 6269 2000
+rect 2269 -1960 2309 1960
+rect 6229 -1960 6269 1960
+rect 2269 -2000 6269 -1960
+rect -6369 -2340 -2369 -2300
+rect -6369 -6260 -6329 -2340
+rect -2409 -6260 -2369 -2340
+rect -6369 -6300 -2369 -6260
+rect -2050 -2340 1950 -2300
+rect -2050 -6260 -2010 -2340
+rect 1910 -6260 1950 -2340
+rect -2050 -6300 1950 -6260
+rect 2269 -2340 6269 -2300
+rect 2269 -6260 2309 -2340
+rect 6229 -6260 6269 -2340
+rect 2269 -6300 6269 -6260
+<< mimcapcontact >>
+rect -6329 2340 -2409 6260
+rect -2010 2340 1910 6260
+rect 2309 2340 6229 6260
+rect -6329 -1960 -2409 1960
+rect -2010 -1960 1910 1960
+rect 2309 -1960 6229 1960
+rect -6329 -6260 -2409 -2340
+rect -2010 -6260 1910 -2340
+rect 2309 -6260 6229 -2340
+<< metal4 >>
+rect -4421 6261 -4317 6450
+rect -102 6261 2 6450
+rect 4217 6261 4321 6450
+rect 6337 6388 6441 6450
+rect 6337 6372 6464 6388
+rect -6330 6260 -2408 6261
+rect -6330 2340 -6329 6260
+rect -2409 2340 -2408 6260
+rect -6330 2339 -2408 2340
+rect -2011 6260 1911 6261
+rect -2011 2340 -2010 6260
+rect 1910 2340 1911 6260
+rect -2011 2339 1911 2340
+rect 2308 6260 6230 6261
+rect 2308 2340 2309 6260
+rect 6229 2340 6230 6260
+rect 2308 2339 6230 2340
+rect -4421 1961 -4317 2339
+rect -102 1961 2 2339
+rect 4217 1961 4321 2339
+rect 6337 2228 6384 6372
+rect 6448 2228 6464 6372
+rect 6337 2212 6464 2228
+rect 6337 2088 6441 2212
+rect 6337 2072 6464 2088
+rect -6330 1960 -2408 1961
+rect -6330 -1960 -6329 1960
+rect -2409 -1960 -2408 1960
+rect -6330 -1961 -2408 -1960
+rect -2011 1960 1911 1961
+rect -2011 -1960 -2010 1960
+rect 1910 -1960 1911 1960
+rect -2011 -1961 1911 -1960
+rect 2308 1960 6230 1961
+rect 2308 -1960 2309 1960
+rect 6229 -1960 6230 1960
+rect 2308 -1961 6230 -1960
+rect -4421 -2339 -4317 -1961
+rect -102 -2339 2 -1961
+rect 4217 -2339 4321 -1961
+rect 6337 -2072 6384 2072
+rect 6448 -2072 6464 2072
+rect 6337 -2088 6464 -2072
+rect 6337 -2212 6441 -2088
+rect 6337 -2228 6464 -2212
+rect -6330 -2340 -2408 -2339
+rect -6330 -6260 -6329 -2340
+rect -2409 -6260 -2408 -2340
+rect -6330 -6261 -2408 -6260
+rect -2011 -2340 1911 -2339
+rect -2011 -6260 -2010 -2340
+rect 1910 -6260 1911 -2340
+rect -2011 -6261 1911 -6260
+rect 2308 -2340 6230 -2339
+rect 2308 -6260 2309 -2340
+rect 6229 -6260 6230 -2340
+rect 2308 -6261 6230 -6260
+rect -4421 -6450 -4317 -6261
+rect -102 -6450 2 -6261
+rect 4217 -6450 4321 -6261
+rect 6337 -6372 6384 -2228
+rect 6448 -6372 6464 -2228
+rect 6337 -6388 6464 -6372
+rect 6337 -6450 6441 -6388
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_1
+string FIXED_BBOX 2169 2200 6369 6400
+string parameters w 20 l 20 val 815.2 carea 2.00 cperi 0.19 nx 3 ny 3 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_WHJTNJ.mag b/mag/sky130_fd_pr__cap_mim_m3_1_WHJTNJ.mag
new file mode 100644
index 0000000..910513b
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_1_WHJTNJ.mag
@@ -0,0 +1,80 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624020278
+<< metal3 >>
+rect -4309 50 -141 4250
+rect 10 4222 4309 4250
+rect 10 78 4225 4222
+rect 4289 78 4309 4222
+rect 10 50 4309 78
+rect -4309 -4250 -141 -50
+rect 10 -78 4309 -50
+rect 10 -4222 4225 -78
+rect 4289 -4222 4309 -78
+rect 10 -4250 4309 -4222
+<< via3 >>
+rect 4225 78 4289 4222
+rect 4225 -4222 4289 -78
+<< mimcap >>
+rect -4209 4110 -209 4150
+rect -4209 190 -4169 4110
+rect -249 190 -209 4110
+rect -4209 150 -209 190
+rect 110 4110 4110 4150
+rect 110 190 150 4110
+rect 4070 190 4110 4110
+rect 110 150 4110 190
+rect -4209 -190 -209 -150
+rect -4209 -4110 -4169 -190
+rect -249 -4110 -209 -190
+rect -4209 -4150 -209 -4110
+rect 110 -190 4110 -150
+rect 110 -4110 150 -190
+rect 4070 -4110 4110 -190
+rect 110 -4150 4110 -4110
+<< mimcapcontact >>
+rect -4169 190 -249 4110
+rect 150 190 4070 4110
+rect -4169 -4110 -249 -190
+rect 150 -4110 4070 -190
+<< metal4 >>
+rect -2261 4111 -2157 4300
+rect 2058 4111 2162 4300
+rect 4178 4238 4282 4300
+rect 4178 4222 4305 4238
+rect -4170 4110 -248 4111
+rect -4170 190 -4169 4110
+rect -249 190 -248 4110
+rect -4170 189 -248 190
+rect 149 4110 4071 4111
+rect 149 190 150 4110
+rect 4070 190 4071 4110
+rect 149 189 4071 190
+rect -2261 -189 -2157 189
+rect 2058 -189 2162 189
+rect 4178 78 4225 4222
+rect 4289 78 4305 4222
+rect 4178 62 4305 78
+rect 4178 -62 4282 62
+rect 4178 -78 4305 -62
+rect -4170 -190 -248 -189
+rect -4170 -4110 -4169 -190
+rect -249 -4110 -248 -190
+rect -4170 -4111 -248 -4110
+rect 149 -190 4071 -189
+rect 149 -4110 150 -190
+rect 4070 -4110 4071 -190
+rect 149 -4111 4071 -4110
+rect -2261 -4300 -2157 -4111
+rect 2058 -4300 2162 -4111
+rect 4178 -4222 4225 -78
+rect 4289 -4222 4305 -78
+rect 4178 -4238 4305 -4222
+rect 4178 -4300 4282 -4238
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_1
+string FIXED_BBOX 10 50 4210 4250
+string parameters w 20 l 20 val 815.2 carea 2.00 cperi 0.19 nx 2 ny 2 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_2Y8F6P.mag b/mag/sky130_fd_pr__cap_mim_m3_2_2Y8F6P.mag
new file mode 100644
index 0000000..84b5fbd
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_2Y8F6P.mag
@@ -0,0 +1,33 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624129585
+<< metal4 >>
+rect -3351 3059 3351 3100
+rect -3351 -3059 3095 3059
+rect 3331 -3059 3351 3059
+rect -3351 -3100 3351 -3059
+<< via4 >>
+rect 3095 -3059 3331 3059
+<< mimcap2 >>
+rect -3251 2960 2749 3000
+rect -3251 -2960 -3211 2960
+rect 2709 -2960 2749 2960
+rect -3251 -3000 2749 -2960
+<< mimcap2contact >>
+rect -3211 -2960 2709 2960
+<< metal5 >>
+rect 3053 3059 3373 3261
+rect -3235 2960 2733 2984
+rect -3235 -2960 -3211 2960
+rect 2709 -2960 2733 2960
+rect -3235 -2984 2733 -2960
+rect 3053 -3059 3095 3059
+rect 3331 -3059 3373 3059
+rect 3053 -3261 3373 -3059
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_2
+string FIXED_BBOX -3351 -3100 2849 3100
+string parameters w 30 l 30 val 920.4 carea 1.00 cperi 0.17 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_2BS6QM.mag b/mag/sky130_fd_pr__nfet_01v8_2BS6QM.mag
new file mode 100644
index 0000000..8926531
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_2BS6QM.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -311 -335 311 335
+<< nmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< ndiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< ndiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< psubdiff >>
+rect -275 203 -241 265
+rect 241 203 275 265
+rect -275 -265 -241 -203
+rect 241 -265 275 -203
+rect -275 -299 -179 -265
+rect 179 -299 275 -265
+<< psubdiffcont >>
+rect -275 -203 -241 203
+rect 241 -203 275 203
+rect -179 -299 179 -265
+<< poly >>
+rect -111 151 111 181
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -151 -81 -125
+rect -15 -151 15 -125
+rect 81 -151 111 -125
+<< locali >>
+rect -275 203 -241 265
+rect 241 203 275 265
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -275 -265 -241 -203
+rect 241 -265 275 -203
+rect -275 -299 -179 -265
+rect 179 -299 275 -265
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -258 -282 258 282
+string parameters w 1.25 l 0.150 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_2BS854.mag b/mag/sky130_fd_pr__nfet_01v8_2BS854.mag
new file mode 100644
index 0000000..f971b0a
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_2BS854.mag
@@ -0,0 +1,103 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -311 -335 311 335
+<< nmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< ndiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< ndiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< psubdiff >>
+rect -241 205 -179 239
+rect 179 205 241 239
+rect -241 -299 -179 -265
+rect 179 -299 241 -265
+<< psubdiffcont >>
+rect -179 205 179 239
+rect -179 -299 179 -265
+<< poly >>
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -147 -81 -125
+rect -15 -147 15 -125
+rect 81 -147 111 -125
+rect -129 -166 129 -147
+rect -129 -200 -106 -166
+rect 102 -200 129 -166
+rect -129 -213 129 -200
+<< polycont >>
+rect -106 -200 102 -166
+<< locali >>
+rect -241 205 -179 239
+rect 179 205 241 239
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -241 -299 -179 -265
+rect 179 -299 241 -265
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+rect -122 -166 118 -163
+rect -122 -200 -106 -166
+rect -106 -200 102 -166
+rect 102 -200 118 -166
+rect -122 -203 118 -200
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+rect -134 -163 130 -157
+rect -134 -203 -122 -163
+rect 118 -203 130 -163
+rect -134 -209 130 -203
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -258 -282 258 282
+string parameters w 1.25 l 0.150 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 0 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_5RJ8EK.mag b/mag/sky130_fd_pr__nfet_01v8_5RJ8EK.mag
new file mode 100644
index 0000000..10786fb
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_5RJ8EK.mag
@@ -0,0 +1,82 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -263 -64 263 252
+rect -263 -66 -81 -64
+rect -63 -66 -33 -64
+rect -15 -66 263 -64
+rect -263 -252 263 -66
+<< nmos >>
+rect -63 -42 -33 42
+rect 33 -42 63 42
+<< ndiff >>
+rect -125 30 -63 42
+rect -125 -30 -113 30
+rect -79 -30 -63 30
+rect -125 -42 -63 -30
+rect -33 30 33 42
+rect -33 -30 -17 30
+rect 17 -30 33 30
+rect -33 -42 33 -30
+rect 63 30 125 42
+rect 63 -30 79 30
+rect 113 -30 125 30
+rect 63 -42 125 -30
+<< ndiffc >>
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+<< psubdiff >>
+rect -227 120 -193 182
+rect 193 120 227 182
+rect -227 -182 -193 -120
+rect 193 -182 227 -120
+rect -227 -216 -131 -182
+rect 131 -216 227 -182
+<< psubdiffcont >>
+rect -227 -120 -193 120
+rect 193 -120 227 120
+rect -131 -216 131 -182
+<< poly >>
+rect -63 42 -33 68
+rect 33 42 63 68
+rect -63 -68 -33 -42
+rect 33 -68 63 -42
+<< locali >>
+rect -227 120 -193 182
+rect 193 120 227 182
+rect -113 30 -79 46
+rect -113 -46 -79 -30
+rect -17 30 17 46
+rect -17 -46 17 -30
+rect 79 30 113 46
+rect 79 -46 113 -30
+rect -227 -182 -193 -120
+rect 193 -182 227 -120
+rect -227 -216 -131 -182
+rect 131 -216 227 -182
+<< viali >>
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+<< metal1 >>
+rect -119 30 -73 42
+rect -119 -30 -113 30
+rect -79 -30 -73 30
+rect -119 -42 -73 -30
+rect -23 30 23 42
+rect -23 -30 -17 30
+rect 17 -30 23 30
+rect -23 -42 23 -30
+rect 73 30 119 42
+rect 73 -30 79 30
+rect 113 -30 119 30
+rect 73 -42 119 -30
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -199 210 199
+string parameters w 0.420 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_7H8F5S.mag b/mag/sky130_fd_pr__nfet_01v8_7H8F5S.mag
new file mode 100644
index 0000000..096127d
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_7H8F5S.mag
@@ -0,0 +1,261 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -647 -360 647 360
+<< nmos >>
+rect -447 -150 -417 150
+rect -351 -150 -321 150
+rect -255 -150 -225 150
+rect -159 -150 -129 150
+rect -63 -150 -33 150
+rect 33 -150 63 150
+rect 129 -150 159 150
+rect 225 -150 255 150
+rect 321 -150 351 150
+rect 417 -150 447 150
+<< ndiff >>
+rect -509 138 -447 150
+rect -509 -138 -497 138
+rect -463 -138 -447 138
+rect -509 -150 -447 -138
+rect -417 138 -351 150
+rect -417 -138 -401 138
+rect -367 -138 -351 138
+rect -417 -150 -351 -138
+rect -321 138 -255 150
+rect -321 -138 -305 138
+rect -271 -138 -255 138
+rect -321 -150 -255 -138
+rect -225 138 -159 150
+rect -225 -138 -209 138
+rect -175 -138 -159 138
+rect -225 -150 -159 -138
+rect -129 138 -63 150
+rect -129 -138 -113 138
+rect -79 -138 -63 138
+rect -129 -150 -63 -138
+rect -33 138 33 150
+rect -33 -138 -17 138
+rect 17 -138 33 138
+rect -33 -150 33 -138
+rect 63 138 129 150
+rect 63 -138 79 138
+rect 113 -138 129 138
+rect 63 -150 129 -138
+rect 159 138 225 150
+rect 159 -138 175 138
+rect 209 -138 225 138
+rect 159 -150 225 -138
+rect 255 138 321 150
+rect 255 -138 271 138
+rect 305 -138 321 138
+rect 255 -150 321 -138
+rect 351 138 417 150
+rect 351 -138 367 138
+rect 401 -138 417 138
+rect 351 -150 417 -138
+rect 447 138 509 150
+rect 447 -138 463 138
+rect 497 -138 509 138
+rect 447 -150 509 -138
+<< ndiffc >>
+rect -497 -138 -463 138
+rect -401 -138 -367 138
+rect -305 -138 -271 138
+rect -209 -138 -175 138
+rect -113 -138 -79 138
+rect -17 -138 17 138
+rect 79 -138 113 138
+rect 175 -138 209 138
+rect 271 -138 305 138
+rect 367 -138 401 138
+rect 463 -138 497 138
+<< psubdiff >>
+rect -611 290 -515 324
+rect 515 290 611 324
+rect -611 228 -577 290
+rect 577 228 611 290
+rect -611 -290 -577 -228
+rect 577 -290 611 -228
+rect -611 -324 -515 -290
+rect 515 -324 611 -290
+<< psubdiffcont >>
+rect -515 290 515 324
+rect -611 -228 -577 228
+rect 577 -228 611 228
+rect -515 -324 515 -290
+<< poly >>
+rect -465 222 465 238
+rect -465 188 -449 222
+rect -415 188 -353 222
+rect -319 188 -257 222
+rect -223 188 -161 222
+rect -127 188 -65 222
+rect -31 188 31 222
+rect 65 188 127 222
+rect 161 188 223 222
+rect 257 188 319 222
+rect 353 188 415 222
+rect 449 188 465 222
+rect -465 172 465 188
+rect -447 150 -417 172
+rect -351 150 -321 172
+rect -255 150 -225 172
+rect -159 150 -129 172
+rect -63 150 -33 172
+rect 33 150 63 172
+rect 129 150 159 172
+rect 225 150 255 172
+rect 321 150 351 172
+rect 417 150 447 172
+rect -447 -176 -417 -150
+rect -351 -176 -321 -150
+rect -255 -176 -225 -150
+rect -159 -176 -129 -150
+rect -63 -176 -33 -150
+rect 33 -176 63 -150
+rect 129 -176 159 -150
+rect 225 -176 255 -150
+rect 321 -176 351 -150
+rect 417 -176 447 -150
+<< polycont >>
+rect -449 188 -415 222
+rect -353 188 -319 222
+rect -257 188 -223 222
+rect -161 188 -127 222
+rect -65 188 -31 222
+rect 31 188 65 222
+rect 127 188 161 222
+rect 223 188 257 222
+rect 319 188 353 222
+rect 415 188 449 222
+<< locali >>
+rect -611 290 -515 324
+rect 515 290 611 324
+rect -611 228 -577 290
+rect 577 228 611 290
+rect -465 188 -449 222
+rect -415 188 -353 222
+rect -319 188 -257 222
+rect -223 188 -161 222
+rect -127 188 -65 222
+rect -31 188 31 222
+rect 65 188 127 222
+rect 161 188 223 222
+rect 257 188 319 222
+rect 353 188 415 222
+rect 449 188 465 222
+rect -497 138 -463 154
+rect -497 -154 -463 -138
+rect -401 138 -367 154
+rect -401 -154 -367 -138
+rect -305 138 -271 154
+rect -305 -154 -271 -138
+rect -209 138 -175 154
+rect -209 -154 -175 -138
+rect -113 138 -79 154
+rect -113 -154 -79 -138
+rect -17 138 17 154
+rect -17 -154 17 -138
+rect 79 138 113 154
+rect 79 -154 113 -138
+rect 175 138 209 154
+rect 175 -154 209 -138
+rect 271 138 305 154
+rect 271 -154 305 -138
+rect 367 138 401 154
+rect 367 -154 401 -138
+rect 463 138 497 154
+rect 463 -154 497 -138
+rect -611 -290 -577 -228
+rect 577 -290 611 -228
+rect -611 -324 -515 -290
+rect 515 -324 611 -290
+<< viali >>
+rect -449 188 -415 222
+rect -353 188 -319 222
+rect -257 188 -223 222
+rect -161 188 -127 222
+rect -65 188 -31 222
+rect 31 188 65 222
+rect 127 188 161 222
+rect 223 188 257 222
+rect 319 188 353 222
+rect 415 188 449 222
+rect -497 -138 -463 138
+rect -401 -138 -367 138
+rect -305 -138 -271 138
+rect -209 -138 -175 138
+rect -113 -138 -79 138
+rect -17 -138 17 138
+rect 79 -138 113 138
+rect 175 -138 209 138
+rect 271 -138 305 138
+rect 367 -138 401 138
+rect 463 -138 497 138
+<< metal1 >>
+rect -464 222 464 231
+rect -464 188 -449 222
+rect -415 188 -353 222
+rect -319 188 -257 222
+rect -223 188 -161 222
+rect -127 188 -65 222
+rect -31 188 31 222
+rect 65 188 127 222
+rect 161 188 223 222
+rect 257 188 319 222
+rect 353 188 415 222
+rect 449 188 464 222
+rect -464 179 464 188
+rect -503 138 -457 150
+rect -503 -138 -497 138
+rect -463 -138 -457 138
+rect -503 -150 -457 -138
+rect -407 138 -361 150
+rect -407 -138 -401 138
+rect -367 -138 -361 138
+rect -407 -150 -361 -138
+rect -311 138 -265 150
+rect -311 -138 -305 138
+rect -271 -138 -265 138
+rect -311 -150 -265 -138
+rect -215 138 -169 150
+rect -215 -138 -209 138
+rect -175 -138 -169 138
+rect -215 -150 -169 -138
+rect -119 138 -73 150
+rect -119 -138 -113 138
+rect -79 -138 -73 138
+rect -119 -150 -73 -138
+rect -23 138 23 150
+rect -23 -138 -17 138
+rect 17 -138 23 138
+rect -23 -150 23 -138
+rect 73 138 119 150
+rect 73 -138 79 138
+rect 113 -138 119 138
+rect 73 -150 119 -138
+rect 169 138 215 150
+rect 169 -138 175 138
+rect 209 -138 215 138
+rect 169 -150 215 -138
+rect 265 138 311 150
+rect 265 -138 271 138
+rect 305 -138 311 138
+rect 265 -150 311 -138
+rect 361 138 407 150
+rect 361 -138 367 138
+rect 401 -138 407 138
+rect 361 -150 407 -138
+rect 457 138 503 150
+rect 457 -138 463 138
+rect 497 -138 503 138
+rect 457 -150 503 -138
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -594 -307 594 307
+string parameters w 1.5 l 0.150 m 1 nf 10 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_8GRULZ.mag b/mag/sky130_fd_pr__nfet_01v8_8GRULZ.mag
new file mode 100644
index 0000000..188586a
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_8GRULZ.mag
@@ -0,0 +1,189 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -1957 -254 1957 254
+<< nmos >>
+rect -1761 -44 -1461 106
+rect -1403 -44 -1103 106
+rect -1045 -44 -745 106
+rect -687 -44 -387 106
+rect -329 -44 -29 106
+rect 29 -44 329 106
+rect 387 -44 687 106
+rect 745 -44 1045 106
+rect 1103 -44 1403 106
+rect 1461 -44 1761 106
+<< ndiff >>
+rect -1819 94 -1761 106
+rect -1819 -32 -1807 94
+rect -1773 -32 -1761 94
+rect -1819 -44 -1761 -32
+rect -1461 94 -1403 106
+rect -1461 -32 -1449 94
+rect -1415 -32 -1403 94
+rect -1461 -44 -1403 -32
+rect -1103 94 -1045 106
+rect -1103 -32 -1091 94
+rect -1057 -32 -1045 94
+rect -1103 -44 -1045 -32
+rect -745 94 -687 106
+rect -745 -32 -733 94
+rect -699 -32 -687 94
+rect -745 -44 -687 -32
+rect -387 94 -329 106
+rect -387 -32 -375 94
+rect -341 -32 -329 94
+rect -387 -44 -329 -32
+rect -29 94 29 106
+rect -29 -32 -17 94
+rect 17 -32 29 94
+rect -29 -44 29 -32
+rect 329 94 387 106
+rect 329 -32 341 94
+rect 375 -32 387 94
+rect 329 -44 387 -32
+rect 687 94 745 106
+rect 687 -32 699 94
+rect 733 -32 745 94
+rect 687 -44 745 -32
+rect 1045 94 1103 106
+rect 1045 -32 1057 94
+rect 1091 -32 1103 94
+rect 1045 -44 1103 -32
+rect 1403 94 1461 106
+rect 1403 -32 1415 94
+rect 1449 -32 1461 94
+rect 1403 -44 1461 -32
+rect 1761 94 1819 106
+rect 1761 -32 1773 94
+rect 1807 -32 1819 94
+rect 1761 -44 1819 -32
+<< ndiffc >>
+rect -1807 -32 -1773 94
+rect -1449 -32 -1415 94
+rect -1091 -32 -1057 94
+rect -733 -32 -699 94
+rect -375 -32 -341 94
+rect -17 -32 17 94
+rect 341 -32 375 94
+rect 699 -32 733 94
+rect 1057 -32 1091 94
+rect 1415 -32 1449 94
+rect 1773 -32 1807 94
+<< psubdiff >>
+rect -1887 184 -1825 218
+rect 1825 184 1887 218
+<< psubdiffcont >>
+rect -1825 184 1825 218
+<< poly >>
+rect -1761 106 -1461 132
+rect -1403 106 -1103 132
+rect -1045 106 -745 132
+rect -687 106 -387 132
+rect -329 106 -29 132
+rect 29 106 329 132
+rect 387 106 687 132
+rect 745 106 1045 132
+rect 1103 106 1403 132
+rect 1461 106 1761 132
+rect -1761 -66 -1461 -44
+rect -1403 -66 -1103 -44
+rect -1045 -66 -745 -44
+rect -687 -66 -387 -44
+rect -329 -66 -29 -44
+rect 29 -66 329 -44
+rect 387 -66 687 -44
+rect 745 -66 1045 -44
+rect 1103 -66 1403 -44
+rect 1461 -66 1761 -44
+rect -1761 -132 1761 -66
+<< locali >>
+rect -1887 184 -1825 218
+rect 1825 184 1887 218
+rect -1807 94 -1773 110
+rect -1807 -48 -1773 -32
+rect -1449 94 -1415 110
+rect -1449 -48 -1415 -32
+rect -1091 94 -1057 110
+rect -1091 -48 -1057 -32
+rect -733 94 -699 110
+rect -733 -48 -699 -32
+rect -375 94 -341 110
+rect -375 -48 -341 -32
+rect -17 94 17 110
+rect -17 -48 17 -32
+rect 341 94 375 110
+rect 341 -48 375 -32
+rect 699 94 733 110
+rect 699 -48 733 -32
+rect 1057 94 1091 110
+rect 1057 -48 1091 -32
+rect 1415 94 1449 110
+rect 1415 -48 1449 -32
+rect 1773 94 1807 110
+rect 1773 -48 1807 -32
+<< viali >>
+rect -1807 -32 -1773 94
+rect -1449 -32 -1415 94
+rect -1091 -32 -1057 94
+rect -733 -32 -699 94
+rect -375 -32 -341 94
+rect -17 -32 17 94
+rect 341 -32 375 94
+rect 699 -32 733 94
+rect 1057 -32 1091 94
+rect 1415 -32 1449 94
+rect 1773 -32 1807 94
+<< metal1 >>
+rect -1813 94 -1767 106
+rect -1813 -32 -1807 94
+rect -1773 -32 -1767 94
+rect -1813 -44 -1767 -32
+rect -1455 94 -1409 106
+rect -1455 -32 -1449 94
+rect -1415 -32 -1409 94
+rect -1455 -44 -1409 -32
+rect -1097 94 -1051 106
+rect -1097 -32 -1091 94
+rect -1057 -32 -1051 94
+rect -1097 -44 -1051 -32
+rect -739 94 -693 106
+rect -739 -32 -733 94
+rect -699 -32 -693 94
+rect -739 -44 -693 -32
+rect -381 94 -335 106
+rect -381 -32 -375 94
+rect -341 -32 -335 94
+rect -381 -44 -335 -32
+rect -23 94 23 106
+rect -23 -32 -17 94
+rect 17 -32 23 94
+rect -23 -44 23 -32
+rect 335 94 381 106
+rect 335 -32 341 94
+rect 375 -32 381 94
+rect 335 -44 381 -32
+rect 693 94 739 106
+rect 693 -32 699 94
+rect 733 -32 739 94
+rect 693 -44 739 -32
+rect 1051 94 1097 106
+rect 1051 -32 1057 94
+rect 1091 -32 1097 94
+rect 1051 -44 1097 -32
+rect 1409 94 1455 106
+rect 1409 -32 1415 94
+rect 1449 -32 1455 94
+rect 1409 -44 1455 -32
+rect 1767 94 1813 106
+rect 1767 -32 1773 94
+rect 1807 -32 1813 94
+rect 1767 -44 1813 -32
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -1904 -201 1904 201
+string parameters w 0.75 l 1.5 m 1 nf 10 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_AQR2CW.mag b/mag/sky130_fd_pr__nfet_01v8_AQR2CW.mag
new file mode 100644
index 0000000..997dd71
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_AQR2CW.mag
@@ -0,0 +1,64 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -216 -254 216 254
+<< nmos >>
+rect -20 -106 20 44
+<< ndiff >>
+rect -78 32 -20 44
+rect -78 -94 -66 32
+rect -32 -94 -20 32
+rect -78 -106 -20 -94
+rect 20 32 78 44
+rect 20 -94 32 32
+rect 66 -94 78 32
+rect 20 -106 78 -94
+<< ndiffc >>
+rect -66 -94 -32 32
+rect 32 -94 66 32
+<< psubdiff >>
+rect -180 122 -146 184
+rect 146 122 180 184
+rect -180 -184 -146 -122
+rect 146 -184 180 -122
+rect -180 -218 -84 -184
+rect 84 -218 180 -184
+<< psubdiffcont >>
+rect -180 -122 -146 122
+rect 146 -122 180 122
+rect -84 -218 84 -184
+<< poly >>
+rect -33 66 33 132
+rect -20 44 20 66
+rect -20 -132 20 -106
+<< locali >>
+rect -180 122 -146 184
+rect 146 122 180 184
+rect -66 32 -32 48
+rect -66 -110 -32 -94
+rect 32 32 66 48
+rect 32 -110 66 -94
+rect -180 -184 -146 -122
+rect 146 -184 180 -122
+rect -180 -218 -84 -184
+rect 84 -218 180 -184
+<< viali >>
+rect -66 -94 -32 32
+rect 32 -94 66 32
+<< metal1 >>
+rect -72 32 -26 44
+rect -72 -94 -66 32
+rect -32 -94 -26 32
+rect -72 -106 -26 -94
+rect 26 32 72 44
+rect 26 -94 32 32
+rect 66 -94 72 32
+rect 26 -106 72 -94
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -163 -201 163 201
+string parameters w 0.75 l 0.2 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_AZESM8.mag b/mag/sky130_fd_pr__nfet_01v8_AZESM8.mag
new file mode 100644
index 0000000..d4649f1
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_AZESM8.mag
@@ -0,0 +1,138 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -455 -335 455 335
+<< nmos >>
+rect -255 -125 -225 125
+rect -159 -125 -129 125
+rect -63 -125 -33 125
+rect 33 -125 63 125
+rect 129 -125 159 125
+rect 225 -125 255 125
+<< ndiff >>
+rect -317 113 -255 125
+rect -317 -113 -305 113
+rect -271 -113 -255 113
+rect -317 -125 -255 -113
+rect -225 113 -159 125
+rect -225 -113 -209 113
+rect -175 -113 -159 113
+rect -225 -125 -159 -113
+rect -129 113 -63 125
+rect -129 -113 -113 113
+rect -79 -113 -63 113
+rect -129 -125 -63 -113
+rect -33 113 33 125
+rect -33 -113 -17 113
+rect 17 -113 33 113
+rect -33 -125 33 -113
+rect 63 113 129 125
+rect 63 -113 79 113
+rect 113 -113 129 113
+rect 63 -125 129 -113
+rect 159 113 225 125
+rect 159 -113 175 113
+rect 209 -113 225 113
+rect 159 -125 225 -113
+rect 255 113 317 125
+rect 255 -113 271 113
+rect 305 -113 317 113
+rect 255 -125 317 -113
+<< ndiffc >>
+rect -305 -113 -271 113
+rect -209 -113 -175 113
+rect -113 -113 -79 113
+rect -17 -113 17 113
+rect 79 -113 113 113
+rect 175 -113 209 113
+rect 271 -113 305 113
+<< psubdiff >>
+rect -419 203 -385 265
+rect 385 203 419 265
+rect -419 -265 -385 -203
+rect 385 -265 419 -203
+rect -419 -299 -323 -265
+rect 323 -299 419 -265
+<< psubdiffcont >>
+rect -419 -203 -385 203
+rect 385 -203 419 203
+rect -323 -299 323 -265
+<< poly >>
+rect -255 125 -225 151
+rect -159 125 -129 151
+rect -63 125 -33 151
+rect 33 125 63 151
+rect 129 125 159 151
+rect 225 125 255 151
+rect -255 -151 -225 -125
+rect -159 -151 -129 -125
+rect -63 -151 -33 -125
+rect 33 -151 63 -125
+rect 129 -151 159 -125
+rect 225 -151 255 -125
+<< locali >>
+rect -419 203 -385 265
+rect 385 203 419 265
+rect -305 113 -271 129
+rect -305 -129 -271 -113
+rect -209 113 -175 129
+rect -209 -129 -175 -113
+rect -113 113 -79 129
+rect -113 -129 -79 -113
+rect -17 113 17 129
+rect -17 -129 17 -113
+rect 79 113 113 129
+rect 79 -129 113 -113
+rect 175 113 209 129
+rect 175 -129 209 -113
+rect 271 113 305 129
+rect 271 -129 305 -113
+rect -419 -265 -385 -203
+rect 385 -265 419 -203
+rect -419 -299 -323 -265
+rect 323 -299 419 -265
+<< viali >>
+rect -305 -113 -271 113
+rect -209 -113 -175 113
+rect -113 -113 -79 113
+rect -17 -113 17 113
+rect 79 -113 113 113
+rect 175 -113 209 113
+rect 271 -113 305 113
+<< metal1 >>
+rect -311 113 -265 125
+rect -311 -113 -305 113
+rect -271 -113 -265 113
+rect -311 -125 -265 -113
+rect -215 113 -169 125
+rect -215 -113 -209 113
+rect -175 -113 -169 113
+rect -215 -125 -169 -113
+rect -119 113 -73 125
+rect -119 -113 -113 113
+rect -79 -113 -73 113
+rect -119 -125 -73 -113
+rect -23 113 23 125
+rect -23 -113 -17 113
+rect 17 -113 23 113
+rect -23 -125 23 -113
+rect 73 113 119 125
+rect 73 -113 79 113
+rect 113 -113 119 113
+rect 73 -125 119 -113
+rect 169 113 215 125
+rect 169 -113 175 113
+rect 209 -113 215 113
+rect 169 -125 215 -113
+rect 265 113 311 125
+rect 265 -113 271 113
+rect 305 -113 311 113
+rect 265 -125 311 -113
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -402 -282 402 282
+string parameters w 1.25 l 0.150 m 1 nf 6 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_BHR94T.mag b/mag/sky130_fd_pr__nfet_01v8_BHR94T.mag
new file mode 100644
index 0000000..0f0e256
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_BHR94T.mag
@@ -0,0 +1,93 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -311 -335 311 335
+<< nmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< ndiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< ndiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< psubdiff >>
+rect -275 203 -241 265
+rect 241 203 275 265
+rect -275 -265 -241 -203
+rect 241 -265 275 -203
+rect -275 -299 -179 -265
+rect 179 -299 275 -265
+<< psubdiffcont >>
+rect -275 -203 -241 203
+rect 241 -203 275 203
+rect -179 -299 179 -265
+<< poly >>
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -151 -81 -125
+rect -15 -151 15 -125
+rect 81 -151 111 -125
+<< locali >>
+rect -275 203 -241 265
+rect 241 203 275 265
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -275 -265 -241 -203
+rect 241 -265 275 -203
+rect -275 -299 -179 -265
+rect 179 -299 275 -265
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -258 -282 258 282
+string parameters w 1.25 l 0.150 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_C3YG4M.mag b/mag/sky130_fd_pr__nfet_01v8_C3YG4M.mag
new file mode 100644
index 0000000..788f763
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_C3YG4M.mag
@@ -0,0 +1,70 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -263 -255 263 255
+<< nmos >>
+rect -63 -45 -33 45
+rect 33 -45 63 45
+<< ndiff >>
+rect -125 33 -63 45
+rect -125 -33 -113 33
+rect -79 -33 -63 33
+rect -125 -45 -63 -33
+rect -33 33 33 45
+rect -33 -33 -17 33
+rect 17 -33 33 33
+rect -33 -45 33 -33
+rect 63 33 125 45
+rect 63 -33 79 33
+rect 113 -33 125 33
+rect 63 -45 125 -33
+<< ndiffc >>
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+<< psubdiff >>
+rect -193 -219 -131 -185
+rect 131 -219 193 -185
+<< psubdiffcont >>
+rect -131 -219 131 -185
+<< poly >>
+rect -129 71 -33 137
+rect -63 45 -33 71
+rect 33 67 99 133
+rect 33 45 63 67
+rect -63 -71 -33 -45
+rect 33 -71 63 -45
+<< locali >>
+rect -113 33 -79 49
+rect -113 -49 -79 -33
+rect -17 33 17 49
+rect -17 -49 17 -33
+rect 79 33 113 49
+rect 79 -49 113 -33
+rect -193 -219 -131 -185
+rect 131 -219 193 -185
+<< viali >>
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+<< metal1 >>
+rect -119 33 -73 45
+rect -119 -33 -113 33
+rect -79 -33 -73 33
+rect -119 -45 -73 -33
+rect -23 33 23 45
+rect -23 -33 -17 33
+rect 17 -33 23 33
+rect -23 -45 23 -33
+rect 73 33 119 45
+rect 73 -33 79 33
+rect 113 -33 119 33
+rect 73 -45 119 -33
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -202 210 202
+string parameters w 0.45 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_CBAU6Y.mag b/mag/sky130_fd_pr__nfet_01v8_CBAU6Y.mag
new file mode 100644
index 0000000..ed5da4a
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_CBAU6Y.mag
@@ -0,0 +1,82 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< error_p >>
+rect -29 -188 29 -182
+rect -29 -222 -17 -188
+rect -29 -228 29 -222
+<< pwell >>
+rect -211 -360 211 360
+<< nmos >>
+rect -15 -150 15 150
+<< ndiff >>
+rect -73 138 -15 150
+rect -73 -138 -61 138
+rect -27 -138 -15 138
+rect -73 -150 -15 -138
+rect 15 138 73 150
+rect 15 -138 27 138
+rect 61 -138 73 138
+rect 15 -150 73 -138
+<< ndiffc >>
+rect -61 -138 -27 138
+rect 27 -138 61 138
+<< psubdiff >>
+rect -175 290 175 324
+rect -175 228 -141 290
+rect 141 228 175 290
+rect -175 -290 -141 -228
+rect 141 -290 175 -228
+rect -175 -324 -79 -290
+rect 79 -324 175 -290
+<< psubdiffcont >>
+rect -175 -228 -141 228
+rect 141 -228 175 228
+rect -79 -324 79 -290
+<< poly >>
+rect -15 150 15 176
+rect -15 -172 15 -150
+rect -33 -188 33 -172
+rect -33 -222 -17 -188
+rect 17 -222 33 -188
+rect -33 -238 33 -222
+<< polycont >>
+rect -17 -222 17 -188
+<< locali >>
+rect -175 290 175 324
+rect -175 228 -141 290
+rect 141 228 175 290
+rect -61 138 -27 154
+rect -61 -154 -27 -138
+rect 27 138 61 154
+rect 27 -154 61 -138
+rect -33 -222 -17 -188
+rect 17 -222 33 -188
+rect -175 -290 -141 -228
+rect 141 -290 175 -228
+rect -175 -324 -79 -290
+rect 79 -324 175 -290
+<< viali >>
+rect -61 -138 -27 138
+rect 27 -138 61 138
+rect -17 -222 17 -188
+<< metal1 >>
+rect -67 138 -21 150
+rect -67 -138 -61 138
+rect -27 -138 -21 138
+rect -67 -150 -21 -138
+rect 21 138 67 150
+rect 21 -138 27 138
+rect 61 -138 67 138
+rect 21 -150 67 -138
+rect -29 -188 29 -182
+rect -29 -222 -17 -188
+rect 17 -222 29 -188
+rect -29 -228 29 -222
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -307 158 307
+string parameters w 1.5 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_CBSTVW.mag b/mag/sky130_fd_pr__nfet_01v8_CBSTVW.mag
new file mode 100644
index 0000000..f567c55
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_CBSTVW.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624058804
+<< error_p >>
+rect -29 -157 29 -151
+rect -29 -191 -17 -157
+rect -29 -197 29 -191
+<< pwell >>
+rect -211 -329 211 329
+<< nmos >>
+rect -15 -119 15 181
+<< ndiff >>
+rect -73 169 -15 181
+rect -73 -107 -61 169
+rect -27 -107 -15 169
+rect -73 -119 -15 -107
+rect 15 169 73 181
+rect 15 -107 27 169
+rect 61 -107 73 169
+rect 15 -119 73 -107
+<< ndiffc >>
+rect -61 -107 -27 169
+rect 27 -107 61 169
+<< psubdiff >>
+rect -175 259 -79 293
+rect 79 259 175 293
+rect -175 197 -141 259
+rect 141 197 175 259
+rect -175 -259 -141 -197
+rect 141 -259 175 -197
+rect -175 -293 -79 -259
+rect 79 -293 175 -259
+<< psubdiffcont >>
+rect -79 259 79 293
+rect -175 -197 -141 197
+rect 141 -197 175 197
+rect -79 -293 79 -259
+<< poly >>
+rect -15 181 15 207
+rect -15 -141 15 -119
+rect -33 -157 33 -141
+rect -33 -191 -17 -157
+rect 17 -191 33 -157
+rect -33 -207 33 -191
+<< polycont >>
+rect -17 -191 17 -157
+<< locali >>
+rect -175 259 -79 293
+rect 79 259 175 293
+rect -175 197 -141 259
+rect 141 197 175 259
+rect -61 169 -27 185
+rect -61 -123 -27 -107
+rect 27 169 61 185
+rect 27 -123 61 -107
+rect -33 -191 -17 -157
+rect 17 -191 33 -157
+rect -175 -259 -141 -197
+rect 141 -259 175 -197
+rect -175 -293 -79 -259
+rect 79 -293 175 -259
+<< viali >>
+rect -61 -107 -27 169
+rect 27 -107 61 169
+rect -17 -191 17 -157
+<< metal1 >>
+rect -67 169 -21 181
+rect -67 -107 -61 169
+rect -27 -107 -21 169
+rect -67 -119 -21 -107
+rect 21 169 67 181
+rect 21 -107 27 169
+rect 61 -107 67 169
+rect 21 -119 67 -107
+rect -29 -157 29 -151
+rect -29 -191 -17 -157
+rect 17 -191 29 -157
+rect -29 -197 29 -191
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -276 158 276
+string parameters w 1.5 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_DXA56D.mag b/mag/sky130_fd_pr__nfet_01v8_DXA56D.mag
new file mode 100644
index 0000000..fc9b925
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_DXA56D.mag
@@ -0,0 +1,108 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -359 -252 359 252
+<< nmos >>
+rect -159 -42 -129 42
+rect -63 -42 -33 42
+rect 33 -42 63 42
+rect 129 -42 159 42
+<< ndiff >>
+rect -221 30 -159 42
+rect -221 -30 -209 30
+rect -175 -30 -159 30
+rect -221 -42 -159 -30
+rect -129 30 -63 42
+rect -129 -30 -113 30
+rect -79 -30 -63 30
+rect -129 -42 -63 -30
+rect -33 30 33 42
+rect -33 -30 -17 30
+rect 17 -30 33 30
+rect -33 -42 33 -30
+rect 63 30 129 42
+rect 63 -30 79 30
+rect 113 -30 129 30
+rect 63 -42 129 -30
+rect 159 30 221 42
+rect 159 -30 175 30
+rect 209 -30 221 30
+rect 159 -42 221 -30
+<< ndiffc >>
+rect -209 -30 -175 30
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+rect 175 -30 209 30
+<< psubdiff >>
+rect -323 120 -289 182
+rect 289 120 323 182
+rect -323 -182 -289 -120
+rect 289 -182 323 -120
+rect -323 -216 -227 -182
+rect 227 -216 323 -182
+<< psubdiffcont >>
+rect -323 -120 -289 120
+rect 289 -120 323 120
+rect -227 -216 227 -182
+<< poly >>
+rect -159 42 -129 68
+rect -63 42 -33 68
+rect 33 42 63 68
+rect 129 42 159 68
+rect -159 -68 -129 -42
+rect -63 -68 -33 -42
+rect 33 -68 63 -42
+rect 129 -68 159 -42
+<< locali >>
+rect -323 120 -289 182
+rect 289 120 323 182
+rect -209 30 -175 46
+rect -209 -46 -175 -30
+rect -113 30 -79 46
+rect -113 -46 -79 -30
+rect -17 30 17 46
+rect -17 -46 17 -30
+rect 79 30 113 46
+rect 79 -46 113 -30
+rect 175 30 209 46
+rect 175 -46 209 -30
+rect -323 -182 -289 -120
+rect 289 -182 323 -120
+rect -323 -216 -227 -182
+rect 227 -216 323 -182
+<< viali >>
+rect -209 -30 -175 30
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+rect 175 -30 209 30
+<< metal1 >>
+rect -215 30 -169 42
+rect -215 -30 -209 30
+rect -175 -30 -169 30
+rect -215 -42 -169 -30
+rect -119 30 -73 42
+rect -119 -30 -113 30
+rect -79 -30 -73 30
+rect -119 -42 -73 -30
+rect -23 30 23 42
+rect -23 -30 -17 30
+rect 17 -30 23 30
+rect -23 -42 23 -30
+rect 73 30 119 42
+rect 73 -30 79 30
+rect 113 -30 119 30
+rect 73 -42 119 -30
+rect 169 30 215 42
+rect 169 -30 175 30
+rect 209 -30 215 30
+rect 169 -42 215 -30
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -306 -199 306 199
+string parameters w 0.420 l 0.150 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_EDT3AT.mag b/mag/sky130_fd_pr__nfet_01v8_EDT3AT.mag
new file mode 100644
index 0000000..133c69b
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_EDT3AT.mag
@@ -0,0 +1,76 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -211 -221 211 221
+<< nmos >>
+rect -15 -11 15 73
+<< ndiff >>
+rect -73 61 -15 73
+rect -73 1 -61 61
+rect -27 1 -15 61
+rect -73 -11 -15 1
+rect 15 61 73 73
+rect 15 1 27 61
+rect 61 1 73 61
+rect 15 -11 73 1
+<< ndiffc >>
+rect -61 1 -27 61
+rect 27 1 61 61
+<< psubdiff >>
+rect -175 89 -141 151
+rect 141 89 175 151
+rect -175 -151 -141 -89
+rect 141 -151 175 -89
+rect -175 -185 -79 -151
+rect 79 -185 175 -151
+<< psubdiffcont >>
+rect -175 -89 -141 89
+rect 141 -89 175 89
+rect -79 -185 79 -151
+<< poly >>
+rect -15 73 15 99
+rect -15 -33 15 -11
+rect -33 -49 33 -33
+rect -33 -83 -17 -49
+rect 17 -83 33 -49
+rect -33 -99 33 -83
+<< polycont >>
+rect -17 -83 17 -49
+<< locali >>
+rect -175 89 -141 151
+rect 141 89 175 151
+rect -61 61 -27 77
+rect -61 -15 -27 1
+rect 27 61 61 77
+rect 27 -15 61 1
+rect -33 -83 -17 -49
+rect 17 -83 33 -49
+rect -175 -151 -141 -89
+rect 141 -151 175 -89
+rect -175 -185 -79 -151
+rect 79 -185 175 -151
+<< viali >>
+rect -61 1 -27 61
+rect 27 1 61 61
+rect -17 -83 17 -49
+<< metal1 >>
+rect -67 61 -21 73
+rect -67 1 -61 61
+rect -27 1 -21 61
+rect -67 -11 -21 1
+rect 21 61 67 73
+rect 21 1 27 61
+rect 61 1 67 61
+rect 21 -11 67 1
+rect -32 -49 32 -40
+rect -32 -83 -17 -49
+rect 17 -83 32 -49
+rect -32 -92 32 -83
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -168 158 168
+string parameters w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_KU9PSX.mag b/mag/sky130_fd_pr__nfet_01v8_KU9PSX.mag
new file mode 100644
index 0000000..37dce9b
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_KU9PSX.mag
@@ -0,0 +1,103 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -263 -305 263 305
+<< nmos >>
+rect -63 -95 -33 95
+rect 33 -95 63 95
+<< ndiff >>
+rect -125 83 -63 95
+rect -125 -83 -113 83
+rect -79 -83 -63 83
+rect -125 -95 -63 -83
+rect -33 83 33 95
+rect -33 -83 -17 83
+rect 17 -83 33 83
+rect -33 -95 33 -83
+rect 63 83 125 95
+rect 63 -83 79 83
+rect 113 -83 125 83
+rect 63 -95 125 -83
+<< ndiffc >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+<< psubdiff >>
+rect -227 173 -193 235
+rect -227 -235 -193 -173
+rect -227 -269 -168 -235
+rect 178 -269 227 -235
+<< psubdiffcont >>
+rect -227 -173 -193 173
+rect -168 -269 178 -235
+<< poly >>
+rect -63 95 -33 121
+rect 33 95 63 121
+rect -63 -117 -33 -95
+rect 33 -117 63 -95
+rect -81 -133 81 -117
+rect -81 -167 -65 -133
+rect 65 -167 81 -133
+rect -81 -183 81 -167
+<< polycont >>
+rect -65 -167 65 -133
+<< locali >>
+rect -227 173 -193 235
+rect -113 83 -79 99
+rect -113 -99 -79 -83
+rect -17 83 17 99
+rect -17 -99 17 -83
+rect 79 83 113 99
+rect 79 -99 113 -83
+rect -81 -167 -65 -133
+rect 65 -167 81 -133
+rect -227 -235 -193 -173
+rect -227 -269 -168 -235
+rect 178 -269 227 -235
+<< viali >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+rect -65 -167 65 -133
+<< metal1 >>
+rect -119 84 -73 95
+rect -132 -85 -122 84
+rect -70 -85 -60 84
+rect -23 83 23 95
+rect 73 84 119 95
+rect -23 -83 -17 83
+rect 17 -83 23 83
+rect -119 -95 -73 -85
+rect -23 -95 23 -83
+rect 60 -85 70 84
+rect 122 -85 132 84
+rect 73 -95 119 -85
+rect -77 -133 77 -127
+rect -77 -167 -65 -133
+rect 65 -167 77 -133
+rect -77 -173 77 -167
+<< via1 >>
+rect -122 83 -70 84
+rect -122 -83 -113 83
+rect -113 -83 -79 83
+rect -79 -83 -70 83
+rect -122 -85 -70 -83
+rect 70 83 122 84
+rect 70 -83 79 83
+rect 79 -83 113 83
+rect 113 -83 122 83
+rect 70 -85 122 -83
+<< metal2 >>
+rect -122 84 -70 94
+rect 70 84 122 94
+rect -70 -85 70 84
+rect -122 -95 -70 -85
+rect 70 -95 122 -85
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -252 210 252
+string parameters w 0.95 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_MUHGM9.mag b/mag/sky130_fd_pr__nfet_01v8_MUHGM9.mag
new file mode 100644
index 0000000..fe33d1f
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_MUHGM9.mag
@@ -0,0 +1,340 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -1127 -285 1127 285
+<< nmos >>
+rect -927 -75 -897 75
+rect -831 -75 -801 75
+rect -735 -75 -705 75
+rect -639 -75 -609 75
+rect -543 -75 -513 75
+rect -447 -75 -417 75
+rect -351 -75 -321 75
+rect -255 -75 -225 75
+rect -159 -75 -129 75
+rect -63 -75 -33 75
+rect 33 -75 63 75
+rect 129 -75 159 75
+rect 225 -75 255 75
+rect 321 -75 351 75
+rect 417 -75 447 75
+rect 513 -75 543 75
+rect 609 -75 639 75
+rect 705 -75 735 75
+rect 801 -75 831 75
+rect 897 -75 927 75
+<< ndiff >>
+rect -989 63 -927 75
+rect -989 -63 -977 63
+rect -943 -63 -927 63
+rect -989 -75 -927 -63
+rect -897 63 -831 75
+rect -897 -63 -881 63
+rect -847 -63 -831 63
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+rect 543 -63 559 63
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+rect 543 -75 609 -63
+rect 639 63 705 75
+rect 639 -63 655 63
+rect 689 -63 705 63
+rect 639 -75 705 -63
+rect 735 63 801 75
+rect 735 -63 751 63
+rect 785 -63 801 63
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+rect 831 63 897 75
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+rect 927 63 989 75
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+rect 977 -63 989 63
+rect 927 -75 989 -63
+<< ndiffc >>
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+rect -881 -63 -847 63
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+rect -689 -63 -655 63
+rect -593 -63 -559 63
+rect -497 -63 -463 63
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+rect 655 -63 689 63
+rect 751 -63 785 63
+rect 847 -63 881 63
+rect 943 -63 977 63
+<< psubdiff >>
+rect -1057 -249 -995 -215
+rect 995 -249 1057 -215
+<< psubdiffcont >>
+rect -995 -249 995 -215
+<< poly >>
+rect -927 97 -33 163
+rect -927 75 -897 97
+rect -831 75 -801 97
+rect -735 75 -705 97
+rect -639 75 -609 97
+rect -543 75 -513 97
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+rect 225 -101 255 -75
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+rect 513 -101 543 -75
+rect 609 -101 639 -75
+rect 705 -101 735 -75
+rect 801 -101 831 -75
+rect 897 -101 927 -75
+<< locali >>
+rect -977 63 -943 79
+rect -977 -79 -943 -63
+rect -881 63 -847 79
+rect -881 -79 -847 -63
+rect -785 63 -751 79
+rect -785 -79 -751 -63
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+rect -209 -79 -175 -63
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+rect -17 63 17 79
+rect -17 -79 17 -63
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+rect 175 63 209 79
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+rect 847 -79 881 -63
+rect 943 63 977 79
+rect 943 -79 977 -63
+rect -1057 -249 -995 -215
+rect 995 -249 1057 -215
+<< viali >>
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+rect -593 -63 -559 63
+rect -497 -63 -463 63
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+rect 847 -63 881 63
+rect 943 -63 977 63
+<< metal1 >>
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+rect -983 -63 -977 63
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+rect -887 63 -841 75
+rect -887 -63 -881 63
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+rect 73 -63 79 63
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+rect 73 -75 119 -63
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+rect 265 63 311 75
+rect 265 -63 271 63
+rect 305 -63 311 63
+rect 265 -75 311 -63
+rect 361 63 407 75
+rect 361 -63 367 63
+rect 401 -63 407 63
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+rect 457 63 503 75
+rect 457 -63 463 63
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+rect 457 -75 503 -63
+rect 553 63 599 75
+rect 553 -63 559 63
+rect 593 -63 599 63
+rect 553 -75 599 -63
+rect 649 63 695 75
+rect 649 -63 655 63
+rect 689 -63 695 63
+rect 649 -75 695 -63
+rect 745 63 791 75
+rect 745 -63 751 63
+rect 785 -63 791 63
+rect 745 -75 791 -63
+rect 841 63 887 75
+rect 841 -63 847 63
+rect 881 -63 887 63
+rect 841 -75 887 -63
+rect 937 63 983 75
+rect 937 -63 943 63
+rect 977 -63 983 63
+rect 937 -75 983 -63
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -1074 -232 1074 232
+string parameters w 0.75 l 0.150 m 1 nf 20 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_T69Y3A.mag b/mag/sky130_fd_pr__nfet_01v8_T69Y3A.mag
new file mode 100644
index 0000000..2ceaa77
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_T69Y3A.mag
@@ -0,0 +1,95 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -257 -327 257 327
+<< nmos >>
+rect -159 -300 -129 300
+rect -63 -300 -33 300
+rect 33 -300 63 300
+rect 129 -300 159 300
+<< ndiff >>
+rect -221 288 -159 300
+rect -221 -288 -209 288
+rect -175 -288 -159 288
+rect -221 -300 -159 -288
+rect -129 288 -63 300
+rect -129 -288 -113 288
+rect -79 -288 -63 288
+rect -129 -300 -63 -288
+rect -33 288 33 300
+rect -33 -288 -17 288
+rect 17 -288 33 288
+rect -33 -300 33 -288
+rect 63 288 129 300
+rect 63 -288 79 288
+rect 113 -288 129 288
+rect 63 -300 129 -288
+rect 159 288 221 300
+rect 159 -288 175 288
+rect 209 -288 221 288
+rect 159 -300 221 -288
+<< ndiffc >>
+rect -209 -288 -175 288
+rect -113 -288 -79 288
+rect -17 -288 17 288
+rect 79 -288 113 288
+rect 175 -288 209 288
+<< poly >>
+rect -257 326 257 499
+rect -159 300 -129 326
+rect -63 300 -33 326
+rect 33 300 63 326
+rect 129 300 159 326
+rect -159 -322 -129 -300
+rect -63 -322 -33 -300
+rect 33 -322 63 -300
+rect 129 -322 159 -300
+rect -257 -404 257 -322
+<< locali >>
+rect -209 288 -175 304
+rect -209 -304 -175 -288
+rect -113 288 -79 304
+rect -113 -304 -79 -288
+rect -17 288 17 304
+rect -17 -304 17 -288
+rect 79 288 113 304
+rect 79 -304 113 -288
+rect 175 288 209 304
+rect 175 -304 209 -288
+<< viali >>
+rect -209 -288 -175 288
+rect -113 -288 -79 288
+rect -17 -288 17 288
+rect 79 -288 113 288
+rect 175 -288 209 288
+<< metal1 >>
+rect -257 353 257 435
+rect -215 288 -169 300
+rect -215 -288 -209 288
+rect -175 -288 -169 288
+rect -215 -343 -169 -288
+rect -119 288 -73 353
+rect -119 -288 -113 288
+rect -79 -288 -73 288
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+rect -23 288 23 300
+rect -23 -288 -17 288
+rect 17 -288 23 288
+rect -23 -343 23 -288
+rect 73 288 119 353
+rect 73 -288 79 288
+rect 113 -288 119 288
+rect 73 -300 119 -288
+rect 169 288 215 300
+rect 169 -288 175 288
+rect 209 -288 215 288
+rect 169 -343 215 -288
+rect -257 -425 257 -343
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -306 -457 306 457
+string parameters w 3 l 0.150 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_U2JGXT.mag b/mag/sky130_fd_pr__nfet_01v8_U2JGXT.mag
new file mode 100644
index 0000000..e00665a
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_U2JGXT.mag
@@ -0,0 +1,81 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624053471
+<< pwell >>
+rect -226 -510 226 510
+<< nmos >>
+rect -30 -300 30 300
+<< ndiff >>
+rect -88 288 -30 300
+rect -88 -288 -76 288
+rect -42 -288 -30 288
+rect -88 -300 -30 -288
+rect 30 288 88 300
+rect 30 -288 42 288
+rect 76 -288 88 288
+rect 30 -300 88 -288
+<< ndiffc >>
+rect -76 -288 -42 288
+rect 42 -288 76 288
+<< psubdiff >>
+rect -190 440 -94 474
+rect 94 440 190 474
+rect -190 378 -156 440
+rect 156 378 190 440
+rect -190 -440 -156 -378
+rect 156 -440 190 -378
+rect -190 -474 -94 -440
+rect 94 -474 190 -440
+<< psubdiffcont >>
+rect -94 440 94 474
+rect -190 -378 -156 378
+rect 156 -378 190 378
+rect -94 -474 94 -440
+<< poly >>
+rect -30 300 30 326
+rect -30 -322 30 -300
+rect -118 -338 30 -322
+rect -118 -372 -92 -338
+rect 11 -372 30 -338
+rect -118 -388 30 -372
+<< polycont >>
+rect -92 -372 11 -338
+<< locali >>
+rect -190 440 -94 474
+rect 94 440 190 474
+rect -190 378 -156 440
+rect 156 378 190 440
+rect -76 288 -42 304
+rect -76 -304 -42 -288
+rect 42 288 76 304
+rect 42 -304 76 -288
+rect -108 -372 -92 -338
+rect 11 -372 30 -338
+rect -190 -440 -156 -378
+rect 156 -440 190 -378
+rect -190 -474 -94 -440
+rect 94 -474 190 -440
+<< viali >>
+rect -76 -288 -42 288
+rect 42 -288 76 288
+rect -92 -372 11 -338
+<< metal1 >>
+rect -82 288 -36 300
+rect -82 -288 -76 288
+rect -42 -288 -36 288
+rect -82 -300 -36 -288
+rect 36 288 82 300
+rect 36 -288 42 288
+rect 76 -288 82 288
+rect 36 -300 82 -288
+rect -117 -338 29 -328
+rect -117 -372 -92 -338
+rect 11 -372 29 -338
+rect -117 -385 29 -372
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -173 -457 173 457
+string parameters w 3 l 0.3 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_YCGG98.mag b/mag/sky130_fd_pr__nfet_01v8_YCGG98.mag
new file mode 100644
index 0000000..dd05d65
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_YCGG98.mag
@@ -0,0 +1,419 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -1367 -285 1367 285
+<< nmos >>
+rect -1167 -75 -1137 75
+rect -1071 -75 -1041 75
+rect -975 -75 -945 75
+rect -879 -75 -849 75
+rect -783 -75 -753 75
+rect -687 -75 -657 75
+rect -591 -75 -561 75
+rect -495 -75 -465 75
+rect -399 -75 -369 75
+rect -303 -75 -273 75
+rect -207 -75 -177 75
+rect -111 -75 -81 75
+rect -15 -75 15 75
+rect 81 -75 111 75
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+rect 369 -75 399 75
+rect 465 -75 495 75
+rect 561 -75 591 75
+rect 657 -75 687 75
+rect 753 -75 783 75
+rect 849 -75 879 75
+rect 945 -75 975 75
+rect 1041 -75 1071 75
+rect 1137 -75 1167 75
+<< ndiff >>
+rect -1229 63 -1167 75
+rect -1229 -63 -1217 63
+rect -1183 -63 -1167 63
+rect -1229 -75 -1167 -63
+rect -1137 63 -1071 75
+rect -1137 -63 -1121 63
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+rect -1041 63 -975 75
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+rect -945 63 -879 75
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+rect -895 -63 -879 63
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+rect -849 63 -783 75
+rect -849 -63 -833 63
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+rect -81 63 -15 75
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+rect -31 -63 -15 63
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+rect 15 -75 81 -63
+rect 111 63 177 75
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+rect 207 63 273 75
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+rect 303 -63 319 63
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+rect 399 63 465 75
+rect 399 -63 415 63
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+rect 591 63 657 75
+rect 591 -63 607 63
+rect 641 -63 657 63
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+rect 687 63 753 75
+rect 687 -63 703 63
+rect 737 -63 753 63
+rect 687 -75 753 -63
+rect 783 63 849 75
+rect 783 -63 799 63
+rect 833 -63 849 63
+rect 783 -75 849 -63
+rect 879 63 945 75
+rect 879 -63 895 63
+rect 929 -63 945 63
+rect 879 -75 945 -63
+rect 975 63 1041 75
+rect 975 -63 991 63
+rect 1025 -63 1041 63
+rect 975 -75 1041 -63
+rect 1071 63 1137 75
+rect 1071 -63 1087 63
+rect 1121 -63 1137 63
+rect 1071 -75 1137 -63
+rect 1167 63 1229 75
+rect 1167 -63 1183 63
+rect 1217 -63 1229 63
+rect 1167 -75 1229 -63
+<< ndiffc >>
+rect -1217 -63 -1183 63
+rect -1121 -63 -1087 63
+rect -1025 -63 -991 63
+rect -929 -63 -895 63
+rect -833 -63 -799 63
+rect -737 -63 -703 63
+rect -641 -63 -607 63
+rect -545 -63 -511 63
+rect -449 -63 -415 63
+rect -353 -63 -319 63
+rect -257 -63 -223 63
+rect -161 -63 -127 63
+rect -65 -63 -31 63
+rect 31 -63 65 63
+rect 127 -63 161 63
+rect 223 -63 257 63
+rect 319 -63 353 63
+rect 415 -63 449 63
+rect 511 -63 545 63
+rect 607 -63 641 63
+rect 703 -63 737 63
+rect 799 -63 833 63
+rect 895 -63 929 63
+rect 991 -63 1025 63
+rect 1087 -63 1121 63
+rect 1183 -63 1217 63
+<< psubdiff >>
+rect 1297 153 1331 215
+rect 1297 -215 1331 -153
+rect -1297 -249 -1235 -215
+rect 1235 -249 1331 -215
+<< psubdiffcont >>
+rect 1297 -153 1331 153
+rect -1235 -249 1235 -215
+<< poly >>
+rect -1167 101 1167 167
+rect -1167 75 -1137 101
+rect -1071 75 -1041 101
+rect -975 75 -945 101
+rect -879 75 -849 101
+rect -783 75 -753 101
+rect -687 75 -657 101
+rect -591 75 -561 101
+rect -495 75 -465 101
+rect -399 75 -369 101
+rect -303 75 -273 101
+rect -207 75 -177 101
+rect -111 75 -81 101
+rect -15 75 15 101
+rect 81 75 111 101
+rect 177 75 207 101
+rect 273 75 303 101
+rect 369 75 399 101
+rect 465 75 495 101
+rect 561 75 591 101
+rect 657 75 687 101
+rect 753 75 783 101
+rect 849 75 879 101
+rect 945 75 975 101
+rect 1041 75 1071 101
+rect 1137 75 1167 101
+rect -1167 -101 -1137 -75
+rect -1071 -101 -1041 -75
+rect -975 -101 -945 -75
+rect -879 -101 -849 -75
+rect -783 -101 -753 -75
+rect -687 -101 -657 -75
+rect -591 -101 -561 -75
+rect -495 -101 -465 -75
+rect -399 -101 -369 -75
+rect -303 -101 -273 -75
+rect -207 -101 -177 -75
+rect -111 -101 -81 -75
+rect -15 -101 15 -75
+rect 81 -101 111 -75
+rect 177 -101 207 -75
+rect 273 -101 303 -75
+rect 369 -101 399 -75
+rect 465 -101 495 -75
+rect 561 -101 591 -75
+rect 657 -101 687 -75
+rect 753 -101 783 -75
+rect 849 -101 879 -75
+rect 945 -101 975 -75
+rect 1041 -101 1071 -75
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+rect -833 -63 -799 63
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+rect 601 -63 607 63
+rect 641 -63 647 63
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+rect 697 63 743 75
+rect 697 -63 703 63
+rect 737 -63 743 63
+rect 697 -75 743 -63
+rect 793 63 839 75
+rect 793 -63 799 63
+rect 833 -63 839 63
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+rect 889 -63 895 63
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+rect 1081 63 1127 75
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+rect 1121 -63 1127 63
+rect 1081 -75 1127 -63
+rect 1177 63 1223 75
+rect 1177 -63 1183 63
+rect 1217 -63 1223 63
+rect 1177 -75 1223 -63
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -1314 -232 1314 232
+string parameters w 0.75 l 0.150 m 1 nf 25 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_ZCYAJJ.mag b/mag/sky130_fd_pr__nfet_01v8_ZCYAJJ.mag
new file mode 100644
index 0000000..0a75018
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_ZCYAJJ.mag
@@ -0,0 +1,105 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -359 -255 359 255
+<< nmos >>
+rect -159 -45 -129 45
+rect -63 -45 -33 45
+rect 33 -45 63 45
+rect 129 -45 159 45
+<< ndiff >>
+rect -221 33 -159 45
+rect -221 -33 -209 33
+rect -175 -33 -159 33
+rect -221 -45 -159 -33
+rect -129 33 -63 45
+rect -129 -33 -113 33
+rect -79 -33 -63 33
+rect -129 -45 -63 -33
+rect -33 33 33 45
+rect -33 -33 -17 33
+rect 17 -33 33 33
+rect -33 -45 33 -33
+rect 63 33 129 45
+rect 63 -33 79 33
+rect 113 -33 129 33
+rect 63 -45 129 -33
+rect 159 33 221 45
+rect 159 -33 175 33
+rect 209 -33 221 33
+rect 159 -45 221 -33
+<< ndiffc >>
+rect -209 -33 -175 33
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+rect 175 -33 209 33
+<< psubdiff >>
+rect -323 123 -289 185
+rect -323 -185 -289 -123
+rect -323 -219 -227 -185
+rect 227 -219 289 -185
+<< psubdiffcont >>
+rect -323 -123 -289 123
+rect -227 -219 227 -185
+<< poly >>
+rect -63 113 159 173
+rect -159 45 -129 71
+rect -63 45 -33 113
+rect 33 45 63 71
+rect 129 45 159 113
+rect -159 -113 -129 -45
+rect -63 -71 -33 -45
+rect 33 -113 63 -45
+rect 129 -71 159 -45
+rect -159 -173 63 -113
+<< locali >>
+rect -323 123 -289 185
+rect -209 33 -175 49
+rect -209 -49 -175 -33
+rect -113 33 -79 49
+rect -113 -49 -79 -33
+rect -17 33 17 49
+rect -17 -49 17 -33
+rect 79 33 113 49
+rect 79 -49 113 -33
+rect 175 33 209 49
+rect 175 -49 209 -33
+rect -323 -185 -289 -123
+rect -323 -219 -227 -185
+rect 227 -219 289 -185
+<< viali >>
+rect -209 -33 -175 33
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+rect 175 -33 209 33
+<< metal1 >>
+rect -215 33 -169 45
+rect -215 -33 -209 33
+rect -175 -33 -169 33
+rect -215 -45 -169 -33
+rect -119 33 -73 45
+rect -119 -33 -113 33
+rect -79 -33 -73 33
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+rect -23 33 23 45
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+rect 17 -33 23 33
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+rect 73 33 119 45
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+rect 113 -33 119 33
+rect 73 -45 119 -33
+rect 169 33 215 45
+rect 169 -33 175 33
+rect 209 -33 215 33
+rect 169 -45 215 -33
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -306 -202 306 202
+string parameters w 0.45 l 0.150 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_ZXAV3F.mag b/mag/sky130_fd_pr__nfet_01v8_ZXAV3F.mag
new file mode 100644
index 0000000..5afa5ef
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_ZXAV3F.mag
@@ -0,0 +1,59 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -211 -255 211 255
+<< nmos >>
+rect -15 -45 15 45
+<< ndiff >>
+rect -73 33 -15 45
+rect -73 -33 -61 33
+rect -27 -33 -15 33
+rect -73 -45 -15 -33
+rect 15 33 73 45
+rect 15 -33 27 33
+rect 61 -33 73 33
+rect 15 -45 73 -33
+<< ndiffc >>
+rect -61 -33 -27 33
+rect 27 -33 61 33
+<< psubdiff >>
+rect 141 123 175 185
+rect 141 -185 175 -123
+rect -141 -219 -79 -185
+rect 79 -219 175 -185
+<< psubdiffcont >>
+rect 141 -123 175 123
+rect -79 -219 79 -185
+<< poly >>
+rect -33 67 15 133
+rect -15 45 15 67
+rect -15 -71 15 -45
+<< locali >>
+rect 141 123 175 185
+rect -61 33 -27 49
+rect -61 -49 -27 -33
+rect 27 33 61 49
+rect 27 -49 61 -33
+rect 141 -185 175 -123
+rect -141 -219 -79 -185
+rect 79 -219 175 -185
+<< viali >>
+rect -61 -33 -27 33
+rect 27 -33 61 33
+<< metal1 >>
+rect -67 33 -21 45
+rect -67 -33 -61 33
+rect -27 -33 -21 33
+rect -67 -45 -21 -33
+rect 21 33 67 45
+rect 21 -33 27 33
+rect 61 -33 67 33
+rect 21 -45 67 -33
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -202 158 202
+string parameters w 0.45 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_4757AC.mag b/mag/sky130_fd_pr__pfet_01v8_4757AC.mag
new file mode 100644
index 0000000..cb97d14
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_4757AC.mag
@@ -0,0 +1,82 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< error_p >>
+rect -29 231 29 237
+rect -29 197 -17 231
+rect -29 191 29 197
+<< nwell >>
+rect -211 -369 211 369
+<< pmos >>
+rect -15 -150 15 150
+<< pdiff >>
+rect -73 138 -15 150
+rect -73 -138 -61 138
+rect -27 -138 -15 138
+rect -73 -150 -15 -138
+rect 15 138 73 150
+rect 15 -138 27 138
+rect 61 -138 73 138
+rect 15 -150 73 -138
+<< pdiffc >>
+rect -61 -138 -27 138
+rect 27 -138 61 138
+<< nsubdiff >>
+rect -175 299 -79 333
+rect 79 299 175 333
+rect -175 237 -141 299
+rect 141 237 175 299
+rect -175 -299 -141 -237
+rect 141 -299 175 -237
+rect -175 -333 175 -299
+<< nsubdiffcont >>
+rect -79 299 79 333
+rect -175 -237 -141 237
+rect 141 -237 175 237
+<< poly >>
+rect -33 231 33 247
+rect -33 197 -17 231
+rect 17 197 33 231
+rect -33 181 33 197
+rect -15 150 15 181
+rect -15 -181 15 -150
+<< polycont >>
+rect -17 197 17 231
+<< locali >>
+rect -175 299 -79 333
+rect 79 299 175 333
+rect -175 237 -141 299
+rect 141 237 175 299
+rect -33 197 -17 231
+rect 17 197 33 231
+rect -61 138 -27 154
+rect -61 -154 -27 -138
+rect 27 138 61 154
+rect 27 -154 61 -138
+rect -175 -299 -141 -237
+rect 141 -299 175 -237
+rect -175 -333 175 -299
+<< viali >>
+rect -17 197 17 231
+rect -61 -138 -27 138
+rect 27 -138 61 138
+<< metal1 >>
+rect -29 231 29 237
+rect -29 197 -17 231
+rect 17 197 29 231
+rect -29 191 29 197
+rect -67 138 -21 150
+rect -67 -138 -61 138
+rect -27 -138 -21 138
+rect -67 -150 -21 -138
+rect 21 138 67 150
+rect 21 -138 27 138
+rect 61 -138 67 138
+rect 21 -150 67 -138
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -316 158 316
+string parameters w 1.5 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_4798MH.mag b/mag/sky130_fd_pr__pfet_01v8_4798MH.mag
new file mode 100644
index 0000000..a113890
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_4798MH.mag
@@ -0,0 +1,93 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -311 -344 311 344
+<< pmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< pdiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< pdiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< nsubdiff >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< nsubdiffcont >>
+rect -179 274 179 308
+rect -275 -212 -241 212
+rect 241 -212 275 212
+<< poly >>
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -156 -81 -125
+rect -15 -156 15 -125
+rect 81 -156 111 -125
+<< locali >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -258 -291 258 291
+string parameters w 1.25 l 0.15 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_4F35BC.mag b/mag/sky130_fd_pr__pfet_01v8_4F35BC.mag
new file mode 100644
index 0000000..8cbc8a7
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_4F35BC.mag
@@ -0,0 +1,111 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -359 -309 359 309
+<< pmos >>
+rect -159 -90 -129 90
+rect -63 -90 -33 90
+rect 33 -90 63 90
+rect 129 -90 159 90
+<< pdiff >>
+rect -221 78 -159 90
+rect -221 -78 -209 78
+rect -175 -78 -159 78
+rect -221 -90 -159 -78
+rect -129 78 -63 90
+rect -129 -78 -113 78
+rect -79 -78 -63 78
+rect -129 -90 -63 -78
+rect -33 78 33 90
+rect -33 -78 -17 78
+rect 17 -78 33 78
+rect -33 -90 33 -78
+rect 63 78 129 90
+rect 63 -78 79 78
+rect 113 -78 129 78
+rect 63 -90 129 -78
+rect 159 78 221 90
+rect 159 -78 175 78
+rect 209 -78 221 78
+rect 159 -90 221 -78
+<< pdiffc >>
+rect -209 -78 -175 78
+rect -113 -78 -79 78
+rect -17 -78 17 78
+rect 79 -78 113 78
+rect 175 -78 209 78
+<< nsubdiff >>
+rect -323 239 -227 273
+rect 227 239 323 273
+rect -323 177 -289 239
+rect 289 177 323 239
+rect -323 -239 -289 -177
+rect 289 -239 323 -177
+<< nsubdiffcont >>
+rect -227 239 227 273
+rect -323 -177 -289 177
+rect 289 -177 323 177
+<< poly >>
+rect -63 159 159 208
+rect -159 90 -129 116
+rect -63 90 -33 159
+rect 33 90 63 116
+rect 129 90 159 159
+rect -159 -158 -129 -90
+rect -63 -116 -33 -90
+rect 33 -158 63 -90
+rect -159 -207 63 -158
+rect 129 -116 159 -90
+rect 129 -182 195 -116
+<< locali >>
+rect -323 239 -227 273
+rect 227 239 323 273
+rect -323 177 -289 239
+rect 289 177 323 239
+rect -209 78 -175 94
+rect -209 -94 -175 -78
+rect -113 78 -79 94
+rect -113 -94 -79 -78
+rect -17 78 17 94
+rect -17 -94 17 -78
+rect 79 78 113 94
+rect 79 -94 113 -78
+rect 175 78 209 94
+rect 175 -94 209 -78
+rect -323 -239 -289 -177
+rect 289 -239 323 -177
+<< viali >>
+rect -209 -78 -175 78
+rect -113 -78 -79 78
+rect -17 -78 17 78
+rect 79 -78 113 78
+rect 175 -78 209 78
+<< metal1 >>
+rect -215 78 -169 90
+rect -215 -78 -209 78
+rect -175 -78 -169 78
+rect -215 -90 -169 -78
+rect -119 78 -73 90
+rect -119 -78 -113 78
+rect -79 -78 -73 78
+rect -119 -90 -73 -78
+rect -23 78 23 90
+rect -23 -78 -17 78
+rect 17 -78 23 78
+rect -23 -90 23 -78
+rect 73 78 119 90
+rect 73 -78 79 78
+rect 113 -78 119 78
+rect 73 -90 119 -78
+rect 169 78 215 90
+rect 169 -78 175 78
+rect 209 -78 215 78
+rect 169 -90 215 -78
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -306 -256 306 256
+string parameters w 0.9 l 0.15 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_4F7GBC.mag b/mag/sky130_fd_pr__pfet_01v8_4F7GBC.mag
new file mode 100644
index 0000000..6950fec
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_4F7GBC.mag
@@ -0,0 +1,59 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -211 -309 211 309
+<< pmos >>
+rect -15 -90 15 90
+<< pdiff >>
+rect -73 78 -15 90
+rect -73 -78 -61 78
+rect -27 -78 -15 78
+rect -73 -90 -15 -78
+rect 15 78 73 90
+rect 15 -78 27 78
+rect 61 -78 73 78
+rect 15 -90 73 -78
+<< pdiffc >>
+rect -61 -78 -27 78
+rect 27 -78 61 78
+<< nsubdiff >>
+rect -141 239 -79 273
+rect 79 239 175 273
+rect 141 177 175 239
+rect 141 -239 175 -177
+<< nsubdiffcont >>
+rect -79 239 79 273
+rect 141 -177 175 177
+<< poly >>
+rect -15 90 15 121
+rect -15 -121 15 -90
+rect -51 -187 15 -121
+<< locali >>
+rect -141 239 -79 273
+rect 79 239 175 273
+rect 141 177 175 239
+rect -61 78 -27 94
+rect -61 -94 -27 -78
+rect 27 78 61 94
+rect 27 -94 61 -78
+rect 141 -239 175 -177
+<< viali >>
+rect -61 -78 -27 78
+rect 27 -78 61 78
+<< metal1 >>
+rect -67 78 -21 90
+rect -67 -78 -61 78
+rect -27 -78 -21 78
+rect -67 -90 -21 -78
+rect 21 78 67 90
+rect 21 -78 27 78
+rect 61 -78 67 78
+rect 21 -90 67 -78
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -256 158 256
+string parameters w 0.9 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_4ML9WA.mag b/mag/sky130_fd_pr__pfet_01v8_4ML9WA.mag
new file mode 100644
index 0000000..9b837bc
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_4ML9WA.mag
@@ -0,0 +1,189 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -2457 -634 2457 634
+<< pmos >>
+rect -2261 -486 -1861 414
+rect -1803 -486 -1403 414
+rect -1345 -486 -945 414
+rect -887 -486 -487 414
+rect -429 -486 -29 414
+rect 29 -486 429 414
+rect 487 -486 887 414
+rect 945 -486 1345 414
+rect 1403 -486 1803 414
+rect 1861 -486 2261 414
+<< pdiff >>
+rect -2319 402 -2261 414
+rect -2319 -474 -2307 402
+rect -2273 -474 -2261 402
+rect -2319 -486 -2261 -474
+rect -1861 402 -1803 414
+rect -1861 -474 -1849 402
+rect -1815 -474 -1803 402
+rect -1861 -486 -1803 -474
+rect -1403 402 -1345 414
+rect -1403 -474 -1391 402
+rect -1357 -474 -1345 402
+rect -1403 -486 -1345 -474
+rect -945 402 -887 414
+rect -945 -474 -933 402
+rect -899 -474 -887 402
+rect -945 -486 -887 -474
+rect -487 402 -429 414
+rect -487 -474 -475 402
+rect -441 -474 -429 402
+rect -487 -486 -429 -474
+rect -29 402 29 414
+rect -29 -474 -17 402
+rect 17 -474 29 402
+rect -29 -486 29 -474
+rect 429 402 487 414
+rect 429 -474 441 402
+rect 475 -474 487 402
+rect 429 -486 487 -474
+rect 887 402 945 414
+rect 887 -474 899 402
+rect 933 -474 945 402
+rect 887 -486 945 -474
+rect 1345 402 1403 414
+rect 1345 -474 1357 402
+rect 1391 -474 1403 402
+rect 1345 -486 1403 -474
+rect 1803 402 1861 414
+rect 1803 -474 1815 402
+rect 1849 -474 1861 402
+rect 1803 -486 1861 -474
+rect 2261 402 2319 414
+rect 2261 -474 2273 402
+rect 2307 -474 2319 402
+rect 2261 -486 2319 -474
+<< pdiffc >>
+rect -2307 -474 -2273 402
+rect -1849 -474 -1815 402
+rect -1391 -474 -1357 402
+rect -933 -474 -899 402
+rect -475 -474 -441 402
+rect -17 -474 17 402
+rect 441 -474 475 402
+rect 899 -474 933 402
+rect 1357 -474 1391 402
+rect 1815 -474 1849 402
+rect 2273 -474 2307 402
+<< nsubdiff >>
+rect -2387 -598 -2325 -564
+rect 2325 -598 2387 -564
+<< nsubdiffcont >>
+rect -2325 -598 2325 -564
+<< poly >>
+rect -2261 455 2261 511
+rect -2261 414 -1861 455
+rect -1803 414 -1403 455
+rect -1345 414 -945 455
+rect -887 414 -487 455
+rect -429 414 -29 455
+rect 29 414 429 455
+rect 487 414 887 455
+rect 945 414 1345 455
+rect 1403 414 1803 455
+rect 1861 414 2261 455
+rect -2261 -512 -1861 -486
+rect -1803 -512 -1403 -486
+rect -1345 -512 -945 -486
+rect -887 -512 -487 -486
+rect -429 -512 -29 -486
+rect 29 -512 429 -486
+rect 487 -512 887 -486
+rect 945 -512 1345 -486
+rect 1403 -512 1803 -486
+rect 1861 -512 2261 -486
+<< locali >>
+rect -2307 402 -2273 418
+rect -2307 -490 -2273 -474
+rect -1849 402 -1815 418
+rect -1849 -490 -1815 -474
+rect -1391 402 -1357 418
+rect -1391 -490 -1357 -474
+rect -933 402 -899 418
+rect -933 -490 -899 -474
+rect -475 402 -441 418
+rect -475 -490 -441 -474
+rect -17 402 17 418
+rect -17 -490 17 -474
+rect 441 402 475 418
+rect 441 -490 475 -474
+rect 899 402 933 418
+rect 899 -490 933 -474
+rect 1357 402 1391 418
+rect 1357 -490 1391 -474
+rect 1815 402 1849 418
+rect 1815 -490 1849 -474
+rect 2273 402 2307 418
+rect 2273 -490 2307 -474
+rect -2387 -598 -2325 -564
+rect 2325 -598 2387 -564
+<< viali >>
+rect -2307 -474 -2273 402
+rect -1849 -474 -1815 402
+rect -1391 -474 -1357 402
+rect -933 -474 -899 402
+rect -475 -474 -441 402
+rect -17 -474 17 402
+rect 441 -474 475 402
+rect 899 -474 933 402
+rect 1357 -474 1391 402
+rect 1815 -474 1849 402
+rect 2273 -474 2307 402
+<< metal1 >>
+rect -2313 402 -2267 414
+rect -2313 -474 -2307 402
+rect -2273 -474 -2267 402
+rect -2313 -486 -2267 -474
+rect -1855 402 -1809 414
+rect -1855 -474 -1849 402
+rect -1815 -474 -1809 402
+rect -1855 -486 -1809 -474
+rect -1397 402 -1351 414
+rect -1397 -474 -1391 402
+rect -1357 -474 -1351 402
+rect -1397 -486 -1351 -474
+rect -939 402 -893 414
+rect -939 -474 -933 402
+rect -899 -474 -893 402
+rect -939 -486 -893 -474
+rect -481 402 -435 414
+rect -481 -474 -475 402
+rect -441 -474 -435 402
+rect -481 -486 -435 -474
+rect -23 402 23 414
+rect -23 -474 -17 402
+rect 17 -474 23 402
+rect -23 -486 23 -474
+rect 435 402 481 414
+rect 435 -474 441 402
+rect 475 -474 481 402
+rect 435 -486 481 -474
+rect 893 402 939 414
+rect 893 -474 899 402
+rect 933 -474 939 402
+rect 893 -486 939 -474
+rect 1351 402 1397 414
+rect 1351 -474 1357 402
+rect 1391 -474 1397 402
+rect 1351 -486 1397 -474
+rect 1809 402 1855 414
+rect 1809 -474 1815 402
+rect 1849 -474 1855 402
+rect 1809 -486 1855 -474
+rect 2267 402 2313 414
+rect 2267 -474 2273 402
+rect 2307 -474 2313 402
+rect 2267 -486 2313 -474
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -2404 -581 2404 581
+string parameters w 4.5 l 2 m 1 nf 10 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_58ZKDE.mag b/mag/sky130_fd_pr__pfet_01v8_58ZKDE.mag
new file mode 100644
index 0000000..02744ae
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_58ZKDE.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -257 -702 257 701
+<< pmos >>
+rect -159 -600 -129 600
+rect -63 -600 -33 600
+rect 33 -600 63 600
+rect 129 -600 159 600
+<< pdiff >>
+rect -221 588 -159 600
+rect -221 -588 -209 588
+rect -175 -588 -159 588
+rect -221 -600 -159 -588
+rect -129 588 -63 600
+rect -129 -588 -113 588
+rect -79 -588 -63 588
+rect -129 -600 -63 -588
+rect -33 588 33 600
+rect -33 -588 -17 588
+rect 17 -588 33 588
+rect -33 -600 33 -588
+rect 63 588 129 600
+rect 63 -588 79 588
+rect 113 -588 129 588
+rect 63 -600 129 -588
+rect 159 588 221 600
+rect 159 -588 175 588
+rect 209 -588 221 588
+rect 159 -600 221 -588
+<< pdiffc >>
+rect -209 -588 -175 588
+rect -113 -588 -79 588
+rect -17 -588 17 588
+rect 79 -588 113 588
+rect 175 -588 209 588
+<< poly >>
+rect -257 624 257 695
+rect -159 600 -129 624
+rect -63 600 -33 624
+rect 33 600 63 624
+rect 129 600 159 624
+rect -159 -621 -129 -600
+rect -63 -621 -33 -600
+rect 33 -621 63 -600
+rect 129 -621 159 -600
+rect -257 -777 257 -621
+<< locali >>
+rect -209 588 -175 604
+rect -209 -604 -175 -588
+rect -113 588 -79 604
+rect -113 -604 -79 -588
+rect -17 588 17 604
+rect -17 -604 17 -588
+rect 79 588 113 604
+rect 79 -604 113 -588
+rect 175 588 209 604
+rect 175 -604 209 -588
+<< viali >>
+rect -209 -588 -175 588
+rect -113 -588 -79 588
+rect -17 -588 17 588
+rect 79 -588 113 588
+rect 175 -588 209 588
+<< metal1 >>
+rect -257 685 257 744
+rect -215 588 -169 685
+rect -215 -588 -209 588
+rect -175 -588 -169 588
+rect -215 -600 -169 -588
+rect -119 588 -73 600
+rect -119 -588 -113 588
+rect -79 -588 -73 588
+rect -119 -636 -73 -588
+rect -23 588 23 685
+rect -23 -588 -17 588
+rect 17 -588 23 588
+rect -23 -600 23 -588
+rect 73 588 119 600
+rect 73 -588 79 588
+rect 113 -588 119 588
+rect 73 -636 119 -588
+rect 169 588 215 685
+rect 169 -588 175 588
+rect 209 -588 215 588
+rect 169 -600 215 -588
+rect -257 -723 257 -636
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string parameters w 6 l 0.15 m 1 nf 4 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_6KD4CR.mag b/mag/sky130_fd_pr__pfet_01v8_6KD4CR.mag
new file mode 100644
index 0000000..79465e7
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_6KD4CR.mag
@@ -0,0 +1,68 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623449341
+<< nwell >>
+rect -263 -264 263 264
+<< pmos >>
+rect -63 -45 -33 45
+rect 33 -45 63 45
+<< pdiff >>
+rect -125 33 -63 45
+rect -125 -33 -113 33
+rect -79 -33 -63 33
+rect -125 -45 -63 -33
+rect -33 33 33 45
+rect -33 -33 -17 33
+rect 17 -33 33 33
+rect -33 -45 33 -33
+rect 63 33 125 45
+rect 63 -33 79 33
+rect 113 -33 125 33
+rect 63 -45 125 -33
+<< pdiffc >>
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+<< nsubdiff >>
+rect -193 194 -131 228
+rect 131 194 193 228
+<< nsubdiffcont >>
+rect -131 194 131 228
+<< poly >>
+rect -63 45 -33 71
+rect 33 45 63 71
+rect -63 -105 -33 -45
+rect 33 -105 63 -45
+<< locali >>
+rect -193 194 -131 228
+rect 131 194 193 228
+rect -113 33 -79 49
+rect -113 -49 -79 -33
+rect -17 33 17 49
+rect -17 -49 17 -33
+rect 79 33 113 49
+rect 79 -49 113 -33
+<< viali >>
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+<< metal1 >>
+rect -119 33 -73 45
+rect -119 -33 -113 33
+rect -79 -33 -73 33
+rect -119 -45 -73 -33
+rect -23 33 23 45
+rect -23 -33 -17 33
+rect 17 -33 23 33
+rect -23 -45 23 -33
+rect 73 33 119 45
+rect 73 -33 79 33
+rect 113 -33 119 33
+rect 73 -45 119 -33
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -211 210 211
+string parameters w 0.45 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_7779BR.mag b/mag/sky130_fd_pr__pfet_01v8_7779BR.mag
new file mode 100644
index 0000000..20b419a
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_7779BR.mag
@@ -0,0 +1,59 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623449341
+<< nwell >>
+rect -211 -264 211 264
+<< pmos >>
+rect -15 -45 15 45
+<< pdiff >>
+rect -73 33 -15 45
+rect -73 -33 -61 33
+rect -27 -33 -15 33
+rect -73 -45 -15 -33
+rect 15 33 73 45
+rect 15 -33 27 33
+rect 61 -33 73 33
+rect 15 -45 73 -33
+<< pdiffc >>
+rect -61 -33 -27 33
+rect 27 -33 61 33
+<< nsubdiff >>
+rect -141 194 -79 228
+rect 79 194 175 228
+rect 141 132 175 194
+rect 141 -194 175 -132
+<< nsubdiffcont >>
+rect -79 194 79 228
+rect 141 -132 175 132
+<< poly >>
+rect -15 45 15 81
+rect -15 -76 15 -45
+rect -33 -142 15 -76
+<< locali >>
+rect -141 194 -79 228
+rect 79 194 175 228
+rect 141 132 175 194
+rect -61 33 -27 49
+rect -61 -49 -27 -33
+rect 27 33 61 49
+rect 27 -49 61 -33
+rect 141 -194 175 -132
+<< viali >>
+rect -61 -33 -27 33
+rect 27 -33 61 33
+<< metal1 >>
+rect -67 33 -21 45
+rect -67 -33 -61 33
+rect -27 -33 -21 33
+rect -67 -45 -21 -33
+rect 21 33 67 45
+rect 21 -33 27 33
+rect 61 -33 67 33
+rect 21 -45 67 -33
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -211 158 211
+string parameters w 0.45 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_7KT7MH.mag b/mag/sky130_fd_pr__pfet_01v8_7KT7MH.mag
new file mode 100644
index 0000000..ac1b6ef
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_7KT7MH.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -311 -344 311 344
+<< pmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< pdiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< pdiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< nsubdiff >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< nsubdiffcont >>
+rect -179 274 179 308
+rect -275 -212 -241 212
+rect 241 -212 275 212
+<< poly >>
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -156 -81 -125
+rect -15 -156 15 -125
+rect 81 -156 111 -125
+rect -111 -186 111 -156
+<< locali >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -258 -291 258 291
+string parameters w 1.25 l 0.15 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_7T83YG.mag b/mag/sky130_fd_pr__pfet_01v8_7T83YG.mag
new file mode 100644
index 0000000..363e9b4
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_7T83YG.mag
@@ -0,0 +1,70 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -263 -309 263 309
+<< pmos >>
+rect -63 -90 -33 90
+rect 33 -90 63 90
+<< pdiff >>
+rect -125 78 -63 90
+rect -125 -78 -113 78
+rect -79 -78 -63 78
+rect -125 -90 -63 -78
+rect -33 78 33 90
+rect -33 -78 -17 78
+rect 17 -78 33 78
+rect -33 -90 33 -78
+rect 63 78 125 90
+rect 63 -78 79 78
+rect 113 -78 125 78
+rect 63 -90 125 -78
+<< pdiffc >>
+rect -113 -78 -79 78
+rect -17 -78 17 78
+rect 79 -78 113 78
+<< nsubdiff >>
+rect -193 239 -131 273
+rect 131 239 193 273
+<< nsubdiffcont >>
+rect -131 239 131 273
+<< poly >>
+rect -63 90 -33 116
+rect 33 90 63 116
+rect -63 -121 -33 -90
+rect -99 -187 -33 -121
+rect 33 -121 63 -90
+rect 33 -187 99 -121
+<< locali >>
+rect -193 239 -131 273
+rect 131 239 193 273
+rect -113 78 -79 94
+rect -113 -94 -79 -78
+rect -17 78 17 94
+rect -17 -94 17 -78
+rect 79 78 113 94
+rect 79 -94 113 -78
+<< viali >>
+rect -113 -78 -79 78
+rect -17 -78 17 78
+rect 79 -78 113 78
+<< metal1 >>
+rect -119 78 -73 90
+rect -119 -78 -113 78
+rect -79 -78 -73 78
+rect -119 -90 -73 -78
+rect -23 78 23 90
+rect -23 -78 -17 78
+rect 17 -78 23 78
+rect -23 -90 23 -78
+rect 73 78 119 90
+rect 73 -78 79 78
+rect 113 -78 119 78
+rect 73 -90 119 -78
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -256 210 256
+string parameters w 0.9 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_8DL6ZL.mag b/mag/sky130_fd_pr__pfet_01v8_8DL6ZL.mag
new file mode 100644
index 0000000..a802291
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_8DL6ZL.mag
@@ -0,0 +1,261 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -647 -369 647 369
+<< pmos >>
+rect -447 -150 -417 150
+rect -351 -150 -321 150
+rect -255 -150 -225 150
+rect -159 -150 -129 150
+rect -63 -150 -33 150
+rect 33 -150 63 150
+rect 129 -150 159 150
+rect 225 -150 255 150
+rect 321 -150 351 150
+rect 417 -150 447 150
+<< pdiff >>
+rect -509 138 -447 150
+rect -509 -138 -497 138
+rect -463 -138 -447 138
+rect -509 -150 -447 -138
+rect -417 138 -351 150
+rect -417 -138 -401 138
+rect -367 -138 -351 138
+rect -417 -150 -351 -138
+rect -321 138 -255 150
+rect -321 -138 -305 138
+rect -271 -138 -255 138
+rect -321 -150 -255 -138
+rect -225 138 -159 150
+rect -225 -138 -209 138
+rect -175 -138 -159 138
+rect -225 -150 -159 -138
+rect -129 138 -63 150
+rect -129 -138 -113 138
+rect -79 -138 -63 138
+rect -129 -150 -63 -138
+rect -33 138 33 150
+rect -33 -138 -17 138
+rect 17 -138 33 138
+rect -33 -150 33 -138
+rect 63 138 129 150
+rect 63 -138 79 138
+rect 113 -138 129 138
+rect 63 -150 129 -138
+rect 159 138 225 150
+rect 159 -138 175 138
+rect 209 -138 225 138
+rect 159 -150 225 -138
+rect 255 138 321 150
+rect 255 -138 271 138
+rect 305 -138 321 138
+rect 255 -150 321 -138
+rect 351 138 417 150
+rect 351 -138 367 138
+rect 401 -138 417 138
+rect 351 -150 417 -138
+rect 447 138 509 150
+rect 447 -138 463 138
+rect 497 -138 509 138
+rect 447 -150 509 -138
+<< pdiffc >>
+rect -497 -138 -463 138
+rect -401 -138 -367 138
+rect -305 -138 -271 138
+rect -209 -138 -175 138
+rect -113 -138 -79 138
+rect -17 -138 17 138
+rect 79 -138 113 138
+rect 175 -138 209 138
+rect 271 -138 305 138
+rect 367 -138 401 138
+rect 463 -138 497 138
+<< nsubdiff >>
+rect -611 299 -515 333
+rect 515 299 611 333
+rect -611 237 -577 299
+rect 577 237 611 299
+rect -611 -299 -577 -237
+rect 577 -299 611 -237
+rect -611 -333 -515 -299
+rect 515 -333 611 -299
+<< nsubdiffcont >>
+rect -515 299 515 333
+rect -611 -237 -577 237
+rect 577 -237 611 237
+rect -515 -333 515 -299
+<< poly >>
+rect -447 150 -417 176
+rect -351 150 -321 176
+rect -255 150 -225 176
+rect -159 150 -129 176
+rect -63 150 -33 176
+rect 33 150 63 176
+rect 129 150 159 176
+rect 225 150 255 176
+rect 321 150 351 176
+rect 417 150 447 176
+rect -447 -181 -417 -150
+rect -351 -181 -321 -150
+rect -255 -181 -225 -150
+rect -159 -181 -129 -150
+rect -63 -181 -33 -150
+rect 33 -181 63 -150
+rect 129 -181 159 -150
+rect 225 -181 255 -150
+rect 321 -181 351 -150
+rect 417 -181 447 -150
+rect -465 -197 465 -181
+rect -465 -231 -449 -197
+rect -415 -231 -353 -197
+rect -319 -231 -257 -197
+rect -223 -231 -161 -197
+rect -127 -231 -65 -197
+rect -31 -231 31 -197
+rect 65 -231 127 -197
+rect 161 -231 223 -197
+rect 257 -231 319 -197
+rect 353 -231 415 -197
+rect 449 -231 465 -197
+rect -465 -247 465 -231
+<< polycont >>
+rect -449 -231 -415 -197
+rect -353 -231 -319 -197
+rect -257 -231 -223 -197
+rect -161 -231 -127 -197
+rect -65 -231 -31 -197
+rect 31 -231 65 -197
+rect 127 -231 161 -197
+rect 223 -231 257 -197
+rect 319 -231 353 -197
+rect 415 -231 449 -197
+<< locali >>
+rect -611 299 -515 333
+rect 515 299 611 333
+rect -611 237 -577 299
+rect 577 237 611 299
+rect -497 138 -463 154
+rect -497 -154 -463 -138
+rect -401 138 -367 154
+rect -401 -154 -367 -138
+rect -305 138 -271 154
+rect -305 -154 -271 -138
+rect -209 138 -175 154
+rect -209 -154 -175 -138
+rect -113 138 -79 154
+rect -113 -154 -79 -138
+rect -17 138 17 154
+rect -17 -154 17 -138
+rect 79 138 113 154
+rect 79 -154 113 -138
+rect 175 138 209 154
+rect 175 -154 209 -138
+rect 271 138 305 154
+rect 271 -154 305 -138
+rect 367 138 401 154
+rect 367 -154 401 -138
+rect 463 138 497 154
+rect 463 -154 497 -138
+rect -465 -231 -449 -197
+rect -415 -231 -353 -197
+rect -319 -231 -257 -197
+rect -223 -231 -161 -197
+rect -127 -231 -65 -197
+rect -31 -231 31 -197
+rect 65 -231 127 -197
+rect 161 -231 223 -197
+rect 257 -231 319 -197
+rect 353 -231 415 -197
+rect 449 -231 465 -197
+rect -611 -299 -577 -237
+rect 577 -299 611 -237
+rect -611 -333 -515 -299
+rect 515 -333 611 -299
+<< viali >>
+rect -497 -138 -463 138
+rect -401 -138 -367 138
+rect -305 -138 -271 138
+rect -209 -138 -175 138
+rect -113 -138 -79 138
+rect -17 -138 17 138
+rect 79 -138 113 138
+rect 175 -138 209 138
+rect 271 -138 305 138
+rect 367 -138 401 138
+rect 463 -138 497 138
+rect -449 -231 -415 -197
+rect -353 -231 -319 -197
+rect -257 -231 -223 -197
+rect -161 -231 -127 -197
+rect -65 -231 -31 -197
+rect 31 -231 65 -197
+rect 127 -231 161 -197
+rect 223 -231 257 -197
+rect 319 -231 353 -197
+rect 415 -231 449 -197
+<< metal1 >>
+rect -503 138 -457 150
+rect -503 -138 -497 138
+rect -463 -138 -457 138
+rect -503 -150 -457 -138
+rect -407 138 -361 150
+rect -407 -138 -401 138
+rect -367 -138 -361 138
+rect -407 -150 -361 -138
+rect -311 138 -265 150
+rect -311 -138 -305 138
+rect -271 -138 -265 138
+rect -311 -150 -265 -138
+rect -215 138 -169 150
+rect -215 -138 -209 138
+rect -175 -138 -169 138
+rect -215 -150 -169 -138
+rect -119 138 -73 150
+rect -119 -138 -113 138
+rect -79 -138 -73 138
+rect -119 -150 -73 -138
+rect -23 138 23 150
+rect -23 -138 -17 138
+rect 17 -138 23 138
+rect -23 -150 23 -138
+rect 73 138 119 150
+rect 73 -138 79 138
+rect 113 -138 119 138
+rect 73 -150 119 -138
+rect 169 138 215 150
+rect 169 -138 175 138
+rect 209 -138 215 138
+rect 169 -150 215 -138
+rect 265 138 311 150
+rect 265 -138 271 138
+rect 305 -138 311 138
+rect 265 -150 311 -138
+rect 361 138 407 150
+rect 361 -138 367 138
+rect 401 -138 407 138
+rect 361 -150 407 -138
+rect 457 138 503 150
+rect 457 -138 463 138
+rect 497 -138 503 138
+rect 457 -150 503 -138
+rect -464 -197 464 -188
+rect -464 -231 -449 -197
+rect -415 -231 -353 -197
+rect -319 -231 -257 -197
+rect -223 -231 -161 -197
+rect -127 -231 -65 -197
+rect -31 -231 31 -197
+rect 65 -231 127 -197
+rect 161 -231 223 -197
+rect 257 -231 319 -197
+rect 353 -231 415 -197
+rect 449 -231 464 -197
+rect -464 -240 464 -231
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -594 -316 594 316
+string parameters w 1.5 l 0.15 m 1 nf 10 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_HRYSXS.mag b/mag/sky130_fd_pr__pfet_01v8_HRYSXS.mag
new file mode 100644
index 0000000..75f22d7
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_HRYSXS.mag
@@ -0,0 +1,64 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -216 -334 216 334
+<< pmos >>
+rect -20 -114 20 186
+<< pdiff >>
+rect -78 174 -20 186
+rect -78 -102 -66 174
+rect -32 -102 -20 174
+rect -78 -114 -20 -102
+rect 20 174 78 186
+rect 20 -102 32 174
+rect 66 -102 78 174
+rect 20 -114 78 -102
+<< pdiffc >>
+rect -66 -102 -32 174
+rect 32 -102 66 174
+<< nsubdiff >>
+rect -180 264 -84 298
+rect 84 264 180 298
+rect -180 201 -146 264
+rect 146 201 180 264
+rect -180 -264 -146 -201
+rect 146 -264 180 -201
+<< nsubdiffcont >>
+rect -84 264 84 298
+rect -180 -201 -146 201
+rect 146 -201 180 201
+<< poly >>
+rect -20 186 20 212
+rect -20 -145 20 -114
+rect -33 -211 33 -145
+<< locali >>
+rect -180 264 -84 298
+rect 84 264 180 298
+rect -180 201 -146 264
+rect 146 201 180 264
+rect -66 174 -32 190
+rect -66 -118 -32 -102
+rect 32 174 66 190
+rect 32 -118 66 -102
+rect -180 -264 -146 -201
+rect 146 -264 180 -201
+<< viali >>
+rect -66 -102 -32 174
+rect 32 -102 66 174
+<< metal1 >>
+rect -72 174 -26 186
+rect -72 -102 -66 174
+rect -32 -102 -26 174
+rect -72 -114 -26 -102
+rect 26 174 72 186
+rect 26 -102 32 174
+rect 66 -102 72 174
+rect 26 -114 72 -102
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -163 -281 163 281
+string parameters w 1.5 l 0.2 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_MJG8BZ.mag b/mag/sky130_fd_pr__pfet_01v8_MJG8BZ.mag
new file mode 100644
index 0000000..594bbc4
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_MJG8BZ.mag
@@ -0,0 +1,79 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -263 -314 263 314
+<< pmos >>
+rect -63 -95 -33 95
+rect 33 -95 63 95
+<< pdiff >>
+rect -125 83 -63 95
+rect -125 -83 -113 83
+rect -79 -83 -63 83
+rect -125 -95 -63 -83
+rect -33 83 33 95
+rect -33 -83 -17 83
+rect 17 -83 33 83
+rect -33 -95 33 -83
+rect 63 83 125 95
+rect 63 -83 79 83
+rect 113 -83 125 83
+rect 63 -95 125 -83
+<< pdiffc >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+<< nsubdiff >>
+rect -227 244 -131 278
+rect 131 244 227 278
+rect -227 182 -193 244
+rect 193 182 227 244
+rect -227 -244 -193 -182
+rect 193 -244 227 -182
+<< nsubdiffcont >>
+rect -131 244 131 278
+rect -227 -182 -193 182
+rect 193 -182 227 182
+<< poly >>
+rect -63 95 -33 121
+rect 33 95 63 121
+rect -63 -126 -33 -95
+rect 33 -126 63 -95
+rect -63 -192 63 -126
+<< locali >>
+rect -227 244 -131 278
+rect 131 244 227 278
+rect -227 182 -193 244
+rect 193 182 227 244
+rect -113 83 -79 99
+rect -113 -99 -79 -83
+rect -17 83 17 99
+rect -17 -99 17 -83
+rect 79 83 113 99
+rect 79 -99 113 -83
+rect -227 -244 -193 -182
+rect 193 -244 227 -182
+<< viali >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+<< metal1 >>
+rect -119 83 -73 95
+rect -119 -83 -113 83
+rect -79 -83 -73 83
+rect -119 -95 -73 -83
+rect -23 83 23 95
+rect -23 -83 -17 83
+rect 17 -83 23 83
+rect -23 -95 23 -83
+rect 73 83 119 95
+rect 73 -83 79 83
+rect 113 -83 119 83
+rect 73 -95 119 -83
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -261 210 261
+string parameters w 0.95 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_MJP3BN.mag b/mag/sky130_fd_pr__pfet_01v8_MJP3BN.mag
new file mode 100644
index 0000000..8177698
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_MJP3BN.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624058804
+<< error_p >>
+rect -29 195 29 201
+rect -29 161 -17 195
+rect -29 155 29 161
+<< nwell >>
+rect -211 -334 211 334
+<< pmos >>
+rect -15 -186 15 114
+<< pdiff >>
+rect -73 102 -15 114
+rect -73 -174 -61 102
+rect -27 -174 -15 102
+rect -73 -186 -15 -174
+rect 15 102 73 114
+rect 15 -174 27 102
+rect 61 -174 73 102
+rect 15 -186 73 -174
+<< pdiffc >>
+rect -61 -174 -27 102
+rect 27 -174 61 102
+<< nsubdiff >>
+rect -175 264 -79 298
+rect 79 264 175 298
+rect -175 201 -141 264
+rect 141 201 175 264
+rect -175 -264 -141 -201
+rect 141 -264 175 -201
+rect -175 -298 -79 -264
+rect 79 -298 175 -264
+<< nsubdiffcont >>
+rect -79 264 79 298
+rect -175 -201 -141 201
+rect 141 -201 175 201
+rect -79 -298 79 -264
+<< poly >>
+rect -33 195 33 211
+rect -33 161 -17 195
+rect 17 161 33 195
+rect -33 145 33 161
+rect -15 114 15 145
+rect -15 -212 15 -186
+<< polycont >>
+rect -17 161 17 195
+<< locali >>
+rect -175 264 -79 298
+rect 79 264 175 298
+rect -175 201 -141 264
+rect 141 201 175 264
+rect -33 161 -17 195
+rect 17 161 33 195
+rect -61 102 -27 118
+rect -61 -190 -27 -174
+rect 27 102 61 118
+rect 27 -190 61 -174
+rect -175 -264 -141 -201
+rect 141 -264 175 -201
+rect -175 -298 -79 -264
+rect 79 -298 175 -264
+<< viali >>
+rect -17 161 17 195
+rect -61 -174 -27 102
+rect 27 -174 61 102
+<< metal1 >>
+rect -29 195 29 201
+rect -29 161 -17 195
+rect 17 161 29 195
+rect -29 155 29 161
+rect -67 102 -21 114
+rect -67 -174 -61 102
+rect -27 -174 -21 102
+rect -67 -186 -21 -174
+rect 21 102 67 114
+rect 21 -174 27 102
+rect 61 -174 67 102
+rect 21 -186 67 -174
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -281 158 281
+string parameters w 1.5 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_ND88ZC.mag b/mag/sky130_fd_pr__pfet_01v8_ND88ZC.mag
new file mode 100644
index 0000000..9fc4394
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_ND88ZC.mag
@@ -0,0 +1,419 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -1367 -369 1367 369
+<< pmos >>
+rect -1167 -150 -1137 150
+rect -1071 -150 -1041 150
+rect -975 -150 -945 150
+rect -879 -150 -849 150
+rect -783 -150 -753 150
+rect -687 -150 -657 150
+rect -591 -150 -561 150
+rect -495 -150 -465 150
+rect -399 -150 -369 150
+rect -303 -150 -273 150
+rect -207 -150 -177 150
+rect -111 -150 -81 150
+rect -15 -150 15 150
+rect 81 -150 111 150
+rect 177 -150 207 150
+rect 273 -150 303 150
+rect 369 -150 399 150
+rect 465 -150 495 150
+rect 561 -150 591 150
+rect 657 -150 687 150
+rect 753 -150 783 150
+rect 849 -150 879 150
+rect 945 -150 975 150
+rect 1041 -150 1071 150
+rect 1137 -150 1167 150
+<< pdiff >>
+rect -1229 138 -1167 150
+rect -1229 -138 -1217 138
+rect -1183 -138 -1167 138
+rect -1229 -150 -1167 -138
+rect -1137 138 -1071 150
+rect -1137 -138 -1121 138
+rect -1087 -138 -1071 138
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+rect -1041 138 -975 150
+rect -1041 -138 -1025 138
+rect -991 -138 -975 138
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+rect -945 138 -879 150
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+rect -849 138 -783 150
+rect -849 -138 -833 138
+rect -799 -138 -783 138
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+rect -753 138 -687 150
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+rect -703 -138 -687 138
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+rect -657 138 -591 150
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+rect -561 138 -495 150
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+rect -273 138 -207 150
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+rect -177 138 -111 150
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+rect -81 138 -15 150
+rect -81 -138 -65 138
+rect -31 -138 -15 138
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+rect 15 138 81 150
+rect 15 -138 31 138
+rect 65 -138 81 138
+rect 15 -150 81 -138
+rect 111 138 177 150
+rect 111 -138 127 138
+rect 161 -138 177 138
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+rect 207 138 273 150
+rect 207 -138 223 138
+rect 257 -138 273 138
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+rect 303 138 369 150
+rect 303 -138 319 138
+rect 353 -138 369 138
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+rect 399 138 465 150
+rect 399 -138 415 138
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+rect 495 138 561 150
+rect 495 -138 511 138
+rect 545 -138 561 138
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+rect 591 138 657 150
+rect 591 -138 607 138
+rect 641 -138 657 138
+rect 591 -150 657 -138
+rect 687 138 753 150
+rect 687 -138 703 138
+rect 737 -138 753 138
+rect 687 -150 753 -138
+rect 783 138 849 150
+rect 783 -138 799 138
+rect 833 -138 849 138
+rect 783 -150 849 -138
+rect 879 138 945 150
+rect 879 -138 895 138
+rect 929 -138 945 138
+rect 879 -150 945 -138
+rect 975 138 1041 150
+rect 975 -138 991 138
+rect 1025 -138 1041 138
+rect 975 -150 1041 -138
+rect 1071 138 1137 150
+rect 1071 -138 1087 138
+rect 1121 -138 1137 138
+rect 1071 -150 1137 -138
+rect 1167 138 1229 150
+rect 1167 -138 1183 138
+rect 1217 -138 1229 138
+rect 1167 -150 1229 -138
+<< pdiffc >>
+rect -1217 -138 -1183 138
+rect -1121 -138 -1087 138
+rect -1025 -138 -991 138
+rect -929 -138 -895 138
+rect -833 -138 -799 138
+rect -737 -138 -703 138
+rect -641 -138 -607 138
+rect -545 -138 -511 138
+rect -449 -138 -415 138
+rect -353 -138 -319 138
+rect -257 -138 -223 138
+rect -161 -138 -127 138
+rect -65 -138 -31 138
+rect 31 -138 65 138
+rect 127 -138 161 138
+rect 223 -138 257 138
+rect 319 -138 353 138
+rect 415 -138 449 138
+rect 511 -138 545 138
+rect 607 -138 641 138
+rect 703 -138 737 138
+rect 799 -138 833 138
+rect 895 -138 929 138
+rect 991 -138 1025 138
+rect 1087 -138 1121 138
+rect 1183 -138 1217 138
+<< nsubdiff >>
+rect -1297 299 -1235 333
+rect 1235 299 1331 333
+rect 1297 237 1331 299
+rect 1297 -299 1331 -237
+<< nsubdiffcont >>
+rect -1235 299 1235 333
+rect 1297 -237 1331 237
+<< poly >>
+rect -1167 150 -1137 176
+rect -1071 150 -1041 176
+rect -975 150 -945 176
+rect -879 150 -849 176
+rect -783 150 -753 176
+rect -687 150 -657 176
+rect -591 150 -561 176
+rect -495 150 -465 176
+rect -399 150 -369 176
+rect -303 150 -273 176
+rect -207 150 -177 176
+rect -111 150 -81 176
+rect -15 150 15 176
+rect 81 150 111 176
+rect 177 150 207 176
+rect 273 150 303 176
+rect 369 150 399 176
+rect 465 150 495 176
+rect 561 150 591 176
+rect 657 150 687 176
+rect 753 150 783 176
+rect 849 150 879 176
+rect 945 150 975 176
+rect 1041 150 1071 176
+rect 1137 150 1167 176
+rect -1167 -181 -1137 -150
+rect -1071 -181 -1041 -150
+rect -975 -181 -945 -150
+rect -879 -181 -849 -150
+rect -783 -181 -753 -150
+rect -687 -181 -657 -150
+rect -591 -181 -561 -150
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+<< viali >>
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+rect 697 138 743 150
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+rect 889 138 935 150
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+rect 1081 -150 1127 -138
+rect 1177 138 1223 150
+rect 1177 -138 1183 138
+rect 1217 -138 1223 138
+rect 1177 -150 1223 -138
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -1314 -316 1314 316
+string parameters w 1.5 l 0.15 m 1 nf 25 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_NKZXKB.mag b/mag/sky130_fd_pr__pfet_01v8_NKZXKB.mag
new file mode 100644
index 0000000..61695b9
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_NKZXKB.mag
@@ -0,0 +1,340 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -1127 -369 1127 369
+<< pmos >>
+rect -927 -150 -897 150
+rect -831 -150 -801 150
+rect -735 -150 -705 150
+rect -639 -150 -609 150
+rect -543 -150 -513 150
+rect -447 -150 -417 150
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+rect 417 -150 447 150
+rect 513 -150 543 150
+rect 609 -150 639 150
+rect 705 -150 735 150
+rect 801 -150 831 150
+rect 897 -150 927 150
+<< pdiff >>
+rect -989 138 -927 150
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+rect -897 138 -831 150
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+rect 927 138 989 150
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+rect 977 -138 989 138
+rect 927 -150 989 -138
+<< pdiffc >>
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+<< nsubdiff >>
+rect -1057 299 -995 333
+rect 995 299 1057 333
+<< nsubdiffcont >>
+rect -995 299 995 333
+<< poly >>
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+rect -831 150 -801 176
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+rect -639 150 -609 176
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+rect -927 -247 -33 -181
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+rect 609 -181 639 -150
+rect 705 -181 735 -150
+rect 801 -181 831 -150
+rect 897 -181 927 -150
+rect 33 -247 927 -181
+<< locali >>
+rect -1057 299 -995 333
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+<< viali >>
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+rect 847 -138 881 138
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+<< metal1 >>
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+rect 457 138 503 150
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+rect 553 138 599 150
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+rect 649 138 695 150
+rect 649 -138 655 138
+rect 689 -138 695 138
+rect 649 -150 695 -138
+rect 745 138 791 150
+rect 745 -138 751 138
+rect 785 -138 791 138
+rect 745 -150 791 -138
+rect 841 138 887 150
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+rect 881 -138 887 138
+rect 841 -150 887 -138
+rect 937 138 983 150
+rect 937 -138 943 138
+rect 977 -138 983 138
+rect 937 -150 983 -138
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -1074 -316 1074 316
+string parameters w 1.5 l 0.15 m 1 nf 20 diffcov 100 polycov 100 guard 1 glc 1 grc 0 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_XJXT7S.mag b/mag/sky130_fd_pr__pfet_01v8_XJXT7S.mag
new file mode 100644
index 0000000..d513894
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_XJXT7S.mag
@@ -0,0 +1,138 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -455 -344 455 344
+<< pmos >>
+rect -255 -125 -225 125
+rect -159 -125 -129 125
+rect -63 -125 -33 125
+rect 33 -125 63 125
+rect 129 -125 159 125
+rect 225 -125 255 125
+<< pdiff >>
+rect -317 113 -255 125
+rect -317 -113 -305 113
+rect -271 -113 -255 113
+rect -317 -125 -255 -113
+rect -225 113 -159 125
+rect -225 -113 -209 113
+rect -175 -113 -159 113
+rect -225 -125 -159 -113
+rect -129 113 -63 125
+rect -129 -113 -113 113
+rect -79 -113 -63 113
+rect -129 -125 -63 -113
+rect -33 113 33 125
+rect -33 -113 -17 113
+rect 17 -113 33 113
+rect -33 -125 33 -113
+rect 63 113 129 125
+rect 63 -113 79 113
+rect 113 -113 129 113
+rect 63 -125 129 -113
+rect 159 113 225 125
+rect 159 -113 175 113
+rect 209 -113 225 113
+rect 159 -125 225 -113
+rect 255 113 317 125
+rect 255 -113 271 113
+rect 305 -113 317 113
+rect 255 -125 317 -113
+<< pdiffc >>
+rect -305 -113 -271 113
+rect -209 -113 -175 113
+rect -113 -113 -79 113
+rect -17 -113 17 113
+rect 79 -113 113 113
+rect 175 -113 209 113
+rect 271 -113 305 113
+<< nsubdiff >>
+rect -419 274 -323 308
+rect 323 274 419 308
+rect -419 212 -385 274
+rect 385 212 419 274
+rect -419 -274 -385 -212
+rect 385 -274 419 -212
+<< nsubdiffcont >>
+rect -323 274 323 308
+rect -419 -212 -385 212
+rect 385 -212 419 212
+<< poly >>
+rect -255 125 -225 151
+rect -159 125 -129 151
+rect -63 125 -33 151
+rect 33 125 63 151
+rect 129 125 159 151
+rect 225 125 255 151
+rect -255 -154 -225 -125
+rect -159 -154 -129 -125
+rect -63 -154 -33 -125
+rect 33 -154 63 -125
+rect 129 -154 159 -125
+rect 225 -154 255 -125
+<< locali >>
+rect -419 274 -323 308
+rect 323 274 419 308
+rect -419 212 -385 274
+rect 385 212 419 274
+rect -305 113 -271 129
+rect -305 -129 -271 -113
+rect -209 113 -175 129
+rect -209 -129 -175 -113
+rect -113 113 -79 129
+rect -113 -129 -79 -113
+rect -17 113 17 129
+rect -17 -129 17 -113
+rect 79 113 113 129
+rect 79 -129 113 -113
+rect 175 113 209 129
+rect 175 -129 209 -113
+rect 271 113 305 129
+rect 271 -129 305 -113
+rect -419 -274 -385 -212
+rect 385 -274 419 -212
+<< viali >>
+rect -305 -113 -271 113
+rect -209 -113 -175 113
+rect -113 -113 -79 113
+rect -17 -113 17 113
+rect 79 -113 113 113
+rect 175 -113 209 113
+rect 271 -113 305 113
+<< metal1 >>
+rect -311 113 -265 125
+rect -311 -113 -305 113
+rect -271 -113 -265 113
+rect -311 -125 -265 -113
+rect -215 113 -169 125
+rect -215 -113 -209 113
+rect -175 -113 -169 113
+rect -215 -125 -169 -113
+rect -119 113 -73 125
+rect -119 -113 -113 113
+rect -79 -113 -73 113
+rect -119 -125 -73 -113
+rect -23 113 23 125
+rect -23 -113 -17 113
+rect 17 -113 23 113
+rect -23 -125 23 -113
+rect 73 113 119 125
+rect 73 -113 79 113
+rect 113 -113 119 113
+rect 73 -125 119 -113
+rect 169 113 215 125
+rect 169 -113 175 113
+rect 209 -113 215 113
+rect 169 -125 215 -113
+rect 265 113 311 125
+rect 265 -113 271 113
+rect 305 -113 311 113
+rect 265 -125 311 -113
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -402 -291 402 291
+string parameters w 1.25 l 0.15 m 1 nf 6 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_ZP3U9B.mag b/mag/sky130_fd_pr__pfet_01v8_ZP3U9B.mag
new file mode 100644
index 0000000..d58647c
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_ZP3U9B.mag
@@ -0,0 +1,108 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -359 -303 359 303
+<< pmos >>
+rect -159 -84 -129 84
+rect -63 -84 -33 84
+rect 33 -84 63 84
+rect 129 -84 159 84
+<< pdiff >>
+rect -221 72 -159 84
+rect -221 -72 -209 72
+rect -175 -72 -159 72
+rect -221 -84 -159 -72
+rect -129 72 -63 84
+rect -129 -72 -113 72
+rect -79 -72 -63 72
+rect -129 -84 -63 -72
+rect -33 72 33 84
+rect -33 -72 -17 72
+rect 17 -72 33 72
+rect -33 -84 33 -72
+rect 63 72 129 84
+rect 63 -72 79 72
+rect 113 -72 129 72
+rect 63 -84 129 -72
+rect 159 72 221 84
+rect 159 -72 175 72
+rect 209 -72 221 72
+rect 159 -84 221 -72
+<< pdiffc >>
+rect -209 -72 -175 72
+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+rect 175 -72 209 72
+<< nsubdiff >>
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+rect 227 233 323 267
+rect -323 171 -289 233
+rect 289 171 323 233
+rect -323 -233 -289 -171
+rect 289 -233 323 -171
+<< nsubdiffcont >>
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+rect -323 -171 -289 171
+rect 289 -171 323 171
+<< poly >>
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+rect 33 84 63 110
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+rect -159 -110 -129 -84
+rect -63 -110 -33 -84
+rect 33 -110 63 -84
+rect 129 -110 159 -84
+<< locali >>
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+rect 79 72 113 88
+rect 79 -88 113 -72
+rect 175 72 209 88
+rect 175 -88 209 -72
+rect -323 -233 -289 -171
+rect 289 -233 323 -171
+<< viali >>
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+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+rect 175 -72 209 72
+<< metal1 >>
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+rect -215 -72 -209 72
+rect -175 -72 -169 72
+rect -215 -84 -169 -72
+rect -119 72 -73 84
+rect -119 -72 -113 72
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+rect 73 -72 79 72
+rect 113 -72 119 72
+rect 73 -84 119 -72
+rect 169 72 215 84
+rect 169 -72 175 72
+rect 209 -72 215 72
+rect 169 -84 215 -72
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -306 -250 306 250
+string parameters w 0.84 l 0.15 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_ZPB9BB.mag b/mag/sky130_fd_pr__pfet_01v8_ZPB9BB.mag
new file mode 100644
index 0000000..0b3d65d
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_ZPB9BB.mag
@@ -0,0 +1,78 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -263 -303 263 303
+<< pmos >>
+rect -63 -84 -33 84
+rect 33 -84 63 84
+<< pdiff >>
+rect -125 72 -63 84
+rect -125 -72 -113 72
+rect -79 -72 -63 72
+rect -125 -84 -63 -72
+rect -33 72 33 84
+rect -33 -72 -17 72
+rect 17 -72 33 72
+rect -33 -84 33 -72
+rect 63 72 125 84
+rect 63 -72 79 72
+rect 113 -72 125 72
+rect 63 -84 125 -72
+<< pdiffc >>
+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+<< nsubdiff >>
+rect -227 233 -131 267
+rect 131 233 227 267
+rect -227 171 -193 233
+rect 193 171 227 233
+rect -227 -233 -193 -171
+rect 193 -233 227 -171
+<< nsubdiffcont >>
+rect -131 233 131 267
+rect -227 -171 -193 171
+rect 193 -171 227 171
+<< poly >>
+rect -63 84 -33 110
+rect 33 84 63 110
+rect -63 -110 -33 -84
+rect 33 -110 63 -84
+<< locali >>
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+rect 131 233 227 267
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+rect 193 171 227 233
+rect -113 72 -79 88
+rect -113 -88 -79 -72
+rect -17 72 17 88
+rect -17 -88 17 -72
+rect 79 72 113 88
+rect 79 -88 113 -72
+rect -227 -233 -193 -171
+rect 193 -233 227 -171
+<< viali >>
+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+<< metal1 >>
+rect -119 72 -73 84
+rect -119 -72 -113 72
+rect -79 -72 -73 72
+rect -119 -84 -73 -72
+rect -23 72 23 84
+rect -23 -72 -17 72
+rect 17 -72 23 72
+rect -23 -84 23 -72
+rect 73 72 119 84
+rect 73 -72 79 72
+rect 113 -72 119 72
+rect 73 -84 119 -72
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -250 210 250
+string parameters w 0.84 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_lvt_8P223X.mag b/mag/sky130_fd_pr__pfet_01v8_lvt_8P223X.mag
new file mode 100644
index 0000000..3e28e0a
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_lvt_8P223X.mag
@@ -0,0 +1,1253 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -2017 76 2017 1196
+rect -2018 -202 2017 76
+rect -2017 -1367 2017 -202
+<< pmoslvt >>
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+rect -1821 -1219 -1731 -319
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+rect 1435 -1219 1525 -319
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+rect 1537 -1207 1571 -331
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+rect 1833 -1207 1867 -331
+<< nsubdiff >>
+rect -1947 1126 -1885 1160
+rect 1885 1126 1947 1160
+rect -1947 1025 -1885 1059
+rect 1885 1025 1947 1059
+<< nsubdiffcont >>
+rect -1885 1126 1885 1160
+rect -1885 1025 1885 1059
+<< poly >>
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+rect -1673 947 -1583 964
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+rect -1821 -1241 -1731 -1219
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+rect -1027 -44 -903 -10
+rect -720 -44 -596 -10
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+rect 1046 -264 1170 -230
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+<< locali >>
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+rect 762 -271 894 -264
+rect 1040 -230 1172 -219
+rect 1040 -264 1046 -230
+rect 1046 -264 1170 -230
+rect 1170 -264 1172 -230
+rect 1040 -271 1172 -264
+rect 1345 -230 1477 -219
+rect 1345 -264 1351 -230
+rect 1351 -264 1475 -230
+rect 1475 -264 1477 -230
+rect 1345 -271 1477 -264
+rect 1650 -230 1782 -219
+rect 1650 -264 1656 -230
+rect 1656 -264 1780 -230
+rect 1780 -264 1782 -230
+rect 1650 -271 1782 -264
+<< metal2 >>
+rect -2017 0 2017 13
+rect -2017 -55 -1913 0
+rect -1773 -55 -1621 0
+rect -1481 -55 -1314 0
+rect -1174 -55 -1038 0
+rect -898 -55 -731 0
+rect -591 -55 -424 0
+rect -284 -55 -148 0
+rect -8 -55 159 0
+rect 299 -55 436 0
+rect 576 -55 756 0
+rect 896 -55 1029 0
+rect 1169 -55 1331 0
+rect 1471 -55 1634 0
+rect 1774 -55 2017 0
+rect -2017 -57 2017 -55
+rect -1913 -65 -1773 -57
+rect -1621 -65 -1481 -57
+rect -1314 -65 -1174 -57
+rect -1038 -65 -898 -57
+rect -731 -65 -591 -57
+rect -424 -65 -284 -57
+rect -148 -65 -8 -57
+rect 159 -65 299 -57
+rect 436 -65 576 -57
+rect 756 -65 896 -57
+rect 1029 -65 1169 -57
+rect 1331 -65 1471 -57
+rect 1634 -65 1774 -57
+rect -1909 -215 -1777 -209
+rect -1622 -215 -1490 -209
+rect -1318 -215 -1186 -209
+rect -1013 -215 -881 -209
+rect -744 -215 -612 -209
+rect -439 -215 -307 -209
+rect -134 -215 -2 -209
+rect 170 -215 302 -209
+rect 457 -215 589 -209
+rect 762 -215 894 -209
+rect 1040 -215 1172 -209
+rect 1345 -215 1477 -209
+rect 1650 -215 1782 -209
+rect -2017 -219 2017 -215
+rect -2017 -271 -1909 -219
+rect -1777 -271 -1622 -219
+rect -1490 -271 -1318 -219
+rect -1186 -271 -1013 -219
+rect -881 -271 -744 -219
+rect -612 -271 -439 -219
+rect -307 -271 -134 -219
+rect -2 -271 170 -219
+rect 302 -271 457 -219
+rect 589 -271 762 -219
+rect 894 -271 1040 -219
+rect 1172 -271 1345 -219
+rect 1477 -271 1650 -219
+rect 1782 -271 2017 -219
+rect -2017 -285 2017 -271
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8_lvt
+string FIXED_BBOX -1964 -1042 1964 1042
+string parameters w 4.5 l 0.45 m 2 nf 25 diffcov 100 polycov 100 guard 1 glc 0 grc 0 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__res_high_po_5p73_X44RQA.mag b/mag/sky130_fd_pr__res_high_po_5p73_X44RQA.mag
new file mode 100644
index 0000000..0f13fc3
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_5p73_X44RQA.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< pwell >>
+rect -739 -2890 739 2890
+<< psubdiff >>
+rect -703 2820 -607 2854
+rect 607 2820 703 2854
+rect -703 2758 -669 2820
+rect 669 2758 703 2820
+rect -703 -2820 -669 -2758
+rect 669 -2820 703 -2758
+rect -703 -2854 -607 -2820
+rect 607 -2854 703 -2820
+<< psubdiffcont >>
+rect -607 2820 607 2854
+rect -703 -2758 -669 2758
+rect 669 -2758 703 2758
+rect -607 -2854 607 -2820
+<< xpolycontact >>
+rect -573 2292 573 2724
+rect -573 -2724 573 -2292
+<< ppolyres >>
+rect -573 -2292 573 2292
+<< locali >>
+rect -703 2820 -607 2854
+rect 607 2820 703 2854
+rect -703 2758 -669 2820
+rect 669 2758 703 2820
+rect -703 -2820 -669 -2758
+rect 669 -2820 703 -2758
+rect -703 -2854 -607 -2820
+rect 607 -2854 703 -2820
+<< viali >>
+rect -557 2309 557 2706
+rect -557 -2706 557 -2309
+<< metal1 >>
+rect -569 2706 569 2712
+rect -569 2309 -557 2706
+rect 557 2309 569 2706
+rect -569 2303 569 2309
+rect -569 -2309 569 -2303
+rect -569 -2706 -557 -2309
+rect 557 -2706 569 -2309
+rect -569 -2712 569 -2706
+<< res5p73 >>
+rect -575 -2294 575 2294
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_5p73
+string FIXED_BBOX -686 -2837 686 2837
+string parameters w 5.730 l 22.92 m 1 nx 1 wmin 5.730 lmin 0.50 rho 319.8 val 1.285k dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_high_po_0p35 sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 1 wmax 5.730 n_guard 0 hv_guard 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_sc_hs__and2_1.mag b/mag/sky130_fd_sc_hs__and2_1.mag
new file mode 100644
index 0000000..1b0d438
--- /dev/null
+++ b/mag/sky130_fd_sc_hs__and2_1.mag
@@ -0,0 +1,251 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -38 332 518 704
+<< pwell >>
+rect 30 274 219 290
+rect 30 49 456 274
+rect 0 0 480 49
+<< scpmos >>
+rect 134 424 164 592
+rect 234 424 264 592
+rect 341 368 371 592
+<< nmoslvt >>
+rect 113 136 143 264
+rect 227 120 257 248
+rect 343 100 373 248
+<< ndiff >>
+rect 56 223 113 264
+rect 56 189 68 223
+rect 102 189 113 223
+rect 56 136 113 189
+rect 143 248 193 264
+rect 143 136 227 248
+rect 177 120 227 136
+rect 257 186 343 248
+rect 257 152 284 186
+rect 318 152 343 186
+rect 257 120 343 152
+rect 272 100 343 120
+rect 373 226 430 248
+rect 373 192 384 226
+rect 418 192 430 226
+rect 373 146 430 192
+rect 373 112 384 146
+rect 418 112 430 146
+rect 373 100 430 112
+<< pdiff >>
+rect 74 580 134 592
+rect 74 546 86 580
+rect 120 546 134 580
+rect 74 476 134 546
+rect 74 442 86 476
+rect 120 442 134 476
+rect 74 424 134 442
+rect 164 584 234 592
+rect 164 550 187 584
+rect 221 550 234 584
+rect 164 470 234 550
+rect 164 436 187 470
+rect 221 436 234 470
+rect 164 424 234 436
+rect 264 580 341 592
+rect 264 546 294 580
+rect 328 546 341 580
+rect 264 488 341 546
+rect 264 454 294 488
+rect 328 454 341 488
+rect 264 424 341 454
+rect 288 368 341 424
+rect 371 580 430 592
+rect 371 546 384 580
+rect 418 546 430 580
+rect 371 500 430 546
+rect 371 466 384 500
+rect 418 466 430 500
+rect 371 420 430 466
+rect 371 386 384 420
+rect 418 386 430 420
+rect 371 368 430 386
+<< ndiffc >>
+rect 68 189 102 223
+rect 284 152 318 186
+rect 384 192 418 226
+rect 384 112 418 146
+<< pdiffc >>
+rect 86 546 120 580
+rect 86 442 120 476
+rect 187 550 221 584
+rect 187 436 221 470
+rect 294 546 328 580
+rect 294 454 328 488
+rect 384 546 418 580
+rect 384 466 418 500
+rect 384 386 418 420
+<< poly >>
+rect 134 592 164 618
+rect 234 592 264 618
+rect 341 592 371 618
+rect 134 409 164 424
+rect 234 409 264 424
+rect 131 309 167 409
+rect 231 336 267 409
+rect 341 353 371 368
+rect 338 336 374 353
+rect 113 279 167 309
+rect 215 320 281 336
+rect 215 286 231 320
+rect 265 286 281 320
+rect 113 264 143 279
+rect 215 270 281 286
+rect 329 320 395 336
+rect 329 286 345 320
+rect 379 286 395 320
+rect 329 270 395 286
+rect 227 248 257 270
+rect 343 248 373 270
+rect 113 114 143 136
+rect 21 98 155 114
+rect 21 64 37 98
+rect 71 64 105 98
+rect 139 64 155 98
+rect 227 94 257 120
+rect 343 74 373 100
+rect 21 48 155 64
+<< polycont >>
+rect 231 286 265 320
+rect 345 286 379 320
+rect 37 64 71 98
+rect 105 64 139 98
+<< locali >>
+rect 0 649 31 683
+rect 65 649 127 683
+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
+rect 449 649 480 683
+rect 70 580 137 649
+rect 70 546 86 580
+rect 120 546 137 580
+rect 70 476 137 546
+rect 70 442 86 476
+rect 120 442 137 476
+rect 70 438 137 442
+rect 171 584 237 600
+rect 171 550 187 584
+rect 221 550 237 584
+rect 171 470 237 550
+rect 171 436 187 470
+rect 221 436 237 470
+rect 278 580 344 649
+rect 278 546 294 580
+rect 328 546 344 580
+rect 278 488 344 546
+rect 278 454 294 488
+rect 328 454 344 488
+rect 278 438 344 454
+rect 384 580 463 596
+rect 418 546 463 580
+rect 384 500 463 546
+rect 418 466 463 500
+rect 171 404 237 436
+rect 384 420 463 466
+rect 52 370 350 404
+rect 418 386 463 420
+rect 384 370 463 386
+rect 52 223 118 370
+rect 316 336 350 370
+rect 215 320 281 336
+rect 215 286 231 320
+rect 265 286 281 320
+rect 215 236 281 286
+rect 316 320 395 336
+rect 316 286 345 320
+rect 379 286 395 320
+rect 316 270 395 286
+rect 429 236 463 370
+rect 52 189 68 223
+rect 102 189 118 223
+rect 368 226 463 236
+rect 52 168 118 189
+rect 268 186 334 202
+rect 268 152 284 186
+rect 318 152 334 186
+rect 21 98 167 134
+rect 21 64 37 98
+rect 71 64 105 98
+rect 139 64 167 98
+rect 21 51 167 64
+rect 268 17 334 152
+rect 368 192 384 226
+rect 418 192 463 226
+rect 368 146 463 192
+rect 368 112 384 146
+rect 418 112 463 146
+rect 368 94 463 112
+rect 0 -17 31 17
+rect 65 -17 127 17
+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 480 17
+<< viali >>
+rect 31 649 65 683
+rect 127 649 161 683
+rect 223 649 257 683
+rect 319 649 353 683
+rect 415 649 449 683
+rect 31 -17 65 17
+rect 127 -17 161 17
+rect 223 -17 257 17
+rect 319 -17 353 17
+rect 415 -17 449 17
+<< metal1 >>
+rect 0 683 480 715
+rect 0 649 31 683
+rect 65 649 127 683
+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
+rect 449 649 480 683
+rect 0 617 480 649
+rect 0 17 480 49
+rect 0 -17 31 17
+rect 65 -17 127 17
+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 480 17
+rect 0 -49 480 -17
+<< labels >>
+rlabel comment s 0 0 0 0 4 and2_1
+flabel pwell s 0 0 480 49 0 FreeSans 200 0 0 0 VNB
+port 4 nsew ground bidirectional
+flabel nwell s 0 617 480 666 0 FreeSans 200 0 0 0 VPB
+port 5 nsew power bidirectional
+flabel metal1 s 0 617 480 666 0 FreeSans 340 0 0 0 VPWR
+port 6 nsew power bidirectional
+flabel metal1 s 0 0 480 49 0 FreeSans 340 0 0 0 VGND
+port 3 nsew ground bidirectional
+flabel locali s 31 94 65 128 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 127 94 161 128 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 223 242 257 276 0 FreeSans 340 0 0 0 B
+port 2 nsew signal input
+flabel locali s 415 390 449 424 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 464 449 498 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 538 449 572 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+<< properties >>
+string LEFsite unit
+string LEFclass CORE
+string FIXED_BBOX 0 0 480 666
+string LEFsymmetry X Y
+string GDS_END 1585064
+string GDS_START 1579992
+<< end >>
diff --git a/mag/sky130_fd_sc_hs__and2_1.mag.original b/mag/sky130_fd_sc_hs__and2_1.mag.original
new file mode 100644
index 0000000..1fed914
--- /dev/null
+++ b/mag/sky130_fd_sc_hs__and2_1.mag.original
@@ -0,0 +1,254 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1622592543
+<< checkpaint >>
+rect -1298 -1309 1778 1975
+<< nwell >>
+rect -38 332 518 704
+<< pwell >>
+rect 30 274 219 290
+rect 30 49 456 274
+rect 0 0 480 49
+<< scpmos >>
+rect 134 424 164 592
+rect 234 424 264 592
+rect 341 368 371 592
+<< nmoslvt >>
+rect 113 136 143 264
+rect 227 120 257 248
+rect 343 100 373 248
+<< ndiff >>
+rect 56 223 113 264
+rect 56 189 68 223
+rect 102 189 113 223
+rect 56 136 113 189
+rect 143 248 193 264
+rect 143 136 227 248
+rect 177 120 227 136
+rect 257 186 343 248
+rect 257 152 284 186
+rect 318 152 343 186
+rect 257 120 343 152
+rect 272 100 343 120
+rect 373 226 430 248
+rect 373 192 384 226
+rect 418 192 430 226
+rect 373 146 430 192
+rect 373 112 384 146
+rect 418 112 430 146
+rect 373 100 430 112
+<< pdiff >>
+rect 74 580 134 592
+rect 74 546 86 580
+rect 120 546 134 580
+rect 74 476 134 546
+rect 74 442 86 476
+rect 120 442 134 476
+rect 74 424 134 442
+rect 164 584 234 592
+rect 164 550 187 584
+rect 221 550 234 584
+rect 164 470 234 550
+rect 164 436 187 470
+rect 221 436 234 470
+rect 164 424 234 436
+rect 264 580 341 592
+rect 264 546 294 580
+rect 328 546 341 580
+rect 264 488 341 546
+rect 264 454 294 488
+rect 328 454 341 488
+rect 264 424 341 454
+rect 288 368 341 424
+rect 371 580 430 592
+rect 371 546 384 580
+rect 418 546 430 580
+rect 371 500 430 546
+rect 371 466 384 500
+rect 418 466 430 500
+rect 371 420 430 466
+rect 371 386 384 420
+rect 418 386 430 420
+rect 371 368 430 386
+<< ndiffc >>
+rect 68 189 102 223
+rect 284 152 318 186
+rect 384 192 418 226
+rect 384 112 418 146
+<< pdiffc >>
+rect 86 546 120 580
+rect 86 442 120 476
+rect 187 550 221 584
+rect 187 436 221 470
+rect 294 546 328 580
+rect 294 454 328 488
+rect 384 546 418 580
+rect 384 466 418 500
+rect 384 386 418 420
+<< poly >>
+rect 134 592 164 618
+rect 234 592 264 618
+rect 341 592 371 618
+rect 134 409 164 424
+rect 234 409 264 424
+rect 131 309 167 409
+rect 231 336 267 409
+rect 341 353 371 368
+rect 338 336 374 353
+rect 113 279 167 309
+rect 215 320 281 336
+rect 215 286 231 320
+rect 265 286 281 320
+rect 113 264 143 279
+rect 215 270 281 286
+rect 329 320 395 336
+rect 329 286 345 320
+rect 379 286 395 320
+rect 329 270 395 286
+rect 227 248 257 270
+rect 343 248 373 270
+rect 113 114 143 136
+rect 21 98 155 114
+rect 21 64 37 98
+rect 71 64 105 98
+rect 139 64 155 98
+rect 227 94 257 120
+rect 343 74 373 100
+rect 21 48 155 64
+<< polycont >>
+rect 231 286 265 320
+rect 345 286 379 320
+rect 37 64 71 98
+rect 105 64 139 98
+<< locali >>
+rect 0 649 31 683
+rect 65 649 127 683
+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
+rect 449 649 480 683
+rect 70 580 137 649
+rect 70 546 86 580
+rect 120 546 137 580
+rect 70 476 137 546
+rect 70 442 86 476
+rect 120 442 137 476
+rect 70 438 137 442
+rect 171 584 237 600
+rect 171 550 187 584
+rect 221 550 237 584
+rect 171 470 237 550
+rect 171 436 187 470
+rect 221 436 237 470
+rect 278 580 344 649
+rect 278 546 294 580
+rect 328 546 344 580
+rect 278 488 344 546
+rect 278 454 294 488
+rect 328 454 344 488
+rect 278 438 344 454
+rect 384 580 463 596
+rect 418 546 463 580
+rect 384 500 463 546
+rect 418 466 463 500
+rect 171 404 237 436
+rect 384 420 463 466
+rect 52 370 350 404
+rect 418 386 463 420
+rect 384 370 463 386
+rect 52 223 118 370
+rect 316 336 350 370
+rect 215 320 281 336
+rect 215 286 231 320
+rect 265 286 281 320
+rect 215 236 281 286
+rect 316 320 395 336
+rect 316 286 345 320
+rect 379 286 395 320
+rect 316 270 395 286
+rect 429 236 463 370
+rect 52 189 68 223
+rect 102 189 118 223
+rect 368 226 463 236
+rect 52 168 118 189
+rect 268 186 334 202
+rect 268 152 284 186
+rect 318 152 334 186
+rect 21 98 167 134
+rect 21 64 37 98
+rect 71 64 105 98
+rect 139 64 167 98
+rect 21 51 167 64
+rect 268 17 334 152
+rect 368 192 384 226
+rect 418 192 463 226
+rect 368 146 463 192
+rect 368 112 384 146
+rect 418 112 463 146
+rect 368 94 463 112
+rect 0 -17 31 17
+rect 65 -17 127 17
+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 480 17
+<< viali >>
+rect 31 649 65 683
+rect 127 649 161 683
+rect 223 649 257 683
+rect 319 649 353 683
+rect 415 649 449 683
+rect 31 -17 65 17
+rect 127 -17 161 17
+rect 223 -17 257 17
+rect 319 -17 353 17
+rect 415 -17 449 17
+<< metal1 >>
+rect 0 683 480 715
+rect 0 649 31 683
+rect 65 649 127 683
+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
+rect 449 649 480 683
+rect 0 617 480 649
+rect 0 17 480 49
+rect 0 -17 31 17
+rect 65 -17 127 17
+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 480 17
+rect 0 -49 480 -17
+<< labels >>
+rlabel comment s 0 0 0 0 4 and2_1
+flabel pwell s 0 0 480 49 0 FreeSans 200 0 0 0 VNB
+port 4 nsew ground bidirectional
+flabel nwell s 0 617 480 666 0 FreeSans 200 0 0 0 VPB
+port 5 nsew power bidirectional
+flabel metal1 s 0 617 480 666 0 FreeSans 340 0 0 0 VPWR
+port 6 nsew power bidirectional
+flabel metal1 s 0 0 480 49 0 FreeSans 340 0 0 0 VGND
+port 3 nsew ground bidirectional
+flabel locali s 31 94 65 128 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 127 94 161 128 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 223 242 257 276 0 FreeSans 340 0 0 0 B
+port 2 nsew signal input
+flabel locali s 415 390 449 424 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 464 449 498 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 538 449 572 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+<< properties >>
+string LEFsite unit
+string LEFclass CORE
+string FIXED_BBOX 0 0 480 666
+string GDS_FILE $PDKPATH/libs.ref/sky130_fd_sc_hs/gds/sky130_fd_sc_hs.gds
+string LEFsymmetry X Y
+string GDS_END 1585064
+string GDS_START 1579992
+<< end >>
diff --git a/mag/sky130_fd_sc_hs__or2_1.mag b/mag/sky130_fd_sc_hs__or2_1.mag
new file mode 100644
index 0000000..7f78ef0
--- /dev/null
+++ b/mag/sky130_fd_sc_hs__or2_1.mag
@@ -0,0 +1,251 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -38 332 518 704
+<< pwell >>
+rect 1 49 479 248
+rect 0 0 480 49
+<< scpmos >>
+rect 122 368 152 536
+rect 206 368 236 536
+rect 364 368 394 592
+<< nmoslvt >>
+rect 125 112 155 222
+rect 250 112 280 222
+rect 366 74 396 222
+<< ndiff >>
+rect 27 183 125 222
+rect 27 149 80 183
+rect 114 149 125 183
+rect 27 112 125 149
+rect 155 181 250 222
+rect 155 147 198 181
+rect 232 147 250 181
+rect 155 112 250 147
+rect 280 152 366 222
+rect 280 118 307 152
+rect 341 118 366 152
+rect 280 112 366 118
+rect 295 74 366 112
+rect 396 210 453 222
+rect 396 176 407 210
+rect 441 176 453 210
+rect 396 120 453 176
+rect 396 86 407 120
+rect 441 86 453 120
+rect 396 74 453 86
+<< pdiff >>
+rect 270 580 364 592
+rect 270 546 317 580
+rect 351 546 364 580
+rect 270 536 364 546
+rect 63 524 122 536
+rect 63 490 75 524
+rect 109 490 122 524
+rect 63 414 122 490
+rect 63 380 75 414
+rect 109 380 122 414
+rect 63 368 122 380
+rect 152 368 206 536
+rect 236 508 364 536
+rect 236 492 317 508
+rect 236 458 249 492
+rect 283 474 317 492
+rect 351 474 364 508
+rect 283 458 364 474
+rect 236 368 364 458
+rect 394 580 453 592
+rect 394 546 407 580
+rect 441 546 453 580
+rect 394 497 453 546
+rect 394 463 407 497
+rect 441 463 453 497
+rect 394 414 453 463
+rect 394 380 407 414
+rect 441 380 453 414
+rect 394 368 453 380
+<< ndiffc >>
+rect 80 149 114 183
+rect 198 147 232 181
+rect 307 118 341 152
+rect 407 176 441 210
+rect 407 86 441 120
+<< pdiffc >>
+rect 317 546 351 580
+rect 75 490 109 524
+rect 75 380 109 414
+rect 249 458 283 492
+rect 317 474 351 508
+rect 407 546 441 580
+rect 407 463 441 497
+rect 407 380 441 414
+<< poly >>
+rect 364 592 394 618
+rect 122 536 152 562
+rect 206 536 236 562
+rect 122 353 152 368
+rect 206 353 236 368
+rect 364 353 394 368
+rect 119 310 155 353
+rect 21 294 155 310
+rect 203 336 239 353
+rect 203 320 280 336
+rect 361 326 397 353
+rect 203 306 225 320
+rect 21 260 37 294
+rect 71 260 105 294
+rect 139 260 155 294
+rect 209 286 225 306
+rect 259 286 280 320
+rect 209 270 280 286
+rect 21 244 155 260
+rect 125 222 155 244
+rect 250 222 280 270
+rect 328 310 397 326
+rect 328 276 344 310
+rect 378 276 397 310
+rect 328 260 397 276
+rect 366 222 396 260
+rect 125 86 155 112
+rect 250 86 280 112
+rect 366 48 396 74
+<< polycont >>
+rect 37 260 71 294
+rect 105 260 139 294
+rect 225 286 259 320
+rect 344 276 378 310
+<< locali >>
+rect 0 649 31 683
+rect 65 649 127 683
+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
+rect 449 649 480 683
+rect 233 580 357 649
+rect 233 546 317 580
+rect 351 546 357 580
+rect 59 524 125 540
+rect 59 490 75 524
+rect 109 490 125 524
+rect 59 424 125 490
+rect 233 508 357 546
+rect 233 492 317 508
+rect 233 458 249 492
+rect 283 474 317 492
+rect 351 474 357 508
+rect 283 458 357 474
+rect 391 580 462 596
+rect 391 546 407 580
+rect 441 546 462 580
+rect 391 497 462 546
+rect 391 463 407 497
+rect 441 463 462 497
+rect 59 414 357 424
+rect 59 380 75 414
+rect 109 390 357 414
+rect 109 380 125 390
+rect 59 364 125 380
+rect 209 320 275 356
+rect 21 294 155 310
+rect 21 260 37 294
+rect 71 260 105 294
+rect 139 260 155 294
+rect 209 286 225 320
+rect 259 286 275 320
+rect 209 270 275 286
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+rect 0 -17 31 17
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+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
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+<< viali >>
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+rect 127 649 161 683
+rect 223 649 257 683
+rect 319 649 353 683
+rect 415 649 449 683
+rect 31 -17 65 17
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+<< metal1 >>
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+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
+rect 449 649 480 683
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+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 480 17
+rect 0 -49 480 -17
+<< labels >>
+rlabel comment s 0 0 0 0 4 or2_1
+flabel pwell s 0 0 480 49 0 FreeSans 200 0 0 0 VNB
+port 4 nsew ground bidirectional
+flabel nwell s 0 617 480 666 0 FreeSans 200 0 0 0 VPB
+port 5 nsew power bidirectional
+flabel metal1 s 0 617 480 666 0 FreeSans 340 0 0 0 VPWR
+port 6 nsew power bidirectional
+flabel metal1 s 0 0 480 49 0 FreeSans 340 0 0 0 VGND
+port 3 nsew ground bidirectional
+flabel locali s 31 242 65 276 0 FreeSans 340 0 0 0 B
+port 2 nsew signal input
+flabel locali s 223 316 257 350 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 415 390 449 424 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 464 449 498 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 538 449 572 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+<< properties >>
+string LEFsite unit
+string LEFclass CORE
+string FIXED_BBOX 0 0 480 666
+string LEFsymmetry X Y
+string GDS_END 1245662
+string GDS_START 1240892
+<< end >>
diff --git a/mag/sky130_fd_sc_hs__or2_1.mag.original b/mag/sky130_fd_sc_hs__or2_1.mag.original
new file mode 100644
index 0000000..ff8dfc0
--- /dev/null
+++ b/mag/sky130_fd_sc_hs__or2_1.mag.original
@@ -0,0 +1,254 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1622592543
+<< checkpaint >>
+rect -1298 -1309 1778 1975
+<< nwell >>
+rect -38 332 518 704
+<< pwell >>
+rect 1 49 479 248
+rect 0 0 480 49
+<< scpmos >>
+rect 122 368 152 536
+rect 206 368 236 536
+rect 364 368 394 592
+<< nmoslvt >>
+rect 125 112 155 222
+rect 250 112 280 222
+rect 366 74 396 222
+<< ndiff >>
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+rect 27 149 80 183
+rect 114 149 125 183
+rect 27 112 125 149
+rect 155 181 250 222
+rect 155 147 198 181
+rect 232 147 250 181
+rect 155 112 250 147
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+rect 341 118 366 152
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+rect 396 210 453 222
+rect 396 176 407 210
+rect 441 176 453 210
+rect 396 120 453 176
+rect 396 86 407 120
+rect 441 86 453 120
+rect 396 74 453 86
+<< pdiff >>
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+rect 270 546 317 580
+rect 351 546 364 580
+rect 270 536 364 546
+rect 63 524 122 536
+rect 63 490 75 524
+rect 109 490 122 524
+rect 63 414 122 490
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+rect 394 497 453 546
+rect 394 463 407 497
+rect 441 463 453 497
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+rect 394 380 407 414
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+rect 394 368 453 380
+<< ndiffc >>
+rect 80 149 114 183
+rect 198 147 232 181
+rect 307 118 341 152
+rect 407 176 441 210
+rect 407 86 441 120
+<< pdiffc >>
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+rect 75 490 109 524
+rect 75 380 109 414
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+rect 407 463 441 497
+rect 407 380 441 414
+<< poly >>
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+rect 21 294 155 310
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+rect 366 48 396 74
+<< polycont >>
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+rect 105 260 139 294
+rect 225 286 259 320
+rect 344 276 378 310
+<< locali >>
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+rect 391 70 462 86
+rect 0 -17 31 17
+rect 65 -17 127 17
+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 480 17
+<< viali >>
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+rect 127 649 161 683
+rect 223 649 257 683
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+rect 415 649 449 683
+rect 31 -17 65 17
+rect 127 -17 161 17
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+rect 319 -17 353 17
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+<< metal1 >>
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+rect 65 649 127 683
+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
+rect 449 649 480 683
+rect 0 617 480 649
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+rect 65 -17 127 17
+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 480 17
+rect 0 -49 480 -17
+<< labels >>
+rlabel comment s 0 0 0 0 4 or2_1
+flabel pwell s 0 0 480 49 0 FreeSans 200 0 0 0 VNB
+port 4 nsew ground bidirectional
+flabel nwell s 0 617 480 666 0 FreeSans 200 0 0 0 VPB
+port 5 nsew power bidirectional
+flabel metal1 s 0 617 480 666 0 FreeSans 340 0 0 0 VPWR
+port 6 nsew power bidirectional
+flabel metal1 s 0 0 480 49 0 FreeSans 340 0 0 0 VGND
+port 3 nsew ground bidirectional
+flabel locali s 31 242 65 276 0 FreeSans 340 0 0 0 B
+port 2 nsew signal input
+flabel locali s 223 316 257 350 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 415 390 449 424 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 464 449 498 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 538 449 572 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+<< properties >>
+string LEFsite unit
+string LEFclass CORE
+string FIXED_BBOX 0 0 480 666
+string GDS_FILE $PDKPATH/libs.ref/sky130_fd_sc_hs/gds/sky130_fd_sc_hs.gds
+string LEFsymmetry X Y
+string GDS_END 1245662
+string GDS_START 1240892
+<< end >>
diff --git a/mag/sky130_fd_sc_hs__xor2_1.mag b/mag/sky130_fd_sc_hs__xor2_1.mag
new file mode 100644
index 0000000..aff2350
--- /dev/null
+++ b/mag/sky130_fd_sc_hs__xor2_1.mag
@@ -0,0 +1,364 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -38 332 806 704
+<< pwell >>
+rect 17 49 754 261
+rect 0 0 768 49
+<< scpmos >>
+rect 128 392 158 592
+rect 212 392 242 592
+rect 422 368 452 592
+rect 536 368 566 592
+rect 636 368 666 592
+<< nmoslvt >>
+rect 164 125 194 235
+rect 323 125 353 235
+rect 425 87 455 235
+rect 503 87 533 235
+rect 617 87 647 235
+<< ndiff >>
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+rect 43 148 51 182
+rect 85 148 119 182
+rect 153 148 164 182
+rect 43 125 164 148
+rect 194 192 323 235
+rect 194 158 205 192
+rect 239 158 278 192
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+rect 578 99 617 133
+rect 533 87 617 99
+rect 647 133 728 235
+rect 647 99 658 133
+rect 692 99 728 133
+rect 647 87 728 99
+<< pdiff >>
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+rect 115 546 128 580
+rect 69 509 128 546
+rect 69 475 81 509
+rect 115 475 128 509
+rect 69 438 128 475
+rect 69 404 81 438
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+rect 666 463 689 497
+rect 723 463 735 497
+rect 666 414 735 463
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+rect 723 380 735 414
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+<< ndiffc >>
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+rect 278 158 312 192
+rect 380 189 414 223
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+rect 519 286 553 320
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+<< locali >>
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+rect 545 -17 607 17
+rect 641 -17 703 17
+rect 737 -17 768 17
+<< viali >>
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+rect 223 649 257 683
+rect 319 649 353 683
+rect 415 649 449 683
+rect 511 649 545 683
+rect 607 649 641 683
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+rect 319 -17 353 17
+rect 415 -17 449 17
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+rect 607 -17 641 17
+rect 703 -17 737 17
+<< metal1 >>
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+rect 65 649 127 683
+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
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+rect 0 -17 31 17
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+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 511 17
+rect 545 -17 607 17
+rect 641 -17 703 17
+rect 737 -17 768 17
+rect 0 -49 768 -17
+<< labels >>
+rlabel comment s 0 0 0 0 4 xor2_1
+flabel pwell s 0 0 768 49 0 FreeSans 200 0 0 0 VNB
+port 4 nsew ground bidirectional
+flabel nwell s 0 617 768 666 0 FreeSans 200 0 0 0 VPB
+port 5 nsew power bidirectional
+flabel metal1 s 0 617 768 666 0 FreeSans 340 0 0 0 VPWR
+port 6 nsew power bidirectional
+flabel metal1 s 0 0 768 49 0 FreeSans 340 0 0 0 VGND
+port 3 nsew ground bidirectional
+flabel locali s 31 242 65 276 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 511 316 545 350 0 FreeSans 340 0 0 0 B
+port 2 nsew signal input
+flabel locali s 511 94 545 128 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 511 168 545 202 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+<< properties >>
+string LEFsite unit
+string LEFclass CORE
+string FIXED_BBOX 0 0 768 666
+string LEFsymmetry X Y
+string GDS_END 2405310
+string GDS_START 2399018
+<< end >>
diff --git a/mag/sky130_fd_sc_hs__xor2_1.mag.original b/mag/sky130_fd_sc_hs__xor2_1.mag.original
new file mode 100644
index 0000000..053ed57
--- /dev/null
+++ b/mag/sky130_fd_sc_hs__xor2_1.mag.original
@@ -0,0 +1,367 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1622592543
+<< checkpaint >>
+rect -1298 -1309 2066 1975
+<< nwell >>
+rect -38 332 806 704
+<< pwell >>
+rect 17 49 754 261
+rect 0 0 768 49
+<< scpmos >>
+rect 128 392 158 592
+rect 212 392 242 592
+rect 422 368 452 592
+rect 536 368 566 592
+rect 636 368 666 592
+<< nmoslvt >>
+rect 164 125 194 235
+rect 323 125 353 235
+rect 425 87 455 235
+rect 503 87 533 235
+rect 617 87 647 235
+<< ndiff >>
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+rect 43 148 51 182
+rect 85 148 119 182
+rect 153 148 164 182
+rect 43 125 164 148
+rect 194 192 323 235
+rect 194 158 205 192
+rect 239 158 278 192
+rect 312 158 323 192
+rect 194 125 323 158
+rect 353 223 425 235
+rect 353 189 380 223
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+rect 578 180 617 214
+rect 533 133 617 180
+rect 533 99 544 133
+rect 578 99 617 133
+rect 533 87 617 99
+rect 647 133 728 235
+rect 647 99 658 133
+rect 692 99 728 133
+rect 647 87 728 99
+<< pdiff >>
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+rect 69 546 81 580
+rect 115 546 128 580
+rect 69 509 128 546
+rect 69 475 81 509
+rect 115 475 128 509
+rect 69 438 128 475
+rect 69 404 81 438
+rect 115 404 128 438
+rect 69 392 128 404
+rect 158 392 212 592
+rect 242 580 301 592
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+rect 242 510 301 546
+rect 242 476 255 510
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+rect 242 406 255 440
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+rect 355 580 422 592
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+rect 401 546 422 580
+rect 355 508 422 546
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+rect 666 580 735 592
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+rect 666 463 689 497
+rect 723 463 735 497
+rect 666 414 735 463
+rect 666 380 689 414
+rect 723 380 735 414
+rect 666 368 735 380
+<< ndiffc >>
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+rect 119 148 153 182
+rect 205 158 239 192
+rect 278 158 312 192
+rect 380 189 414 223
+rect 380 99 414 133
+rect 544 180 578 214
+rect 544 99 578 133
+rect 658 99 692 133
+<< pdiffc >>
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+rect 255 546 289 580
+rect 255 476 289 510
+rect 255 406 289 440
+rect 367 546 401 580
+rect 367 474 401 508
+rect 478 546 512 580
+rect 589 546 623 580
+rect 589 474 623 508
+rect 689 546 723 580
+rect 689 463 723 497
+rect 689 380 723 414
+<< poly >>
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+rect 212 592 242 618
+rect 422 592 452 618
+rect 536 592 566 618
+rect 636 592 666 618
+rect 128 377 158 392
+rect 212 377 242 392
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+rect 636 353 666 368
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+rect 257 323 353 339
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+rect 257 273 353 289
+rect 21 257 194 273
+rect 164 235 194 257
+rect 323 235 353 273
+rect 419 250 455 353
+rect 533 336 569 353
+rect 425 235 455 250
+rect 503 320 569 336
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+<< labels >>
+rlabel comment s 0 0 0 0 4 xor2_1
+flabel pwell s 0 0 768 49 0 FreeSans 200 0 0 0 VNB
+port 4 nsew ground bidirectional
+flabel nwell s 0 617 768 666 0 FreeSans 200 0 0 0 VPB
+port 5 nsew power bidirectional
+flabel metal1 s 0 617 768 666 0 FreeSans 340 0 0 0 VPWR
+port 6 nsew power bidirectional
+flabel metal1 s 0 0 768 49 0 FreeSans 340 0 0 0 VGND
+port 3 nsew ground bidirectional
+flabel locali s 31 242 65 276 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 511 316 545 350 0 FreeSans 340 0 0 0 B
+port 2 nsew signal input
+flabel locali s 511 94 545 128 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 511 168 545 202 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+<< properties >>
+string LEFsite unit
+string LEFclass CORE
+string FIXED_BBOX 0 0 768 666
+string GDS_FILE $PDKPATH/libs.ref/sky130_fd_sc_hs/gds/sky130_fd_sc_hs.gds
+string LEFsymmetry X Y
+string GDS_END 2405310
+string GDS_START 2399018
+<< end >>
diff --git a/mag/top_pll_v1.mag b/mag/top_pll_v1.mag
new file mode 100644
index 0000000..e732e11
--- /dev/null
+++ b/mag/top_pll_v1.mag
@@ -0,0 +1,592 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624402156
+<< nwell >>
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+transform -1 0 18034 0 -1 -350
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+use div_by_5 div_by_5_0
+timestamp 1624402156
+transform -1 0 13250 0 1 -3418
+box -556 0 13892 3068
+use ring_osc_buffer ring_osc_buffer_0
+timestamp 1624402156
+transform 1 0 18509 0 1 653
+box 0 0 1963 1270
+use ring_osc ring_osc_0
+timestamp 1624049879
+transform 1 0 14447 0 1 -174
+box -422 0 3882 2956
+use PFD PFD_0
+timestamp 1624049879
+transform 1 0 0 0 1 1304
+box 0 -1304 3790 1304
+use pfd_cp_interface pfd_cp_interface_0
+timestamp 1624049879
+transform 1 0 3909 0 1 -230
+box 0 0 2154 3068
+use buffer_salida buffer_salida_0
+timestamp 1624049879
+transform 1 0 20599 0 1 1292
+box -63 -1119 28718 1568
+use charge_pump charge_pump_0
+timestamp 1624049879
+transform 1 0 6183 0 1 -142
+box 0 -96 7722 2988
+use loop_filter loop_filter_0
+timestamp 1624049879
+transform 1 0 15820 0 1 -9473
+box -16462 -24206 34360 5780
+<< labels >>
+rlabel metal2 2159 858 2211 1750 1 pfd_reset
+rlabel metal1 0 1956 210 2022 1 in_ref
+rlabel metal2 3988 1876 4074 2034 1 QA
+rlabel metal2 3988 574 4074 733 1 QB
+rlabel metal2 6053 755 9497 863 1 Down
+rlabel metal2 5469 971 10410 1079 1 nDown
+rlabel metal2 5469 1529 10410 1637 1 Up
+rlabel metal2 6089 1746 9499 1854 1 nUp
+rlabel metal1 8859 2012 8963 2633 1 biasp
+rlabel metal1 11133 2158 11217 2499 1 pswitch
+rlabel metal1 11118 80 11244 311 1 nswitch
+rlabel metal2 13764 206 14377 369 1 vco_vctrl
+rlabel metal3 16756 -71 16812 -15 1 vco_D0
+rlabel metal2 18091 1189 18520 1241 1 vco_out
+rlabel metal1 18878 1176 19279 1256 1 out_first_buffer
+rlabel via1 19587 1172 19999 1256 1 out_to_div
+rlabel metal1 14816 -2673 15040 -2617 1 out_div_2
+rlabel metal1 14819 -1154 15043 -1098 1 n_out_div_2
+rlabel metal1 14281 -1166 14682 -1086 1 n_out_buffer_div_2
+rlabel metal1 14281 -2683 14682 -2603 1 out_buffer_div_2
+rlabel metal1 13806 -2677 13973 -2599 1 out_by_2
+rlabel metal1 13806 -1170 13973 -1092 1 n_out_by_2
+rlabel metal2 -279 -954 161 -878 1 div_5_Q1_shift
+rlabel metal3 -627 -882 -495 518 1 out_div_by_5
+rlabel metal2 -405 -1940 -319 -1188 1 div_5_Q1
+rlabel metal1 6175 -1110 6996 -1051 1 div_5_Q0
+rlabel metal2 9937 -2546 10013 -1824 1 div_5_nQ0
+rlabel metal1 10227 -2717 10598 -2658 1 div_5_nQ2
+rlabel metal1 6405 304 8963 408 1 iref_cp
+rlabel metal1 0 2578 3504 2816 1 vdd
+rlabel metal1 18326 -208 19370 723 1 vss
+rlabel metal4 19686 -4493 43939 -3693 1 lf_vc
+rlabel metal1 20560 1182 20839 1241 1 out_to_buffer
+rlabel metal1 48286 1072 49317 1356 1 out_to_pad
+<< end >>
diff --git a/mag/top_pll_v2.mag b/mag/top_pll_v2.mag
new file mode 100644
index 0000000..ef4fb6a
--- /dev/null
+++ b/mag/top_pll_v2.mag
@@ -0,0 +1,594 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624402156
+<< nwell >>
+rect 0 2846 20536 2860
+rect 0 2838 6183 2846
+rect 0 2608 3909 2838
+rect 3790 2062 3909 2608
+rect 6063 2012 6183 2838
+rect 13905 2752 20536 2846
+rect 13905 1955 14025 2752
+rect 18329 1955 20536 2752
+rect 18510 1923 20536 1955
+rect 20472 1290 20536 1923
+rect 49317 1290 50180 2860
+rect -3 -230 3909 546
+rect -3 -350 6063 -230
+rect 955 -370 2001 -350
+<< pwell >>
+rect 3790 706 3909 2062
+rect 2872 546 3909 706
+rect 13905 784 14901 854
+rect 18329 784 18510 1215
+rect 20472 1190 20593 1290
+rect 20456 1176 20593 1190
+rect 13905 653 18510 784
+rect 19367 653 20225 754
+rect 20472 653 20593 1176
+rect 13905 223 20593 653
+rect 13905 181 20796 223
+rect 27347 181 46785 1226
+rect 49317 769 50180 1290
+rect 49319 181 50180 769
+rect 13905 -238 50180 181
+rect 19278 -3693 50180 -238
+rect 19278 -3827 49370 -3693
+rect 20572 -4375 49370 -3827
+<< psubdiff >>
+rect 20575 24 20599 114
+rect 49259 24 49283 114
+rect 48569 -453 50169 -429
+rect 13461 -1919 13485 -1831
+rect 14493 -1919 14517 -1831
+rect 48569 -4056 50169 -4032
+<< nsubdiff >>
+rect 43 -212 67 -124
+rect 416 -212 440 -124
+rect 1252 -220 1276 -132
+rect 1625 -220 1649 -132
+rect 2420 -214 2446 -126
+rect 2795 -214 2819 -126
+<< psubdiffcont >>
+rect 20599 24 49259 114
+rect 13485 -1919 14493 -1831
+rect 48569 -4032 50169 -453
+<< nsubdiffcont >>
+rect 67 -212 416 -124
+rect 1276 -220 1625 -132
+rect 2446 -214 2795 -126
+<< poly >>
+rect 10374 2156 10680 2179
+rect 10374 2078 10395 2156
+rect 10657 2078 10680 2156
+rect 10374 2055 10680 2078
+rect 10354 385 10697 405
+rect 10354 280 10372 385
+rect 10671 280 10697 385
+rect 10354 269 10697 280
+<< polycont >>
+rect 9420 2020 9699 2114
+rect 10395 2078 10657 2156
+rect 9434 325 9696 449
+rect 10372 280 10671 385
+<< locali >>
+rect 20583 24 20599 114
+rect 49259 24 49275 114
+rect 48569 -453 50169 -437
+rect 48569 -4048 50169 -4032
+<< viali >>
+rect 10374 2156 10680 2179
+rect 9399 2114 9723 2134
+rect 9399 2020 9420 2114
+rect 9420 2020 9699 2114
+rect 9699 2020 9723 2114
+rect 10374 2078 10395 2156
+rect 10395 2078 10657 2156
+rect 10657 2078 10680 2156
+rect 10374 2055 10680 2078
+rect 9399 1999 9723 2020
+rect 9405 449 9723 468
+rect 9405 325 9434 449
+rect 9434 325 9696 449
+rect 9696 325 9723 449
+rect 9405 306 9723 325
+rect 10354 385 10697 405
+rect 10354 280 10372 385
+rect 10372 280 10671 385
+rect 10671 280 10697 385
+rect 10354 269 10697 280
+rect 20599 24 49259 114
+rect 22 -124 2852 -112
+rect 22 -212 67 -124
+rect 67 -212 416 -124
+rect 416 -126 2852 -124
+rect 416 -132 2446 -126
+rect 416 -212 1276 -132
+rect 22 -220 1276 -212
+rect 1276 -220 1625 -132
+rect 1625 -214 2446 -132
+rect 2446 -214 2795 -126
+rect 2795 -214 2852 -126
+rect 1625 -220 2852 -214
+rect 22 -232 2852 -220
+rect 13416 -1831 14548 -1810
+rect 13416 -1919 13485 -1831
+rect 13485 -1919 14493 -1831
+rect 14493 -1919 14548 -1831
+rect 13416 -1931 14548 -1919
+rect 48569 -4032 50169 -453
+<< metal1 >>
+rect 0 2824 20536 2830
+rect 0 2816 20548 2824
+rect 0 2808 6183 2816
+rect 0 2674 6294 2808
+rect 13869 2687 20548 2816
+rect 13869 2674 20472 2687
+rect 0 2578 3504 2674
+rect 3150 2150 3504 2578
+rect 5909 2095 6099 2096
+rect 4963 2090 5581 2095
+rect 3909 2034 3919 2090
+rect 4143 2034 4153 2090
+rect 4963 2034 5180 2090
+rect 5404 2034 5581 2090
+rect 4963 2029 5581 2034
+rect 5873 2091 6099 2095
+rect 5873 2035 5955 2091
+rect 6089 2035 6099 2091
+rect 5873 2030 6099 2035
+rect 5873 2029 6063 2030
+rect 0 1956 210 2022
+rect 8859 2012 8963 2633
+rect 13835 2624 20472 2674
+rect 13835 2617 14025 2624
+rect 10362 2179 10692 2185
+rect 9387 2134 9735 2140
+rect 9387 1999 9399 2134
+rect 9723 1999 9735 2134
+rect 10362 2055 10374 2179
+rect 10680 2055 10692 2179
+rect 11133 2158 11217 2499
+rect 10362 2049 10692 2055
+rect 9387 1993 9735 1999
+rect 18308 1990 20472 2624
+rect 18329 1985 20472 1990
+rect 18510 1880 20472 1985
+rect 18510 1879 19087 1880
+rect 18863 1841 19087 1879
+rect 18863 1823 19020 1841
+rect 3857 1234 3909 1468
+rect 6052 1268 6259 1468
+rect 3857 870 3976 1234
+rect 3790 830 3976 870
+rect 3585 776 3976 830
+rect 3790 736 3976 776
+rect 6183 830 6259 1268
+rect 18510 1190 18520 1242
+rect 18728 1190 18738 1242
+rect 18878 1176 19279 1256
+rect 19577 1172 19587 1256
+rect 19999 1172 20009 1256
+rect 20308 1250 20318 1253
+rect 20305 1172 20318 1250
+rect 20308 1169 20318 1172
+rect 20560 1241 20570 1253
+rect 20560 1182 20839 1241
+rect 20560 1169 20570 1182
+rect 48286 1072 49317 1356
+rect -619 518 -609 715
+rect -513 652 -503 715
+rect 6183 695 6219 830
+rect 18329 723 18510 783
+rect 18326 715 19398 723
+rect 18326 712 19370 715
+rect -513 586 210 652
+rect -513 518 -503 586
+rect 5003 574 5581 579
+rect 3909 518 3919 574
+rect 4143 518 4153 574
+rect 5003 518 5180 574
+rect 5404 518 5581 574
+rect 5003 513 5581 518
+rect 5873 574 6063 579
+rect 5873 518 5919 574
+rect 6053 518 6063 574
+rect 5873 513 6063 518
+rect 9393 468 9735 474
+rect 6405 392 8963 408
+rect 6403 320 8963 392
+rect 6405 304 8963 320
+rect 9393 306 9405 468
+rect 9723 306 9735 468
+rect 9393 300 9735 306
+rect 10342 405 10709 411
+rect 10342 269 10354 405
+rect 10697 269 10709 405
+rect 10342 263 10709 269
+rect -1 -106 499 93
+rect 1102 19 1997 124
+rect 11118 80 11244 311
+rect 1194 -106 1694 19
+rect 2372 -106 2872 55
+rect 18326 -66 19612 712
+rect 20472 677 20536 788
+rect 20443 244 20536 677
+rect 24126 244 24570 245
+rect 48566 244 49046 267
+rect 20443 114 49287 244
+rect 20443 24 20599 114
+rect 49259 24 49287 114
+rect 20443 18 49287 24
+rect -1 -112 2872 -106
+rect -1 -232 22 -112
+rect 2852 -232 2872 -112
+rect -1 -238 2872 -232
+rect -1 -407 499 -238
+rect 1194 -370 1694 -238
+rect 1102 -514 1997 -370
+rect 2372 -445 2872 -238
+rect 3909 -380 6063 -200
+rect 13905 -208 19612 -66
+rect -627 -1095 -617 -882
+rect -505 -1095 -495 -882
+rect 6175 -1110 6996 -1051
+rect 13787 -1223 13797 -1056
+rect 13962 -1092 13972 -1056
+rect 13962 -1170 13973 -1092
+rect 14281 -1166 14682 -1086
+rect 14819 -1154 15043 -1098
+rect 13962 -1223 13972 -1170
+rect 13580 -1706 13842 -1507
+rect 13580 -1725 14356 -1706
+rect 19367 -1720 19612 -208
+rect 48566 -441 49046 18
+rect 13288 -1896 13289 -1731
+rect 13768 -1804 14356 -1725
+rect 13404 -1810 14560 -1804
+rect 13404 -1931 13416 -1810
+rect 14548 -1931 14560 -1810
+rect 13404 -1937 14560 -1931
+rect 13768 -2069 14356 -1937
+rect 19278 -1964 19612 -1720
+rect 48563 -453 50175 -441
+rect 13768 -2215 13842 -2069
+rect 10227 -2717 10598 -2658
+rect 13760 -2695 13770 -2498
+rect 13951 -2599 13961 -2498
+rect 13951 -2677 13973 -2599
+rect 13951 -2695 13961 -2677
+rect 14281 -2683 14682 -2603
+rect 14816 -2673 15040 -2617
+rect 48563 -4032 48569 -453
+rect 50169 -4032 50175 -453
+rect 48563 -5101 50175 -4032
+rect 7710 -20126 8742 -20046
+<< via1 >>
+rect 3919 2034 4143 2090
+rect 5180 2034 5404 2090
+rect 5955 2035 6089 2091
+rect 9420 2020 9699 2114
+rect 10395 2078 10657 2156
+rect 18520 1190 18728 1242
+rect 19587 1172 19999 1256
+rect 20318 1169 20560 1253
+rect -609 518 -513 715
+rect 3919 518 4143 574
+rect 5180 518 5404 574
+rect 5919 518 6053 574
+rect 9434 325 9696 449
+rect 10372 280 10671 385
+rect -617 -1095 -505 -882
+rect 13797 -1223 13962 -1056
+rect 13770 -2695 13951 -2498
+<< metal2 >>
+rect 10395 2156 10657 2166
+rect 9420 2114 9699 2124
+rect 3919 2090 4143 2100
+rect 3919 2024 4143 2034
+rect 5180 2090 5404 2100
+rect 5180 2024 5404 2034
+rect 5955 2091 6089 2101
+rect 5955 2025 6089 2035
+rect 10395 2068 10657 2078
+rect 3988 1928 4074 2024
+rect 9420 2010 9699 2020
+rect 3738 1876 4074 1928
+rect 5955 1831 9647 1854
+rect 5955 1812 9499 1831
+rect 6089 1775 9499 1812
+rect 9633 1775 9647 1831
+rect 6089 1756 9647 1775
+rect 2159 858 2211 1750
+rect 5955 1746 9647 1756
+rect 5232 1611 10645 1637
+rect 5232 1555 5245 1611
+rect 5469 1609 10645 1611
+rect 5469 1555 10410 1609
+rect 5232 1553 10410 1555
+rect 10634 1553 10645 1609
+rect 5232 1529 10645 1553
+rect 19587 1256 19999 1266
+rect 18520 1242 18728 1252
+rect 18091 1190 18520 1241
+rect 18091 1189 18728 1190
+rect 18520 1180 18728 1189
+rect 19587 1162 19999 1172
+rect 20318 1253 20560 1263
+rect 20318 1159 20560 1169
+rect 5232 1055 10645 1079
+rect 5232 1053 10410 1055
+rect 5232 997 5245 1053
+rect 5469 999 10410 1053
+rect 10634 999 10645 1055
+rect 5469 997 10645 999
+rect 5232 971 10645 997
+rect 13187 980 13690 990
+rect 5919 853 9631 863
+rect 6053 797 9497 853
+rect 5919 755 9631 797
+rect 3988 732 4074 733
+rect -609 715 -513 725
+rect 3685 680 4074 732
+rect 3988 584 4074 680
+rect -609 508 -513 518
+rect 3919 574 4143 584
+rect 3919 508 4143 518
+rect 5180 574 5404 584
+rect 5180 508 5404 518
+rect 5919 574 6053 584
+rect 5919 508 6053 518
+rect 9434 449 9696 459
+rect 9434 315 9696 325
+rect 10372 385 10671 395
+rect 13187 381 13690 391
+rect 10372 270 10671 280
+rect 13764 206 14377 369
+rect 14214 25 14377 206
+rect -617 -882 -505 -872
+rect -279 -954 161 -878
+rect -617 -1105 -505 -1095
+rect 13797 -1056 13962 -1046
+rect -405 -1940 -319 -1188
+rect 13797 -1233 13962 -1223
+rect 9937 -2546 10013 -1824
+rect 13770 -2498 13951 -2488
+rect 13770 -2705 13951 -2695
+<< via2 >>
+rect 5180 2034 5404 2090
+rect 5955 2035 6089 2091
+rect 9491 2043 9625 2099
+rect 10412 2078 10636 2134
+rect 5955 1756 6089 1812
+rect 9499 1775 9633 1831
+rect 5245 1555 5469 1611
+rect 10410 1553 10634 1609
+rect 19587 1172 19999 1256
+rect 5245 997 5469 1053
+rect 10410 999 10634 1055
+rect 5919 797 6053 853
+rect 9497 797 9631 853
+rect -609 518 -513 715
+rect 5180 518 5404 574
+rect 5919 518 6053 574
+rect 9497 359 9631 415
+rect 13187 391 13690 980
+rect 10412 306 10636 362
+rect -617 -1095 -505 -882
+rect 13797 -1223 13962 -1056
+rect 13770 -2695 13951 -2498
+<< metal3 >>
+rect 10402 2134 10646 2139
+rect 9470 2099 9672 2114
+rect 5170 2090 5414 2095
+rect 5170 2034 5180 2090
+rect 5404 2034 5414 2090
+rect 5170 2029 5414 2034
+rect 5945 2091 6099 2096
+rect 5945 2035 5955 2091
+rect 6089 2035 6099 2091
+rect 5945 2030 6099 2035
+rect 9470 2043 9491 2099
+rect 9625 2043 9672 2099
+rect 10402 2078 10412 2134
+rect 10636 2078 10646 2134
+rect 10402 2073 10646 2078
+rect 9470 2034 9672 2043
+rect 5262 1616 5322 2029
+rect 5992 1817 6052 2030
+rect 9525 1836 9585 2034
+rect 9489 1831 9643 1836
+rect 5945 1812 6099 1817
+rect 5945 1756 5955 1812
+rect 6089 1756 6099 1812
+rect 9489 1775 9499 1831
+rect 9633 1775 9643 1831
+rect 9489 1770 9643 1775
+rect 9525 1769 9585 1770
+rect 5945 1751 6099 1756
+rect 5992 1742 6052 1751
+rect 5235 1611 5479 1616
+rect 10494 1614 10554 2073
+rect 5235 1555 5245 1611
+rect 5469 1555 5479 1611
+rect 5235 1550 5479 1555
+rect 10400 1609 10644 1614
+rect 10400 1553 10410 1609
+rect 10634 1553 10644 1609
+rect 10400 1548 10644 1553
+rect 19577 1256 20009 1261
+rect 19577 1172 19587 1256
+rect 19999 1172 20009 1256
+rect 19577 1167 20009 1172
+rect 5235 1053 5479 1058
+rect 5235 997 5245 1053
+rect 5469 997 5479 1053
+rect 5235 992 5479 997
+rect 10400 1055 10644 1060
+rect 10400 999 10410 1055
+rect 10634 999 10644 1055
+rect 10400 994 10644 999
+rect -627 715 -495 725
+rect -627 518 -609 715
+rect -513 518 -495 715
+rect 5262 579 5322 992
+rect 5956 858 6016 867
+rect 5909 853 6063 858
+rect 5909 797 5919 853
+rect 6053 797 6063 853
+rect 5909 792 6063 797
+rect 9487 853 9641 858
+rect 9487 797 9497 853
+rect 9631 797 9641 853
+rect 9487 792 9641 797
+rect 5956 579 6016 792
+rect -627 -882 -495 518
+rect 5170 574 5414 579
+rect 5170 518 5180 574
+rect 5404 518 5414 574
+rect 5170 513 5414 518
+rect 5909 574 6063 579
+rect 5909 518 5919 574
+rect 6053 518 6063 574
+rect 5909 513 6063 518
+rect 9534 420 9594 792
+rect 9487 415 9641 420
+rect 9487 359 9497 415
+rect 9631 359 9641 415
+rect 10494 367 10554 994
+rect 13177 980 13700 985
+rect 13177 391 13187 980
+rect 13690 391 13700 980
+rect 13177 386 13700 391
+rect 9487 354 9641 359
+rect 10402 362 10646 367
+rect 10402 306 10412 362
+rect 10636 306 10646 362
+rect 10402 301 10646 306
+rect -627 -1095 -617 -882
+rect -505 -1095 -495 -882
+rect -627 -1100 -495 -1095
+rect 13224 -3781 13580 386
+rect 16756 -71 16812 -15
+rect 13787 -1053 13972 -1051
+rect 13785 -1259 13795 -1053
+rect 13965 -1259 13975 -1053
+rect 18944 -1835 19058 -1290
+rect 18937 -1939 18947 -1835
+rect 19055 -1939 19065 -1835
+rect 19758 -1841 19952 1167
+rect 19758 -1930 19773 -1841
+rect 19940 -1930 19952 -1841
+rect 13760 -2498 13961 -2493
+rect 13760 -2695 13770 -2498
+rect 13951 -2695 13961 -2498
+rect 13760 -2700 13961 -2695
+rect 18944 -2750 19058 -1939
+rect 19758 -1964 19952 -1930
+rect 13067 -4358 13077 -3781
+rect 13764 -4358 13774 -3781
+<< via3 >>
+rect 13795 -1056 13965 -1053
+rect 13795 -1223 13797 -1056
+rect 13797 -1223 13962 -1056
+rect 13962 -1223 13965 -1056
+rect 13795 -1259 13965 -1223
+rect 18947 -1939 19055 -1835
+rect 19773 -1930 19940 -1841
+rect 13770 -2695 13951 -2498
+rect 13077 -4358 13764 -3781
+<< metal4 >>
+rect 638 -1053 13971 -1048
+rect 638 -1259 13795 -1053
+rect 13965 -1259 13971 -1053
+rect 638 -1271 13971 -1259
+rect 18944 -1835 19952 -1831
+rect 18944 -1939 18947 -1835
+rect 19055 -1841 19952 -1835
+rect 19055 -1930 19773 -1841
+rect 19940 -1930 19952 -1841
+rect 19055 -1939 19952 -1930
+rect 18944 -1943 19952 -1939
+rect 638 -2498 13971 -2481
+rect 638 -2695 13770 -2498
+rect 13951 -2695 13971 -2498
+rect 638 -2704 13971 -2695
+rect 13076 -3781 13765 -3780
+rect 13076 -4358 13077 -3781
+rect 13764 -4358 13765 -3781
+rect 13076 -4359 13765 -4358
+rect 19686 -4493 43939 -3693
+use charge_pump charge_pump_0
+timestamp 1624049879
+transform 1 0 6183 0 1 -142
+box 0 -96 7722 2988
+use buffer_salida buffer_salida_0
+timestamp 1624049879
+transform 1 0 20599 0 1 1292
+box -63 -1119 28718 1568
+use pfd_cp_interface pfd_cp_interface_0
+timestamp 1624049879
+transform 1 0 3909 0 1 -230
+box 0 0 2154 3068
+use PFD PFD_0
+timestamp 1624049879
+transform 1 0 0 0 1 1304
+box 0 -1304 3790 1304
+use ring_osc ring_osc_0
+timestamp 1624049879
+transform 1 0 14447 0 1 -174
+box -422 0 3882 2956
+use ring_osc_buffer ring_osc_buffer_0
+timestamp 1624402156
+transform 1 0 18509 0 1 653
+box 0 0 1963 1270
+use div_by_5 div_by_5_0
+timestamp 1624402156
+transform -1 0 13250 0 1 -3418
+box -556 0 13892 3068
+use div_by_2 div_by_2_0
+timestamp 1624402156
+transform -1 0 18034 0 -1 -350
+box -1244 0 4228 3068
+use loop_filter_v2 loop_filter_v2_0
+timestamp 1624053471
+transform 1 0 15820 0 1 -9473
+box -16462 -24206 34360 5780
+<< labels >>
+rlabel metal2 2159 858 2211 1750 1 pfd_reset
+rlabel metal1 0 1956 210 2022 1 in_ref
+rlabel metal2 3988 1876 4074 2034 1 QA
+rlabel metal2 3988 574 4074 733 1 QB
+rlabel metal2 6053 755 9497 863 1 Down
+rlabel metal2 5469 971 10410 1079 1 nDown
+rlabel metal2 5469 1529 10410 1637 1 Up
+rlabel metal2 6089 1746 9499 1854 1 nUp
+rlabel metal1 8859 2012 8963 2633 1 biasp
+rlabel metal1 11133 2158 11217 2499 1 pswitch
+rlabel metal1 11118 80 11244 311 1 nswitch
+rlabel metal2 13764 206 14377 369 1 vco_vctrl
+rlabel metal2 18091 1189 18520 1241 1 vco_out
+rlabel metal1 18878 1176 19279 1256 1 out_first_buffer
+rlabel via1 19587 1172 19999 1256 1 out_to_div
+rlabel metal1 14816 -2673 15040 -2617 1 out_div_2
+rlabel metal1 14819 -1154 15043 -1098 1 n_out_div_2
+rlabel metal1 14281 -1166 14682 -1086 1 n_out_buffer_div_2
+rlabel metal1 14281 -2683 14682 -2603 1 out_buffer_div_2
+rlabel metal1 13806 -2677 13973 -2599 1 out_by_2
+rlabel metal1 13806 -1170 13973 -1092 1 n_out_by_2
+rlabel metal2 -279 -954 161 -878 1 div_5_Q1_shift
+rlabel metal3 -627 -882 -495 518 1 out_div_by_5
+rlabel metal2 -405 -1940 -319 -1188 1 div_5_Q1
+rlabel metal1 6175 -1110 6996 -1051 1 div_5_Q0
+rlabel metal2 9937 -2546 10013 -1824 1 div_5_nQ0
+rlabel metal1 10227 -2717 10598 -2658 1 div_5_nQ2
+rlabel metal1 6405 304 8963 408 1 iref_cp
+rlabel metal1 0 2578 3504 2816 1 vdd
+rlabel metal1 18326 -208 19370 723 1 vss
+rlabel metal4 19686 -4493 43939 -3693 1 lf_vc
+rlabel metal1 20560 1182 20839 1241 1 out_to_buffer
+rlabel metal1 48286 1072 49317 1356 1 out_to_pad
+rlabel metal1 7710 -20126 8742 -20046 1 DO_cap
+rlabel metal3 16756 -71 16812 -15 1 D0_vco
+<< end >>
diff --git a/mag/trans_gate.mag b/mag/trans_gate.mag
new file mode 100644
index 0000000..96c6ca1
--- /dev/null
+++ b/mag/trans_gate.mag
@@ -0,0 +1,132 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624049879
+<< nwell >>
+rect -53 635 569 723
+<< pwell >>
+rect -53 -811 569 -723
+<< psubdiff >>
+rect 55 -775 79 -741
+rect 437 -775 461 -741
+<< nsubdiff >>
+rect 55 653 79 687
+rect 437 653 461 687
+<< psubdiffcont >>
+rect 79 -775 437 -741
+<< nsubdiffcont >>
+rect 79 653 437 687
+<< poly >>
+rect 147 69 371 135
+rect 279 31 371 69
+rect 279 -37 291 31
+rect 359 -37 371 31
+rect 279 -53 371 -37
+rect 145 -69 237 -53
+rect 145 -137 157 -69
+rect 225 -137 237 -69
+rect 145 -171 237 -137
+rect 145 -237 369 -171
+<< polycont >>
+rect 291 -37 359 31
+rect 157 -137 225 -69
+<< locali >>
+rect 279 31 371 47
+rect 279 -37 291 31
+rect 359 -37 371 31
+rect 279 -53 371 -37
+rect 145 -69 237 -53
+rect 145 -137 157 -69
+rect 225 -137 237 -69
+rect 145 -153 237 -137
+<< viali >>
+rect -17 653 79 687
+rect 79 653 437 687
+rect 437 653 533 687
+rect -17 565 533 599
+rect 291 -37 359 31
+rect 157 -137 225 -69
+rect -17 -687 533 -653
+rect -17 -775 79 -741
+rect 79 -775 437 -741
+rect 437 -775 533 -741
+<< metal1 >>
+rect -53 687 569 693
+rect -53 653 -17 687
+rect 533 653 569 687
+rect -53 599 165 653
+rect 217 599 569 653
+rect -53 565 -17 599
+rect 533 565 569 599
+rect -53 559 165 565
+rect 217 559 569 565
+rect 45 462 329 508
+rect 45 404 137 462
+rect 283 404 329 462
+rect 45 -171 97 404
+rect 425 183 477 416
+rect 187 120 233 178
+rect 419 120 477 183
+rect 187 74 477 120
+rect 279 -53 291 37
+rect 359 -53 371 37
+rect 145 -143 157 -53
+rect 225 -143 237 -53
+rect 45 -217 329 -171
+rect 45 -341 97 -217
+rect 283 -263 329 -217
+rect 45 -513 91 -341
+rect 419 -343 477 74
+rect 425 -455 477 -343
+rect 419 -501 477 -455
+rect 187 -559 233 -513
+rect 379 -559 477 -501
+rect 187 -605 477 -559
+rect -53 -653 569 -647
+rect -53 -687 -17 -653
+rect 533 -687 569 -653
+rect -53 -741 299 -687
+rect 351 -741 569 -687
+rect -53 -775 -17 -741
+rect 533 -775 569 -741
+rect -53 -781 569 -775
+<< via1 >>
+rect 165 653 217 663
+rect 165 599 217 653
+rect 165 565 217 599
+rect 165 559 217 565
+rect 291 31 359 37
+rect 291 -37 359 31
+rect 291 -53 359 -37
+rect 157 -69 225 -53
+rect 157 -137 225 -69
+rect 157 -143 225 -137
+rect 299 -687 351 -653
+rect 299 -741 351 -687
+rect 299 -757 351 -741
+<< metal2 >>
+rect 157 663 225 673
+rect 157 559 165 663
+rect 217 559 225 663
+rect 157 -53 225 559
+rect 157 -153 225 -143
+rect 291 37 359 47
+rect 291 -653 359 -53
+rect 291 -757 299 -653
+rect 351 -757 359 -653
+rect 291 -766 359 -757
+rect 299 -767 351 -766
+use sky130_fd_pr__pfet_01v8_4798MH sky130_fd_pr__pfet_01v8_4798MH_0
+timestamp 1624049879
+transform 1 0 258 0 1 291
+box -311 -344 311 344
+use sky130_fd_pr__nfet_01v8_BHR94T sky130_fd_pr__nfet_01v8_BHR94T_0
+timestamp 1624049879
+transform 1 0 258 0 1 -388
+box -311 -335 311 335
+<< labels >>
+rlabel metal1 217 599 569 653 1 vdd
+rlabel metal1 -53 -741 299 -687 1 vss
+rlabel space 419 -605 477 416 1 out
+rlabel space 45 -513 97 508 1 in
+<< end >>
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index ebc5e1b..6b6fd30 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,33 +1,415 @@
magic
tech sky130A
magscale 1 2
-timestamp 1620395479
-<< mvpsubdiff >>
-rect 345740 628255 345764 629032
-rect 371078 628255 371102 629032
-<< mvpsubdiffcont >>
-rect 345764 628255 371078 629032
+timestamp 1624402156
+<< nwell >>
+rect 14730 660108 64962 661110
+rect 14730 660034 64841 660108
+rect 82888 660083 133067 660649
+rect 83408 660052 119178 660083
+rect 14730 659150 14782 660034
+rect 28401 659941 28758 659982
+rect 83408 659846 112858 660052
+rect 124441 660015 133067 660083
+<< pwell >>
+rect 371257 636863 371689 637515
+<< nsubdiff >>
+rect 14777 660157 14801 660354
+rect 21672 660157 21696 660354
+rect 23064 660169 23088 660375
+rect 28678 660169 28702 660375
+rect 28954 660172 28978 660367
+rect 34940 660172 34964 660367
+rect 35514 660153 35538 660369
+rect 63779 660153 63803 660369
+rect 84063 660216 84087 660457
+rect 112239 660216 112263 660457
+rect 112659 660076 112683 660241
+rect 119084 660076 119108 660241
+rect 119365 660188 119389 660416
+rect 124370 660188 124394 660416
+rect 124754 660180 124778 660424
+rect 132540 660180 132564 660424
+<< nsubdiffcont >>
+rect 14801 660157 21672 660354
+rect 23088 660169 28678 660375
+rect 28978 660172 34940 660367
+rect 35538 660153 63779 660369
+rect 84087 660216 112239 660457
+rect 112683 660076 119084 660241
+rect 119389 660188 124370 660416
+rect 124778 660180 132540 660424
<< locali >>
-rect 345748 628255 345764 629032
-rect 371078 628255 371094 629032
+rect 14785 660157 14801 660354
+rect 21672 660157 21688 660354
+rect 23072 660169 23088 660375
+rect 28678 660169 28694 660375
+rect 28962 660172 28978 660367
+rect 34940 660172 34956 660367
+rect 35522 660153 35538 660369
+rect 63779 660153 63795 660369
+rect 84071 660216 84087 660457
+rect 112239 660216 112255 660457
+rect 112667 660076 112683 660241
+rect 119084 660076 119100 660241
+rect 119373 660188 119389 660416
+rect 124370 660188 124386 660416
<< viali >>
-rect 357593 628300 359298 629000
+rect 14801 660157 21672 660354
+rect 23088 660169 28678 660375
+rect 28978 660172 34940 660367
+rect 35538 660153 63779 660369
+rect 84087 660216 112239 660457
+rect 112683 660076 119084 660241
+rect 119389 660188 124370 660416
+rect 124762 660180 124778 660424
+rect 124778 660180 132540 660424
+rect 132540 660180 132556 660424
<< metal1 >>
-rect 357470 629399 359442 629457
-rect 357470 628057 357538 629399
-rect 359388 628057 359442 629399
-rect 357470 627990 359442 628057
+rect 202956 687835 202966 688225
+rect 206549 687835 206559 688225
+rect 207113 687795 207123 688222
+rect 210595 687795 210605 688222
+rect 211166 687819 211176 688246
+rect 214648 687819 214658 688246
+rect 223050 688060 223060 688186
+rect 223016 687894 223060 688060
+rect 223050 687834 223060 687894
+rect 226864 688060 226874 688186
+rect 226864 687894 226915 688060
+rect 226864 687834 226874 687894
+rect 227267 687846 227277 688273
+rect 230749 687846 230759 688273
+rect 231320 687855 231330 688282
+rect 234802 687855 234812 688282
+rect 235302 687865 235312 688292
+rect 238784 687865 238794 688292
+rect 239323 687860 239333 688287
+rect 242805 687860 242815 688287
+rect 243362 687858 243372 688285
+rect 246844 687858 246854 688285
+rect 202763 685044 202773 685354
+rect 247145 685044 247155 685354
+rect 83775 660472 112339 660489
+rect 23004 660431 64063 660453
+rect 23004 660397 23042 660431
+rect 21700 660392 23042 660397
+rect 14751 660388 23042 660392
+rect 14751 660354 14834 660388
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+rect 14751 660121 14834 660157
+rect 14751 660101 23042 660121
+rect 64025 660101 64063 660431
+rect 14751 660070 64063 660101
+rect 14751 660012 21718 660070
+rect 23004 660030 64063 660070
+rect 23037 660018 28912 660030
+rect 14751 659692 14783 660012
+rect 83746 659999 83756 660472
+rect 112324 660409 112339 660472
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+rect 112324 660408 112754 660409
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+rect 112324 660010 112657 660332
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+rect 64423 658604 66170 658984
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+rect 64423 657999 66170 658320
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+rect 68582 658984 68592 659137
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+rect 79846 658972 83253 658973
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+rect 79838 657985 79848 658972
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+rect 206575 658728 206585 658758
+rect 206248 658662 206585 658728
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+rect 34989 656786 35045 657163
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+rect 35066 656680 35076 656786
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+rect 152333 657778 157347 658062
+rect 152333 657395 156268 657778
+rect 149997 657379 156268 657395
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+rect 112802 657160 112812 657243
+rect 112685 656533 112741 657160
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+rect 197704 657001 197714 657125
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+rect 112626 656348 112636 656533
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+rect 156207 656248 156786 656708
+rect 186130 656623 186140 656702
+rect 186225 656623 186235 656702
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+rect 186119 656316 186129 656414
+rect 186241 656316 186251 656414
+rect 12125 655528 13406 655533
+rect 12125 655200 14468 655528
+rect 133382 655200 135242 655528
+rect 12125 652870 13406 655200
+rect 134093 653281 135239 655200
+rect 207475 654986 208245 655013
+rect 206694 654658 208245 654986
+rect 12125 651670 15784 652870
+rect 132088 652146 135239 653281
+rect 207475 652403 208245 654658
+rect 132558 652135 135239 652146
+rect 12125 651669 15583 651670
+rect 12125 651650 13406 651669
+rect 205405 651403 208245 652403
+rect 205405 651383 207885 651403
+rect 124847 637057 124857 637281
+rect 125442 637057 125452 637281
<< via1 >>
-rect 357538 629000 359388 629399
-rect 357538 628300 357593 629000
-rect 357593 628300 359298 629000
-rect 359298 628300 359388 629000
-rect 357538 628057 359388 628300
+rect 202966 687835 206549 688225
+rect 207123 687795 210595 688222
+rect 211176 687819 214648 688246
+rect 223060 687834 226864 688186
+rect 227277 687846 230749 688273
+rect 231330 687855 234802 688282
+rect 235312 687865 238784 688292
+rect 239333 687860 242805 688287
+rect 243372 687858 246844 688285
+rect 202773 685044 247145 685354
+rect 23042 660388 64025 660431
+rect 14834 660375 64025 660388
+rect 14834 660354 23088 660375
+rect 14834 660157 21672 660354
+rect 21672 660169 23088 660354
+rect 23088 660169 28678 660375
+rect 28678 660369 64025 660375
+rect 28678 660367 35538 660369
+rect 28678 660172 28978 660367
+rect 28978 660172 34940 660367
+rect 34940 660172 35538 660367
+rect 28678 660169 35538 660172
+rect 21672 660157 35538 660169
+rect 14834 660153 35538 660157
+rect 35538 660153 63779 660369
+rect 63779 660153 64025 660369
+rect 14834 660121 64025 660153
+rect 23042 660101 64025 660121
+rect 83756 660457 112324 660472
+rect 83756 660216 84087 660457
+rect 84087 660216 112239 660457
+rect 112239 660216 112324 660457
+rect 120252 660424 133038 660445
+rect 120252 660416 124762 660424
+rect 83756 659999 112324 660216
+rect 112657 660241 119074 660332
+rect 112657 660076 112683 660241
+rect 112683 660076 119074 660241
+rect 120252 660188 124370 660416
+rect 124370 660188 124762 660416
+rect 120252 660180 124762 660188
+rect 124762 660180 132556 660424
+rect 132556 660180 133038 660424
+rect 120252 660106 133038 660180
+rect 112657 659953 119074 660076
+rect 157083 659472 198006 659901
+rect 13065 659103 14624 659376
+rect 133081 659175 133354 659303
+rect 66170 657870 68582 659137
+rect 79848 657985 82308 658972
+rect 206585 658630 206858 658758
+rect 21160 657532 23640 657665
+rect 34979 657163 35060 657242
+rect 34974 656680 35066 656786
+rect 124336 657529 126700 657669
+rect 149997 657395 152333 658524
+rect 112670 657160 112802 657243
+rect 197714 657001 199942 657125
+rect 112636 656348 112797 656533
+rect 186140 656623 186225 656702
+rect 186129 656316 186241 656414
+rect 124857 637057 125442 637281
<< metal2 >>
-rect 357470 629399 359442 629457
-rect 357470 628057 357538 629399
-rect 359388 628057 359442 629399
-rect 357470 627990 359442 628057
+rect 211169 688703 214642 688713
+rect 207123 688623 210596 688633
+rect 198295 688226 199269 688229
+rect 202966 688226 206549 688235
+rect 198295 688225 206549 688226
+rect 198295 688219 202966 688225
+rect 199269 687835 202966 688219
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+rect 198295 687825 206549 687830
+rect 198295 687820 199269 687825
+rect 235312 688693 238785 688703
+rect 231330 688683 234803 688693
+rect 227277 688664 230750 688674
+rect 214642 688246 214648 688256
+rect 211169 687865 211176 687875
+rect 223060 688186 226864 688196
+rect 223060 687824 226864 687834
+rect 235312 687855 238785 687865
+rect 239333 688688 242806 688698
+rect 231330 687845 234803 687855
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+rect 243372 688686 246845 688696
+rect 243372 687848 246845 687858
+rect 227277 687826 230750 687836
+rect 211176 687809 214648 687819
+rect 207123 687785 210596 687795
+rect 202773 685354 247145 685364
+rect 202773 685034 202780 685044
+rect 247142 685034 247145 685044
+rect 202780 684701 247142 684711
+rect 83765 660846 124085 660856
+rect 23042 660657 64025 660667
+rect 14834 660388 23042 660398
+rect 14834 660111 23042 660121
+rect 23042 660091 64025 660101
+rect 83756 660472 83765 660482
+rect 157083 660502 197708 660512
+rect 124085 660445 133038 660455
+rect 112324 659999 112657 660179
+rect 83756 659989 112324 659999
+rect 119074 660106 120252 660179
+rect 119074 660096 133038 660106
+rect 119074 659999 120418 660096
+rect 112657 659943 119074 659953
+rect 197708 659901 198006 659911
+rect 2509 659760 14155 659826
+rect 2509 658727 2671 659760
+rect 5073 659386 14155 659760
+rect 133210 659558 140004 659630
+rect 5073 659376 14624 659386
+rect 5073 659103 13065 659376
+rect 133210 659313 137580 659558
+rect 133081 659303 137580 659313
+rect 133354 659175 137580 659303
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+rect 5073 659093 14624 659103
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+rect 5073 658727 14155 659093
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+rect 79848 658972 82308 658982
+rect 133210 658887 137580 659165
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+rect 157083 659462 198006 659472
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+rect 206714 659015 212383 659085
+rect 206714 658768 209986 659015
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+rect 79848 657975 82308 657985
+rect 149997 658524 152333 658534
+rect 66170 657860 68582 657870
+rect 21160 657690 23631 657700
+rect 23631 657665 23640 657675
+rect 21160 657522 23640 657532
+rect 124336 657669 126700 657679
+rect 124336 657519 126700 657529
+rect 206714 658377 209986 658620
+rect 212293 658377 212383 659015
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+rect 149997 657385 152333 657395
+rect 34979 657242 35060 657252
+rect 32682 657177 34979 657233
+rect 34979 657153 35060 657163
+rect 112670 657243 112802 657253
+rect 112802 657177 115172 657233
+rect 112670 657150 112802 657160
+rect 197714 657125 199942 657135
+rect 73065 657028 74069 657038
+rect 34974 656786 35066 656796
+rect 35452 656766 73065 656798
+rect 35066 656710 73065 656766
+rect 34974 656670 35066 656680
+rect 35452 656678 73065 656710
+rect 197714 656991 199942 657001
+rect 186140 656702 186225 656712
+rect 186225 656635 188420 656691
+rect 186140 656613 186225 656623
+rect 112636 656533 112797 656543
+rect 74069 656363 112636 656488
+rect 112636 656338 112797 656348
+rect 152623 656403 186037 656431
+rect 152623 656300 152633 656403
+rect 73065 656212 74069 656222
+rect 153791 656393 186037 656403
+rect 186129 656414 186241 656424
+rect 153791 656337 186129 656393
+rect 153791 656300 186037 656337
+rect 186129 656306 186241 656316
+rect 152633 656124 153791 656134
+rect 144160 637403 145498 637413
+rect 125227 637291 144160 637369
+rect 124857 637281 144160 637291
+rect 125442 637057 144160 637281
+rect 124857 637047 144160 637057
+rect 125227 636972 144160 637047
+rect 145498 636972 145544 637369
+rect 144160 636927 145498 636937
+rect 368681 635516 368816 635526
+rect 368681 635411 368816 635421
+rect 368680 633678 368815 633688
+rect 368680 633573 368815 633583
+rect 152624 510676 153820 510686
+rect 1323 510540 152624 510561
+rect 1323 510538 73012 510540
+rect 1323 510236 1358 510538
+rect 2171 510260 73012 510538
+rect 74070 510260 152624 510540
+rect 2171 510236 152624 510260
+rect 1323 510212 152624 510236
+rect 153820 510212 153853 510561
+rect 152624 510195 153820 510205
+rect 1326 467320 145524 467339
+rect 1326 467316 144170 467320
+rect 1326 467014 1361 467316
+rect 2174 467014 144170 467316
+rect 1326 467013 144170 467014
+rect 145472 467013 145524 467320
+rect 1326 466990 145524 467013
rect 524 -800 636 480
rect 1706 -800 1818 480
rect 2888 -800 3000 480
@@ -523,156 +905,515 @@
rect 582068 -800 582180 480
rect 583250 -800 583362 480
<< via2 >>
-rect 357538 628057 359388 629399
+rect 198295 687830 199269 688219
+rect 207123 688222 210596 688623
+rect 207123 687795 210595 688222
+rect 210595 687795 210596 688222
+rect 211169 688246 214642 688703
+rect 227277 688273 230750 688664
+rect 211169 687875 211176 688246
+rect 211176 687875 214642 688246
+rect 223060 687834 226864 688186
+rect 227277 687846 230749 688273
+rect 230749 687846 230750 688273
+rect 227277 687836 230750 687846
+rect 231330 688282 234803 688683
+rect 231330 687855 234802 688282
+rect 234802 687855 234803 688282
+rect 235312 688292 238785 688693
+rect 235312 687865 238784 688292
+rect 238784 687865 238785 688292
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<< metal3 >>
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rect -800 295420 480 295532
rect -800 294238 480 294350
@@ -692,18 +1433,25 @@
rect -800 248852 480 248964
rect -800 247670 480 247782
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-rect 582340 235230 584800 240030
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rect -800 214888 1660 219688
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rect -800 172888 1660 177688
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rect -800 124776 480 124888
rect -800 123594 480 123706
rect -800 122412 480 122524
@@ -765,180 +1513,1452 @@
rect -800 1544 480 1656
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<< via3 >>
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<< metal4 >>
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<< via4 >>
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<< metal5 >>
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<< comment >>
rect -100 704000 584100 704100
rect -100 0 0 704000
rect 584000 0 584100 704000
rect -100 -100 584100 0
-use user_analog_proj_example user_analog_proj_example_0
-timestamp 1620310959
-transform 1 0 345668 0 -1 627114
-box -59 -22 25476 8324
+use mimcap_decoup_1x5 mimcap_decoup_1x5_0
+array 0 0 34500 0 2 6522
+timestamp 1624376995
+transform 1 0 38481 0 1 560871
+box 0 -159 34500 6363
+use top_pll_v1 top_pll_v1_0
+timestamp 1624402156
+transform 1 0 14782 0 1 657248
+box -642 -33679 50180 2860
+use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_0
+array 0 0 6724 0 8 6522
+timestamp 1624129585
+transform 1 0 74005 0 1 616157
+box -3351 -3261 3373 3261
+use top_pll_v2 *top_pll_v2_0
+timestamp 1624402156
+transform -1 0 133068 0 1 657248
+box -642 -33679 50180 2860
+use mimcap_decoup_1x5 mimcap_decoup_1x5_1
+array 0 0 34500 0 2 6522
+timestamp 1624376995
+transform 1 0 126717 0 1 559996
+box 0 -159 34500 6363
+use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_1
+array 0 0 6724 0 8 6522
+timestamp 1624129585
+transform 1 0 144463 0 1 616442
+box -3351 -3261 3373 3261
+use top_pll_v1 *top_pll_v1_1
+timestamp 1624402156
+transform -1 0 206380 0 1 656706
+box -642 -33679 50180 2860
+use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_2
+array 0 0 6724 0 6 6522
+timestamp 1624129585
+transform 1 0 220679 0 1 616773
+box -3351 -3261 3373 3261
+use mimcap_decoup_1x5 mimcap_decoup_1x5_2
+array 0 0 34500 0 2 6522
+timestamp 1624376995
+transform 1 0 197202 0 1 560156
+box 0 -159 34500 6363
+use bias bias_0
+timestamp 1624049879
+transform 1 0 202834 0 -1 687483
+box -54 -412 44317 2238
+use mimcap_decoup_1x5 mimcap_decoup_1x5_6
+array 0 0 34500 0 1 6522
+timestamp 1624376995
+transform -1 0 345445 0 1 602155
+box 0 -159 34500 6363
+use mimcap_decoup_1x5 mimcap_decoup_1x5_3
+array 0 0 34500 0 2 6522
+timestamp 1624376995
+transform 1 0 291410 0 1 559700
+box 0 -159 34500 6363
+use res_amp_top res_amp_top_0 ~/caravel_analog_fulgor/mag/afernandez_residue_amplifier
+timestamp 1624402156
+transform 1 0 349695 0 1 630386
+box -5005 -972 31038 12726
+use mimcap_decoup_1x5 mimcap_decoup_1x5_4
+array 0 0 34500 0 2 6522
+timestamp 1624376995
+transform 1 0 382888 0 1 560156
+box 0 -159 34500 6363
+use mimcap_decoup_1x5 mimcap_decoup_1x5_5
+array 0 0 34500 0 2 6522
+timestamp 1624376995
+transform 1 0 489384 0 1 560611
+box 0 -159 34500 6363
<< labels >>
flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
port 0 nsew signal bidirectional
@@ -1024,8 +3044,6 @@
port 40 nsew signal bidirectional
flabel metal3 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
port 41 nsew signal bidirectional
-flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
-port 42 nsew signal bidirectional
flabel metal3 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
port 43 nsew signal bidirectional
flabel metal3 s 120194 702300 125194 704800 0 FreeSans 1920 180 0 0 io_analog[7]
@@ -1036,8 +3054,6 @@
port 46 nsew signal bidirectional
flabel metal3 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
port 47 nsew signal bidirectional
-flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
-port 48 nsew signal bidirectional
flabel metal3 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
port 49 nsew signal bidirectional
flabel metal3 s 326794 702300 328994 704800 0 FreeSans 1920 180 0 0 io_clamp_high[0]
@@ -2052,10 +4068,6 @@
port 554 nsew signal bidirectional
flabel metal3 s 0 633842 1660 638642 0 FreeSans 1120 0 0 0 vccd2
port 555 nsew signal bidirectional
-flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
-port 556 nsew signal bidirectional
-flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
-port 557 nsew signal bidirectional
flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1120 0 0 0 vdda1
port 558 nsew signal bidirectional
flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1120 0 0 0 vdda1
@@ -2072,8 +4084,6 @@
port 564 nsew signal bidirectional
flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
port 565 nsew signal bidirectional
-flabel metal3 s 0 559442 1660 564242 0 FreeSans 1120 0 0 0 vssa2
-port 566 nsew signal bidirectional
flabel metal3 s 0 549442 1660 554242 0 FreeSans 1120 0 0 0 vssa2
port 567 nsew signal bidirectional
flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1120 0 0 0 vssd1
@@ -2296,10 +4306,16 @@
port 676 nsew signal input
flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
port 677 nsew signal input
-flabel metal3 572152 640142 580220 644150 0 FreeSans 16000 0 0 0 VCCD1
-flabel metal3 567038 550960 577302 554546 0 FreeSans 16000 0 0 0 VDDA1
-flabel metal3 511190 664896 514962 676272 0 FreeSans 16000 90 0 0 VSSA1
-flabel metal3 561703 191929 571721 195859 0 FreeSans 16000 0 0 0 VSSD1
+flabel metal3 s -800 559442 860 564242 0 FreeSans 1120 180 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
+port 556 nsew signal bidirectional
<< properties >>
string FIXED_BBOX 0 0 584000 704000
<< end >>
diff --git a/mag/user_analog_project_wrapper_backup.mag b/mag/user_analog_project_wrapper_backup.mag
new file mode 100644
index 0000000..b5ee2cf
--- /dev/null
+++ b/mag/user_analog_project_wrapper_backup.mag
@@ -0,0 +1,2936 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624066370
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+rect 583520 7454 584800 7566
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+rect -800 5090 480 5202
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+rect -800 3908 480 4020
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+rect -800 2726 480 2838
+rect 583520 2726 584800 2838
+rect -800 1544 480 1656
+rect 583520 1544 584800 1656
+<< via3 >>
+rect 17558 690824 19943 693242
+rect 66188 690828 68553 693229
+rect 21892 681701 22854 683906
+rect 23042 660657 64017 661269
+rect 23042 660101 64017 660657
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+rect 582403 550629 584710 551658
+rect 582466 540677 584684 545159
+rect 578937 224950 584001 240589
+rect 578907 136610 583774 151577
+<< metal4 >>
+rect 510305 704716 525574 704717
+rect 510305 701790 510306 704716
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+rect 32695 240589 584002 240590
+rect 32695 240427 578937 240589
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+rect 275011 225260 578937 225376
+rect 32695 225102 578937 225260
+rect 22911 225078 578937 225102
+rect 563330 224950 578937 225078
+rect 584001 224950 584002 240589
+rect 563330 224949 584002 224950
+rect 563330 224854 583937 224949
+rect 100326 151653 584154 151892
+rect 100326 151638 338641 151653
+rect 100326 136586 100582 151638
+rect 116556 136586 338641 151638
+rect 100326 136461 338641 136586
+rect 354383 151577 584154 151653
+rect 354383 136610 578907 151577
+rect 583774 136610 584154 151577
+rect 354383 136461 584154 136610
+rect 100326 136443 584154 136461
+<< via4 >>
+rect 510306 701790 525573 704716
+rect 510466 697694 525573 701790
+rect 202733 684711 202780 685235
+rect 202780 684711 247109 685235
+rect 202733 684082 202805 684711
+rect 202805 684082 247109 684711
+rect 202733 683217 247109 684082
+rect 31049 673154 46493 677668
+rect 101968 673232 117567 677786
+rect 216750 673124 232071 677761
+rect 260437 671893 274962 678175
+rect 452327 673047 467023 677887
+rect 23042 661269 64017 661882
+rect 23042 660101 64017 661269
+rect 83765 661487 124085 662834
+rect 83765 660179 124071 661487
+rect 124071 660179 124085 661487
+rect 83049 624683 133410 624733
+rect 82973 624630 133488 624683
+rect 14337 621627 14427 624437
+rect 14427 621627 64282 624437
+rect 14337 618001 64282 621627
+rect 82973 622007 83152 624630
+rect 83152 622007 133410 624630
+rect 133410 622007 133488 624630
+rect 82973 617893 133488 622007
+rect 30180 583701 46130 599282
+rect 100668 583221 116512 598859
+rect 338602 583865 353942 598747
+rect 510429 583750 525629 599011
+rect 546176 584066 561217 598800
+rect 17921 540202 32921 555772
+rect 216832 540306 232047 555641
+rect 259862 540435 275226 555640
+rect 452164 540149 467493 555601
+rect 101051 417422 116402 432558
+rect 338894 417742 354227 432559
+rect 545705 417276 561038 432093
+rect 17721 363349 33021 378616
+rect 259965 363295 275183 378759
+rect 452093 363464 467213 378918
+rect 17911 225102 32695 240605
+rect 259755 225260 275011 240427
+rect 452031 225376 467535 240355
+rect 100582 136586 116556 151638
+rect 338641 136461 354383 151653
+<< metal5 >>
+rect 510282 704716 525597 704740
+rect 510282 703705 510306 704716
+rect 510173 701790 510306 703705
+rect 525573 703705 525597 704716
+rect 510173 697694 510466 701790
+rect 525573 697694 525839 703705
+rect 202709 685235 247133 685259
+rect 202709 683217 202733 685235
+rect 247109 683217 247133 685235
+rect 202709 683193 247133 683217
+rect 30960 677668 46833 678350
+rect 30960 673154 31049 677668
+rect 46493 673154 46833 677668
+rect 101944 677786 117591 677810
+rect 101944 677524 101968 677786
+rect 30960 661906 46833 673154
+rect 101864 673232 101968 677524
+rect 117567 677524 117591 677786
+rect 216581 677761 232247 683193
+rect 117567 673232 117672 677524
+rect 101864 662858 117672 673232
+rect 216581 673124 216750 677761
+rect 232071 673124 232247 677761
+rect 83741 662834 124109 662858
+rect 23018 661882 64041 661906
+rect 23018 660101 23042 661882
+rect 64017 660101 64041 661882
+rect 83741 660179 83765 662834
+rect 124085 660179 124109 662834
+rect 83741 660155 124109 660179
+rect 23018 660077 64041 660101
+rect 83025 624733 133434 624757
+rect 83025 624707 83049 624733
+rect 82949 624683 83049 624707
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+rect 133410 624683 133512 624707
+rect 14313 624437 64306 624461
+rect 14313 618001 14337 624437
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+rect 14313 617977 64306 618001
+rect 30017 599282 46173 617977
+rect 82949 617893 82973 624683
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+rect 82949 617869 133512 617893
+rect 30017 586019 30180 599282
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+rect 100463 598859 116619 617869
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+rect 451976 240355 467642 363464
+rect 451976 227015 452031 240355
+rect 452007 225376 452031 227015
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+rect 545384 432093 561540 584066
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+rect 467535 225376 467559 227015
+rect 452007 225352 467559 225376
+rect 338385 136722 338641 151653
+rect 100463 136311 116619 136586
+rect 338617 136461 338641 136722
+rect 354383 136722 354541 151653
+rect 545384 137728 561540 417276
+rect 354383 136461 354407 136722
+rect 338617 136437 354407 136461
+<< comment >>
+rect -100 704000 584100 704100
+rect -100 0 0 704000
+rect 584000 0 584100 704000
+rect -100 -100 584100 0
+use bias bias_0
+timestamp 1624049879
+transform 1 0 202834 0 -1 687483
+box -54 -412 44317 2238
+use top_pll_v1 *top_pll_v1_0
+timestamp 1624049879
+transform 1 0 14782 0 1 657248
+box -642 -33679 50180 2860
+use top_pll_v2 top_pll_v2_0
+timestamp 1624054096
+transform -1 0 133068 0 1 657248
+box -642 -33679 50180 2860
+<< labels >>
+flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -800 381864 480 381976 0 FreeSans 1120 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -800 338642 480 338754 0 FreeSans 1120 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -800 295420 480 295532 0 FreeSans 1120 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -800 252398 480 252510 0 FreeSans 1120 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -800 124776 480 124888 0 FreeSans 1120 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -800 81554 480 81666 0 FreeSans 1120 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -800 38332 480 38444 0 FreeSans 1120 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -800 16910 480 17022 0 FreeSans 1120 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 583520 313652 584800 313764 0 FreeSans 1120 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 583520 358874 584800 358986 0 FreeSans 1120 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 583520 405296 584800 405408 0 FreeSans 1120 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 583520 449718 584800 449830 0 FreeSans 1120 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 583520 494140 584800 494252 0 FreeSans 1120 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 583520 583562 584800 583674 0 FreeSans 1120 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -800 511530 480 511642 0 FreeSans 1120 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -800 468308 480 468420 0 FreeSans 1120 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -800 425086 480 425198 0 FreeSans 1120 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 583520 270412 584800 270524 0 FreeSans 1120 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -800 380682 480 380794 0 FreeSans 1120 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -800 337460 480 337572 0 FreeSans 1120 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -800 294238 480 294350 0 FreeSans 1120 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -800 251216 480 251328 0 FreeSans 1120 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -800 123594 480 123706 0 FreeSans 1120 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -800 80372 480 80484 0 FreeSans 1120 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -800 37150 480 37262 0 FreeSans 1120 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -800 15728 480 15840 0 FreeSans 1120 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 583520 314834 584800 314946 0 FreeSans 1120 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 583520 360056 584800 360168 0 FreeSans 1120 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 583520 406478 584800 406590 0 FreeSans 1120 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 583520 450900 584800 451012 0 FreeSans 1120 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 583520 495322 584800 495434 0 FreeSans 1120 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 583520 584744 584800 584856 0 FreeSans 1120 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -800 510348 480 510460 0 FreeSans 1120 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -800 467126 480 467238 0 FreeSans 1120 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -800 423904 480 424016 0 FreeSans 1120 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1120 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 566594 702300 571594 704800 0 FreeSans 1920 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 465394 702300 470394 704800 0 FreeSans 1920 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 413394 702300 418394 704800 0 FreeSans 1920 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 120194 702300 125194 704800 0 FreeSans 1920 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 68194 702300 73194 704800 0 FreeSans 1920 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 16194 702300 21194 704800 0 FreeSans 1920 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 326794 702300 328994 704800 0 FreeSans 1920 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 225094 702300 227294 704800 0 FreeSans 1920 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 173394 702300 175594 704800 0 FreeSans 1920 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 324294 702300 326494 704800 0 FreeSans 1920 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 222594 702300 224794 704800 0 FreeSans 1920 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 170894 702300 173094 704800 0 FreeSans 1920 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 583520 2726 584800 2838 0 FreeSans 1120 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 583520 408842 584800 408954 0 FreeSans 1120 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 583520 453264 584800 453376 0 FreeSans 1120 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 583520 497686 584800 497798 0 FreeSans 1120 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 583520 587108 584800 587220 0 FreeSans 1120 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -800 507984 480 508096 0 FreeSans 1120 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -800 464762 480 464874 0 FreeSans 1120 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -800 421540 480 421652 0 FreeSans 1120 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -800 378318 480 378430 0 FreeSans 1120 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -800 335096 480 335208 0 FreeSans 1120 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -800 291874 480 291986 0 FreeSans 1120 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 583520 7454 584800 7566 0 FreeSans 1120 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -800 248852 480 248964 0 FreeSans 1120 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -800 121230 480 121342 0 FreeSans 1120 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -800 78008 480 78120 0 FreeSans 1120 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -800 34786 480 34898 0 FreeSans 1120 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -800 13364 480 13476 0 FreeSans 1120 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -800 8636 480 8748 0 FreeSans 1120 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -800 3908 480 4020 0 FreeSans 1120 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 583520 12182 584800 12294 0 FreeSans 1120 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 583520 16910 584800 17022 0 FreeSans 1120 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 583520 21638 584800 21750 0 FreeSans 1120 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 583520 48096 584800 48208 0 FreeSans 1120 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 583520 92754 584800 92866 0 FreeSans 1120 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 583520 272776 584800 272888 0 FreeSans 1120 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 583520 317198 584800 317310 0 FreeSans 1120 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 583520 362420 584800 362532 0 FreeSans 1120 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 583520 1544 584800 1656 0 FreeSans 1120 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 583520 407660 584800 407772 0 FreeSans 1120 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 583520 452082 584800 452194 0 FreeSans 1120 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 583520 496504 584800 496616 0 FreeSans 1120 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 583520 585926 584800 586038 0 FreeSans 1120 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -800 509166 480 509278 0 FreeSans 1120 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -800 465944 480 466056 0 FreeSans 1120 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -800 422722 480 422834 0 FreeSans 1120 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -800 379500 480 379612 0 FreeSans 1120 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -800 336278 480 336390 0 FreeSans 1120 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -800 293056 480 293168 0 FreeSans 1120 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 583520 6272 584800 6384 0 FreeSans 1120 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -800 250034 480 250146 0 FreeSans 1120 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -800 122412 480 122524 0 FreeSans 1120 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -800 79190 480 79302 0 FreeSans 1120 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -800 35968 480 36080 0 FreeSans 1120 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -800 14546 480 14658 0 FreeSans 1120 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -800 9818 480 9930 0 FreeSans 1120 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -800 5090 480 5202 0 FreeSans 1120 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 583520 11000 584800 11112 0 FreeSans 1120 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 583520 15728 584800 15840 0 FreeSans 1120 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 583520 20456 584800 20568 0 FreeSans 1120 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 583520 46914 584800 47026 0 FreeSans 1120 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 583520 91572 584800 91684 0 FreeSans 1120 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 583520 271594 584800 271706 0 FreeSans 1120 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 583520 316016 584800 316128 0 FreeSans 1120 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 583520 361238 584800 361350 0 FreeSans 1120 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 583520 5090 584800 5202 0 FreeSans 1120 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 583520 411206 584800 411318 0 FreeSans 1120 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 583520 455628 584800 455740 0 FreeSans 1120 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 583520 500050 584800 500162 0 FreeSans 1120 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 583520 589472 584800 589584 0 FreeSans 1120 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -800 505620 480 505732 0 FreeSans 1120 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -800 462398 480 462510 0 FreeSans 1120 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -800 419176 480 419288 0 FreeSans 1120 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -800 375954 480 376066 0 FreeSans 1120 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -800 332732 480 332844 0 FreeSans 1120 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -800 289510 480 289622 0 FreeSans 1120 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 583520 9818 584800 9930 0 FreeSans 1120 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -800 246488 480 246600 0 FreeSans 1120 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -800 118866 480 118978 0 FreeSans 1120 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -800 75644 480 75756 0 FreeSans 1120 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -800 32422 480 32534 0 FreeSans 1120 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -800 11000 480 11112 0 FreeSans 1120 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -800 6272 480 6384 0 FreeSans 1120 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -800 1544 480 1656 0 FreeSans 1120 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 583520 14546 584800 14658 0 FreeSans 1120 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 583520 19274 584800 19386 0 FreeSans 1120 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1120 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1120 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1120 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1120 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1120 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1120 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1120 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1120 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1120 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1120 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1120 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -800 506802 480 506914 0 FreeSans 1120 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -800 463580 480 463692 0 FreeSans 1120 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -800 420358 480 420470 0 FreeSans 1120 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -800 377136 480 377248 0 FreeSans 1120 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -800 333914 480 334026 0 FreeSans 1120 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -800 290692 480 290804 0 FreeSans 1120 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 583520 8636 584800 8748 0 FreeSans 1120 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -800 247670 480 247782 0 FreeSans 1120 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -800 120048 480 120160 0 FreeSans 1120 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -800 76826 480 76938 0 FreeSans 1120 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -800 33604 480 33716 0 FreeSans 1120 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -800 12182 480 12294 0 FreeSans 1120 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -800 7454 480 7566 0 FreeSans 1120 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -800 2726 480 2838 0 FreeSans 1120 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1120 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1120 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1120 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1120 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1120 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1120 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1120 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1120 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 125816 -800 125928 480 0 FreeSans 1120 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 480416 -800 480528 480 0 FreeSans 1120 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 483962 -800 484074 480 0 FreeSans 1120 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 487508 -800 487620 480 0 FreeSans 1120 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 491054 -800 491166 480 0 FreeSans 1120 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 494600 -800 494712 480 0 FreeSans 1120 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 498146 -800 498258 480 0 FreeSans 1120 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 501692 -800 501804 480 0 FreeSans 1120 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 505238 -800 505350 480 0 FreeSans 1120 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 508784 -800 508896 480 0 FreeSans 1120 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 512330 -800 512442 480 0 FreeSans 1120 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 161276 -800 161388 480 0 FreeSans 1120 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 515876 -800 515988 480 0 FreeSans 1120 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 519422 -800 519534 480 0 FreeSans 1120 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 522968 -800 523080 480 0 FreeSans 1120 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 526514 -800 526626 480 0 FreeSans 1120 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 530060 -800 530172 480 0 FreeSans 1120 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 533606 -800 533718 480 0 FreeSans 1120 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 537152 -800 537264 480 0 FreeSans 1120 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 540698 -800 540810 480 0 FreeSans 1120 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 544244 -800 544356 480 0 FreeSans 1120 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 547790 -800 547902 480 0 FreeSans 1120 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 164822 -800 164934 480 0 FreeSans 1120 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 551336 -800 551448 480 0 FreeSans 1120 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 554882 -800 554994 480 0 FreeSans 1120 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 558428 -800 558540 480 0 FreeSans 1120 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 561974 -800 562086 480 0 FreeSans 1120 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 565520 -800 565632 480 0 FreeSans 1120 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 569066 -800 569178 480 0 FreeSans 1120 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 572612 -800 572724 480 0 FreeSans 1120 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 576158 -800 576270 480 0 FreeSans 1120 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 168368 -800 168480 480 0 FreeSans 1120 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 171914 -800 172026 480 0 FreeSans 1120 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 175460 -800 175572 480 0 FreeSans 1120 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 179006 -800 179118 480 0 FreeSans 1120 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 182552 -800 182664 480 0 FreeSans 1120 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 186098 -800 186210 480 0 FreeSans 1120 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 189644 -800 189756 480 0 FreeSans 1120 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 193190 -800 193302 480 0 FreeSans 1120 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 129362 -800 129474 480 0 FreeSans 1120 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 196736 -800 196848 480 0 FreeSans 1120 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 200282 -800 200394 480 0 FreeSans 1120 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 203828 -800 203940 480 0 FreeSans 1120 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 207374 -800 207486 480 0 FreeSans 1120 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 210920 -800 211032 480 0 FreeSans 1120 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 214466 -800 214578 480 0 FreeSans 1120 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 218012 -800 218124 480 0 FreeSans 1120 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 221558 -800 221670 480 0 FreeSans 1120 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 225104 -800 225216 480 0 FreeSans 1120 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 228650 -800 228762 480 0 FreeSans 1120 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 132908 -800 133020 480 0 FreeSans 1120 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 232196 -800 232308 480 0 FreeSans 1120 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 235742 -800 235854 480 0 FreeSans 1120 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 239288 -800 239400 480 0 FreeSans 1120 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 242834 -800 242946 480 0 FreeSans 1120 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 246380 -800 246492 480 0 FreeSans 1120 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 249926 -800 250038 480 0 FreeSans 1120 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 253472 -800 253584 480 0 FreeSans 1120 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 257018 -800 257130 480 0 FreeSans 1120 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 260564 -800 260676 480 0 FreeSans 1120 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 264110 -800 264222 480 0 FreeSans 1120 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 136454 -800 136566 480 0 FreeSans 1120 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 267656 -800 267768 480 0 FreeSans 1120 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 271202 -800 271314 480 0 FreeSans 1120 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 274748 -800 274860 480 0 FreeSans 1120 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 278294 -800 278406 480 0 FreeSans 1120 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 281840 -800 281952 480 0 FreeSans 1120 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 285386 -800 285498 480 0 FreeSans 1120 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 288932 -800 289044 480 0 FreeSans 1120 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 292478 -800 292590 480 0 FreeSans 1120 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 296024 -800 296136 480 0 FreeSans 1120 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 299570 -800 299682 480 0 FreeSans 1120 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 140000 -800 140112 480 0 FreeSans 1120 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 303116 -800 303228 480 0 FreeSans 1120 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 306662 -800 306774 480 0 FreeSans 1120 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 310208 -800 310320 480 0 FreeSans 1120 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 313754 -800 313866 480 0 FreeSans 1120 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 317300 -800 317412 480 0 FreeSans 1120 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 320846 -800 320958 480 0 FreeSans 1120 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 324392 -800 324504 480 0 FreeSans 1120 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 327938 -800 328050 480 0 FreeSans 1120 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 331484 -800 331596 480 0 FreeSans 1120 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 335030 -800 335142 480 0 FreeSans 1120 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 143546 -800 143658 480 0 FreeSans 1120 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 338576 -800 338688 480 0 FreeSans 1120 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 342122 -800 342234 480 0 FreeSans 1120 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 345668 -800 345780 480 0 FreeSans 1120 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 349214 -800 349326 480 0 FreeSans 1120 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 352760 -800 352872 480 0 FreeSans 1120 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 356306 -800 356418 480 0 FreeSans 1120 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 359852 -800 359964 480 0 FreeSans 1120 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 363398 -800 363510 480 0 FreeSans 1120 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 366944 -800 367056 480 0 FreeSans 1120 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 370490 -800 370602 480 0 FreeSans 1120 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 147092 -800 147204 480 0 FreeSans 1120 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 374036 -800 374148 480 0 FreeSans 1120 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 377582 -800 377694 480 0 FreeSans 1120 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 381128 -800 381240 480 0 FreeSans 1120 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 384674 -800 384786 480 0 FreeSans 1120 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 388220 -800 388332 480 0 FreeSans 1120 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 391766 -800 391878 480 0 FreeSans 1120 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 395312 -800 395424 480 0 FreeSans 1120 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 398858 -800 398970 480 0 FreeSans 1120 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 402404 -800 402516 480 0 FreeSans 1120 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 405950 -800 406062 480 0 FreeSans 1120 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 150638 -800 150750 480 0 FreeSans 1120 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 409496 -800 409608 480 0 FreeSans 1120 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 413042 -800 413154 480 0 FreeSans 1120 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 416588 -800 416700 480 0 FreeSans 1120 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 420134 -800 420246 480 0 FreeSans 1120 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 423680 -800 423792 480 0 FreeSans 1120 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 427226 -800 427338 480 0 FreeSans 1120 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 430772 -800 430884 480 0 FreeSans 1120 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 434318 -800 434430 480 0 FreeSans 1120 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 437864 -800 437976 480 0 FreeSans 1120 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 441410 -800 441522 480 0 FreeSans 1120 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 154184 -800 154296 480 0 FreeSans 1120 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 444956 -800 445068 480 0 FreeSans 1120 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 448502 -800 448614 480 0 FreeSans 1120 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 452048 -800 452160 480 0 FreeSans 1120 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 455594 -800 455706 480 0 FreeSans 1120 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 459140 -800 459252 480 0 FreeSans 1120 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 462686 -800 462798 480 0 FreeSans 1120 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 466232 -800 466344 480 0 FreeSans 1120 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 469778 -800 469890 480 0 FreeSans 1120 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 473324 -800 473436 480 0 FreeSans 1120 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 476870 -800 476982 480 0 FreeSans 1120 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 157730 -800 157842 480 0 FreeSans 1120 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 126998 -800 127110 480 0 FreeSans 1120 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 481598 -800 481710 480 0 FreeSans 1120 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 485144 -800 485256 480 0 FreeSans 1120 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 488690 -800 488802 480 0 FreeSans 1120 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 492236 -800 492348 480 0 FreeSans 1120 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 495782 -800 495894 480 0 FreeSans 1120 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 499328 -800 499440 480 0 FreeSans 1120 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 502874 -800 502986 480 0 FreeSans 1120 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 506420 -800 506532 480 0 FreeSans 1120 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 509966 -800 510078 480 0 FreeSans 1120 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 513512 -800 513624 480 0 FreeSans 1120 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 162458 -800 162570 480 0 FreeSans 1120 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 517058 -800 517170 480 0 FreeSans 1120 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 520604 -800 520716 480 0 FreeSans 1120 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 524150 -800 524262 480 0 FreeSans 1120 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 527696 -800 527808 480 0 FreeSans 1120 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 531242 -800 531354 480 0 FreeSans 1120 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 534788 -800 534900 480 0 FreeSans 1120 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 538334 -800 538446 480 0 FreeSans 1120 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 541880 -800 541992 480 0 FreeSans 1120 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 545426 -800 545538 480 0 FreeSans 1120 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 548972 -800 549084 480 0 FreeSans 1120 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 166004 -800 166116 480 0 FreeSans 1120 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 552518 -800 552630 480 0 FreeSans 1120 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 556064 -800 556176 480 0 FreeSans 1120 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 559610 -800 559722 480 0 FreeSans 1120 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 563156 -800 563268 480 0 FreeSans 1120 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 566702 -800 566814 480 0 FreeSans 1120 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 570248 -800 570360 480 0 FreeSans 1120 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 573794 -800 573906 480 0 FreeSans 1120 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 577340 -800 577452 480 0 FreeSans 1120 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 169550 -800 169662 480 0 FreeSans 1120 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 173096 -800 173208 480 0 FreeSans 1120 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 176642 -800 176754 480 0 FreeSans 1120 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 180188 -800 180300 480 0 FreeSans 1120 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 183734 -800 183846 480 0 FreeSans 1120 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 187280 -800 187392 480 0 FreeSans 1120 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 190826 -800 190938 480 0 FreeSans 1120 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 194372 -800 194484 480 0 FreeSans 1120 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 130544 -800 130656 480 0 FreeSans 1120 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 197918 -800 198030 480 0 FreeSans 1120 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 201464 -800 201576 480 0 FreeSans 1120 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 205010 -800 205122 480 0 FreeSans 1120 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 208556 -800 208668 480 0 FreeSans 1120 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 212102 -800 212214 480 0 FreeSans 1120 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 215648 -800 215760 480 0 FreeSans 1120 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 219194 -800 219306 480 0 FreeSans 1120 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 222740 -800 222852 480 0 FreeSans 1120 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 226286 -800 226398 480 0 FreeSans 1120 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 229832 -800 229944 480 0 FreeSans 1120 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 134090 -800 134202 480 0 FreeSans 1120 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 233378 -800 233490 480 0 FreeSans 1120 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 236924 -800 237036 480 0 FreeSans 1120 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 240470 -800 240582 480 0 FreeSans 1120 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 244016 -800 244128 480 0 FreeSans 1120 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 247562 -800 247674 480 0 FreeSans 1120 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 251108 -800 251220 480 0 FreeSans 1120 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 254654 -800 254766 480 0 FreeSans 1120 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 258200 -800 258312 480 0 FreeSans 1120 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 261746 -800 261858 480 0 FreeSans 1120 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 265292 -800 265404 480 0 FreeSans 1120 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 137636 -800 137748 480 0 FreeSans 1120 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 268838 -800 268950 480 0 FreeSans 1120 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 272384 -800 272496 480 0 FreeSans 1120 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 275930 -800 276042 480 0 FreeSans 1120 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 279476 -800 279588 480 0 FreeSans 1120 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 283022 -800 283134 480 0 FreeSans 1120 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 286568 -800 286680 480 0 FreeSans 1120 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 290114 -800 290226 480 0 FreeSans 1120 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 293660 -800 293772 480 0 FreeSans 1120 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 297206 -800 297318 480 0 FreeSans 1120 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 300752 -800 300864 480 0 FreeSans 1120 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 141182 -800 141294 480 0 FreeSans 1120 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 304298 -800 304410 480 0 FreeSans 1120 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 307844 -800 307956 480 0 FreeSans 1120 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 311390 -800 311502 480 0 FreeSans 1120 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 314936 -800 315048 480 0 FreeSans 1120 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 318482 -800 318594 480 0 FreeSans 1120 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 322028 -800 322140 480 0 FreeSans 1120 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 325574 -800 325686 480 0 FreeSans 1120 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 329120 -800 329232 480 0 FreeSans 1120 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 332666 -800 332778 480 0 FreeSans 1120 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 336212 -800 336324 480 0 FreeSans 1120 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 144728 -800 144840 480 0 FreeSans 1120 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 339758 -800 339870 480 0 FreeSans 1120 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 343304 -800 343416 480 0 FreeSans 1120 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 346850 -800 346962 480 0 FreeSans 1120 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 350396 -800 350508 480 0 FreeSans 1120 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 353942 -800 354054 480 0 FreeSans 1120 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 357488 -800 357600 480 0 FreeSans 1120 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 361034 -800 361146 480 0 FreeSans 1120 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 364580 -800 364692 480 0 FreeSans 1120 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 368126 -800 368238 480 0 FreeSans 1120 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 371672 -800 371784 480 0 FreeSans 1120 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 148274 -800 148386 480 0 FreeSans 1120 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 375218 -800 375330 480 0 FreeSans 1120 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 378764 -800 378876 480 0 FreeSans 1120 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 382310 -800 382422 480 0 FreeSans 1120 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 385856 -800 385968 480 0 FreeSans 1120 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 389402 -800 389514 480 0 FreeSans 1120 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 392948 -800 393060 480 0 FreeSans 1120 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 396494 -800 396606 480 0 FreeSans 1120 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 400040 -800 400152 480 0 FreeSans 1120 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 403586 -800 403698 480 0 FreeSans 1120 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 407132 -800 407244 480 0 FreeSans 1120 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 151820 -800 151932 480 0 FreeSans 1120 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 410678 -800 410790 480 0 FreeSans 1120 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 414224 -800 414336 480 0 FreeSans 1120 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 417770 -800 417882 480 0 FreeSans 1120 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 421316 -800 421428 480 0 FreeSans 1120 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 424862 -800 424974 480 0 FreeSans 1120 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 428408 -800 428520 480 0 FreeSans 1120 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 431954 -800 432066 480 0 FreeSans 1120 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 435500 -800 435612 480 0 FreeSans 1120 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 439046 -800 439158 480 0 FreeSans 1120 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 442592 -800 442704 480 0 FreeSans 1120 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 155366 -800 155478 480 0 FreeSans 1120 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 446138 -800 446250 480 0 FreeSans 1120 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 449684 -800 449796 480 0 FreeSans 1120 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 453230 -800 453342 480 0 FreeSans 1120 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 456776 -800 456888 480 0 FreeSans 1120 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 460322 -800 460434 480 0 FreeSans 1120 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 463868 -800 463980 480 0 FreeSans 1120 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 467414 -800 467526 480 0 FreeSans 1120 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 470960 -800 471072 480 0 FreeSans 1120 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 474506 -800 474618 480 0 FreeSans 1120 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 478052 -800 478164 480 0 FreeSans 1120 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 158912 -800 159024 480 0 FreeSans 1120 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 128180 -800 128292 480 0 FreeSans 1120 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 482780 -800 482892 480 0 FreeSans 1120 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 486326 -800 486438 480 0 FreeSans 1120 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 489872 -800 489984 480 0 FreeSans 1120 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 493418 -800 493530 480 0 FreeSans 1120 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 496964 -800 497076 480 0 FreeSans 1120 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 500510 -800 500622 480 0 FreeSans 1120 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 504056 -800 504168 480 0 FreeSans 1120 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 507602 -800 507714 480 0 FreeSans 1120 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 511148 -800 511260 480 0 FreeSans 1120 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 514694 -800 514806 480 0 FreeSans 1120 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 163640 -800 163752 480 0 FreeSans 1120 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 518240 -800 518352 480 0 FreeSans 1120 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 521786 -800 521898 480 0 FreeSans 1120 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 525332 -800 525444 480 0 FreeSans 1120 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 528878 -800 528990 480 0 FreeSans 1120 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 532424 -800 532536 480 0 FreeSans 1120 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 535970 -800 536082 480 0 FreeSans 1120 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 539516 -800 539628 480 0 FreeSans 1120 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 543062 -800 543174 480 0 FreeSans 1120 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 546608 -800 546720 480 0 FreeSans 1120 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 550154 -800 550266 480 0 FreeSans 1120 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 167186 -800 167298 480 0 FreeSans 1120 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 553700 -800 553812 480 0 FreeSans 1120 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 557246 -800 557358 480 0 FreeSans 1120 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 560792 -800 560904 480 0 FreeSans 1120 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 564338 -800 564450 480 0 FreeSans 1120 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 567884 -800 567996 480 0 FreeSans 1120 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 571430 -800 571542 480 0 FreeSans 1120 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 574976 -800 575088 480 0 FreeSans 1120 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 578522 -800 578634 480 0 FreeSans 1120 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 170732 -800 170844 480 0 FreeSans 1120 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 174278 -800 174390 480 0 FreeSans 1120 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 177824 -800 177936 480 0 FreeSans 1120 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 181370 -800 181482 480 0 FreeSans 1120 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 184916 -800 185028 480 0 FreeSans 1120 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 188462 -800 188574 480 0 FreeSans 1120 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 192008 -800 192120 480 0 FreeSans 1120 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 195554 -800 195666 480 0 FreeSans 1120 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 131726 -800 131838 480 0 FreeSans 1120 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 199100 -800 199212 480 0 FreeSans 1120 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 202646 -800 202758 480 0 FreeSans 1120 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 206192 -800 206304 480 0 FreeSans 1120 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 209738 -800 209850 480 0 FreeSans 1120 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 213284 -800 213396 480 0 FreeSans 1120 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 216830 -800 216942 480 0 FreeSans 1120 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 220376 -800 220488 480 0 FreeSans 1120 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 223922 -800 224034 480 0 FreeSans 1120 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 227468 -800 227580 480 0 FreeSans 1120 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 231014 -800 231126 480 0 FreeSans 1120 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 135272 -800 135384 480 0 FreeSans 1120 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 234560 -800 234672 480 0 FreeSans 1120 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 238106 -800 238218 480 0 FreeSans 1120 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 241652 -800 241764 480 0 FreeSans 1120 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 245198 -800 245310 480 0 FreeSans 1120 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 248744 -800 248856 480 0 FreeSans 1120 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 252290 -800 252402 480 0 FreeSans 1120 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 255836 -800 255948 480 0 FreeSans 1120 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 259382 -800 259494 480 0 FreeSans 1120 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 262928 -800 263040 480 0 FreeSans 1120 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 266474 -800 266586 480 0 FreeSans 1120 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 138818 -800 138930 480 0 FreeSans 1120 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 270020 -800 270132 480 0 FreeSans 1120 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 273566 -800 273678 480 0 FreeSans 1120 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 277112 -800 277224 480 0 FreeSans 1120 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 280658 -800 280770 480 0 FreeSans 1120 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 284204 -800 284316 480 0 FreeSans 1120 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 287750 -800 287862 480 0 FreeSans 1120 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 291296 -800 291408 480 0 FreeSans 1120 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 294842 -800 294954 480 0 FreeSans 1120 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 298388 -800 298500 480 0 FreeSans 1120 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 301934 -800 302046 480 0 FreeSans 1120 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 142364 -800 142476 480 0 FreeSans 1120 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 305480 -800 305592 480 0 FreeSans 1120 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 309026 -800 309138 480 0 FreeSans 1120 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 312572 -800 312684 480 0 FreeSans 1120 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 316118 -800 316230 480 0 FreeSans 1120 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 319664 -800 319776 480 0 FreeSans 1120 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 323210 -800 323322 480 0 FreeSans 1120 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 326756 -800 326868 480 0 FreeSans 1120 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 330302 -800 330414 480 0 FreeSans 1120 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 333848 -800 333960 480 0 FreeSans 1120 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 337394 -800 337506 480 0 FreeSans 1120 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 145910 -800 146022 480 0 FreeSans 1120 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 340940 -800 341052 480 0 FreeSans 1120 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 344486 -800 344598 480 0 FreeSans 1120 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 348032 -800 348144 480 0 FreeSans 1120 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 351578 -800 351690 480 0 FreeSans 1120 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 355124 -800 355236 480 0 FreeSans 1120 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 358670 -800 358782 480 0 FreeSans 1120 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 362216 -800 362328 480 0 FreeSans 1120 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 365762 -800 365874 480 0 FreeSans 1120 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 369308 -800 369420 480 0 FreeSans 1120 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 372854 -800 372966 480 0 FreeSans 1120 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 149456 -800 149568 480 0 FreeSans 1120 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 376400 -800 376512 480 0 FreeSans 1120 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 379946 -800 380058 480 0 FreeSans 1120 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 383492 -800 383604 480 0 FreeSans 1120 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 387038 -800 387150 480 0 FreeSans 1120 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 390584 -800 390696 480 0 FreeSans 1120 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 394130 -800 394242 480 0 FreeSans 1120 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 397676 -800 397788 480 0 FreeSans 1120 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 401222 -800 401334 480 0 FreeSans 1120 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 404768 -800 404880 480 0 FreeSans 1120 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 408314 -800 408426 480 0 FreeSans 1120 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 153002 -800 153114 480 0 FreeSans 1120 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 411860 -800 411972 480 0 FreeSans 1120 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 415406 -800 415518 480 0 FreeSans 1120 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 418952 -800 419064 480 0 FreeSans 1120 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 422498 -800 422610 480 0 FreeSans 1120 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 426044 -800 426156 480 0 FreeSans 1120 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 429590 -800 429702 480 0 FreeSans 1120 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 433136 -800 433248 480 0 FreeSans 1120 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 436682 -800 436794 480 0 FreeSans 1120 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 440228 -800 440340 480 0 FreeSans 1120 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 443774 -800 443886 480 0 FreeSans 1120 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 156548 -800 156660 480 0 FreeSans 1120 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 447320 -800 447432 480 0 FreeSans 1120 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 450866 -800 450978 480 0 FreeSans 1120 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 454412 -800 454524 480 0 FreeSans 1120 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 457958 -800 458070 480 0 FreeSans 1120 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 461504 -800 461616 480 0 FreeSans 1120 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 465050 -800 465162 480 0 FreeSans 1120 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 468596 -800 468708 480 0 FreeSans 1120 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 472142 -800 472254 480 0 FreeSans 1120 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 475688 -800 475800 480 0 FreeSans 1120 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 479234 -800 479346 480 0 FreeSans 1120 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 160094 -800 160206 480 0 FreeSans 1120 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 579704 -800 579816 480 0 FreeSans 1120 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 580886 -800 580998 480 0 FreeSans 1120 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 582068 -800 582180 480 0 FreeSans 1120 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 583250 -800 583362 480 0 FreeSans 1120 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 582340 639784 584800 644584 0 FreeSans 1120 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 582340 629784 584800 634584 0 FreeSans 1120 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 643842 1660 648642 0 FreeSans 1120 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 633842 1660 638642 0 FreeSans 1120 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1120 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1120 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 204888 1660 209688 0 FreeSans 1120 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 214888 1660 219688 0 FreeSans 1120 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 520594 702340 525394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1120 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 549442 1660 554242 0 FreeSans 1120 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1120 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 582340 181430 584800 186230 0 FreeSans 1120 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 172888 1660 177688 0 FreeSans 1120 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 162888 1660 167688 0 FreeSans 1120 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 524 -800 636 480 0 FreeSans 1120 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 1706 -800 1818 480 0 FreeSans 1120 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 2888 -800 3000 480 0 FreeSans 1120 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 7616 -800 7728 480 0 FreeSans 1120 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 47804 -800 47916 480 0 FreeSans 1120 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 51350 -800 51462 480 0 FreeSans 1120 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 54896 -800 55008 480 0 FreeSans 1120 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 58442 -800 58554 480 0 FreeSans 1120 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 61988 -800 62100 480 0 FreeSans 1120 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 65534 -800 65646 480 0 FreeSans 1120 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 69080 -800 69192 480 0 FreeSans 1120 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 72626 -800 72738 480 0 FreeSans 1120 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 76172 -800 76284 480 0 FreeSans 1120 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 79718 -800 79830 480 0 FreeSans 1120 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 12344 -800 12456 480 0 FreeSans 1120 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 83264 -800 83376 480 0 FreeSans 1120 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 86810 -800 86922 480 0 FreeSans 1120 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 90356 -800 90468 480 0 FreeSans 1120 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 93902 -800 94014 480 0 FreeSans 1120 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 97448 -800 97560 480 0 FreeSans 1120 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 100994 -800 101106 480 0 FreeSans 1120 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 104540 -800 104652 480 0 FreeSans 1120 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 108086 -800 108198 480 0 FreeSans 1120 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 111632 -800 111744 480 0 FreeSans 1120 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 115178 -800 115290 480 0 FreeSans 1120 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 17072 -800 17184 480 0 FreeSans 1120 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 118724 -800 118836 480 0 FreeSans 1120 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 122270 -800 122382 480 0 FreeSans 1120 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 21800 -800 21912 480 0 FreeSans 1120 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 26528 -800 26640 480 0 FreeSans 1120 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 30074 -800 30186 480 0 FreeSans 1120 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 33620 -800 33732 480 0 FreeSans 1120 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 37166 -800 37278 480 0 FreeSans 1120 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 40712 -800 40824 480 0 FreeSans 1120 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 44258 -800 44370 480 0 FreeSans 1120 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 4070 -800 4182 480 0 FreeSans 1120 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 8798 -800 8910 480 0 FreeSans 1120 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 48986 -800 49098 480 0 FreeSans 1120 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 52532 -800 52644 480 0 FreeSans 1120 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 56078 -800 56190 480 0 FreeSans 1120 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 59624 -800 59736 480 0 FreeSans 1120 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 63170 -800 63282 480 0 FreeSans 1120 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 66716 -800 66828 480 0 FreeSans 1120 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 70262 -800 70374 480 0 FreeSans 1120 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 73808 -800 73920 480 0 FreeSans 1120 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 77354 -800 77466 480 0 FreeSans 1120 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 80900 -800 81012 480 0 FreeSans 1120 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 13526 -800 13638 480 0 FreeSans 1120 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 84446 -800 84558 480 0 FreeSans 1120 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 87992 -800 88104 480 0 FreeSans 1120 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 91538 -800 91650 480 0 FreeSans 1120 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 95084 -800 95196 480 0 FreeSans 1120 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 98630 -800 98742 480 0 FreeSans 1120 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 102176 -800 102288 480 0 FreeSans 1120 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 105722 -800 105834 480 0 FreeSans 1120 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 109268 -800 109380 480 0 FreeSans 1120 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 112814 -800 112926 480 0 FreeSans 1120 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 116360 -800 116472 480 0 FreeSans 1120 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 18254 -800 18366 480 0 FreeSans 1120 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 119906 -800 120018 480 0 FreeSans 1120 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 123452 -800 123564 480 0 FreeSans 1120 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 22982 -800 23094 480 0 FreeSans 1120 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 27710 -800 27822 480 0 FreeSans 1120 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 31256 -800 31368 480 0 FreeSans 1120 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 34802 -800 34914 480 0 FreeSans 1120 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 38348 -800 38460 480 0 FreeSans 1120 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 1120 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 1120 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 1120 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 1120 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 1120 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 1120 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 1120 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 64352 -800 64464 480 0 FreeSans 1120 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 1120 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 71444 -800 71556 480 0 FreeSans 1120 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 1120 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 1120 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 1120 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 1120 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 1120 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 1120 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 92720 -800 92832 480 0 FreeSans 1120 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 1120 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 1120 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 1120 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 1120 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 1120 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 1120 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 1120 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 1120 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 1120 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 1120 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 1120 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 1120 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 1120 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 1120 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 1120 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 1120 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 1120 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 1120 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 1120 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 1120 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 1120 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 1120 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
+port 677 nsew signal input
+flabel metal3 s -800 559442 860 564242 0 FreeSans 1120 180 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/mag/user_analog_project_wrapper_backup_2.mag b/mag/user_analog_project_wrapper_backup_2.mag
new file mode 100644
index 0000000..9437f5b
--- /dev/null
+++ b/mag/user_analog_project_wrapper_backup_2.mag
@@ -0,0 +1,3404 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624385832
+<< nwell >>
+rect 14730 660108 64962 661110
+rect 14730 660034 64841 660108
+rect 82888 660083 133067 660649
+rect 83408 660052 119178 660083
+rect 14730 659150 14782 660034
+rect 28401 659941 28758 659982
+rect 83408 659846 112858 660052
+rect 124441 660015 133067 660083
+<< pwell >>
+rect 371257 636863 371689 637515
+<< nsubdiff >>
+rect 14777 660157 14801 660354
+rect 21672 660157 21696 660354
+rect 23064 660169 23088 660375
+rect 28678 660169 28702 660375
+rect 28954 660172 28978 660367
+rect 34940 660172 34964 660367
+rect 35514 660153 35538 660369
+rect 63779 660153 63803 660369
+rect 84063 660216 84087 660457
+rect 112239 660216 112263 660457
+rect 112659 660076 112683 660241
+rect 119084 660076 119108 660241
+rect 119365 660188 119389 660416
+rect 124370 660188 124394 660416
+rect 124754 660180 124778 660424
+rect 132540 660180 132564 660424
+<< nsubdiffcont >>
+rect 14801 660157 21672 660354
+rect 23088 660169 28678 660375
+rect 28978 660172 34940 660367
+rect 35538 660153 63779 660369
+rect 84087 660216 112239 660457
+rect 112683 660076 119084 660241
+rect 119389 660188 124370 660416
+rect 124778 660180 132540 660424
+<< locali >>
+rect 14785 660157 14801 660354
+rect 21672 660157 21688 660354
+rect 23072 660169 23088 660375
+rect 28678 660169 28694 660375
+rect 28962 660172 28978 660367
+rect 34940 660172 34956 660367
+rect 35522 660153 35538 660369
+rect 63779 660153 63795 660369
+rect 84071 660216 84087 660457
+rect 112239 660216 112255 660457
+rect 112667 660076 112683 660241
+rect 119084 660076 119100 660241
+rect 119373 660188 119389 660416
+rect 124370 660188 124386 660416
+<< viali >>
+rect 14801 660157 21672 660354
+rect 23088 660169 28678 660375
+rect 28978 660172 34940 660367
+rect 35538 660153 63779 660369
+rect 84087 660216 112239 660457
+rect 112683 660076 119084 660241
+rect 119389 660188 124370 660416
+rect 124762 660180 124778 660424
+rect 124778 660180 132540 660424
+rect 132540 660180 132556 660424
+<< metal1 >>
+rect 207113 687795 207123 688222
+rect 210595 687795 210605 688222
+rect 211166 687819 211176 688246
+rect 214648 687819 214658 688246
+rect 223050 688060 223060 688186
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+rect 223050 687834 223060 687894
+rect 226864 688060 226874 688186
+rect 226864 687894 226915 688060
+rect 226864 687834 226874 687894
+rect 227267 687846 227277 688273
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+rect 231320 687855 231330 688282
+rect 234802 687855 234812 688282
+rect 235302 687865 235312 688292
+rect 238784 687865 238794 688292
+rect 239323 687860 239333 688287
+rect 242805 687860 242815 688287
+rect 243362 687858 243372 688285
+rect 246844 687858 246854 688285
+rect 202763 685044 202773 685354
+rect 247145 685044 247155 685354
+rect 83775 660472 112339 660489
+rect 23004 660431 64063 660453
+rect 23004 660397 23042 660431
+rect 21700 660392 23042 660397
+rect 14751 660388 23042 660392
+rect 14751 660354 14834 660388
+rect 14751 660157 14801 660354
+rect 14751 660121 14834 660157
+rect 14751 660101 23042 660121
+rect 64025 660101 64063 660431
+rect 14751 660070 64063 660101
+rect 14751 660012 21718 660070
+rect 23004 660030 64063 660070
+rect 23037 660018 28912 660030
+rect 14751 659692 14783 660012
+rect 83746 659999 83756 660472
+rect 112324 660409 112339 660472
+rect 119184 660445 133061 660493
+rect 119184 660416 120252 660445
+rect 112324 660408 112754 660409
+rect 119106 660408 119389 660416
+rect 112324 660332 119389 660408
+rect 112324 660010 112657 660332
+rect 119074 660241 119389 660332
+rect 119084 660188 119389 660241
+rect 119084 660106 120252 660188
+rect 133038 660416 133061 660445
+rect 133038 660106 133067 660416
+rect 119084 660076 133067 660106
+rect 112324 659999 112334 660010
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+rect 12990 659376 14703 659415
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+rect 14624 659204 14991 659270
+rect 132917 659204 133081 659270
+rect 14624 659103 14703 659204
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+rect 12990 659070 14703 659103
+rect 66160 658984 66170 659137
+rect 64423 658604 66170 658984
+rect 63068 658320 66170 658604
+rect 64423 657999 66170 658320
+rect 66160 657870 66170 657999
+rect 68582 658984 68592 659137
+rect 68582 657999 68603 658984
+rect 79846 658972 83253 658973
+rect 68582 657870 68592 657999
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+rect 82308 658604 83253 658972
+rect 82308 658320 84035 658604
+rect 82308 657988 83253 658320
+rect 82308 657985 82318 657988
+rect 21150 657532 21160 657665
+rect 23640 657532 23650 657665
+rect 64013 657266 64962 657593
+rect 34969 657163 34979 657242
+rect 35060 657163 35070 657242
+rect 34989 656786 35045 657163
+rect 34964 656680 34974 656786
+rect 35066 656680 35076 656786
+rect 64135 656771 64962 657266
+rect 64163 656761 64962 656771
+rect 64457 656747 64962 656761
+rect 82894 657275 83827 657583
+rect 124326 657529 124336 657669
+rect 126700 657529 126710 657669
+rect 82894 656573 83702 657275
+rect 112660 657160 112670 657243
+rect 112802 657160 112812 657243
+rect 112685 656533 112741 657160
+rect 112626 656348 112636 656533
+rect 112797 656348 112807 656533
+rect 12125 655528 13406 655533
+rect 12125 655200 14468 655528
+rect 133382 655200 135242 655528
+rect 12125 652870 13406 655200
+rect 134093 653281 135239 655200
+rect 12125 651670 15784 652870
+rect 132088 652146 135239 653281
+rect 132558 652135 135239 652146
+rect 12125 651669 15583 651670
+rect 12125 651650 13406 651669
+rect 124847 637057 124857 637281
+rect 125442 637057 125452 637281
+<< via1 >>
+rect 207123 687795 210595 688222
+rect 211176 687819 214648 688246
+rect 223060 687834 226864 688186
+rect 227277 687846 230749 688273
+rect 231330 687855 234802 688282
+rect 235312 687865 238784 688292
+rect 239333 687860 242805 688287
+rect 243372 687858 246844 688285
+rect 202773 685044 247145 685354
+rect 23042 660388 64025 660431
+rect 14834 660375 64025 660388
+rect 14834 660354 23088 660375
+rect 14834 660157 21672 660354
+rect 21672 660169 23088 660354
+rect 23088 660169 28678 660375
+rect 28678 660369 64025 660375
+rect 28678 660367 35538 660369
+rect 28678 660172 28978 660367
+rect 28978 660172 34940 660367
+rect 34940 660172 35538 660367
+rect 28678 660169 35538 660172
+rect 21672 660157 35538 660169
+rect 14834 660153 35538 660157
+rect 35538 660153 63779 660369
+rect 63779 660153 64025 660369
+rect 14834 660121 64025 660153
+rect 23042 660101 64025 660121
+rect 83756 660457 112324 660472
+rect 83756 660216 84087 660457
+rect 84087 660216 112239 660457
+rect 112239 660216 112324 660457
+rect 120252 660424 133038 660445
+rect 120252 660416 124762 660424
+rect 83756 659999 112324 660216
+rect 112657 660241 119074 660332
+rect 112657 660076 112683 660241
+rect 112683 660076 119074 660241
+rect 120252 660188 124370 660416
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+rect 120252 660180 124762 660188
+rect 124762 660180 132556 660424
+rect 132556 660180 133038 660424
+rect 120252 660106 133038 660180
+rect 112657 659953 119074 660076
+rect 13065 659103 14624 659376
+rect 133081 659175 133354 659303
+rect 66170 657870 68582 659137
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+rect 21160 657532 23640 657665
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+rect 34974 656680 35066 656786
+rect 124336 657529 126700 657669
+rect 112670 657160 112802 657243
+rect 112636 656348 112797 656533
+rect 124857 637057 125442 637281
+<< metal2 >>
+rect 211169 688703 214642 688713
+rect 207123 688623 210596 688633
+rect 235312 688693 238785 688703
+rect 231330 688683 234803 688693
+rect 227277 688664 230750 688674
+rect 214642 688246 214648 688256
+rect 211169 687865 211176 687875
+rect 223060 688186 226864 688196
+rect 223060 687824 226864 687834
+rect 235312 687855 238785 687865
+rect 239333 688688 242806 688698
+rect 231330 687845 234803 687855
+rect 239333 687850 242806 687860
+rect 243372 688686 246845 688696
+rect 243372 687848 246845 687858
+rect 227277 687826 230750 687836
+rect 211176 687809 214648 687819
+rect 207123 687785 210596 687795
+rect 202773 685354 247145 685364
+rect 202773 685034 202780 685044
+rect 247142 685034 247145 685044
+rect 202780 684701 247142 684711
+rect 83765 660846 124085 660856
+rect 23042 660657 64025 660667
+rect 14834 660388 23042 660398
+rect 14834 660111 23042 660121
+rect 23042 660091 64025 660101
+rect 83756 660472 83765 660482
+rect 124085 660445 133038 660455
+rect 112324 659999 112657 660179
+rect 83756 659989 112324 659999
+rect 119074 660106 120252 660179
+rect 119074 660096 133038 660106
+rect 119074 659999 120418 660096
+rect 112657 659943 119074 659953
+rect 2509 659760 14155 659826
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+rect 133081 659303 137580 659313
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+<< metal5 >>
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+<< comment >>
+rect -100 704000 584100 704100
+rect -100 0 0 704000
+rect 584000 0 584100 704000
+rect -100 -100 584100 0
+use res_amp_top res_amp_top_0 ~/caravel_analog_fulgor/mag/afernandez_residue_amplifier
+timestamp 1624371743
+transform 1 0 349695 0 1 630386
+box -5005 -972 31038 12726
+use top_pll_v2 top_pll_v2_0
+timestamp 1624316735
+transform -1 0 133068 0 1 657248
+box -642 -33679 50180 2860
+use top_pll_v1 *top_pll_v1_0
+timestamp 1624316735
+transform 1 0 14782 0 1 657248
+box -642 -33679 50180 2860
+use bias bias_0
+timestamp 1624049879
+transform 1 0 202834 0 -1 687483
+box -54 -412 44317 2238
+<< labels >>
+flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -800 381864 480 381976 0 FreeSans 1120 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -800 338642 480 338754 0 FreeSans 1120 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -800 295420 480 295532 0 FreeSans 1120 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -800 252398 480 252510 0 FreeSans 1120 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -800 124776 480 124888 0 FreeSans 1120 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -800 81554 480 81666 0 FreeSans 1120 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -800 38332 480 38444 0 FreeSans 1120 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -800 16910 480 17022 0 FreeSans 1120 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 583520 313652 584800 313764 0 FreeSans 1120 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 583520 358874 584800 358986 0 FreeSans 1120 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 583520 405296 584800 405408 0 FreeSans 1120 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 583520 449718 584800 449830 0 FreeSans 1120 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 583520 494140 584800 494252 0 FreeSans 1120 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 583520 583562 584800 583674 0 FreeSans 1120 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -800 511530 480 511642 0 FreeSans 1120 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -800 468308 480 468420 0 FreeSans 1120 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -800 425086 480 425198 0 FreeSans 1120 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 583520 270412 584800 270524 0 FreeSans 1120 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -800 380682 480 380794 0 FreeSans 1120 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -800 337460 480 337572 0 FreeSans 1120 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -800 294238 480 294350 0 FreeSans 1120 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -800 251216 480 251328 0 FreeSans 1120 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -800 123594 480 123706 0 FreeSans 1120 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -800 80372 480 80484 0 FreeSans 1120 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -800 37150 480 37262 0 FreeSans 1120 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -800 15728 480 15840 0 FreeSans 1120 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 583520 314834 584800 314946 0 FreeSans 1120 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 583520 360056 584800 360168 0 FreeSans 1120 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 583520 406478 584800 406590 0 FreeSans 1120 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 583520 450900 584800 451012 0 FreeSans 1120 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 583520 495322 584800 495434 0 FreeSans 1120 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 583520 584744 584800 584856 0 FreeSans 1120 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -800 510348 480 510460 0 FreeSans 1120 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -800 467126 480 467238 0 FreeSans 1120 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -800 423904 480 424016 0 FreeSans 1120 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1120 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 566594 702300 571594 704800 0 FreeSans 1920 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 465394 702300 470394 704800 0 FreeSans 1920 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 413394 702300 418394 704800 0 FreeSans 1920 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 120194 702300 125194 704800 0 FreeSans 1920 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 68194 702300 73194 704800 0 FreeSans 1920 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 16194 702300 21194 704800 0 FreeSans 1920 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 326794 702300 328994 704800 0 FreeSans 1920 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 225094 702300 227294 704800 0 FreeSans 1920 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 173394 702300 175594 704800 0 FreeSans 1920 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 324294 702300 326494 704800 0 FreeSans 1920 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 222594 702300 224794 704800 0 FreeSans 1920 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 170894 702300 173094 704800 0 FreeSans 1920 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 583520 2726 584800 2838 0 FreeSans 1120 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 583520 408842 584800 408954 0 FreeSans 1120 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 583520 453264 584800 453376 0 FreeSans 1120 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 583520 497686 584800 497798 0 FreeSans 1120 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 583520 587108 584800 587220 0 FreeSans 1120 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -800 507984 480 508096 0 FreeSans 1120 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -800 464762 480 464874 0 FreeSans 1120 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -800 421540 480 421652 0 FreeSans 1120 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -800 378318 480 378430 0 FreeSans 1120 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -800 335096 480 335208 0 FreeSans 1120 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -800 291874 480 291986 0 FreeSans 1120 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 583520 7454 584800 7566 0 FreeSans 1120 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -800 248852 480 248964 0 FreeSans 1120 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -800 121230 480 121342 0 FreeSans 1120 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -800 78008 480 78120 0 FreeSans 1120 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -800 34786 480 34898 0 FreeSans 1120 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -800 13364 480 13476 0 FreeSans 1120 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -800 8636 480 8748 0 FreeSans 1120 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -800 3908 480 4020 0 FreeSans 1120 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 583520 12182 584800 12294 0 FreeSans 1120 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 583520 16910 584800 17022 0 FreeSans 1120 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 583520 21638 584800 21750 0 FreeSans 1120 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 583520 48096 584800 48208 0 FreeSans 1120 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 583520 92754 584800 92866 0 FreeSans 1120 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 583520 272776 584800 272888 0 FreeSans 1120 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 583520 317198 584800 317310 0 FreeSans 1120 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 583520 362420 584800 362532 0 FreeSans 1120 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 583520 1544 584800 1656 0 FreeSans 1120 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 583520 407660 584800 407772 0 FreeSans 1120 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 583520 452082 584800 452194 0 FreeSans 1120 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 583520 496504 584800 496616 0 FreeSans 1120 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 583520 585926 584800 586038 0 FreeSans 1120 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -800 509166 480 509278 0 FreeSans 1120 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -800 465944 480 466056 0 FreeSans 1120 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -800 422722 480 422834 0 FreeSans 1120 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -800 379500 480 379612 0 FreeSans 1120 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -800 336278 480 336390 0 FreeSans 1120 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -800 293056 480 293168 0 FreeSans 1120 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 583520 6272 584800 6384 0 FreeSans 1120 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -800 250034 480 250146 0 FreeSans 1120 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -800 122412 480 122524 0 FreeSans 1120 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -800 79190 480 79302 0 FreeSans 1120 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -800 35968 480 36080 0 FreeSans 1120 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -800 14546 480 14658 0 FreeSans 1120 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -800 9818 480 9930 0 FreeSans 1120 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -800 5090 480 5202 0 FreeSans 1120 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 583520 11000 584800 11112 0 FreeSans 1120 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 583520 15728 584800 15840 0 FreeSans 1120 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 583520 20456 584800 20568 0 FreeSans 1120 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 583520 46914 584800 47026 0 FreeSans 1120 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 583520 91572 584800 91684 0 FreeSans 1120 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 583520 271594 584800 271706 0 FreeSans 1120 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 583520 316016 584800 316128 0 FreeSans 1120 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 583520 361238 584800 361350 0 FreeSans 1120 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 583520 5090 584800 5202 0 FreeSans 1120 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 583520 411206 584800 411318 0 FreeSans 1120 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 583520 455628 584800 455740 0 FreeSans 1120 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 583520 500050 584800 500162 0 FreeSans 1120 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 583520 589472 584800 589584 0 FreeSans 1120 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -800 505620 480 505732 0 FreeSans 1120 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -800 462398 480 462510 0 FreeSans 1120 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -800 419176 480 419288 0 FreeSans 1120 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -800 375954 480 376066 0 FreeSans 1120 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -800 332732 480 332844 0 FreeSans 1120 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -800 289510 480 289622 0 FreeSans 1120 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 583520 9818 584800 9930 0 FreeSans 1120 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -800 246488 480 246600 0 FreeSans 1120 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -800 118866 480 118978 0 FreeSans 1120 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -800 75644 480 75756 0 FreeSans 1120 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -800 32422 480 32534 0 FreeSans 1120 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -800 11000 480 11112 0 FreeSans 1120 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -800 6272 480 6384 0 FreeSans 1120 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -800 1544 480 1656 0 FreeSans 1120 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 583520 14546 584800 14658 0 FreeSans 1120 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 583520 19274 584800 19386 0 FreeSans 1120 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1120 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1120 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1120 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1120 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1120 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1120 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1120 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1120 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1120 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1120 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1120 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -800 506802 480 506914 0 FreeSans 1120 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -800 463580 480 463692 0 FreeSans 1120 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -800 420358 480 420470 0 FreeSans 1120 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -800 377136 480 377248 0 FreeSans 1120 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -800 333914 480 334026 0 FreeSans 1120 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -800 290692 480 290804 0 FreeSans 1120 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 583520 8636 584800 8748 0 FreeSans 1120 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -800 247670 480 247782 0 FreeSans 1120 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -800 120048 480 120160 0 FreeSans 1120 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -800 76826 480 76938 0 FreeSans 1120 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -800 33604 480 33716 0 FreeSans 1120 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -800 12182 480 12294 0 FreeSans 1120 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -800 7454 480 7566 0 FreeSans 1120 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -800 2726 480 2838 0 FreeSans 1120 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1120 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1120 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1120 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1120 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1120 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1120 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1120 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1120 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 125816 -800 125928 480 0 FreeSans 1120 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 480416 -800 480528 480 0 FreeSans 1120 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 483962 -800 484074 480 0 FreeSans 1120 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 487508 -800 487620 480 0 FreeSans 1120 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 491054 -800 491166 480 0 FreeSans 1120 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 494600 -800 494712 480 0 FreeSans 1120 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 498146 -800 498258 480 0 FreeSans 1120 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 501692 -800 501804 480 0 FreeSans 1120 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 505238 -800 505350 480 0 FreeSans 1120 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 508784 -800 508896 480 0 FreeSans 1120 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 512330 -800 512442 480 0 FreeSans 1120 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 161276 -800 161388 480 0 FreeSans 1120 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 515876 -800 515988 480 0 FreeSans 1120 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 519422 -800 519534 480 0 FreeSans 1120 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 522968 -800 523080 480 0 FreeSans 1120 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 526514 -800 526626 480 0 FreeSans 1120 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 530060 -800 530172 480 0 FreeSans 1120 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 533606 -800 533718 480 0 FreeSans 1120 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 537152 -800 537264 480 0 FreeSans 1120 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 540698 -800 540810 480 0 FreeSans 1120 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 544244 -800 544356 480 0 FreeSans 1120 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 547790 -800 547902 480 0 FreeSans 1120 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 164822 -800 164934 480 0 FreeSans 1120 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 551336 -800 551448 480 0 FreeSans 1120 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 554882 -800 554994 480 0 FreeSans 1120 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 558428 -800 558540 480 0 FreeSans 1120 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 561974 -800 562086 480 0 FreeSans 1120 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 565520 -800 565632 480 0 FreeSans 1120 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 569066 -800 569178 480 0 FreeSans 1120 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 572612 -800 572724 480 0 FreeSans 1120 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 576158 -800 576270 480 0 FreeSans 1120 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 168368 -800 168480 480 0 FreeSans 1120 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 171914 -800 172026 480 0 FreeSans 1120 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 175460 -800 175572 480 0 FreeSans 1120 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 179006 -800 179118 480 0 FreeSans 1120 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 182552 -800 182664 480 0 FreeSans 1120 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 186098 -800 186210 480 0 FreeSans 1120 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 189644 -800 189756 480 0 FreeSans 1120 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 193190 -800 193302 480 0 FreeSans 1120 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 129362 -800 129474 480 0 FreeSans 1120 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 196736 -800 196848 480 0 FreeSans 1120 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 200282 -800 200394 480 0 FreeSans 1120 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 203828 -800 203940 480 0 FreeSans 1120 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 207374 -800 207486 480 0 FreeSans 1120 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 210920 -800 211032 480 0 FreeSans 1120 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 214466 -800 214578 480 0 FreeSans 1120 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 218012 -800 218124 480 0 FreeSans 1120 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 221558 -800 221670 480 0 FreeSans 1120 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 225104 -800 225216 480 0 FreeSans 1120 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 228650 -800 228762 480 0 FreeSans 1120 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 132908 -800 133020 480 0 FreeSans 1120 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 232196 -800 232308 480 0 FreeSans 1120 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 235742 -800 235854 480 0 FreeSans 1120 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 239288 -800 239400 480 0 FreeSans 1120 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 242834 -800 242946 480 0 FreeSans 1120 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 246380 -800 246492 480 0 FreeSans 1120 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 249926 -800 250038 480 0 FreeSans 1120 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 253472 -800 253584 480 0 FreeSans 1120 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 257018 -800 257130 480 0 FreeSans 1120 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 260564 -800 260676 480 0 FreeSans 1120 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 264110 -800 264222 480 0 FreeSans 1120 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 136454 -800 136566 480 0 FreeSans 1120 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 267656 -800 267768 480 0 FreeSans 1120 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 271202 -800 271314 480 0 FreeSans 1120 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 274748 -800 274860 480 0 FreeSans 1120 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 278294 -800 278406 480 0 FreeSans 1120 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 281840 -800 281952 480 0 FreeSans 1120 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 285386 -800 285498 480 0 FreeSans 1120 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 288932 -800 289044 480 0 FreeSans 1120 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 292478 -800 292590 480 0 FreeSans 1120 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 296024 -800 296136 480 0 FreeSans 1120 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 299570 -800 299682 480 0 FreeSans 1120 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 140000 -800 140112 480 0 FreeSans 1120 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 303116 -800 303228 480 0 FreeSans 1120 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 306662 -800 306774 480 0 FreeSans 1120 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 310208 -800 310320 480 0 FreeSans 1120 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 313754 -800 313866 480 0 FreeSans 1120 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 317300 -800 317412 480 0 FreeSans 1120 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 320846 -800 320958 480 0 FreeSans 1120 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 324392 -800 324504 480 0 FreeSans 1120 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 327938 -800 328050 480 0 FreeSans 1120 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 331484 -800 331596 480 0 FreeSans 1120 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 335030 -800 335142 480 0 FreeSans 1120 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 143546 -800 143658 480 0 FreeSans 1120 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 338576 -800 338688 480 0 FreeSans 1120 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 342122 -800 342234 480 0 FreeSans 1120 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 345668 -800 345780 480 0 FreeSans 1120 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 349214 -800 349326 480 0 FreeSans 1120 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 352760 -800 352872 480 0 FreeSans 1120 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 356306 -800 356418 480 0 FreeSans 1120 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 359852 -800 359964 480 0 FreeSans 1120 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 363398 -800 363510 480 0 FreeSans 1120 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 366944 -800 367056 480 0 FreeSans 1120 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 370490 -800 370602 480 0 FreeSans 1120 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 147092 -800 147204 480 0 FreeSans 1120 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 374036 -800 374148 480 0 FreeSans 1120 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 377582 -800 377694 480 0 FreeSans 1120 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 381128 -800 381240 480 0 FreeSans 1120 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 384674 -800 384786 480 0 FreeSans 1120 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 388220 -800 388332 480 0 FreeSans 1120 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 391766 -800 391878 480 0 FreeSans 1120 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 395312 -800 395424 480 0 FreeSans 1120 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 398858 -800 398970 480 0 FreeSans 1120 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 402404 -800 402516 480 0 FreeSans 1120 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 405950 -800 406062 480 0 FreeSans 1120 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 150638 -800 150750 480 0 FreeSans 1120 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 409496 -800 409608 480 0 FreeSans 1120 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 413042 -800 413154 480 0 FreeSans 1120 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 416588 -800 416700 480 0 FreeSans 1120 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 420134 -800 420246 480 0 FreeSans 1120 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 423680 -800 423792 480 0 FreeSans 1120 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 427226 -800 427338 480 0 FreeSans 1120 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 430772 -800 430884 480 0 FreeSans 1120 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 434318 -800 434430 480 0 FreeSans 1120 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 437864 -800 437976 480 0 FreeSans 1120 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 441410 -800 441522 480 0 FreeSans 1120 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 154184 -800 154296 480 0 FreeSans 1120 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 444956 -800 445068 480 0 FreeSans 1120 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 448502 -800 448614 480 0 FreeSans 1120 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 452048 -800 452160 480 0 FreeSans 1120 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 455594 -800 455706 480 0 FreeSans 1120 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 459140 -800 459252 480 0 FreeSans 1120 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 462686 -800 462798 480 0 FreeSans 1120 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 466232 -800 466344 480 0 FreeSans 1120 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 469778 -800 469890 480 0 FreeSans 1120 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 473324 -800 473436 480 0 FreeSans 1120 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 476870 -800 476982 480 0 FreeSans 1120 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 157730 -800 157842 480 0 FreeSans 1120 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 126998 -800 127110 480 0 FreeSans 1120 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 481598 -800 481710 480 0 FreeSans 1120 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 485144 -800 485256 480 0 FreeSans 1120 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 488690 -800 488802 480 0 FreeSans 1120 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 492236 -800 492348 480 0 FreeSans 1120 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 495782 -800 495894 480 0 FreeSans 1120 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 499328 -800 499440 480 0 FreeSans 1120 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 502874 -800 502986 480 0 FreeSans 1120 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 506420 -800 506532 480 0 FreeSans 1120 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 509966 -800 510078 480 0 FreeSans 1120 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 513512 -800 513624 480 0 FreeSans 1120 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 162458 -800 162570 480 0 FreeSans 1120 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 517058 -800 517170 480 0 FreeSans 1120 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 520604 -800 520716 480 0 FreeSans 1120 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 524150 -800 524262 480 0 FreeSans 1120 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 527696 -800 527808 480 0 FreeSans 1120 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 531242 -800 531354 480 0 FreeSans 1120 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 534788 -800 534900 480 0 FreeSans 1120 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 538334 -800 538446 480 0 FreeSans 1120 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 541880 -800 541992 480 0 FreeSans 1120 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 545426 -800 545538 480 0 FreeSans 1120 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 548972 -800 549084 480 0 FreeSans 1120 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 166004 -800 166116 480 0 FreeSans 1120 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 552518 -800 552630 480 0 FreeSans 1120 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 556064 -800 556176 480 0 FreeSans 1120 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 559610 -800 559722 480 0 FreeSans 1120 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 563156 -800 563268 480 0 FreeSans 1120 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 566702 -800 566814 480 0 FreeSans 1120 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 570248 -800 570360 480 0 FreeSans 1120 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 573794 -800 573906 480 0 FreeSans 1120 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 577340 -800 577452 480 0 FreeSans 1120 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 169550 -800 169662 480 0 FreeSans 1120 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 173096 -800 173208 480 0 FreeSans 1120 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 176642 -800 176754 480 0 FreeSans 1120 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 180188 -800 180300 480 0 FreeSans 1120 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 183734 -800 183846 480 0 FreeSans 1120 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 187280 -800 187392 480 0 FreeSans 1120 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 190826 -800 190938 480 0 FreeSans 1120 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 194372 -800 194484 480 0 FreeSans 1120 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 130544 -800 130656 480 0 FreeSans 1120 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 197918 -800 198030 480 0 FreeSans 1120 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 201464 -800 201576 480 0 FreeSans 1120 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 205010 -800 205122 480 0 FreeSans 1120 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 208556 -800 208668 480 0 FreeSans 1120 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 212102 -800 212214 480 0 FreeSans 1120 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 215648 -800 215760 480 0 FreeSans 1120 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 219194 -800 219306 480 0 FreeSans 1120 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 222740 -800 222852 480 0 FreeSans 1120 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 226286 -800 226398 480 0 FreeSans 1120 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 229832 -800 229944 480 0 FreeSans 1120 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 134090 -800 134202 480 0 FreeSans 1120 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 233378 -800 233490 480 0 FreeSans 1120 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 236924 -800 237036 480 0 FreeSans 1120 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 240470 -800 240582 480 0 FreeSans 1120 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 244016 -800 244128 480 0 FreeSans 1120 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 247562 -800 247674 480 0 FreeSans 1120 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 251108 -800 251220 480 0 FreeSans 1120 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 254654 -800 254766 480 0 FreeSans 1120 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 258200 -800 258312 480 0 FreeSans 1120 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 261746 -800 261858 480 0 FreeSans 1120 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 265292 -800 265404 480 0 FreeSans 1120 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 137636 -800 137748 480 0 FreeSans 1120 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 268838 -800 268950 480 0 FreeSans 1120 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 272384 -800 272496 480 0 FreeSans 1120 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 275930 -800 276042 480 0 FreeSans 1120 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 279476 -800 279588 480 0 FreeSans 1120 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 283022 -800 283134 480 0 FreeSans 1120 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 286568 -800 286680 480 0 FreeSans 1120 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 290114 -800 290226 480 0 FreeSans 1120 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 293660 -800 293772 480 0 FreeSans 1120 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 297206 -800 297318 480 0 FreeSans 1120 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 300752 -800 300864 480 0 FreeSans 1120 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 141182 -800 141294 480 0 FreeSans 1120 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 304298 -800 304410 480 0 FreeSans 1120 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 307844 -800 307956 480 0 FreeSans 1120 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 311390 -800 311502 480 0 FreeSans 1120 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 314936 -800 315048 480 0 FreeSans 1120 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 318482 -800 318594 480 0 FreeSans 1120 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 322028 -800 322140 480 0 FreeSans 1120 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 325574 -800 325686 480 0 FreeSans 1120 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 329120 -800 329232 480 0 FreeSans 1120 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 332666 -800 332778 480 0 FreeSans 1120 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 336212 -800 336324 480 0 FreeSans 1120 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 144728 -800 144840 480 0 FreeSans 1120 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 339758 -800 339870 480 0 FreeSans 1120 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 343304 -800 343416 480 0 FreeSans 1120 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 346850 -800 346962 480 0 FreeSans 1120 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 350396 -800 350508 480 0 FreeSans 1120 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 353942 -800 354054 480 0 FreeSans 1120 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 357488 -800 357600 480 0 FreeSans 1120 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 361034 -800 361146 480 0 FreeSans 1120 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 364580 -800 364692 480 0 FreeSans 1120 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 368126 -800 368238 480 0 FreeSans 1120 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 371672 -800 371784 480 0 FreeSans 1120 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 148274 -800 148386 480 0 FreeSans 1120 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 375218 -800 375330 480 0 FreeSans 1120 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 378764 -800 378876 480 0 FreeSans 1120 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 382310 -800 382422 480 0 FreeSans 1120 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 385856 -800 385968 480 0 FreeSans 1120 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 389402 -800 389514 480 0 FreeSans 1120 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 392948 -800 393060 480 0 FreeSans 1120 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 396494 -800 396606 480 0 FreeSans 1120 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 400040 -800 400152 480 0 FreeSans 1120 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 403586 -800 403698 480 0 FreeSans 1120 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 407132 -800 407244 480 0 FreeSans 1120 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 151820 -800 151932 480 0 FreeSans 1120 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 410678 -800 410790 480 0 FreeSans 1120 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 414224 -800 414336 480 0 FreeSans 1120 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 417770 -800 417882 480 0 FreeSans 1120 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 421316 -800 421428 480 0 FreeSans 1120 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 424862 -800 424974 480 0 FreeSans 1120 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 428408 -800 428520 480 0 FreeSans 1120 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 431954 -800 432066 480 0 FreeSans 1120 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 435500 -800 435612 480 0 FreeSans 1120 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 439046 -800 439158 480 0 FreeSans 1120 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 442592 -800 442704 480 0 FreeSans 1120 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 155366 -800 155478 480 0 FreeSans 1120 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 446138 -800 446250 480 0 FreeSans 1120 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 449684 -800 449796 480 0 FreeSans 1120 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 453230 -800 453342 480 0 FreeSans 1120 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 456776 -800 456888 480 0 FreeSans 1120 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 460322 -800 460434 480 0 FreeSans 1120 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 463868 -800 463980 480 0 FreeSans 1120 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 467414 -800 467526 480 0 FreeSans 1120 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 470960 -800 471072 480 0 FreeSans 1120 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 474506 -800 474618 480 0 FreeSans 1120 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 478052 -800 478164 480 0 FreeSans 1120 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 158912 -800 159024 480 0 FreeSans 1120 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 128180 -800 128292 480 0 FreeSans 1120 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 482780 -800 482892 480 0 FreeSans 1120 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 486326 -800 486438 480 0 FreeSans 1120 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 489872 -800 489984 480 0 FreeSans 1120 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 493418 -800 493530 480 0 FreeSans 1120 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 496964 -800 497076 480 0 FreeSans 1120 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 500510 -800 500622 480 0 FreeSans 1120 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 504056 -800 504168 480 0 FreeSans 1120 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 507602 -800 507714 480 0 FreeSans 1120 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 511148 -800 511260 480 0 FreeSans 1120 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 514694 -800 514806 480 0 FreeSans 1120 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 163640 -800 163752 480 0 FreeSans 1120 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 518240 -800 518352 480 0 FreeSans 1120 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 521786 -800 521898 480 0 FreeSans 1120 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 525332 -800 525444 480 0 FreeSans 1120 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 528878 -800 528990 480 0 FreeSans 1120 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 532424 -800 532536 480 0 FreeSans 1120 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 535970 -800 536082 480 0 FreeSans 1120 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 539516 -800 539628 480 0 FreeSans 1120 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 543062 -800 543174 480 0 FreeSans 1120 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 546608 -800 546720 480 0 FreeSans 1120 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 550154 -800 550266 480 0 FreeSans 1120 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 167186 -800 167298 480 0 FreeSans 1120 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 553700 -800 553812 480 0 FreeSans 1120 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 557246 -800 557358 480 0 FreeSans 1120 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 560792 -800 560904 480 0 FreeSans 1120 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 564338 -800 564450 480 0 FreeSans 1120 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 567884 -800 567996 480 0 FreeSans 1120 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 571430 -800 571542 480 0 FreeSans 1120 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 574976 -800 575088 480 0 FreeSans 1120 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 578522 -800 578634 480 0 FreeSans 1120 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 170732 -800 170844 480 0 FreeSans 1120 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 174278 -800 174390 480 0 FreeSans 1120 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 177824 -800 177936 480 0 FreeSans 1120 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 181370 -800 181482 480 0 FreeSans 1120 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 184916 -800 185028 480 0 FreeSans 1120 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 188462 -800 188574 480 0 FreeSans 1120 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 192008 -800 192120 480 0 FreeSans 1120 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 195554 -800 195666 480 0 FreeSans 1120 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 131726 -800 131838 480 0 FreeSans 1120 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 199100 -800 199212 480 0 FreeSans 1120 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 202646 -800 202758 480 0 FreeSans 1120 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 206192 -800 206304 480 0 FreeSans 1120 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 209738 -800 209850 480 0 FreeSans 1120 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 213284 -800 213396 480 0 FreeSans 1120 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 216830 -800 216942 480 0 FreeSans 1120 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 220376 -800 220488 480 0 FreeSans 1120 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 223922 -800 224034 480 0 FreeSans 1120 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 227468 -800 227580 480 0 FreeSans 1120 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 231014 -800 231126 480 0 FreeSans 1120 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 135272 -800 135384 480 0 FreeSans 1120 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 234560 -800 234672 480 0 FreeSans 1120 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 238106 -800 238218 480 0 FreeSans 1120 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 241652 -800 241764 480 0 FreeSans 1120 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 245198 -800 245310 480 0 FreeSans 1120 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 248744 -800 248856 480 0 FreeSans 1120 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 252290 -800 252402 480 0 FreeSans 1120 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 255836 -800 255948 480 0 FreeSans 1120 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 259382 -800 259494 480 0 FreeSans 1120 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 262928 -800 263040 480 0 FreeSans 1120 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 266474 -800 266586 480 0 FreeSans 1120 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 138818 -800 138930 480 0 FreeSans 1120 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 270020 -800 270132 480 0 FreeSans 1120 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 273566 -800 273678 480 0 FreeSans 1120 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 277112 -800 277224 480 0 FreeSans 1120 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 280658 -800 280770 480 0 FreeSans 1120 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 284204 -800 284316 480 0 FreeSans 1120 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 287750 -800 287862 480 0 FreeSans 1120 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 291296 -800 291408 480 0 FreeSans 1120 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 294842 -800 294954 480 0 FreeSans 1120 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 298388 -800 298500 480 0 FreeSans 1120 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 301934 -800 302046 480 0 FreeSans 1120 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 142364 -800 142476 480 0 FreeSans 1120 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 305480 -800 305592 480 0 FreeSans 1120 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 309026 -800 309138 480 0 FreeSans 1120 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 312572 -800 312684 480 0 FreeSans 1120 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 316118 -800 316230 480 0 FreeSans 1120 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 319664 -800 319776 480 0 FreeSans 1120 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 323210 -800 323322 480 0 FreeSans 1120 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 326756 -800 326868 480 0 FreeSans 1120 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 330302 -800 330414 480 0 FreeSans 1120 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 333848 -800 333960 480 0 FreeSans 1120 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 337394 -800 337506 480 0 FreeSans 1120 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 145910 -800 146022 480 0 FreeSans 1120 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 340940 -800 341052 480 0 FreeSans 1120 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 344486 -800 344598 480 0 FreeSans 1120 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 348032 -800 348144 480 0 FreeSans 1120 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 351578 -800 351690 480 0 FreeSans 1120 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 355124 -800 355236 480 0 FreeSans 1120 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 358670 -800 358782 480 0 FreeSans 1120 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 362216 -800 362328 480 0 FreeSans 1120 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 365762 -800 365874 480 0 FreeSans 1120 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 369308 -800 369420 480 0 FreeSans 1120 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 372854 -800 372966 480 0 FreeSans 1120 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 149456 -800 149568 480 0 FreeSans 1120 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 376400 -800 376512 480 0 FreeSans 1120 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 379946 -800 380058 480 0 FreeSans 1120 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 383492 -800 383604 480 0 FreeSans 1120 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 387038 -800 387150 480 0 FreeSans 1120 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 390584 -800 390696 480 0 FreeSans 1120 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 394130 -800 394242 480 0 FreeSans 1120 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 397676 -800 397788 480 0 FreeSans 1120 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 401222 -800 401334 480 0 FreeSans 1120 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 404768 -800 404880 480 0 FreeSans 1120 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 408314 -800 408426 480 0 FreeSans 1120 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 153002 -800 153114 480 0 FreeSans 1120 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 411860 -800 411972 480 0 FreeSans 1120 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 415406 -800 415518 480 0 FreeSans 1120 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 418952 -800 419064 480 0 FreeSans 1120 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 422498 -800 422610 480 0 FreeSans 1120 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 426044 -800 426156 480 0 FreeSans 1120 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 429590 -800 429702 480 0 FreeSans 1120 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 433136 -800 433248 480 0 FreeSans 1120 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 436682 -800 436794 480 0 FreeSans 1120 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 440228 -800 440340 480 0 FreeSans 1120 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 443774 -800 443886 480 0 FreeSans 1120 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 156548 -800 156660 480 0 FreeSans 1120 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 447320 -800 447432 480 0 FreeSans 1120 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 450866 -800 450978 480 0 FreeSans 1120 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 454412 -800 454524 480 0 FreeSans 1120 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 457958 -800 458070 480 0 FreeSans 1120 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 461504 -800 461616 480 0 FreeSans 1120 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 465050 -800 465162 480 0 FreeSans 1120 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 468596 -800 468708 480 0 FreeSans 1120 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 472142 -800 472254 480 0 FreeSans 1120 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 475688 -800 475800 480 0 FreeSans 1120 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 479234 -800 479346 480 0 FreeSans 1120 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 160094 -800 160206 480 0 FreeSans 1120 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 579704 -800 579816 480 0 FreeSans 1120 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 580886 -800 580998 480 0 FreeSans 1120 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 582068 -800 582180 480 0 FreeSans 1120 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 583250 -800 583362 480 0 FreeSans 1120 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 582340 639784 584800 644584 0 FreeSans 1120 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 582340 629784 584800 634584 0 FreeSans 1120 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 643842 1660 648642 0 FreeSans 1120 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 633842 1660 638642 0 FreeSans 1120 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1120 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1120 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 204888 1660 209688 0 FreeSans 1120 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 214888 1660 219688 0 FreeSans 1120 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 520594 702340 525394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1120 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 549442 1660 554242 0 FreeSans 1120 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1120 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 582340 181430 584800 186230 0 FreeSans 1120 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 172888 1660 177688 0 FreeSans 1120 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 162888 1660 167688 0 FreeSans 1120 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 524 -800 636 480 0 FreeSans 1120 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 1706 -800 1818 480 0 FreeSans 1120 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 2888 -800 3000 480 0 FreeSans 1120 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 7616 -800 7728 480 0 FreeSans 1120 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 47804 -800 47916 480 0 FreeSans 1120 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 51350 -800 51462 480 0 FreeSans 1120 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 54896 -800 55008 480 0 FreeSans 1120 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 58442 -800 58554 480 0 FreeSans 1120 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 61988 -800 62100 480 0 FreeSans 1120 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 65534 -800 65646 480 0 FreeSans 1120 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 69080 -800 69192 480 0 FreeSans 1120 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 72626 -800 72738 480 0 FreeSans 1120 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 76172 -800 76284 480 0 FreeSans 1120 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 79718 -800 79830 480 0 FreeSans 1120 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 12344 -800 12456 480 0 FreeSans 1120 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 83264 -800 83376 480 0 FreeSans 1120 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 86810 -800 86922 480 0 FreeSans 1120 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 90356 -800 90468 480 0 FreeSans 1120 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 93902 -800 94014 480 0 FreeSans 1120 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 97448 -800 97560 480 0 FreeSans 1120 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 100994 -800 101106 480 0 FreeSans 1120 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 104540 -800 104652 480 0 FreeSans 1120 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 108086 -800 108198 480 0 FreeSans 1120 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 111632 -800 111744 480 0 FreeSans 1120 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 115178 -800 115290 480 0 FreeSans 1120 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 17072 -800 17184 480 0 FreeSans 1120 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 118724 -800 118836 480 0 FreeSans 1120 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 122270 -800 122382 480 0 FreeSans 1120 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 21800 -800 21912 480 0 FreeSans 1120 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 26528 -800 26640 480 0 FreeSans 1120 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 30074 -800 30186 480 0 FreeSans 1120 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 33620 -800 33732 480 0 FreeSans 1120 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 37166 -800 37278 480 0 FreeSans 1120 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 40712 -800 40824 480 0 FreeSans 1120 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 44258 -800 44370 480 0 FreeSans 1120 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 4070 -800 4182 480 0 FreeSans 1120 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 8798 -800 8910 480 0 FreeSans 1120 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 48986 -800 49098 480 0 FreeSans 1120 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 52532 -800 52644 480 0 FreeSans 1120 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 56078 -800 56190 480 0 FreeSans 1120 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 59624 -800 59736 480 0 FreeSans 1120 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 63170 -800 63282 480 0 FreeSans 1120 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 66716 -800 66828 480 0 FreeSans 1120 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 70262 -800 70374 480 0 FreeSans 1120 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 73808 -800 73920 480 0 FreeSans 1120 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 77354 -800 77466 480 0 FreeSans 1120 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 80900 -800 81012 480 0 FreeSans 1120 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 13526 -800 13638 480 0 FreeSans 1120 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 84446 -800 84558 480 0 FreeSans 1120 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 87992 -800 88104 480 0 FreeSans 1120 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 91538 -800 91650 480 0 FreeSans 1120 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 95084 -800 95196 480 0 FreeSans 1120 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 98630 -800 98742 480 0 FreeSans 1120 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 102176 -800 102288 480 0 FreeSans 1120 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 105722 -800 105834 480 0 FreeSans 1120 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 109268 -800 109380 480 0 FreeSans 1120 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 112814 -800 112926 480 0 FreeSans 1120 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 116360 -800 116472 480 0 FreeSans 1120 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 18254 -800 18366 480 0 FreeSans 1120 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 119906 -800 120018 480 0 FreeSans 1120 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 123452 -800 123564 480 0 FreeSans 1120 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 22982 -800 23094 480 0 FreeSans 1120 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 27710 -800 27822 480 0 FreeSans 1120 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 31256 -800 31368 480 0 FreeSans 1120 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 34802 -800 34914 480 0 FreeSans 1120 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 38348 -800 38460 480 0 FreeSans 1120 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 1120 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 1120 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 1120 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 1120 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 1120 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 1120 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 1120 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 64352 -800 64464 480 0 FreeSans 1120 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 1120 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 71444 -800 71556 480 0 FreeSans 1120 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 1120 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 1120 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 1120 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 1120 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 1120 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 1120 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 92720 -800 92832 480 0 FreeSans 1120 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 1120 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 1120 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 1120 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 1120 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 1120 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 1120 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 1120 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 1120 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 1120 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 1120 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 1120 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 1120 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 1120 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 1120 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 1120 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 1120 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 1120 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 1120 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 1120 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 1120 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 1120 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 1120 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
+port 677 nsew signal input
+flabel metal3 s -800 559442 860 564242 0 FreeSans 1120 180 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/skywater_setup.sh b/skywater_setup.sh
new file mode 100755
index 0000000..bfe93c6
--- /dev/null
+++ b/skywater_setup.sh
@@ -0,0 +1,137 @@
+#!/bin/bash
+
+echo "################# SkyWater130nm Enviroment Setup #################"
+sudo apt-get update
+sudo apt-get upgrade
+
+echo "################# Installing dependencies #################"
+sudo apt install git libtool automake autoconf texinfo libreadline-dev \
+ tcl8.6-dev tk8.6-dev libx11-dev libxaw7-dev xcb \
+ libxpm-dev bison flex libcairo2-dev m4 tcsh xterm wget \
+ csh tcl-dev tk-dev ca-certificates qt5-default \
+ libqt5designer5 libqt5multimedia5 libqt5multimediawidgets5 \
+ libqt5opengl5 libqt5svg5 libqt5xmlpatterns5 libruby ruby ruby-dev \
+ python3 python3-dev libz-dev -y
+
+version=$(lsb_release -cs)
+if [ $version == "focal" ]; then
+ echo "############################"
+ echo "Ubuntu 20.04. Installing adms"
+ echo "############################"
+ sudo apt install adms -y
+else
+ echo "#####################################"
+ echo "Ubuntu not 20.04. Not installing adms"
+ echo "#####################################"
+fi
+
+echo "################# Changing directory to $HOME #################"
+cd
+
+echo "################# Creating directory for PDK & Tools #################"
+mkdir skywater
+cd skywater
+
+echo "################# Installing ngspice #################"
+git clone https://git.code.sf.net/p/ngspice/ngspice
+cd ngspice
+if [ $version == "focal" ]; then
+ ./autogen.sh --adms
+ mkdir release
+ cd release
+ ../configure --with-x --enable-xspice --enable-cider --enable-openmp --enable-pss --with-readline=yes --disable-debug
+ make -j4
+ sudo make install
+ cd $HOME/skywater
+else
+ ./autogen.sh
+ mkdir release
+ cd release
+ ../configure --with-x --enable-xspice --enable-cider --enable-openmp --enable-pss --with-readline=yes --disable-debug
+ make -j4
+ sudo make install
+ cd $HOME/skywater
+fi
+
+echo "################# Installing XSCHEM #################"
+git clone https://github.com/StefanSchippers/xschem.git
+cd xschem
+./configure --prefix=/usr/local --user-conf-dir=~/.xschem \
+ --user-lib-path=~/share/xschem/xschem_library \
+ --sys-lib-path=/usr/local/share/xschem/xschem_library
+make -j4
+sudo make install
+cd $HOME/skywater
+
+echo "################# Cloning Google/Skywarter Symbols for Xschem #################"
+git clone https://github.com/StefanSchippers/xschem_sky130.git
+
+echo "################# Installing Magic #################"
+git clone git://opencircuitdesign.com/magic
+cd magic
+git checkout magic-8.3
+./configure
+make
+sudo make install
+cd $HOME/skywater
+
+echo "################# Installing klayout #################"
+
+if [ $version == "focal" ]; then
+ wget https://www.klayout.org/downloads/Ubuntu-20/klayout_0.26.11-1_amd64.deb
+else
+ wget https://www.klayout.org/downloads/Ubuntu-16/klayout_0.26.11-1_amd64.deb
+fi
+
+sudo dpkg -i ./klayout_0.26.11-1_amd64.deb
+sudo apt-get install -f -y
+rm klayout_0.26.11-1_amd64.deb
+
+echo "################# Installing netgen #################"
+git clone git://opencircuitdesign.com/netgen
+cd netgen
+git checkout netgen-1.5
+./configure
+make
+sudo make install
+cd $HOME/skywater
+
+echo "################# Cloning Google/Skywarter 130nm PDK #################"
+git clone https://github.com/google/skywater-pdk.git
+cd skywater-pdk
+git submodule init libraries/sky130_fd_io/latest
+git submodule init libraries/sky130_fd_pr/latest
+git submodule init libraries/sky130_fd_sc_hd/latest
+git submodule init libraries/sky130_fd_sc_hdll/latest
+git submodule init libraries/sky130_fd_sc_hs/latest
+git submodule init libraries/sky130_fd_sc_ms/latest
+git submodule init libraries/sky130_fd_sc_ls/latest
+git submodule init libraries/sky130_fd_sc_lp/latest
+git submodule init libraries/sky130_fd_sc_hvl/latest
+git submodule update
+make timing
+cp -a libraries/sky130_fd_pr libraries/sky130_fd_pr_ngspice
+cd libraries/sky130_fd_pr_ngspice/latest
+patch -p2 < $HOME/skywater/xschem_sky130/sky130_fd_pr.patch
+cd $HOME/skywater
+cp ~/sky130-mpw2-fulgor/sky130.lib skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/
+
+echo "################# Installing Open PDKs #################"
+git clone git://opencircuitdesign.com/open_pdks
+cd open_pdks
+git checkout open_pdks-1.0
+mkdir -p $HOME/skywater/pdk/skywater130
+./configure --enable-sky130-pdk=$HOME/skywater/skywater-pdk/libraries --with-sky130-local-path=$HOME/skywater/pdk/skywater130 --enable-xschem-sky130=$HOME/skywater/xschem_sky130
+make
+sudo make install
+#cd $HOME/skywater/pdk/skywater130/sky130A/libs.tech/magic
+#sudo ln -s 1.* current
+#cd $HOME/skywater
+
+#echo "################# Copying sky130A.magicrc to magicrc #################"
+#cp $HOME/skywater/pdk/skywater130/sky130A/libs.tech/magic/sky130A.magicrc $HOME/sky130-mpw2-fulgor/magicrc
+
+#echo "################# Installing Precheck #################"
+#git clone https://github.com/efabless/open_mpw_precheck.git
+#export TARGET_PATH="$HOME/caravel_fulgor_opamp"
+#export PDK_PATH="$HOME/skywater/pdk/skywater130"
diff --git a/xschem/DFF.sch b/xschem/DFF.sch
new file mode 100644
index 0000000..c834907
--- /dev/null
+++ b/xschem/DFF.sch
@@ -0,0 +1,64 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 100 -20 160 -20 { lab=CLK}
+N 140 20 160 20 { lab=Q}
+N 210 40 210 60 { lab=vss}
+N 210 -60 210 -40 { lab=D}
+N 140 260 160 260 { lab=P1}
+N 210 280 210 300 { lab=vss}
+N 210 180 210 200 { lab=D}
+N 140 20 140 100 { lab=Q}
+N 140 100 300 140 { lab=Q}
+N 300 140 300 240 { lab=Q}
+N 260 240 300 240 { lab=Q}
+N 120 220 160 220 { lab=P}
+N 120 140 120 220 { lab=P}
+N 120 140 300 100 { lab=P}
+N 300 -0 300 100 { lab=P}
+N 260 0 300 -0 { lab=P}
+N 260 500 280 500 { lab=P2}
+N 210 520 210 540 { lab=vss}
+N 260 740 280 740 { lab=Reset}
+N 210 760 210 780 { lab=vss}
+N 210 660 210 680 { lab=D}
+N 120 620 120 720 { lab=P2}
+N 120 720 160 720 { lab=P2}
+N 260 700 300 700 { lab=P1}
+N 300 620 300 700 { lab=P1}
+N 210 420 210 440 { lab=D}
+N 140 470 140 580 { lab=P1}
+N 140 260 140 470 { lab=P1}
+N 140 480 160 480 { lab=P1}
+N 140 580 300 620 { lab=P1}
+N 260 460 300 460 { lab=P}
+N 300 380 300 460 { lab=P}
+N 120 320 300 380 { lab=P}
+N 120 220 120 320 { lab=P}
+N 280 500 300 500 { lab=P2}
+N 300 500 300 580 { lab=P2}
+N 120 620 300 580 { lab=P2}
+N 300 240 380 240 { lab=Q}
+N 280 740 370 740 { lab=Reset}
+N 210 -70 210 -60 { lab=D}
+C {ipin.sym} 210 -70 1 0 {name=p1 lab=D}
+C {ipin.sym} 100 -20 0 0 {name=p2 lab=CLK}
+C {opin.sym} 380 240 0 0 {name=p3 lab=Q}
+C {lab_pin.sym} 210 60 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 140 220 0 0 {name=l2 sig_type=std_logic lab=P}
+C {lab_pin.sym} 210 300 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 210 180 1 0 {name=l5 sig_type=std_logic lab=D}
+C {lab_pin.sym} 210 540 1 1 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 210 660 3 1 {name=l7 sig_type=std_logic lab=D}
+C {lab_pin.sym} 210 420 1 0 {name=l8 sig_type=std_logic lab=D}
+C {lab_wire.sym} 290 700 0 0 {name=l9 sig_type=std_logic lab=P1}
+C {lab_wire.sym} 290 500 0 0 {name=l10 sig_type=std_logic lab=P2}
+C {ipin.sym} 370 740 2 0 {name=p4 lab=Reset}
+C {iopin.sym} 210 780 1 0 {name=p5 lab=vss}
+C {nor.sym} 210 0 0 0 {name=x1}
+C {nor.sym} 210 240 0 0 {name=x2}
+C {nor.sym} 210 480 0 1 {name=x3}
+C {nor.sym} 210 720 0 1 {name=x4}
diff --git a/xschem/DFF.sym b/xschem/DFF.sym
new file mode 100644
index 0000000..37d092d
--- /dev/null
+++ b/xschem/DFF.sym
@@ -0,0 +1,34 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -30 -30 -30 30 {}
+L 4 30 -30 30 30 {}
+L 4 -50 -30 -30 -30 {}
+L 4 -50 0 -30 0 {}
+L 4 30 -30 50 -30 {}
+L 4 0 40 0 60 {}
+L 4 -30 -40 -30 -30 {}
+L 4 -30 -40 30 -40 {}
+L 4 30 -40 30 -30 {}
+L 4 -30 30 -30 40 {}
+L 4 -30 40 30 40 {}
+L 4 30 30 30 40 {}
+L 7 0 -60 0 -40 {}
+B 5 -52.5 -32.5 -47.5 -27.5 {name=D dir=in }
+B 5 -52.5 -2.5 -47.5 2.5 {name=CLK dir=in }
+B 5 47.5 -32.5 52.5 -27.5 {name=Q dir=out }
+B 5 -2.5 57.5 2.5 62.5 {name=Reset dir=in }
+B 5 -2.5 -62.5 2.5 -57.5 {name=vss dir=inout }
+T {@symname} 8.5 44 0 0 0.3 0.3 {}
+T {@name} 15 -52 0 0 0.2 0.2 {}
+T {D} -25 -34 0 0 0.2 0.2 {}
+T {CLK} -25 -4 0 0 0.2 0.2 {}
+T {Q} 25 -34 0 1 0.2 0.2 {}
+T {Reset} -15 26 0 0 0.2 0.2 {}
+T {vss} -5 -54 0 1 0.2 0.2 {}
diff --git a/xschem/DFlipFlop.sch b/xschem/DFlipFlop.sch
new file mode 100644
index 0000000..f8435cd
--- /dev/null
+++ b/xschem/DFlipFlop.sch
@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 150 -210 210 -210 { lab=D_d}
+N 280 -290 280 -250 { lab=vdd}
+N 300 -90 300 -60 { lab=vss}
+N 570 -210 640 -210 { lab=Q}
+N 640 -210 650 -210 { lab=Q}
+N 150 -130 210 -130 { lab=nD_d}
+N 350 -130 390 -130 { lab=nA}
+N 350 -210 390 -210 { lab=A}
+N 390 -210 430 -210 { lab=A}
+N 390 -130 430 -130 { lab=nA}
+N 520 -90 520 -60 { lab=vss}
+N 500 -90 500 -60 { lab=nCLK}
+N 500 -280 500 -250 { lab=vdd}
+N 280 -90 280 -60 { lab=CLK}
+N 570 -130 640 -130 { lab=nQ}
+N 640 -130 650 -130 { lab=nQ}
+N -130 -170 -100 -170 { lab=D}
+N -100 -170 -60 -170 { lab=D}
+N 0 -260 0 -230 { lab=vdd}
+N 0 -110 0 -80 { lab=vss}
+N 60 -150 90 -150 { lab=nD_d}
+N 90 -150 90 -130 { lab=nD_d}
+N 90 -130 150 -130 { lab=nD_d}
+N 60 -190 90 -190 { lab=D_d}
+N 90 -210 90 -190 { lab=D_d}
+N 90 -210 150 -210 { lab=D_d}
+C {iopin.sym} 280 -290 3 0 {name=p1 lab=vdd}
+C {iopin.sym} 300 -60 1 0 {name=p3 lab=vss}
+C {opin.sym} 650 -210 0 0 {name=p7 lab=Q}
+C {lab_pin.sym} 520 -60 3 0 {name=l7 lab=vss}
+C {lab_pin.sym} 500 -280 1 0 {name=l8 lab=vdd}
+C {lab_wire.sym} 380 -130 0 1 {name=l19 lab=nA}
+C {opin.sym} 650 -130 0 0 {name=p2 lab=nQ}
+C {lab_wire.sym} 380 -210 0 1 {name=l1 lab=A}
+C {ipin.sym} -130 -170 0 0 {name=p6 lab=D}
+C {lab_wire.sym} 150 -210 0 0 {name=l27 lab=D_d}
+C {lab_wire.sym} 150 -130 0 0 {name=l28 lab=nD_d}
+C {ipin.sym} 280 -60 3 0 {name=p4 lab=CLK}
+C {ipin.sym} 500 -60 3 0 {name=p5 lab=nCLK}
+C {lab_pin.sym} 0 -260 1 0 {name=l2 lab=vdd}
+C {lab_pin.sym} 0 -80 3 0 {name=l3 lab=vss}
+C {clock_inverter.sym} 0 -170 0 0 {name=x1}
+C {latch_diff.sym} 280 -170 0 0 {name=x2}
+C {latch_diff.sym} 500 -170 0 0 {name=x3}
diff --git a/xschem/DFlipFlop.sym b/xschem/DFlipFlop.sym
new file mode 100644
index 0000000..3498bba
--- /dev/null
+++ b/xschem/DFlipFlop.sym
@@ -0,0 +1,40 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 -40 70 -40 {}
+L 4 50 40 70 40 {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 0 -50 0 {}
+L 4 -50 -60 50 -60 {}
+L 4 -50 60 50 60 {}
+L 4 -50 -10 -40 -0 {}
+L 4 -50 10 -40 -0 {}
+L 4 -50 -60 -50 60 {}
+L 4 50 -60 50 60 {}
+L 4 -70 40 -50 40 {}
+L 4 -50 30 -40 40 {}
+L 4 -50 50 -40 40 {}
+L 7 0 -80 0 -60 {}
+L 7 0 60 0 80 {}
+B 5 -2.5 -82.5 2.5 -77.5 {name=vdd dir=inout }
+B 5 67.5 -42.5 72.5 -37.5 {name=Q dir=out }
+B 5 67.5 37.5 72.5 42.5 {name=nQ dir=out }
+B 5 -2.5 77.5 2.5 82.5 {name=vss dir=inout }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=D dir=in }
+B 5 -72.5 -2.5 -67.5 2.5 {name=CLK dir=in }
+B 5 -72.5 37.5 -67.5 42.5 {name=nCLK dir=in }
+T {@symname} 7 64 0 0 0.3 0.3 {}
+T {@name} -15 -52 0 0 0.2 0.2 {}
+T {vdd} -14 -85 3 1 0.2 0.2 {}
+T {Q} 45 -44 0 1 0.2 0.2 {}
+T {nQ} 45 36 0 1 0.2 0.2 {}
+T {vss} -6 85 1 1 0.2 0.2 {}
+T {D} -45 -44 0 0 0.2 0.2 {}
+T {CLK} -35 -4 0 0 0.2 0.2 {}
+T {nCLK} -35 36 0 0 0.2 0.2 {}
diff --git a/xschem/PFD.sch b/xschem/PFD.sch
new file mode 100644
index 0000000..e32e606
--- /dev/null
+++ b/xschem/PFD.sch
@@ -0,0 +1,40 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 30 60 30 130 { lab=Reset}
+N 30 100 90 100 { lab=Reset}
+N 30 130 30 140 { lab=Reset}
+N 80 230 240 230 { lab=Down}
+N 240 120 240 230 { lab=Down}
+N 190 120 240 120 { lab=Down}
+N 190 80 240 80 { lab=Up}
+N 240 -30 240 80 { lab=Up}
+N 80 -30 240 -30 { lab=Up}
+N -60 230 -20 230 { lab=vdd}
+N -60 -30 -20 -30 { lab=vdd}
+N 30 -100 30 -60 { lab=vss}
+N 30 260 30 290 { lab=vss}
+N 140 150 140 170 { lab=vss}
+N 140 30 140 50 { lab=vdd}
+N -60 200 -20 200 { lab=B}
+N -60 -0 -20 0 { lab=A}
+N 240 -30 320 -30 { lab=Up}
+N 240 230 320 230 { lab=Down}
+N 0 100 30 100 { lab=Reset}
+C {DFF.sym} 30 0 0 0 {name=x1}
+C {DFF.sym} 30 200 2 1 {name=x2}
+C {iopin.sym} -60 -30 2 0 {name=p1 lab=vdd}
+C {iopin.sym} 30 -100 3 0 {name=p2 lab=vss}
+C {ipin.sym} -60 0 0 0 {name=p3 lab=A}
+C {ipin.sym} -60 200 0 0 {name=p4 lab=B}
+C {opin.sym} 320 230 0 0 {name=p5 lab=Down}
+C {opin.sym} 320 -30 0 0 {name=p6 lab=Up}
+C {lab_pin.sym} 30 290 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -60 230 0 0 {name=l2 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 140 170 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 30 1 0 {name=l4 sig_type=std_logic lab=vdd}
+C {iopin.sym} 0 100 2 0 {name=p7 lab=Reset}
+C {and_pfd.sym} 140 100 0 1 {name=x3}
diff --git a/xschem/PFD.sym b/xschem/PFD.sym
new file mode 100644
index 0000000..6c91f69
--- /dev/null
+++ b/xschem/PFD.sym
@@ -0,0 +1,48 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -40 -50 40 {}
+L 4 50 -40 50 40 {}
+L 4 50 -40 70 -40 {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 40 -50 40 {}
+L 4 50 40 70 40 {}
+L 4 -50 40 -50 60 {}
+L 4 -50 80 50 80 {}
+L 4 50 40 50 60 {}
+L 4 50 -60 50 -40 {}
+L 4 -50 -80 50 -80 {}
+L 4 -50 -60 -50 -40 {}
+L 4 50 -80 50 -60 {}
+L 4 -50 -80 -50 -60 {}
+L 4 -50 60 -50 80 {}
+L 4 50 60 50 80 {}
+L 4 -40 60 -40 80 {}
+L 4 -40 60 40 60 {}
+L 4 40 60 40 80 {}
+L 7 20 -100 20 -80 {}
+L 7 -20 -100 -20 -80 {}
+L 7 0 80 0 100 {}
+B 5 17.5 -102.5 22.5 -97.5 {name=vss dir=inout }
+B 5 -22.5 -102.5 -17.5 -97.5 {name=vdd dir=inout }
+B 5 67.5 -42.5 72.5 -37.5 {name=Up dir=out }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=A dir=in }
+B 5 -72.5 37.5 -67.5 42.5 {name=B dir=in }
+B 5 67.5 37.5 72.5 42.5 {name=Down dir=out }
+B 5 -2.5 97.5 2.5 102.5 {name=Reset dir=inout }
+T {@symname} 52.5 64 0 0 0.3 0.3 {}
+T {@name} -25 -2 0 0 0.2 0.2 {}
+T {vss} 6 -105 3 1 0.2 0.2 {}
+T {vdd} -34 -105 3 1 0.2 0.2 {}
+T {Up} 45 -44 0 1 0.2 0.2 {}
+T {A} -45 -44 0 0 0.2 0.2 {}
+T {B} -45 36 0 0 0.2 0.2 {}
+T {Down} 45 36 0 1 0.2 0.2 {}
+T {Reset} 14 115 1 1 0.2 0.2 {}
+T {Debug} 15 66 0 1 0.2 0.2 {}
diff --git a/xschem/PFD_pex_c.sym b/xschem/PFD_pex_c.sym
new file mode 100644
index 0000000..71929af
--- /dev/null
+++ b/xschem/PFD_pex_c.sym
@@ -0,0 +1,48 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -40 -50 40 {}
+L 4 50 -40 50 40 {}
+L 4 50 -40 70 -40 {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 40 -50 40 {}
+L 4 50 40 70 40 {}
+L 4 -50 40 -50 60 {}
+L 4 -50 80 50 80 {}
+L 4 50 40 50 60 {}
+L 4 50 -60 50 -40 {}
+L 4 -50 -80 50 -80 {}
+L 4 -50 -60 -50 -40 {}
+L 4 50 -80 50 -60 {}
+L 4 -50 -80 -50 -60 {}
+L 4 -50 60 -50 80 {}
+L 4 50 60 50 80 {}
+L 4 -40 60 -40 80 {}
+L 4 -40 60 40 60 {}
+L 4 40 60 40 80 {}
+L 7 20 -100 20 -80 {}
+L 7 -20 -100 -20 -80 {}
+L 7 0 80 0 100 {}
+B 5 17.5 -102.5 22.5 -97.5 {name=vss dir=inout }
+B 5 -22.5 -102.5 -17.5 -97.5 {name=vdd dir=inout }
+B 5 67.5 -42.5 72.5 -37.5 {name=Up dir=out }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=A dir=in }
+B 5 -72.5 37.5 -67.5 42.5 {name=B dir=in }
+B 5 67.5 37.5 72.5 42.5 {name=Down dir=out }
+B 5 -2.5 97.5 2.5 102.5 {name=Reset dir=inout }
+T {@symname} 52.5 64 0 0 0.3 0.3 {}
+T {@name} -25 -2 0 0 0.2 0.2 {}
+T {vss} 6 -105 3 1 0.2 0.2 {}
+T {vdd} -34 -105 3 1 0.2 0.2 {}
+T {Up} 45 -44 0 1 0.2 0.2 {}
+T {A} -45 -44 0 0 0.2 0.2 {}
+T {B} -45 36 0 0 0.2 0.2 {}
+T {Down} 45 36 0 1 0.2 0.2 {}
+T {Reset} 14 115 1 1 0.2 0.2 {}
+T {Debug} 15 66 0 1 0.2 0.2 {}
diff --git a/xschem/analog_wrapper_tb.sch b/xschem/analog_wrapper_tb.sch
index 736a27c..20590e8 100644
--- a/xschem/analog_wrapper_tb.sch
+++ b/xschem/analog_wrapper_tb.sch
@@ -73,21 +73,21 @@
N -60 -70 0 -70 { lab=#net26}
N -60 -50 0 -50 { lab=#net27}
C {user_analog_project_wrapper.sym} 150 -110 0 0 {name=x1}
-C {devices/vsource.sym} 590 -220 0 0 {name=V1 value="PWL(0.0 0 400u 0 5.4m 3.3)"}
-C {devices/vsource.sym} 690 -220 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3 1.8)"}
-C {devices/vsource.sym} 780 -220 0 0 {name=V3 value="PWL(0.0 0 100u 0 5m 3.3)"}
-C {devices/bus_connect.sym} 660 10 1 1 {name=l1 lab=io_analog[4]}
-C {devices/gnd.sym} 730 -150 0 0 {name=l2 lab=GND}
-C {devices/bus_connect.sym} 630 30 1 0 {name=l3 lab=io_clamp_high[2:1]}
-C {devices/bus_connect.sym} 630 90 1 0 {name=l8 lab=io_clamp_high[0]}
-C {devices/lab_pin.sym} 570 30 0 0 {name=l11 sig_type=std_logic lab=io_clamp_high[2:0]}
-C {devices/lab_pin.sym} 570 10 0 0 {name=l12 sig_type=std_logic lab=io_analog[10:0]}
-C {devices/lab_pin.sym} 480 50 0 0 {name=l9 sig_type=std_logic lab=io_clamp_low[2:0]}
-C {devices/lab_pin.sym} 450 -50 0 0 {name=l4 sig_type=std_logic lab=io_oeb[26:0]}
-C {devices/lab_pin.sym} 450 -70 0 0 {name=l5 sig_type=std_logic lab=io_out[26:0]}
-C {devices/bus_connect.sym} 510 -50 0 0 {name=l6 lab=io_oeb[16:15]}
-C {devices/bus_connect.sym} 600 -50 0 0 {name=l7 lab=io_oeb[12:11]}
-C {devices/code_shown.sym} 920 -130 0 0 {name=s1 only_toplevel=false value=".param mc_mm_switch=0
+C {vsource.sym} 590 -220 0 0 {name=V1 value="PWL(0.0 0 400u 0 5.4m 3.3)"}
+C {vsource.sym} 690 -220 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3 1.8)"}
+C {vsource.sym} 780 -220 0 0 {name=V3 value="PWL(0.0 0 100u 0 5m 3.3)"}
+C {bus_connect.sym} 660 10 1 1 {name=l1 lab=io_analog[4]}
+C {gnd.sym} 730 -150 0 0 {name=l2 lab=GND}
+C {bus_connect.sym} 630 30 1 0 {name=l3 lab=io_clamp_high[2:1]}
+C {bus_connect.sym} 630 90 1 0 {name=l8 lab=io_clamp_high[0]}
+C {lab_pin.sym} 570 30 0 0 {name=l11 sig_type=std_logic lab=io_clamp_high[2:0]}
+C {lab_pin.sym} 570 10 0 0 {name=l12 sig_type=std_logic lab=io_analog[10:0]}
+C {lab_pin.sym} 480 50 0 0 {name=l9 sig_type=std_logic lab=io_clamp_low[2:0]}
+C {lab_pin.sym} 450 -50 0 0 {name=l4 sig_type=std_logic lab=io_oeb[26:0]}
+C {lab_pin.sym} 450 -70 0 0 {name=l5 sig_type=std_logic lab=io_out[26:0]}
+C {bus_connect.sym} 510 -50 0 0 {name=l6 lab=io_oeb[16:15]}
+C {bus_connect.sym} 600 -50 0 0 {name=l7 lab=io_oeb[12:11]}
+C {code_shown.sym} 920 -130 0 0 {name=s1 only_toplevel=false value=".param mc_mm_switch=0
.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
.control
diff --git a/xschem/and_pfd.sch b/xschem/and_pfd.sch
new file mode 100644
index 0000000..98b0aba
--- /dev/null
+++ b/xschem/and_pfd.sch
@@ -0,0 +1,173 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 60 160 60 220 { lab=#net1}
+N 60 20 60 100 { lab=out_nand}
+N 60 280 60 320 { lab=vss}
+N 60 320 260 320 { lab=vss}
+N 260 280 260 320 { lab=vss}
+N 260 170 260 220 { lab=#net2}
+N 260 20 260 100 { lab=out_nand}
+N 260 -80 260 -40 { lab=vdd}
+N 60 -80 260 -80 { lab=vdd}
+N 60 -80 60 -40 { lab=vdd}
+N 60 -10 260 -10 { lab=vdd}
+N 160 -80 160 -10 { lab=vdd}
+N 60 60 260 60 { lab=out_nand}
+N 60 130 150 130 { lab=vss}
+N 60 250 260 250 { lab=vss}
+N 160 250 160 320 { lab=vss}
+N 170 130 260 130 { lab=vss}
+N 260 160 260 170 { lab=#net2}
+N -40 130 20 130 { lab=A}
+N -40 250 20 250 { lab=B}
+N 300 250 360 250 { lab=A}
+N 300 130 360 130 { lab=B}
+N 300 -10 360 -10 { lab=B}
+N -40 -10 20 -10 { lab=A}
+N -40 -80 60 -80 { lab=vdd}
+N -40 320 60 320 { lab=vss}
+N 260 60 360 60 { lab=out_nand}
+N 490 30 490 100 { lab=out}
+N 420 0 450 0 { lab=out_nand}
+N 420 0 420 130 { lab=out_nand}
+N 420 130 450 130 { lab=out_nand}
+N 360 60 420 60 { lab=out_nand}
+N 260 320 490 320 { lab=vss}
+N 490 160 490 320 { lab=vss}
+N 490 -80 490 -30 { lab=vdd}
+N 260 -80 490 -80 { lab=vdd}
+N 490 60 600 60 { lab=out}
+N 490 0 560 0 { lab=vdd}
+N 560 -80 560 0 { lab=vdd}
+N 490 -80 560 -80 { lab=vdd}
+N 490 130 580 130 { lab=vss}
+N 580 130 580 320 { lab=vss}
+N 490 320 580 320 { lab=vss}
+N 150 130 170 130 { lab=vss}
+N 160 130 160 250 { lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} 40 130 0 0 {name=M1
+L=0.15
+W=0.45
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 40 -10 0 0 {name=M2
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 40 250 0 0 {name=M3
+L=0.15
+W=0.45
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 280 130 0 1 {name=M4
+L=0.15
+W=0.45
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 280 250 0 1 {name=M5
+L=0.15
+W=0.45
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 280 -10 0 1 {name=M6
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -40 -80 2 0 {name=p1 lab=vdd}
+C {iopin.sym} -40 320 2 0 {name=p2 lab=vss}
+C {opin.sym} 600 60 0 0 {name=p3 lab=out}
+C {ipin.sym} -40 130 0 0 {name=p4 lab=A}
+C {ipin.sym} -40 250 0 0 {name=p5 lab=B}
+C {lab_pin.sym} -40 -10 0 0 {name=l1 sig_type=std_logic lab=A}
+C {lab_pin.sym} 360 -10 2 0 {name=l2 sig_type=std_logic lab=B}
+C {lab_pin.sym} 360 130 2 0 {name=l3 sig_type=std_logic lab=B}
+C {lab_pin.sym} 360 250 2 0 {name=l4 sig_type=std_logic lab=A}
+C {sky130_fd_pr/pfet_01v8.sym} 470 0 0 0 {name=M7
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 470 130 0 0 {name=M8
+L=0.15
+W=0.45
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 310 60 0 1 {name=l5 sig_type=std_logic lab=out_nand}
diff --git a/xschem/and_pfd.sym b/xschem/and_pfd.sym
new file mode 100644
index 0000000..833b9df
--- /dev/null
+++ b/xschem/and_pfd.sym
@@ -0,0 +1,32 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 30 0 50 0 {}
+L 4 -50 -20 -30 -20 {}
+L 4 -50 20 -30 20 {}
+L 4 -30 -30 -30 30 {}
+L 4 -30 -30 -0 -30 {}
+L 4 -30 30 -0 30 {}
+L 4 -3 30 2 30 {}
+L 4 -2 -30 2 -30 {}
+L 7 0 -50 0 -30 {}
+L 7 0 30 0 50 {}
+B 5 -2.5 -52.5 2.5 -47.5 {name=vdd dir=inout }
+B 5 47.5 -2.5 52.5 2.5 {name=out dir=out }
+B 5 -52.5 -22.5 -47.5 -17.5 {name=A dir=in }
+B 5 -52.5 17.5 -47.5 22.5 {name=B dir=in }
+B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout }
+A 4 -0.5 0 30.10398644698074 274.7636416907262 170.4727166185477 {}
+T {@symname} 4 34 0 0 0.3 0.3 {}
+T {@name} -25 -12 0 0 0.2 0.2 {}
+T {vdd} -14 -55 3 1 0.2 0.2 {}
+T {out} 55 -14 0 1 0.2 0.2 {}
+T {A} -45 -34 0 0 0.2 0.2 {}
+T {B} -45 6 0 0 0.2 0.2 {}
+T {vss} -6 55 1 1 0.2 0.2 {}
diff --git a/xschem/bias.sch b/xschem/bias.sch
new file mode 100644
index 0000000..375151d
--- /dev/null
+++ b/xschem/bias.sch
@@ -0,0 +1,480 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 470 -700 470 -660 { lab=#net1}
+N 190 -860 190 -800 { lab=vdd}
+N 470 -860 470 -800 { lab=vdd}
+N 190 -700 190 -660 { lab=vbp1}
+N 270 -770 430 -770 { lab=vbp1}
+N 190 -710 270 -710 { lab=vbp1}
+N 270 -770 270 -710 { lab=vbp1}
+N 110 -630 190 -630 { lab=vdd}
+N 110 -770 190 -770 { lab=vdd}
+N 470 -770 550 -770 { lab=vdd}
+N 470 -630 550 -630 { lab=vdd}
+N 190 -740 190 -710 { lab=vbp1}
+N 230 -770 270 -770 { lab=vbp1}
+N 470 -600 470 -540 { lab=iref_0}
+N 190 -710 190 -700 { lab=vbp1}
+N 470 -740 470 -700 { lab=#net1}
+N 470 -540 470 -520 { lab=iref_0}
+N 740 -700 740 -660 { lab=#net2}
+N 740 -860 740 -800 { lab=vdd}
+N 740 -770 820 -770 { lab=vdd}
+N 740 -630 820 -630 { lab=vdd}
+N 740 -600 740 -540 { lab=iref_1}
+N 740 -740 740 -700 { lab=#net2}
+N 740 -540 740 -520 { lab=iref_1}
+N 640 -770 700 -770 { lab=vbp1}
+N 640 -630 700 -630 { lab=iref}
+N 990 -700 990 -660 { lab=#net3}
+N 990 -860 990 -800 { lab=vdd}
+N 990 -770 1070 -770 { lab=vdd}
+N 990 -630 1070 -630 { lab=vdd}
+N 990 -600 990 -540 { lab=iref_2}
+N 990 -740 990 -700 { lab=#net3}
+N 990 -540 990 -520 { lab=iref_2}
+N 890 -770 950 -770 { lab=vbp1}
+N 890 -630 950 -630 { lab=iref}
+N 1230 -700 1230 -660 { lab=#net4}
+N 1230 -860 1230 -800 { lab=vdd}
+N 1230 -770 1310 -770 { lab=vdd}
+N 1230 -630 1310 -630 { lab=vdd}
+N 1230 -600 1230 -540 { lab=iref_3}
+N 1230 -740 1230 -700 { lab=#net4}
+N 1230 -540 1230 -520 { lab=iref_3}
+N 1130 -770 1190 -770 { lab=vbp1}
+N 1130 -630 1190 -630 { lab=iref}
+N 1480 -700 1480 -660 { lab=#net5}
+N 1480 -860 1480 -800 { lab=vdd}
+N 1480 -770 1560 -770 { lab=vdd}
+N 1480 -630 1560 -630 { lab=vdd}
+N 1480 -600 1480 -540 { lab=iref_4}
+N 1480 -740 1480 -700 { lab=#net5}
+N 1480 -540 1480 -520 { lab=iref_4}
+N 1380 -770 1440 -770 { lab=vbp1}
+N 1380 -630 1440 -630 { lab=iref}
+N 470 -190 470 -150 { lab=#net6}
+N 470 -350 470 -290 { lab=vdd}
+N 470 -260 550 -260 { lab=vdd}
+N 470 -120 550 -120 { lab=vdd}
+N 470 -90 470 -30 { lab=iref_5}
+N 470 -230 470 -190 { lab=#net6}
+N 470 -30 470 -10 { lab=iref_5}
+N 740 -190 740 -150 { lab=#net7}
+N 740 -350 740 -290 { lab=vdd}
+N 740 -260 820 -260 { lab=vdd}
+N 740 -120 820 -120 { lab=vdd}
+N 740 -90 740 -30 { lab=iref_6}
+N 740 -230 740 -190 { lab=#net7}
+N 740 -30 740 -10 { lab=iref_6}
+N 640 -260 700 -260 { lab=vbp1}
+N 640 -120 700 -120 { lab=iref}
+N 990 -190 990 -150 { lab=#net8}
+N 990 -350 990 -290 { lab=vdd}
+N 990 -260 1070 -260 { lab=vdd}
+N 990 -120 1070 -120 { lab=vdd}
+N 990 -90 990 -30 { lab=iref_7}
+N 990 -230 990 -190 { lab=#net8}
+N 990 -30 990 -10 { lab=iref_7}
+N 890 -260 950 -260 { lab=vbp1}
+N 890 -120 950 -120 { lab=iref}
+N 1230 -190 1230 -150 { lab=#net9}
+N 1230 -350 1230 -290 { lab=vdd}
+N 1230 -260 1310 -260 { lab=vdd}
+N 1230 -120 1310 -120 { lab=vdd}
+N 1230 -90 1230 -30 { lab=iref_8}
+N 1230 -230 1230 -190 { lab=#net9}
+N 1230 -30 1230 -10 { lab=iref_8}
+N 1130 -260 1190 -260 { lab=vbp1}
+N 1130 -120 1190 -120 { lab=iref}
+N 1480 -190 1480 -150 { lab=#net10}
+N 1480 -350 1480 -290 { lab=vdd}
+N 1480 -260 1560 -260 { lab=vdd}
+N 1480 -120 1560 -120 { lab=vdd}
+N 1480 -90 1480 -30 { lab=iref_cp_9}
+N 1480 -230 1480 -190 { lab=#net10}
+N 1480 -30 1480 -10 { lab=iref_cp_9}
+N 1380 -260 1440 -260 { lab=vbp1}
+N 1380 -120 1440 -120 { lab=iref}
+N 370 -260 430 -260 { lab=vbp1}
+N 370 -120 430 -120 { lab=iref}
+N 230 -630 430 -630 { lab=iref}
+N 190 -600 190 -500 { lab=iref}
+N 190 -550 280 -550 { lab=iref}
+N 280 -630 280 -550 { lab=iref}
+C {lab_pin.sym} 110 -770 0 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 550 -770 2 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 470 -860 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 340 -770 0 0 {name=l5 sig_type=std_logic lab=vbp1}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 210 -630 0 1 {name=M1
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 210 -770 0 1 {name=M2
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 450 -770 0 0 {name=M3
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 450 -630 0 0 {name=M4
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {iopin.sym} 190 -500 1 0 {name=p8 lab=iref}
+C {iopin.sym} 190 -860 3 0 {name=p9 lab=vdd}
+C {lab_pin.sym} 550 -630 2 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 110 -630 0 0 {name=l9 sig_type=std_logic lab=vdd}
+C {opin.sym} 470 -520 1 0 {name=p1 lab=iref_0}
+C {lab_pin.sym} 820 -770 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 740 -860 1 0 {name=l3 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 720 -770 0 0 {name=M5
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 720 -630 0 0 {name=M6
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 820 -630 2 0 {name=l4 sig_type=std_logic lab=vdd}
+C {opin.sym} 740 -520 1 0 {name=p2 lab=iref_1}
+C {lab_wire.sym} 680 -770 0 0 {name=l10 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1070 -770 2 0 {name=l13 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 990 -860 1 0 {name=l14 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 970 -770 0 0 {name=M7
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 970 -630 0 0 {name=M8
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1070 -630 2 0 {name=l15 sig_type=std_logic lab=vdd}
+C {opin.sym} 990 -520 1 0 {name=p3 lab=iref_2}
+C {lab_wire.sym} 930 -770 0 0 {name=l16 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1310 -770 2 0 {name=l18 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1230 -860 1 0 {name=l19 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1210 -770 0 0 {name=M9
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1210 -630 0 0 {name=M10
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1310 -630 2 0 {name=l20 sig_type=std_logic lab=vdd}
+C {opin.sym} 1230 -520 1 0 {name=p4 lab=iref_3}
+C {lab_wire.sym} 1170 -770 0 0 {name=l21 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1560 -770 2 0 {name=l23 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1480 -860 1 0 {name=l24 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1460 -770 0 0 {name=M11
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1460 -630 0 0 {name=M12
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1560 -630 2 0 {name=l25 sig_type=std_logic lab=vdd}
+C {opin.sym} 1480 -520 1 0 {name=p5 lab=iref_4}
+C {lab_wire.sym} 1420 -770 0 0 {name=l26 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 550 -260 2 0 {name=l28 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 470 -350 1 0 {name=l29 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 450 -260 0 0 {name=M13
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 450 -120 0 0 {name=M14
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 550 -120 2 0 {name=l30 sig_type=std_logic lab=vdd}
+C {opin.sym} 470 -10 1 0 {name=p6 lab=iref_5}
+C {lab_pin.sym} 820 -260 2 0 {name=l31 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 740 -350 1 0 {name=l32 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 720 -260 0 0 {name=M15
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 720 -120 0 0 {name=M16
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 820 -120 2 0 {name=l33 sig_type=std_logic lab=vdd}
+C {opin.sym} 740 -10 1 0 {name=p7 lab=iref_6}
+C {lab_wire.sym} 680 -260 0 0 {name=l34 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1070 -260 2 0 {name=l36 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 990 -350 1 0 {name=l37 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 970 -260 0 0 {name=M17
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 970 -120 0 0 {name=M18
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1070 -120 2 0 {name=l38 sig_type=std_logic lab=vdd}
+C {opin.sym} 990 -10 1 0 {name=p10 lab=iref_7}
+C {lab_wire.sym} 930 -260 0 0 {name=l39 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1310 -260 2 0 {name=l41 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1230 -350 1 0 {name=l42 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1210 -260 0 0 {name=M19
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1210 -120 0 0 {name=M20
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1310 -120 2 0 {name=l43 sig_type=std_logic lab=vdd}
+C {opin.sym} 1230 -10 1 0 {name=p11 lab=iref_8}
+C {lab_wire.sym} 1170 -260 0 0 {name=l44 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1560 -260 2 0 {name=l46 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1480 -350 1 0 {name=l47 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1460 -260 0 0 {name=M21
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1460 -120 0 0 {name=M22
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1560 -120 2 0 {name=l48 sig_type=std_logic lab=vdd}
+C {opin.sym} 1480 -10 1 0 {name=p12 lab=iref_9}
+C {lab_wire.sym} 1420 -260 0 0 {name=l49 sig_type=std_logic lab=vbp1}
+C {lab_wire.sym} 410 -260 0 0 {name=l51 sig_type=std_logic lab=vbp1}
+C {lab_wire.sym} 360 -630 0 0 {name=l1 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 670 -630 0 0 {name=l12 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 920 -630 0 0 {name=l17 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 1170 -630 0 0 {name=l22 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 1410 -630 0 0 {name=l27 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 400 -120 0 0 {name=l35 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 670 -120 0 0 {name=l40 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 920 -120 0 0 {name=l45 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 1160 -120 0 0 {name=l50 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 1410 -120 0 0 {name=l52 sig_type=std_logic lab=iref}
diff --git a/xschem/bias.sym b/xschem/bias.sym
new file mode 100644
index 0000000..2f3e347
--- /dev/null
+++ b/xschem/bias.sym
@@ -0,0 +1,53 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -110 -40 -10 {}
+L 4 40 -110 40 -10 {}
+L 4 -40 110 40 110 {}
+L 4 -40 -110 40 -110 {}
+L 4 40 -90 60 -90 {}
+L 4 40 -70 60 -70 {}
+L 4 40 -50 60 -50 {}
+L 4 40 -30 60 -30 {}
+L 4 40 -10 60 -10 {}
+L 4 40 10 60 10 {}
+L 4 40 30 60 30 {}
+L 4 40 50 60 50 {}
+L 4 40 70 60 70 {}
+L 4 40 90 60 90 {}
+L 4 40 -10 40 110 {}
+L 4 -40 -10 -40 110 {}
+L 7 0 -130 0 -110 {}
+L 7 0 110 0 130 {}
+B 5 -2.5 -132.5 2.5 -127.5 {name=vdd dir=inout }
+B 5 -2.5 127.5 2.5 132.5 {name=iref dir=inout }
+B 5 57.5 -92.5 62.5 -87.5 {name=iref_0 dir=out }
+B 5 57.5 -72.5 62.5 -67.5 {name=iref_1 dir=out }
+B 5 57.5 -52.5 62.5 -47.5 {name=iref_2 dir=out }
+B 5 57.5 -32.5 62.5 -27.5 {name=iref_3 dir=out }
+B 5 57.5 -12.5 62.5 -7.5 {name=iref_4 dir=out }
+B 5 57.5 7.5 62.5 12.5 {name=iref_5 dir=out }
+B 5 57.5 27.5 62.5 32.5 {name=iref_6 dir=out }
+B 5 57.5 47.5 62.5 52.5 {name=iref_7 dir=out }
+B 5 57.5 67.5 62.5 72.5 {name=iref_8 dir=out }
+B 5 57.5 87.5 62.5 92.5 {name=iref_9 dir=out }
+T {@symname} 34 114 0 0 0.3 0.3 {}
+T {@name} 5 -122 0 0 0.2 0.2 {}
+T {vdd} -14 -135 3 1 0.2 0.2 {}
+T {iref} -6 135 1 1 0.2 0.2 {}
+T {iref_0} 35 -94 0 1 0.2 0.2 {}
+T {iref_1} 35 -74 0 1 0.2 0.2 {}
+T {iref_2} 35 -54 0 1 0.2 0.2 {}
+T {iref_3} 35 -34 0 1 0.2 0.2 {}
+T {iref_4} 35 -14 0 1 0.2 0.2 {}
+T {iref_5} 35 6 0 1 0.2 0.2 {}
+T {iref_6} 35 26 0 1 0.2 0.2 {}
+T {iref_7} 35 46 0 1 0.2 0.2 {}
+T {iref_8} 35 66 0 1 0.2 0.2 {}
+T {iref_9} 35 86 0 1 0.2 0.2 {}
diff --git a/xschem/bias_pex_c.sym b/xschem/bias_pex_c.sym
new file mode 100644
index 0000000..29cf8e2
--- /dev/null
+++ b/xschem/bias_pex_c.sym
@@ -0,0 +1,56 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -110 -40 -10 {}
+L 4 40 -110 40 -10 {}
+L 4 -40 110 40 110 {}
+L 4 -40 -110 40 -110 {}
+L 4 40 -90 60 -90 {}
+L 4 40 -70 60 -70 {}
+L 4 40 -50 60 -50 {}
+L 4 40 -30 60 -30 {}
+L 4 40 -10 60 -10 {}
+L 4 40 10 60 10 {}
+L 4 40 30 60 30 {}
+L 4 40 50 60 50 {}
+L 4 40 70 60 70 {}
+L 4 40 90 60 90 {}
+L 4 40 -10 40 110 {}
+L 4 -40 -10 -40 110 {}
+L 7 0 -130 0 -110 {}
+L 7 -20 110 -20 130 {}
+L 7 20 110 20 130 {}
+B 5 -2.5 -132.5 2.5 -127.5 {name=vdd dir=inout }
+B 5 -22.5 127.5 -17.5 132.5 {name=iref dir=inout }
+B 5 17.5 127.5 22.5 132.5 {name=vss dir=inout }
+B 5 57.5 -92.5 62.5 -87.5 {name=iref_0 dir=out }
+B 5 57.5 -72.5 62.5 -67.5 {name=iref_1 dir=out }
+B 5 57.5 -52.5 62.5 -47.5 {name=iref_2 dir=out }
+B 5 57.5 -32.5 62.5 -27.5 {name=iref_3 dir=out }
+B 5 57.5 -12.5 62.5 -7.5 {name=iref_4 dir=out }
+B 5 57.5 7.5 62.5 12.5 {name=iref_5 dir=out }
+B 5 57.5 27.5 62.5 32.5 {name=iref_6 dir=out }
+B 5 57.5 47.5 62.5 52.5 {name=iref_7 dir=out }
+B 5 57.5 67.5 62.5 72.5 {name=iref_8 dir=out }
+B 5 57.5 87.5 62.5 92.5 {name=iref_9 dir=out }
+T {@symname} 34 114 0 0 0.3 0.3 {}
+T {@name} 5 -122 0 0 0.2 0.2 {}
+T {vdd} -14 -135 3 1 0.2 0.2 {}
+T {iref} -26 135 1 1 0.2 0.2 {}
+T {vss} 14 135 1 1 0.2 0.2 {}
+T {iref_0} 35 -94 0 1 0.2 0.2 {}
+T {iref_1} 35 -74 0 1 0.2 0.2 {}
+T {iref_2} 35 -54 0 1 0.2 0.2 {}
+T {iref_3} 35 -34 0 1 0.2 0.2 {}
+T {iref_4} 35 -14 0 1 0.2 0.2 {}
+T {iref_5} 35 6 0 1 0.2 0.2 {}
+T {iref_6} 35 26 0 1 0.2 0.2 {}
+T {iref_7} 35 46 0 1 0.2 0.2 {}
+T {iref_8} 35 66 0 1 0.2 0.2 {}
+T {iref_9} 35 86 0 1 0.2 0.2 {}
diff --git a/xschem/buffer_no_inv_x05.sch b/xschem/buffer_no_inv_x05.sch
new file mode 100644
index 0000000..246cd4e
--- /dev/null
+++ b/xschem/buffer_no_inv_x05.sch
@@ -0,0 +1,21 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1440 -410 1520 -410 { lab=in}
+N 1560 -510 1560 -460 { lab=avdd1p8}
+N 1560 -360 1560 -310 { lab=avss1p8}
+N 1650 -410 1760 -410 { lab=#net1}
+N 1800 -510 1800 -460 { lab=avdd1p8}
+N 1800 -360 1800 -310 { lab=avss1p8}
+N 1890 -410 2000 -410 { lab=out}
+C {ipin.sym} 1440 -410 0 0 {name=p4 lab=in}
+C {iopin.sym} 1560 -510 0 0 {name=p15 lab=avdd1p8}
+C {iopin.sym} 1560 -310 0 0 {name=p16 lab=avss1p8}
+C {inverter_min.sym} 1580 -410 0 0 {name=x1}
+C {opin.sym} 2000 -410 0 0 {name=p1 lab=out}
+C {inverter_min.sym} 1820 -410 0 0 {name=x2}
+C {lab_wire.sym} 1800 -500 0 0 {name=l1 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 1800 -310 0 0 {name=l2 sig_type=std_logic lab=avss1p8}
diff --git a/xschem/buffer_no_inv_x05.sym b/xschem/buffer_no_inv_x05.sym
new file mode 100644
index 0000000..fc966fb
--- /dev/null
+++ b/xschem/buffer_no_inv_x05.sym
@@ -0,0 +1,26 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -90 -170 -70 -170 {}
+L 4 -70 -210 -70 -130 {}
+L 4 -70 -130 10 -170 {}
+L 4 -70 -210 10 -170 {}
+L 4 10 -170 30 -170 {}
+L 7 -50 -220 -50 -200 {}
+L 7 -50 -140 -50 -120 {}
+B 5 -52.5 -222.5 -47.5 -217.5 {name=avdd1p8 dir=inout }
+B 5 -92.5 -172.5 -87.5 -167.5 {name=in dir=in }
+B 5 -52.5 -122.5 -47.5 -117.5 {name=avss1p8 dir=inout }
+B 5 27.5 -172.5 32.5 -167.5 {name=out dir=out}
+T {@symname} 10 -210 0 0 0.3 0.3 {}
+T {@name} -60 -170 0 0 0.2 0.2 {}
+T {avdd1p8} 0 -230 0 1 0.2 0.2 {}
+T {in} -110 -180 0 0 0.2 0.2 {}
+T {avss1p8} -50 -120 0 1 0.2 0.2 {}
+T {out} 40 -180 0 0 0.2 0.2 {}
diff --git a/xschem/buffer_salida.sch b/xschem/buffer_salida.sch
new file mode 100644
index 0000000..828e5c8
--- /dev/null
+++ b/xschem/buffer_salida.sch
@@ -0,0 +1,138 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -300 250 -180 { lab=#net1}
+N 250 -240 340 -240 { lab=#net1}
+N 160 -150 210 -150 { lab=in}
+N 160 -330 160 -150 { lab=in}
+N 160 -330 210 -330 { lab=in}
+N 100 -240 160 -240 { lab=in}
+N 250 -420 250 -360 { lab=vdd}
+N 250 -120 250 -60 { lab=vss}
+N 250 -330 350 -330 { lab=vdd}
+N 250 -150 350 -150 { lab=vss}
+N 590 -300 590 -180 { lab=#net2}
+N 590 -240 680 -240 { lab=#net2}
+N 500 -150 550 -150 { lab=#net1}
+N 500 -330 500 -150 { lab=#net1}
+N 500 -330 550 -330 { lab=#net1}
+N 590 -330 690 -330 { lab=vdd}
+N 590 -150 690 -150 { lab=vss}
+N 910 -300 910 -180 { lab=out}
+N 910 -240 1000 -240 { lab=out}
+N 820 -150 870 -150 { lab=#net2}
+N 820 -330 820 -150 { lab=#net2}
+N 820 -330 870 -330 { lab=#net2}
+N 910 -330 1010 -330 { lab=vdd}
+N 910 -150 1010 -150 { lab=vss}
+N 590 -120 590 -90 { lab=vss}
+N 590 -390 590 -360 { lab=vdd}
+N 590 -90 590 -70 { lab=vss}
+N 590 -410 590 -390 { lab=vdd}
+N 910 -120 910 -90 { lab=vss}
+N 910 -90 910 -70 { lab=vss}
+N 910 -390 910 -360 { lab=vdd}
+N 910 -410 910 -390 { lab=vdd}
+N 340 -240 500 -240 { lab=#net1}
+N 680 -240 820 -240 { lab=#net2}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -330 0 0 {name=M2
+L=0.15
+W=6
+nf=1
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 250 -60 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 -240 0 0 {name=p2 lab=in}
+C {sky130_fd_pr/nfet_01v8.sym} 230 -150 0 0 {name=M1
+L=0.15
+W=3
+nf=1
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 350 -150 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -330 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 250 -420 3 0 {name=p4 lab=vdd}
+C {sky130_fd_pr/pfet_01v8.sym} 570 -330 0 0 {name=M3
+L=0.15
+W=6
+nf=1
+mult=32
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 570 -150 0 0 {name=M4
+L=0.15
+W=3
+nf=1
+mult=32
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 690 -150 2 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 690 -330 2 0 {name=l4 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8.sym} 890 -330 0 0 {name=M5
+L=0.15
+W=6
+nf=1
+mult=256
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {opin.sym} 1000 -240 0 0 {name=p6 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 890 -150 0 0 {name=M6
+L=0.15
+W=3
+nf=1
+mult=256
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 1010 -150 2 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1010 -330 2 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 590 -410 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 590 -70 3 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 910 -70 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 910 -410 1 0 {name=l10 sig_type=std_logic lab=vdd}
diff --git a/xschem/buffer_salida.sym b/xschem/buffer_salida.sym
new file mode 100644
index 0000000..cdda9c9
--- /dev/null
+++ b/xschem/buffer_salida.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/buffer_salida_pex_c.sym b/xschem/buffer_salida_pex_c.sym
new file mode 100644
index 0000000..0c2e821
--- /dev/null
+++ b/xschem/buffer_salida_pex_c.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/cap1_loop_filter.sch b/xschem/cap1_loop_filter.sch
new file mode 100644
index 0000000..c3dc0df
--- /dev/null
+++ b/xschem/cap1_loop_filter.sch
@@ -0,0 +1,12 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 420 -110 420 -80 { lab=in}
+N 420 -20 420 0 { lab=out}
+N 420 -0 420 30 { lab=out}
+C {iopin.sym} 420 -110 3 0 {name=p2 lab=in}
+C {iopin.sym} 420 30 1 0 {name=p1 lab=out}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 420 -50 0 0 {name=C1 model=cap_mim_m3_1 W=25 L=25 MF=25 spiceprefix=X}
diff --git a/xschem/cap1_loop_filter.sym b/xschem/cap1_loop_filter.sym
new file mode 100644
index 0000000..69677d2
--- /dev/null
+++ b/xschem/cap1_loop_filter.sym
@@ -0,0 +1,21 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -30 -20 -30 20 {}
+L 4 30 -20 30 20 {}
+L 4 -30 20 30 20 {}
+L 4 -30 -20 30 -20 {}
+L 7 0 -40 0 -20 {}
+L 7 0 20 0 40 {}
+B 5 -2.5 -42.5 2.5 -37.5 {name=in dir=inout }
+B 5 -2.5 37.5 2.5 42.5 {name=out dir=inout }
+T {@symname} 20 24 0 0 0.3 0.3 {}
+T {@name} 25 -32 0 0 0.2 0.2 {}
+T {in} -14 -45 3 1 0.2 0.2 {}
+T {out} -6 45 1 1 0.2 0.2 {}
diff --git a/xschem/cap2_loop_filter.sch b/xschem/cap2_loop_filter.sch
new file mode 100644
index 0000000..46db674
--- /dev/null
+++ b/xschem/cap2_loop_filter.sch
@@ -0,0 +1,12 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 420 -110 420 -80 { lab=in}
+N 420 -20 420 0 { lab=out}
+N 420 -0 420 30 { lab=out}
+C {iopin.sym} 420 -110 3 0 {name=p2 lab=in}
+C {iopin.sym} 420 30 1 0 {name=p1 lab=out}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 420 -50 0 0 {name=C1 model=cap_mim_m3_1 W=20 L=20 MF=9 spiceprefix=X}
diff --git a/xschem/cap2_loop_filter.sym b/xschem/cap2_loop_filter.sym
new file mode 100644
index 0000000..69677d2
--- /dev/null
+++ b/xschem/cap2_loop_filter.sym
@@ -0,0 +1,21 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -30 -20 -30 20 {}
+L 4 30 -20 30 20 {}
+L 4 -30 20 30 20 {}
+L 4 -30 -20 30 -20 {}
+L 7 0 -40 0 -20 {}
+L 7 0 20 0 40 {}
+B 5 -2.5 -42.5 2.5 -37.5 {name=in dir=inout }
+B 5 -2.5 37.5 2.5 42.5 {name=out dir=inout }
+T {@symname} 20 24 0 0 0.3 0.3 {}
+T {@name} 25 -32 0 0 0.2 0.2 {}
+T {in} -14 -45 3 1 0.2 0.2 {}
+T {out} -6 45 1 1 0.2 0.2 {}
diff --git a/xschem/cap3_loop_filter.sch b/xschem/cap3_loop_filter.sch
new file mode 100644
index 0000000..b95316f
--- /dev/null
+++ b/xschem/cap3_loop_filter.sch
@@ -0,0 +1,12 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 420 -110 420 -80 { lab=in}
+N 420 -20 420 0 { lab=out}
+N 420 -0 420 30 { lab=out}
+C {iopin.sym} 420 -110 3 0 {name=p2 lab=in}
+C {iopin.sym} 420 30 1 0 {name=p1 lab=out}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 420 -50 0 0 {name=C1 model=cap_mim_m3_1 W=20 L=20 MF=4 spiceprefix=X}
diff --git a/xschem/cap3_loop_filter.sym b/xschem/cap3_loop_filter.sym
new file mode 100644
index 0000000..69677d2
--- /dev/null
+++ b/xschem/cap3_loop_filter.sym
@@ -0,0 +1,21 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -30 -20 -30 20 {}
+L 4 30 -20 30 20 {}
+L 4 -30 20 30 20 {}
+L 4 -30 -20 30 -20 {}
+L 7 0 -40 0 -20 {}
+L 7 0 20 0 40 {}
+B 5 -2.5 -42.5 2.5 -37.5 {name=in dir=inout }
+B 5 -2.5 37.5 2.5 42.5 {name=out dir=inout }
+T {@symname} 20 24 0 0 0.3 0.3 {}
+T {@name} 25 -32 0 0 0.2 0.2 {}
+T {in} -14 -45 3 1 0.2 0.2 {}
+T {out} -6 45 1 1 0.2 0.2 {}
diff --git a/xschem/charge_pump.sch b/xschem/charge_pump.sch
new file mode 100644
index 0000000..7a02fd5
--- /dev/null
+++ b/xschem/charge_pump.sch
@@ -0,0 +1,277 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -30 190 -30 230 { lab=nswitch}
+N -100 190 -30 190 { lab=nswitch}
+N -30 190 30 190 { lab=nswitch}
+N -30 290 -30 320 { lab=vss}
+N -30 320 70 320 { lab=vss}
+N 70 220 70 320 { lab=vss}
+N 70 190 170 190 { lab=vss}
+N 170 190 170 320 { lab=vss}
+N 70 320 170 320 { lab=vss}
+N -130 190 -130 320 { lab=vss}
+N -130 320 -30 320 { lab=vss}
+N -30 260 70 260 { lab=vss}
+N -220 320 -130 320 { lab=vss}
+N -100 -150 30 -150 { lab=pswitch}
+N -30 -180 -30 -150 { lab=pswitch}
+N 70 -260 70 -180 { lab=vdd}
+N -30 -260 -30 -240 { lab=vdd}
+N -30 -210 70 -210 { lab=vdd}
+N 70 -150 170 -150 { lab=vdd}
+N 170 -260 170 -150 { lab=vdd}
+N 70 -260 170 -260 { lab=vdd}
+N -130 -260 -130 -150 { lab=vdd}
+N -130 -110 -130 -90 { lab=nUp}
+N -160 -40 -120 -40 { lab=nUp}
+N -130 130 -130 150 { lab=Down}
+N -170 70 -130 70 { lab=Down}
+N 70 0 170 0 { lab=out}
+N -230 -260 -130 -260 { lab=vdd}
+N -250 320 -220 320 { lab=vss}
+N -90 -210 -90 -200 { lab=Up}
+N -90 -210 -70 -210 { lab=Up}
+N -90 260 -70 260 { lab=nDown}
+N -120 260 -120 300 { lab=nDown}
+N -120 260 -90 260 { lab=nDown}
+N -130 -260 70 -260 { lab=vdd}
+N -210 190 -160 190 { lab=iref}
+N -220 -150 -160 -150 { lab=biasp}
+N 70 120 70 160 { lab=#net1}
+N 70 -0 70 60 { lab=out}
+N 70 -30 70 0 { lab=out}
+N 70 -120 70 -90 { lab=#net2}
+N -130 70 -100 70 { lab=Down}
+N -120 -40 -100 -40 { lab=nUp}
+N -130 -90 -130 -40 { lab=nUp}
+N -60 -10 -60 0 { lab=pswitch}
+N -60 0 20 0 { lab=pswitch}
+N 20 -80 20 0 { lab=pswitch}
+N -60 -80 20 -80 { lab=pswitch}
+N -60 -80 -60 -70 { lab=pswitch}
+N -30 -90 -30 -80 { lab=pswitch}
+N -60 -40 -40 -40 { lab=vdd}
+N -60 100 -60 110 { lab=nswitch}
+N -60 110 20 110 { lab=nswitch}
+N 20 30 20 110 { lab=nswitch}
+N -60 30 20 30 { lab=nswitch}
+N -60 30 -60 40 { lab=nswitch}
+N -130 70 -130 130 { lab=Down}
+N -60 70 -40 70 { lab=vss}
+N -30 110 -30 190 { lab=nswitch}
+N -30 -150 -30 -90 { lab=pswitch}
+N -40 140 -30 140 { lab=nswitch}
+N -40 -100 -30 -100 { lab=pswitch}
+N -690 220 -690 280 { lab=vss}
+N -740 190 -690 190 { lab=vss}
+N -650 190 -600 190 { lab=iref}
+N -620 120 -620 190 { lab=iref}
+N -690 120 -620 120 { lab=iref}
+N -690 80 -690 160 { lab=iref}
+N -820 320 -530 320 { lab=vss}
+N -690 280 -690 320 { lab=vss}
+N -440 220 -440 280 { lab=vss}
+N -440 190 -360 190 { lab=vss}
+N -440 -230 -440 -180 { lab=vdd}
+N -520 -150 -440 -150 { lab=vdd}
+N -530 190 -480 190 { lab=iref}
+N -400 -150 -340 -150 { lab=biasp}
+N -340 -150 -340 -90 { lab=biasp}
+N -440 -90 -340 -90 { lab=biasp}
+N -440 -120 -440 -90 { lab=biasp}
+N -440 -90 -440 -70 { lab=biasp}
+N -440 120 -440 160 { lab=biasp}
+N -340 -150 -320 -150 { lab=biasp}
+N -320 -150 -220 -150 { lab=biasp}
+N -540 -260 -240 -260 { lab=vdd}
+N -240 -260 -230 -260 { lab=vdd}
+N -440 -260 -440 -230 { lab=vdd}
+N -520 -260 -520 -150 { lab=vdd}
+N -360 320 -250 320 { lab=vss}
+N -520 320 -360 320 { lab=vss}
+N -530 320 -520 320 { lab=vss}
+N -440 280 -440 320 { lab=vss}
+N -600 190 -530 190 { lab=iref}
+N -440 -70 -440 120 { lab=biasp}
+N -790 190 -740 190 { lab=vss}
+N -790 190 -790 320 { lab=vss}
+N -360 190 -340 190 { lab=vss}
+N -340 190 -340 320 { lab=vss}
+N -340 -90 -340 -60 { lab=biasp}
+N 70 60 70 120 {}
+N 70 -90 70 -30 {}
+C {iopin.sym} -820 320 2 0 {name=p1 lab=vss}
+C {iopin.sym} -540 -260 2 0 {name=p2 lab=vdd}
+C {ipin.sym} -170 70 0 0 {name=p3 lab=Down}
+C {ipin.sym} -160 -40 0 0 {name=p4 lab=nUp}
+C {ipin.sym} -90 -200 3 0 {name=p5 lab=Up}
+C {ipin.sym} -120 300 2 0 {name=p6 lab=nDown}
+C {opin.sym} 170 0 0 0 {name=p7 lab=out}
+C {lab_wire.sym} 0 -150 0 0 {name=l4 sig_type=std_logic lab=pswitch}
+C {lab_wire.sym} 0 190 0 0 {name=l3 sig_type=std_logic lab=nswitch}
+C {sky130_fd_pr/pfet_01v8.sym} 50 -150 0 0 {name=M1
+L=0.15
+W=1.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 50 190 0 0 {name=M2
+L=0.15
+W=0.75
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -130 -130 3 0 {name=M3
+L=0.15
+W=1.5
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -50 -210 0 0 {name=M4
+L=0.15
+W=1.5
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} -130 170 1 0 {name=M5
+L=0.15
+W=0.75
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} -50 260 0 0 {name=M6
+L=0.15
+W=0.75
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -80 -40 0 0 {name=M7
+L=2
+W=4.5
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} -40 70 2 0 {name=l8 lab=vss}
+C {lab_pin.sym} -40 -40 2 0 {name=l1 lab=vdd}
+C {sky130_fd_pr/nfet_01v8.sym} -80 70 0 0 {name=M8
+L=1.5
+W=0.75
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -40 140 2 0 {name=p8 lab=nswitch}
+C {iopin.sym} -40 -100 2 0 {name=p11 lab=pswitch}
+C {sky130_fd_pr/nfet_01v8.sym} -670 190 0 1 {name=M9
+L=0.15
+W=0.75
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} -460 190 0 0 {name=M10
+L=0.15
+W=0.75
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -420 -150 0 1 {name=M11
+L=0.15
+W=1.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} -690 80 1 0 {name=p9 lab=iref}
+C {lab_pin.sym} -210 190 0 0 {name=l10 lab=iref}
+C {lab_wire.sym} -260 -150 0 0 {name=l2 sig_type=std_logic lab=biasp}
+C {iopin.sym} -340 -60 1 0 {name=p10 lab=biasp}
diff --git a/xschem/charge_pump.sym b/xschem/charge_pump.sym
new file mode 100644
index 0000000..177239c
--- /dev/null
+++ b/xschem/charge_pump.sym
@@ -0,0 +1,65 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -60 -40 -60 40 {}
+L 4 70 -40 70 40 {}
+L 4 -80 -60 -60 -60 {}
+L 4 -80 -20 -60 -20 {}
+L 4 70 0 90 0 {}
+L 4 -80 20 -60 20 {}
+L 4 -80 60 -60 60 {}
+L 4 -60 -70 -60 -50 {}
+L 4 -60 50 -60 70 {}
+L 4 -60 60 -60 70 {}
+L 4 70 40 70 70 {}
+L 4 70 -60 70 -40 {}
+L 4 -60 -50 -60 -40 {}
+L 4 -60 40 -60 50 {}
+L 4 -60 -80 -60 -70 {}
+L 4 -60 -80 40 -80 {}
+L 4 70 -80 70 -60 {}
+L 4 -60 70 -60 80 {}
+L 4 -60 80 40 80 {}
+L 4 70 70 70 80 {}
+L 4 40 -80 70 -80 {}
+L 4 40 80 70 80 {}
+L 4 -40 60 -40 80 {}
+L 4 -40 60 50 60 {}
+L 4 50 60 50 80 {}
+L 4 -40 -100 -40 -80 {}
+L 7 20 -100 20 -80 {}
+L 7 50 -100 50 -80 {}
+L 7 -30 80 -30 100 {}
+L 7 0 80 0 100 {}
+L 7 30 80 30 100 {}
+B 5 17.5 -102.5 22.5 -97.5 {name=vdd dir=inout }
+B 5 -82.5 -62.5 -77.5 -57.5 {name=Up dir=in }
+B 5 -82.5 -22.5 -77.5 -17.5 {name=nUp dir=in }
+B 5 87.5 -2.5 92.5 2.5 {name=out dir=out }
+B 5 -82.5 17.5 -77.5 22.5 {name=Down dir=in }
+B 5 -82.5 57.5 -77.5 62.5 {name=nDown dir=in }
+B 5 47.5 -102.5 52.5 -97.5 {name=vss dir=inout }
+B 5 -42.5 -102.5 -37.5 -97.5 {name=iref dir=in }
+B 5 -32.5 97.5 -27.5 102.5 {name=nswitch dir=inout }
+B 5 -2.5 97.5 2.5 102.5 {name=pswitch dir=inout }
+B 5 27.5 97.5 32.5 102.5 {name=biasp dir=inout }
+T {@symname} 80 84 0 0 0.3 0.3 {}
+T {@name} -35 -12 0 0 0.2 0.2 {}
+T {vdd} 6 -105 3 1 0.2 0.2 {}
+T {Up} -55 -74 0 0 0.2 0.2 {}
+T {nUp} -55 -34 0 0 0.2 0.2 {}
+T {out} 65 -14 0 1 0.2 0.2 {}
+T {Down} -55 6 0 0 0.2 0.2 {}
+T {nDown} -55 46 0 0 0.2 0.2 {}
+T {vss} 44 -85 1 1 0.2 0.2 {}
+T {iref} -54 -105 3 1 0.2 0.2 {}
+T {nswitch} -16 125 1 1 0.2 0.2 {}
+T {pswitch} 14 125 1 1 0.2 0.2 {}
+T {Debug} -15 66 0 0 0.2 0.2 {}
+T {biasp} 44 115 1 1 0.2 0.2 {}
diff --git a/xschem/charge_pump_pex_c.sym b/xschem/charge_pump_pex_c.sym
new file mode 100644
index 0000000..0030ebb
--- /dev/null
+++ b/xschem/charge_pump_pex_c.sym
@@ -0,0 +1,65 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -60 -40 -60 40 {}
+L 4 70 -40 70 40 {}
+L 4 -80 -60 -60 -60 {}
+L 4 -80 -20 -60 -20 {}
+L 4 70 0 90 0 {}
+L 4 -80 20 -60 20 {}
+L 4 -80 60 -60 60 {}
+L 4 -60 -70 -60 -50 {}
+L 4 -60 50 -60 70 {}
+L 4 -60 60 -60 70 {}
+L 4 70 40 70 70 {}
+L 4 70 -60 70 -40 {}
+L 4 -60 -50 -60 -40 {}
+L 4 -60 40 -60 50 {}
+L 4 -60 -80 -60 -70 {}
+L 4 -60 -80 40 -80 {}
+L 4 70 -80 70 -60 {}
+L 4 -60 70 -60 80 {}
+L 4 -60 80 40 80 {}
+L 4 70 70 70 80 {}
+L 4 40 -80 70 -80 {}
+L 4 40 80 70 80 {}
+L 4 -40 60 -40 80 {}
+L 4 -40 60 50 60 {}
+L 4 50 60 50 80 {}
+L 4 -40 -100 -40 -80 {}
+L 7 20 -100 20 -80 {}
+L 7 50 -100 50 -80 {}
+L 7 -30 80 -30 100 {}
+L 7 0 80 0 100 {}
+L 7 30 80 30 100 {}
+B 5 17.5 -102.5 22.5 -97.5 {name=vdd dir=inout }
+B 5 -82.5 -62.5 -77.5 -57.5 {name=Up dir=in }
+B 5 -82.5 -22.5 -77.5 -17.5 {name=nUp dir=in }
+B 5 87.5 -2.5 92.5 2.5 {name=out dir=out }
+B 5 -82.5 17.5 -77.5 22.5 {name=Down dir=in }
+B 5 -82.5 57.5 -77.5 62.5 {name=nDown dir=in }
+B 5 47.5 -102.5 52.5 -97.5 {name=vss dir=inout }
+B 5 -42.5 -102.5 -37.5 -97.5 {name=iref dir=in }
+B 5 -32.5 97.5 -27.5 102.5 {name=nswitch dir=inout }
+B 5 -2.5 97.5 2.5 102.5 {name=pswitch dir=inout }
+B 5 27.5 97.5 32.5 102.5 {name=biasp dir=inout }
+T {@symname} 80 84 0 0 0.3 0.3 {}
+T {@name} -35 -12 0 0 0.2 0.2 {}
+T {vdd} 6 -105 3 1 0.2 0.2 {}
+T {Up} -55 -74 0 0 0.2 0.2 {}
+T {nUp} -55 -34 0 0 0.2 0.2 {}
+T {out} 65 -14 0 1 0.2 0.2 {}
+T {Down} -55 6 0 0 0.2 0.2 {}
+T {nDown} -55 46 0 0 0.2 0.2 {}
+T {vss} 44 -85 1 1 0.2 0.2 {}
+T {iref} -54 -105 3 1 0.2 0.2 {}
+T {nswitch} -16 125 1 1 0.2 0.2 {}
+T {pswitch} 14 125 1 1 0.2 0.2 {}
+T {Debug} -15 66 0 0 0.2 0.2 {}
+T {biasp} 44 115 1 1 0.2 0.2 {}
diff --git a/xschem/clock_inverter.sch b/xschem/clock_inverter.sch
new file mode 100644
index 0000000..7d62fc3
--- /dev/null
+++ b/xschem/clock_inverter.sch
@@ -0,0 +1,41 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -430 0 -400 0 { lab=CLK}
+N -280 -200 -280 -170 { lab=vdd}
+N -280 -70 -280 -40 { lab=vss}
+N -280 180 -280 210 { lab=vss}
+N -280 50 -280 80 { lab=vdd}
+N -360 -120 -320 -120 { lab=CLK}
+N -400 0 -360 0 { lab=CLK}
+N -70 -200 -70 -170 { lab=vdd}
+N -70 -70 -70 -40 { lab=vss}
+N -360 130 -320 130 { lab=CLK}
+N -360 10 -360 130 { lab=CLK}
+N -360 -110 -360 10 { lab=CLK}
+N -360 -120 -360 -110 { lab=CLK}
+N -40 20 -40 50 { lab=vdd}
+N -40 230 -40 260 { lab=vss}
+N -190 130 -130 130 { lab=#net1}
+N 50 -120 140 -120 { lab=CLK_d}
+N 50 130 140 130 { lab=nCLK_d}
+N 20 -120 50 -120 { lab=CLK_d}
+N -190 -120 -110 -120 { lab=#net2}
+C {ipin.sym} -430 0 0 0 {name=p4 lab=CLK}
+C {iopin.sym} -280 -200 3 0 {name=p1 lab=vdd}
+C {lab_pin.sym} -280 -40 3 0 {name=l5 lab=vss}
+C {trans_gate.sym} -40 130 0 0 {name=x5}
+C {iopin.sym} -280 210 1 0 {name=p11 lab=vss}
+C {lab_pin.sym} -280 50 1 0 {name=l12 lab=vdd}
+C {lab_pin.sym} -70 -200 1 0 {name=l9 lab=vdd}
+C {lab_pin.sym} -70 -40 3 0 {name=l10 lab=vss}
+C {lab_pin.sym} -40 20 1 0 {name=l13 lab=vdd}
+C {lab_pin.sym} -40 260 3 0 {name=l14 lab=vss}
+C {opin.sym} 140 130 0 0 {name=p16 lab=nCLK_d}
+C {opin.sym} 140 -120 0 0 {name=p17 lab=CLK_d}
+C {inverter_cp_x1.sym} -50 -120 0 0 {name=x1}
+C {inverter_cp_x1.sym} -260 -120 0 0 {name=x2}
+C {inverter_cp_x1.sym} -260 130 0 0 {name=x3}
diff --git a/xschem/clock_inverter.sym b/xschem/clock_inverter.sym
new file mode 100644
index 0000000..971d7ed
--- /dev/null
+++ b/xschem/clock_inverter.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -40 -40 40 {}
+L 4 40 -40 40 40 {}
+L 4 40 -20 60 -20 {}
+L 4 -60 0 -40 0 {}
+L 4 40 20 60 20 {}
+L 4 -40 -40 40 -40 {}
+L 4 -40 40 40 40 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout }
+B 5 57.5 -22.5 62.5 -17.5 {name=CLK_d dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=CLK dir=in }
+B 5 57.5 17.5 62.5 22.5 {name=nCLK_d dir=out }
+B 5 -2.5 57.5 2.5 62.5 {name=vss dir=inout }
+T {@symname} 9 44 0 0 0.3 0.3 {}
+T {@name} 15 -52 0 0 0.2 0.2 {}
+T {vdd} -14 -65 3 1 0.2 0.2 {}
+T {CLK_d} 35 -24 0 1 0.2 0.2 {}
+T {CLK} -35 -4 0 0 0.2 0.2 {}
+T {nCLK_d} 35 16 0 1 0.2 0.2 {}
+T {vss} -6 65 1 1 0.2 0.2 {}
diff --git a/xschem/csvco.sch b/xschem/csvco.sch
new file mode 100644
index 0000000..5f70a27
--- /dev/null
+++ b/xschem/csvco.sch
@@ -0,0 +1,93 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -210 -150 -210 -120 { lab=vdd}
+N -320 10 -280 10 { lab=vctrl}
+N -510 10 -470 10 { lab=vss}
+N -470 40 -470 80 { lab=vss}
+N -430 10 -390 10 { lab=vctrl}
+N -470 -130 -470 -100 { lab=vdd}
+N -500 -70 -470 -70 { lab=vdd}
+N -210 60 -210 100 { lab=vss}
+N -170 60 -170 70 { lab=D0}
+N -430 -70 -280 -70 { lab=vbp}
+N -470 -30 -420 -30 { lab=vbp}
+N -420 -30 -410 -30 { lab=vbp}
+N -410 -70 -410 -30 { lab=vbp}
+N -470 -30 -470 -20 { lab=vbp}
+N -470 -40 -470 -30 { lab=vbp}
+N -390 10 -320 10 { lab=vctrl}
+N -350 10 -350 70 { lab=vctrl}
+N -340 -30 -280 -30 { lab=out}
+N -140 -30 -70 -30 { lab=out1}
+N -70 -30 30 -30 { lab=out1}
+N -10 -70 30 -70 { lab=vbp}
+N -10 10 30 10 { lab=vctrl}
+N 100 -150 100 -120 { lab=vdd}
+N 100 60 100 100 { lab=vss}
+N 140 60 140 70 { lab=D0}
+N 170 -30 240 -30 { lab=out2}
+N 240 -30 340 -30 { lab=out2}
+N 300 -70 340 -70 { lab=vbp}
+N 300 10 340 10 { lab=vctrl}
+N 410 -150 410 -120 { lab=vdd}
+N 410 60 410 100 { lab=vss}
+N 450 60 450 70 { lab=D0}
+N 480 -30 540 -30 { lab=out}
+C {lab_pin.sym} -210 -150 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {ipin.sym} -350 70 3 0 {name=p83 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} -510 10 2 1 {name=l83 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} -450 10 0 1 {name=M1
+L=0.15
+W=1.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -470 80 3 1 {name=p84 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} -450 -70 0 1 {name=M2
+L=0.15
+W=1.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -470 -130 1 1 {name=p86 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -500 -70 2 1 {name=l87 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} -350 -70 0 1 {name=l88 sig_type=std_logic lab=vbp}
+C {opin.sym} 540 -30 2 1 {name=p1 sig_type=std_logic lab=out}
+C {lab_pin.sym} -210 100 3 0 {name=l31 sig_type=std_logic lab=vss}
+C {ipin.sym} -170 70 3 0 {name=p6 sig_type=std_logic lab=D0}
+C {lab_wire.sym} -340 -30 0 1 {name=l8 sig_type=std_logic lab=out}
+C {lab_wire.sym} -70 -30 0 1 {name=l12 sig_type=std_logic lab=out1}
+C {lab_pin.sym} -10 -70 0 0 {name=l32 sig_type=std_logic lab=vbp}
+C {lab_pin.sym} -10 10 0 0 {name=l33 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 100 -150 1 0 {name=l34 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 100 100 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 70 3 0 {name=l46 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 300 -70 0 0 {name=l36 sig_type=std_logic lab=vbp}
+C {lab_pin.sym} 300 10 0 0 {name=l37 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 410 -150 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 100 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 450 70 3 0 {name=l47 sig_type=std_logic lab=D0}
+C {lab_wire.sym} 240 -30 0 1 {name=l48 sig_type=std_logic lab=out2}
+C {csvco_branch.sym} -210 -30 0 0 {name=x1}
+C {csvco_branch.sym} 100 -30 0 0 {name=x2}
+C {csvco_branch.sym} 410 -30 0 0 {name=x3}
diff --git a/xschem/csvco.sym b/xschem/csvco.sym
new file mode 100644
index 0000000..52a2546
--- /dev/null
+++ b/xschem/csvco.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -70 0 -50 0 {}
+L 4 -50 40 -40 30 {}
+L 7 0 -70 0 -50 {}
+L 7 0 50 0 70 {}
+B 5 -2.5 -72.5 2.5 -67.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=D0 dir=in }
+B 5 -72.5 -2.5 -67.5 2.5 {name=vctrl dir=in }
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+A 4 -0.1779661016949153 0 50.00031671833042 89.79606673072159 360 {}
+A 4 -14 12.5 18.76832437912346 41.76029970389787 96.47940059220427 {}
+A 4 14 -12.5 18.76832437912346 221.7602997038979 96.47940059220427 {}
+T {@symname} 7.5 52 0 0 0.3 0.3 {}
+T {@name} -15.5 -42.5 0 0 0.2 0.2 {}
+T {vdd} -14.5 -71.5 3 1 0.2 0.2 {}
+T {out} 73.5 -13.5 0 1 0.2 0.2 {}
+T {D0} -66.5 27.5 0 0 0.2 0.2 {}
+T {vctrl} -73.5 -14 0 0 0.2 0.2 {}
+T {vss} -1.5 68.5 1 1 0.2 0.2 {}
diff --git a/xschem/csvco_branch.sch b/xschem/csvco_branch.sch
new file mode 100644
index 0000000..5c911f0
--- /dev/null
+++ b/xschem/csvco_branch.sch
@@ -0,0 +1,92 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 540 -300 540 -270 { lab=vdd_inv}
+N 540 -70 580 -70 { lab=vss}
+N 440 -220 500 -220 { lab=in}
+N 630 -220 700 -220 { lab=out}
+N 540 -350 540 -300 { lab=vdd_inv}
+N 540 -440 540 -410 { lab=vdd}
+N 540 -380 570 -380 { lab=vdd}
+N 540 -170 540 -100 { lab=vss_inv}
+N 540 -40 540 0 { lab=vss}
+N 460 -70 500 -70 { lab=vctrl}
+N 580 -190 580 -150 { lab=vss}
+N 580 -280 580 -250 { lab=vdd}
+N 700 -220 760 -220 { lab=out}
+N 900 -220 1440 -220 { lab=out}
+N 760 -220 900 -220 { lab=out}
+N 460 -380 500 -380 { lab=vbp}
+N 1440 -220 1490 -220 { lab=out}
+N 1070 -220 1070 -180 { lab=out}
+N 1000 -150 1030 -150 { lab=D0}
+N 1070 -150 1110 -150 { lab=vss}
+N 1070 -120 1070 -80 { lab=#net1}
+N 1070 -20 1070 20 { lab=vss}
+C {lab_pin.sym} 580 -70 2 0 {name=l3 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 520 -380 0 0 {name=M1
+L=0.15
+W=1.5
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 570 -380 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {ipin.sym} 460 -70 0 0 {name=p83 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 580 -150 3 0 {name=l127 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 580 -280 1 0 {name=l139 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 640 -220 0 1 {name=l106 sig_type=std_logic lab=out}
+C {ipin.sym} 460 -380 0 0 {name=p1 sig_type=std_logic lab=vbp}
+C {iopin.sym} 540 -440 3 0 {name=p6 sig_type=std_logic lab=vdd}
+C {iopin.sym} 540 0 1 0 {name=p7 sig_type=std_logic lab=vss}
+C {ipin.sym} 440 -220 0 0 {name=p8 sig_type=std_logic lab=in}
+C {opin.sym} 1490 -220 0 0 {name=p9 sig_type=std_logic lab=out}
+C {lab_wire.sym} 540 -340 3 0 {name=l1 sig_type=std_logic lab=vdd_inv}
+C {lab_wire.sym} 540 -160 3 0 {name=l4 sig_type=std_logic lab=vss_inv}
+C {sky130_fd_pr/nfet_01v8.sym} 520 -70 0 0 {name=M2
+L=0.15
+W=1.5
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1050 -150 0 0 {name=M4
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} 1000 -150 0 0 {name=p3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 1110 -150 2 0 {name=l8 sig_type=std_logic lab=vss}
+C {inverter_csvco.sym} 560 -220 0 0 {name=x1}
+C {capa.sym} 1070 -50 0 0 {name=C1
+m=1
+value=5.78f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1070 20 3 0 {name=l5 sig_type=std_logic lab=vss}
diff --git a/xschem/csvco_branch.sym b/xschem/csvco_branch.sym
new file mode 100644
index 0000000..0289106
--- /dev/null
+++ b/xschem/csvco_branch.sym
@@ -0,0 +1,36 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 0 -50 0 {}
+L 4 50 0 70 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -50 -70 -50 70 {}
+L 4 -50 70 50 70 {}
+L 4 50 -70 50 70 {}
+L 4 -50 -70 50 -70 {}
+L 4 40 70 40 90 {}
+L 7 0 -90 0 -70 {}
+L 7 0 70 0 90 {}
+B 5 -2.5 -92.5 2.5 -87.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=vbp sig_type=std_logic dir=in }
+B 5 -72.5 -2.5 -67.5 2.5 {name=in sig_type=std_logic dir=in }
+B 5 67.5 -2.5 72.5 2.5 {name=out sig_type=std_logic dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=vctrl sig_type=std_logic dir=in }
+B 5 -2.5 87.5 2.5 92.5 {name=vss sig_type=std_logic dir=inout }
+B 5 37.5 87.5 42.5 92.5 {name=D0 sig_type=std_logic dir=in }
+T {@symname} 58 54 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vdd} -4 -65 3 1 0.2 0.2 {}
+T {vbp} -45 -44 0 0 0.2 0.2 {}
+T {in} -45 -4 0 0 0.2 0.2 {}
+T {out} 45 -4 0 1 0.2 0.2 {}
+T {vctrl} -45 36 0 0 0.2 0.2 {}
+T {vss} 4 65 1 1 0.2 0.2 {}
+T {D0} 36 65 3 0 0.2 0.2 {}
diff --git a/xschem/csvco_branch_v2.sch b/xschem/csvco_branch_v2.sch
new file mode 100644
index 0000000..5cd32b9
--- /dev/null
+++ b/xschem/csvco_branch_v2.sch
@@ -0,0 +1,92 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 540 -300 540 -270 { lab=vdd_inv}
+N 540 -70 580 -70 { lab=vss}
+N 440 -220 500 -220 { lab=in}
+N 630 -220 700 -220 { lab=out}
+N 540 -350 540 -300 { lab=vdd_inv}
+N 540 -440 540 -410 { lab=vdd}
+N 540 -380 570 -380 { lab=vdd}
+N 540 -170 540 -100 { lab=vss_inv}
+N 540 -40 540 0 { lab=vss}
+N 460 -70 500 -70 { lab=vctrl}
+N 580 -190 580 -150 { lab=vss}
+N 580 -280 580 -250 { lab=vdd}
+N 700 -220 760 -220 { lab=out}
+N 900 -220 1440 -220 { lab=out}
+N 760 -220 900 -220 { lab=out}
+N 460 -380 500 -380 { lab=vbp}
+N 1440 -220 1490 -220 { lab=out}
+N 1070 -220 1070 -180 { lab=out}
+N 1000 -150 1030 -150 { lab=D0}
+N 1070 -150 1110 -150 { lab=vss}
+N 1070 -120 1070 -80 { lab=#net1}
+N 1070 -20 1070 20 { lab=vss}
+C {lab_pin.sym} 580 -70 2 0 {name=l3 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 520 -380 0 0 {name=M1
+L=0.15
+W=1.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 570 -380 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {ipin.sym} 460 -70 0 0 {name=p83 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 580 -150 3 0 {name=l127 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 580 -280 1 0 {name=l139 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 640 -220 0 1 {name=l106 sig_type=std_logic lab=out}
+C {ipin.sym} 460 -380 0 0 {name=p1 sig_type=std_logic lab=vbp}
+C {iopin.sym} 540 -440 3 0 {name=p6 sig_type=std_logic lab=vdd}
+C {iopin.sym} 540 0 1 0 {name=p7 sig_type=std_logic lab=vss}
+C {ipin.sym} 440 -220 0 0 {name=p8 sig_type=std_logic lab=in}
+C {opin.sym} 1490 -220 0 0 {name=p9 sig_type=std_logic lab=out}
+C {lab_wire.sym} 540 -340 3 0 {name=l1 sig_type=std_logic lab=vdd_inv}
+C {lab_wire.sym} 540 -160 3 0 {name=l4 sig_type=std_logic lab=vss_inv}
+C {sky130_fd_pr/nfet_01v8.sym} 520 -70 0 0 {name=M2
+L=0.15
+W=1.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1050 -150 0 0 {name=M4
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} 1000 -150 0 0 {name=p3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 1110 -150 2 0 {name=l8 sig_type=std_logic lab=vss}
+C {capa.sym} 1070 -50 0 0 {name=C1
+m=1
+value=5.78f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1070 20 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {inverter_csvco.sym} 560 -220 0 0 {name=x1}
diff --git a/xschem/csvco_branch_v2.sym b/xschem/csvco_branch_v2.sym
new file mode 100644
index 0000000..0289106
--- /dev/null
+++ b/xschem/csvco_branch_v2.sym
@@ -0,0 +1,36 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 0 -50 0 {}
+L 4 50 0 70 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -50 -70 -50 70 {}
+L 4 -50 70 50 70 {}
+L 4 50 -70 50 70 {}
+L 4 -50 -70 50 -70 {}
+L 4 40 70 40 90 {}
+L 7 0 -90 0 -70 {}
+L 7 0 70 0 90 {}
+B 5 -2.5 -92.5 2.5 -87.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=vbp sig_type=std_logic dir=in }
+B 5 -72.5 -2.5 -67.5 2.5 {name=in sig_type=std_logic dir=in }
+B 5 67.5 -2.5 72.5 2.5 {name=out sig_type=std_logic dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=vctrl sig_type=std_logic dir=in }
+B 5 -2.5 87.5 2.5 92.5 {name=vss sig_type=std_logic dir=inout }
+B 5 37.5 87.5 42.5 92.5 {name=D0 sig_type=std_logic dir=in }
+T {@symname} 58 54 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vdd} -4 -65 3 1 0.2 0.2 {}
+T {vbp} -45 -44 0 0 0.2 0.2 {}
+T {in} -45 -4 0 0 0.2 0.2 {}
+T {out} 45 -4 0 1 0.2 0.2 {}
+T {vctrl} -45 36 0 0 0.2 0.2 {}
+T {vss} 4 65 1 1 0.2 0.2 {}
+T {D0} 36 65 3 0 0.2 0.2 {}
diff --git a/xschem/csvco_pex_c.sym b/xschem/csvco_pex_c.sym
new file mode 100644
index 0000000..b24a424
--- /dev/null
+++ b/xschem/csvco_pex_c.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -70 0 -50 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -50 40 -40 30 {}
+L 7 0 -70 0 -50 {}
+L 7 0 50 0 70 {}
+B 5 -2.5 -72.5 2.5 -67.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -72.5 -2.5 -67.5 2.5 {name=vctrl dir=in }
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+B 5 -72.5 37.5 -67.5 42.5 {name=D0 dir=in }
+A 4 -0.1779661016949153 0 50.00031671833042 89.79606673072159 360 {}
+A 4 -14 12.5 18.76832437912346 41.76029970389787 96.47940059220427 {}
+A 4 14 -12.5 18.76832437912346 221.7602997038979 96.47940059220427 {}
+T {@symname} 7.5 52 0 0 0.3 0.3 {}
+T {@name} -15.5 -42.5 0 0 0.2 0.2 {}
+T {vdd} -14.5 -71.5 3 1 0.2 0.2 {}
+T {out} 73.5 -13.5 0 1 0.2 0.2 {}
+T {vctrl} -73.5 -14 0 0 0.2 0.2 {}
+T {vss} -1.5 68.5 1 1 0.2 0.2 {}
+T {D0} -73.5 26 0 0 0.2 0.2 {}
diff --git a/xschem/csvco_v2.sch b/xschem/csvco_v2.sch
new file mode 100644
index 0000000..c7f8414
--- /dev/null
+++ b/xschem/csvco_v2.sch
@@ -0,0 +1,93 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -210 -150 -210 -120 { lab=vdd}
+N -320 10 -280 10 { lab=vctrl}
+N -510 10 -470 10 { lab=vss}
+N -470 40 -470 80 { lab=vss}
+N -430 10 -390 10 { lab=vctrl}
+N -470 -130 -470 -100 { lab=vdd}
+N -500 -70 -470 -70 { lab=vdd}
+N -210 60 -210 100 { lab=vss}
+N -170 60 -170 70 { lab=D0}
+N -430 -70 -280 -70 { lab=vbp}
+N -470 -30 -420 -30 { lab=vbp}
+N -420 -30 -410 -30 { lab=vbp}
+N -410 -70 -410 -30 { lab=vbp}
+N -470 -30 -470 -20 { lab=vbp}
+N -470 -40 -470 -30 { lab=vbp}
+N -390 10 -320 10 { lab=vctrl}
+N -350 10 -350 70 { lab=vctrl}
+N -340 -30 -280 -30 { lab=out}
+N -140 -30 -70 -30 { lab=out1}
+N -70 -30 30 -30 { lab=out1}
+N -10 -70 30 -70 { lab=vbp}
+N -10 10 30 10 { lab=vctrl}
+N 100 -150 100 -120 { lab=vdd}
+N 100 60 100 100 { lab=vss}
+N 140 60 140 70 { lab=D0}
+N 170 -30 240 -30 { lab=out2}
+N 240 -30 340 -30 { lab=out2}
+N 300 -70 340 -70 { lab=vbp}
+N 300 10 340 10 { lab=vctrl}
+N 410 -150 410 -120 { lab=vdd}
+N 410 60 410 100 { lab=vss}
+N 450 60 450 70 { lab=D0}
+N 480 -30 540 -30 { lab=out}
+C {lab_pin.sym} -210 -150 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {ipin.sym} -350 70 3 0 {name=p83 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} -510 10 2 1 {name=l83 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} -450 10 0 1 {name=M1
+L=0.15
+W=1.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -470 80 3 1 {name=p84 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} -450 -70 0 1 {name=M2
+L=0.15
+W=1.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -470 -130 1 1 {name=p86 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -500 -70 2 1 {name=l87 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} -350 -70 0 1 {name=l88 sig_type=std_logic lab=vbp}
+C {opin.sym} 540 -30 2 1 {name=p1 sig_type=std_logic lab=out}
+C {lab_pin.sym} -210 100 3 0 {name=l31 sig_type=std_logic lab=vss}
+C {ipin.sym} -170 70 3 0 {name=p6 sig_type=std_logic lab=D0}
+C {lab_wire.sym} -340 -30 0 1 {name=l8 sig_type=std_logic lab=out}
+C {lab_wire.sym} -70 -30 0 1 {name=l12 sig_type=std_logic lab=out1}
+C {lab_pin.sym} -10 -70 0 0 {name=l32 sig_type=std_logic lab=vbp}
+C {lab_pin.sym} -10 10 0 0 {name=l33 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 100 -150 1 0 {name=l34 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 100 100 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 70 3 0 {name=l46 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 300 -70 0 0 {name=l36 sig_type=std_logic lab=vbp}
+C {lab_pin.sym} 300 10 0 0 {name=l37 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 410 -150 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 100 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 450 70 3 0 {name=l47 sig_type=std_logic lab=D0}
+C {lab_wire.sym} 240 -30 0 1 {name=l48 sig_type=std_logic lab=out2}
+C {csvco_branch_v2.sym} -210 -30 0 0 {name=x2}
+C {csvco_branch_v2.sym} 100 -30 0 0 {name=x3}
+C {csvco_branch_v2.sym} 410 -30 0 0 {name=x4}
diff --git a/xschem/csvco_v2.sym b/xschem/csvco_v2.sym
new file mode 100644
index 0000000..52a2546
--- /dev/null
+++ b/xschem/csvco_v2.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -70 0 -50 0 {}
+L 4 -50 40 -40 30 {}
+L 7 0 -70 0 -50 {}
+L 7 0 50 0 70 {}
+B 5 -2.5 -72.5 2.5 -67.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=D0 dir=in }
+B 5 -72.5 -2.5 -67.5 2.5 {name=vctrl dir=in }
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+A 4 -0.1779661016949153 0 50.00031671833042 89.79606673072159 360 {}
+A 4 -14 12.5 18.76832437912346 41.76029970389787 96.47940059220427 {}
+A 4 14 -12.5 18.76832437912346 221.7602997038979 96.47940059220427 {}
+T {@symname} 7.5 52 0 0 0.3 0.3 {}
+T {@name} -15.5 -42.5 0 0 0.2 0.2 {}
+T {vdd} -14.5 -71.5 3 1 0.2 0.2 {}
+T {out} 73.5 -13.5 0 1 0.2 0.2 {}
+T {D0} -66.5 27.5 0 0 0.2 0.2 {}
+T {vctrl} -73.5 -14 0 0 0.2 0.2 {}
+T {vss} -1.5 68.5 1 1 0.2 0.2 {}
diff --git a/xschem/csvco_v2_pex_c.sym b/xschem/csvco_v2_pex_c.sym
new file mode 100644
index 0000000..b24a424
--- /dev/null
+++ b/xschem/csvco_v2_pex_c.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -70 0 -50 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -50 40 -40 30 {}
+L 7 0 -70 0 -50 {}
+L 7 0 50 0 70 {}
+B 5 -2.5 -72.5 2.5 -67.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -72.5 -2.5 -67.5 2.5 {name=vctrl dir=in }
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+B 5 -72.5 37.5 -67.5 42.5 {name=D0 dir=in }
+A 4 -0.1779661016949153 0 50.00031671833042 89.79606673072159 360 {}
+A 4 -14 12.5 18.76832437912346 41.76029970389787 96.47940059220427 {}
+A 4 14 -12.5 18.76832437912346 221.7602997038979 96.47940059220427 {}
+T {@symname} 7.5 52 0 0 0.3 0.3 {}
+T {@name} -15.5 -42.5 0 0 0.2 0.2 {}
+T {vdd} -14.5 -71.5 3 1 0.2 0.2 {}
+T {out} 73.5 -13.5 0 1 0.2 0.2 {}
+T {vctrl} -73.5 -14 0 0 0.2 0.2 {}
+T {vss} -1.5 68.5 1 1 0.2 0.2 {}
+T {D0} -73.5 26 0 0 0.2 0.2 {}
diff --git a/xschem/delay_cell_buff.sch b/xschem/delay_cell_buff.sch
new file mode 100644
index 0000000..63b9ec6
--- /dev/null
+++ b/xschem/delay_cell_buff.sch
@@ -0,0 +1,126 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1050 -620 1130 -620 { lab=clk,clk1_int,clk1,clk2_int,clk2,clk3_int,clk3,clk4_int,clk4,clk5_int,clk5,clk6_int,clk6,clk7_int}
+N 1170 -710 1170 -660 { lab=avdd1p8}
+N 1170 -580 1170 -530 { lab=avss1p8}
+N 1240 -620 1350 -620 { lab=clk1_int,clk1,clk2_int,clk2,clk3_int,clk3,clk4_int,clk4,clk5_int,clk5,clk6_int,clk6,clk7_int,clk7}
+N 1040 -710 1070 -710 { lab=clk}
+N 1980 -590 1980 -530 { lab=avss1p8}
+N 1990 -590 1990 -530 { lab=avdd1p8}
+N 1870 -490 1950 -490 { lab=clk3}
+N 1870 -470 1950 -470 { lab=clk2}
+N 1980 -430 1980 -410 { lab=reg2}
+N 1980 -410 2030 -410 { lab=reg2}
+N 2020 -480 2100 -480 { lab=#net1}
+N 1980 -360 1980 -300 { lab=avss1p8}
+N 1990 -360 1990 -300 { lab=avdd1p8}
+N 1870 -260 1950 -260 { lab=clk1}
+N 1870 -240 1950 -240 { lab=clk}
+N 1980 -200 1980 -180 { lab=reg2}
+N 1980 -180 2030 -180 { lab=reg2}
+N 2020 -250 2100 -250 { lab=#net2}
+N 2260 -500 2260 -440 { lab=avss1p8}
+N 2270 -500 2270 -440 { lab=avdd1p8}
+N 2160 -400 2230 -400 { lab=#net1}
+N 2160 -380 2230 -380 { lab=#net2}
+N 2260 -340 2260 -320 { lab=reg1}
+N 2260 -320 2310 -320 { lab=reg1}
+N 2300 -390 2380 -390 { lab=#net3}
+N 2100 -480 2160 -480 { lab=#net1}
+N 2160 -480 2160 -400 { lab=#net1}
+N 2100 -250 2160 -250 { lab=#net2}
+N 2160 -380 2160 -250 { lab=#net2}
+N 2740 -600 2810 -600 { lab=out_mux}
+N 2760 -560 2810 -560 { lab=clk}
+N 2760 -560 2760 -480 { lab=clk}
+N 2850 -690 2850 -630 { lab=avdd1p8}
+N 2850 -530 2850 -470 { lab=avss1p8}
+N 2920 -580 3000 -580 { lab=clk_out}
+N 1980 -1030 1980 -970 { lab=avss1p8}
+N 1990 -1030 1990 -970 { lab=avdd1p8}
+N 1870 -930 1950 -930 { lab=clk7}
+N 1870 -910 1950 -910 { lab=clk6}
+N 1980 -870 1980 -850 { lab=reg2}
+N 1980 -850 2030 -850 { lab=reg2}
+N 2020 -920 2100 -920 { lab=#net4}
+N 1980 -800 1980 -740 { lab=avss1p8}
+N 1990 -800 1990 -740 { lab=avdd1p8}
+N 1870 -700 1950 -700 { lab=clk5}
+N 1870 -680 1950 -680 { lab=clk4}
+N 1980 -640 1980 -620 { lab=reg2}
+N 1980 -620 2030 -620 { lab=reg2}
+N 2020 -690 2100 -690 { lab=#net5}
+N 2260 -940 2260 -880 { lab=avss1p8}
+N 2270 -940 2270 -880 { lab=avdd1p8}
+N 2160 -840 2230 -840 { lab=#net4}
+N 2160 -820 2230 -820 { lab=#net5}
+N 2260 -780 2260 -760 { lab=reg1}
+N 2260 -760 2310 -760 { lab=reg1}
+N 2300 -830 2380 -830 { lab=#net6}
+N 2100 -920 2160 -920 { lab=#net4}
+N 2160 -920 2160 -840 { lab=#net4}
+N 2100 -690 2160 -690 { lab=#net5}
+N 2160 -820 2160 -690 { lab=#net5}
+N 2500 -710 2500 -650 { lab=avss1p8}
+N 2510 -710 2510 -650 { lab=avdd1p8}
+N 2500 -550 2500 -530 { lab=reg0}
+N 2500 -530 2550 -530 { lab=reg0}
+N 2540 -600 2620 -600 { lab=out_mux}
+N 2380 -590 2380 -390 { lab=#net3}
+N 2380 -590 2470 -590 { lab=#net3}
+N 2380 -610 2470 -610 { lab=#net6}
+N 2380 -760 2380 -610 { lab=#net6}
+N 2380 -830 2380 -760 { lab=#net6}
+C {ipin.sym} 1040 -710 0 0 {name=p4 lab=clk}
+C {iopin.sym} 1170 -710 0 0 {name=p15 lab=avdd1p8}
+C {iopin.sym} 1170 -530 0 0 {name=p16 lab=avss1p8}
+C {lab_wire.sym} 1080 -620 0 0 {name=l1 sig_type=std_logic lab=clk,clk1_int,clk1,clk2_int,clk2,clk3_int,clk3,clk4_int,clk4,clk5_int,clk5,clk6_int,clk6,clk7_int}
+C {lab_wire.sym} 1280 -620 2 0 {name=l2 sig_type=std_logic lab=clk1_int,clk1,clk2_int,clk2,clk3_int,clk3,clk4_int,clk4,clk5_int,clk5,clk6_int,clk6,clk7_int,clk7}
+C {mux_2to1_logic.sym} 1730 -290 0 0 {name=x1}
+C {lab_wire.sym} 1980 -580 0 0 {name=l3 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 1990 -590 2 0 {name=l4 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 1990 -410 2 0 {name=l5 sig_type=std_logic lab=reg2}
+C {mux_2to1_logic.sym} 1730 -60 0 0 {name=x2}
+C {lab_wire.sym} 1980 -350 0 0 {name=l6 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 1990 -360 2 0 {name=l7 sig_type=std_logic lab=avdd1p8}
+C {mux_2to1_logic.sym} 2010 -200 0 0 {name=x3}
+C {lab_wire.sym} 2260 -480 0 0 {name=l9 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 2270 -490 2 0 {name=l10 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 1880 -240 2 0 {name=l12 sig_type=std_logic lab=clk}
+C {lab_wire.sym} 1900 -260 0 0 {name=l13 sig_type=std_logic lab=clk1}
+C {lab_wire.sym} 1880 -470 2 0 {name=l14 sig_type=std_logic lab=clk2}
+C {lab_wire.sym} 1910 -490 0 0 {name=l15 sig_type=std_logic lab=clk3}
+C {nand_logic.sym} 2860 -480 0 0 {name=x4}
+C {lab_wire.sym} 2760 -510 2 0 {name=l16 sig_type=std_logic lab=clk}
+C {lab_wire.sym} 2850 -680 2 0 {name=l17 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 2850 -490 2 0 {name=l18 sig_type=std_logic lab=avss1p8}
+C {opin.sym} 3000 -580 0 0 {name=p1 lab=clk_out}
+C {ipin.sym} 2030 -180 2 0 {name=p2 lab=reg2}
+C {ipin.sym} 2310 -320 2 0 {name=p3 lab=reg1}
+C {buffer_no_inv_x05.sym} 1220 -450 0 0 {name=x5[13..0]}
+C {lab_wire.sym} 2770 -600 0 0 {name=l11 sig_type=std_logic lab=out_mux}
+C {mux_2to1_logic.sym} 1730 -730 0 0 {name=x5}
+C {lab_wire.sym} 1980 -1020 0 0 {name=l19 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 1990 -1030 2 0 {name=l20 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 1990 -850 2 0 {name=l21 sig_type=std_logic lab=reg2}
+C {mux_2to1_logic.sym} 1730 -500 0 0 {name=x6}
+C {lab_wire.sym} 1980 -790 0 0 {name=l22 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 1990 -800 2 0 {name=l23 sig_type=std_logic lab=avdd1p8}
+C {mux_2to1_logic.sym} 2010 -640 0 0 {name=x7}
+C {lab_wire.sym} 2260 -920 0 0 {name=l24 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 2270 -930 2 0 {name=l25 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 1880 -680 2 0 {name=l26 sig_type=std_logic lab=clk4}
+C {lab_wire.sym} 1900 -700 0 0 {name=l27 sig_type=std_logic lab=clk5}
+C {lab_wire.sym} 1880 -910 2 0 {name=l28 sig_type=std_logic lab=clk6}
+C {lab_wire.sym} 1910 -930 0 0 {name=l29 sig_type=std_logic lab=clk7}
+C {lab_wire.sym} 2010 -620 2 0 {name=l31 sig_type=std_logic lab=reg2}
+C {lab_wire.sym} 2280 -760 2 0 {name=l32 sig_type=std_logic lab=reg1}
+C {mux_2to1_logic.sym} 2250 -410 0 0 {name=x8}
+C {lab_wire.sym} 2500 -690 0 0 {name=l33 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 2510 -700 2 0 {name=l34 sig_type=std_logic lab=avdd1p8}
+C {ipin.sym} 2550 -530 2 0 {name=p5 lab=reg0}
+C {lab_wire.sym} 2580 -600 2 0 {name=l35 sig_type=std_logic lab=out_mux}
diff --git a/xschem/delay_cell_buff.sym b/xschem/delay_cell_buff.sym
new file mode 100644
index 0000000..659ef94
--- /dev/null
+++ b/xschem/delay_cell_buff.sym
@@ -0,0 +1,39 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -90 -170 -70 -170 {}
+L 4 -70 -210 -70 -130 {}
+L 4 -70 -130 10 -170 {}
+L 4 -70 -210 10 -170 {}
+L 4 -60 -130 20 -170 {}
+L 4 -60 -210 20 -170 {}
+L 4 -50 -130 30 -170 {}
+L 4 -50 -210 30 -170 {}
+L 4 30 -170 50 -170 {}
+L 4 -10 -150 -10 -130 {}
+L 4 0 -150 0 -130 {}
+L 4 10 -150 10 -130 {}
+L 7 -50 -220 -50 -200 {}
+L 7 -50 -140 -50 -120 {}
+B 5 -52.5 -222.5 -47.5 -217.5 {name=avdd1p8 dir=inout }
+B 5 -92.5 -172.5 -87.5 -167.5 {name=clk dir=in }
+B 5 -52.5 -122.5 -47.5 -117.5 {name=avss1p8 dir=inout }
+B 5 47.5 -172.5 52.5 -167.5 {name=clk_out dir=out}
+B 5 -12.5 -132.5 -7.5 -127.5 {name=reg0 dir=in }
+B 5 -2.5 -132.5 2.5 -127.5 {name=reg1 dir=in }
+B 5 7.5 -132.5 12.5 -127.5 {name=reg2 dir=in }
+T {@symname} 20 -240 0 0 0.3 0.3 {}
+T {@name} -60 -170 0 0 0.2 0.2 {}
+T {avdd1p8} 0 -230 0 1 0.2 0.2 {}
+T {clk} -110 -180 0 0 0.2 0.2 {}
+T {avss1p8} -50 -120 0 1 0.2 0.2 {}
+T {clk_out} 60 -180 0 0 0.2 0.2 {}
+T {reg0} -20 -100 3 0 0.2 0.2 {}
+T {reg1} -10 -100 3 0 0.2 0.2 {}
+T {reg2} 0 -100 3 0 0.2 0.2 {}
diff --git a/xschem/dff_pfd_pex_c.sym b/xschem/dff_pfd_pex_c.sym
new file mode 100644
index 0000000..f100e2b
--- /dev/null
+++ b/xschem/dff_pfd_pex_c.sym
@@ -0,0 +1,34 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -30 -30 -30 30 {}
+L 4 30 -30 30 30 {}
+L 4 -50 -30 -30 -30 {}
+L 4 -50 0 -30 0 {}
+L 4 30 -30 50 -30 {}
+L 4 0 40 0 60 {}
+L 4 -30 -40 -30 -30 {}
+L 4 -30 -40 30 -40 {}
+L 4 30 -40 30 -30 {}
+L 4 -30 30 -30 40 {}
+L 4 -30 40 30 40 {}
+L 4 30 30 30 40 {}
+L 7 0 -60 0 -40 {}
+B 5 -52.5 -32.5 -47.5 -27.5 {name=vdd dir=in }
+B 5 -52.5 -2.5 -47.5 2.5 {name=CLK dir=in }
+B 5 47.5 -32.5 52.5 -27.5 {name=Q dir=out }
+B 5 -2.5 57.5 2.5 62.5 {name=Reset dir=in }
+B 5 -2.5 -62.5 2.5 -57.5 {name=vss dir=inout }
+T {@symname} 8.5 44 0 0 0.3 0.3 {}
+T {@name} 15 -52 0 0 0.2 0.2 {}
+T {D} -25 -34 0 0 0.2 0.2 {}
+T {CLK} -25 -4 0 0 0.2 0.2 {}
+T {Q} 25 -34 0 1 0.2 0.2 {}
+T {Reset} -15 26 0 0 0.2 0.2 {}
+T {vss} -5 -54 0 1 0.2 0.2 {}
diff --git a/xschem/div_by_2.sch b/xschem/div_by_2.sch
new file mode 100644
index 0000000..db07f51
--- /dev/null
+++ b/xschem/div_by_2.sch
@@ -0,0 +1,71 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 130 20 160 20 { lab=CLK}
+N 560 -40 630 -40 { lab=out_div}
+N 1080 -120 1090 -120 { lab=CLK_2}
+N 160 20 200 20 { lab=CLK}
+N 380 0 420 0 { lab=CLK_d}
+N 380 40 420 40 { lab=nCLK_d}
+N 490 80 490 110 { lab=vss}
+N 490 -120 490 -80 { lab=vdd}
+N 560 40 600 40 { lab=nout_div}
+N 600 40 640 40 { lab=nout_div}
+N 320 40 380 40 { lab=nCLK_d}
+N 320 0 380 0 { lab=CLK_d}
+N 260 -80 260 -40 { lab=vdd}
+N 260 80 260 110 { lab=vss}
+N 380 -40 420 -40 { lab=nout_div}
+N 1030 -120 1080 -120 { lab=CLK_2}
+N 740 -210 740 -170 { lab=vdd}
+N 740 -70 740 -40 { lab=vss}
+N 740 40 740 80 { lab=vdd}
+N 740 180 740 210 { lab=vss}
+N 640 130 700 130 { lab=nout_div}
+N 640 40 640 130 { lab=nout_div}
+N 640 -120 700 -120 { lab=out_div}
+N 640 -120 640 -40 { lab=out_div}
+N 630 -40 640 -40 { lab=out_div}
+N 830 -120 900 -120 { lab=o1}
+N 1080 130 1090 130 { lab=nCLK_2}
+N 1030 130 1080 130 { lab=nCLK_2}
+N 830 130 900 130 { lab=o2}
+N 940 -210 940 -170 { lab=vdd}
+N 940 -70 940 -40 { lab=vss}
+N 940 40 940 80 { lab=vdd}
+N 940 180 940 210 { lab=vss}
+N 670 130 670 200 { lab=nout_div}
+N 870 130 870 200 { lab=o2}
+N 860 -190 860 -120 { lab=o1}
+N 670 -190 670 -120 { lab=out_div}
+C {ipin.sym} 130 20 0 0 {name=p4 lab=CLK}
+C {opin.sym} 1090 -120 0 0 {name=p7 lab=CLK_2}
+C {lab_wire.sym} 380 0 0 0 {name=l20 lab=CLK_d}
+C {lab_wire.sym} 380 40 0 0 {name=l21 lab=nCLK_d}
+C {iopin.sym} 490 110 1 0 {name=p2 lab=vss}
+C {iopin.sym} 490 -120 3 0 {name=p5 lab=vdd}
+C {opin.sym} 1090 130 0 0 {name=p1 lab=nCLK_2}
+C {lab_pin.sym} 260 -80 1 0 {name=l3 lab=vdd}
+C {lab_pin.sym} 260 110 3 0 {name=l6 lab=vss}
+C {lab_pin.sym} 380 -40 0 0 {name=l1 lab=nout_div}
+C {DFlipFlop.sym} 490 0 0 0 {name=x1}
+C {clock_inverter.sym} 260 20 0 0 {name=x2}
+C {inverter_min_x2.sym} 760 -120 0 0 {name=x3}
+C {inverter_min_x4.sym} 960 -120 0 0 {name=x4}
+C {lab_pin.sym} 740 -210 1 0 {name=l2 lab=vdd}
+C {lab_pin.sym} 740 -40 3 0 {name=l4 lab=vss}
+C {lab_pin.sym} 740 40 1 0 {name=l5 lab=vdd}
+C {lab_pin.sym} 740 210 3 0 {name=l7 lab=vss}
+C {lab_pin.sym} 940 -210 1 0 {name=l8 lab=vdd}
+C {lab_pin.sym} 940 -40 3 0 {name=l9 lab=vss}
+C {lab_pin.sym} 940 40 1 0 {name=l10 lab=vdd}
+C {lab_pin.sym} 940 210 3 0 {name=l11 lab=vss}
+C {iopin.sym} 670 200 1 0 {name=p3 lab=nout_div}
+C {iopin.sym} 870 200 1 0 {name=p6 lab=o2}
+C {iopin.sym} 860 -190 3 0 {name=p8 lab=o1}
+C {iopin.sym} 670 -190 3 0 {name=p9 lab=out_div}
+C {inverter_min_x2.sym} 760 130 0 0 {name=x5}
+C {inverter_min_x4.sym} 960 130 0 0 {name=x6}
diff --git a/xschem/div_by_2.sym b/xschem/div_by_2.sym
new file mode 100644
index 0000000..e00042c
--- /dev/null
+++ b/xschem/div_by_2.sym
@@ -0,0 +1,58 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 20 70 20 {}
+L 4 -70 0 -50 0 {}
+L 4 -50 -40 -50 0 {}
+L 4 -40 -60 40 -60 {}
+L 4 50 -40 50 20 {}
+L 4 50 20 50 40 {}
+L 4 -50 60 50 60 {}
+L 4 -50 -0 -50 40 {}
+L 4 -50 -10 -40 0 {}
+L 4 -50 10 -40 0 {}
+L 4 50 -20 70 -20 {}
+L 4 50 -40 50 -20 {}
+L 4 50 -20 50 40 {}
+L 4 40 -60 50 -60 {}
+L 4 50 -60 50 -40 {}
+L 4 50 40 50 60 {}
+L 4 -50 40 -50 60 {}
+L 4 -50 -60 -50 -40 {}
+L 4 -50 -60 -40 -60 {}
+L 4 -40 40 -40 60 {}
+L 4 -40 40 40 40 {}
+L 4 40 40 40 60 {}
+L 7 20 -80 20 -60 {}
+L 7 -20 -80 -20 -60 {}
+L 7 -30 60 -30 80 {}
+L 7 -10 60 -10 80 {}
+L 7 10 60 10 80 {}
+L 7 30 60 30 80 {}
+B 5 67.5 17.5 72.5 22.5 {name=nCLK_2 dir=out }
+B 5 17.5 -82.5 22.5 -77.5 {name=vss dir=inout }
+B 5 -72.5 -2.5 -67.5 2.5 {name=CLK dir=in }
+B 5 -22.5 -82.5 -17.5 -77.5 {name=vdd dir=inout }
+B 5 67.5 -22.5 72.5 -17.5 {name=CLK_2 dir=out }
+B 5 -32.5 77.5 -27.5 82.5 {name=out_div dir=inout }
+B 5 -12.5 77.5 -7.5 82.5 {name=nout_div dir=inout }
+B 5 7.5 77.5 12.5 82.5 {name=o1 dir=inout }
+B 5 27.5 77.5 32.5 82.5 {name=o2 dir=inout }
+T {@symname} 46 64 0 0 0.3 0.3 {}
+T {@name} -15 -42 0 0 0.2 0.2 {}
+T {nCLK_2} 45 6 0 1 0.2 0.2 {}
+T {vss} 25 -86 3 1 0.2 0.2 {}
+T {CLK} -35 -4 0 0 0.2 0.2 {}
+T {vdd} -24 -65 1 1 0.2 0.2 {}
+T {CLK_2} 45 -24 0 1 0.2 0.2 {}
+T {Debug} 15 46 0 1 0.2 0.2 {}
+T {out_div} -35 106 1 1 0.2 0.2 {}
+T {nout_div} -15 106 1 1 0.2 0.2 {}
+T {o1} 5 86 1 1 0.2 0.2 {}
+T {o2} 25 86 1 1 0.2 0.2 {}
diff --git a/xschem/div_by_2_pex_c.sym b/xschem/div_by_2_pex_c.sym
new file mode 100644
index 0000000..ebe7cd4
--- /dev/null
+++ b/xschem/div_by_2_pex_c.sym
@@ -0,0 +1,58 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 20 70 20 {}
+L 4 -70 0 -50 0 {}
+L 4 -50 -40 -50 0 {}
+L 4 -40 -60 40 -60 {}
+L 4 50 -40 50 20 {}
+L 4 50 20 50 40 {}
+L 4 -50 60 50 60 {}
+L 4 -50 -0 -50 40 {}
+L 4 -50 -10 -40 0 {}
+L 4 -50 10 -40 0 {}
+L 4 50 -20 70 -20 {}
+L 4 50 -40 50 -20 {}
+L 4 50 -20 50 40 {}
+L 4 40 -60 50 -60 {}
+L 4 50 -60 50 -40 {}
+L 4 50 40 50 60 {}
+L 4 -50 40 -50 60 {}
+L 4 -50 -60 -50 -40 {}
+L 4 -50 -60 -40 -60 {}
+L 4 -40 40 -40 60 {}
+L 4 -40 40 40 40 {}
+L 4 40 40 40 60 {}
+L 7 20 -80 20 -60 {}
+L 7 -20 -80 -20 -60 {}
+L 7 -30 60 -30 80 {}
+L 7 -10 60 -10 80 {}
+L 7 10 60 10 80 {}
+L 7 30 60 30 80 {}
+B 5 67.5 17.5 72.5 22.5 {name=nCLK_2 dir=out }
+B 5 17.5 -82.5 22.5 -77.5 {name=vss dir=inout }
+B 5 -72.5 -2.5 -67.5 2.5 {name=CLK dir=in }
+B 5 -22.5 -82.5 -17.5 -77.5 {name=vdd dir=inout }
+B 5 67.5 -22.5 72.5 -17.5 {name=CLK_2 dir=out }
+B 5 -32.5 77.5 -27.5 82.5 {name=out_div dir=inout }
+B 5 -12.5 77.5 -7.5 82.5 {name=nout_div dir=inout }
+B 5 7.5 77.5 12.5 82.5 {name=o1 dir=inout }
+B 5 27.5 77.5 32.5 82.5 {name=o2 dir=inout }
+T {@symname} 46 64 0 0 0.3 0.3 {}
+T {@name} -15 -42 0 0 0.2 0.2 {}
+T {nCLK_2} 45 6 0 1 0.2 0.2 {}
+T {vss} 25 -86 3 1 0.2 0.2 {}
+T {CLK} -35 -4 0 0 0.2 0.2 {}
+T {vdd} -24 -65 1 1 0.2 0.2 {}
+T {CLK_2} 45 -24 0 1 0.2 0.2 {}
+T {Debug} 15 46 0 1 0.2 0.2 {}
+T {out_div} -35 106 1 1 0.2 0.2 {}
+T {nout_div} -15 106 1 1 0.2 0.2 {}
+T {o1} 5 86 1 1 0.2 0.2 {}
+T {o2} 25 86 1 1 0.2 0.2 {}
diff --git a/xschem/div_by_5.sch b/xschem/div_by_5.sch
new file mode 100644
index 0000000..b4f028e
--- /dev/null
+++ b/xschem/div_by_5.sch
@@ -0,0 +1,97 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 0 -660 0 -620 { lab=vdd}
+N 0 -460 0 -430 { lab=vss}
+N -120 -540 -70 -540 { lab=CLK}
+N -120 -500 -70 -500 { lab=nCLK}
+N 390 -660 390 -620 { lab=vdd}
+N 390 -460 390 -430 { lab=vss}
+N 270 -540 320 -540 { lab=CLK}
+N 270 -500 320 -500 { lab=nCLK}
+N 800 -660 800 -620 { lab=vdd}
+N 800 -460 800 -430 { lab=vss}
+N 680 -540 730 -540 { lab=CLK}
+N 680 -500 730 -500 { lab=nCLK}
+N 870 -580 920 -580 { lab=Q0}
+N 70 -500 100 -500 { lab=nQ2}
+N 870 -500 920 -500 { lab=nQ0}
+N -100 -640 -100 -580 { lab=D2}
+N -100 -580 -70 -580 { lab=D2}
+N 70 -580 100 -580 { lab=Q2}
+N 460 -500 490 -500 { lab=nQ1}
+N 460 -580 490 -580 { lab=Q1}
+N 700 -580 730 -580 { lab=D0}
+N 290 -580 320 -580 { lab=D1}
+N -120 -810 -120 -760 { lab=Q0}
+N -80 -810 -80 -760 { lab=Q1}
+N 270 -630 270 -580 { lab=D1}
+N 270 -580 290 -580 { lab=D1}
+N 290 -800 290 -750 { lab=Q1}
+N 250 -800 250 -750 { lab=Q0}
+N 680 -640 680 -580 { lab=D0}
+N 680 -580 700 -580 { lab=D0}
+N 700 -810 700 -760 { lab=nQ2}
+N 660 -810 660 -760 { lab=nQ0}
+N 1190 -460 1190 -430 { lab=vss}
+N 1190 -660 1190 -620 { lab=vdd}
+N 1070 -500 1120 -500 { lab=CLK}
+N 1070 -540 1120 -540 { lab=nCLK}
+N 1090 -580 1120 -580 { lab=Q1}
+N 1260 -580 1370 -580 { lab=Q1_shift}
+N 1340 -620 1370 -620 { lab=Q1}
+N 1490 -600 1550 -600 { lab=CLK_5}
+N 1260 -500 1320 -500 { lab=nQ1_shift}
+N 1330 -550 1370 -550 { lab=Q1_shift}
+N 1330 -580 1330 -550 { lab=Q1_shift}
+C {iopin.sym} 0 -660 3 0 {name=p5 lab=vdd}
+C {iopin.sym} 0 -430 1 0 {name=p6 lab=vss}
+C {ipin.sym} -120 -540 0 0 {name=p8 lab=CLK}
+C {lab_pin.sym} 270 -540 0 0 {name=l9 lab=CLK}
+C {lab_pin.sym} 270 -500 0 0 {name=l10 lab=nCLK}
+C {lab_pin.sym} 680 -540 0 0 {name=l11 lab=CLK}
+C {lab_pin.sym} 680 -500 0 0 {name=l12 lab=nCLK}
+C {opin.sym} 1550 -600 0 0 {name=p15 lab=CLK_5}
+C {lab_pin.sym} 390 -660 1 0 {name=l29 lab=vdd}
+C {lab_pin.sym} 800 -660 1 0 {name=l30 lab=vdd}
+C {lab_pin.sym} 390 -430 3 0 {name=l31 lab=vss}
+C {lab_pin.sym} 800 -430 3 0 {name=l32 lab=vss}
+C {lab_pin.sym} -120 -810 1 0 {name=l13 lab=Q0}
+C {lab_wire.sym} 100 -580 0 0 {name=l15 lab=Q2}
+C {lab_pin.sym} -100 -580 0 0 {name=l16 lab=D2}
+C {lab_wire.sym} 490 -500 0 0 {name=l14 lab=nQ1}
+C {sky130_stdcells/and2_1.sym} -100 -700 1 0 {name=x8 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {lab_pin.sym} -80 -810 1 0 {name=l17 lab=Q1}
+C {sky130_stdcells/xor2_1.sym} 270 -690 1 0 {name=x9 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {lab_pin.sym} 270 -580 0 0 {name=l19 lab=D1}
+C {lab_pin.sym} 290 -800 1 0 {name=l22 lab=Q1}
+C {lab_pin.sym} 250 -800 1 0 {name=l27 lab=Q0}
+C {sky130_stdcells/and2_1.sym} 680 -700 1 0 {name=x10 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {lab_pin.sym} 680 -580 0 0 {name=l33 lab=D0}
+C {lab_pin.sym} 700 -810 1 0 {name=l34 lab=nQ2}
+C {lab_pin.sym} 660 -810 1 0 {name=l35 lab=nQ0}
+C {lab_pin.sym} 1190 -430 3 0 {name=l36 lab=vss}
+C {lab_pin.sym} 1190 -660 1 0 {name=l37 lab=vdd}
+C {lab_pin.sym} 1070 -500 2 1 {name=l38 lab=CLK}
+C {lab_pin.sym} 1070 -540 2 1 {name=l39 lab=nCLK}
+C {lab_pin.sym} 1090 -580 0 0 {name=l40 lab=Q1}
+C {sky130_stdcells/or2_1.sym} 1430 -600 0 0 {name=x12 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {lab_pin.sym} 1340 -620 0 0 {name=l41 lab=Q1}
+C {lab_wire.sym} 1330 -580 0 0 {name=l44 lab=Q1_shift}
+C {ipin.sym} -120 -500 0 0 {name=p1 lab=nCLK}
+C {lab_wire.sym} 1320 -500 0 0 {name=l1 lab=nQ1_shift}
+C {DFlipFlop.sym} 0 -540 0 0 {name=x1}
+C {DFlipFlop.sym} 390 -540 0 0 {name=x2}
+C {DFlipFlop.sym} 800 -540 0 0 {name=x3}
+C {DFlipFlop.sym} 1190 -540 0 0 {name=x4}
+C {noconn.sym} 490 -500 2 0 {name=l2}
+C {noconn.sym} 1320 -500 2 0 {name=l3}
+C {noconn.sym} 100 -580 2 0 {name=l4}
+C {iopin.sym} 100 -500 0 0 {name=p2 lab=nQ2}
+C {iopin.sym} 490 -580 0 0 {name=p3 lab=Q1}
+C {iopin.sym} 920 -580 0 0 {name=p4 lab=Q0}
+C {iopin.sym} 920 -500 0 0 {name=p7 lab=nQ0}
+C {iopin.sym} 1370 -550 0 0 {name=p9 lab=Q1_shift}
diff --git a/xschem/div_by_5.sym b/xschem/div_by_5.sym
new file mode 100644
index 0000000..c0eb1b7
--- /dev/null
+++ b/xschem/div_by_5.sym
@@ -0,0 +1,64 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 60 0 80 0 {}
+L 4 -80 -20 -60 -20 {}
+L 4 -60 -40 -60 -20 {}
+L 4 -50 -60 50 -60 {}
+L 4 60 -40 60 40 {}
+L 4 -50 60 50 60 {}
+L 4 -60 -20 -60 40 {}
+L 4 -60 -30 -50 -20 {}
+L 4 -60 -10 -50 -20 {}
+L 4 -80 20 -60 20 {}
+L 4 -60 -40 -60 20 {}
+L 4 -60 20 -60 40 {}
+L 4 -60 10 -50 20 {}
+L 4 -60 30 -50 20 {}
+L 4 60 40 60 60 {}
+L 4 -60 40 -60 60 {}
+L 4 -60 -60 -60 -40 {}
+L 4 60 -60 60 -40 {}
+L 4 50 60 60 60 {}
+L 4 -60 60 -50 60 {}
+L 4 -60 -60 -50 -60 {}
+L 4 50 -60 60 -60 {}
+L 4 50 40 50 60 {}
+L 4 -50 40 50 40 {}
+L 4 -50 40 -50 60 {}
+L 7 -20 -80 -20 -60 {}
+L 7 20 -80 20 -60 {}
+L 7 -40 60 -40 80 {}
+L 7 -20 60 -20 80 {}
+L 7 20 60 20 80 {}
+L 7 40 60 40 80 {}
+L 7 0 60 0 80 {}
+B 5 -22.5 -82.5 -17.5 -77.5 {name=vdd dir=inout }
+B 5 77.5 -2.5 82.5 2.5 {name=CLK_5 dir=out }
+B 5 -82.5 -22.5 -77.5 -17.5 {name=CLK dir=in }
+B 5 17.5 -82.5 22.5 -77.5 {name=vss dir=inout }
+B 5 -82.5 17.5 -77.5 22.5 {name=nCLK dir=in }
+B 5 -42.5 77.5 -37.5 82.5 {name=nQ2 dir=inout }
+B 5 -22.5 77.5 -17.5 82.5 {name=Q1 dir=inout }
+B 5 17.5 77.5 22.5 82.5 {name=nQ0 dir=inout }
+B 5 37.5 77.5 42.5 82.5 {name=Q0 dir=inout }
+B 5 -2.5 77.5 2.5 82.5 {name=Q1_shift dir=inout }
+T {@symname} 66 64 0 0 0.3 0.3 {}
+T {@name} -5 -32 0 0 0.2 0.2 {}
+T {vdd} -34 -85 3 1 0.2 0.2 {}
+T {CLK_5} 45 -4 0 1 0.2 0.2 {}
+T {CLK} -45 -24 0 0 0.2 0.2 {}
+T {vss} 14 -65 1 1 0.2 0.2 {}
+T {nCLK} -45 16 0 0 0.2 0.2 {}
+T {nQ2} -26 85 1 1 0.2 0.2 {}
+T {Q1} -6 85 1 1 0.2 0.2 {}
+T {nQ0} 34 85 1 1 0.2 0.2 {}
+T {Q0} 54 85 1 1 0.2 0.2 {}
+T {Q1_shift} 14 105 1 1 0.2 0.2 {}
+T {Debug} -15 46 0 0 0.2 0.2 {}
diff --git a/xschem/div_by_5_pex_c.sym b/xschem/div_by_5_pex_c.sym
new file mode 100644
index 0000000..b637808
--- /dev/null
+++ b/xschem/div_by_5_pex_c.sym
@@ -0,0 +1,64 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 60 0 80 0 {}
+L 4 -80 -20 -60 -20 {}
+L 4 -60 -40 -60 -20 {}
+L 4 -50 -60 50 -60 {}
+L 4 60 -40 60 40 {}
+L 4 -50 60 50 60 {}
+L 4 -60 -20 -60 40 {}
+L 4 -60 -30 -50 -20 {}
+L 4 -60 -10 -50 -20 {}
+L 4 -80 20 -60 20 {}
+L 4 -60 -40 -60 20 {}
+L 4 -60 20 -60 40 {}
+L 4 -60 10 -50 20 {}
+L 4 -60 30 -50 20 {}
+L 4 60 40 60 60 {}
+L 4 -60 40 -60 60 {}
+L 4 -60 -60 -60 -40 {}
+L 4 60 -60 60 -40 {}
+L 4 50 60 60 60 {}
+L 4 -60 60 -50 60 {}
+L 4 -60 -60 -50 -60 {}
+L 4 50 -60 60 -60 {}
+L 4 50 40 50 60 {}
+L 4 -50 40 50 40 {}
+L 4 -50 40 -50 60 {}
+L 7 -20 -80 -20 -60 {}
+L 7 20 -80 20 -60 {}
+L 7 -40 60 -40 80 {}
+L 7 -20 60 -20 80 {}
+L 7 20 60 20 80 {}
+L 7 40 60 40 80 {}
+L 7 0 60 0 80 {}
+B 5 -22.5 -82.5 -17.5 -77.5 {name=vdd dir=inout }
+B 5 77.5 -2.5 82.5 2.5 {name=CLK_5 dir=out }
+B 5 -82.5 -22.5 -77.5 -17.5 {name=CLK dir=in }
+B 5 17.5 -82.5 22.5 -77.5 {name=vss dir=inout }
+B 5 -82.5 17.5 -77.5 22.5 {name=nCLK dir=in }
+B 5 -42.5 77.5 -37.5 82.5 {name=nQ2 dir=inout }
+B 5 -22.5 77.5 -17.5 82.5 {name=Q1 dir=inout }
+B 5 17.5 77.5 22.5 82.5 {name=nQ0 dir=inout }
+B 5 37.5 77.5 42.5 82.5 {name=Q0 dir=inout }
+B 5 -2.5 77.5 2.5 82.5 {name=Q1_shift dir=inout }
+T {@symname} 66 64 0 0 0.3 0.3 {}
+T {@name} -5 -32 0 0 0.2 0.2 {}
+T {vdd} -34 -85 3 1 0.2 0.2 {}
+T {CLK_5} 45 -4 0 1 0.2 0.2 {}
+T {CLK} -45 -24 0 0 0.2 0.2 {}
+T {vss} 14 -65 1 1 0.2 0.2 {}
+T {nCLK} -45 16 0 0 0.2 0.2 {}
+T {nQ2} -26 85 1 1 0.2 0.2 {}
+T {Q1} -6 85 1 1 0.2 0.2 {}
+T {nQ0} 34 85 1 1 0.2 0.2 {}
+T {Q0} 54 85 1 1 0.2 0.2 {}
+T {Q1_shift} 14 105 1 1 0.2 0.2 {}
+T {Debug} -15 46 0 0 0.2 0.2 {}
diff --git a/xschem/example_por.sch b/xschem/example_por.sch
index cf6e0c3..b09dbeb 100644
--- a/xschem/example_por.sch
+++ b/xschem/example_por.sch
@@ -289,9 +289,9 @@
C {sky130_stdcells/buf_8.sym} 3170 -40 0 0 {name=x3 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ }
C {sky130_stdcells/inv_8.sym} 3170 60 0 0 {name=x4 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ }
C {sky130_stdcells/buf_1.sym} 3020 -130 0 0 {name=x5 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__schmitt }
-C {devices/iopin.sym} 2840 -400 0 0 {name=p1 lab=vdd3v3}
-C {devices/iopin.sym} 2870 110 0 0 {name=p2 lab=vss}
-C {devices/opin.sym} 3300 -130 0 0 {name=p3 lab=porb_h}
-C {devices/opin.sym} 3300 -40 0 0 {name=p4 lab=porb_l}
-C {devices/opin.sym} 3300 60 0 0 {name=p5 lab=por_l}
-C {devices/iopin.sym} 2840 -330 0 0 {name=p6 lab=vdd1v8}
+C {iopin.sym} 2840 -400 0 0 {name=p1 lab=vdd3v3}
+C {iopin.sym} 2870 110 0 0 {name=p2 lab=vss}
+C {opin.sym} 3300 -130 0 0 {name=p3 lab=porb_h}
+C {opin.sym} 3300 -40 0 0 {name=p4 lab=porb_l}
+C {opin.sym} 3300 60 0 0 {name=p5 lab=por_l}
+C {iopin.sym} 2840 -330 0 0 {name=p6 lab=vdd1v8}
diff --git a/xschem/example_por_tb.sch b/xschem/example_por_tb.sch
index 664018f..0e88178 100644
--- a/xschem/example_por_tb.sch
+++ b/xschem/example_por_tb.sch
@@ -28,18 +28,18 @@
N -330 60 -280 60 {}
N -330 -110 -210 -110 {}
C {example_por.sym} -10 -20 0 0 {name=x1}
-C {devices/gnd.sym} -100 60 0 0 {name=l1 lab=GND}
-C {devices/vsource.sym} -330 -30 0 0 {name=V1 value="PWL(0.0 0 100u 0 5m 3.3)"}
-C {devices/vsource.sym} -540 -30 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3m 1.8)"}
-C {devices/opin.sym} -340 -110 0 1 {name=p1 lab=vdd3v3}
-C {devices/opin.sym} -560 -130 0 1 {name=p2 lab=vdd1v8}
-C {devices/opin.sym} 180 -50 0 0 {name=p3 lab=porb_h}
-C {devices/opin.sym} 180 -20 0 0 {name=p4 lab=porb_l}
-C {devices/opin.sym} 180 10 0 0 {name=p5 lab=por_l}
-C {devices/code_shown.sym} -470 140 0 0 {name=s1 only_toplevel=false value=".param mc_mm_switch=0
+C {gnd.sym} -100 60 0 0 {name=l1 lab=GND}
+C {vsource.sym} -330 -30 0 0 {name=V1 value="PWL(0.0 0 100u 0 5m 3.3)"}
+C {vsource.sym} -540 -30 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3m 1.8)"}
+C {opin.sym} -340 -110 0 1 {name=p1 lab=vdd3v3}
+C {opin.sym} -560 -130 0 1 {name=p2 lab=vdd1v8}
+C {opin.sym} 180 -50 0 0 {name=p3 lab=porb_h}
+C {opin.sym} 180 -20 0 0 {name=p4 lab=porb_l}
+C {opin.sym} 180 10 0 0 {name=p5 lab=por_l}
+C {code_shown.sym} -470 140 0 0 {name=s1 only_toplevel=false value=".param mc_mm_switch=0
.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"}
-C {devices/code_shown.sym} -470 250 0 0 {name=s2 only_toplevel=false value=".control
+C {code_shown.sym} -470 250 0 0 {name=s2 only_toplevel=false value=".control
tran 1u 20m
plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
.endc"}
diff --git a/xschem/inverter_cp_x1.sch b/xschem/inverter_cp_x1.sch
new file mode 100644
index 0000000..c9fe522
--- /dev/null
+++ b/xschem/inverter_cp_x1.sch
@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vdd}
+N 250 90 350 90 { lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.15
+W=1.25
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.15
+W=1.25
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}
diff --git a/xschem/inverter_cp_x1.sym b/xschem/inverter_cp_x1.sym
new file mode 100644
index 0000000..cdda9c9
--- /dev/null
+++ b/xschem/inverter_cp_x1.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/inverter_cp_x2.sch b/xschem/inverter_cp_x2.sch
new file mode 100644
index 0000000..734bbdd
--- /dev/null
+++ b/xschem/inverter_cp_x2.sch
@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vdd}
+N 250 90 350 90 { lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.15
+W=1.25
+nf=1
+mult=6
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.15
+W=1.25
+nf=1
+mult=6
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}
diff --git a/xschem/inverter_cp_x2.sym b/xschem/inverter_cp_x2.sym
new file mode 100644
index 0000000..cdda9c9
--- /dev/null
+++ b/xschem/inverter_cp_x2.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/inverter_csvco.sch b/xschem/inverter_csvco.sch
new file mode 100644
index 0000000..5d55284
--- /dev/null
+++ b/xschem/inverter_csvco.sch
@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vbulkp}
+N 250 90 350 90 { lab=vbulkn}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.2
+W=0.75
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.2
+W=1.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 350 90 0 0 {name=p5 lab=vbulkn}
+C {iopin.sym} 350 -90 0 0 {name=p6 lab=vbulkp}
diff --git a/xschem/inverter_csvco.sym b/xschem/inverter_csvco.sym
new file mode 100644
index 0000000..611d998
--- /dev/null
+++ b/xschem/inverter_csvco.sym
@@ -0,0 +1,33 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+L 7 20 -30 20 -10 {}
+L 7 20 10 20 30 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+B 5 17.5 -32.5 22.5 -27.5 {name=vbulkp dir=inout }
+B 5 17.5 27.5 22.5 32.5 {name=vbulkn dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} 34 10 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
+T {vbulkp} 6 -55 3 1 0.2 0.2 {}
+T {vbulkn} 14 55 1 1 0.2 0.2 {}
diff --git a/xschem/inverter_csvco_pex_c.sym b/xschem/inverter_csvco_pex_c.sym
new file mode 100644
index 0000000..0fbd461
--- /dev/null
+++ b/xschem/inverter_csvco_pex_c.sym
@@ -0,0 +1,33 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primative
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+L 7 20 -30 20 -10 {}
+L 7 20 10 20 30 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+B 5 17.5 -32.5 22.5 -27.5 {name=vbulkp dir=inout }
+B 5 17.5 27.5 22.5 32.5 {name=vbulkn dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} 34 10 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
+T {vbulkp} 6 -55 3 1 0.2 0.2 {}
+T {vbulkn} 14 55 1 1 0.2 0.2 {}
diff --git a/xschem/inverter_min.sch b/xschem/inverter_min.sch
new file mode 100644
index 0000000..40a3506
--- /dev/null
+++ b/xschem/inverter_min.sch
@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vdd}
+N 250 90 350 90 { lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.15
+W=0.84
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.15
+W=0.42
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}
diff --git a/xschem/inverter_min.sym b/xschem/inverter_min.sym
new file mode 100644
index 0000000..cdda9c9
--- /dev/null
+++ b/xschem/inverter_min.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/inverter_min_x16.sch b/xschem/inverter_min_x16.sch
new file mode 100644
index 0000000..0ab95a7
--- /dev/null
+++ b/xschem/inverter_min_x16.sch
@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vdd}
+N 250 90 350 90 { lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.15
+W=0.84
+nf=1
+mult=16
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.15
+W=0.42
+nf=1
+mult=16
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}
diff --git a/xschem/inverter_min_x16.sym b/xschem/inverter_min_x16.sym
new file mode 100644
index 0000000..cdda9c9
--- /dev/null
+++ b/xschem/inverter_min_x16.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/inverter_min_x2.sch b/xschem/inverter_min_x2.sch
new file mode 100644
index 0000000..e986f76
--- /dev/null
+++ b/xschem/inverter_min_x2.sch
@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vdd}
+N 250 90 350 90 { lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.15
+W=0.84
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.15
+W=0.42
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}
diff --git a/xschem/inverter_min_x2.sym b/xschem/inverter_min_x2.sym
new file mode 100644
index 0000000..cdda9c9
--- /dev/null
+++ b/xschem/inverter_min_x2.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/inverter_min_x2_pex_c.sym b/xschem/inverter_min_x2_pex_c.sym
new file mode 100644
index 0000000..0c2e821
--- /dev/null
+++ b/xschem/inverter_min_x2_pex_c.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/inverter_min_x4.sch b/xschem/inverter_min_x4.sch
new file mode 100644
index 0000000..6f8dda8
--- /dev/null
+++ b/xschem/inverter_min_x4.sch
@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vdd}
+N 250 90 350 90 { lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.15
+W=0.84
+nf=1
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.15
+W=0.42
+nf=1
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}
diff --git a/xschem/inverter_min_x4.sym b/xschem/inverter_min_x4.sym
new file mode 100644
index 0000000..cdda9c9
--- /dev/null
+++ b/xschem/inverter_min_x4.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/inverter_min_x4_pex_c.sym b/xschem/inverter_min_x4_pex_c.sym
new file mode 100644
index 0000000..0c2e821
--- /dev/null
+++ b/xschem/inverter_min_x4_pex_c.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/iref_ctrl_res_amp.sch b/xschem/iref_ctrl_res_amp.sch
new file mode 100644
index 0000000..dd5cd50
--- /dev/null
+++ b/xschem/iref_ctrl_res_amp.sch
@@ -0,0 +1,283 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 960 -1040 960 -980 { lab=iref}
+N 960 -920 960 -870 { lab=#net1}
+N 950 -950 960 -950 { lab=avss1p8}
+N 950 -950 950 -870 { lab=avss1p8}
+N 950 -770 960 -770 { lab=avss1p8}
+N 1110 -920 1110 -870 { lab=#net2}
+N 1110 -950 1120 -950 { lab=avss1p8}
+N 1120 -950 1120 -870 { lab=avss1p8}
+N 1110 -770 1120 -770 { lab=avss1p8}
+N 960 -1000 1000 -1000 { lab=iref}
+N 1000 -950 1070 -950 { lab=iref}
+N 960 -770 1110 -770 { lab=avss1p8}
+N 1110 -1080 1110 -980 { lab=vctrl}
+N 1100 -1110 1110 -1110 { lab=avdd1p8}
+N 1100 -1260 1110 -1260 { lab=avdd1p8}
+N 1150 -1110 1220 -1110 { lab=vctrl}
+N 1180 -1110 1180 -1050 { lab=vctrl}
+N 1110 -1050 1180 -1050 { lab=vctrl}
+N 1110 -1160 1110 -1140 { lab=#net3}
+N 1110 -1260 1110 -1220 { lab=avdd1p8}
+N 1100 -1260 1100 -1110 { lab=avdd1p8}
+N 1100 -1190 1110 -1190 { lab=avdd1p8}
+N 1150 -1190 1200 -1190 { lab=avss1p8}
+N 1020 -1000 1020 -950 { lab=iref}
+N 1000 -1000 1020 -1000 { lab=iref}
+N 1220 -920 1220 -870 { lab=#net4}
+N 1220 -950 1230 -950 { lab=avss1p8}
+N 1230 -950 1230 -870 { lab=avss1p8}
+N 1340 -920 1340 -870 { lab=#net5}
+N 1340 -950 1350 -950 { lab=avss1p8}
+N 1350 -950 1350 -870 { lab=avss1p8}
+N 1340 -870 1340 -860 { lab=#net5}
+N 1220 -870 1220 -860 { lab=#net4}
+N 1120 -770 1220 -770 { lab=avss1p8}
+N 1220 -800 1220 -770 { lab=avss1p8}
+N 1230 -870 1230 -830 { lab=avss1p8}
+N 1220 -830 1230 -830 { lab=avss1p8}
+N 1230 -830 1230 -770 { lab=avss1p8}
+N 1350 -870 1350 -830 { lab=avss1p8}
+N 1340 -830 1350 -830 { lab=avss1p8}
+N 1220 -770 1350 -770 { lab=avss1p8}
+N 1350 -830 1350 -770 { lab=avss1p8}
+N 1340 -800 1340 -770 { lab=avss1p8}
+N 1140 -950 1180 -950 { lab=iref}
+N 1260 -950 1300 -950 { lab=iref}
+N 1160 -830 1180 -830 { lab=reg0}
+N 1280 -830 1300 -830 { lab=reg1}
+N 1220 -1000 1220 -980 { lab=vctrl}
+N 1110 -1000 1220 -1000 { lab=vctrl}
+N 1220 -1000 1340 -1000 { lab=vctrl}
+N 1340 -1000 1340 -980 { lab=vctrl}
+N 1120 -870 1120 -830 { lab=avss1p8}
+N 1110 -830 1120 -830 { lab=avss1p8}
+N 1110 -800 1110 -770 { lab=avss1p8}
+N 1120 -830 1120 -770 { lab=avss1p8}
+N 1110 -870 1110 -860 { lab=#net2}
+N 960 -870 960 -860 { lab=#net1}
+N 950 -870 950 -830 { lab=avss1p8}
+N 950 -830 960 -830 { lab=avss1p8}
+N 960 -800 960 -770 { lab=avss1p8}
+N 950 -830 950 -770 { lab=avss1p8}
+N 1000 -830 1070 -830 { lab=avdd1p8}
+N 1460 -920 1460 -870 { lab=#net6}
+N 1460 -950 1470 -950 { lab=avss1p8}
+N 1470 -950 1470 -870 { lab=avss1p8}
+N 1460 -870 1460 -860 { lab=#net6}
+N 1470 -870 1470 -830 { lab=avss1p8}
+N 1460 -830 1470 -830 { lab=avss1p8}
+N 1340 -770 1470 -770 { lab=avss1p8}
+N 1470 -830 1470 -770 { lab=avss1p8}
+N 1460 -800 1460 -770 { lab=avss1p8}
+N 1380 -950 1420 -950 { lab=iref}
+N 1400 -830 1420 -830 { lab=reg2}
+N 1340 -1000 1460 -1000 { lab=vctrl}
+N 1460 -1000 1460 -980 { lab=vctrl}
+N 1220 -1110 1260 -1110 { lab=vctrl}
+N 960 -1090 960 -1040 { lab=iref}
+N 1180 -770 1180 -690 { lab=avss1p8}
+N 1110 -1290 1110 -1260 { lab=avdd1p8}
+C {iopin.sym} 1110 -1290 0 0 {name=p15 lab=avdd1p8}
+C {iopin.sym} 1180 -690 0 0 {name=p16 lab=avss1p8}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 980 -950 0 1 {name=M7
+L=0.15
+W=1
+nf=1
+mult=6
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 1090 -950 0 0 {name=M8
+L=0.15
+W=1
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1130 -1110 0 1 {name=M9
+L=0.15
+W=1
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {ngspice_probe.sym} 1110 -900 2 0 {name=r6}
+C {sky130_fd_pr/pfet_01v8.sym} 1130 -1190 0 1 {name=M10
+L=0.15
+W=1
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 1180 -1190 2 0 {name=l69 sig_type=std_logic lab=avss1p8}
+C {ngspice_probe.sym} 1110 -1150 0 0 {name=r25}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 1200 -950 0 0 {name=M1
+L=0.15
+W=1
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 1320 -950 0 0 {name=M2
+L=0.15
+W=1
+nf=1
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 1200 -830 0 0 {name=M3
+L=0.15
+W=1
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 1320 -830 0 0 {name=M4
+L=0.15
+W=1
+nf=1
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_wire.sym} 1140 -950 2 0 {name=l30 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 1260 -950 2 0 {name=l36 sig_type=std_logic lab=iref}
+C {ipin.sym} 1160 -830 3 0 {name=p6 lab=reg0}
+C {ipin.sym} 1280 -830 3 0 {name=p7 lab=reg1}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 1090 -830 0 0 {name=M5
+L=0.15
+W=1
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 980 -830 0 1 {name=M6
+L=0.15
+W=1
+nf=1
+mult=6
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_wire.sym} 1010 -830 2 0 {name=l37 sig_type=std_logic lab=avdd1p8
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 1440 -950 0 0 {name=M11
+L=0.15
+W=1
+nf=1
+mult=8
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 1440 -830 0 0 {name=M12
+L=0.15
+W=1
+nf=1
+mult=8
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_wire.sym} 1380 -950 2 0 {name=l38 sig_type=std_logic lab=iref}
+C {ipin.sym} 1400 -830 3 0 {name=p8 lab=reg2}
+C {opin.sym} 1260 -1110 0 0 {name=p9 lab=vctrl}
+C {ipin.sym} 960 -1090 1 0 {name=p10 lab=iref}
+C {ngspice_get_value.sym} 1350 -1190 0 0 {name=r19 node="v(@M.XM9.msky130_fd_pr__pfet_01v8[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 1350 -1160 0 0 {name=r20 node="v(@M.XM9.msky130_fd_pr__pfet_01v8[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 1280 -1190 0 0 {name=r21 node="i(@M.XM9.msky130_fd_pr__pfet_01v8[id])"
+descr="id="}
+C {ngspice_get_value.sym} 1280 -1130 0 0 {name=r22 node="v(@M.XM9.msky130_fd_pr__pfet_01v8[vth])"
+descr="vth="}
+C {ngspice_get_value.sym} 1280 -1160 0 0 {name=r23 node="@M.XM9.msky130_fd_pr__pfet_01v8[gm]"
+descr="gm="}
+C {ngspice_get_value.sym} 1350 -1130 0 0 {name=r24 node="@M.XM9.msky130_fd_pr__pfet_01v8[gds]"
+descr="gds="}
+C {ngspice_probe.sym} 1220 -900 2 0 {name=r1}
+C {ngspice_probe.sym} 1340 -900 2 0 {name=r2}
+C {ngspice_probe.sym} 1460 -900 2 0 {name=r3}
diff --git a/xschem/iref_ctrl_res_amp.sym b/xschem/iref_ctrl_res_amp.sym
new file mode 100644
index 0000000..e1042bb
--- /dev/null
+++ b/xschem/iref_ctrl_res_amp.sym
@@ -0,0 +1,56 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -90 -200 -70 -200 {}
+L 4 -70 -210 -70 -130 {}
+L 4 30 -170 50 -170 {}
+L 4 -20 -130 -20 -110 {}
+L 4 -10 -130 -10 -110 {}
+L 4 0 -130 0 -110 {}
+L 4 -70 -130 30 -130 {}
+L 4 30 -210 30 -130 {}
+L 4 -70 -210 30 -210 {}
+L 4 -70 -200 -50 -200 {}
+L 4 -50 -200 -50 -150 {}
+L 4 -60 -170 -50 -160 {}
+L 4 -60 -170 -40 -170 {}
+L 4 -50 -160 -40 -170 {}
+L 4 -50 -150 -50 -130 {}
+L 4 10 -170 30 -170 {}
+L 4 -50 -180 -40 -180 {}
+L 4 -40 -180 -40 -160 {}
+L 4 -60 -160 -40 -160 {}
+L 4 -60 -180 -60 -160 {}
+L 4 -60 -180 -50 -180 {}
+L 4 -20 -150 -20 -140 {}
+L 4 -10 -150 -10 -140 {}
+L 4 -0 -150 -0 -140 {}
+L 4 -20 -210 -20 -200 {}
+L 4 -20 -200 0 -200 {}
+L 4 0 -200 0 -180 {}
+L 4 -40 -170 -20 -170 {}
+L 7 -20 -230 -20 -210 {}
+L 7 -50 -130 -50 -110 {}
+B 5 -22.5 -232.5 -17.5 -227.5 {name=avdd1p8 dir=inout }
+B 5 -92.5 -202.5 -87.5 -197.5 {name=iref dir=in }
+B 5 -52.5 -112.5 -47.5 -107.5 {name=avss1p8 dir=inout }
+B 5 47.5 -172.5 52.5 -167.5 {name=vctrl dir=out}
+B 5 -22.5 -112.5 -17.5 -107.5 {name=reg0 dir=in }
+B 5 -12.5 -112.5 -7.5 -107.5 {name=reg1 dir=in }
+B 5 -2.5 -112.5 2.5 -107.5 {name=reg2 dir=in }
+A 4 -5 -165 15.8113883008419 198.434948822922 360 {}
+T {@symname} 30 -230 0 0 0.3 0.3 {}
+T {@name} -20 -200 0 0 0.2 0.2 {}
+T {avdd1p8} 30 -240 0 1 0.2 0.2 {}
+T {iref} -110 -210 0 0 0.2 0.2 {}
+T {avss1p8} -50 -110 0 1 0.2 0.2 {}
+T {vctrl} 60 -180 0 0 0.2 0.2 {}
+T {reg0} -30 -80 3 0 0.2 0.2 {}
+T {reg1} -20 -80 3 0 0.2 0.2 {}
+T {reg2} -10 -80 3 0 0.2 0.2 {}
diff --git a/xschem/latch_diff.sch b/xschem/latch_diff.sch
new file mode 100644
index 0000000..3458830
--- /dev/null
+++ b/xschem/latch_diff.sch
@@ -0,0 +1,120 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 60 80 60 100 { lab=#net1}
+N 60 100 180 100 { lab=#net1}
+N 180 100 180 120 { lab=#net1}
+N 180 100 300 100 { lab=#net1}
+N 300 80 300 100 { lab=#net1}
+N 60 -40 60 20 { lab=nQ}
+N 60 -140 60 -100 { lab=vdd}
+N 60 -140 300 -140 { lab=vdd}
+N 300 -140 300 -100 { lab=vdd}
+N 300 -40 300 20 { lab=Q}
+N 60 50 300 50 { lab=vss}
+N 60 -10 130 -10 { lab=nQ}
+N 130 -10 220 -70 { lab=nQ}
+N 220 -70 260 -70 { lab=nQ}
+N 100 -70 130 -70 { lab=Q}
+N 130 -70 230 -10 { lab=Q}
+N 230 -10 300 -10 { lab=Q}
+N -10 -70 60 -70 { lab=vdd}
+N -10 -140 -10 -70 { lab=vdd}
+N -10 -140 60 -140 { lab=vdd}
+N 300 -70 370 -70 { lab=vdd}
+N 370 -140 370 -70 { lab=vdd}
+N 300 -140 370 -140 { lab=vdd}
+N -10 -10 60 -10 { lab=nQ}
+N 300 -10 370 -10 { lab=Q}
+N -10 50 20 50 { lab=D}
+N 340 50 370 50 { lab=nD}
+N -10 150 140 150 { lab=CLK}
+N 180 180 180 210 { lab=vss}
+N 180 150 220 150 { lab=vss}
+N -30 210 180 210 { lab=vss}
+N -30 -140 -10 -140 { lab=vdd}
+N -30 -10 -10 -10 { lab=nQ}
+N -30 50 -10 50 { lab=D}
+N -30 150 -10 150 { lab=CLK}
+C {sky130_fd_pr/nfet_01v8.sym} 160 150 0 0 {name=M3
+L=0.15
+W=1.25
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -30 -140 2 0 {name=p1 lab=vdd}
+C {iopin.sym} -30 210 2 0 {name=p2 lab=vss}
+C {ipin.sym} -30 50 0 0 {name=p4 lab=D}
+C {opin.sym} -30 -10 2 0 {name=p5 lab=nQ}
+C {ipin.sym} -30 150 0 0 {name=p3 lab=CLK}
+C {lab_pin.sym} 220 150 2 0 {name=l6 lab=vss}
+C {ipin.sym} 370 50 2 0 {name=p6 lab=nD}
+C {opin.sym} 370 -10 0 0 {name=p7 lab=Q}
+C {lab_wire.sym} 160 50 0 1 {name=l1 lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 80 -70 0 1 {name=M4
+L=0.15
+W=0.95
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 280 -70 0 0 {name=M5
+L=0.15
+W=0.95
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 40 50 0 0 {name=M1
+L=0.15
+W=0.95
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 320 50 0 1 {name=M2
+L=0.15
+W=0.95
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
diff --git a/xschem/latch_diff.sym b/xschem/latch_diff.sym
new file mode 100644
index 0000000..34bb3fc
--- /dev/null
+++ b/xschem/latch_diff.sym
@@ -0,0 +1,36 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 40 70 40 {}
+L 4 50 -40 70 -40 {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 40 -50 40 {}
+L 4 0 60 0 80 {}
+L 4 -50 -60 -50 60 {}
+L 4 50 -60 50 60 {}
+L 4 -50 60 50 60 {}
+L 4 -50 -60 50 -60 {}
+L 7 0 -80 0 -60 {}
+L 7 20 60 20 80 {}
+B 5 -2.5 -82.5 2.5 -77.5 {name=vdd dir=inout }
+B 5 67.5 37.5 72.5 42.5 {name=nQ dir=out }
+B 5 67.5 -42.5 72.5 -37.5 {name=Q dir=out }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=D dir=in }
+B 5 -72.5 37.5 -67.5 42.5 {name=nD dir=in }
+B 5 -2.5 77.5 2.5 82.5 {name=CLK dir=in }
+B 5 17.5 77.5 22.5 82.5 {name=vss dir=inout }
+T {@symname} 7 -76 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vdd} -14 -85 3 1 0.2 0.2 {}
+T {nQ} 45 36 0 1 0.2 0.2 {}
+T {Q} 45 -44 0 1 0.2 0.2 {}
+T {D} -45 -44 0 0 0.2 0.2 {}
+T {nD} -45 36 0 0 0.2 0.2 {}
+T {CLK} -14 45 0 0 0.2 0.2 {}
+T {vss} 34 85 1 1 0.2 0.2 {}
diff --git a/xschem/loop_filter.sch b/xschem/loop_filter.sch
new file mode 100644
index 0000000..a345bac
--- /dev/null
+++ b/xschem/loop_filter.sch
@@ -0,0 +1,37 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 420 300 420 340 { lab=vss}
+N 420 -110 420 -80 { lab=in}
+N 650 300 650 320 { lab=vss}
+N 650 -100 650 -80 { lab=in}
+N 420 -100 650 -100 { lab=in}
+N 350 20 350 40 { lab=#net1}
+N 350 20 420 20 { lab=#net1}
+N 420 -0 420 20 { lab=#net1}
+N 420 20 510 20 { lab=#net1}
+N 510 20 510 40 { lab=#net1}
+N 350 120 350 140 { lab=vc_pex}
+N 350 140 510 140 { lab=vc_pex}
+N 510 120 510 140 { lab=vc_pex}
+N 650 100 650 300 { lab=vss}
+N 650 -80 650 20 { lab=in}
+N 420 140 420 210 { lab=vc_pex}
+N 420 210 420 220 { lab=vc_pex}
+N 400 80 460 80 { lab=vss}
+N 350 -40 370 -40 { lab=vss}
+N 420 180 450 180 { lab=vc_pex}
+C {iopin.sym} 420 -110 3 0 {name=p2 lab=in}
+C {iopin.sym} 420 340 1 0 {name=p3 lab=vss}
+C {lab_pin.sym} 650 320 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {res_loop_filter.sym} 420 -40 0 0 {name=x1}
+C {res_loop_filter.sym} 350 80 2 0 {name=x2}
+C {res_loop_filter.sym} 510 80 2 1 {name=x3}
+C {cap1_loop_filter.sym} 420 260 0 0 {name=x4}
+C {cap2_loop_filter.sym} 650 60 0 0 {name=x5}
+C {lab_pin.sym} 430 80 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -40 2 1 {name=l3 sig_type=std_logic lab=vss}
+C {iopin.sym} 450 180 0 0 {name=p1 lab=vc_pex}
diff --git a/xschem/loop_filter.sym b/xschem/loop_filter.sym
new file mode 100644
index 0000000..cffe115
--- /dev/null
+++ b/xschem/loop_filter.sym
@@ -0,0 +1,24 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 40 -50 40 50 {}
+L 4 -40 -50 -40 50 {}
+L 4 -40 -50 40 -50 {}
+L 4 -40 50 40 50 {}
+L 7 0 50 0 70 {}
+L 7 0 -70 0 -50 {}
+L 7 40 0 60 0 {}
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+B 5 -2.5 -72.5 2.5 -67.5 {name=in dir=inout }
+B 5 57.5 -2.5 62.5 2.5 {name=vc_pex dir=inout }
+T {@symname} 52.5 34 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vss} -6 75 1 1 0.2 0.2 {}
+T {in} -14 -75 3 1 0.2 0.2 {}
+T {vc_pex} 75 -14 0 1 0.2 0.2 {}
diff --git a/xschem/loop_filter_pex_c.sym b/xschem/loop_filter_pex_c.sym
new file mode 100644
index 0000000..a7d0cd0
--- /dev/null
+++ b/xschem/loop_filter_pex_c.sym
@@ -0,0 +1,24 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 40 -50 40 50 {}
+L 4 -40 -50 -40 50 {}
+L 4 -40 -50 40 -50 {}
+L 4 -40 50 40 50 {}
+L 7 0 50 0 70 {}
+L 7 0 -70 0 -50 {}
+L 7 40 0 60 0 {}
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+B 5 -2.5 -72.5 2.5 -67.5 {name=in dir=inout }
+B 5 57.5 -2.5 62.5 2.5 {name=vc_pex dir=inout }
+T {@symname} 52.5 34 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vss} -6 75 1 1 0.2 0.2 {}
+T {in} -14 -75 3 1 0.2 0.2 {}
+T {vc_pex} 75 -14 0 1 0.2 0.2 {}
diff --git a/xschem/loop_filter_v2.sch b/xschem/loop_filter_v2.sch
new file mode 100644
index 0000000..7b8ae90
--- /dev/null
+++ b/xschem/loop_filter_v2.sch
@@ -0,0 +1,63 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 420 300 420 340 { lab=vss}
+N 420 -110 420 -80 { lab=in}
+N 650 300 650 320 { lab=vss}
+N 650 -100 650 -80 { lab=in}
+N 420 -100 650 -100 { lab=in}
+N 350 20 350 40 { lab=#net1}
+N 350 20 420 20 { lab=#net1}
+N 420 -0 420 20 { lab=#net1}
+N 420 20 510 20 { lab=#net1}
+N 510 20 510 40 { lab=#net1}
+N 350 120 350 140 { lab=vc_pex}
+N 350 140 510 140 { lab=vc_pex}
+N 510 120 510 140 { lab=vc_pex}
+N 650 100 650 300 { lab=vss}
+N 650 -80 650 20 { lab=in}
+N 420 140 420 210 { lab=vc_pex}
+N 420 210 420 220 { lab=vc_pex}
+N 400 80 460 80 { lab=vss}
+N 350 -40 370 -40 { lab=vss}
+N 420 180 450 180 { lab=vc_pex}
+N 830 -100 830 -60 { lab=in}
+N 650 -100 740 -100 { lab=in}
+N 870 -30 900 -30 { lab=in}
+N 740 -100 830 -100 { lab=in}
+N 810 -30 830 -30 { lab=vss}
+N 830 -0 830 90 { lab=#net2}
+N 830 310 830 330 { lab=vss}
+N 830 170 830 310 { lab=vss}
+C {iopin.sym} 420 -110 3 0 {name=p2 lab=in}
+C {iopin.sym} 420 340 1 0 {name=p3 lab=vss}
+C {lab_pin.sym} 650 320 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {res_loop_filter.sym} 420 -40 0 0 {name=x1}
+C {res_loop_filter.sym} 350 80 2 0 {name=x2}
+C {res_loop_filter.sym} 510 80 2 1 {name=x3}
+C {cap1_loop_filter.sym} 420 260 0 0 {name=x4}
+C {cap2_loop_filter.sym} 650 60 0 0 {name=x5}
+C {lab_pin.sym} 430 80 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -40 2 1 {name=l3 sig_type=std_logic lab=vss}
+C {iopin.sym} 450 180 0 0 {name=p1 lab=vc_pex}
+C {sky130_fd_pr/nfet_01v8.sym} 850 -30 0 1 {name=M1
+L=0.3
+W=3
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 900 -30 0 0 {name=p4 lab=D0_cap}
+C {lab_pin.sym} 810 -30 0 0 {name=l4 sig_type=std_logic lab=vss}
+C {cap3_loop_filter.sym} 830 130 0 0 {name=x6}
+C {lab_pin.sym} 830 330 3 0 {name=l5 sig_type=std_logic lab=vss}
diff --git a/xschem/loop_filter_v2.sym b/xschem/loop_filter_v2.sym
new file mode 100644
index 0000000..7b21685
--- /dev/null
+++ b/xschem/loop_filter_v2.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 40 -50 40 50 {}
+L 4 -40 -50 -40 50 {}
+L 4 -40 -50 40 -50 {}
+L 4 -40 50 40 50 {}
+L 7 0 50 0 70 {}
+L 7 0 -70 0 -50 {}
+L 7 40 0 60 0 {}
+L 7 -60 0 -40 0 {}
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+B 5 -2.5 -72.5 2.5 -67.5 {name=in dir=inout }
+B 5 57.5 -2.5 62.5 2.5 {name=vc_pex dir=inout }
+B 5 -62.5 -2.5 -57.5 2.5 {name=D0_cap dir=inout }
+T {@symname} 52.5 34 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vss} -6 75 1 1 0.2 0.2 {}
+T {in} -14 -75 3 1 0.2 0.2 {}
+T {vc_pex} 75 -14 0 1 0.2 0.2 {}
+T {D0_cap} -85 -16 0 0 0.2 0.2 {}
diff --git a/xschem/mux_2to1_logic.sch b/xschem/mux_2to1_logic.sch
new file mode 100644
index 0000000..62e648c
--- /dev/null
+++ b/xschem/mux_2to1_logic.sch
@@ -0,0 +1,112 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 20 -170 60 -170 { lab=DinB}
+N 20 -270 20 -170 { lab=DinB}
+N 20 -270 60 -270 { lab=DinB}
+N -80 -220 20 -220 { lab=DinB}
+N 120 -170 160 -170 { lab=out}
+N 160 -270 160 -170 { lab=out}
+N 120 -270 160 -270 { lab=out}
+N 160 -220 240 -220 { lab=out}
+N 20 90 60 90 { lab=DinA}
+N 20 -10 20 90 { lab=DinA}
+N 20 -10 60 -10 { lab=DinA}
+N -80 40 20 40 { lab=DinA}
+N 120 90 160 90 { lab=out}
+N 160 -10 160 90 { lab=out}
+N 120 -10 160 -10 { lab=out}
+N 160 40 240 40 { lab=out}
+N 240 -220 240 40 { lab=out}
+N 240 -100 360 -100 { lab=out}
+N 90 -270 90 -250 { lab=avdd1p8}
+N 90 -250 140 -250 { lab=avdd1p8}
+N 90 -190 90 -170 { lab=avss1p8}
+N 40 -190 90 -190 { lab=avss1p8}
+N 90 -10 90 10 { lab=avdd1p8}
+N 90 10 140 10 { lab=avdd1p8}
+N 90 70 90 90 { lab=avss1p8}
+N 40 70 90 70 { lab=avss1p8}
+N 90 -365 90 -310 { lab=sel_b}
+N 90 -125 90 -50 { lab=sel}
+N 90 135 90 190 { lab=sel_b}
+N 90 -130 90 -125 { lab=sel}
+N 90 130 90 135 { lab=sel_b}
+N -145 -490 -90 -490 { lab=sel}
+N 40 -490 105 -490 { lab=sel_b}
+N -50 -575 -50 -540 { lab=avdd1p8}
+N -50 -440 -50 -405 { lab=avss1p8}
+C {lab_wire.sym} 90 -335 0 0 {name=l1 sig_type=std_logic lab=sel_b}
+C {lab_wire.sym} 90 175 0 0 {name=l2 sig_type=std_logic lab=sel_b}
+C {lab_wire.sym} 90 -85 0 0 {name=l3 sig_type=std_logic lab=sel}
+C {lab_wire.sym} 100 -250 2 0 {name=l6 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 95 10 2 0 {name=l7 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 90 -190 0 0 {name=l8 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 90 70 0 0 {name=l9 sig_type=std_logic lab=avss1p8}
+C {ipin.sym} -80 -220 0 0 {name=p3 lab=DinB}
+C {ipin.sym} -80 40 0 0 {name=p4 lab=DinA}
+C {iopin.sym} -50 -575 2 0 {name=p1 lab=avdd1p8}
+C {iopin.sym} -50 -405 2 0 {name=p2 lab=avss1p8}
+C {ipin.sym} -145 -490 0 0 {name=p6 lab=sel}
+C {lab_wire.sym} 90 -490 0 0 {name=l4 sig_type=std_logic lab=sel_b}
+C {opin.sym} 360 -100 0 0 {name=p5 lab=out}
+C {sky130_fd_pr/pfet_01v8.sym} 90 -290 3 1 {name=M5
+L=0.15
+W=2.22
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 90 -150 3 0 {name=M6
+L=0.15
+W=1.11
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 90 -30 3 1 {name=M2
+L=0.15
+W=2.22
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 90 110 3 0 {name=M7
+L=0.15
+W=1.11
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {inverter_min.sym} -30 -490 0 0 {name=x1}
diff --git a/xschem/mux_2to1_logic.sym b/xschem/mux_2to1_logic.sym
new file mode 100644
index 0000000..f623d3f
--- /dev/null
+++ b/xschem/mux_2to1_logic.sym
@@ -0,0 +1,35 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 240 -220 240 -160 {}
+L 4 250 -160 250 -140 {}
+L 4 220 -200 240 -200 {}
+L 4 270 -190 290 -190 {}
+L 4 220 -180 240 -180 {}
+L 4 270 -210 270 -170 {}
+L 4 240 -220 270 -210 {}
+L 4 240 -160 270 -170 {}
+L 7 260 -240 260 -220 {}
+L 7 250 -240 250 -220 {}
+B 5 257.5 -242.5 262.5 -237.5 {name=avdd1p8 dir=inout }
+B 5 247.5 -142.5 252.5 -137.5 {name=sel dir=in }
+B 5 247.5 -242.5 252.5 -237.5 {name=avss1p8 dir=inout }
+B 5 217.5 -202.5 222.5 -197.5 {name=DinB dir=in }
+B 5 287.5 -192.5 292.5 -187.5 {name=out dir=out }
+B 5 217.5 -182.5 222.5 -177.5 {name=DinA dir=in }
+T {@symname} 279 -216 0 0 0.3 0.3 {}
+T {@name} 265 -162 0 0 0.2 0.2 {}
+T {avdd1p8} 284 -225 1 1 0.2 0.2 {}
+T {sel} 244 -145 1 0 0.2 0.2 {}
+T {avss1p8} 244 -225 1 1 0.2 0.2 {}
+T {DinB} 195 -214 0 0 0.2 0.2 {}
+T {out} 305 -184 0 1 0.2 0.2 {}
+T {DinA} 195 -174 0 0 0.2 0.2 {}
+T {0} 250 -180 0 0 0.2 0.2 {}
+T {1} 250 -210 0 0 0.2 0.2 {}
diff --git a/xschem/nand_logic.sch b/xschem/nand_logic.sch
new file mode 100644
index 0000000..2ff4039
--- /dev/null
+++ b/xschem/nand_logic.sch
@@ -0,0 +1,97 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 0 -210 0 -190 { lab=avdd1p8}
+N 0 -210 150 -210 { lab=avdd1p8}
+N 150 -210 150 -190 { lab=avdd1p8}
+N 0 -130 0 -40 { lab=out}
+N 0 -80 150 -80 { lab=out}
+N 0 20 0 80 { lab=n1}
+N 0 140 0 170 { lab=avss1p8}
+N 60 -240 60 -210 { lab=avdd1p8}
+N -100 -160 -40 -160 { lab=in1}
+N -100 -160 -100 -110 { lab=in1}
+N -170 -110 -100 -110 { lab=in1}
+N -100 -110 -100 110 { lab=in1}
+N -100 110 -40 110 { lab=in1}
+N 80 -160 110 -160 { lab=in2}
+N 80 -160 80 -110 { lab=in2}
+N -70 -110 80 -110 { lab=in2}
+N -70 -110 -70 -10 { lab=in2}
+N -70 -10 -40 -10 { lab=in2}
+N -170 -70 -70 -70 { lab=in2}
+N 0 -10 30 -10 { lab=avss1p8}
+N 0 110 30 110 { lab=avss1p8}
+N 150 -160 180 -160 { lab=avdd1p8}
+N 0 -160 30 -160 { lab=avdd1p8}
+N 150 -80 350 -80 { lab=out}
+N 150 -130 150 -80 { lab=out}
+C {ipin.sym} -170 -110 0 0 {name=p1 lab=in1}
+C {ipin.sym} -170 -70 0 0 {name=p2 lab=in2}
+C {opin.sym} 350 -80 0 0 {name=p3 lab=out}
+C {iopin.sym} 60 -240 0 0 {name=p4 lab=avdd1p8}
+C {iopin.sym} 0 170 0 0 {name=p5 lab=avss1p8}
+C {lab_wire.sym} 20 -160 2 0 {name=l3 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 170 -160 2 0 {name=l4 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 20 110 2 0 {name=l7 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 20 -10 2 0 {name=l8 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 0 50 0 0 {name=l9 sig_type=std_logic lab=n1}
+C {sky130_fd_pr/pfet_01v8.sym} 130 -160 0 0 {name=M4
+L=0.15
+W=1.02
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} -20 110 0 0 {name=M5
+L=0.15
+W=1.02
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} -20 -10 0 0 {name=M1
+L=0.15
+W=1.02
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -20 -160 0 0 {name=M2
+L=0.15
+W=1.02
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
diff --git a/xschem/nand_logic.sym b/xschem/nand_logic.sym
new file mode 100644
index 0000000..0ddadda
--- /dev/null
+++ b/xschem/nand_logic.sym
@@ -0,0 +1,32 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -120 -30 -120 {}
+L 4 -30 -130 -30 -70 {}
+L 4 -30 -130 0 -130 {}
+L 4 -30 -70 0 -70 {}
+L 4 -50 -80 -30 -80 {}
+L 4 50 -100 60 -100 {}
+L 4 40 -100 50 -100 {}
+L 7 -10 -150 -10 -130 {}
+L 7 -10 -70 -10 -50 {}
+B 5 -12.5 -152.5 -7.5 -147.5 {name=avdd1p8 dir=inout }
+B 5 -52.5 -122.5 -47.5 -117.5 {name=in1 dir=in }
+B 5 57.5 -102.5 62.5 -97.5 {name=out dir=out }
+B 5 -52.5 -82.5 -47.5 -77.5 {name=in2 dir=in }
+B 5 -12.5 -52.5 -7.5 -47.5 {name=avss1p8 dir=inout }
+A 4 40 -100 5 180 360 {}
+A 4 0 -100 30 270 180 {}
+T {@symname} 19 -156 0 0 0.3 0.3 {}
+T {@name} 25 -132 0 0 0.2 0.2 {}
+T {avdd1p8} -15 -154 0 1 0.2 0.2 {}
+T {in1} -75 -124 0 0 0.2 0.2 {}
+T {out} 75 -94 0 1 0.2 0.2 {}
+T {in2} -75 -84 0 0 0.2 0.2 {}
+T {avss1p8} -15 -54 0 1 0.2 0.2 {}
diff --git a/xschem/nor.sch b/xschem/nor.sch
new file mode 100644
index 0000000..07b6bfa
--- /dev/null
+++ b/xschem/nor.sch
@@ -0,0 +1,131 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 210 80 210 130 { lab=out}
+N 210 80 420 80 { lab=out}
+N 420 80 420 130 { lab=out}
+N 420 30 420 80 { lab=out}
+N 210 -80 210 -30 { lab=#net1}
+N 210 30 210 80 { lab=out}
+N 420 -80 420 -30 { lab=#net2}
+N 210 -180 210 -140 { lab=vdd}
+N 210 -180 420 -180 { lab=vdd}
+N 420 -180 420 -140 { lab=vdd}
+N 420 190 420 230 { lab=vss}
+N 210 230 420 230 { lab=vss}
+N 210 190 210 230 { lab=vss}
+N 210 160 420 160 { lab=vss}
+N 320 160 320 230 { lab=vss}
+N 210 -110 320 -110 { lab=vdd}
+N 320 -110 420 -110 { lab=vdd}
+N 320 -180 320 -110 { lab=vdd}
+N 350 0 420 0 { lab=vdd}
+N 210 0 280 0 { lab=vdd}
+N 100 230 210 230 { lab=vss}
+N 100 -180 210 -180 { lab=vdd}
+N 100 0 170 -0 { lab=B}
+N 100 -110 170 -110 { lab=A}
+N 100 160 170 160 { lab=A}
+N 460 -110 520 -110 { lab=B}
+N 460 0 520 0 { lab=A}
+N 460 160 520 160 { lab=B}
+N 420 80 520 80 { lab=out}
+N 320 -110 320 0 { lab=vdd}
+N 280 -0 320 0 { lab=vdd}
+N 320 0 350 -0 { lab=vdd}
+C {sky130_fd_pr/nfet_01v8.sym} 190 160 0 0 {name=M1
+L=0.15
+W=0.45
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 440 160 0 1 {name=M2
+L=0.15
+W=0.45
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} 100 -110 0 0 {name=p1 lab=A}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=B}
+C {lab_pin.sym} 100 160 0 0 {name=l1 sig_type=std_logic lab=A}
+C {iopin.sym} 100 -180 2 0 {name=p3 lab=vdd}
+C {opin.sym} 520 80 0 0 {name=p4 lab=out}
+C {iopin.sym} 100 230 2 0 {name=p5 lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 190 0 0 0 {name=M4
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 520 0 2 0 {name=l2 sig_type=std_logic lab=A}
+C {lab_pin.sym} 520 160 2 0 {name=l3 sig_type=std_logic lab=B}
+C {lab_pin.sym} 520 -110 2 0 {name=l4 sig_type=std_logic lab=B}
+C {sky130_fd_pr/pfet_01v8.sym} 190 -110 0 0 {name=M3
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 440 -110 0 1 {name=M5
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 440 0 0 1 {name=M6
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
diff --git a/xschem/nor.sym b/xschem/nor.sym
new file mode 100644
index 0000000..cf80fc8
--- /dev/null
+++ b/xschem/nor.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -20 -30 -20 {}
+L 4 -50 20 -30 20 {}
+L 4 30 0 50 0 {}
+L 7 0 -40 0 -20 {}
+L 7 0 20 0 40 {}
+B 5 -2.5 -42.5 2.5 -37.5 {name=vdd dir=inout }
+B 5 -52.5 -22.5 -47.5 -17.5 {name=A dir=in }
+B 5 -52.5 17.5 -47.5 22.5 {name=B dir=in }
+B 5 47.5 -2.5 52.5 2.5 {name=out dir=out }
+B 5 -2.5 37.5 2.5 42.5 {name=vss dir=inout }
+A 4 -60 -0 36.05551275463989 303.6900675259798 112.6198649480405 {}
+A 4 -35 35 65.19202405202648 32.47119229084849 61.92751306414704 {}
+A 4 25 -0.5 5.024937810560445 354.2894068625004 360 {}
+A 4 -35 -35 65.19202405202648 265.6012946450045 61.92751306414704 {}
+T {@symname} 14.5 7 0 0 0.3 0.3 {}
+T {@name} -17 -7 0 0 0.2 0.2 {}
+T {vdd} -14 -45 3 1 0.2 0.2 {}
+T {A} -47 -30 0 0 0.2 0.2 {}
+T {B} -47 10 0 0 0.2 0.2 {}
+T {out} 47 -10 0 1 0.2 0.2 {}
+T {vss} -6 45 1 1 0.2 0.2 {}
diff --git a/xschem/pfd_cp_interface.sch b/xschem/pfd_cp_interface.sch
new file mode 100644
index 0000000..37d1f7b
--- /dev/null
+++ b/xschem/pfd_cp_interface.sch
@@ -0,0 +1,64 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -220 -200 -220 -170 { lab=vdd}
+N -220 -70 -220 -40 { lab=vss}
+N -220 40 -220 70 { lab=vdd}
+N -220 170 -220 200 { lab=vss}
+N -290 -120 -260 -120 { lab=QA}
+N -290 120 -260 120 { lab=QB}
+N -30 -200 -30 -170 { lab=vdd}
+N -30 -70 -30 -40 { lab=vss}
+N 20 0 20 30 { lab=vdd}
+N -130 120 -70 120 { lab=nQB}
+N 20 220 20 250 { lab=vss}
+N -130 -120 -70 -120 { lab=nQA}
+N 110 120 170 120 { lab=nDown}
+N 60 -120 170 -120 { lab=Up}
+N 210 170 210 200 { lab=vss}
+N 210 40 210 70 { lab=vdd}
+N 210 -70 210 -40 { lab=vss}
+N 210 -200 210 -170 { lab=vdd}
+N 300 -120 360 -120 { lab=nUp}
+N 300 120 360 120 { lab=Down}
+N 130 120 130 250 { lab=nDown}
+N 130 -250 130 -120 { lab=Up}
+N 360 -120 420 -120 { lab=nUp}
+N 360 120 420 120 { lab=Down}
+N 130 250 420 250 { lab=nDown}
+N 130 -250 420 -250 { lab=Up}
+N -360 120 -290 120 { lab=QB}
+N -360 -120 -290 -120 { lab=QA}
+C {lab_wire.sym} 110 -120 0 0 {name=l20 sig_type=std_logic lab=Up}
+C {lab_wire.sym} 350 120 0 0 {name=l21 sig_type=std_logic lab=Down}
+C {trans_gate.sym} 20 120 0 0 {name=x5}
+C {iopin.sym} -220 -200 3 0 {name=p7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -220 -40 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -220 40 1 0 {name=l10 sig_type=std_logic lab=vdd}
+C {iopin.sym} -220 200 1 0 {name=p11 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -200 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 20 0 1 0 {name=l19 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -30 -40 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 20 250 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 210 200 3 0 {name=l23 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 210 40 1 0 {name=l24 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 210 -40 3 0 {name=l25 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 210 -200 1 0 {name=l26 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 350 -120 0 0 {name=l29 sig_type=std_logic lab=nUp}
+C {lab_wire.sym} 160 120 0 0 {name=l30 sig_type=std_logic lab=nDown}
+C {lab_wire.sym} -90 120 0 0 {name=l33 sig_type=std_logic lab=nQB}
+C {lab_wire.sym} -90 -120 0 0 {name=l34 sig_type=std_logic lab=nQA}
+C {inverter_cp_x1.sym} -10 -120 0 0 {name=x3}
+C {ipin.sym} -360 -120 0 0 {name=p1 lab=QA}
+C {ipin.sym} -360 120 0 0 {name=p2 lab=QB}
+C {opin.sym} 420 250 0 0 {name=p3 lab=nDown}
+C {opin.sym} 420 120 0 0 {name=p4 lab=Down}
+C {opin.sym} 420 -120 0 0 {name=p5 lab=nUp}
+C {opin.sym} 420 -250 0 0 {name=p6 lab=Up}
+C {inverter_cp_x1.sym} -200 120 0 0 {name=x1}
+C {inverter_cp_x1.sym} -200 -120 0 0 {name=x2}
+C {inverter_cp_x2.sym} 230 -120 0 0 {name=x4}
+C {inverter_cp_x2.sym} 230 120 0 0 {name=x6}
diff --git a/xschem/pfd_cp_interface.sym b/xschem/pfd_cp_interface.sym
new file mode 100644
index 0000000..fc77e91
--- /dev/null
+++ b/xschem/pfd_cp_interface.sym
@@ -0,0 +1,43 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -60 -50 60 {}
+L 4 50 -60 50 60 {}
+L 4 50 -60 70 -60 {}
+L 4 -70 -40 -50 -40 {}
+L 4 50 -20 70 -20 {}
+L 4 50 20 70 20 {}
+L 4 -70 40 -50 40 {}
+L 4 50 60 70 60 {}
+L 4 -50 80 50 80 {}
+L 4 -50 -80 50 -80 {}
+L 4 -50 -80 -50 -60 {}
+L 4 -50 60 -50 80 {}
+L 4 50 60 50 80 {}
+L 4 50 -80 50 -60 {}
+L 7 0 -100 0 -80 {}
+L 7 0 80 0 100 {}
+B 5 67.5 -62.5 72.5 -57.5 {name=Up dir=out }
+B 5 -2.5 -102.5 2.5 -97.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=QA dir=in }
+B 5 67.5 -22.5 72.5 -17.5 {name=nUp dir=out }
+B 5 67.5 17.5 72.5 22.5 {name=Down dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=QB dir=in }
+B 5 -2.5 97.5 2.5 102.5 {name=vss sig_type=std_logic dir=inout }
+B 5 67.5 57.5 72.5 62.5 {name=nDown dir=out }
+T {@symname} 10 84 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {Up} 45 -64 0 1 0.2 0.2 {}
+T {vdd} -14 -105 3 1 0.2 0.2 {}
+T {QA} -45 -44 0 0 0.2 0.2 {}
+T {nUp} 45 -24 0 1 0.2 0.2 {}
+T {Down} 45 16 0 1 0.2 0.2 {}
+T {QB} -45 36 0 0 0.2 0.2 {}
+T {vss} -6 105 1 1 0.2 0.2 {}
+T {nDown} 45 56 0 1 0.2 0.2 {}
diff --git a/xschem/pfd_cp_interface_pex_c.sym b/xschem/pfd_cp_interface_pex_c.sym
new file mode 100644
index 0000000..dcaecae
--- /dev/null
+++ b/xschem/pfd_cp_interface_pex_c.sym
@@ -0,0 +1,43 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -60 -50 60 {}
+L 4 50 -60 50 60 {}
+L 4 50 -60 70 -60 {}
+L 4 -70 -40 -50 -40 {}
+L 4 50 -20 70 -20 {}
+L 4 50 20 70 20 {}
+L 4 -70 40 -50 40 {}
+L 4 50 60 70 60 {}
+L 4 -50 80 50 80 {}
+L 4 -50 -80 50 -80 {}
+L 4 -50 -80 -50 -60 {}
+L 4 -50 60 -50 80 {}
+L 4 50 60 50 80 {}
+L 4 50 -80 50 -60 {}
+L 7 0 -100 0 -80 {}
+L 7 0 80 0 100 {}
+B 5 67.5 -62.5 72.5 -57.5 {name=Up dir=out }
+B 5 -2.5 -102.5 2.5 -97.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=QA dir=in }
+B 5 67.5 -22.5 72.5 -17.5 {name=nUp dir=out }
+B 5 67.5 17.5 72.5 22.5 {name=Down dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=QB dir=in }
+B 5 -2.5 97.5 2.5 102.5 {name=vss sig_type=std_logic dir=inout }
+B 5 67.5 57.5 72.5 62.5 {name=nDown dir=out }
+T {@symname} 10 84 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {Up} 45 -64 0 1 0.2 0.2 {}
+T {vdd} -14 -105 3 1 0.2 0.2 {}
+T {QA} -45 -44 0 0 0.2 0.2 {}
+T {nUp} 45 -24 0 1 0.2 0.2 {}
+T {Down} 45 16 0 1 0.2 0.2 {}
+T {QB} -45 36 0 0 0.2 0.2 {}
+T {vss} -6 105 1 1 0.2 0.2 {}
+T {nDown} 45 56 0 1 0.2 0.2 {}
diff --git a/xschem/res_amp_lin.sch b/xschem/res_amp_lin.sch
new file mode 100644
index 0000000..70a3d08
--- /dev/null
+++ b/xschem/res_amp_lin.sch
@@ -0,0 +1,195 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 790 -60 790 -30 { lab=avss1p8}
+N 1110 -60 1110 -30 { lab=avss1p8}
+N 1110 -260 1110 -190 { lab=outp}
+N 790 -260 790 -190 { lab=outn}
+N 790 -350 790 -320 { lab=vp}
+N 1110 -350 1110 -320 { lab=vp}
+N 950 -400 950 -350 { lab=vp}
+N 950 -510 950 -460 { lab=int}
+N 950 -620 950 -570 { lab=avdd1p8}
+N 950 -30 950 20 { lab=avss1p8}
+N 1110 -220 1220 -220 { lab=outp}
+N 680 -220 790 -220 { lab=outn}
+N 1150 -290 1210 -290 { lab=inn}
+N 690 -290 750 -290 { lab=inp}
+N 870 -540 910 -540 { lab=clk}
+N 800 -540 870 -540 { lab=clk}
+N 1100 -290 1110 -290 { lab=avdd1p8}
+N 1100 -290 1100 -240 { lab=avdd1p8}
+N 790 -290 800 -290 { lab=avdd1p8}
+N 800 -290 800 -240 { lab=avdd1p8}
+N 790 -350 1110 -350 { lab=vp}
+N 790 -30 1110 -30 { lab=avss1p8}
+N 950 -430 1000 -430 { lab=avdd1p8}
+N 950 -540 1000 -540 { lab=avdd1p8}
+N 830 -100 1070 -100 { lab=clk}
+N 790 -190 790 -130 { lab=outn}
+N 790 -70 790 -60 { lab=avss1p8}
+N 1110 -70 1110 -60 { lab=avss1p8}
+N 1110 -190 1110 -130 { lab=outp}
+N 1110 -100 1120 -100 { lab=avss1p8}
+N 1120 -100 1120 -30 { lab=avss1p8}
+N 1110 -30 1120 -30 { lab=avss1p8}
+N 780 -100 790 -100 { lab=avss1p8}
+N 780 -100 780 -30 { lab=avss1p8}
+N 780 -30 790 -30 { lab=avss1p8}
+N 800 -430 910 -430 { lab=vctrl}
+C {iopin.sym} 950 -620 0 0 {name=p5 lab=avdd1p8}
+C {iopin.sym} 950 20 0 0 {name=p6 lab=avss1p8}
+C {ngspice_get_value.sym} 710 -360 0 0 {name=r1 node="v(@M.X3.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 710 -330 0 0 {name=r2 node="v(@M.X3.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 640 -360 0 0 {name=r11 node="i(@M.X3.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[id])"
+descr="id="}
+C {opin.sym} 1220 -220 0 0 {name=p9 lab=outp}
+C {opin.sym} 680 -220 2 0 {name=p10 lab=outn}
+C {ipin.sym} 1210 -290 2 0 {name=p11 lab=inn}
+C {ipin.sym} 690 -290 0 0 {name=p12 lab=inp}
+C {ipin.sym} 800 -540 0 0 {name=p13 lab=clk}
+C {lab_wire.sym} 1100 -280 3 0 {name=l12 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 800 -280 1 1 {name=l13 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 990 -430 2 0 {name=l14 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 990 -540 2 0 {name=l15 sig_type=std_logic lab=avdd1p8}
+C {ngspice_probe.sym} 1010 -350 0 0 {name=r19}
+C {lab_wire.sym} 930 -350 0 0 {name=l16 sig_type=std_logic lab=vp}
+C {ngspice_probe.sym} 950 -480 0 0 {name=r20}
+C {ngspice_get_value.sym} 1070 -430 0 0 {name=r26 node="v(@M.X3.X1.XM3.msky130_fd_pr__pfet_01v8_lvt[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 1070 -400 0 0 {name=r27 node="v(@M.X3.X1.XM3.msky130_fd_pr__pfet_01v8_lvt[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 1140 -430 0 0 {name=r28 node="v(@M.X3.X1.XM3.msky130_fd_pr__pfet_01v8_lvt[vdsat])"
+descr="vdsat="}
+C {ngspice_get_value.sym} 1140 -400 0 0 {name=r29 node="i(@M.X3.X1.XM3.msky130_fd_pr__pfet_01v8_lvt[id])"
+descr="id="}
+C {ngspice_get_value.sym} 640 -300 0 0 {name=r3 node="v(@M.X3.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[vth])"
+descr="vth="}
+C {lab_wire.sym} 950 -100 2 0 {name=l1 sig_type=std_logic lab=clk}
+C {sky130_fd_pr/pfet_01v8.sym} 930 -540 0 0 {name=M6
+L=0.15
+W=1
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 810 -100 0 1 {name=M8
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 1090 -100 0 0 {name=M9
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {ngspice_get_value.sym} 1190 -110 0 0 {name=r18 node="v(@M.X3.X1.XM9.msky130_fd_pr__nfet_01v8_lvt[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 1190 -80 0 0 {name=r30 node="v(@M.X3.X1.XM9.msky130_fd_pr__nfet_01v8_lvt[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 1240 -110 0 0 {name=r31 node="v(@M.X3.X1.XM9.msky130_fd_pr__nfet_01v8_lvt[vdsat])"
+descr="vdsat="}
+C {ngspice_get_value.sym} 1240 -80 0 0 {name=r32 node="i(@M.X3.X1.XM9.msky130_fd_pr__nfet_01v8_lvt[id])"
+descr="id="}
+C {ngspice_get_value.sym} 640 -330 0 0 {name=r33 node="@M.X3.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[gm]"
+descr="gm="}
+C {ngspice_get_value.sym} 1190 -40 0 0 {name=r34 node="@M.X3.X1.XM9.msky130_fd_pr__nfet_01v8_lvt[gds]"
+descr="gds="}
+C {ngspice_get_value.sym} 710 -300 0 0 {name=r35 node="@M.X3.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[gds]"
+descr="gds="}
+C {ipin.sym} 800 -430 0 0 {name=p1 lab=vctrl}
+C {ngspice_get_value.sym} 1220 -360 0 0 {name=r4 node="v(@M.X3.X1.XM2.msky130_fd_pr__pfet_01v8_lvt[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 1220 -330 0 0 {name=r5 node="v(@M.X3.X1.XM2.msky130_fd_pr__pfet_01v8_lvt[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 1150 -360 0 0 {name=r12 node="i(@M.X3.X1.XM2.msky130_fd_pr__pfet_01v8_lvt[id])"
+descr="id="}
+C {ngspice_get_value.sym} 1150 -300 0 0 {name=r36 node="v(@M.X3.X1.XM2.msky130_fd_pr__pfet_01v8_lvt[vth])"
+descr="vth="}
+C {ngspice_get_value.sym} 1150 -330 0 0 {name=r37 node="@M.X3.X1.XM2.msky130_fd_pr__pfet_01v8_lvt[gm]"
+descr="gm="}
+C {ngspice_get_value.sym} 1220 -300 0 0 {name=r38 node="@M.X3.X1.XM2.msky130_fd_pr__pfet_01v8_lvt[gds]"
+descr="gds="}
+C {ngspice_get_value.sym} 640 -110 0 0 {name=r39 node="v(@M.X3.X1.XM8.msky130_fd_pr__nfet_01v8_lvt[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 640 -80 0 0 {name=r40 node="v(@M.X3.X1.XM8.msky130_fd_pr__nfet_01v8_lvt[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 690 -110 0 0 {name=r41 node="v(@M.X3.X1.XM8.msky130_fd_pr__nfet_01v8_lvt[vdsat])"
+descr="vdsat="}
+C {ngspice_get_value.sym} 690 -80 0 0 {name=r42 node="i(@M.X3.X1.XM8.msky130_fd_pr__nfet_01v8_lvt[id])"
+descr="id="}
+C {ngspice_get_value.sym} 640 -40 0 0 {name=r43 node="@M.X3.X1.XM8.msky130_fd_pr__nfet_01v8_lvt[gds]"
+descr="gds="}
+C {sky130_fd_pr/pfet_01v8.sym} 930 -430 0 0 {name=M3
+L=0.15
+W=1
+nf=1
+mult=5
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 770 -290 0 0 {name=M1
+L=0.15
+W=1
+nf=1
+mult=20
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1130 -290 0 1 {name=M2
+L=0.15
+W=1
+nf=1
+mult=20
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 950 -480 0 0 {name=l2 sig_type=std_logic lab=int}
diff --git a/xschem/res_amp_lin.sym b/xschem/res_amp_lin.sym
new file mode 100644
index 0000000..a5a190d
--- /dev/null
+++ b/xschem/res_amp_lin.sym
@@ -0,0 +1,38 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -10 -180 10 -180 {}
+L 4 -10 -160 10 -160 {}
+L 4 -90 -160 -70 -160 {}
+L 4 -90 -180 -70 -180 {}
+L 4 -90 -140 -70 -140 {}
+L 4 -70 -210 -70 -130 {}
+L 4 -70 -130 10 -170 {}
+L 4 -70 -210 10 -170 {}
+L 4 -90 -200 -70 -200 {}
+L 7 -40 -220 -40 -200 {}
+L 7 -40 -140 -40 -120 {}
+B 5 -42.5 -222.5 -37.5 -217.5 {name=avdd1p8 dir=inout }
+B 5 -92.5 -142.5 -87.5 -137.5 {name=clk dir=in }
+B 5 -92.5 -182.5 -87.5 -177.5 {name=inp dir=in }
+B 5 -92.5 -162.5 -87.5 -157.5 {name=inn dir=in }
+B 5 7.5 -162.5 12.5 -157.5 {name=outp dir=out }
+B 5 7.5 -182.5 12.5 -177.5 {name=outn dir=out }
+B 5 -42.5 -122.5 -37.5 -117.5 {name=avss1p8 dir=inout }
+B 5 -92.5 -202.5 -87.5 -197.5 {name=vctrl dir=in }
+T {@symname} -19 -216 0 0 0.3 0.3 {}
+T {@name} -65 -172 0 0 0.2 0.2 {}
+T {avdd1p8} -5 -244 0 1 0.2 0.2 {}
+T {clk} -115 -144 0 0 0.2 0.2 {}
+T {inp} -115 -184 0 0 0.2 0.2 {}
+T {inn} -115 -164 0 0 0.2 0.2 {}
+T {outp} 45 -164 0 1 0.2 0.2 {}
+T {outn} 45 -184 0 1 0.2 0.2 {}
+T {avss1p8} -5 -114 0 1 0.2 0.2 {}
+T {vctrl} -115 -204 0 0 0.2 0.2 {}
diff --git a/xschem/res_amp_lin_prog.sch b/xschem/res_amp_lin_prog.sch
new file mode 100644
index 0000000..84a4843
--- /dev/null
+++ b/xschem/res_amp_lin_prog.sch
@@ -0,0 +1,230 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 2550 -430 2600 -430 { lab=clk}
+N 2730 -510 2730 -480 { lab=avdd1p8}
+N 2680 -510 2730 -510 { lab=avdd1p8}
+N 2730 -380 2730 -360 { lab=avss1p8}
+N 2680 -360 2730 -360 { lab=avss1p8}
+N 2770 -390 2770 -320 { lab=delay_reg0}
+N 2780 -390 2780 -320 { lab=delay_reg1}
+N 2830 -430 2920 -430 { lab=clk_out}
+N 2790 -390 2790 -320 { lab=delay_reg2}
+N 3020 -780 3090 -780 { lab=clk_out}
+N 3020 -800 3090 -800 { lab=inn}
+N 3020 -820 3090 -820 { lab=inp}
+N 3200 -800 3270 -800 { lab=outp}
+N 3200 -820 3270 -820 { lab=outn}
+N 3140 -910 3140 -860 { lab=avdd1p8}
+N 3140 -760 3140 -710 { lab=avss1p8}
+N 3670 -670 3670 -650 { lab=outn_cap}
+N 3710 -700 3730 -700 { lab=clk_out_b}
+N 3730 -700 3730 -650 { lab=clk_out_b}
+N 3640 -650 3640 -610 { lab=outn_cap}
+N 3860 -630 3860 -580 { lab=outn_cap}
+N 3860 -520 3860 -470 { lab=avss1p8}
+N 3810 -550 3860 -550 { lab=avss1p8}
+N 3190 -820 3200 -820 { lab=outn}
+N 3190 -800 3200 -800 { lab=outp}
+N 3020 -840 3090 -840 { lab=vctrl}
+N 3610 -760 3610 -730 { lab=outn}
+N 3640 -770 3640 -760 { lab=outn}
+N 3270 -820 3590 -820 { lab=outn}
+N 3610 -670 3610 -650 { lab=outn_cap}
+N 3610 -650 3670 -650 { lab=outn_cap}
+N 3550 -700 3570 -700 { lab=clk_out}
+N 3550 -700 3550 -660 { lab=clk_out}
+N 3670 -760 3670 -730 { lab=outn}
+N 3610 -760 3670 -760 { lab=outn}
+N 3660 -700 3670 -700 { lab=avss1p8}
+N 3610 -700 3620 -700 { lab=avdd1p8}
+N 3660 -730 3660 -700 { lab=avss1p8}
+N 3620 -700 3620 -670 { lab=avdd1p8}
+N 3400 -680 3400 -660 { lab=outp_cap}
+N 3440 -710 3460 -710 { lab=clk_out_b}
+N 3460 -710 3460 -660 { lab=clk_out_b}
+N 3340 -770 3340 -740 { lab=outp}
+N 3370 -780 3370 -770 { lab=outp}
+N 3340 -680 3340 -660 { lab=outp_cap}
+N 3340 -660 3400 -660 { lab=outp_cap}
+N 3280 -710 3300 -710 { lab=clk_out}
+N 3280 -710 3280 -670 { lab=clk_out}
+N 3400 -770 3400 -740 { lab=outp}
+N 3340 -770 3400 -770 { lab=outp}
+N 3390 -710 3400 -710 { lab=avss1p8}
+N 3340 -710 3350 -710 { lab=avdd1p8}
+N 3390 -740 3390 -710 { lab=avss1p8}
+N 3350 -710 3350 -680 { lab=avdd1p8}
+N 3370 -660 3370 -620 { lab=outp_cap}
+N 2920 -430 2970 -430 { lab=clk_out}
+N 3010 -510 3010 -480 { lab=avdd1p8}
+N 2960 -510 3010 -510 { lab=avdd1p8}
+N 3010 -380 3010 -360 { lab=avss1p8}
+N 2960 -360 3010 -360 { lab=avss1p8}
+N 3100 -430 3170 -430 { lab=clk_out_b}
+N 3900 -550 3960 -550 { lab=rst}
+N 2600 -430 2650 -430 { lab=clk}
+N 2650 -430 2690 -430 { lab=clk}
+N 4060 -630 4060 -580 { lab=outp_cap}
+N 4060 -520 4060 -470 { lab=avss1p8}
+N 4060 -550 4110 -550 { lab=avss1p8}
+N 3960 -550 4020 -550 { lab=rst}
+N 2740 -950 2740 -900 { lab=avdd1p8}
+N 2710 -780 2710 -730 { lab=avss1p8}
+N 2810 -840 3020 -840 { lab=vctrl}
+N 2550 -870 2670 -870 { lab=iref}
+N 2740 -780 2740 -730 { lab=iref_reg0}
+N 2750 -780 2750 -730 { lab=iref_reg1}
+N 2760 -780 2760 -730 { lab=iref_reg2}
+N 3640 -790 3640 -770 { lab=outn}
+N 3640 -820 3640 -790 { lab=outn}
+N 3590 -820 3640 -820 { lab=outn}
+N 3270 -800 3370 -800 { lab=outp}
+N 3370 -800 3370 -780 { lab=outp}
+N 3370 -620 3370 -590 { lab=outp_cap}
+N 3640 -610 3640 -580 { lab=outn_cap}
+N 3730 -850 3780 -850 { lab=outn}
+N 3730 -830 3780 -830 { lab=outp}
+N 3730 -810 3780 -810 { lab=outn_cap}
+N 3730 -790 3780 -790 { lab=outp_cap}
+N 3970 -550 3970 -500 { lab=rst}
+C {ipin.sym} 2550 -430 0 0 {name=p4 lab=clk}
+C {opin.sym} 3780 -830 0 0 {name=p7 lab=outp}
+C {opin.sym} 3780 -850 0 0 {name=p8 lab=outn}
+C {iopin.sym} 3140 -910 0 0 {name=p15 lab=avdd1p8}
+C {iopin.sym} 3140 -710 2 0 {name=p16 lab=avss1p8}
+C {delay_cell_buff.sym} 2780 -260 0 0 {name=x3}
+C {lab_wire.sym} 2710 -510 0 0 {name=l4 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 2710 -360 0 0 {name=l9 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 2900 -430 2 0 {name=l14 sig_type=std_logic lab=clk_out}
+C {lab_wire.sym} 3020 -780 2 0 {name=l27 sig_type=std_logic lab=clk_out}
+C {lab_wire.sym} 3370 -800 2 0 {name=l28 sig_type=std_logic lab=outp}
+C {lab_wire.sym} 3430 -820 2 0 {name=l29 sig_type=std_logic lab=outn}
+C {ngspice_probe.sym} 3320 -800 0 0 {name=r2}
+C {ngspice_probe.sym} 3230 -800 0 0 {name=r3}
+C {ngspice_probe.sym} 3040 -780 0 0 {name=r5}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 3880 -550 0 1 {name=M3
+L=0.15
+W=1
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_wire.sym} 3860 -600 3 1 {name=l34 sig_type=std_logic lab=outn_cap}
+C {lab_wire.sym} 3860 -500 1 1 {name=l35 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 3820 -550 1 1 {name=l37 sig_type=std_logic lab=avss1p8}
+C {ngspice_probe.sym} 3040 -840 0 0 {name=r10}
+C {res_amp_lin.sym} 3180 -640 0 0 {name=x4}
+C {lab_wire.sym} 2950 -840 0 0 {name=l36 sig_type=std_logic lab=vctrl}
+C {lab_wire.sym} 3620 -680 1 0 {name=l39 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 3660 -720 3 0 {name=l47 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 3370 -630 2 0 {name=l48 sig_type=std_logic lab=outp_cap}
+C {lab_wire.sym} 3350 -690 1 0 {name=l50 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 3390 -730 3 0 {name=l51 sig_type=std_logic lab=avss1p8}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 3420 -710 0 1 {name=M1
+L=0.15
+W=1
+nf=1
+mult=5
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 3690 -700 0 1 {name=M2
+L=0.15
+W=1
+nf=1
+mult=5
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 3320 -710 0 0 {name=M5
+L=0.35
+W=1
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 3590 -700 0 0 {name=M6
+L=0.35
+W=1
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_wire.sym} 3640 -620 2 0 {name=l42 sig_type=std_logic lab=outn_cap}
+C {inverter_min_x4.sym} 3030 -430 0 0 {name=x5}
+C {lab_wire.sym} 2990 -510 0 0 {name=l15 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 2990 -360 0 0 {name=l32 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 3140 -430 2 0 {name=l33 sig_type=std_logic lab=clk_out_b}
+C {lab_wire.sym} 3280 -680 0 0 {name=l38 sig_type=std_logic lab=clk_out}
+C {lab_wire.sym} 3460 -680 2 0 {name=l40 sig_type=std_logic lab=clk_out_b}
+C {lab_wire.sym} 3550 -690 0 0 {name=l44 sig_type=std_logic lab=clk_out}
+C {lab_wire.sym} 3730 -680 2 0 {name=l45 sig_type=std_logic lab=clk_out_b}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 4040 -550 0 0 {name=M4
+L=0.15
+W=1
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_wire.sym} 4060 -600 1 0 {name=l61 sig_type=std_logic lab=outp_cap}
+C {lab_wire.sym} 4060 -500 3 0 {name=l62 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 4100 -550 3 0 {name=l63 sig_type=std_logic lab=avss1p8}
+C {iref_ctrl_res_amp.sym} 2760 -670 0 0 {name=x7}
+C {lab_wire.sym} 2740 -930 0 0 {name=l1 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 2710 -740 0 0 {name=l2 sig_type=std_logic lab=avss1p8}
+C {ipin.sym} 2550 -870 0 0 {name=p1 lab=iref}
+C {ipin.sym} 3020 -820 0 0 {name=p5 lab=inp}
+C {ipin.sym} 3020 -800 0 0 {name=p6 lab=inn}
+C {ipin.sym} 2740 -730 3 0 {name=p2 lab=iref_reg0}
+C {ipin.sym} 2750 -730 3 0 {name=p3 lab=iref_reg1}
+C {ipin.sym} 2760 -730 3 0 {name=p9 lab=iref_reg2}
+C {opin.sym} 3780 -790 0 0 {name=p10 lab=outp_cap}
+C {opin.sym} 3780 -810 0 0 {name=p11 lab=outn_cap}
+C {ipin.sym} 2770 -320 3 0 {name=p12 lab=delay_reg0}
+C {ipin.sym} 2780 -320 3 0 {name=p13 lab=delay_reg1}
+C {ipin.sym} 2790 -320 3 0 {name=p14 lab=delay_reg2}
+C {ipin.sym} 3970 -500 3 0 {name=p17 lab=rst}
diff --git a/xschem/res_amp_lin_prog.sym b/xschem/res_amp_lin_prog.sym
new file mode 100644
index 0000000..bcaeb60
--- /dev/null
+++ b/xschem/res_amp_lin_prog.sym
@@ -0,0 +1,94 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 100 -200 120 -200 {}
+L 4 100 -180 120 -180 {}
+L 4 -170 -160 -150 -160 {}
+L 4 -170 -180 -150 -180 {}
+L 4 -170 -220 -150 -220 {}
+L 4 -70 -210 -70 -130 {}
+L 4 -70 -130 10 -170 {}
+L 4 -70 -210 10 -170 {}
+L 4 100 -180 120 -180 {}
+L 4 -150 -250 -150 -90 {}
+L 4 100 -250 100 -90 {}
+L 4 -50 -250 -50 -200 {}
+L 4 -50 -140 -50 -90 {}
+L 4 100 -150 120 -150 {}
+L 4 100 -130 120 -130 {}
+L 4 100 -130 120 -130 {}
+L 4 30 -130 30 -120 {}
+L 4 20 -120 40 -120 {}
+L 4 20 -110 40 -110 {}
+L 4 60 -130 60 -120 {}
+L 4 50 -120 70 -120 {}
+L 4 50 -110 70 -110 {}
+L 4 -150 -250 100 -250 {}
+L 4 -150 -90 100 -90 {}
+L 4 -150 -180 -70 -180 {}
+L 4 -150 -160 -70 -160 {}
+L 4 -170 -240 -150 -240 {}
+L 4 -130 -90 -130 -70 {}
+L 4 -140 -90 -140 -70 {}
+L 4 -110 -90 -110 -70 {}
+L 4 -120 -90 -120 -70 {}
+L 4 -90 -90 -90 -70 {}
+L 4 -100 -90 -100 -70 {}
+L 4 -170 -110 -150 -110 {}
+L 4 -50 -100 60 -100 {}
+L 4 30 -110 30 -100 {}
+L 4 60 -110 60 -100 {}
+L 4 -0 -180 10 -180 {}
+L 4 10 -180 20 -190 {}
+L 4 0 -160 10 -160 {}
+L 4 10 -160 20 -170 {}
+L 4 20 -160 30 -160 {}
+L 4 30 -160 30 -130 {}
+L 4 20 -180 60 -180 {}
+L 4 60 -180 60 -130 {}
+L 4 30 -150 100 -150 {}
+L 4 60 -130 100 -130 {}
+L 7 -50 -270 -50 -250 {}
+L 7 -50 -90 -50 -70 {}
+B 5 -52.5 -272.5 -47.5 -267.5 {name=avdd1p8 dir=inout }
+B 5 -172.5 -222.5 -167.5 -217.5 {name=rst dir=in }
+B 5 -172.5 -182.5 -167.5 -177.5 {name=inp dir=in }
+B 5 -172.5 -162.5 -167.5 -157.5 {name=inn dir=in }
+B 5 117.5 -182.5 122.5 -177.5 {name=outp dir=out }
+B 5 117.5 -202.5 122.5 -197.5 {name=outn dir=out }
+B 5 -52.5 -72.5 -47.5 -67.5 {name=avss1p8 dir=inout }
+B 5 117.5 -132.5 122.5 -127.5 {name=outp_cap dir=out }
+B 5 117.5 -152.5 122.5 -147.5 {name=outn_cap dir=out }
+B 5 -172.5 -242.5 -167.5 -237.5 {name=clk dir=in }
+B 5 -142.5 -72.5 -137.5 -67.5 {name=iref_reg0 dir=in }
+B 5 -132.5 -72.5 -127.5 -67.5 {name=iref_reg1 dir=in }
+B 5 -122.5 -72.5 -117.5 -67.5 {name=iref_reg2 dir=in }
+B 5 -112.5 -72.5 -107.5 -67.5 {name=delay_reg0 dir=in }
+B 5 -92.5 -72.5 -87.5 -67.5 {name=delay_reg2 dir=in }
+B 5 -102.5 -72.5 -97.5 -67.5 {name=delay_reg1 dir=in }
+B 5 -172.5 -112.5 -167.5 -107.5 {name=iref dir=in }
+T {@symname} 0 -240 0 0 0.3 0.3 {}
+T {@name} -60 -170 0 0 0.2 0.2 {}
+T {avdd1p8} 0 -270 0 1 0.2 0.2 {}
+T {rst} -190 -230 0 0 0.2 0.2 {}
+T {inp} -190 -180 0 0 0.2 0.2 {}
+T {inn} -190 -160 0 0 0.2 0.2 {}
+T {outp} 150 -180 0 1 0.2 0.2 {}
+T {outn} 150 -200 0 1 0.2 0.2 {}
+T {avss1p8} 0 -80 0 1 0.2 0.2 {}
+T {outp_cap} 170 -130 0 1 0.2 0.2 {}
+T {outn_cap} 170 -150 0 1 0.2 0.2 {}
+T {clk} -190 -250 0 0 0.2 0.2 {}
+T {iref_reg0} -140 -20 3 0 0.2 0.2 {}
+T {iref_reg1} -130 -20 3 0 0.2 0.2 {}
+T {iref_reg2} -120 -20 3 0 0.2 0.2 {}
+T {delay_reg0} -110 -10 3 0 0.2 0.2 {}
+T {delay_reg1} -100 -10 3 0 0.2 0.2 {}
+T {delay_reg2} -90 -10 3 0 0.2 0.2 {}
+T {iref} -190 -110 0 0 0.2 0.2 {}
diff --git a/xschem/res_amp_sync_v2.sch b/xschem/res_amp_sync_v2.sch
new file mode 100644
index 0000000..867d063
--- /dev/null
+++ b/xschem/res_amp_sync_v2.sch
@@ -0,0 +1,164 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 220 160 340 160 { lab=clkp}
+N 220 160 340 160 { lab=clkp}
+N 220 200 340 200 { lab=clkn}
+N 220 200 340 200 { lab=clkn}
+N 410 10 410 80 { lab=avdd1p8}
+N 410 240 410 310 { lab=avss1p8}
+N 410 -220 410 -190 { lab=avdd1p8}
+N 410 -220 430 -220 { lab=avdd1p8}
+N 410 -70 410 -40 { lab=avss1p8}
+N 390 -40 410 -40 { lab=avss1p8}
+N 480 120 540 120 { lab=q1}
+N 540 -120 540 120 { lab=q1}
+N 290 -120 290 120 { lab=d1}
+N 290 120 340 120 { lab=d1}
+N 580 200 700 200 { lab=q1}
+N 580 200 700 200 { lab=q1}
+N 770 10 770 80 { lab=avdd1p8}
+N 770 240 770 310 { lab=avss1p8}
+N 840 120 900 120 { lab=q2}
+N 900 -120 900 120 { lab=q2}
+N 650 -120 650 120 { lab=d2}
+N 650 120 700 120 { lab=d2}
+N 580 160 700 160 { lab=d1}
+N -290 550 -290 620 { lab=avdd1p8}
+N -290 780 -290 850 { lab=avss1p8}
+N -20 420 -20 490 { lab=avdd1p8}
+N -150 570 -90 570 { lab=clkp}
+N -150 610 -90 610 { lab=clkn}
+N -420 700 -360 700 { lab=clkp}
+N -420 740 -360 740 { lab=clkn}
+N -420 660 -360 660 { lab=d1}
+N -150 530 -90 530 { lab=q2}
+N 50 530 210 530 { lab=#net1}
+N -220 660 -100 660 { lab=#net2}
+N -100 660 -100 720 { lab=#net2}
+N -100 720 210 720 { lab=#net2}
+N 210 640 210 720 { lab=#net2}
+N 210 640 240 640 { lab=#net2}
+N 210 600 240 600 { lab=#net1}
+N 210 530 210 600 { lab=#net1}
+N 280 500 280 570 { lab=avdd1p8}
+N 280 670 280 740 { lab=avss1p8}
+N 350 620 410 620 { lab=#net3}
+N 450 500 450 570 { lab=avdd1p8}
+N 450 670 450 740 { lab=avss1p8}
+N 600 620 680 620 { lab=pulse}
+N 940 510 940 580 { lab=avdd1p8}
+N 940 740 940 810 { lab=avss1p8}
+N 810 660 870 660 { lab=clkp}
+N 810 700 870 700 { lab=clkn}
+N 810 620 870 620 { lab=pulse}
+N 680 620 810 620 { lab=pulse}
+N 1010 620 1110 620 { lab=#net4}
+N 1510 620 1590 620 { lab=clk_amp}
+N 1150 500 1150 570 { lab=avdd1p8}
+N 1150 670 1150 740 { lab=avss1p8}
+N 1420 500 1420 570 { lab=avdd1p8}
+N 1420 670 1420 740 { lab=avss1p8}
+N 1240 620 1290 620 { lab=#net5}
+N 1110 850 1110 920 { lab=avdd1p8}
+N 1110 1020 1110 1090 { lab=avss1p8}
+N 940 850 940 920 { lab=avdd1p8}
+N 940 1020 940 1090 { lab=avss1p8}
+N 1010 970 1070 970 { lab=#net6}
+N 1200 970 1360 970 { lab=rst}
+N 810 950 900 950 { lab=pulse}
+N 810 990 900 990 { lab=clkp}
+N -220 740 -200 740 { lab=#net7}
+N 50 610 70 610 { lab=#net8}
+N 480 200 500 200 { lab=#net9}
+N 840 200 860 200 { lab=#net10}
+N 1010 700 1030 700 { lab=#net11}
+N -20 650 -20 680 { lab=avss1p8}
+N 450 -130 540 -130 { lab=q1}
+N 540 -130 540 -120 { lab=q1}
+N 290 -130 290 -120 { lab=d1}
+N 320 -130 340 -130 { lab=d1}
+N 410 -190 410 -180 { lab=avdd1p8}
+N 410 -80 410 -70 { lab=avss1p8}
+N 540 620 600 620 { lab=pulse}
+N 290 -130 320 -130 { lab=d1}
+N 770 -220 770 -190 { lab=avdd1p8}
+N 770 -220 790 -220 { lab=avdd1p8}
+N 770 -70 770 -40 { lab=avss1p8}
+N 750 -40 770 -40 { lab=avss1p8}
+N 810 -130 900 -130 { lab=q2}
+N 900 -130 900 -120 { lab=q2}
+N 650 -130 650 -120 { lab=d2}
+N 680 -130 700 -130 { lab=d2}
+N 770 -190 770 -180 { lab=avdd1p8}
+N 770 -80 770 -70 { lab=avss1p8}
+N 650 -130 680 -130 { lab=d2}
+N 1290 620 1380 620 { lab=#net5}
+C {ipin.sym} 220 200 0 0 {name=p3 lab=clkn}
+C {ipin.sym} 220 160 0 0 {name=p4 lab=clkp}
+C {iopin.sym} 410 10 0 0 {name=p1 lab=avdd1p8}
+C {iopin.sym} 410 310 0 0 {name=p8 lab=avss1p8}
+C {lab_wire.sym} 420 -220 0 0 {name=l1 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 400 -40 2 0 {name=l2 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 770 40 0 0 {name=l7 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 770 290 2 0 {name=l8 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 290 -10 2 0 {name=l11 sig_type=std_logic lab=d1}
+C {lab_wire.sym} 540 0 2 0 {name=l12 sig_type=std_logic lab=q1}
+C {lab_wire.sym} 640 200 2 0 {name=l13 sig_type=std_logic lab=q1}
+C {lab_wire.sym} 640 160 2 0 {name=l14 sig_type=std_logic lab=d1}
+C {lab_wire.sym} 650 -10 2 0 {name=l17 sig_type=std_logic lab=d2}
+C {lab_wire.sym} 900 0 2 0 {name=l18 sig_type=std_logic lab=q2}
+C {lab_wire.sym} -290 570 0 0 {name=l19 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} -290 830 2 0 {name=l20 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} -20 440 0 0 {name=l21 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} -20 680 2 0 {name=l22 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} -140 570 2 0 {name=l23 sig_type=std_logic lab=clkp}
+C {lab_wire.sym} -140 610 2 0 {name=l24 sig_type=std_logic lab=clkn}
+C {lab_wire.sym} -410 700 2 0 {name=l25 sig_type=std_logic lab=clkp}
+C {lab_wire.sym} -410 740 2 0 {name=l26 sig_type=std_logic lab=clkn}
+C {lab_wire.sym} -400 660 2 0 {name=l27 sig_type=std_logic lab=d1}
+C {lab_wire.sym} -130 530 2 0 {name=l28 sig_type=std_logic lab=q2}
+C {nand_logic.sym} 290 720 0 0 {name=x4}
+C {lab_wire.sym} 280 520 0 0 {name=l29 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 280 720 2 0 {name=l30 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 450 520 0 0 {name=l33 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 450 720 2 0 {name=l34 sig_type=std_logic lab=avss1p8}
+C {inverter_min_x4.sym} 390 -130 0 1 {name=x1}
+C {inverter_min_x4.sym} 470 620 0 0 {name=x5}
+C {lab_wire.sym} 940 530 0 0 {name=l52 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 940 790 2 0 {name=l53 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 820 660 2 0 {name=l54 sig_type=std_logic lab=clkp}
+C {lab_wire.sym} 820 700 2 0 {name=l55 sig_type=std_logic lab=clkn}
+C {lab_wire.sym} 770 620 0 0 {name=l56 sig_type=std_logic lab=pulse}
+C {lab_wire.sym} 1150 520 0 0 {name=l61 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 1150 720 2 0 {name=l62 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 1420 520 2 0 {name=l63 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 1420 720 2 0 {name=l64 sig_type=std_logic lab=avss1p8}
+C {nand_logic.sym} 950 1070 0 0 {name=x21}
+C {lab_wire.sym} 1110 870 0 0 {name=l65 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 1110 1070 2 0 {name=l66 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 940 870 0 0 {name=l67 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 940 1070 2 0 {name=l68 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 820 950 0 0 {name=l69 sig_type=std_logic lab=pulse}
+C {lab_wire.sym} 820 990 0 0 {name=l70 sig_type=std_logic lab=clkp}
+C {opin.sym} 1360 970 0 0 {name=p6 lab=rst}
+C {opin.sym} 1590 620 0 0 {name=p5 lab=clk_amp}
+C {DFlipFlop.sym} -290 700 0 0 {name=x3}
+C {noconn.sym} -200 740 2 0 {name=l5}
+C {DFlipFlop.sym} -20 570 0 0 {name=x6}
+C {noconn.sym} 70 610 2 0 {name=l6}
+C {DFlipFlop.sym} 410 160 0 0 {name=x7}
+C {noconn.sym} 500 200 2 0 {name=l9}
+C {DFlipFlop.sym} 770 160 0 0 {name=x8}
+C {noconn.sym} 860 200 2 0 {name=l10}
+C {DFlipFlop.sym} 940 660 0 0 {name=x9}
+C {noconn.sym} 1030 700 2 0 {name=l15}
+C {lab_wire.sym} 780 -220 0 0 {name=l3 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 760 -40 2 0 {name=l4 sig_type=std_logic lab=avss1p8}
+C {inverter_min_x4.sym} 750 -130 0 1 {name=x2}
+C {inverter_min_x4.sym} 1130 970 0 0 {name=x10}
+C {inverter_min_x4.sym} 1170 620 0 0 {name=x11}
+C {inverter_min_x16.sym} 1440 620 0 0 {name=x12}
diff --git a/xschem/res_amp_sync_v2.sym b/xschem/res_amp_sync_v2.sym
new file mode 100644
index 0000000..4d3a008
--- /dev/null
+++ b/xschem/res_amp_sync_v2.sym
@@ -0,0 +1,37 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 30 130 30 {}
+L 4 -130 -30 -130 30 {}
+L 4 130 -30 130 30 {}
+L 4 -150 -30 -130 -30 {}
+L 4 -150 0 -130 0 {}
+L 4 130 -40 150 -40 {}
+L 4 -130 -50 -130 -30 {}
+L 4 -130 -60 130 -60 {}
+L 4 130 -50 130 -30 {}
+L 4 -130 -60 -130 -50 {}
+L 4 130 -60 130 -50 {}
+L 4 130 0 150 0 {}
+L 7 0 -80 0 -60 {}
+L 7 0 30 0 50 {}
+B 5 -2.5 -82.5 2.5 -77.5 {name=avdd1p8 dir=inout }
+B 5 -152.5 -32.5 -147.5 -27.5 {name=clkp dir=in }
+B 5 -152.5 -2.5 -147.5 2.5 {name=clkn dir=in }
+B 5 -2.5 47.5 2.5 52.5 {name=avss1p8 dir=inout }
+B 5 147.5 -42.5 152.5 -37.5 {name=clk_amp dir=out }
+B 5 147.5 -2.5 152.5 2.5 {name=rst dir=out }
+T {@symname} 46 -86 0 0 0.3 0.3 {}
+T {@name} -15 -22 0 0 0.2 0.2 {}
+T {avdd1p8} 16 -55 0 1 0.2 0.2 {}
+T {clkp} -125 -34 0 0 0.2 0.2 {}
+T {clkn} -125 -4 0 0 0.2 0.2 {}
+T {avss1p8} -26 25 2 1 0.2 0.2 {}
+T {clk_amp} 125 -44 0 1 0.2 0.2 {}
+T {rst} 125 -4 0 1 0.2 0.2 {}
diff --git a/xschem/res_amp_top.sch b/xschem/res_amp_top.sch
new file mode 100644
index 0000000..afc412a
--- /dev/null
+++ b/xschem/res_amp_top.sch
@@ -0,0 +1,87 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 600 70 600 150 { lab=iref_reg0}
+N 610 70 610 150 { lab=iref_reg1}
+N 620 70 620 150 { lab=iref_reg2}
+N 630 70 630 150 { lab=delay_reg0}
+N 640 70 640 150 { lab=delay_reg1}
+N 650 70 650 150 { lab=delay_reg2}
+N 500 -40 570 -40 { lab=inp}
+N 500 -20 570 -20 { lab=inn}
+N 500 -100 570 -100 { lab=clk_amp}
+N 500 -80 570 -80 { lab=rst}
+N 860 -60 940 -60 { lab=outn_amp}
+N 860 -40 940 -40 { lab=outp_amp}
+N 860 -10 940 -10 { lab=outn_cap}
+N 860 10 940 10 { lab=outp_cap}
+N 690 -180 690 -130 { lab=avdd1p8}
+N 690 70 690 120 { lab=avss1p8}
+N 500 30 570 30 { lab=iref0}
+N 1440 -20 1530 -20 { lab=outp}
+N 1440 90 1530 90 { lab=outn}
+N 1310 -160 1310 -110 { lab=avdd1p8}
+N 1310 180 1310 230 { lab=avss1p8}
+N 1070 90 1150 90 { lab=outn_cap}
+N 1070 -20 1150 -20 { lab=outp_cap}
+N 240 80 240 130 { lab=avdd1p8}
+N 240 260 240 310 { lab=avss1p8}
+N 30 180 90 180 { lab=clkp}
+N 30 210 90 210 { lab=clkn}
+N 390 170 440 170 { lab=clk_amp}
+N 390 210 440 210 { lab=rst}
+N 1200 180 1200 250 { lab=iref1}
+N 1220 180 1220 250 { lab=iref2}
+N 1240 180 1240 250 { lab=iref3}
+N 1260 180 1260 250 { lab=iref4}
+N 890 220 890 250 { lab=avss1p8}
+N 890 250 1000 250 { lab=avss1p8}
+N 1000 220 1000 250 { lab=avss1p8}
+N 890 110 890 160 { lab=outp_cap}
+N 1000 110 1000 160 { lab=outn_cap}
+C {res_amp_lin_prog.sym} 740 140 0 0 {name=x2}
+C {lab_wire.sym} 530 -80 0 0 {name=l31 sig_type=std_logic lab=rst}
+C {lab_wire.sym} 930 -60 0 0 {name=l32 sig_type=std_logic lab=outn_amp}
+C {lab_wire.sym} 930 -40 0 0 {name=l33 sig_type=std_logic lab=outp_amp}
+C {lab_wire.sym} 930 -10 0 0 {name=l34 sig_type=std_logic lab=outn_cap}
+C {lab_wire.sym} 930 10 0 0 {name=l35 sig_type=std_logic lab=outp_cap}
+C {res_amp_sync_v2.sym} 240 210 0 0 {name=x1}
+C {source_follower_buff_diff.sym} 1310 150 0 0 {name=x3}
+C {lab_wire.sym} 1310 -150 2 0 {name=l1 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 1310 210 2 0 {name=l2 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 1120 -20 0 0 {name=l3 sig_type=std_logic lab=outp_cap}
+C {lab_wire.sym} 1120 90 0 0 {name=l4 sig_type=std_logic lab=outn_cap}
+C {ipin.sym} 500 -40 0 0 {name=p12 lab=inp}
+C {ipin.sym} 500 -20 0 0 {name=p1 lab=inn}
+C {noconn.sym} 940 -60 2 0 {name=l5}
+C {noconn.sym} 940 -40 2 0 {name=l6}
+C {lab_wire.sym} 240 90 2 0 {name=l7 sig_type=std_logic lab=avdd1p8}
+C {lab_wire.sym} 240 290 2 0 {name=l8 sig_type=std_logic lab=avss1p8}
+C {ipin.sym} 30 180 0 0 {name=p2 lab=clkp}
+C {ipin.sym} 30 210 0 0 {name=p3 lab=clkn}
+C {lab_wire.sym} 430 170 0 0 {name=l9 sig_type=std_logic lab=clk_amp}
+C {lab_wire.sym} 540 -100 0 0 {name=l10 sig_type=std_logic lab=clk_amp}
+C {lab_wire.sym} 430 210 0 0 {name=l11 sig_type=std_logic lab=rst}
+C {iopin.sym} 690 -180 0 0 {name=p5 lab=avdd1p8}
+C {iopin.sym} 690 120 0 0 {name=p4 lab=avss1p8}
+C {ipin.sym} 500 30 0 0 {name=p14 lab=iref0}
+C {ipin.sym} 1200 250 3 0 {name=p6 lab=iref1}
+C {ipin.sym} 1220 250 3 0 {name=p7 lab=iref2}
+C {ipin.sym} 1240 250 3 0 {name=p8 lab=iref3}
+C {ipin.sym} 1260 250 3 0 {name=p9 lab=iref4}
+C {opin.sym} 1530 90 0 0 {name=p10 lab=outn}
+C {opin.sym} 1530 -20 0 0 {name=p11 lab=outp}
+C {ipin.sym} 600 150 3 0 {name=p13 lab=iref_reg0}
+C {ipin.sym} 610 150 3 0 {name=p15 lab=iref_reg1}
+C {ipin.sym} 620 150 3 0 {name=p16 lab=iref_reg2}
+C {ipin.sym} 630 150 3 0 {name=p17 lab=delay_reg0}
+C {ipin.sym} 640 150 3 0 {name=p18 lab=delay_reg1}
+C {ipin.sym} 650 150 3 0 {name=p19 lab=delay_reg2}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 890 190 0 0 {name=C1 model=cap_mim_m3_1 W=5.5 L=7.5 MF=1 spiceprefix=X}
+C {lab_wire.sym} 920 250 2 0 {name=l12 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 890 120 0 0 {name=l13 sig_type=std_logic lab=outp_cap}
+C {lab_wire.sym} 1000 130 0 0 {name=l14 sig_type=std_logic lab=outn_cap}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 1000 190 0 0 {name=C2 model=cap_mim_m3_1 W=5.5 L=7.5 MF=1 spiceprefix=X}
diff --git a/xschem/res_amp_top.sym b/xschem/res_amp_top.sym
new file mode 100644
index 0000000..f44918a
--- /dev/null
+++ b/xschem/res_amp_top.sym
@@ -0,0 +1,122 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 100 -180 120 -180 {}
+L 4 100 -160 120 -160 {}
+L 4 -170 -160 -150 -160 {}
+L 4 -170 -180 -150 -180 {}
+L 4 -70 -210 -70 -130 {}
+L 4 -70 -130 10 -170 {}
+L 4 -70 -210 10 -170 {}
+L 4 100 -160 120 -160 {}
+L 4 -150 -250 -150 -90 {}
+L 4 100 -250 100 -90 {}
+L 4 -50 -250 -50 -200 {}
+L 4 -50 -140 -50 -90 {}
+L 4 30 -130 30 -120 {}
+L 4 20 -120 40 -120 {}
+L 4 20 -110 40 -110 {}
+L 4 60 -130 60 -120 {}
+L 4 50 -120 70 -120 {}
+L 4 50 -110 70 -110 {}
+L 4 60 -160 60 -140 {}
+L 4 -150 -250 100 -250 {}
+L 4 -150 -60 100 -60 {}
+L 4 -150 -180 -70 -180 {}
+L 4 -150 -160 -70 -160 {}
+L 4 -170 -240 -150 -240 {}
+L 4 -130 -60 -130 -40 {}
+L 4 -140 -60 -140 -40 {}
+L 4 -110 -60 -110 -40 {}
+L 4 -120 -60 -120 -40 {}
+L 4 -90 -60 -90 -40 {}
+L 4 -100 -60 -100 -40 {}
+L 4 -170 -110 -150 -110 {}
+L 4 -50 -80 60 -80 {}
+L 4 30 -110 30 -100 {}
+L 4 60 -110 60 -100 {}
+L 4 -170 -220 -150 -220 {}
+L 4 30 -100 30 -80 {}
+L 4 60 -100 60 -80 {}
+L 4 -50 -90 -50 -80 {}
+L 4 -150 -90 -150 -60 {}
+L 4 100 -90 100 -60 {}
+L 4 0 -180 10 -180 {}
+L 4 10 -180 20 -190 {}
+L 4 20 -180 30 -180 {}
+L 4 30 -180 30 -130 {}
+L 4 -0 -160 10 -160 {}
+L 4 10 -160 20 -170 {}
+L 4 20 -160 60 -160 {}
+L 4 60 -140 60 -130 {}
+L 4 30 -180 60 -180 {}
+L 4 60 -190 60 -180 {}
+L 4 60 -190 70 -180 {}
+L 4 60 -170 70 -180 {}
+L 4 60 -180 60 -170 {}
+L 4 70 -190 80 -180 {}
+L 4 70 -170 80 -180 {}
+L 4 80 -180 100 -180 {}
+L 4 60 -160 70 -160 {}
+L 4 70 -170 70 -160 {}
+L 4 70 -170 80 -160 {}
+L 4 70 -150 80 -160 {}
+L 4 70 -160 70 -150 {}
+L 4 80 -170 90 -160 {}
+L 4 80 -150 90 -160 {}
+L 4 90 -160 100 -160 {}
+L 4 80 -170 80 -150 {}
+L 4 70 -190 70 -170 {}
+L 4 -170 -100 -150 -100 {}
+L 4 -170 -90 -150 -90 {}
+L 4 -170 -80 -150 -80 {}
+L 4 -170 -70 -150 -70 {}
+L 4 -10 -80 -10 -60 {}
+L 7 -50 -270 -50 -250 {}
+L 7 -10 -60 -10 -40 {}
+B 5 -52.5 -272.5 -47.5 -267.5 {name=avdd1p8 dir=inout }
+B 5 -172.5 -182.5 -167.5 -177.5 {name=inp dir=in }
+B 5 -172.5 -162.5 -167.5 -157.5 {name=inn dir=in }
+B 5 117.5 -162.5 122.5 -157.5 {name=outp dir=out }
+B 5 117.5 -182.5 122.5 -177.5 {name=outn dir=out }
+B 5 -12.5 -42.5 -7.5 -37.5 {name=avss1p8 dir=inout }
+B 5 -172.5 -242.5 -167.5 -237.5 {name=clkp dir=in }
+B 5 -142.5 -42.5 -137.5 -37.5 {name=iref_reg0 dir=in }
+B 5 -132.5 -42.5 -127.5 -37.5 {name=iref_reg1 dir=in }
+B 5 -122.5 -42.5 -117.5 -37.5 {name=iref_reg2 dir=in }
+B 5 -112.5 -42.5 -107.5 -37.5 {name=delay_reg0 dir=in }
+B 5 -92.5 -42.5 -87.5 -37.5 {name=delay_reg2 dir=in }
+B 5 -102.5 -42.5 -97.5 -37.5 {name=delay_reg1 dir=in }
+B 5 -172.5 -112.5 -167.5 -107.5 {name=iref0 dir=in }
+B 5 -172.5 -222.5 -167.5 -217.5 {name=clkn dir=in }
+B 5 -172.5 -102.5 -167.5 -97.5 {name=iref1 dir=in }
+B 5 -172.5 -92.5 -167.5 -87.5 {name=iref2 dir=in }
+B 5 -172.5 -82.5 -167.5 -77.5 {name=iref3 dir=in }
+B 5 -172.5 -72.5 -167.5 -67.5 {name=iref4 dir=in }
+T {@symname} 0 -240 0 0 0.3 0.3 {}
+T {@name} -60 -170 0 0 0.2 0.2 {}
+T {avdd1p8} 0 -270 0 1 0.2 0.2 {}
+T {inp} -190 -180 0 0 0.2 0.2 {}
+T {inn} -190 -160 0 0 0.2 0.2 {}
+T {outp} 150 -160 0 1 0.2 0.2 {}
+T {outn} 150 -180 0 1 0.2 0.2 {}
+T {avss1p8} 0 -50 0 1 0.2 0.2 {}
+T {clkp} -200 -250 0 0 0.2 0.2 {}
+T {iref_reg0} -140 10 3 0 0.2 0.2 {}
+T {iref_reg1} -130 10 3 0 0.2 0.2 {}
+T {iref_reg2} -120 10 3 0 0.2 0.2 {}
+T {delay_reg0} -110 20 3 0 0.2 0.2 {}
+T {delay_reg1} -100 20 3 0 0.2 0.2 {}
+T {delay_reg2} -90 20 3 0 0.2 0.2 {}
+T {iref0} -200 -120 0 0 0.2 0.2 {}
+T {clkn} -200 -230 0 0 0.2 0.2 {}
+T {iref1} -200 -110 0 0 0.2 0.2 {}
+T {iref2} -200 -100 0 0 0.2 0.2 {}
+T {iref3} -200 -90 0 0 0.2 0.2 {}
+T {iref4} -200 -80 0 0 0.2 0.2 {}
diff --git a/xschem/res_loop_filter.sch b/xschem/res_loop_filter.sch
new file mode 100644
index 0000000..58e7dc7
--- /dev/null
+++ b/xschem/res_loop_filter.sch
@@ -0,0 +1,19 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 360 -50 400 -50 { lab=vss}
+N 420 -110 420 -80 { lab=in}
+N 420 -20 420 0 { lab=vc_pex}
+N 420 -0 420 30 {}
+C {iopin.sym} 420 -110 3 0 {name=p2 lab=in}
+C {iopin.sym} 360 -50 2 0 {name=p3 lab=vss}
+C {iopin.sym} 420 30 1 0 {name=p1 lab=out}
+C {sky130_fd_pr/res_high_po_1p41.sym} 420 -50 0 0 {name=R3
+W=5.73
+L=22.92
+model=res_high_po_5p73
+spiceprefix=X
+mult=1}
diff --git a/xschem/res_loop_filter.sym b/xschem/res_loop_filter.sym
new file mode 100644
index 0000000..851a092
--- /dev/null
+++ b/xschem/res_loop_filter.sym
@@ -0,0 +1,24 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -30 -20 -30 20 {}
+L 4 30 -20 30 20 {}
+L 4 -30 20 30 20 {}
+L 4 -30 -20 30 -20 {}
+L 7 0 -40 0 -20 {}
+L 7 0 20 0 40 {}
+L 7 -50 0 -30 0 {}
+B 5 -2.5 -42.5 2.5 -37.5 {name=in dir=inout }
+B 5 -2.5 37.5 2.5 42.5 {name=out dir=inout }
+B 5 -52.5 -2.5 -47.5 2.5 {name=vss dir=inout }
+T {@symname} 20 24 0 0 0.3 0.3 {}
+T {@name} 25 -32 0 0 0.2 0.2 {}
+T {in} -14 -45 3 1 0.2 0.2 {}
+T {out} -6 45 1 1 0.2 0.2 {}
+T {vss} -55 -6 2 1 0.2 0.2 {}
diff --git a/xschem/ring_osc_buffer.sch b/xschem/ring_osc_buffer.sch
new file mode 100644
index 0000000..18e1f4e
--- /dev/null
+++ b/xschem/ring_osc_buffer.sch
@@ -0,0 +1,35 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 780 -210 820 -210 { lab=o1}
+N 690 -290 690 -260 { lab=vdd}
+N 690 -160 690 -130 { lab=vss}
+N 990 -290 990 -260 { lab=vdd}
+N 990 -160 990 -130 { lab=vss}
+N 620 -210 650 -210 { lab=in_vco}
+N 820 -210 950 -210 { lab=o1}
+N 1080 -210 1210 -210 { lab=out_div}
+N 1320 -290 1320 -260 { lab=vdd}
+N 1320 -160 1320 -130 { lab=vss}
+N 1210 -210 1280 -210 { lab=out_div}
+N 1410 -210 1450 -210 { lab=out_pad}
+N 570 -210 620 -210 { lab=in_vco}
+N 1180 -210 1180 -140 { lab=out_div}
+N 880 -260 880 -210 { lab=o1}
+C {iopin.sym} 690 -290 3 0 {name=p16 sig_type=std_logic lab=vdd}
+C {iopin.sym} 690 -130 1 0 {name=p40 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 990 -290 1 0 {name=l48 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 990 -130 3 0 {name=l49 sig_type=std_logic lab=vss}
+C {ipin.sym} 570 -210 0 0 {name=p60 sig_type=std_logic lab=in_vco}
+C {lab_wire.sym} 810 -210 0 0 {name=l61 sig_type=std_logic lab=o1}
+C {lab_pin.sym} 1320 -290 1 0 {name=l74 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1320 -130 3 0 {name=l84 sig_type=std_logic lab=vss}
+C {opin.sym} 1450 -210 2 1 {name=p86 sig_type=std_logic lab=out_pad}
+C {inverter_min_x2.sym} 710 -210 0 0 {name=x1}
+C {inverter_min_x4.sym} 1010 -210 0 0 {name=x2}
+C {opin.sym} 1180 -140 3 1 {name=p1 sig_type=std_logic lab=out_div}
+C {iopin.sym} 880 -260 3 0 {name=p2 sig_type=std_logic lab=o1}
+C {inverter_min_x4.sym} 1340 -210 0 0 {name=x3}
diff --git a/xschem/ring_osc_buffer.sym b/xschem/ring_osc_buffer.sym
new file mode 100644
index 0000000..587bc9c
--- /dev/null
+++ b/xschem/ring_osc_buffer.sym
@@ -0,0 +1,43 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -40 -40 40 {}
+L 4 40 -40 40 40 {}
+L 4 -60 0 -40 0 {}
+L 4 40 -20 60 -20 {}
+L 4 40 20 60 20 {}
+L 4 -40 -50 40 -50 {}
+L 4 -40 50 40 50 {}
+L 4 -30 40 -30 50 {}
+L 4 -30 30 30 30 {}
+L 4 30 40 30 50 {}
+L 4 -30 30 -30 40 {}
+L 4 30 30 30 40 {}
+L 4 40 40 40 50 {}
+L 4 -40 40 -40 50 {}
+L 4 -40 -50 -40 -40 {}
+L 4 40 -50 40 -40 {}
+L 7 -20 -70 -20 -50 {}
+L 7 20 -70 20 -50 {}
+L 7 0 50 0 70 {}
+B 5 -22.5 -72.5 -17.5 -67.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in_vco sig_type=std_logic dir=in }
+B 5 57.5 -22.5 62.5 -17.5 {name=out_pad sig_type=std_logic dir=out }
+B 5 57.5 17.5 62.5 22.5 {name=out_div sig_type=std_logic dir=out }
+B 5 17.5 -72.5 22.5 -67.5 {name=vss sig_type=std_logic dir=inout }
+B 5 -2.5 67.5 2.5 72.5 {name=o1 sig_type=std_logic dir=inout }
+T {@symname} 44.5 54 0 0 0.3 0.3 {}
+T {@name} -15 -12 0 0 0.2 0.2 {}
+T {vdd} -34 -75 3 1 0.2 0.2 {}
+T {in_vco} -75 -14 0 0 0.2 0.2 {}
+T {out_pad} 85 -34 0 1 0.2 0.2 {}
+T {out_div} 85 6 0 1 0.2 0.2 {}
+T {vss} 6 -75 3 1 0.2 0.2 {}
+T {Debug} 15 36 0 1 0.2 0.2 {}
+T {o1} 14 75 1 1 0.2 0.2 {}
diff --git a/xschem/ring_osc_buffer_pex_c.sym b/xschem/ring_osc_buffer_pex_c.sym
new file mode 100644
index 0000000..6b44152
--- /dev/null
+++ b/xschem/ring_osc_buffer_pex_c.sym
@@ -0,0 +1,43 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -40 -40 40 {}
+L 4 40 -40 40 40 {}
+L 4 -60 0 -40 0 {}
+L 4 40 -20 60 -20 {}
+L 4 40 20 60 20 {}
+L 4 -40 -50 40 -50 {}
+L 4 -40 50 40 50 {}
+L 4 -30 40 -30 50 {}
+L 4 -30 30 30 30 {}
+L 4 30 40 30 50 {}
+L 4 -30 30 -30 40 {}
+L 4 30 30 30 40 {}
+L 4 40 40 40 50 {}
+L 4 -40 40 -40 50 {}
+L 4 -40 -50 -40 -40 {}
+L 4 40 -50 40 -40 {}
+L 7 -20 -70 -20 -50 {}
+L 7 20 -70 20 -50 {}
+L 7 0 50 0 70 {}
+B 5 -22.5 -72.5 -17.5 -67.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in_vco sig_type=std_logic dir=in }
+B 5 57.5 -22.5 62.5 -17.5 {name=out_pad sig_type=std_logic dir=out }
+B 5 57.5 17.5 62.5 22.5 {name=out_div sig_type=std_logic dir=out }
+B 5 17.5 -72.5 22.5 -67.5 {name=vss sig_type=std_logic dir=inout }
+B 5 -2.5 67.5 2.5 72.5 {name=o1 sig_type=std_logic dir=inout }
+T {@symname} 44.5 54 0 0 0.3 0.3 {}
+T {@name} -15 -12 0 0 0.2 0.2 {}
+T {vdd} -34 -75 3 1 0.2 0.2 {}
+T {in_vco} -75 -14 0 0 0.2 0.2 {}
+T {out_pad} 85 -34 0 1 0.2 0.2 {}
+T {out_div} 85 6 0 1 0.2 0.2 {}
+T {vss} 6 -75 3 1 0.2 0.2 {}
+T {Debug} 15 36 0 1 0.2 0.2 {}
+T {o1} 14 75 1 1 0.2 0.2 {}
diff --git a/xschem/simulations/.spiceinit b/xschem/simulations/.spiceinit
new file mode 100644
index 0000000..0c7a371
--- /dev/null
+++ b/xschem/simulations/.spiceinit
@@ -0,0 +1,5 @@
+set ngbehavior=hsa
+set ng_nomodcheck
+set numthreads=8
+set filetype=ascii
+set outputpath=~sky130-mpw2-fulgorring_osc
diff --git a/xschem/simulations/DFF.spice b/xschem/simulations/DFF.spice
new file mode 100644
index 0000000..2de16a7
--- /dev/null
+++ b/xschem/simulations/DFF.spice
@@ -0,0 +1,43 @@
+**.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+**.ends
+
+* expanding symbol: nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/DFlipFlop.spice b/xschem/simulations/DFlipFlop.spice
new file mode 100644
index 0000000..dfdb429
--- /dev/null
+++ b/xschem/simulations/DFlipFlop.spice
@@ -0,0 +1,93 @@
+**.subckt DFlipFlop vdd vss Q nQ D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+**.ends
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/PFD.spice b/xschem/simulations/PFD.spice
new file mode 100644
index 0000000..65e94d9
--- /dev/null
+++ b/xschem/simulations/PFD.spice
@@ -0,0 +1,96 @@
+**.subckt PFD vdd vss A B Down Up Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+**.ends
+
+* expanding symbol: DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding symbol: and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/PFD_pex_c.spice b/xschem/simulations/PFD_pex_c.spice
new file mode 100644
index 0000000..c9ccf62
--- /dev/null
+++ b/xschem/simulations/PFD_pex_c.spice
@@ -0,0 +1,251 @@
+* NGSPICE file created from PFD.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_159_n90# a_n129_n90# 0.06fF
+C1 a_159_n90# w_n359_n309# 0.09fF
+C2 a_159_n90# a_n33_n90# 0.09fF
+C3 a_159_n90# a_63_n90# 0.26fF
+C4 a_n63_n116# a_n159_n207# 0.12fF
+C5 a_n221_n90# a_159_n90# 0.04fF
+C6 a_n129_n90# w_n359_n309# 0.06fF
+C7 a_n129_n90# a_n33_n90# 0.26fF
+C8 a_n129_n90# a_63_n90# 0.09fF
+C9 a_n33_n90# w_n359_n309# 0.05fF
+C10 a_63_n90# w_n359_n309# 0.06fF
+C11 a_n33_n90# a_63_n90# 0.26fF
+C12 a_n221_n90# a_n129_n90# 0.26fF
+C13 a_n221_n90# w_n359_n309# 0.09fF
+C14 a_n221_n90# a_n33_n90# 0.09fF
+C15 a_n221_n90# a_63_n90# 0.06fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n125_n45# a_n33_n45# 0.13fF
+C1 a_n125_n45# a_63_n45# 0.05fF
+C2 a_n33_n45# a_63_n45# 0.13fF
+C3 a_33_n71# a_n129_71# 0.04fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 out A 0.06fF
+C1 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C2 out vdd 0.11fF
+C3 B out 0.40fF
+C4 A vdd 0.09fF
+C5 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C6 B A 0.24fF
+C7 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C1 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C2 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C3 nor_pfd_2/B vdd 0.02fF
+C4 Q nor_pfd_2/B 2.22fF
+C5 Reset nor_pfd_2/B 0.43fF
+C6 vdd nor_pfd_2/A -0.01fF
+C7 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C8 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C9 Q nor_pfd_2/A 1.38fF
+C10 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C11 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C12 Q vdd 0.08fF
+C13 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C14 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C15 Reset Q 0.14fF
+C16 nor_pfd_3/A vdd 0.09fF
+C17 nor_pfd_3/A Q 0.98fF
+C18 CLK Q 0.04fF
+C19 Reset nor_pfd_3/A 0.12fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 Reset vss 1.48fF
+C24 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 nor_pfd_2/A vss 2.56fF
+C27 vdd vss 16.42fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 nor_pfd_3/A vss 3.16fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_n45# a_159_n45# 0.03fF
+C1 a_n33_n45# a_159_n45# 0.05fF
+C2 a_63_n45# a_159_n45# 0.13fF
+C3 a_n129_n45# a_n221_n45# 0.13fF
+C4 a_n33_n45# a_n221_n45# 0.05fF
+C5 a_63_n45# a_n221_n45# 0.03fF
+C6 a_n159_n173# a_n63_n71# 0.10fF
+C7 a_n221_n45# a_159_n45# 0.02fF
+C8 a_n129_n45# a_n33_n45# 0.13fF
+C9 a_n129_n45# a_63_n45# 0.05fF
+C10 a_n33_n45# a_63_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n99_n187# a_33_n187# 0.04fF
+C1 a_63_n90# a_n33_n90# 0.26fF
+C2 a_63_n90# a_n125_n90# 0.09fF
+C3 a_n125_n90# a_n33_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n73_n45# a_15_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n73_n90# w_n211_n309# 0.04fF
+C1 a_15_n90# w_n211_n309# 0.09fF
+C2 a_15_n90# a_n73_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# out vss vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 A B 0.33fF
+C1 B a_656_410# 0.30fF
+C2 out a_656_410# 0.20fF
+C3 A a_656_410# 0.04fF
+C4 vdd out 0.10fF
+C5 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C6 vdd A 0.05fF
+C7 vdd a_656_410# 0.20fF
+C8 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C9 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD_pex_c vss vdd Up A B Down Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# Reset vss vdd Up Down and_pfd
+C0 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C1 Down vdd 0.08fF
+C2 vdd Reset 0.02fF
+C3 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C4 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
+C5 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
+C6 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C7 Down Up 0.06fF
+C8 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C9 Up vdd 1.62fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C19 vdd vss 44.73fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 4.18fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 Reset vss 5.05fF
+C31 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C34 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C35 Up vss 2.76fF
+C36 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C37 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
diff --git a/xschem/analog_wrapper_tb.spice b/xschem/simulations/analog_wrapper_tb.spice
similarity index 100%
rename from xschem/analog_wrapper_tb.spice
rename to xschem/simulations/analog_wrapper_tb.spice
diff --git a/xschem/simulations/and_pfd.spice b/xschem/simulations/and_pfd.spice
new file mode 100644
index 0000000..60e45db
--- /dev/null
+++ b/xschem/simulations/and_pfd.spice
@@ -0,0 +1,33 @@
+**.subckt and_pfd vdd vss out A B
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/bias_pex_c.spice b/xschem/simulations/bias_pex_c.spice
new file mode 100644
index 0000000..0caf87b
--- /dev/null
+++ b/xschem/simulations/bias_pex_c.spice
@@ -0,0 +1,157 @@
+* NGSPICE file created from bias.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_8P223X VSUBS a_n2017_n1317# a_n1731_n1219# a_n1879_n1219#
++ a_n2017_n61# w_n2018_n202#
+X0 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X1 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X2 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X3 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X4 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X5 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X6 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X7 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X8 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X9 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X10 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X11 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X12 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X13 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X14 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X15 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X16 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X17 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X18 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X19 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X20 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X21 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X22 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X23 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X24 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X25 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X26 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X27 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X28 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X29 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X30 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X31 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X32 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X33 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X34 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X35 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X36 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X37 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X38 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X39 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X40 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X41 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X42 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X43 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X44 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X45 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X46 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X47 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X48 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+C0 a_n1879_n1219# w_n2018_n202# 0.25fF
+C1 a_n1731_n1219# w_n2018_n202# 19.90fF
+C2 a_n2017_n1317# w_n2018_n202# 0.16fF
+C3 a_n2017_n61# w_n2018_n202# 1.37fF
+C4 a_n1731_n1219# a_n1879_n1219# 19.29fF
+C5 a_n2017_n1317# a_n1879_n1219# 2.66fF
+C6 a_n1731_n1219# a_n2017_n1317# 4.73fF
+C7 a_n2017_n61# a_n1879_n1219# 0.16fF
+C8 a_n1731_n1219# a_n2017_n61# 5.23fF
+C9 a_n2017_n61# a_n2017_n1317# 2.88fF
+C10 a_n1879_n1219# VSUBS 1.53fF
+C11 a_n2017_n1317# VSUBS 5.03fF
+C12 a_n1731_n1219# VSUBS 2.60fF
+C13 a_n2017_n61# VSUBS 5.10fF
+C14 w_n2018_n202# VSUBS 37.43fF
+.ends
+
+.subckt bias_pex_c vdd iref vss iref_0 iref_1 iref_2 iref_3 iref_4 iref_5 iref_6 iref_7 iref_8 iref_9
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_5 vss iref m1_20168_984# iref m1_20168_984#
++ vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_6 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219#
++ iref_5 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_7 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219#
++ iref_6 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_9 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219#
++ iref_8 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_8 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219#
++ iref_7 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_10 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219#
++ iref_9 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_0 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219#
++ iref_0 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_1 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219#
++ iref_1 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_2 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219#
++ iref_2 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_3 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219#
++ iref_3 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_4 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219#
++ iref_4 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+C0 iref iref_2 -0.01fF
+C1 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# iref_5 0.24fF
+C2 iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.02fF
+C3 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vdd 0.24fF
+C4 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# m1_20168_984# -0.39fF
+C5 iref_7 iref_6 0.05fF
+C6 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# iref_8 0.24fF
+C7 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vdd 0.24fF
+C8 iref m1_20168_984# 0.07fF
+C9 iref iref_5 0.05fF
+C10 iref iref_9 -0.01fF
+C11 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.01fF
+C12 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# 0.67fF
+C13 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# 0.24fF
+C14 iref_7 iref_8 0.05fF
+C15 iref_3 iref_4 0.05fF
+C16 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# iref_2 0.24fF
+C17 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C18 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vdd 0.24fF
+C19 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# 0.54fF
+C20 iref iref_8 -0.03fF
+C21 iref_7 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C22 iref_6 iref_5 0.05fF
+C23 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# m1_20168_984# 0.01fF
+C24 iref_2 iref_3 0.05fF
+C25 iref vdd -0.07fF
+C26 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref_3 0.24fF
+C27 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.24fF
+C28 iref iref_1 -0.02fF
+C29 iref_2 iref_1 0.05fF
+C30 iref iref_4 0.30fF
+C31 iref_8 iref_9 0.05fF
+C32 iref sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# -0.15fF
+C33 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vdd 0.24fF
+C34 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# iref_6 0.24fF
+C35 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# iref_1 0.24fF
+C36 m1_20168_984# vdd 0.25fF
+C37 iref_0 iref_1 0.05fF
+C38 iref vss 32.42fF
+C39 iref_4 vss 1.17fF
+C40 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vss 2.60fF
+C41 iref_3 vss 0.64fF
+C42 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vss 2.60fF
+C43 iref_2 vss -1.26fF
+C44 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vss 2.60fF
+C45 iref_1 vss -0.80fF
+C46 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vss 2.60fF
+C47 m1_20168_984# vss 56.92fF
+C48 vdd vss 416.01fF
+C49 iref_0 vss 1.88fF
+C50 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vss 2.60fF
+C51 iref_9 vss -1.13fF
+C52 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vss 2.60fF
+C53 iref_7 vss -1.38fF
+C54 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vss 2.60fF
+C55 iref_8 vss -1.19fF
+C56 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vss 2.60fF
+C57 iref_6 vss -1.00fF
+C58 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vss 2.60fF
+C59 iref_5 vss 1.40fF
+C60 sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vss 2.60fF
+.ends
+
diff --git a/xschem/simulations/buffer_salida.spice b/xschem/simulations/buffer_salida.spice
new file mode 100644
index 0000000..e1c0b34
--- /dev/null
+++ b/xschem/simulations/buffer_salida.spice
@@ -0,0 +1,26 @@
+**.subckt buffer_salida vss in vdd out
+*.iopin vss
+*.ipin in
+*.iopin vdd
+*.opin out
+XM2 net1 in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 net1 in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM3 net2 net1 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM4 net2 net1 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM5 out net2 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+XM6 out net2 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/buffer_salida_pex_c.spice b/xschem/simulations/buffer_salida_pex_c.spice
new file mode 100644
index 0000000..bd41c7e
--- /dev/null
+++ b/xschem/simulations/buffer_salida_pex_c.spice
@@ -0,0 +1,191 @@
+* NGSPICE file created from buffer_salida.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n221_n600# a_n257_n777# 0.25fF
+C1 a_n129_n600# a_n257_n777# 0.29fF
+C2 a_n129_n600# a_n221_n600# 7.87fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n129_n300# a_n221_n300# 4.05fF
+C1 a_n257_n404# a_n221_n300# 0.21fF
+C2 a_n129_n300# a_n257_n404# 0.30fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida_pex_c vdd out in vss
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 out a_3996_n100# 55.19fF
+C1 vdd in 0.02fF
+C2 in a_678_n100# 0.81fF
+C3 a_3996_n100# vdd 3.68fF
+C4 a_3996_n100# a_678_n100# 6.52fF
+C5 out vdd 47.17fF
+C6 vdd a_678_n100# 0.08fF
+C7 vdd vss 183.00fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
diff --git a/xschem/simulations/cap1_loop_filter.spice b/xschem/simulations/cap1_loop_filter.spice
new file mode 100644
index 0000000..b760ea2
--- /dev/null
+++ b/xschem/simulations/cap1_loop_filter.spice
@@ -0,0 +1,7 @@
+**.subckt cap1_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/cap2_loop_filter.spice b/xschem/simulations/cap2_loop_filter.spice
new file mode 100644
index 0000000..c495244
--- /dev/null
+++ b/xschem/simulations/cap2_loop_filter.spice
@@ -0,0 +1,7 @@
+**.subckt cap2_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/cap3_loop_filter.spice b/xschem/simulations/cap3_loop_filter.spice
new file mode 100644
index 0000000..2c47061
--- /dev/null
+++ b/xschem/simulations/cap3_loop_filter.spice
@@ -0,0 +1,7 @@
+**.subckt cap3_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=4 m=4
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/charge_pump.spice b/xschem/simulations/charge_pump.spice
new file mode 100644
index 0000000..3958f73
--- /dev/null
+++ b/xschem/simulations/charge_pump.spice
@@ -0,0 +1,48 @@
+**.subckt charge_pump vss vdd Down nUp Up nDown out nswitch pswitch iref biasp
+*.iopin vss
+*.iopin vdd
+*.ipin Down
+*.ipin nUp
+*.ipin Up
+*.ipin nDown
+*.opin out
+*.iopin nswitch
+*.iopin pswitch
+*.ipin iref
+*.iopin biasp
+XM1 out pswitch vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM2 out nswitch vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM3 pswitch nUp biasp vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 pswitch Up vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM5 nswitch Down iref vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM6 nswitch nDown vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM7 pswitch nUp pswitch vdd sky130_fd_pr__pfet_01v8 L=2 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM8 nswitch Down nswitch vss sky130_fd_pr__nfet_01v8 L=1.5 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM9 iref iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM10 biasp iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM11 biasp biasp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/charge_pump_pex_c.spice b/xschem/simulations/charge_pump_pex_c.spice
new file mode 100644
index 0000000..90a1be4
--- /dev/null
+++ b/xschem/simulations/charge_pump_pex_c.spice
@@ -0,0 +1,692 @@
+* NGSPICE file created from charge_pump.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_1803_n486# w_n2457_n634# 0.02fF
+C1 a_2261_n486# w_n2457_n634# 0.02fF
+C2 w_n2457_n634# a_n487_n486# 0.02fF
+C3 a_n945_n486# w_n2457_n634# 0.02fF
+C4 a_n29_n486# w_n2457_n634# 0.02fF
+C5 a_n1403_n486# w_n2457_n634# 0.02fF
+C6 w_n2457_n634# a_n2319_n486# 0.02fF
+C7 w_n2457_n634# a_887_n486# 0.02fF
+C8 a_n1861_n486# w_n2457_n634# 0.02fF
+C9 w_n2457_n634# a_1345_n486# 0.02fF
+C10 a_429_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_303_n75# a_111_n75# 0.08fF
+C1 a_n657_n75# a_n465_n75# 0.08fF
+C2 a_n273_n75# a_n81_n75# 0.08fF
+C3 a_n1229_n75# a_n1041_n75# 0.08fF
+C4 a_687_n75# a_591_n75# 0.22fF
+C5 a_687_n75# a_303_n75# 0.03fF
+C6 a_n657_n75# a_n1041_n75# 0.03fF
+C7 a_n1229_n75# a_n1137_n75# 0.22fF
+C8 a_591_n75# a_975_n75# 0.03fF
+C9 a_n465_n75# a_n369_n75# 0.22fF
+C10 a_n561_n75# a_n177_n75# 0.03fF
+C11 a_207_n75# a_399_n75# 0.08fF
+C12 a_399_n75# a_15_n75# 0.03fF
+C13 a_207_n75# a_n177_n75# 0.03fF
+C14 a_n1229_n75# a_n945_n75# 0.05fF
+C15 a_15_n75# a_n177_n75# 0.08fF
+C16 a_n657_n75# a_n945_n75# 0.05fF
+C17 a_n465_n75# a_n273_n75# 0.08fF
+C18 a_111_n75# a_399_n75# 0.05fF
+C19 a_111_n75# a_n177_n75# 0.05fF
+C20 a_687_n75# a_399_n75# 0.05fF
+C21 a_n465_n75# a_n81_n75# 0.03fF
+C22 a_495_n75# a_879_n75# 0.03fF
+C23 a_303_n75# a_n81_n75# 0.03fF
+C24 a_591_n75# a_879_n75# 0.05fF
+C25 a_n369_n75# a_n177_n75# 0.08fF
+C26 a_n273_n75# a_n177_n75# 0.22fF
+C27 a_783_n75# a_1071_n75# 0.05fF
+C28 a_687_n75# a_783_n75# 0.22fF
+C29 a_n1041_n75# a_n1137_n75# 0.22fF
+C30 a_975_n75# a_783_n75# 0.08fF
+C31 a_n81_n75# a_n177_n75# 0.22fF
+C32 a_495_n75# a_591_n75# 0.22fF
+C33 a_n945_n75# a_n1041_n75# 0.22fF
+C34 a_303_n75# a_495_n75# 0.08fF
+C35 a_n561_n75# a_n753_n75# 0.08fF
+C36 a_1167_n75# a_783_n75# 0.03fF
+C37 a_n561_n75# a_n849_n75# 0.05fF
+C38 a_n945_n75# a_n1137_n75# 0.08fF
+C39 a_n849_n75# a_n753_n75# 0.22fF
+C40 a_303_n75# a_591_n75# 0.05fF
+C41 a_207_n75# a_15_n75# 0.08fF
+C42 a_n465_n75# a_n177_n75# 0.05fF
+C43 a_207_n75# a_111_n75# 0.22fF
+C44 a_495_n75# a_399_n75# 0.22fF
+C45 a_111_n75# a_15_n75# 0.22fF
+C46 a_591_n75# a_399_n75# 0.08fF
+C47 a_303_n75# a_399_n75# 0.22fF
+C48 a_n561_n75# a_n657_n75# 0.22fF
+C49 a_n849_n75# a_n1229_n75# 0.03fF
+C50 a_n657_n75# a_n753_n75# 0.22fF
+C51 a_879_n75# a_783_n75# 0.22fF
+C52 a_n657_n75# a_n849_n75# 0.08fF
+C53 a_687_n75# a_1071_n75# 0.03fF
+C54 a_n561_n75# a_n369_n75# 0.08fF
+C55 a_n753_n75# a_n369_n75# 0.03fF
+C56 a_975_n75# a_1071_n75# 0.22fF
+C57 a_687_n75# a_975_n75# 0.05fF
+C58 a_n369_n75# a_15_n75# 0.03fF
+C59 a_n561_n75# a_n273_n75# 0.05fF
+C60 a_1167_n75# a_1071_n75# 0.22fF
+C61 a_1167_n75# a_975_n75# 0.08fF
+C62 a_495_n75# a_783_n75# 0.05fF
+C63 a_n273_n75# a_15_n75# 0.05fF
+C64 a_591_n75# a_783_n75# 0.08fF
+C65 a_n81_n75# a_207_n75# 0.05fF
+C66 a_n273_n75# a_111_n75# 0.03fF
+C67 a_n81_n75# a_15_n75# 0.22fF
+C68 a_n657_n75# a_n369_n75# 0.05fF
+C69 a_n81_n75# a_111_n75# 0.08fF
+C70 a_n561_n75# a_n465_n75# 0.22fF
+C71 a_n465_n75# a_n753_n75# 0.05fF
+C72 a_n849_n75# a_n465_n75# 0.03fF
+C73 a_n657_n75# a_n273_n75# 0.03fF
+C74 a_879_n75# a_1071_n75# 0.08fF
+C75 a_687_n75# a_879_n75# 0.08fF
+C76 a_n753_n75# a_n1041_n75# 0.05fF
+C77 a_783_n75# a_399_n75# 0.03fF
+C78 a_n849_n75# a_n1041_n75# 0.08fF
+C79 a_975_n75# a_879_n75# 0.22fF
+C80 a_n753_n75# a_n1137_n75# 0.03fF
+C81 a_n273_n75# a_n369_n75# 0.22fF
+C82 a_495_n75# a_207_n75# 0.05fF
+C83 a_n849_n75# a_n1137_n75# 0.05fF
+C84 a_n561_n75# a_n945_n75# 0.03fF
+C85 a_1167_n75# a_879_n75# 0.05fF
+C86 a_n945_n75# a_n753_n75# 0.08fF
+C87 a_n369_n75# a_n81_n75# 0.05fF
+C88 a_591_n75# a_207_n75# 0.03fF
+C89 a_n849_n75# a_n945_n75# 0.22fF
+C90 a_303_n75# a_207_n75# 0.22fF
+C91 a_495_n75# a_111_n75# 0.03fF
+C92 a_303_n75# a_15_n75# 0.05fF
+C93 a_687_n75# a_495_n75# 0.08fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n989_n150# a_n897_n150# 0.43fF
+C1 a_639_n150# a_447_n150# 0.16fF
+C2 a_n513_n150# a_n609_n150# 0.43fF
+C3 a_n417_n150# a_n801_n150# 0.07fF
+C4 a_n989_n150# a_n801_n150# 0.16fF
+C5 a_543_n150# a_735_n150# 0.16fF
+C6 a_735_n150# a_351_n150# 0.07fF
+C7 a_543_n150# a_159_n150# 0.07fF
+C8 a_n513_n150# a_n225_n150# 0.10fF
+C9 a_351_n150# a_159_n150# 0.16fF
+C10 a_447_n150# a_735_n150# 0.10fF
+C11 a_447_n150# a_159_n150# 0.10fF
+C12 a_63_n150# a_255_n150# 0.16fF
+C13 a_639_n150# a_831_n150# 0.16fF
+C14 a_927_n150# a_831_n150# 0.43fF
+C15 a_63_n150# a_n321_n150# 0.07fF
+C16 a_n321_n150# a_n705_n150# 0.07fF
+C17 a_n513_n150# a_n129_n150# 0.07fF
+C18 a_639_n150# a_255_n150# 0.07fF
+C19 a_n513_n150# a_n897_n150# 0.07fF
+C20 a_n609_n150# a_n321_n150# 0.10fF
+C21 a_255_n150# a_n33_n150# 0.10fF
+C22 a_n33_n150# a_n321_n150# 0.10fF
+C23 a_n513_n150# a_n801_n150# 0.10fF
+C24 a_831_n150# a_735_n150# 0.43fF
+C25 a_n321_n150# a_n225_n150# 0.43fF
+C26 a_n513_n150# a_n417_n150# 0.43fF
+C27 a_n927_n247# a_33_n247# 0.09fF
+C28 a_255_n150# a_159_n150# 0.43fF
+C29 a_n609_n150# a_n705_n150# 0.43fF
+C30 a_63_n150# a_n33_n150# 0.43fF
+C31 a_639_n150# a_927_n150# 0.10fF
+C32 a_63_n150# a_n225_n150# 0.10fF
+C33 a_255_n150# a_n129_n150# 0.07fF
+C34 a_543_n150# a_351_n150# 0.16fF
+C35 a_n321_n150# a_n129_n150# 0.16fF
+C36 a_n609_n150# a_n225_n150# 0.07fF
+C37 a_543_n150# a_447_n150# 0.43fF
+C38 a_447_n150# a_351_n150# 0.43fF
+C39 a_63_n150# a_159_n150# 0.43fF
+C40 a_n33_n150# a_n225_n150# 0.16fF
+C41 a_639_n150# a_735_n150# 0.43fF
+C42 a_927_n150# a_735_n150# 0.16fF
+C43 a_n321_n150# a_n417_n150# 0.43fF
+C44 a_n33_n150# a_159_n150# 0.16fF
+C45 a_63_n150# a_n129_n150# 0.16fF
+C46 a_n705_n150# a_n897_n150# 0.16fF
+C47 a_n225_n150# a_159_n150# 0.07fF
+C48 a_n609_n150# a_n897_n150# 0.10fF
+C49 a_n705_n150# a_n801_n150# 0.43fF
+C50 a_n33_n150# a_n129_n150# 0.43fF
+C51 a_n609_n150# a_n801_n150# 0.16fF
+C52 a_831_n150# a_543_n150# 0.10fF
+C53 a_n129_n150# a_n225_n150# 0.43fF
+C54 a_n417_n150# a_n705_n150# 0.10fF
+C55 a_n989_n150# a_n705_n150# 0.10fF
+C56 a_n609_n150# a_n417_n150# 0.16fF
+C57 a_255_n150# a_543_n150# 0.10fF
+C58 a_831_n150# a_447_n150# 0.07fF
+C59 a_255_n150# a_351_n150# 0.43fF
+C60 a_n989_n150# a_n609_n150# 0.07fF
+C61 a_n33_n150# a_n417_n150# 0.07fF
+C62 a_n129_n150# a_159_n150# 0.10fF
+C63 a_255_n150# a_447_n150# 0.16fF
+C64 a_n225_n150# a_n417_n150# 0.16fF
+C65 a_n513_n150# a_n321_n150# 0.16fF
+C66 a_63_n150# a_351_n150# 0.10fF
+C67 a_n897_n150# a_n801_n150# 0.43fF
+C68 a_639_n150# a_543_n150# 0.43fF
+C69 a_63_n150# a_447_n150# 0.07fF
+C70 a_639_n150# a_351_n150# 0.10fF
+C71 a_927_n150# a_543_n150# 0.07fF
+C72 a_n129_n150# a_n417_n150# 0.10fF
+C73 a_n33_n150# a_351_n150# 0.07fF
+C74 a_n513_n150# a_n705_n150# 0.16fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n989_n75# a_n801_n75# 0.08fF
+C1 a_927_n75# a_735_n75# 0.08fF
+C2 a_63_n75# a_447_n75# 0.03fF
+C3 a_n225_n75# a_n33_n75# 0.08fF
+C4 a_n129_n75# a_n417_n75# 0.05fF
+C5 a_n801_n75# a_n705_n75# 0.22fF
+C6 a_351_n75# a_n33_n75# 0.03fF
+C7 a_927_n75# a_831_n75# 0.22fF
+C8 a_n989_n75# a_n609_n75# 0.03fF
+C9 a_159_n75# a_543_n75# 0.03fF
+C10 a_63_n75# a_n225_n75# 0.05fF
+C11 a_735_n75# a_543_n75# 0.08fF
+C12 a_63_n75# a_351_n75# 0.05fF
+C13 a_n705_n75# a_n609_n75# 0.22fF
+C14 a_n129_n75# a_255_n75# 0.03fF
+C15 a_831_n75# a_543_n75# 0.05fF
+C16 a_n513_n75# a_n705_n75# 0.08fF
+C17 a_n33_n75# a_n417_n75# 0.03fF
+C18 a_255_n75# a_159_n75# 0.22fF
+C19 a_n321_n75# a_n609_n75# 0.05fF
+C20 a_447_n75# a_639_n75# 0.08fF
+C21 a_n513_n75# a_n321_n75# 0.08fF
+C22 a_n225_n75# a_n321_n75# 0.22fF
+C23 a_n33_n75# a_255_n75# 0.05fF
+C24 a_n705_n75# a_n417_n75# 0.05fF
+C25 a_639_n75# a_351_n75# 0.05fF
+C26 a_63_n75# a_255_n75# 0.08fF
+C27 a_639_n75# a_927_n75# 0.05fF
+C28 a_n801_n75# a_n609_n75# 0.08fF
+C29 a_n321_n75# a_n417_n75# 0.22fF
+C30 a_n801_n75# a_n513_n75# 0.05fF
+C31 a_639_n75# a_543_n75# 0.22fF
+C32 a_n513_n75# a_n609_n75# 0.22fF
+C33 a_n225_n75# a_n609_n75# 0.03fF
+C34 a_447_n75# a_351_n75# 0.22fF
+C35 a_n129_n75# a_159_n75# 0.05fF
+C36 a_n927_n101# a_33_n101# 0.08fF
+C37 a_n513_n75# a_n225_n75# 0.05fF
+C38 a_639_n75# a_255_n75# 0.03fF
+C39 a_n801_n75# a_n417_n75# 0.03fF
+C40 a_n129_n75# a_n33_n75# 0.22fF
+C41 a_831_n75# a_735_n75# 0.22fF
+C42 a_447_n75# a_543_n75# 0.22fF
+C43 a_n417_n75# a_n609_n75# 0.08fF
+C44 a_n33_n75# a_159_n75# 0.08fF
+C45 a_63_n75# a_n129_n75# 0.08fF
+C46 a_n513_n75# a_n417_n75# 0.22fF
+C47 a_n897_n75# a_n989_n75# 0.22fF
+C48 a_n225_n75# a_n417_n75# 0.08fF
+C49 a_63_n75# a_159_n75# 0.22fF
+C50 a_351_n75# a_543_n75# 0.08fF
+C51 a_447_n75# a_255_n75# 0.08fF
+C52 a_n897_n75# a_n705_n75# 0.08fF
+C53 a_927_n75# a_543_n75# 0.03fF
+C54 a_63_n75# a_n33_n75# 0.22fF
+C55 a_n321_n75# a_n129_n75# 0.08fF
+C56 a_351_n75# a_255_n75# 0.22fF
+C57 a_639_n75# a_735_n75# 0.22fF
+C58 a_n321_n75# a_n33_n75# 0.05fF
+C59 a_255_n75# a_543_n75# 0.05fF
+C60 a_n989_n75# a_n705_n75# 0.05fF
+C61 a_639_n75# a_831_n75# 0.08fF
+C62 a_n897_n75# a_n801_n75# 0.22fF
+C63 a_63_n75# a_n321_n75# 0.03fF
+C64 a_n897_n75# a_n609_n75# 0.05fF
+C65 a_n321_n75# a_n705_n75# 0.03fF
+C66 a_447_n75# a_159_n75# 0.05fF
+C67 a_447_n75# a_735_n75# 0.05fF
+C68 a_n897_n75# a_n513_n75# 0.03fF
+C69 a_n513_n75# a_n129_n75# 0.03fF
+C70 a_n225_n75# a_n129_n75# 0.22fF
+C71 a_447_n75# a_831_n75# 0.03fF
+C72 a_n225_n75# a_159_n75# 0.03fF
+C73 a_351_n75# a_159_n75# 0.08fF
+C74 a_351_n75# a_735_n75# 0.03fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n1103_n44# a_n1461_n44# 0.04fF
+C1 a_1045_n44# a_687_n44# 0.04fF
+C2 a_n29_n44# a_329_n44# 0.04fF
+C3 a_n1103_n44# a_n745_n44# 0.04fF
+C4 a_1403_n44# a_1761_n44# 0.04fF
+C5 a_n1461_n44# a_n1819_n44# 0.04fF
+C6 a_687_n44# a_329_n44# 0.04fF
+C7 a_n387_n44# a_n29_n44# 0.04fF
+C8 a_n387_n44# a_n745_n44# 0.04fF
+C9 a_1403_n44# a_1045_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_975_n150# a_783_n150# 0.16fF
+C1 w_n1367_n369# a_1071_n150# 0.07fF
+C2 a_n561_n150# a_n177_n150# 0.07fF
+C3 a_591_n150# a_879_n150# 0.10fF
+C4 a_111_n150# a_207_n150# 0.43fF
+C5 a_n753_n150# a_n849_n150# 0.43fF
+C6 a_n273_n150# a_n657_n150# 0.07fF
+C7 a_687_n150# a_303_n150# 0.07fF
+C8 a_n465_n150# a_n849_n150# 0.07fF
+C9 a_n177_n150# a_207_n150# 0.07fF
+C10 a_687_n150# a_399_n150# 0.10fF
+C11 a_n561_n150# a_n273_n150# 0.10fF
+C12 a_207_n150# a_303_n150# 0.43fF
+C13 a_15_n150# a_n369_n150# 0.07fF
+C14 a_n753_n150# a_n369_n150# 0.07fF
+C15 a_399_n150# a_207_n150# 0.16fF
+C16 a_n81_n150# a_207_n150# 0.10fF
+C17 a_n657_n150# a_n849_n150# 0.16fF
+C18 a_n1041_n150# a_n849_n150# 0.16fF
+C19 a_n369_n150# a_n465_n150# 0.43fF
+C20 a_591_n150# a_303_n150# 0.10fF
+C21 a_n1229_n150# a_n849_n150# 0.07fF
+C22 a_399_n150# a_591_n150# 0.16fF
+C23 a_n561_n150# a_n849_n150# 0.10fF
+C24 a_687_n150# a_495_n150# 0.16fF
+C25 a_1167_n150# a_879_n150# 0.10fF
+C26 a_975_n150# a_1071_n150# 0.43fF
+C27 a_n945_n150# a_n849_n150# 0.43fF
+C28 a_n657_n150# a_n369_n150# 0.10fF
+C29 a_207_n150# a_495_n150# 0.10fF
+C30 a_783_n150# a_1071_n150# 0.10fF
+C31 a_n561_n150# a_n369_n150# 0.16fF
+C32 a_111_n150# a_n177_n150# 0.10fF
+C33 a_111_n150# a_303_n150# 0.16fF
+C34 a_591_n150# a_495_n150# 0.43fF
+C35 a_879_n150# w_n1367_n369# 0.04fF
+C36 a_111_n150# a_399_n150# 0.10fF
+C37 a_687_n150# a_975_n150# 0.10fF
+C38 a_111_n150# a_n81_n150# 0.16fF
+C39 a_n1137_n150# a_n849_n150# 0.10fF
+C40 a_111_n150# a_n273_n150# 0.07fF
+C41 a_879_n150# a_495_n150# 0.07fF
+C42 a_n177_n150# a_n81_n150# 0.43fF
+C43 a_399_n150# a_303_n150# 0.43fF
+C44 a_687_n150# a_783_n150# 0.43fF
+C45 a_n81_n150# a_303_n150# 0.07fF
+C46 a_n177_n150# a_n273_n150# 0.43fF
+C47 a_n753_n150# a_n465_n150# 0.10fF
+C48 a_1167_n150# w_n1367_n369# 0.14fF
+C49 a_591_n150# a_975_n150# 0.07fF
+C50 a_111_n150# a_495_n150# 0.07fF
+C51 a_n81_n150# a_n273_n150# 0.16fF
+C52 a_n753_n150# a_n657_n150# 0.43fF
+C53 a_n753_n150# a_n1041_n150# 0.10fF
+C54 a_591_n150# a_783_n150# 0.16fF
+C55 a_495_n150# a_303_n150# 0.16fF
+C56 a_n657_n150# a_n465_n150# 0.16fF
+C57 a_879_n150# a_975_n150# 0.43fF
+C58 a_n561_n150# a_n753_n150# 0.16fF
+C59 a_399_n150# a_495_n150# 0.43fF
+C60 a_n945_n150# a_n753_n150# 0.16fF
+C61 a_n561_n150# a_n465_n150# 0.43fF
+C62 a_879_n150# a_783_n150# 0.43fF
+C63 a_n657_n150# a_n1041_n150# 0.07fF
+C64 a_n177_n150# a_n369_n150# 0.16fF
+C65 a_15_n150# a_207_n150# 0.16fF
+C66 a_687_n150# a_1071_n150# 0.07fF
+C67 a_n1229_n150# a_n1041_n150# 0.16fF
+C68 a_1167_n150# a_975_n150# 0.16fF
+C69 a_n561_n150# a_n657_n150# 0.43fF
+C70 a_n81_n150# a_n369_n150# 0.10fF
+C71 a_n945_n150# a_n657_n150# 0.10fF
+C72 a_n945_n150# a_n1041_n150# 0.43fF
+C73 a_n273_n150# a_n369_n150# 0.43fF
+C74 a_1167_n150# a_783_n150# 0.07fF
+C75 a_n945_n150# a_n1229_n150# 0.10fF
+C76 a_n1137_n150# a_n753_n150# 0.07fF
+C77 a_n561_n150# a_n945_n150# 0.07fF
+C78 a_399_n150# a_783_n150# 0.07fF
+C79 a_975_n150# w_n1367_n369# 0.05fF
+C80 a_879_n150# a_1071_n150# 0.16fF
+C81 a_15_n150# a_111_n150# 0.43fF
+C82 a_n1137_n150# a_n1041_n150# 0.43fF
+C83 a_n1137_n150# a_n1229_n150# 0.43fF
+C84 a_687_n150# a_591_n150# 0.43fF
+C85 a_15_n150# a_n177_n150# 0.16fF
+C86 a_783_n150# a_495_n150# 0.10fF
+C87 a_15_n150# a_303_n150# 0.10fF
+C88 a_1167_n150# a_1071_n150# 0.43fF
+C89 a_n945_n150# a_n1137_n150# 0.16fF
+C90 a_591_n150# a_207_n150# 0.07fF
+C91 a_n177_n150# a_n465_n150# 0.10fF
+C92 a_15_n150# a_399_n150# 0.07fF
+C93 a_15_n150# a_n81_n150# 0.43fF
+C94 a_687_n150# a_879_n150# 0.16fF
+C95 a_15_n150# a_n273_n150# 0.10fF
+C96 a_n81_n150# a_n465_n150# 0.07fF
+C97 a_n273_n150# a_n465_n150# 0.16fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump_pex_c vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 out vdd 6.70fF
+C1 biasp pswitch 3.02fF
+C2 nswitch pswitch 0.06fF
+C3 nUp pswitch 5.66fF
+C4 vdd biasp 2.64fF
+C5 nswitch vdd 0.07fF
+C6 nswitch nDown 0.48fF
+C7 nDown Down 0.13fF
+C8 iref biasp 0.80fF
+C9 nswitch iref 1.83fF
+C10 nUp Up 0.15fF
+C11 vdd pswitch 3.89fF
+C12 nswitch out 1.43fF
+C13 out nUp 0.31fF
+C14 pswitch Up 0.86fF
+C15 nswitch biasp 0.03fF
+C16 out pswitch 5.12fF
+C17 nswitch Down 2.26fF
+C18 Down nUp 0.25fF
+C19 vdd vss 35.71fF
+C20 nswitch vss 6.13fF
+C21 Down vss 4.77fF
+C22 nDown vss 1.11fF
+C23 Up vss 1.17fF
+C24 biasp vss 1.10fF
+C25 iref vss 10.11fF
+C26 out vss -3.12fF
+C27 pswitch vss 3.28fF
+C28 nUp vss 5.85fF
+.ends
+
diff --git a/xschem/simulations/clock_inverter.spice b/xschem/simulations/clock_inverter.spice
new file mode 100644
index 0000000..babdc08
--- /dev/null
+++ b/xschem/simulations/clock_inverter.spice
@@ -0,0 +1,47 @@
+**.subckt clock_inverter CLK vdd vss nCLK_d CLK_d
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+**.ends
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/csvco.spice b/xschem/simulations/csvco.spice
new file mode 100644
index 0000000..828d217
--- /dev/null
+++ b/xschem/simulations/csvco.spice
@@ -0,0 +1,62 @@
+**.subckt csvco vctrl vss vdd out D0
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x4 vdd vbp out out1 vctrl vss D0 csvco_branch
+x5 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x6 vdd vbp out2 out vctrl vss D0 csvco_branch
+**.ends
+
+* expanding symbol: ring_osc/sch/csvco_branch.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/ring_osc/sch/csvco_branch.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/ring_osc/sch/csvco_branch.sch
+.subckt csvco_branch vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding symbol: inverter_csvco/sch/inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/csvco_branch.spice b/xschem/simulations/csvco_branch.spice
new file mode 100644
index 0000000..c6afb0c
--- /dev/null
+++ b/xschem/simulations/csvco_branch.spice
@@ -0,0 +1,41 @@
+**.subckt csvco_branch vctrl vbp vdd vss in out D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+**.ends
+
+* expanding symbol: inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/csvco_branch_v2.spice b/xschem/simulations/csvco_branch_v2.spice
new file mode 100644
index 0000000..4812219
--- /dev/null
+++ b/xschem/simulations/csvco_branch_v2.spice
@@ -0,0 +1,41 @@
+**.subckt csvco_branch_v2 vctrl vbp vdd vss in out D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+C1 net1 vss 5.78f m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+**.ends
+
+* expanding symbol: inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/csvco_pex_c.spice b/xschem/simulations/csvco_pex_c.spice
new file mode 100644
index 0000000..4241239
--- /dev/null
+++ b/xschem/simulations/csvco_pex_c.spice
@@ -0,0 +1,314 @@
+* NGSPICE file created from ring_osc.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_15_n150# 0.51fF
+C1 a_n73_n150# a_n33_n238# 0.02fF
+C2 a_n33_n238# a_15_n150# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_181# a_n73_n150# 0.01fF
+C1 a_n33_181# w_n211_n369# 0.05fF
+C2 w_n211_n369# a_n73_n150# 0.20fF
+C3 a_15_n150# a_n33_181# 0.01fF
+C4 a_15_n150# a_n73_n150# 0.51fF
+C5 a_15_n150# w_n211_n369# 0.20fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n150# a_n321_n150# 0.10fF
+C1 a_n129_n150# a_n225_n150# 0.43fF
+C2 a_447_n150# a_n465_172# 0.01fF
+C3 a_63_n150# a_159_n150# 0.43fF
+C4 a_n509_n150# a_n417_n150# 0.43fF
+C5 a_n509_n150# a_n465_172# 0.01fF
+C6 a_n465_172# a_159_n150# 0.10fF
+C7 a_n33_n150# a_n129_n150# 0.43fF
+C8 a_n225_n150# a_n509_n150# 0.10fF
+C9 a_n225_n150# a_159_n150# 0.07fF
+C10 a_255_n150# a_n129_n150# 0.07fF
+C11 a_n129_n150# a_n321_n150# 0.16fF
+C12 a_447_n150# a_351_n150# 0.43fF
+C13 a_63_n150# a_n465_172# 0.10fF
+C14 a_255_n150# a_447_n150# 0.16fF
+C15 a_63_n150# a_n225_n150# 0.10fF
+C16 a_n465_172# a_n417_n150# 0.10fF
+C17 a_351_n150# a_159_n150# 0.16fF
+C18 a_n33_n150# a_159_n150# 0.16fF
+C19 a_n225_n150# a_n417_n150# 0.16fF
+C20 a_n321_n150# a_n509_n150# 0.16fF
+C21 a_n225_n150# a_n465_172# 0.10fF
+C22 a_255_n150# a_159_n150# 0.43fF
+C23 a_351_n150# a_63_n150# 0.10fF
+C24 a_63_n150# a_n33_n150# 0.43fF
+C25 a_255_n150# a_63_n150# 0.16fF
+C26 a_n33_n150# a_n417_n150# 0.07fF
+C27 a_63_n150# a_n321_n150# 0.07fF
+C28 a_351_n150# a_n465_172# 0.10fF
+C29 a_n129_n150# a_n509_n150# 0.07fF
+C30 a_n33_n150# a_n465_172# 0.10fF
+C31 a_n129_n150# a_159_n150# 0.10fF
+C32 a_255_n150# a_n465_172# 0.10fF
+C33 a_n33_n150# a_n225_n150# 0.16fF
+C34 a_n321_n150# a_n417_n150# 0.43fF
+C35 a_n321_n150# a_n465_172# 0.10fF
+C36 a_n225_n150# a_n321_n150# 0.43fF
+C37 a_447_n150# a_159_n150# 0.10fF
+C38 a_63_n150# a_n129_n150# 0.16fF
+C39 a_351_n150# a_n33_n150# 0.07fF
+C40 a_n129_n150# a_n417_n150# 0.10fF
+C41 a_n129_n150# a_n465_172# 0.10fF
+C42 a_447_n150# a_63_n150# 0.07fF
+C43 a_255_n150# a_351_n150# 0.43fF
+C44 a_255_n150# a_n33_n150# 0.10fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n321_n150# a_n129_n150# 0.16fF
+C1 w_n647_n369# a_n129_n150# 0.02fF
+C2 w_n647_n369# a_351_n150# 0.07fF
+C3 a_n417_n150# a_n129_n150# 0.10fF
+C4 a_n465_n247# a_63_n150# 0.08fF
+C5 a_159_n150# w_n647_n369# 0.04fF
+C6 a_159_n150# a_n129_n150# 0.10fF
+C7 a_n321_n150# a_n33_n150# 0.10fF
+C8 w_n647_n369# a_n33_n150# 0.02fF
+C9 a_159_n150# a_351_n150# 0.16fF
+C10 a_255_n150# a_447_n150# 0.16fF
+C11 a_n417_n150# a_n33_n150# 0.07fF
+C12 a_255_n150# a_63_n150# 0.16fF
+C13 a_n129_n150# a_n33_n150# 0.43fF
+C14 a_n33_n150# a_351_n150# 0.07fF
+C15 a_n225_n150# a_n321_n150# 0.43fF
+C16 a_n225_n150# w_n647_n369# 0.04fF
+C17 a_159_n150# a_n33_n150# 0.16fF
+C18 a_n417_n150# a_n225_n150# 0.16fF
+C19 a_n225_n150# a_n129_n150# 0.43fF
+C20 w_n647_n369# a_447_n150# 0.14fF
+C21 a_n321_n150# a_63_n150# 0.07fF
+C22 w_n647_n369# a_63_n150# 0.02fF
+C23 a_255_n150# a_n465_n247# 0.08fF
+C24 a_159_n150# a_n225_n150# 0.07fF
+C25 a_n321_n150# a_n509_n150# 0.16fF
+C26 w_n647_n369# a_n509_n150# 0.14fF
+C27 a_351_n150# a_447_n150# 0.43fF
+C28 a_n129_n150# a_63_n150# 0.16fF
+C29 a_63_n150# a_351_n150# 0.10fF
+C30 a_n417_n150# a_n509_n150# 0.43fF
+C31 a_n129_n150# a_n509_n150# 0.07fF
+C32 a_n225_n150# a_n33_n150# 0.16fF
+C33 a_159_n150# a_447_n150# 0.10fF
+C34 a_159_n150# a_63_n150# 0.43fF
+C35 a_n321_n150# a_n465_n247# 0.08fF
+C36 a_n465_n247# w_n647_n369# 0.47fF
+C37 a_63_n150# a_n33_n150# 0.43fF
+C38 a_n417_n150# a_n465_n247# 0.08fF
+C39 a_n465_n247# a_n129_n150# 0.08fF
+C40 a_n465_n247# a_351_n150# 0.08fF
+C41 a_159_n150# a_n465_n247# 0.08fF
+C42 a_255_n150# w_n647_n369# 0.05fF
+C43 a_n225_n150# a_63_n150# 0.10fF
+C44 a_n225_n150# a_n509_n150# 0.10fF
+C45 a_255_n150# a_n129_n150# 0.07fF
+C46 a_n465_n247# a_n33_n150# 0.08fF
+C47 a_255_n150# a_351_n150# 0.43fF
+C48 a_63_n150# a_447_n150# 0.07fF
+C49 a_255_n150# a_159_n150# 0.43fF
+C50 a_n321_n150# w_n647_n369# 0.05fF
+C51 a_n225_n150# a_n465_n247# 0.08fF
+C52 a_n417_n150# a_n321_n150# 0.43fF
+C53 a_255_n150# a_n33_n150# 0.10fF
+C54 a_n417_n150# w_n647_n369# 0.07fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n33_n99# 0.02fF
+C1 a_15_n11# a_n73_n11# 0.15fF
+C2 a_n73_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# w_n216_n334# 0.20fF
+C1 a_20_n114# a_n78_n114# 0.42fF
+C2 a_20_n114# w_n216_n334# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 out in 0.11fF
+C1 out vbulkp 0.08fF
+C2 vdd in 0.01fF
+C3 vdd vbulkp 0.04fF
+C4 vss in 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 vbp vdd 1.21fF
+C1 out inverter_csvco_0/vss 0.03fF
+C2 D0 inverter_csvco_0/vss 0.02fF
+C3 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C4 out in 0.06fF
+C5 out D0 0.09fF
+C6 vdd cap_vco_0/t 0.04fF
+C7 inverter_csvco_0/vdd vdd 1.89fF
+C8 inverter_csvco_0/vdd in 0.01fF
+C9 out cap_vco_0/t 0.70fF
+C10 inverter_csvco_0/vdd out 0.02fF
+C11 inverter_csvco_0/vdd vbp 0.75fF
+C12 in inverter_csvco_0/vss 0.01fF
+C13 vctrl inverter_csvco_0/vss 0.87fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt csvco_pex_c vdd out_vco vctrl vss D0
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+C0 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
+C1 csvco_branch_2/in out_vco 0.58fF
+C2 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C3 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C4 csvco_branch_2/vbp vdd 1.49fF
+C5 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C6 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C7 out_vco csvco_branch_1/in 0.76fF
+C8 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C9 vctrl csvco_branch_2/vbp 0.06fF
+C10 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C11 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C12 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C13 vctrl D0 4.41fF
+C14 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C15 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C16 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C17 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C18 csvco_branch_2/in vss 1.60fF
+C19 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C20 vdd vss 31.40fF
+C21 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C22 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C23 csvco_branch_1/in vss 1.58fF
+C24 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C25 out_vco vss 0.67fF
+C26 D0 vss -1.21fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
diff --git a/xschem/simulations/csvco_v2.spice b/xschem/simulations/csvco_v2.spice
new file mode 100644
index 0000000..325c09e
--- /dev/null
+++ b/xschem/simulations/csvco_v2.spice
@@ -0,0 +1,62 @@
+**.subckt csvco_v2 vctrl vss vdd out D0
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x2 vdd vbp out out1 vctrl vss D0 csvco_branch_v2
+x3 vdd vbp out1 out2 vctrl vss D0 csvco_branch_v2
+x4 vdd vbp out2 out vctrl vss D0 csvco_branch_v2
+**.ends
+
+* expanding symbol: csvco_branch_v2.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch_v2.sch
+.subckt csvco_branch_v2 vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding symbol: inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/csvco_v2_pex_c.spice b/xschem/simulations/csvco_v2_pex_c.spice
new file mode 100644
index 0000000..1507fd5
--- /dev/null
+++ b/xschem/simulations/csvco_v2_pex_c.spice
@@ -0,0 +1,174 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n73_n150# 0.51fF
+C1 a_15_n150# a_n33_n238# 0.02fF
+C2 a_n33_n238# a_n73_n150# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n119# a_n73_n119# 0.51fF
+C1 a_15_n119# a_n33_n207# 0.02fF
+C2 a_n33_n207# a_n73_n119# 0.02fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n186# w_n211_n334# 0.21fF
+C1 a_n73_n186# a_n33_145# 0.01fF
+C2 a_n73_n186# w_n211_n334# 0.21fF
+C3 a_15_n186# a_n73_n186# 0.51fF
+C4 w_n211_n334# a_n33_145# 0.05fF
+C5 a_15_n186# a_n33_145# 0.01fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n73_n11# 0.15fF
+C1 a_15_n11# a_n33_n99# 0.02fF
+C2 a_n33_n99# a_n73_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_20_n114# w_n216_n334# 0.20fF
+C1 a_n78_n114# w_n216_n334# 0.20fF
+C2 a_20_n114# a_n78_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 out vbulkp 0.08fF
+C1 out in 0.11fF
+C2 vdd vbulkp 0.04fF
+C3 in vss 0.01fF
+C4 in vdd 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch_v2 vctrl in cap_vco_0/t D0 out m1_185_1641# vss vdd inverter_csvco_0/vss
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 vdd out 0.03fF
+C1 out inverter_csvco_0/vdd 0.02fF
+C2 vctrl cap_vco_0/t 0.03fF
+C3 D0 cap_vco_0/t 0.18fF
+C4 vdd m1_185_1641# 0.48fF
+C5 inverter_csvco_0/vss vctrl 0.23fF
+C6 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C7 inverter_csvco_0/vss cap_vco_0/t 0.12fF
+C8 D0 inverter_csvco_0/vss 0.01fF
+C9 in inverter_csvco_0/vss 0.01fF
+C10 in inverter_csvco_0/vdd 0.01fF
+C11 out cap_vco_0/t 0.11fF
+C12 D0 out 0.09fF
+C13 out in 0.06fF
+C14 vdd inverter_csvco_0/vdd 0.97fF
+C15 out inverter_csvco_0/vss 0.03fF
+C16 vdd vss 3.58fF
+C17 out vss 0.87fF
+C18 inverter_csvco_0/vdd vss 0.14fF
+C19 in vss 0.70fF
+C20 inverter_csvco_0/vss vss 0.72fF
+C21 D0 vss -0.49fF
+C22 m1_185_1641# vss -0.03fF
+C23 cap_vco_0/t vss 8.30fF
+C24 vctrl vss 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_15_n150# 0.51fF
+C1 a_15_n150# a_n33_181# 0.01fF
+C2 w_n211_n369# a_15_n150# 0.20fF
+C3 a_n73_n150# a_n33_181# 0.01fF
+C4 w_n211_n369# a_n73_n150# 0.20fF
+C5 w_n211_n369# a_n33_181# 0.05fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt csvco_v2_pex_c vdd out_vco D0 vctrl vss
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in csvco_branch_v2_1/cap_vco_0/t D0 csvco_branch_v2_2/in
++ vbp vss vdd csvco_branch_v2_1/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco csvco_branch_v2_0/cap_vco_0/t D0 csvco_branch_v2_1/in
++ vbp vss vdd csvco_branch_v2_0/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in csvco_branch_v2_2/cap_vco_0/t D0 out_vco
++ vbp vss vdd csvco_branch_v2_2/inverter_csvco_0/vss csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+C0 csvco_branch_v2_0/cap_vco_0/t vctrl 0.24fF
+C1 csvco_branch_v2_1/in out_vco 0.76fF
+C2 csvco_branch_v2_1/inverter_csvco_0/vss D0 0.04fF
+C3 csvco_branch_v2_0/cap_vco_0/t D0 0.12fF
+C4 csvco_branch_v2_2/in vdd 0.01fF
+C5 vbp vdd 3.04fF
+C6 vctrl vbp 0.06fF
+C7 vctrl csvco_branch_v2_1/cap_vco_0/t 0.24fF
+C8 csvco_branch_v2_2/in out_vco 0.59fF
+C9 D0 csvco_branch_v2_2/inverter_csvco_0/vss 0.04fF
+C10 D0 csvco_branch_v2_2/cap_vco_0/t 1.03fF
+C11 csvco_branch_v2_1/in vdd 0.01fF
+C12 D0 csvco_branch_v2_1/cap_vco_0/t 0.12fF
+C13 vdd vss 14.19fF
+C14 csvco_branch_v2_2/inverter_csvco_0/vdd vss 0.14fF
+C15 csvco_branch_v2_2/inverter_csvco_0/vss vss 0.44fF
+C16 csvco_branch_v2_2/cap_vco_0/t vss 7.06fF
+C17 csvco_branch_v2_1/in vss 1.66fF
+C18 csvco_branch_v2_0/inverter_csvco_0/vdd vss 0.14fF
+C19 out_vco vss 0.49fF
+C20 csvco_branch_v2_0/inverter_csvco_0/vss vss 0.44fF
+C21 D0 vss -1.24fF
+C22 vbp vss -0.38fF
+C23 csvco_branch_v2_0/cap_vco_0/t vss 7.07fF
+C24 vctrl vss 5.55fF
+C25 csvco_branch_v2_2/in vss 1.67fF
+C26 csvco_branch_v2_1/inverter_csvco_0/vdd vss 0.14fF
+C27 csvco_branch_v2_1/inverter_csvco_0/vss vss 0.44fF
+C28 csvco_branch_v2_1/cap_vco_0/t vss 7.07fF
+.ends
+
diff --git a/xschem/current_test.spice b/xschem/simulations/current_test.spice
similarity index 100%
rename from xschem/current_test.spice
rename to xschem/simulations/current_test.spice
diff --git a/xschem/simulations/dff_pfd_pex_c.spice b/xschem/simulations/dff_pfd_pex_c.spice
new file mode 100644
index 0000000..a49bac6
--- /dev/null
+++ b/xschem/simulations/dff_pfd_pex_c.spice
@@ -0,0 +1,116 @@
+* NGSPICE file created from dff_pfd.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 w_n359_n309# a_159_n90# 0.09fF
+C1 a_n33_n90# w_n359_n309# 0.05fF
+C2 a_n33_n90# a_159_n90# 0.09fF
+C3 a_n221_n90# a_63_n90# 0.06fF
+C4 a_63_n90# w_n359_n309# 0.06fF
+C5 a_n129_n90# a_n221_n90# 0.26fF
+C6 a_63_n90# a_159_n90# 0.26fF
+C7 a_63_n90# a_n33_n90# 0.26fF
+C8 a_n129_n90# w_n359_n309# 0.06fF
+C9 a_n129_n90# a_159_n90# 0.06fF
+C10 a_n129_n90# a_n33_n90# 0.26fF
+C11 a_n159_n207# a_n63_n116# 0.12fF
+C12 a_n221_n90# w_n359_n309# 0.09fF
+C13 a_n221_n90# a_159_n90# 0.04fF
+C14 a_n221_n90# a_n33_n90# 0.09fF
+C15 a_n129_n90# a_63_n90# 0.09fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n33_n45# 0.13fF
+C1 a_33_n71# a_n129_71# 0.04fF
+C2 a_n125_n45# a_n33_n45# 0.13fF
+C3 a_n125_n45# a_63_n45# 0.05fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out 0.08fF
+C1 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C2 A vdd 0.09fF
+C3 A B 0.24fF
+C4 A out 0.06fF
+C5 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C6 vdd out 0.11fF
+C7 B out 0.40fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd_pex_c vdd CLK Q Reset vss
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C2 nor_pfd_3/A vdd 0.09fF
+C3 Q nor_pfd_2/B 2.22fF
+C4 Q nor_pfd_2/A 1.38fF
+C5 Q Reset 0.14fF
+C6 Q CLK 0.04fF
+C7 nor_pfd_2/B vdd 0.02fF
+C8 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C9 vdd nor_pfd_2/A -0.01fF
+C10 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C11 nor_pfd_3/A Reset 0.12fF
+C12 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C13 Q vdd 0.08fF
+C14 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C15 Q nor_pfd_3/A 0.98fF
+C16 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C17 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C18 nor_pfd_2/B Reset 0.43fF
+C19 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C22 Reset vss 1.48fF
+C23 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C24 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C25 nor_pfd_2/A vss 2.56fF
+C26 nor_pfd_2/B vss 1.42fF
+C27 vdd vss 16.42fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 0.26fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 nor_pfd_3/A vss 3.16fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
diff --git a/xschem/simulations/div_by_2.spice b/xschem/simulations/div_by_2.spice
new file mode 100644
index 0000000..4347632
--- /dev/null
+++ b/xschem/simulations/div_by_2.spice
@@ -0,0 +1,149 @@
+**.subckt div_by_2 CLK CLK_2 vss vdd nCLK_2 nout_div o2 o1 out_div
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+**.ends
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/div_by_2_pex_c.spice b/xschem/simulations/div_by_2_pex_c.spice
new file mode 100644
index 0000000..54bb1f2
--- /dev/null
+++ b/xschem/simulations/div_by_2_pex_c.spice
@@ -0,0 +1,448 @@
+* NGSPICE file created from div_by_2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH_div2 VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n173_n125# 0.08fF
+C1 a_15_n125# w_n311_n344# 0.09fF
+C2 a_n15_n156# a_n111_n156# 0.02fF
+C3 a_111_n125# w_n311_n344# 0.14fF
+C4 a_111_n125# a_15_n125# 0.36fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 a_n81_n125# w_n311_n344# 0.09fF
+C7 a_15_n125# a_n81_n125# 0.36fF
+C8 w_n311_n344# a_n173_n125# 0.14fF
+C9 a_111_n125# a_n81_n125# 0.13fF
+C10 a_n15_n156# a_81_n156# 0.02fF
+C11 a_15_n125# a_n173_n125# 0.13fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T_div2 a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n15_n151# a_81_n151# 0.02fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_n81_n125# a_n173_n125# 0.36fF
+C5 a_15_n125# a_111_n125# 0.36fF
+C6 a_15_n125# a_n173_n125# 0.13fF
+C7 a_n111_n151# a_n15_n151# 0.02fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate_div2 m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH_div2
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T_div2
+C0 m1_45_n513# vdd 0.69fF
+C1 m1_45_n513# m1_187_n605# 0.36fF
+C2 vdd m1_187_n605# 0.55fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH_div2 VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_n81_n125# a_n173_n125# 0.36fF
+C2 a_15_n125# w_n311_n344# 0.09fF
+C3 a_15_n125# a_111_n125# 0.36fF
+C4 a_n81_n125# w_n311_n344# 0.09fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 w_n311_n344# a_n173_n125# 0.14fF
+C7 a_111_n125# a_n173_n125# 0.08fF
+C8 a_111_n125# w_n311_n344# 0.14fF
+C9 a_15_n125# a_n81_n125# 0.36fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM_div2 w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n81_n125# 0.36fF
+C1 a_111_n125# a_n81_n125# 0.13fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 a_111_n125# a_n173_n125# 0.08fF
+C4 a_15_n125# a_n173_n125# 0.13fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1_div2 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH_div2
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM_div2
+C0 out vdd 0.10fF
+C1 out in 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter_div2 vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out CLK CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate_div2
+Xinverter_cp_x1_0 CLK inverter_cp_x1_0/out vss vdd inverter_cp_x1_div2
+Xinverter_cp_x1_1 CLK inverter_cp_x1_2/in vss vdd inverter_cp_x1_div2
+Xinverter_cp_x1_2 inverter_cp_x1_2/in CLK_d vss vdd inverter_cp_x1_div2
+C0 vdd inverter_cp_x1_2/in 0.21fF
+C1 inverter_cp_x1_2/in CLK_d 0.12fF
+C2 CLK inverter_cp_x1_0/out 0.31fF
+C3 vdd CLK_d 0.03fF
+C4 vdd inverter_cp_x1_0/out 0.28fF
+C5 vdd nCLK_d 0.03fF
+C6 nCLK_d inverter_cp_x1_0/out 0.11fF
+C7 CLK inverter_cp_x1_2/in 0.31fF
+C8 vdd CLK 0.36fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ_div2 VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_n125_n95# 0.11fF
+C1 a_63_n95# a_n33_n95# 0.28fF
+C2 a_63_n95# a_n125_n95# 0.10fF
+C3 a_63_n95# w_n263_n314# 0.11fF
+C4 a_n33_n95# a_n125_n95# 0.28fF
+C5 w_n263_n314# a_n33_n95# 0.08fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854_div2 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_n129_n213# a_n81_n125# 0.10fF
+C3 a_n173_n125# a_n81_n125# 0.36fF
+C4 a_111_n125# a_15_n125# 0.36fF
+C5 a_n173_n125# a_n129_n213# 0.02fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_111_n125# a_n129_n213# 0.01fF
+C8 a_15_n125# a_n81_n125# 0.36fF
+C9 a_n129_n213# a_15_n125# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX_div2 a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n81_n183# a_n33_n95# 0.10fF
+C1 a_n125_n95# a_n33_n95# 0.88fF
+C2 a_n125_n95# a_n81_n183# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff_div2 m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ_div2
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ_div2
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854_div2
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX_div2
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX_div2
+C0 Q m1_657_280# 0.94fF
+C1 Q nD 0.05fF
+C2 D Q 0.05fF
+C3 nQ Q 0.93fF
+C4 vdd Q 0.16fF
+C5 CLK m1_657_280# 0.24fF
+C6 nQ m1_657_280# 1.41fF
+C7 nQ nD 0.05fF
+C8 D nQ 0.05fF
+C9 vdd nQ 0.16fF
+C10 D vss 0.53fF
+C11 Q vss -0.55fF
+C12 m1_657_280# vss 1.88fF
+C13 nD vss 0.16fF
+C14 CLK vss 0.87fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop_div2 vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in nQ Q latch_diff_1/m1_657_280#
++ latch_diff_1/nD vdd clock_inverter_0/inverter_cp_x1_0/out CLK latch_diff_0/D nCLK
++ D latch_diff_0/nD latch_diff_0/m1_657_280#
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in vdd clock_inverter_0/inverter_cp_x1_0/out
++ D latch_diff_0/D latch_diff_0/nD clock_inverter_div2
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff_div2
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff_div2
+C0 latch_diff_1/nD vdd 0.02fF
+C1 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C2 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C3 latch_diff_1/nD Q 0.01fF
+C4 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C5 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C6 latch_diff_1/D nQ 0.11fF
+C7 latch_diff_1/nD latch_diff_0/D 0.04fF
+C8 latch_diff_1/D vdd 0.03fF
+C9 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C10 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C11 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C12 latch_diff_0/nD latch_diff_1/D 0.41fF
+C13 latch_diff_1/D latch_diff_0/D 0.11fF
+C14 latch_diff_1/D latch_diff_1/nD 0.33fF
+C15 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C16 nQ latch_diff_1/nD 0.08fF
+C17 latch_diff_0/nD vdd 0.14fF
+C18 vdd latch_diff_0/D 0.09fF
+C19 Q vss -0.92fF
+C20 latch_diff_1/m1_657_280# vss 0.64fF
+C21 nCLK vss 0.83fF
+C22 nQ vss 0.57fF
+C23 latch_diff_1/D vss -0.30fF
+C24 latch_diff_0/m1_657_280# vss 0.72fF
+C25 CLK vss 0.83fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B_div2 VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_129_n110# a_33_n110# 0.02fF
+C1 w_n359_n303# a_63_n84# 0.06fF
+C2 a_159_n84# a_n221_n84# 0.04fF
+C3 a_n159_n110# a_n63_n110# 0.02fF
+C4 w_n359_n303# a_n33_n84# 0.05fF
+C5 a_n129_n84# a_63_n84# 0.09fF
+C6 a_n33_n84# a_n129_n84# 0.24fF
+C7 w_n359_n303# a_n221_n84# 0.08fF
+C8 a_159_n84# w_n359_n303# 0.08fF
+C9 a_n63_n110# a_33_n110# 0.02fF
+C10 a_n221_n84# a_n129_n84# 0.24fF
+C11 a_159_n84# a_n129_n84# 0.05fF
+C12 a_n33_n84# a_63_n84# 0.24fF
+C13 a_n221_n84# a_63_n84# 0.05fF
+C14 a_159_n84# a_63_n84# 0.24fF
+C15 w_n359_n303# a_n129_n84# 0.06fF
+C16 a_n221_n84# a_n33_n84# 0.09fF
+C17 a_159_n84# a_n33_n84# 0.09fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D_div2 w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n129_n42# a_63_n42# 0.05fF
+C1 a_n221_n42# a_n33_n42# 0.05fF
+C2 a_n129_n42# a_159_n42# 0.03fF
+C3 a_n221_n42# a_63_n42# 0.03fF
+C4 a_n33_n42# a_63_n42# 0.12fF
+C5 a_n221_n42# a_159_n42# 0.02fF
+C6 a_n33_n42# a_159_n42# 0.05fF
+C7 a_n129_n42# a_n221_n42# 0.12fF
+C8 a_n63_n68# a_33_n68# 0.02fF
+C9 a_129_n68# a_33_n68# 0.02fF
+C10 a_159_n42# a_63_n42# 0.12fF
+C11 a_n129_n42# a_n33_n42# 0.12fF
+C12 a_n63_n68# a_n159_n68# 0.02fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4_div2 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B_div2
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D_div2
+C0 out in 0.67fF
+C1 vdd in 0.33fF
+C2 out vdd 0.62fF
+C3 in vss 1.89fF
+C4 out vss 0.66fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK_div2 a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_33_n68# a_n63_n68# 0.02fF
+C1 a_63_n42# a_n33_n42# 0.12fF
+C2 a_63_n42# a_n125_n42# 0.05fF
+C3 a_n125_n42# a_n33_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB_div2 VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n33_n84# a_63_n84# 0.24fF
+C1 a_n33_n84# w_n263_n303# 0.07fF
+C2 a_n33_n84# a_n125_n84# 0.24fF
+C3 w_n263_n303# a_63_n84# 0.10fF
+C4 a_n125_n84# a_63_n84# 0.09fF
+C5 a_33_n110# a_n63_n110# 0.02fF
+C6 w_n263_n303# a_n125_n84# 0.10fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2_div2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK_div2
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB_div2
+C0 in vdd 0.01fF
+C1 out vdd 0.15fF
+C2 out in 0.30fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2_pex_c nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+XDFlipFlop_0 vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_1/nD
++ vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/D
++ DFlipFlop_0/nCLK nout_div DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/latch_diff_0/m1_657_280#
++ DFlipFlop_div2
+Xinverter_min_x4_1 o2 nCLK_2 vss vdd inverter_min_x4_div2
+Xinverter_min_x4_0 o1 CLK_2 vss vdd inverter_min_x4_div2
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in vdd clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter_div2
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2_div2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2_div2
+C0 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C1 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C2 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C3 o1 out_div 0.01fF
+C4 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C5 vdd out_div 0.03fF
+C6 vdd o2 0.14fF
+C7 nout_div DFlipFlop_0/latch_diff_1/m1_657_280# 0.21fF
+C8 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C9 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C10 DFlipFlop_0/nCLK vdd 0.30fF
+C11 vdd nCLK_2 0.08fF
+C12 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C13 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/nD 0.11fF
+C14 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C15 vdd o1 0.14fF
+C16 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
+C17 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C18 nout_div out_div 0.22fF
+C19 o1 CLK_2 0.11fF
+C20 vdd DFlipFlop_0/CLK 0.40fF
+C21 vdd CLK_2 0.08fF
+C22 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C23 DFlipFlop_0/nCLK nout_div 0.43fF
+C24 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C25 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
+C26 DFlipFlop_0/nCLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.46fF
+C27 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C28 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C29 DFlipFlop_0/latch_diff_0/D nout_div 0.09fF
+C30 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C31 vdd nout_div 0.16fF
+C32 o2 nCLK_2 0.11fF
+C33 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C34 nout_div DFlipFlop_0/CLK 0.42fF
+C35 DFlipFlop_0/CLK vss 1.03fF
+C36 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C37 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C38 CLK vss 3.27fF
+C39 DFlipFlop_0/nCLK vss 1.76fF
+C40 o1 vss 2.21fF
+C41 CLK_2 vss 1.08fF
+C42 o2 vss 2.21fF
+C43 nCLK_2 vss 1.08fF
+C44 out_div vss -1.37fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C47 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C48 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.86fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
diff --git a/xschem/simulations/div_by_5.spice b/xschem/simulations/div_by_5.spice
new file mode 100644
index 0000000..bfac654
--- /dev/null
+++ b/xschem/simulations/div_by_5.spice
@@ -0,0 +1,118 @@
+**.subckt div_by_5 vdd vss CLK CLK_5 nCLK nQ2 Q1 Q0 nQ0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+**.ends
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/div_by_5_pex_c.spice b/xschem/simulations/div_by_5_pex_c.spice
new file mode 100644
index 0000000..f087166
--- /dev/null
+++ b/xschem/simulations/div_by_5_pex_c.spice
@@ -0,0 +1,595 @@
+* NGSPICE file created from div_by_5.ext - technology: sky130A
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 X a_194_125# 0.29fF
+C1 a_194_125# A 0.18fF
+C2 a_194_125# B 0.57fF
+C3 X VPWR 0.07fF
+C4 X VGND 0.28fF
+C5 VPWR A 0.15fF
+C6 A VGND 0.31fF
+C7 a_355_368# a_194_125# 0.51fF
+C8 VPWR B 0.09fF
+C9 B VGND 0.10fF
+C10 VPWR a_355_368# 0.37fF
+C11 a_194_125# a_158_392# 0.06fF
+C12 VPWR a_194_125# 0.33fF
+C13 a_194_125# VGND 0.25fF
+C14 X B 0.13fF
+C15 A B 0.28fF
+C16 VPWR VPB 0.06fF
+C17 X a_355_368# 0.17fF
+C18 a_355_368# A 0.02fF
+C19 VPWR VGND 0.01fF
+C20 a_355_368# B 0.08fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n81_n125# 0.36fF
+C1 a_n173_n125# w_n311_n344# 0.14fF
+C2 a_n173_n125# a_n81_n125# 0.36fF
+C3 a_81_n156# a_n15_n156# 0.02fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_111_n125# w_n311_n344# 0.14fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_n111_n156# a_n15_n156# 0.02fF
+C8 w_n311_n344# a_n81_n125# 0.09fF
+C9 a_15_n125# a_111_n125# 0.36fF
+C10 a_15_n125# w_n311_n344# 0.09fF
+C11 a_n173_n125# a_111_n125# 0.08fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_n173_n125# 0.36fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 a_81_n151# a_n15_n151# 0.02fF
+C3 a_111_n125# a_n173_n125# 0.08fF
+C4 a_n15_n151# a_n111_n151# 0.02fF
+C5 a_n81_n125# a_111_n125# 0.13fF
+C6 a_15_n125# a_n173_n125# 0.13fF
+C7 a_n81_n125# a_15_n125# 0.36fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_187_n605# m1_45_n513# 0.36fF
+C1 vdd m1_45_n513# 0.69fF
+C2 vdd m1_187_n605# 0.55fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_15_n125# 0.36fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 w_n311_n344# a_15_n125# 0.09fF
+C4 a_111_n125# a_n173_n125# 0.08fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_111_n125# w_n311_n344# 0.14fF
+C7 a_n173_n125# a_n81_n125# 0.36fF
+C8 a_n173_n125# w_n311_n344# 0.14fF
+C9 w_n311_n344# a_n81_n125# 0.09fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n81_n125# a_111_n125# 0.13fF
+C2 a_111_n125# a_15_n125# 0.36fF
+C3 a_n81_n125# a_n173_n125# 0.36fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_n81_n125# a_15_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 out vdd 0.10fF
+C1 out in 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in vdd 0.21fF
+C1 CLK inverter_cp_x1_2/in 0.31fF
+C2 CLK_d vdd 0.03fF
+C3 nCLK_d vdd 0.03fF
+C4 CLK vdd 0.36fF
+C5 CLK_d inverter_cp_x1_2/in 0.12fF
+C6 inverter_cp_x1_0/out vdd 0.28fF
+C7 inverter_cp_x1_0/out nCLK_d 0.11fF
+C8 inverter_cp_x1_0/out CLK 0.31fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 CLK vss 3.03fF
+C12 inverter_cp_x1_0/out vss 1.97fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_63_n95# 0.11fF
+C1 a_n125_n95# a_63_n95# 0.10fF
+C2 a_n33_n95# w_n263_n314# 0.08fF
+C3 a_n125_n95# a_n33_n95# 0.28fF
+C4 a_n33_n95# a_63_n95# 0.28fF
+C5 a_n125_n95# w_n263_n314# 0.11fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n129_n213# 0.02fF
+C1 a_n81_n125# a_n173_n125# 0.36fF
+C2 a_n129_n213# a_111_n125# 0.01fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_n173_n125# a_111_n125# 0.08fF
+C5 a_15_n125# a_n129_n213# 0.10fF
+C6 a_n81_n125# a_15_n125# 0.36fF
+C7 a_15_n125# a_n173_n125# 0.13fF
+C8 a_15_n125# a_111_n125# 0.36fF
+C9 a_n81_n125# a_n129_n213# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n81_n183# 0.16fF
+C1 a_n33_n95# a_n125_n95# 0.88fF
+C2 a_n33_n95# a_n81_n183# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 nQ D 0.05fF
+C1 nQ nD 0.05fF
+C2 nQ Q 0.93fF
+C3 nQ vdd 0.16fF
+C4 nQ m1_657_280# 1.41fF
+C5 D Q 0.05fF
+C6 nD Q 0.05fF
+C7 vdd Q 0.16fF
+C8 m1_657_280# CLK 0.24fF
+C9 Q m1_657_280# 0.94fF
+C10 D vss 0.53fF
+C11 m1_657_280# vss 1.88fF
+C12 nD vss 0.16fF
+C13 CLK vss 0.87fF
+C14 Q vss -0.55fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ latch_diff_0/nD Q latch_diff_1/nD latch_diff_1/m1_657_280# D latch_diff_0/D vdd
++ CLK clock_inverter_0/inverter_cp_x1_0/out nCLK
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_0/nD latch_diff_1/D 0.41fF
+C1 latch_diff_1/nD Q 0.01fF
+C2 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C3 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C4 latch_diff_1/nD vdd 0.02fF
+C5 latch_diff_0/D latch_diff_1/D 0.11fF
+C6 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C7 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
+C8 latch_diff_1/nD latch_diff_1/D 0.33fF
+C9 vdd latch_diff_1/D 0.03fF
+C10 latch_diff_1/nD nQ 0.08fF
+C11 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C12 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C13 latch_diff_0/D latch_diff_0/m1_657_280# 0.37fF
+C14 vdd latch_diff_0/nD 0.14fF
+C15 latch_diff_1/nD latch_diff_0/D 0.04fF
+C16 nQ latch_diff_1/D 0.11fF
+C17 latch_diff_0/D vdd 0.09fF
+C18 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
+C19 latch_diff_1/m1_657_280# vss 0.64fF
+C20 nCLK vss 0.83fF
+C21 Q vss -0.92fF
+C22 nQ vss 0.57fF
+C23 latch_diff_0/m1_657_280# vss 0.72fF
+C24 CLK vss 0.83fF
+C25 latch_diff_1/D vss -0.30fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 D vss 3.27fF
+C30 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 X VGND 0.15fF
+C1 A VGND 0.21fF
+C2 VPWR a_56_136# 0.57fF
+C3 B X 0.02fF
+C4 B A 0.08fF
+C5 a_56_136# VGND 0.06fF
+C6 VPWR VPB 0.04fF
+C7 B a_56_136# 0.30fF
+C8 VPWR B 0.02fF
+C9 a_56_136# X 0.26fF
+C10 a_56_136# A 0.17fF
+C11 VPWR X 0.20fF
+C12 VPWR A 0.07fF
+C13 B VGND 0.03fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 B a_63_368# 0.14fF
+C1 A B 0.10fF
+C2 VGND X 0.16fF
+C3 VGND a_63_368# 0.27fF
+C4 VPWR X 0.18fF
+C5 VPWR a_63_368# 0.29fF
+C6 a_152_368# a_63_368# 0.03fF
+C7 A VPWR 0.05fF
+C8 VGND B 0.11fF
+C9 X a_63_368# 0.33fF
+C10 B VPWR 0.01fF
+C11 A X 0.02fF
+C12 VPB VPWR 0.04fF
+C13 A a_63_368# 0.28fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5_pex_c vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/D DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 DFlipFlop_1/latch_diff_0/nD Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/D DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/D DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD Q1_shift DFlipFlop_3/latch_diff_1/nD
++ DFlipFlop_3/latch_diff_1/m1_657_280# Q1 DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C1 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C2 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C3 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C4 nQ0 vdd 0.11fF
+C5 DFlipFlop_0/D Q0 0.39fF
+C6 DFlipFlop_1/D vdd 0.25fF
+C7 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
+C8 vdd CLK_5 0.15fF
+C9 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
+C10 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C11 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C12 Q0 CLK 0.08fF
+C13 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C14 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
+C15 DFlipFlop_1/D nQ0 0.12fF
+C16 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C17 DFlipFlop_3/nQ vdd 0.02fF
+C18 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C19 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C20 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C21 DFlipFlop_2/nQ nCLK 0.09fF
+C22 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C23 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C24 CLK nQ2 0.17fF
+C25 DFlipFlop_0/D vdd 0.19fF
+C26 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C27 CLK vdd 0.41fF
+C28 Q1 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C29 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C30 Q1 DFlipFlop_0/Q 0.13fF
+C31 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C32 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C33 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C34 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C35 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C36 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C37 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
+C38 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.28fF
+C39 nQ0 CLK 0.19fF
+C40 DFlipFlop_2/nQ vdd 0.02fF
+C41 Q1 Q1_shift 0.36fF
+C42 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C43 DFlipFlop_1/D CLK 0.21fF
+C44 Q1 DFlipFlop_2/D 0.10fF
+C45 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C46 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C47 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C48 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C49 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C50 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
+C51 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C52 DFlipFlop_3/nQ CLK 0.01fF
+C53 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C54 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C55 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C56 DFlipFlop_0/Q Q0 0.21fF
+C57 nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
+C58 nCLK DFlipFlop_0/Q 0.11fF
+C59 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C60 sky130_fd_sc_hs__xor2_1_0/a_355_368# Q0 0.03fF
+C61 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
+C62 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.08fF
+C63 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C64 DFlipFlop_2/D Q0 0.25fF
+C65 DFlipFlop_2/D nCLK 0.41fF
+C66 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C67 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C68 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C69 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
+C70 DFlipFlop_0/Q nQ2 0.09fF
+C71 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C72 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C73 Q1 DFlipFlop_3/latch_diff_1/m1_657_280# 0.28fF
+C74 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
+C75 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C76 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C77 DFlipFlop_2/nQ CLK 0.13fF
+C78 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C79 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C80 Q1 Q0 9.65fF
+C81 Q1 nCLK -0.01fF
+C82 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C83 sky130_fd_sc_hs__xor2_1_0/a_355_368# vdd 0.03fF
+C84 Q1_shift vdd 0.10fF
+C85 DFlipFlop_2/D vdd 0.07fF
+C86 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C87 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C88 nCLK DFlipFlop_1/latch_diff_1/nD 0.16fF
+C89 Q1 nQ2 0.07fF
+C90 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C91 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
+C92 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
+C93 Q1 vdd 9.49fF
+C94 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C95 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C96 nCLK sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.02fF
+C97 nCLK Q0 0.20fF
+C98 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C99 Q1 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C100 DFlipFlop_3/nQ Q1_shift 0.04fF
+C101 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_1/D 0.03fF
+C102 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C103 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C104 Q1 nQ0 0.06fF
+C105 DFlipFlop_0/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C106 Q1 DFlipFlop_1/D 0.03fF
+C107 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C108 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C109 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C110 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C111 DFlipFlop_0/Q CLK 0.08fF
+C112 Q0 nQ2 0.23fF
+C113 nQ0 DFlipFlop_1/latch_diff_0/m1_657_280# 0.25fF
+C114 nCLK nQ2 0.10fF
+C115 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C116 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
+C117 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
+C118 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C119 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C120 Q1 DFlipFlop_3/nQ 0.10fF
+C121 sky130_fd_sc_hs__and2_1_1/a_143_136# CLK 0.03fF
+C122 Q0 vdd 5.33fF
+C123 nCLK vdd 0.34fF
+C124 DFlipFlop_2/D CLK 0.14fF
+C125 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C126 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C127 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C128 Q1 DFlipFlop_0/latch_diff_0/D 0.15fF
+C129 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
+C130 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C131 Q1 DFlipFlop_0/D 0.13fF
+C132 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C133 nQ0 Q0 0.33fF
+C134 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
+C135 nQ0 nCLK 0.09fF
+C136 DFlipFlop_1/D Q0 0.07fF
+C137 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C138 DFlipFlop_1/D nCLK 0.14fF
+C139 Q1 CLK -0.10fF
+C140 vdd nQ2 0.04fF
+C141 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C142 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C143 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C144 nQ0 DFlipFlop_1/latch_diff_0/nD 0.08fF
+C145 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C146 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C147 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C148 Q1 DFlipFlop_2/nQ 0.31fF
+C149 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
+C150 nQ0 nQ2 0.03fF
+C151 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C152 nCLK DFlipFlop_3/nQ 0.02fF
+C153 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C154 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C155 Q1_shift sky130_fd_sc_hs__or2_1_0/a_63_368# -0.27fF
+C156 nQ0 DFlipFlop_1/latch_diff_0/D 0.09fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C162 Q1_shift vss -1.63fF
+C163 DFlipFlop_3/nQ vss 0.52fF
+C164 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 Q1 vss 1.26fF
+C170 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C172 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C173 DFlipFlop_2/nQ vss 0.50fF
+C174 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/D vss 5.34fF
+C180 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C183 Q0 vss 0.53fF
+C184 nQ0 vss 1.84fF
+C185 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/D vss 3.72fF
+C191 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C194 nCLK vss 4.92fF
+C195 DFlipFlop_0/Q vss -0.94fF
+C196 nQ2 vss 2.05fF
+C197 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C198 CLK vss 4.85fF
+C199 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C200 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/D vss 4.04fF
+C204 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
diff --git a/xschem/example_por_tb.spice b/xschem/simulations/example_por_tb.spice
similarity index 100%
rename from xschem/example_por_tb.spice
rename to xschem/simulations/example_por_tb.spice
diff --git a/xschem/simulations/inverter_cp_x1.spice b/xschem/simulations/inverter_cp_x1.spice
new file mode 100644
index 0000000..e7fa406
--- /dev/null
+++ b/xschem/simulations/inverter_cp_x1.spice
@@ -0,0 +1,14 @@
+**.subckt inverter_cp_x1 vss in out vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/inverter_cp_x2.spice b/xschem/simulations/inverter_cp_x2.spice
new file mode 100644
index 0000000..7b8d413
--- /dev/null
+++ b/xschem/simulations/inverter_cp_x2.spice
@@ -0,0 +1,14 @@
+**.subckt inverter_cp_x2 vss in out vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/inverter_csvco.spice b/xschem/simulations/inverter_csvco.spice
new file mode 100644
index 0000000..ccb62c1
--- /dev/null
+++ b/xschem/simulations/inverter_csvco.spice
@@ -0,0 +1,16 @@
+**.subckt inverter_csvco vss in out vdd vbulkn vbulkp
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/inverter_csvco_pex_c.spice b/xschem/simulations/inverter_csvco_pex_c.spice
new file mode 100644
index 0000000..8a84801
--- /dev/null
+++ b/xschem/simulations/inverter_csvco_pex_c.spice
@@ -0,0 +1,37 @@
+* NGSPICE file created from inverter_csvco.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_20_n114# 0.20fF
+C1 w_n216_n334# a_n78_n114# 0.20fF
+C2 a_20_n114# a_n78_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco_pex_c vdd out in vss vbulkp vbulkn
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vdd vbulkp 0.04fF
+C1 in vss 0.01fF
+C2 in out 0.11fF
+C3 vbulkp out 0.08fF
+C4 in vdd 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
diff --git a/xschem/simulations/inverter_min_x2.spice b/xschem/simulations/inverter_min_x2.spice
new file mode 100644
index 0000000..4f0dc98
--- /dev/null
+++ b/xschem/simulations/inverter_min_x2.spice
@@ -0,0 +1,14 @@
+**.subckt inverter_min_x2 vss in out vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/inverter_min_x2_pex_c.spice b/xschem/simulations/inverter_min_x2_pex_c.spice
new file mode 100644
index 0000000..fef0f8e
--- /dev/null
+++ b/xschem/simulations/inverter_min_x2_pex_c.spice
@@ -0,0 +1,47 @@
+* NGSPICE file created from inverter_min_x2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK_inv2 a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n125_n42# a_63_n42# 0.05fF
+C1 a_63_n42# a_n33_n42# 0.12fF
+C2 a_n125_n42# a_n33_n42# 0.12fF
+C3 a_33_n68# a_n63_n68# 0.02fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB_inv2 VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n33_n84# a_n125_n84# 0.24fF
+C1 a_63_n84# a_n33_n84# 0.24fF
+C2 a_n125_n84# w_n263_n303# 0.10fF
+C3 a_63_n84# w_n263_n303# 0.10fF
+C4 a_33_n110# a_n63_n110# 0.02fF
+C5 a_63_n84# a_n125_n84# 0.09fF
+C6 a_n33_n84# w_n263_n303# 0.07fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2_pex_c vdd out in vss
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK_inv2
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB_inv2
+C0 out vdd 0.15fF
+C1 out in 0.30fF
+C2 vdd in 0.01fF
+C3 out vss 0.66fF
+C4 in vss 0.72fF
+C5 vdd vss 2.93fF
+.ends
+
diff --git a/xschem/simulations/inverter_min_x4.spice b/xschem/simulations/inverter_min_x4.spice
new file mode 100644
index 0000000..3c9ede2
--- /dev/null
+++ b/xschem/simulations/inverter_min_x4.spice
@@ -0,0 +1,14 @@
+**.subckt inverter_min_x4 vss in out vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/inverter_min_x4_pex_c.spice b/xschem/simulations/inverter_min_x4_pex_c.spice
new file mode 100644
index 0000000..379107d
--- /dev/null
+++ b/xschem/simulations/inverter_min_x4_pex_c.spice
@@ -0,0 +1,79 @@
+* NGSPICE file created from inverter_min_x4.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B_inv4 VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n129_n84# a_n221_n84# 0.24fF
+C1 w_n359_n303# a_n33_n84# 0.05fF
+C2 a_159_n84# a_n33_n84# 0.09fF
+C3 a_63_n84# a_n221_n84# 0.05fF
+C4 a_159_n84# w_n359_n303# 0.08fF
+C5 a_33_n110# a_n63_n110# 0.02fF
+C6 a_129_n110# a_33_n110# 0.02fF
+C7 a_63_n84# a_n129_n84# 0.09fF
+C8 a_n221_n84# a_n33_n84# 0.09fF
+C9 w_n359_n303# a_n221_n84# 0.08fF
+C10 a_159_n84# a_n221_n84# 0.04fF
+C11 a_n129_n84# a_n33_n84# 0.24fF
+C12 a_n159_n110# a_n63_n110# 0.02fF
+C13 w_n359_n303# a_n129_n84# 0.06fF
+C14 a_159_n84# a_n129_n84# 0.05fF
+C15 a_63_n84# a_n33_n84# 0.24fF
+C16 a_63_n84# w_n359_n303# 0.06fF
+C17 a_159_n84# a_63_n84# 0.24fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D_inv4 w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_63_n42# a_n33_n42# 0.12fF
+C1 a_n129_n42# a_n33_n42# 0.12fF
+C2 a_33_n68# a_n63_n68# 0.02fF
+C3 a_n129_n42# a_63_n42# 0.05fF
+C4 a_n159_n68# a_n63_n68# 0.02fF
+C5 a_159_n42# a_n221_n42# 0.02fF
+C6 a_33_n68# a_129_n68# 0.02fF
+C7 a_n221_n42# a_n33_n42# 0.05fF
+C8 a_159_n42# a_n33_n42# 0.05fF
+C9 a_n221_n42# a_63_n42# 0.03fF
+C10 a_n129_n42# a_n221_n42# 0.12fF
+C11 a_159_n42# a_63_n42# 0.12fF
+C12 a_n129_n42# a_159_n42# 0.03fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4_pex_c vdd out in vss
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B_inv4
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D_inv4
+C0 out vdd 0.62fF
+C1 in vdd 0.33fF
+C2 in out 0.67fF
+C3 in vss 1.89fF
+C4 out vss 0.66fF
+C5 vdd vss 3.87fF
+.ends
+
diff --git a/xschem/simulations/latch_diff.spice b/xschem/simulations/latch_diff.spice
new file mode 100644
index 0000000..ebb2734
--- /dev/null
+++ b/xschem/simulations/latch_diff.spice
@@ -0,0 +1,26 @@
+**.subckt latch_diff vdd vss D nQ CLK nD Q
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/latch_diff_pex_c.spice b/xschem/simulations/latch_diff_pex_c.spice
new file mode 100644
index 0000000..f7aa001
--- /dev/null
+++ b/xschem/simulations/latch_diff_pex_c.spice
@@ -0,0 +1,73 @@
+* NGSPICE file created from latch_diff.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# w_n263_n314# 0.08fF
+C1 a_n125_n95# w_n263_n314# 0.11fF
+C2 a_63_n95# w_n263_n314# 0.11fF
+C3 a_n33_n95# a_n125_n95# 0.28fF
+C4 a_63_n95# a_n33_n95# 0.28fF
+C5 a_63_n95# a_n125_n95# 0.10fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_111_n125# 0.36fF
+C1 a_n81_n125# a_15_n125# 0.36fF
+C2 a_15_n125# a_n173_n125# 0.13fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_111_n125# a_n173_n125# 0.08fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.05fF
+C7 a_15_n125# w_n311_n335# 0.05fF
+C8 a_n81_n125# w_n311_n335# 0.05fF
+C9 a_n173_n125# w_n311_n335# 0.05fF
+C10 a_n129_n213# w_n311_n335# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_n125_n95# 0.88fF
+C1 a_n33_n95# a_n81_n183# 0.10fF
+C2 a_n81_n183# a_n125_n95# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff vss vdd Q nQ D nD CLK
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 nQ m1_657_280# 1.41fF
+C1 vdd Q 0.16fF
+C2 nQ Q 0.93fF
+C3 Q nD 0.05fF
+C4 Q D 0.05fF
+C5 nQ vdd 0.16fF
+C6 CLK m1_657_280# 0.20fF
+C7 Q m1_657_280# 0.94fF
+C8 nQ nD 0.05fF
+C9 nQ D 0.05fF
+C10 D vss 0.53fF
+C11 nD vss 0.16fF
+C12 m1_657_280# vss 1.88fF
+C13 CLK vss 0.54fF
+C14 Q vss 1.08fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.30fF
+.ends
+
diff --git a/xschem/simulations/loop_filter.spice b/xschem/simulations/loop_filter.spice
new file mode 100644
index 0000000..572e21d
--- /dev/null
+++ b/xschem/simulations/loop_filter.spice
@@ -0,0 +1,43 @@
+**.subckt loop_filter in vss vc_pex
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+x1 in net1 vss res_loop_filter
+x2 vc_pex net1 vss res_loop_filter
+x3 vc_pex net1 vss res_loop_filter
+x4 vc_pex vss cap1_loop_filter
+x5 in vss cap2_loop_filter
+**.ends
+
+* expanding symbol: res_loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sch
+.subckt res_loop_filter in out vss
+*.iopin in
+*.iopin vss
+*.iopin out
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 L=22.92 mult=1 m=1
+.ends
+
+
+* expanding symbol: cap1_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
+.subckt cap1_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+.ends
+
+
+* expanding symbol: cap2_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
+.subckt cap2_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/loop_filter_pex_c.spice b/xschem/simulations/loop_filter_pex_c.spice
new file mode 100644
index 0000000..d05db7b
--- /dev/null
+++ b/xschem/simulations/loop_filter_pex_c.spice
@@ -0,0 +1,207 @@
+* NGSPICE file created from loop_filter.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C1 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C2 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C3 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C4 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C5 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C6 m3_7988_8000# m3_7988_2700# 3.39fF
+C7 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C8 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C9 m3_2669_n2600# m3_2669_2700# 3.28fF
+C10 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C11 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C12 m3_n2650_n2600# m3_n2650_n7900# 3.28fF
+C13 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C14 m3_7988_2700# m3_2669_2700# 2.73fF
+C15 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C16 m3_2669_8000# c1_n13188_n13100# 58.61fF
+C17 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C18 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C19 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C20 m3_2669_8000# m3_n2650_8000# 2.73fF
+C21 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C22 m3_7988_n2600# m3_7988_n7900# 3.39fF
+C23 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C24 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C25 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C26 m3_n2650_n2600# m3_n7969_n2600# 2.73fF
+C27 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C28 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C29 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C30 m3_7988_n13200# m3_7988_n7900# 3.39fF
+C31 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C32 m3_n2650_n2600# m3_n2650_2700# 3.28fF
+C33 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C34 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C35 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C36 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C37 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C38 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C39 m3_n2650_2700# m3_2669_2700# 2.73fF
+C40 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C41 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C42 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C43 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C44 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C45 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C46 m3_7988_n2600# m3_7988_2700# 3.39fF
+C47 m3_2669_8000# m3_7988_8000# 2.73fF
+C48 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
+C49 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C50 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C51 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
+C52 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C53 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C54 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C55 m3_2669_8000# m3_2669_2700# 3.28fF
+C56 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
+C57 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C58 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C59 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C60 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C61 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C62 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C63 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C64 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
+C1 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C2 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C3 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C4 c1_2269_n6300# c1_n2050_n6300# 1.99fF
+C5 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C6 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C7 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
+C8 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C9 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C10 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C11 m3_n2150_2200# m3_n2150_n2100# 2.63fF
+C12 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C13 c1_2269_n6300# m3_2169_n6400# 121.67fF
+C14 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C15 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C16 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C17 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C18 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 out in 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_pex_c vss in vc_pex
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 vc_pex in 0.18fF
+C1 vc_pex vss -2.18fF
+C2 res_loop_filter_2/out vss 8.49fF
+C3 in vss -35.88fF
+.ends
+
diff --git a/xschem/simulations/loop_filter_real.spice b/xschem/simulations/loop_filter_real.spice
new file mode 100644
index 0000000..16522de
--- /dev/null
+++ b/xschem/simulations/loop_filter_real.spice
@@ -0,0 +1,9 @@
+**.subckt loop_filter_real vss vctrl
+*.iopin vss
+*.iopin vctrl
+C1 net2 vss 'C1' m=1
+C2 net1 vss 'C2' m=1
+XR1 net2 vctrl __UNCONNECTED_PIN__0 sky130_fd_pr__res_xhigh_po_1p41 W=1.41 L=1 mult=1 m=1
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/loop_filter_v2.spice b/xschem/simulations/loop_filter_v2.spice
new file mode 100644
index 0000000..22d74b1
--- /dev/null
+++ b/xschem/simulations/loop_filter_v2.spice
@@ -0,0 +1,58 @@
+**.subckt loop_filter_v2 in vss vc_pex D0_cap
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+*.iopin D0_cap
+x1 in net1 vss res_loop_filter
+x2 vc_pex net1 vss res_loop_filter
+x3 vc_pex net1 vss res_loop_filter
+x4 vc_pex vss cap1_loop_filter
+x5 in vss cap2_loop_filter
+XM1 in D0_cap net2 vss sky130_fd_pr__nfet_01v8 L=0.3 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x6 net2 vss cap3_loop_filter
+**.ends
+
+* expanding symbol: res_loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sch
+.subckt res_loop_filter in out vss
+*.iopin in
+*.iopin vss
+*.iopin out
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 L=22.92 mult=1 m=1
+.ends
+
+
+* expanding symbol: cap1_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
+.subckt cap1_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+.ends
+
+
+* expanding symbol: cap2_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
+.subckt cap2_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+.ends
+
+
+* expanding symbol: cap3_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sch
+.subckt cap3_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=4 m=4
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/nor.spice b/xschem/simulations/nor.spice
new file mode 100644
index 0000000..520e5fd
--- /dev/null
+++ b/xschem/simulations/nor.spice
@@ -0,0 +1,27 @@
+**.subckt nor A B vdd out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/pfd_cp_interface.spice b/xschem/simulations/pfd_cp_interface.spice
new file mode 100644
index 0000000..5e4088b
--- /dev/null
+++ b/xschem/simulations/pfd_cp_interface.spice
@@ -0,0 +1,69 @@
+**.subckt pfd_cp_interface vdd vss QA QB nDown Down nUp Up
+*.iopin vdd
+*.iopin vss
+*.ipin QA
+*.ipin QB
+*.opin nDown
+*.opin Down
+*.opin nUp
+*.opin Up
+x5 vdd nDown nQB vss trans_gate
+x3 vdd Up nQA vss inverter_cp_x1
+x1 vdd nQB QB vss inverter_cp_x1
+x2 vdd nQA QA vss inverter_cp_x1
+x4 vdd nUp Up vss inverter_cp_x2
+x6 vdd Down nDown vss inverter_cp_x2
+**.ends
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/pfd_cp_interface_pex_c.spice b/xschem/simulations/pfd_cp_interface_pex_c.spice
new file mode 100644
index 0000000..d7391c5
--- /dev/null
+++ b/xschem/simulations/pfd_cp_interface_pex_c.spice
@@ -0,0 +1,258 @@
+* NGSPICE file created from pfd_cp_interface.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8_pci a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_63_n125# a_255_n125# 0.13fF
+C1 a_159_n125# a_255_n125# 0.36fF
+C2 a_n317_n125# a_n33_n125# 0.08fF
+C3 a_n33_n125# a_63_n125# 0.36fF
+C4 a_n129_n125# a_255_n125# 0.06fF
+C5 a_n33_n125# a_159_n125# 0.13fF
+C6 a_n33_n125# a_n225_n125# 0.13fF
+C7 a_n129_n125# a_n33_n125# 0.36fF
+C8 a_129_n151# a_225_n151# 0.02fF
+C9 a_n33_n125# a_255_n125# 0.08fF
+C10 a_n255_n151# a_n159_n151# 0.02fF
+C11 a_33_n151# a_n63_n151# 0.02fF
+C12 a_n317_n125# a_63_n125# 0.06fF
+C13 a_n159_n151# a_n63_n151# 0.02fF
+C14 a_129_n151# a_33_n151# 0.02fF
+C15 a_63_n125# a_159_n125# 0.36fF
+C16 a_n317_n125# a_n225_n125# 0.36fF
+C17 a_63_n125# a_n225_n125# 0.08fF
+C18 a_n317_n125# a_n129_n125# 0.13fF
+C19 a_n129_n125# a_63_n125# 0.13fF
+C20 a_159_n125# a_n225_n125# 0.06fF
+C21 a_n129_n125# a_159_n125# 0.08fF
+C22 a_n129_n125# a_n225_n125# 0.36fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S_pci VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n225_n125# a_n317_n125# 0.36fF
+C1 a_33_n154# a_129_n154# 0.02fF
+C2 a_n129_n125# a_159_n125# 0.08fF
+C3 a_n129_n125# w_n455_n344# 0.04fF
+C4 a_n159_n154# a_n63_n154# 0.02fF
+C5 a_n33_n125# a_n317_n125# 0.08fF
+C6 a_n129_n125# a_63_n125# 0.13fF
+C7 a_255_n125# a_159_n125# 0.36fF
+C8 a_n225_n125# a_n33_n125# 0.13fF
+C9 a_255_n125# w_n455_n344# 0.11fF
+C10 a_n255_n154# a_n159_n154# 0.02fF
+C11 a_63_n125# a_255_n125# 0.13fF
+C12 a_n129_n125# a_255_n125# 0.06fF
+C13 w_n455_n344# a_n317_n125# 0.11fF
+C14 a_n225_n125# a_159_n125# 0.06fF
+C15 a_n225_n125# w_n455_n344# 0.06fF
+C16 a_63_n125# a_n317_n125# 0.06fF
+C17 a_n129_n125# a_n317_n125# 0.13fF
+C18 a_n225_n125# a_63_n125# 0.08fF
+C19 a_159_n125# a_n33_n125# 0.13fF
+C20 w_n455_n344# a_n33_n125# 0.05fF
+C21 a_n225_n125# a_n129_n125# 0.36fF
+C22 a_63_n125# a_n33_n125# 0.36fF
+C23 a_n63_n154# a_33_n154# 0.02fF
+C24 a_n129_n125# a_n33_n125# 0.36fF
+C25 w_n455_n344# a_159_n125# 0.06fF
+C26 a_225_n154# a_129_n154# 0.02fF
+C27 a_255_n125# a_n33_n125# 0.08fF
+C28 a_63_n125# a_159_n125# 0.36fF
+C29 a_63_n125# w_n455_n344# 0.04fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2_pci in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8_pci
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S_pci
+C0 in vdd 0.04fF
+C1 in out 0.85fF
+C2 out vdd 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH_pci VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n311_n344# a_15_n125# 0.09fF
+C1 a_81_n156# a_n15_n156# 0.02fF
+C2 a_n173_n125# w_n311_n344# 0.14fF
+C3 w_n311_n344# a_111_n125# 0.14fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 w_n311_n344# a_n81_n125# 0.09fF
+C7 a_n173_n125# a_111_n125# 0.08fF
+C8 a_15_n125# a_n81_n125# 0.36fF
+C9 a_n111_n156# a_n15_n156# 0.02fF
+C10 a_n173_n125# a_n81_n125# 0.36fF
+C11 a_111_n125# a_n81_n125# 0.13fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T_pci a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_81_n151# a_n15_n151# 0.02fF
+C1 a_15_n125# a_n81_n125# 0.36fF
+C2 a_n173_n125# a_15_n125# 0.13fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n15_n151# a_n111_n151# 0.02fF
+C5 a_n173_n125# a_n81_n125# 0.36fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_n173_n125# a_111_n125# 0.08fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate_pci in out vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss out in in vdd vss vss out sky130_fd_pr__pfet_01v8_4798MH_pci
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd out in in vdd out sky130_fd_pr__nfet_01v8_BHR94T_pci
+C0 out vdd 0.55fF
+C1 out in 0.36fF
+C2 in vdd 0.69fF
+C3 out vss 0.97fF
+C4 in vss 1.35fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH_pci VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_111_n125# 0.13fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 a_n173_n125# a_111_n125# 0.08fF
+C3 a_n81_n125# w_n311_n344# 0.09fF
+C4 a_15_n125# w_n311_n344# 0.09fF
+C5 a_n173_n125# w_n311_n344# 0.14fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 a_n173_n125# a_n81_n125# 0.36fF
+C8 w_n311_n344# a_111_n125# 0.14fF
+C9 a_15_n125# a_n173_n125# 0.13fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM_pci w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_111_n125# a_n173_n125# 0.08fF
+C2 a_n81_n125# a_n173_n125# 0.36fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n81_n125# a_15_n125# 0.36fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1_pci in out vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH_pci
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM_pci
+C0 out in 0.32fF
+C1 out vdd 0.10fF
+C2 in vdd 0.02fF
+C3 out vss 0.84fF
+C4 in vss 1.06fF
+C5 vdd vss 3.13fF
+.ends
+
+.subckt pfd_cp_interface_pex_c Up vdd QA nUp Down QB vss nDown
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2_pci
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2_pci
+Xtrans_gate_0 trans_gate_0/in nDown vss vdd trans_gate_pci
+Xinverter_cp_x1_0 QB trans_gate_0/in vss vdd inverter_cp_x1_pci
+Xinverter_cp_x1_1 QA inverter_cp_x1_2/in vss vdd inverter_cp_x1_pci
+Xinverter_cp_x1_2 inverter_cp_x1_2/in Up vss vdd inverter_cp_x1_pci
+C0 nDown vdd 0.80fF
+C1 nDown Down 0.23fF
+C2 vdd inverter_cp_x1_2/in 0.40fF
+C3 Up inverter_cp_x1_2/in 0.12fF
+C4 Down vdd 0.09fF
+C5 nDown trans_gate_0/in 0.11fF
+C6 vdd Up 0.60fF
+C7 nUp vdd 0.14fF
+C8 nUp Up 0.20fF
+C9 vdd trans_gate_0/in 0.24fF
+C10 Down trans_gate_0/in 0.12fF
+C11 inverter_cp_x1_2/in vss 1.95fF
+C12 QA vss 1.17fF
+C13 trans_gate_0/in vss 1.97fF
+C14 QB vss 1.17fF
+C15 vdd vss 27.67fF
+C16 nUp vss 1.32fF
+C17 Up vss 2.60fF
+C18 Down vss 1.26fF
+C19 nDown vss 3.02fF
+.ends
+
diff --git a/xschem/simulations/res_amp_lin_prog.spice b/xschem/simulations/res_amp_lin_prog.spice
new file mode 100644
index 0000000..011077d
--- /dev/null
+++ b/xschem/simulations/res_amp_lin_prog.spice
@@ -0,0 +1,260 @@
+**.subckt res_amp_lin_prog clk outp outn avdd1p8 avss1p8 iref inp inn iref_reg0 iref_reg1 iref_reg2
+*+ outp_cap outn_cap delay_reg0 delay_reg1 delay_reg2 rst
+*.ipin clk
+*.opin outp
+*.opin outn
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin iref
+*.ipin inp
+*.ipin inn
+*.ipin iref_reg0
+*.ipin iref_reg1
+*.ipin iref_reg2
+*.opin outp_cap
+*.opin outn_cap
+*.ipin delay_reg0
+*.ipin delay_reg1
+*.ipin delay_reg2
+*.ipin rst
+x3 avdd1p8 clk avss1p8 clk_out delay_reg0 delay_reg1 delay_reg2 delay_cell_buff
+XM3 outn_cap rst avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+x4 avdd1p8 clk_out inp inn outp outn avss1p8 vctrl res_amp_lin
+XM1 outp clk_out_b outp_cap avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XM2 outn clk_out_b outn_cap avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XM5 outp_cap clk_out outp avdd1p8 sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM6 outn_cap clk_out outn avdd1p8 sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+x5 avdd1p8 clk_out_b clk_out avss1p8 inverter_min_x4
+XM4 outp_cap rst avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+x7 avdd1p8 iref avss1p8 vctrl iref_reg0 iref_reg1 iref_reg2 iref_ctrl_res_amp
+**.ends
+
+* expanding symbol: delay_cell_buff.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/delay_cell_buff.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/delay_cell_buff.sch
+.subckt delay_cell_buff avdd1p8 clk avss1p8 clk_out reg0 reg1 reg2
+*.ipin clk
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin clk_out
+*.ipin reg2
+*.ipin reg1
+*.ipin reg0
+x1 avdd1p8 reg2 avss1p8 clk3 net1 clk2 mux_2to1_logic
+x2 avdd1p8 reg2 avss1p8 clk1 net2 clk mux_2to1_logic
+x3 avdd1p8 reg1 avss1p8 net1 net3 net2 mux_2to1_logic
+x4 avdd1p8 out_mux clk_out clk avss1p8 nand_logic
+x513 avdd1p8 clk avss1p8 clk1_int buffer_no_inv_x05
+x512 avdd1p8 clk1_int avss1p8 clk1 buffer_no_inv_x05
+x511 avdd1p8 clk1 avss1p8 clk2_int buffer_no_inv_x05
+x510 avdd1p8 clk2_int avss1p8 clk2 buffer_no_inv_x05
+x59 avdd1p8 clk2 avss1p8 clk3_int buffer_no_inv_x05
+x58 avdd1p8 clk3_int avss1p8 clk3 buffer_no_inv_x05
+x57 avdd1p8 clk3 avss1p8 clk4_int buffer_no_inv_x05
+x56 avdd1p8 clk4_int avss1p8 clk4 buffer_no_inv_x05
+x55 avdd1p8 clk4 avss1p8 clk5_int buffer_no_inv_x05
+x54 avdd1p8 clk5_int avss1p8 clk5 buffer_no_inv_x05
+x53 avdd1p8 clk5 avss1p8 clk6_int buffer_no_inv_x05
+x52 avdd1p8 clk6_int avss1p8 clk6 buffer_no_inv_x05
+x51 avdd1p8 clk6 avss1p8 clk7_int buffer_no_inv_x05
+x50 avdd1p8 clk7_int avss1p8 clk7 buffer_no_inv_x05
+x5 avdd1p8 reg2 avss1p8 clk7 net4 clk6 mux_2to1_logic
+x6 avdd1p8 reg2 avss1p8 clk5 net5 clk4 mux_2to1_logic
+x7 avdd1p8 reg1 avss1p8 net4 net6 net5 mux_2to1_logic
+x8 avdd1p8 reg0 avss1p8 net6 out_mux net3 mux_2to1_logic
+.ends
+
+
+* expanding symbol: res_amp_lin.sym # of pins=8
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin.sch
+.subckt res_amp_lin avdd1p8 clk inp inn outp outn avss1p8 vctrl
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin outp
+*.opin outn
+*.ipin inn
+*.ipin inp
+*.ipin clk
+*.ipin vctrl
+XM6 int clk avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XM8 outn clk avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM9 outp clk avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM3 vp vctrl int avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=5 m=5
+XM1 outn inp vp avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=20 m=20
+XM2 outp inn vp avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=20 m=20
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: iref_ctrl_res_amp.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sch
+.subckt iref_ctrl_res_amp avdd1p8 iref avss1p8 vctrl reg0 reg1 reg2
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin reg0
+*.ipin reg1
+*.ipin reg2
+*.opin vctrl
+*.ipin iref
+XM7 iref iref net1 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6
+XM8 vctrl iref net2 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XM9 vctrl vctrl net3 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XM10 net3 avss1p8 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XM1 vctrl iref net4 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XM2 vctrl iref net5 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=4 m=4
+XM3 net4 reg0 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XM4 net5 reg1 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=4 m=4
+XM5 net2 avdd1p8 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XM6 net1 avdd1p8 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6
+XM11 vctrl iref net6 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+XM12 net6 reg2 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+.ends
+
+
+* expanding symbol: mux_2to1_logic.sym # of pins=6
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/mux_2to1_logic.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/mux_2to1_logic.sch
+.subckt mux_2to1_logic avdd1p8 sel avss1p8 DinB out DinA
+*.ipin DinB
+*.ipin DinA
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin sel
+*.opin out
+XM5 out sel_b DinB avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=2.22 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM6 DinB sel out avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.11 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out sel DinA avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=2.22 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM7 DinA sel_b out avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.11 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+x1 avdd1p8 sel_b sel avss1p8 inverter_min
+.ends
+
+
+* expanding symbol: nand_logic.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/nand_logic.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/nand_logic.sch
+.subckt nand_logic avdd1p8 in1 out in2 avss1p8
+*.ipin in1
+*.ipin in2
+*.opin out
+*.iopin avdd1p8
+*.iopin avss1p8
+XM4 out in2 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XM5 n1 in1 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in2 n1 avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 out in1 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: buffer_no_inv_x05.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sch
+.subckt buffer_no_inv_x05 avdd1p8 in avss1p8 out
+*.ipin in
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin out
+x1 avdd1p8 net1 in avss1p8 inverter_min
+x2 avdd1p8 out net1 avss1p8 inverter_min
+.ends
+
+
+* expanding symbol: inverter_min.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min.sch
+.subckt inverter_min vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/res_loop_filter.spice b/xschem/simulations/res_loop_filter.spice
new file mode 100644
index 0000000..c7e6b84
--- /dev/null
+++ b/xschem/simulations/res_loop_filter.spice
@@ -0,0 +1,8 @@
+**.subckt res_loop_filter in vss out
+*.iopin in
+*.iopin vss
+*.iopin out
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 L=22.92 mult=1 m=1
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/ring_osc_buffer.spice b/xschem/simulations/ring_osc_buffer.spice
new file mode 100644
index 0000000..f4cf772
--- /dev/null
+++ b/xschem/simulations/ring_osc_buffer.spice
@@ -0,0 +1,47 @@
+**.subckt ring_osc_buffer vdd vss in_vco out_pad out_div o1
+*.iopin vdd
+*.iopin vss
+*.ipin in_vco
+*.opin out_pad
+*.opin out_div
+*.iopin o1
+x1 vdd o1 in_vco vss inverter_min_x2
+x2 vdd out_div o1 vss inverter_min_x4
+x3 vdd out_pad out_div vss inverter_min_x4
+**.ends
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/ring_osc_buffer_pex_c.spice b/xschem/simulations/ring_osc_buffer_pex_c.spice
new file mode 100644
index 0000000..09b7e3a
--- /dev/null
+++ b/xschem/simulations/ring_osc_buffer_pex_c.spice
@@ -0,0 +1,140 @@
+* NGSPICE file created from ring_osc_buffer.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B_ro_buff VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n129_n84# a_n33_n84# 0.24fF
+C1 a_n129_n84# w_n359_n303# 0.06fF
+C2 a_63_n84# a_159_n84# 0.24fF
+C3 a_n63_n110# a_n159_n110# 0.02fF
+C4 a_n221_n84# a_159_n84# 0.04fF
+C5 a_159_n84# a_n33_n84# 0.09fF
+C6 w_n359_n303# a_159_n84# 0.08fF
+C7 a_n63_n110# a_33_n110# 0.02fF
+C8 a_n129_n84# a_159_n84# 0.05fF
+C9 a_63_n84# a_n221_n84# 0.05fF
+C10 a_129_n110# a_33_n110# 0.02fF
+C11 a_63_n84# a_n33_n84# 0.24fF
+C12 a_63_n84# w_n359_n303# 0.06fF
+C13 a_n221_n84# a_n33_n84# 0.09fF
+C14 a_n221_n84# w_n359_n303# 0.08fF
+C15 a_63_n84# a_n129_n84# 0.09fF
+C16 a_n129_n84# a_n221_n84# 0.24fF
+C17 w_n359_n303# a_n33_n84# 0.05fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D_ro_buff w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n221_n42# a_159_n42# 0.02fF
+C1 a_33_n68# a_129_n68# 0.02fF
+C2 a_n159_n68# a_n63_n68# 0.02fF
+C3 a_n221_n42# a_n129_n42# 0.12fF
+C4 a_n33_n42# a_159_n42# 0.05fF
+C5 a_63_n42# a_159_n42# 0.12fF
+C6 a_n33_n42# a_n129_n42# 0.12fF
+C7 a_63_n42# a_n129_n42# 0.05fF
+C8 a_n129_n42# a_159_n42# 0.03fF
+C9 a_n221_n42# a_n33_n42# 0.05fF
+C10 a_n221_n42# a_63_n42# 0.03fF
+C11 a_33_n68# a_n63_n68# 0.02fF
+C12 a_63_n42# a_n33_n42# 0.12fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4_ro_buff in out vss vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_ro_buff_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B_ro_buff
+Xsky130_fd_pr__nfet_01v8_DXA56D_ro_buff_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D_ro_buff
+C0 out vdd 0.62fF
+C1 in out 0.67fF
+C2 in vdd 0.33fF
+C3 in vss 1.89fF
+C4 out vss 0.66fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK_ro_buff a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_n33_n42# a_n125_n42# 0.12fF
+C2 a_63_n42# a_n125_n42# 0.05fF
+C3 a_63_n42# a_n33_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB_ro_buff VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 w_n263_n303# a_n125_n84# 0.10fF
+C1 w_n263_n303# a_n33_n84# 0.07fF
+C2 w_n263_n303# a_63_n84# 0.10fF
+C3 a_n63_n110# a_33_n110# 0.02fF
+C4 a_n33_n84# a_n125_n84# 0.24fF
+C5 a_n125_n84# a_63_n84# 0.09fF
+C6 a_n33_n84# a_63_n84# 0.24fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2_ro_buff in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_ro_buff_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK_ro_buff
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_ro_buff_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB_ro_buff
+C0 in vdd 0.01fF
+C1 out vdd 0.15fF
+C2 out in 0.30fF
+C3 out vss 0.66fF
+C4 in vss 0.72fF
+C5 vdd vss 2.93fF
+.ends
+
+.subckt ring_osc_buffer_pex_c vdd in_vco out_pad out_div vss o1
+Xinverter_min_x4_1 out_div out_pad vss vdd inverter_min_x4_ro_buff
+Xinverter_min_x4_0 o1 out_div vss vdd inverter_min_x4_ro_buff
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2_ro_buff
+C0 out_div out_pad 0.15fF
+C1 o1 vdd 0.09fF
+C2 out_div o1 0.11fF
+C3 vdd out_pad 0.10fF
+C4 out_div vdd 0.17fF
+C5 in_vco vss 0.83fF
+C6 vdd vss 14.54fF
+C7 o1 vss 2.72fF
+C8 out_div vss 3.00fF
+C9 out_pad vss 0.70fF
+.ends
+
diff --git a/xschem/simulations/tb_DFF.spice b/xschem/simulations/tb_DFF.spice
new file mode 100644
index 0000000..c72a0f5
--- /dev/null
+++ b/xschem/simulations/tb_DFF.spice
@@ -0,0 +1,57 @@
+**.subckt tb_DFF
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+Vdiv B vss PULSE(0 {vin} 0 1p 1p {1.05*Tref/2} {1.05*Tref}) DC {vin} AC 0
+C1 Up vss 10f m=1
+x2 Up vdd Q net3 net2 net4 vss net1 pfd_cp_interface_pex_c
+x1 vdd A Q B vss dff_pfd_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = 1.8
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 1f
+
+.options TEMP = 50.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/dff_pfd_pex_c.spice
+
+.ic v(net3) = 0.0
+.ic v(net4) = 0.0
+.ic v(Q) = 0.0
+
+* Data to save
+.save all
+
+* Simulation
+.control
+ tran 0.1ns 200ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ write tb_DFF_nor_tran.raw
+ plot v(A)+2 v(B)+2 v(Q)
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_PFD.spice b/xschem/simulations/tb_PFD.spice
new file mode 100644
index 0000000..7ca5a31
--- /dev/null
+++ b/xschem/simulations/tb_PFD.spice
@@ -0,0 +1,146 @@
+**.subckt tb_PFD
+x1 vss vdd QA A B QB Reset PFD
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+Vdiv B vss PULSE(0 {vin} 0 1p 1p {1.05*Tref/2} {1.05*Tref}) DC {vin} AC 0
+x2 net4 vdd QA net3 net2 QB vss net1 pfd_cp_interface_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 10f
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 400ns
+ write tb_PFD_tran.raw
+ plot v(Reset) v(QB)+2 v(QA)+4 v(A)+6 v(B)+6
+
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding symbol: DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding symbol: and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_PFD_pex.spice b/xschem/simulations/tb_PFD_pex.spice
new file mode 100644
index 0000000..76570e4
--- /dev/null
+++ b/xschem/simulations/tb_PFD_pex.spice
@@ -0,0 +1,56 @@
+**.subckt tb_PFD_pex
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vdiv B vss PULSE(0 {vin} 0 1p 1p {1.05*Tref/2} {1.05*Tref}) DC {vin} AC 0
+Vref1 A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+x2 net4 vdd QA net3 net2 QB vss net1 pfd_cp_interface_pex_c
+x1 vss vdd QA A B QB Reset PFD_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 10f
+
+.options TEMP = 100.0
+.option RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+
+* Simulation
+.control
+ tran 0.001ns 400ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ write tb_PFD_pex_tran.raw
+ plot v(Reset) v(QB)+2 v(QA)+4 v(A)+6 v(B)+6
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_buffer_salida.sch b/xschem/simulations/tb_buffer_salida.sch
new file mode 100644
index 0000000..6376927
--- /dev/null
+++ b/xschem/simulations/tb_buffer_salida.sch
@@ -0,0 +1,93 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 40 50 40 80 { lab=vss}
+N 40 -80 40 -50 { lab=vdd}
+N 600 0 680 0 { lab=out}
+N -60 -0 0 0 { lab=pll_out}
+N 40 80 40 100 { lab=vss}
+N 40 -100 40 -80 { lab=vdd}
+N -440 120 -440 170 { lab=GND}
+N -260 120 -260 170 { lab=vss}
+N -350 120 -350 170 { lab=vss}
+N -440 10 -440 60 { lab=vss}
+N -260 10 -260 60 { lab=pll_out}
+N -350 10 -350 60 { lab=vdd}
+N 680 0 680 20 { lab=out}
+N 680 80 680 100 { lab=vss}
+N 260 50 260 80 { lab=vss}
+N 260 -80 260 -50 { lab=vdd}
+N 260 80 260 100 { lab=vss}
+N 260 -100 260 -80 { lab=vdd}
+N 130 0 220 -0 { lab=in}
+N 350 0 430 -0 { lab=int1}
+N 430 -0 450 -0 { lab=int1}
+N 580 -0 600 0 { lab=out}
+N 490 -90 490 -50 { lab=vdd}
+N 260 -90 490 -90 { lab=vdd}
+N 490 50 490 80 { lab=vss}
+N 260 80 490 80 { lab=vss}
+C {lab_pin.sym} 40 -100 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 40 100 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 650 0 0 0 {name=l3 sig_type=std_logic lab=out}
+C {vsource.sym} -440 90 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -350 90 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -260 90 0 0 {name=VIN value="PULSE(0 \{vin\} 0 1p 1p \{T/2\} \{T\}) DC \{vin\} AC 0"}
+C {gnd.sym} -440 170 0 0 {name=l9 lab=GND}
+C {lab_pin.sym} -350 170 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -260 170 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 10 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -260 10 1 0 {name=l13 sig_type=std_logic lab=pll_out}
+C {lab_pin.sym} -440 10 1 0 {name=l14 sig_type=std_logic lab=vss}
+C {netlist_not_shown.sym} -400 -180 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param vdd = 1.8
+.param vss = 0
+.param vin = 1.8
+.param T = 1n
+.param C = 10f
+
+.options TEMP = 27.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/sky130-mpw2-fulgor/inverter_min/sch/simulations/inverter_min_pex_c.spice
+.include ~/sky130-mpw2-fulgor/inverter_min/sch/simulations/inverter_min_pex_c_old.spice
+
+* Data to save
+.save all
+
+
+* Simulation
+.control
+
+ reset
+
+ tran .001ns 10ns
+
+
+ write tb_buffer_salida_tran.raw
+ plot v(in) v(int1)+2 v(out)+4
+.endc
+
+.end
+"}
+C {capa.sym} 680 50 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 680 100 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 190 0 0 0 {name=l5 sig_type=std_logic lab=in}
+C {inverter_min_x4/sch/inverter_min_x4.sym} 60 0 0 0 {name=x1}
+C {lab_pin.sym} 260 -100 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 260 100 3 0 {name=l7 sig_type=std_logic lab=vss}
+C {inverter_min_x4/sch/inverter_min_x4.sym} 280 0 0 0 {name=x3}
+C {lab_pin.sym} -40 0 0 0 {name=l18 sig_type=std_logic lab=pll_out}
+C {lab_pin.sym} 400 0 0 0 {name=l19 sig_type=std_logic lab=int1}
+C {buffer_salida/sch/buffer_salida.sym} 510 0 0 0 {name=x2}
diff --git a/xschem/simulations/tb_buffer_salida.spice b/xschem/simulations/tb_buffer_salida.spice
new file mode 100644
index 0000000..53c1f51
--- /dev/null
+++ b/xschem/simulations/tb_buffer_salida.spice
@@ -0,0 +1,92 @@
+**.subckt tb_buffer_salida
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+VIN pll_out vss PULSE(0 {vin} 0 1p 1p {T/2} {T}) DC {vin} AC 0
+C1 out vss 20p m=1
+x1 vdd in pll_out vss inverter_min_x4
+x3 vdd int1 in vss inverter_min_x4
+x2 vdd out int1 vss buffer_salida
+**** begin user architecture code
+
+
+
+* Parameters
+.param vdd = 1.8
+.param vss = 0
+.param vin = 1.8
+.param T = 1n
+.param C = 10f
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+
+
+* Simulation
+.control
+
+ reset
+
+ tran .001ns 10ns
+
+
+ plot v(in) v(int1)+2 v(out)+4
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: buffer_salida.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sch
+.subckt buffer_salida vdd out in vss
+*.iopin vss
+*.ipin in
+*.iopin vdd
+*.opin out
+XM2 net1 in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 net1 in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM3 net2 net1 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM4 net2 net1 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM5 out net2 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+XM6 out net2 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_buffer_salida_pex_c.sch b/xschem/simulations/tb_buffer_salida_pex_c.sch
new file mode 100644
index 0000000..475247f
--- /dev/null
+++ b/xschem/simulations/tb_buffer_salida_pex_c.sch
@@ -0,0 +1,93 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 40 50 40 80 { lab=vss}
+N 40 -80 40 -50 { lab=vdd}
+N 600 0 680 0 { lab=out}
+N -60 -0 0 0 { lab=pll_out}
+N 40 80 40 100 { lab=vss}
+N 40 -100 40 -80 { lab=vdd}
+N -440 120 -440 170 { lab=GND}
+N -260 120 -260 170 { lab=vss}
+N -350 120 -350 170 { lab=vss}
+N -440 10 -440 60 { lab=vss}
+N -260 10 -260 60 { lab=pll_out}
+N -350 10 -350 60 { lab=vdd}
+N 680 0 680 20 { lab=out}
+N 680 80 680 100 { lab=vss}
+N 260 50 260 80 { lab=vss}
+N 260 -80 260 -50 { lab=vdd}
+N 260 80 260 100 { lab=vss}
+N 260 -100 260 -80 { lab=vdd}
+N 130 0 220 -0 { lab=in}
+N 350 0 430 -0 { lab=int1}
+N 430 -0 450 -0 { lab=int1}
+N 580 -0 600 0 { lab=out}
+N 490 -90 490 -50 { lab=vdd}
+N 260 -90 490 -90 { lab=vdd}
+N 490 50 490 80 { lab=vss}
+N 260 80 490 80 { lab=vss}
+C {lab_pin.sym} 40 -100 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 40 100 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 650 0 0 0 {name=l3 sig_type=std_logic lab=out}
+C {vsource.sym} -440 90 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -350 90 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -260 90 0 0 {name=VIN value="PULSE(0 \{vin\} 0 1p 1p \{T/2\} \{T\}) DC \{vin\} AC 0"}
+C {gnd.sym} -440 170 0 0 {name=l9 lab=GND}
+C {lab_pin.sym} -350 170 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -260 170 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 10 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -260 10 1 0 {name=l13 sig_type=std_logic lab=pll_out}
+C {lab_pin.sym} -440 10 1 0 {name=l14 sig_type=std_logic lab=vss}
+C {netlist_not_shown.sym} -400 -180 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param vdd = 1.8
+.param vss = 0
+.param vin = 1.8
+.param T = 1n
+.param C = 10f
+
+.options TEMP = 27.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/sky130-mpw2-fulgor/buffer_salida/sch/simulations/buffer_salida_pex_c.spice
+
+
+* Data to save
+.save all
+
+
+* Simulation
+.control
+
+ reset
+
+ tran .001ns 10ns
+
+
+ write tb_buffer_salida_tran.raw
+ plot v(in) v(int1)+2 v(out)+4
+.endc
+
+.end
+"}
+C {capa.sym} 680 50 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 680 100 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 190 0 0 0 {name=l5 sig_type=std_logic lab=in}
+C {inverter_min_x4/sch/inverter_min_x4.sym} 60 0 0 0 {name=x1}
+C {lab_pin.sym} 260 -100 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 260 100 3 0 {name=l7 sig_type=std_logic lab=vss}
+C {inverter_min_x4/sch/inverter_min_x4.sym} 280 0 0 0 {name=x3}
+C {lab_pin.sym} -40 0 0 0 {name=l18 sig_type=std_logic lab=pll_out}
+C {lab_pin.sym} 400 0 0 0 {name=l19 sig_type=std_logic lab=int1}
+C {buffer_salida/sch/buffer_salida_pex_c.sym} 510 0 0 0 {name=x2}
diff --git a/xschem/simulations/tb_buffer_salida_pex_c.spice b/xschem/simulations/tb_buffer_salida_pex_c.spice
new file mode 100644
index 0000000..a0ef3b8
--- /dev/null
+++ b/xschem/simulations/tb_buffer_salida_pex_c.spice
@@ -0,0 +1,65 @@
+**.subckt tb_buffer_salida_pex_c
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+VIN pll_out vss PULSE(0 {vin} 0 1p 1p {T/2} {T}) DC {vin} AC 0
+C1 out vss 20p m=1
+x1 vdd in pll_out vss inverter_min_x4
+x3 vdd int1 in vss inverter_min_x4
+x2 vdd out int1 vss buffer_salida_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param vdd = 1.8
+.param vss = 0
+.param vin = 1.8
+.param T = 1n
+.param C = 10f
+
+.options TEMP = 27.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/caravel_analog_fulgor/xschem/simulations/buffer_salida_pex_c.spice
+
+
+* Data to save
+.save all
+
+
+* Simulation
+.control
+
+ reset
+
+ tran .001ns 10ns
+
+
+ plot v(in) v(int1)+2 v(out)+4
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_cap_cp.spice b/xschem/simulations/tb_cap_cp.spice
new file mode 100644
index 0000000..67593e1
--- /dev/null
+++ b/xschem/simulations/tb_cap_cp.spice
@@ -0,0 +1,65 @@
+**.subckt tb_cap_cp
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+XM1 vss vdd vss vss sky130_fd_pr__nfet_01v8 L=0.3 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM2 vss vdd vss vss sky130_fd_pr__pfet_01v8 L=0.3 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param Cn = 0.0001fF
+.param Cp = 0.0001fF
+.param iref=100u
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+*.include ~/sky130-mpw2-fulgor/PFD/sch/simulations/PFD_pex_c.spice
+.include ~/sky130-mpw2-fulgor/pfd_cp_interface/sch/simulations/pfd_cp_interface_pex_c.spice
+
+* Data to save
+.save all @M.XM1.msky130_fd_pr__nfet_01v8[cgs] @M.XM2.msky130_fd_pr__pfet_01v8[cgs] @M.XM1.msky130_fd_pr__nfet_01v8[cgd] @M.XM2.msky130_fd_pr__pfet_01v8[cgd] @M.XM1.msky130_fd_pr__nfet_01v8[cgb] @M.XM2.msky130_fd_pr__pfet_01v8[cgb] @M.XM1.msky130_fd_pr__nfet_01v8[cgg] @M.XM2.msky130_fd_pr__pfet_01v8[cgg]
+
+
+* Simulation
+.control
+ op
+ echo .
+ echo ---- Cgs ----
+ print @M.XM1.msky130_fd_pr__nfet_01v8[cgs]
+ print @M.XM2.msky130_fd_pr__pfet_01v8[cgs]
+ echo .
+ echo ---- Cgd ----
+ print @M.XM1.msky130_fd_pr__nfet_01v8[cgd]
+ print @M.XM2.msky130_fd_pr__pfet_01v8[cgd]
+ echo .
+ echo ---- Cgs ----
+ print @M.XM1.msky130_fd_pr__nfet_01v8[cgb]
+ print @M.XM2.msky130_fd_pr__pfet_01v8[cgb]
+ echo .
+ echo ---- Cgs ----
+ print @M.XM1.msky130_fd_pr__nfet_01v8[cgg]
+ print @M.XM2.msky130_fd_pr__pfet_01v8[cgg]
+
+
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_charge_pump.spice b/xschem/simulations/tb_charge_pump.spice
new file mode 100644
index 0000000..49eab40
--- /dev/null
+++ b/xschem/simulations/tb_charge_pump.spice
@@ -0,0 +1,235 @@
+**.subckt tb_charge_pump
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref net2 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+Vdiv net1 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+C1 net3 vss 33.5p m=1
+R1 vctrl net3 2k m=1
+C2 vctrl vss 6.7p m=1
+vout cp_out vctrl 0
+x1 vss vdd net16 net17 net18 net19 Reset PFD
+x5 vdd net4 net2 vss inverter_cp_x2
+x6 vdd QA net4 vss inverter_cp_x2
+x7 vdd net5 net1 vss inverter_cp_x2
+x8 vdd QB net5 vss inverter_cp_x2
+x3 Up vdd QA nUp Down QB vss nDown pfd_cp_interface_pex_c
+x2 vdd Up nUp cp_out Down nDown vss iref_cp nswitch pswitch biasp charge_pump_pex_c
+I0 net6 vss 100u
+x4 vdd net6 vss iref_cp net7 net8 net9 net10 net11 net12 net13 net14 net15 bias_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param Cn = 0.0001fF
+.param Cp = 0.0001fF
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+*.include ~/caravel_analog_fulgor/xschem/simulations/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/charge_pump_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+.ic v(vctrl) = 0.0
+
+* Simulation
+.control
+ op
+ echo .
+ echo ---- M1 bias ----
+ print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[id]
+ print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vds]
+ print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+ print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vgs]
+ echo ---- M2 bias ----
+ print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[id]
+ print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vds]
+ print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+ print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vgs]
+ echo ---- M3 bias ----
+ print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[id]
+ print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vds]
+ print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+ print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vgs]
+ echo ---- M4 bias ----
+ print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[id]
+ print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vds]
+ print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+ print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vgs]
+ echo ---- M5 bias ----
+ print @M.X4.XM5.msky130_fd_pr__nfet_01v8[id]
+ print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vds]
+ print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vdsat]
+ print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vgs]
+ echo ---- M6 bias ----
+ print @M.X4.XM6.msky130_fd_pr__nfet_01v8[id]
+ print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vds]
+ print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vdsat]
+ print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vgs]
+ echo ---- M7 bias ----
+ print @M.X4.XM7.msky130_fd_pr__pfet_01v8[id]
+ print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vds]
+ print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vdsat]
+ print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vgs]
+ echo --- Cgs ---
+ print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgs]
+ print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgs]
+ echo --- Cgs ---
+ print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgd]
+ print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgd]
+ echo --- Cgs ---
+ print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgb]
+ print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgb]
+ echo --- Cgs ---
+ print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgg]
+ print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgg]
+
+ reset
+
+
+ tran 0.01ns 400ns
+ write tb_cp_gate_switched_tran.raw
+ plot i(v.x2.vm1) i(v.x2.vm2)
+ plot v(vctrl) v(nDown)+2 v(Down)+4 v(nUp)+6 v(Up)+8 v(QB)+10 v(QA)+12
+ plot v(pswitch) v(nswitch) xlimit 4ns 44ns
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding symbol: inverter_cp_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+
+* expanding symbol: DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding symbol: and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_csvco.spice b/xschem/simulations/tb_csvco.spice
new file mode 100644
index 0000000..51cc484
--- /dev/null
+++ b/xschem/simulations/tb_csvco.spice
@@ -0,0 +1,236 @@
+**.subckt tb_csvco
+vss vss GND {vss}
+vdd vdd vss {vdd}
+x1 vdd out_ro_n out_ro vss inverter_min_x2
+x2 vdd out_ro_buf out_ro_n vss inverter_min_x4
+C1 out_ro_buf vss 10f m=1
+Vctrl vctrl vss DC {vctrl}
+VD0 D0 vss DC {vd0}
+x3 vdd out_ro D0 vctrl vss csvco
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+ tran 0.01ns 50ns
+ meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+ meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+ let T = Tosc/10.0
+ let Tbuf = Toscbuf/10.0
+ let f = 1/T
+ let fbuf = 1/Tbuf
+ let Td = 1/(2*3*f)
+ print T Tbuf f fbuf Td
+ let i = i + 0.1
+ alterparam vctrl = $&i
+ reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+* let i = 0
+* let j = 0
+* while j < 2
+* while i < 2
+* tran 0.1ns 100us
+* meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+* meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+* let T = Tosc/10.0
+* let Tbuf = Toscbuf/10.0
+* let f = 1/T
+* let fbuf = 1/Tbuf
+* let Td = 1/(2*3*f)
+* print T Tbuf f fbuf Td
+* let i = i + 1
+* alterparam vctrl = 1.8
+* reset
+* end
+* alterparam vctrl = 0.7
+* alterparam vd0 = 0.0
+* alterparam vd1 = 1.8
+* alterparam vd2 = 1.8
+* alterpatam vd3 = 0.0
+* let i = 0
+* let j = j + 1
+* reset
+* end
+* plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+* plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+* plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+* plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+* print tran1.f tran2.f tran3.f tran4.f
+* let frange_vtun_0 = tran2.f - tran1.f
+* let frange_vtun_1 = tran4.f - tran3.f
+* print frange_vtun_0 frange_vtun_1
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: csvco.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sch
+.subckt csvco vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd vbp out out1 vctrl vss D0 csvco_branch
+x2 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x3 vdd vbp out2 out vctrl vss D0 csvco_branch
+.ends
+
+
+* expanding symbol: csvco_branch.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sch
+.subckt csvco_branch vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding symbol: inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_csvco_pex_c.spice b/xschem/simulations/tb_csvco_pex_c.spice
new file mode 100644
index 0000000..04776d5
--- /dev/null
+++ b/xschem/simulations/tb_csvco_pex_c.spice
@@ -0,0 +1,172 @@
+**.subckt tb_csvco_pex_c
+vss vss GND {vss}
+vdd vdd vss {vdd}
+x1 vdd out_ro_n out_ro vss inverter_min_x2
+x2 vdd out_ro_buf out_ro_n vss inverter_min_x4
+C1 out_ro_buf vss 10f m=1
+Vctrl vctrl vss DC {vctrl}
+VD0 D0 vss DC {vd0}
+x3 vdd out_ro vctrl vss D0 csvco_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+ tran 0.01ns 50ns
+ meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+ meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+ let T = Tosc/10.0
+ let Tbuf = Toscbuf/10.0
+ let f = 1/T
+ let fbuf = 1/Tbuf
+ let Td = 1/(2*3*f)
+ print T Tbuf f fbuf Td
+ let i = i + 0.1
+ alterparam vctrl = $&i
+ reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+* let i = 0
+* let j = 0
+* while j < 2
+* while i < 2
+* tran 0.1ns 100us
+* meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+* meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+* let T = Tosc/10.0
+* let Tbuf = Toscbuf/10.0
+* let f = 1/T
+* let fbuf = 1/Tbuf
+* let Td = 1/(2*3*f)
+* print T Tbuf f fbuf Td
+* let i = i + 1
+* alterparam vctrl = 1.8
+* reset
+* end
+* alterparam vctrl = 0.7
+* alterparam vd0 = 0.0
+* alterparam vd1 = 1.8
+* alterparam vd2 = 1.8
+* alterpatam vd3 = 0.0
+* let i = 0
+* let j = j + 1
+* reset
+* end
+* plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+* plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+* plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+* plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+* print tran1.f tran2.f tran3.f tran4.f
+* let frange_vtun_0 = tran2.f - tran1.f
+* let frange_vtun_1 = tran4.f - tran3.f
+* print frange_vtun_0 frange_vtun_1
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_csvco_v2.spice b/xschem/simulations/tb_csvco_v2.spice
new file mode 100644
index 0000000..37d8c8b
--- /dev/null
+++ b/xschem/simulations/tb_csvco_v2.spice
@@ -0,0 +1,219 @@
+**.subckt tb_csvco_v2
+vss vss GND {vss}
+vdd vdd vss {vdd}
+x1 vdd out_ro_n out_ro vss inverter_min_x2
+x2 vdd out_ro_buf out_ro_n vss inverter_min_x4
+C1 out_ro_buf vss 10f m=1
+Vctrl vctrl vss DC {vctrl}
+VD0 D0 vss DC {vd0}
+x3 vdd out_ro D0 vctrl vss csvco_v2
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_csvco_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+ tran 0.01ns 50ns
+ meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+ meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+ let T = Tosc/10.0
+ let Tbuf = Toscbuf/10.0
+ let f = 1/T
+ let fbuf = 1/Tbuf
+ let Td = 1/(2*3*f)
+ print T Tbuf f fbuf Td
+ let i = i + 0.1
+ alterparam vctrl = $&i
+ reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+* let i = 0
+* let j = 0
+* while j < 2
+* while i < 2
+* tran 0.1ns 100us
+* meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+* meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+* let T = Tosc/10.0
+* let Tbuf = Toscbuf/10.0
+* let f = 1/T
+* let fbuf = 1/Tbuf
+* let Td = 1/(2*3*f)
+* print T Tbuf f fbuf Td
+* let i = i + 1
+* alterparam vctrl = 1.8
+* reset
+* end
+* alterparam vctrl = 0.7
+* alterparam vd0 = 0.0
+* alterparam vd1 = 1.8
+* alterparam vd2 = 1.8
+* alterpatam vd3 = 0.0
+* let i = 0
+* let j = j + 1
+* reset
+* end
+* plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+* plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+* plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+* plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+* print tran1.f tran2.f tran3.f tran4.f
+* let frange_vtun_0 = tran2.f - tran1.f
+* let frange_vtun_1 = tran4.f - tran3.f
+* print frange_vtun_0 frange_vtun_1
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: csvco_v2.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_v2.sch
+.subckt csvco_v2 vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x2 vdd vbp out out1 vctrl vss D0 csvco_branch_v2
+x3 vdd vbp out1 out2 vctrl vss D0 csvco_branch_v2
+x4 vdd vbp out2 out vctrl vss D0 csvco_branch_v2
+.ends
+
+
+* expanding symbol: csvco_branch_v2.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch_v2.sch
+.subckt csvco_branch_v2 vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+C1 net1 vss 5.78f m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco_pex_c
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_csvco_v2_pex_c.spice b/xschem/simulations/tb_csvco_v2_pex_c.spice
new file mode 100644
index 0000000..69cf631
--- /dev/null
+++ b/xschem/simulations/tb_csvco_v2_pex_c.spice
@@ -0,0 +1,173 @@
+**.subckt tb_csvco_v2_pex_c
+vss vss GND {vss}
+vdd vdd vss {vdd}
+x1 vdd out_ro_n out_ro vss inverter_min_x2
+x2 vdd out_ro_buf out_ro_n vss inverter_min_x4
+C1 out_ro_buf vss 10f m=1
+Vctrl vctrl vss DC {vctrl}
+VD0 D0 vss DC {vd0}
+x3 vdd out_ro vctrl vss D0 csvco_v2_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+.options TEMP = 0.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_v2_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+ tran 0.01ns 200ns
+ meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+ meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+ let T = Tosc/10.0
+ let Tbuf = Toscbuf/10.0
+ let f = 1/T
+ let fbuf = 1/Tbuf
+ let Td = 1/(2*3*f)
+ print T Tbuf f fbuf Td
+ let i = i + 0.1
+ alterparam vctrl = $&i
+ reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+* let i = 0
+* let j = 0
+* while j < 2
+* while i < 2
+* tran 0.1ns 100us
+* meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+* meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+* let T = Tosc/10.0
+* let Tbuf = Toscbuf/10.0
+* let f = 1/T
+* let fbuf = 1/Tbuf
+* let Td = 1/(2*3*f)
+* print T Tbuf f fbuf Td
+* let i = i + 1
+* alterparam vctrl = 1.8
+* reset
+* end
+* alterparam vctrl = 0.7
+* alterparam vd0 = 0.0
+* alterparam vd1 = 1.8
+* alterparam vd2 = 1.8
+* alterpatam vd3 = 0.0
+* let i = 0
+* let j = j + 1
+* reset
+* end
+* plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+* plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+* plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+* plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+* print tran1.f tran2.f tran3.f tran4.f
+* let frange_vtun_0 = tran2.f - tran1.f
+* let frange_vtun_1 = tran4.f - tran3.f
+* print frange_vtun_0 frange_vtun_1
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_div_by_2.spice b/xschem/simulations/tb_div_by_2.spice
new file mode 100644
index 0000000..519a0ce
--- /dev/null
+++ b/xschem/simulations/tb_div_by_2.spice
@@ -0,0 +1,212 @@
+**.subckt tb_div_by_2
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref net1 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+x1 nout vss A vdd out out_div net3 net4 net5 div_by_2
+x2 vdd net2 net1 vss inverter_min_x2_pex_c
+x3 vdd A net2 vss inverter_min_x4_pex_c
+C1 nout vss 10f m=1
+C2 out vss 10f m=1
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 200ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ write tb_div_by_2_tran.raw
+ plot v(out) v(A) v(nout)+2 v(A)+2
+ plot v(out_div) v(out)
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_div_by_2_pex_c.spice b/xschem/simulations/tb_div_by_2_pex_c.spice
new file mode 100644
index 0000000..e5c61d7
--- /dev/null
+++ b/xschem/simulations/tb_div_by_2_pex_c.spice
@@ -0,0 +1,76 @@
+**.subckt tb_div_by_2_pex_c
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+x1 nout vss A vdd out net9 net10 net11 net12 div_by_2_pex_c
+Vref net2 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+x3 vdd net3 net2 vss inverter_min_x2_pex_c
+x4 vdd A net3 vss inverter_min_x4_pex_c
+x2 vdd net1 out vss nout net4 net5 net7 net8 net6 div_by_5_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(x2.q0) = 0.0
+.ic v(x2.nq0) = 0.0
+.ic v(x2.q1) = 0.0
+.ic v(x2.nq1) = 0.0
+.ic v(x2.q1_shift) = 0.0
+.ic v(x2.nq1_shift) = 0.0
+.ic v(x2.q2) = 0.0
+.ic v(x2.nq2) = 0.0
+.ic v(x2.x1.a) = 0.0
+.ic v(x2.x1.na) = 0.0
+.ic v(x2.x1.D_d) = 0.0
+.ic v(x2.x1.nD_d) = 0.0
+.ic v(out) = 0.0
+.ic v(nout) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 200ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ write tb_div_by_2_tran.raw
+ plot v(out) v(A) v(nout)+2 v(A)+2
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+**** begin user architecture code
+
+**** end user architecture code
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_div_by_5.spice b/xschem/simulations/tb_div_by_5.spice
new file mode 100644
index 0000000..630f57f
--- /dev/null
+++ b/xschem/simulations/tb_div_by_5.spice
@@ -0,0 +1,246 @@
+**.subckt tb_div_by_5
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref CLK vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+C2 clk_10 vss 10f m=1
+x2 nclk_2 vss CLK vdd clk_2 net1 net2 net3 net4 div_by_2
+x1 vdd clk_10 clk_2 vss nclk_2 net5 net6 net7 net8 net9 div_by_5
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+
+.ic v(CLK) = 0.0
+.ic v(x1.q2) = 0.0
+.ic v(x1.q1) = 0.0
+.ic v(x1.q1_shift) = 0.0
+.ic v(x1.q0) = 0.0
+.ic v(x1.x1.a) = 0.0
+.ic v(x1.x1.D_d) = 0.0
+.ic v(x1.x1.nD_d) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 600ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ write tb_div_by_5_tran.raw
+ plot v(clk_10) v(clk) v(clk_2) v(clk_2)+3 v(clk)+6
+ plot v(x1.Q2) v(x1.Q1)+2 v(clk_Q0)+4 v(x1.Q1_shift)+6 v(clk_10)+8
+
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: div_by_5.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
+.subckt div_by_5 vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+.GLOBAL GND
+**** begin user architecture code
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/and2/sky130_fd_sc_hs__and2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/xor2/sky130_fd_sc_hs__xor2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/or2/sky130_fd_sc_hs__or2_1.spice
+
+**** end user architecture code
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_div_by_5_pex_c.spice b/xschem/simulations/tb_div_by_5_pex_c.spice
new file mode 100644
index 0000000..3ab0cfe
--- /dev/null
+++ b/xschem/simulations/tb_div_by_5_pex_c.spice
@@ -0,0 +1,73 @@
+**.subckt tb_div_by_5_pex_c
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+x1 nclk_2 vss A vdd clk_2 net14 net15 net16 net17 div_by_2_pex_c
+Vref net1 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+x3 vdd net2 net1 vss inverter_min_x2_pex_c
+x4 vdd A net2 vss inverter_min_x4_pex_c
+x5 vss vdd net10 net11 clk_5 net9 net8 PFD_pex_c
+x2 vdd clk_5 clk_2_buf vss nclk_2_buf net3 net4 net6 net7 net5 div_by_5_pex_c
+x6 vdd net12 clk_2 vss inverter_min_x2_pex_c
+x7 vdd clk_2_buf net12 vss inverter_min_x4_pex_c
+x8 vdd net13 nclk_2 vss inverter_min_x2_pex_c
+x9 vdd nclk_2_buf net13 vss inverter_min_x4_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(x2.q0) = 0.0
+.ic v(x2.nq0) = 0.0
+.ic v(x2.q1) = 0.0
+.ic v(x2.nq1) = 0.0
+.ic v(x2.q1_shift) = 0.0
+.ic v(x2.nq1_shift) = 0.0
+.ic v(x2.q2) = 0.0
+.ic v(x2.nq2) = 0.0
+.ic v(x2.x1.a) = 0.0
+.ic v(x2.x1.na) = 0.0
+.ic v(x2.x1.D_d) = 0.0
+.ic v(x2.x1.nD_d) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(clk_5)
+
+* Simulation
+.control
+ tran 0.01ns 200ns
+ write tb_div_by_5_tran.raw
+ plot v(clk_2) v(A) v(nclk_2)+2 v(A)+2
+ plot v(clk_5) v(clk_2_buf) v(A)
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_inverter_csvco.spice b/xschem/simulations/tb_inverter_csvco.spice
new file mode 100644
index 0000000..039f534
--- /dev/null
+++ b/xschem/simulations/tb_inverter_csvco.spice
@@ -0,0 +1,96 @@
+**.subckt tb_inverter_csvco
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+VIN in vss PULSE(0 {vin} 0 1p 1p {T/2} {T}) DC {vin} AC 0
+C1 out vss 10f m=1
+x1 vdd out in vss vdd vss inverter_csvco
+x2 vdd out_pex_c in vss vdd vss inverter_csvco_pex_c
+C2 out_pex_c vss 10f m=1
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0
+.param vin = vdd
+.param T = 100n
+
+.options TEMP = 50.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/sky130-mpw2-fulgor/inverter_csvco/sch/simulations/inverter_csvco_pex_c.spice
+
+* Initial Conditions
+.ic v(out) = 0.0
+.ic v(out_wp) = 0.0
+.ic v(out_wp_rc) = 0.0
+.ic v(out_pex_c) = 0.0
+
+* Data to save
+.save all @M.X1.XM1.msky130_fd_pr__nfet_01v8[id] @M.X1.XM2.msky130_fd_pr__pfet_01v8[id] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgs] @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgd] @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgd] @M.X1.XM1.msky130_fd_pr__nfet_01v8[csb] @M.X1.XM2.msky130_fd_pr__pfet_01v8[csb] @M.X1.XM1.msky130_fd_pr__nfet_01v8[cdb] @M.X1.XM2.msky130_fd_pr__pfet_01v8[cdb] @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgg] @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgg] @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgb] @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgb]
+
+* Simulation
+.control
+ set filetype = ascii
+ op
+ write tb_inverter_min.raw
+ echo .
+ echo ------ OP Results -----
+ print all
+
+ reset
+
+ dc vin 0 1.8 0.01
+ setplot dc1
+ plot v(in) v(out) v(out_pex_c)
+ write tb_inverter_min_dc.raw
+
+ reset
+
+ tran 1ns 1us
+ meas tran tpLH trig v(in) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ meas tran tpHL trig v(in) val=0.9 rise=5 targ v(out) val=0.9 fall=4
+ meas tran tpLHc trig v(in) val=0.9 fall=5 targ v(out_pex_c) val=0.9 rise=5
+ meas tran tpHLc trig v(in) val=0.9 rise=5 targ v(out_pex_c) val=0.9 fall=4
+ let tp = (0.5*(tpLH + tpHL))
+ let tp_c = (0.5*(tpLHc + tpHLc))
+ echo .
+ echo ---- tp Ideal ----
+ print tpLH tpHL tp
+ echo .
+ echo ---- tp PEX C ----
+ print tpLHc tpHLc tp_c
+ write tb_inverter_tran.raw
+ plot v(in) v(out) v(out_pex_c)+2
+
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_loop_filter.spice b/xschem/simulations/tb_loop_filter.spice
new file mode 100644
index 0000000..5d54826
--- /dev/null
+++ b/xschem/simulations/tb_loop_filter.spice
@@ -0,0 +1,66 @@
+**.subckt tb_loop_filter
+VSS vss GND {vss}
+vdd vdd vss {vdd}
+Vref A vss PULSE(0 1.0 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+x1 vss A vc loop_filter
+x2 vss A vc_pex loop_filter_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 5e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param R1 = 1.6k
+.param C1 = 33.5p
+.param C2 = 6.7p
+
+.options TEMP = 50.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/caravel_analog_fulgor/xschem/simulations/loop_filter_pex_c.spice
+
+* Data to save
+
+
+* Simulation
+.control
+
+ tran 0.01ns 200ns
+ meas tran t1 when v(vc)=0.63
+ meas tran t2 when v(vc_pex)=0.63
+ let R = t1/0.5p
+ let Rpex = t2/05.p
+ print R Rpex
+ plot v(vc) v(vc_pex)
+.endc
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sch
+.subckt loop_filter vss in vc_pex
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+XC1 vc_pex vss sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+XC2 in vss sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+XR2 vc_pex net1 vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+XR1 vc_pex net1 vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+XR3 net1 in vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_top_pll_v1.spice b/xschem/simulations/tb_top_pll_v1.spice
new file mode 100644
index 0000000..6a6459b
--- /dev/null
+++ b/xschem/simulations/tb_top_pll_v1.spice
@@ -0,0 +1,751 @@
+**.subckt tb_top_pll_v1
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+VD0 D0 vss {vd0}
+I0 net1 vss {iref}
+x1 iref_cp vss vdd vco_out vctrl Up QB nUp A out_to_pad Down nDown QA D0 lf_vc vco_buffer_out biasp
++ pswitch pfd_reset nswitch out_by_2 out_to_div out_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1
++ out_buffer_div_2 n_out_buffer_div_2 div_5_Q0 n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer top_pll_v1
+x2 vdd net1 vss iref_cp net2 net3 net4 net5 net6 net7 net8 net9 net10 bias
+C1 out_to_pad vss 20p m=1
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+ let T = Tosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14
++ v(out_by_5)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+ plot v(out_by_5) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: top_pll_v1.sym # of pins=34
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1.sch
+.subckt top_pll_v1 iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
++ pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
++ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
++ n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.iopin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.iopin out_to_buffer
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin div_5_Q1
+*.iopin div_5_Q1_shift
+*.iopin div_5_nQ0
+*.iopin div_5_Q0
+*.iopin div_5_nQ2
+*.iopin out_div_by_5
+*.iopin out_to_pad
+x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD
+x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump
+x3 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface
+x4 vss vco_vctrl lf_vc loop_filter
+x5 vdd vco_out vco_D0 vco_vctrl vss csvco
+x6 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer
+x7 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift
++ div_by_5
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2
+x9 vdd out_to_pad out_to_buffer vss buffer_salida
+.ends
+
+
+* expanding symbol: bias.sym # of pins=13
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sch
+.subckt bias vdd iref vss iref_0 iref_1 iref_2 iref_3 iref_4 iref_5 iref_6 iref_7 iref_8 iref_9
+*.iopin iref
+*.iopin vdd
+*.opin iref_0
+*.opin iref_1
+*.opin iref_2
+*.opin iref_3
+*.opin iref_4
+*.opin iref_5
+*.opin iref_6
+*.opin iref_7
+*.opin iref_8
+*.opin iref_9
+XM1 iref iref vbp1 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM2 vbp1 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM3 net1 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM4 iref_0 iref net1 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM5 net2 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM6 iref_1 iref net2 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM7 net3 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM8 iref_2 iref net3 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM9 net4 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM10 iref_3 iref net4 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM11 net5 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM12 iref_4 iref net5 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM13 net6 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM14 iref_5 iref net6 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM15 net7 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM16 iref_6 iref net7 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM17 net8 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM18 iref_7 iref net8 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM19 net9 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM20 iref_8 iref net9 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM21 net10 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM22 iref_9 iref net10 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+.ends
+
+
+* expanding symbol: PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding symbol: charge_pump.sym # of pins=11
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sch
+.subckt charge_pump vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
+*.iopin vss
+*.iopin vdd
+*.ipin Down
+*.ipin nUp
+*.ipin Up
+*.ipin nDown
+*.opin out
+*.iopin nswitch
+*.iopin pswitch
+*.ipin iref
+*.iopin biasp
+XM1 out pswitch vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM2 out nswitch vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM3 pswitch nUp biasp vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 pswitch Up vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM5 nswitch Down iref vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM6 nswitch nDown vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM7 pswitch nUp pswitch vdd sky130_fd_pr__pfet_01v8 L=2 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM8 nswitch Down nswitch vss sky130_fd_pr__nfet_01v8 L=1.5 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM9 iref iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM10 biasp iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM11 biasp biasp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+.ends
+
+
+* expanding symbol: pfd_cp_interface.sym # of pins=8
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
+.subckt pfd_cp_interface Up vdd QA nUp Down QB vss nDown
+*.iopin vdd
+*.iopin vss
+*.ipin QA
+*.ipin QB
+*.opin nDown
+*.opin Down
+*.opin nUp
+*.opin Up
+x5 vdd nDown nQB vss trans_gate
+x3 vdd Up nQA vss inverter_cp_x1
+x1 vdd nQB QB vss inverter_cp_x1
+x2 vdd nQA QA vss inverter_cp_x1
+x4 vdd nUp Up vss inverter_cp_x2
+x6 vdd Down nDown vss inverter_cp_x2
+.ends
+
+
+* expanding symbol: loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sch
+.subckt loop_filter vss in vc_pex
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+x1 in net1 vss res_loop_filter
+x2 vc_pex net1 vss res_loop_filter
+x3 vc_pex net1 vss res_loop_filter
+x4 vc_pex vss cap1_loop_filter
+x5 in vss cap2_loop_filter
+.ends
+
+
+* expanding symbol: csvco.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sch
+.subckt csvco vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd vbp out out1 vctrl vss D0 csvco_branch
+x2 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x3 vdd vbp out2 out vctrl vss D0 csvco_branch
+.ends
+
+
+* expanding symbol: ring_osc_buffer.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
+.subckt ring_osc_buffer vdd in_vco out_pad out_div vss o1
+*.iopin vdd
+*.iopin vss
+*.ipin in_vco
+*.opin out_pad
+*.opin out_div
+*.iopin o1
+x1 vdd o1 in_vco vss inverter_min_x2
+x2 vdd out_div o1 vss inverter_min_x4
+x3 vdd out_pad out_div vss inverter_min_x4
+.ends
+
+
+* expanding symbol: div_by_5.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
+.subckt div_by_5 vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: buffer_salida.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sch
+.subckt buffer_salida vdd out in vss
+*.iopin vss
+*.ipin in
+*.iopin vdd
+*.opin out
+XM2 net1 in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 net1 in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM3 net2 net1 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM4 net2 net1 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM5 out net2 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+XM6 out net2 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+.ends
+
+
+* expanding symbol: DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding symbol: and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+
+* expanding symbol: res_loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sch
+.subckt res_loop_filter in out vss
+*.iopin in
+*.iopin vss
+*.iopin out
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 L=22.92 mult=1 m=1
+.ends
+
+
+* expanding symbol: cap1_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
+.subckt cap1_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+.ends
+
+
+* expanding symbol: cap2_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
+.subckt cap2_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+.ends
+
+
+* expanding symbol: csvco_branch.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sch
+.subckt csvco_branch vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+.GLOBAL GND
+**** begin user architecture code
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/and2/sky130_fd_sc_hs__and2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/xor2/sky130_fd_sc_hs__xor2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/or2/sky130_fd_sc_hs__or2_1.spice
+
+**** end user architecture code
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_top_pll_v1_pex_c.spice b/xschem/simulations/tb_top_pll_v1_pex_c.spice
new file mode 100644
index 0000000..1353856
--- /dev/null
+++ b/xschem/simulations/tb_top_pll_v1_pex_c.spice
@@ -0,0 +1,86 @@
+**.subckt tb_top_pll_v1_pex_c
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+VD0 D0 vss {vd0}
+I0 net1 vss {iref}
+x1 iref_cp vss vdd vco_out vctrl Up QB nUp A out_to_pad Down nDown QA D0 lf_vc vco_buffer_out biasp
++ pswitch pfd_reset nswitch out_by_2 out_to_div out_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1
++ out_buffer_div_2 n_out_buffer_div_2 div_5_Q0 n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer top_pll_v1_pex_c
+x9 vdd net1 vss iref_cp net2 net3 net4 net5 net6 net7 net8 net9 net10 bias_pex_c
+C1 out_to_pad vss 10p m=1
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SF
+.include ~/caravel_analog_fulgor/xschem/simulations/top_pll_v1_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_div) val=0.9 fall=1005 targ v(out_to_div) val=0.9 fall=1105
+ let T = Tosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14
++ v(out_by_5)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 (out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+ plot v(out_by_5) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_top_pll_v1_pex_no_integration.spice b/xschem/simulations/tb_top_pll_v1_pex_no_integration.spice
new file mode 100644
index 0000000..8f0648b
--- /dev/null
+++ b/xschem/simulations/tb_top_pll_v1_pex_no_integration.spice
@@ -0,0 +1,153 @@
+**.subckt tb_top_pll_v1_pex_no_integration
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+VD0 D0 vss {vd0}
+I0 net1 vss {iref}
+x2 vdd net1 vss iref_cp net2 net3 net4 net5 net6 net7 net8 net9 net10 bias_pex_c
+x1 iref_cp vss vdd vco_out vctrl Up QB nUp A out_to_pad Down nDown QA D0 lf_vc vco_buffer_out biasp
++ pswitch pfd_reset nswitch out_by_2 out_to_div out_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1
++ out_buffer_div_2 n_out_buffer_div_2 div_5_Q0 n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer
++ top_pll_v1_pex_no_integration
+C1 out_to_pad vss 20p m=1
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/charge_pump_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/loop_filter_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/ring_osc_buffer_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/buffer_salida_pex_c.spice
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+ let T = Tosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14
++ v(out_by_5)+16
+ plot v(out_to_pad)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+ plot v(out_by_5) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: top_pll_v1_pex_no_integration.sym # of pins=34
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1_pex_no_integration.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1_pex_no_integration.sch
+.subckt top_pll_v1_pex_no_integration iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref
++ out_to_pad Down nDown pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2
++ out_to_div out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2
++ div_5_Q0 n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.iopin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.opin out_to_pad
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin div_5_Q1
+*.iopin div_5_Q1_shift
+*.iopin div_5_nQ0
+*.iopin div_5_Q0
+*.iopin div_5_nQ2
+*.iopin out_div_by_5
+*.iopin out_to_buffer
+x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD_pex_c
+x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump_pex_c
+x3 vdd vco_out vco_vctrl vss vco_D0 csvco_pex_c
+x5 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift
++ div_by_5_pex_c
+x6 vss vco_vctrl lf_vc loop_filter_pex_c
+x7 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface_pex_c
+x8 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer_pex_c
+x4 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2_pex_c
+x9 vdd out_to_pad out_to_buffer vss buffer_salida_pex_c
+.ends
+
+.GLOBAL GND
+**** begin user architecture code
+
+**** end user architecture code
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_top_pll_v2_pex_c.spice b/xschem/simulations/tb_top_pll_v2_pex_c.spice
new file mode 100644
index 0000000..9d1290e
--- /dev/null
+++ b/xschem/simulations/tb_top_pll_v2_pex_c.spice
@@ -0,0 +1,88 @@
+**.subckt tb_top_pll_v2_pex_c
+VSS vss GND {vss}
+VDD vdd vss {vdd}
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0
+VD0 D0_vco vss {vd0}
+I0 net1 vss {iref}
+x9 vdd net1 vss iref_cp net2 net3 net4 net5 net6 net7 net8 net9 net10 bias_pex_c
+C1 out_to_pad vss 10p m=1
+x1 iref_cp vss vdd vco_out vctrl Up QB nUp A out_to_pad Down nDown QA D0_vco lf_vc vco_buffer_out
++ biasp pswitch pfd_reset nswitch out_by_2 out_to_div out_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1
++ out_buffer_div_2 n_out_buffer_div_2 div_5_Q0 n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer D0_cap top_pll_v2_pex_c
+VD1 D0_cap vss {vd1}
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param vd1 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.include ~/caravel_analog_fulgor/xschem/simulations/top_pll_v2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_div) val=0.9 fall=1005 targ v(out_to_div) val=0.9 fall=1105
+ let T = Tosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14
++ v(out_by_5)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 (out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+ plot v(out_by_5) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_vco.spice b/xschem/simulations/tb_vco.spice
new file mode 100644
index 0000000..b0f1ef8
--- /dev/null
+++ b/xschem/simulations/tb_vco.spice
@@ -0,0 +1,227 @@
+**.subckt tb_vco vctrl D0 D1 D2 D3
+*.ipin vctrl
+*.ipin D0
+*.ipin D1
+*.ipin D2
+*.ipin D3
+vss vss GND {vss}
+vdd vdd vss {vdd}
+C1 out vss 10f m=1
+Vctrl vctrl vss DC {vctrl}
+x5 vdd out out4 vss inverter_min_x2
+x4 vdd out4 out3 vss inverter_min_x2
+XM1 net2 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM4 net2 vdd vss vss sky130_fd_pr__nfet_01v8 L=0.6 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net1 vss vdd vdd sky130_fd_pr__pfet_01v8 L=0.6 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net1 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+C4 net7 vss 1f m=1
+XM15 out1 D0 net7 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+C2 net8 vss 2f m=1
+C3 net9 vss 4f m=1
+C5 net10 vss 8f m=1
+C6 net11 vss 1f m=1
+C7 net12 vss 2f m=1
+C8 net13 vss 4f m=1
+C9 net14 vss 8f m=1
+C10 net15 vss 1f m=1
+C11 net16 vss 2f m=1
+C12 net17 vss 4f m=1
+C13 net18 vss 8f m=1
+VD0 D0 vss DC {vd0}
+VD1 D1 vss DC {vd1}
+VD2 D2 vss DC {vd2}
+VD3 D3 vss DC {vd3}
+XM9 net5 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM12 net6 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM2 net3 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM5 net4 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM16 out1 D1 net8 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 out1 D2 net9 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 out1 D3 net10 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 out2 D0 net11 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 out2 D1 net12 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 out2 D2 net13 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 out2 D3 net14 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 out3 D0 net15 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 out3 D1 net16 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 out3 D2 net17 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 out3 D3 net18 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net5 vss vdd vdd sky130_fd_pr__pfet_01v8 L=0.6 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net6 vss vdd vdd sky130_fd_pr__pfet_01v8 L=0.6 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 net1 out1 out3 net2 vdd vss inverter_csvco_pex_c
+x2 net5 out2 out1 net3 vdd vss inverter_csvco_pex_c
+x3 net6 out3 out2 net4 vdd vss inverter_csvco_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vctrl = 1.0
+.param vd0 = 0.0
+.param vd1 = 0.0
+.param vd2 = 0.0
+.param vd3 = 0.0
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/sky130-mpw2-fulgor/inverter_csvco/sch/simulations/inverter_csvco_pex_c.spice
+
+* Data to save
+.save all @M.XM7.msky130_fd_pr__pfet_01v8[id] @M.XM7.msky130_fd_pr__pfet_01v8[vds] @M.XM7.msky130_fd_pr__pfet_01v8[vdsat] @M.XM10.msky130_fd_pr__pfet_01v8[id] @M.XM10.msky130_fd_pr__pfet_01v8[vds] @M.XM10.msky130_fd_pr__pfet_01v8[vdsat] @M.XM13.msky130_fd_pr__pfet_01v8[id] @M.XM13.msky130_fd_pr__pfet_01v8[vds] @M.XM13.msky130_fd_pr__pfet_01v8[vdsat] @M.XM1.msky130_fd_pr__nfet_01v8[id] @M.XM1.msky130_fd_pr__nfet_01v8[vds] @M.XM1.msky130_fd_pr__nfet_01v8[vdsat] @M.XM4.msky130_fd_pr__nfet_01v8[id] @M.XM4.msky130_fd_pr__nfet_01v8[vds] @M.XM4.msky130_fd_pr__nfet_01v8[vdsat] @M.XM14.msky130_fd_pr__nfet_01v8[id] @M.XM14.msky130_fd_pr__pfet_01v8[vds] @M.XM14.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM1.msky130_fd_pr__nfet_01v8[id] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[id] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat]
+
+.ic v(out1) = vdd/2
+.ic v(out2) = vdd/2
+.ic v(out3) = vdd/2
+.ic v(out4) = 0.0
+.ic v(out) = 0.0
+
+* Simulation
+.control
+op
+write tb_vco.raw
+
+echo ----- M1 -----
+print @M.XM1.msky130_fd_pr__nfet_01v8[id]
+print @M.XM1.msky130_fd_pr__nfet_01v8[vds]
+print @M.XM1.msky130_fd_pr__nfet_01v8[vdsat]
+
+echo ----- M4 -----
+print @M.XM4.msky130_fd_pr__nfet_01v8[id]
+print @M.XM4.msky130_fd_pr__nfet_01v8[vds]
+print @M.XM4.msky130_fd_pr__nfet_01v8[vdsat]
+
+echo ----- M14 -----
+print @M.XM14.msky130_fd_pr__nfet_01v8[id]
+print @M.XM14.msky130_fd_pr__nfet_01v8[vds]
+print @M.XM14.msky130_fd_pr__nfet_01v8[vdsat]
+
+echo ----- M7 -----
+print @M.XM7.msky130_fd_pr__pfet_01v8[id]
+print @M.XM7.msky130_fd_pr__pfet_01v8[vds]
+print @M.XM7.msky130_fd_pr__pfet_01v8[vdsat]
+
+echo ----- M10 -----
+print @M.XM10.msky130_fd_pr__pfet_01v8[id]
+print @M.XM10.msky130_fd_pr__pfet_01v8[vds]
+print @M.XM10.msky130_fd_pr__pfet_01v8[vdsat]
+
+echo ----- M13 -----
+print @M.XM13.msky130_fd_pr__pfet_01v8[id]
+print @M.XM13.msky130_fd_pr__pfet_01v8[vds]
+print @M.XM13.msky130_fd_pr__pfet_01v8[vdsat]
+
+echo ----- Inverter NMOS -----
+print @M.X1.XM1.msky130_fd_pr__nfet_01v8[id]
+print @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds]
+print @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat]
+
+echo ----- Inverter PMOS -----
+print @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
+print @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
+print @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat]
+
+alterparam vctrl = 0.0
+reset
+
+let i = 0
+while i <= 1.9
+ tran 0.01ns 50ns
+ meas tran To trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ let T = To/10.0
+ let f = 1/T
+ echo .
+ echo --- VCO ----
+ print T f
+ let i = i + 0.3
+ alterparam vctrl = $&i
+ reset
+end
+*plot v(tran1.out) v(tran1.vctrl)
+*plot v(tran2.out) v(tran2.vctrl)
+*plot v(tran3.out) v(tran3.vctrl)
+*plot v(tran4.out) v(tran4.vctrl)
+*plot v(tran5.out) v(tran5.vctrl)
+*plot v(tran6.out) v(tran6.vctrl)
+*plot v(tran7.out) v(tran7.vctrl)
+print tran7.f tran6.f tran5.f tran4.f tran3.f tran2.f tran1.f
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: inverter_min_x2/sch/inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/threshold_test_tb.spice b/xschem/simulations/threshold_test_tb.spice
similarity index 100%
rename from xschem/threshold_test_tb.spice
rename to xschem/simulations/threshold_test_tb.spice
diff --git a/xschem/simulations/top_pll_v1.spice b/xschem/simulations/top_pll_v1.spice
new file mode 100644
index 0000000..669a492
--- /dev/null
+++ b/xschem/simulations/top_pll_v1.spice
@@ -0,0 +1,573 @@
+**.subckt top_pll_v1 vdd vss in_ref pfd_QA pfd_QB Up nUp Down nDown pfd_reset cp_nswitch cp_pswitch
+*+ cp_biasp iref_cp lf_vc vco_D0 vco_vctrl vco_out out_first_buffer out_to_buffer out_to_div out_by_2
+*+ n_out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2 div_5_Q1 div_5_Q1_shift div_5_nQ0
+*+ div_5_Q0 div_5_nQ2 out_div_by_5 out_to_pad
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.iopin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.iopin out_to_buffer
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin div_5_Q1
+*.iopin div_5_Q1_shift
+*.iopin div_5_nQ0
+*.iopin div_5_Q0
+*.iopin div_5_nQ2
+*.iopin out_div_by_5
+*.iopin out_to_pad
+x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD
+x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump
+x3 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface
+x4 vss vco_vctrl lf_vc loop_filter
+x5 vdd vco_out vco_D0 vco_vctrl vss csvco
+x6 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer
+x7 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift
++ div_by_5
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2
+x9 vdd out_to_pad out_to_buffer vss buffer_salida
+**.ends
+
+* expanding symbol: PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding symbol: charge_pump.sym # of pins=11
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sch
+.subckt charge_pump vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
+*.iopin vss
+*.iopin vdd
+*.ipin Down
+*.ipin nUp
+*.ipin Up
+*.ipin nDown
+*.opin out
+*.iopin nswitch
+*.iopin pswitch
+*.ipin iref
+*.iopin biasp
+XM1 out pswitch vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM2 out nswitch vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM3 pswitch nUp biasp vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 pswitch Up vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM5 nswitch Down iref vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM6 nswitch nDown vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM7 pswitch nUp pswitch vdd sky130_fd_pr__pfet_01v8 L=2 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM8 nswitch Down nswitch vss sky130_fd_pr__nfet_01v8 L=1.5 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM9 iref iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM10 biasp iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM11 biasp biasp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+.ends
+
+
+* expanding symbol: pfd_cp_interface.sym # of pins=8
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
+.subckt pfd_cp_interface Up vdd QA nUp Down QB vss nDown
+*.iopin vdd
+*.iopin vss
+*.ipin QA
+*.ipin QB
+*.opin nDown
+*.opin Down
+*.opin nUp
+*.opin Up
+x5 vdd nDown nQB vss trans_gate
+x3 vdd Up nQA vss inverter_cp_x1
+x1 vdd nQB QB vss inverter_cp_x1
+x2 vdd nQA QA vss inverter_cp_x1
+x4 vdd nUp Up vss inverter_cp_x2
+x6 vdd Down nDown vss inverter_cp_x2
+.ends
+
+
+* expanding symbol: loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sch
+.subckt loop_filter vss in vc_pex
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+x1 in net1 vss res_loop_filter
+x2 vc_pex net1 vss res_loop_filter
+x3 vc_pex net1 vss res_loop_filter
+x4 vc_pex vss cap1_loop_filter
+x5 in vss cap2_loop_filter
+.ends
+
+
+* expanding symbol: csvco.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sch
+.subckt csvco vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd vbp out out1 vctrl vss D0 csvco_branch
+x2 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x3 vdd vbp out2 out vctrl vss D0 csvco_branch
+.ends
+
+
+* expanding symbol: ring_osc_buffer.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
+.subckt ring_osc_buffer vdd in_vco out_pad out_div vss o1
+*.iopin vdd
+*.iopin vss
+*.ipin in_vco
+*.opin out_pad
+*.opin out_div
+*.iopin o1
+x1 vdd o1 in_vco vss inverter_min_x2
+x2 vdd out_div o1 vss inverter_min_x4
+x3 vdd out_pad out_div vss inverter_min_x4
+.ends
+
+
+* expanding symbol: div_by_5.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
+.subckt div_by_5 vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: buffer_salida.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sch
+.subckt buffer_salida vdd out in vss
+*.iopin vss
+*.ipin in
+*.iopin vdd
+*.opin out
+XM2 net1 in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 net1 in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM3 net2 net1 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM4 net2 net1 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM5 out net2 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+XM6 out net2 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+.ends
+
+
+* expanding symbol: DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding symbol: and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+
+* expanding symbol: res_loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sch
+.subckt res_loop_filter in out vss
+*.iopin in
+*.iopin vss
+*.iopin out
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 L=22.92 mult=1 m=1
+.ends
+
+
+* expanding symbol: cap1_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
+.subckt cap1_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+.ends
+
+
+* expanding symbol: cap2_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
+.subckt cap2_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+.ends
+
+
+* expanding symbol: csvco_branch.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sch
+.subckt csvco_branch vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/top_pll_v1_pex_c.spice b/xschem/simulations/top_pll_v1_pex_c.spice
new file mode 100644
index 0000000..17a76d5
--- /dev/null
+++ b/xschem/simulations/top_pll_v1_pex_c.spice
@@ -0,0 +1,2883 @@
+* NGSPICE file created from top_pll_v1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_2669_8000# m3_n2650_8000# 2.73fF
+C1 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C2 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C3 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C4 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C5 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C6 m3_n2650_2700# m3_2669_2700# 2.73fF
+C7 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C8 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C9 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C10 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C11 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C12 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C13 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C14 m3_2669_n2600# m3_2669_2700# 3.28fF
+C15 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C16 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C17 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C18 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C19 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C20 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C21 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C22 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C23 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C24 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C25 m3_2669_n13200# m3_7988_n13200# 2.73fF
+C26 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
+C27 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C28 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C29 m3_2669_8000# m3_2669_2700# 3.28fF
+C30 m3_7988_2700# m3_7988_n2600# 3.39fF
+C31 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C32 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C33 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C34 m3_7988_2700# m3_2669_2700# 2.73fF
+C35 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C36 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C37 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C38 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C39 m3_2669_n2600# c1_n13188_n13100# 58.86fF
+C40 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C41 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C42 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C43 m3_2669_8000# m3_7988_8000# 2.73fF
+C44 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C45 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C46 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C47 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C48 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C49 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C50 m3_7988_2700# m3_7988_8000# 3.39fF
+C51 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C52 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C53 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C54 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C55 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C56 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C57 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C58 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C59 m3_2669_n2600# m3_n2650_n2600# 2.73fF
+C60 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C61 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C62 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C63 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C64 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C1 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C2 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C3 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C4 c1_n6369_n6300# m3_n6469_2200# 38.10fF
+C5 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C6 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C7 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C8 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C9 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C10 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
+C11 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
+C12 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C13 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C14 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C15 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C16 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C17 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C18 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 vc_pex vss -38.13fF
+C2 res_loop_filter_2/out vss 8.49fF
+C3 in vss -18.79fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 w_n2457_n634# a_2261_n486# 0.02fF
+C1 w_n2457_n634# a_n29_n486# 0.02fF
+C2 w_n2457_n634# a_n1403_n486# 0.02fF
+C3 w_n2457_n634# a_1345_n486# 0.02fF
+C4 w_n2457_n634# a_1803_n486# 0.02fF
+C5 w_n2457_n634# a_n2319_n486# 0.02fF
+C6 w_n2457_n634# a_n945_n486# 0.02fF
+C7 w_n2457_n634# a_n1861_n486# 0.02fF
+C8 w_n2457_n634# a_n487_n486# 0.02fF
+C9 w_n2457_n634# a_887_n486# 0.02fF
+C10 w_n2457_n634# a_429_n486# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n945_n75# a_n753_n75# 0.08fF
+C1 a_n849_n75# a_n561_n75# 0.05fF
+C2 a_111_n75# a_399_n75# 0.05fF
+C3 a_n1229_n75# a_n1041_n75# 0.08fF
+C4 a_n81_n75# a_111_n75# 0.08fF
+C5 a_n1137_n75# a_n753_n75# 0.03fF
+C6 a_303_n75# a_591_n75# 0.05fF
+C7 a_591_n75# a_495_n75# 0.22fF
+C8 a_303_n75# a_495_n75# 0.08fF
+C9 a_399_n75# a_207_n75# 0.08fF
+C10 a_n81_n75# a_n177_n75# 0.22fF
+C11 a_n273_n75# a_n465_n75# 0.08fF
+C12 a_n273_n75# a_15_n75# 0.05fF
+C13 a_n81_n75# a_207_n75# 0.05fF
+C14 a_975_n75# a_1071_n75# 0.22fF
+C15 a_n1041_n75# a_n753_n75# 0.05fF
+C16 a_n945_n75# a_n1137_n75# 0.08fF
+C17 a_975_n75# a_879_n75# 0.22fF
+C18 a_15_n75# a_399_n75# 0.03fF
+C19 a_n81_n75# a_n465_n75# 0.03fF
+C20 a_n177_n75# a_n369_n75# 0.08fF
+C21 a_n657_n75# a_n753_n75# 0.22fF
+C22 a_n81_n75# a_15_n75# 0.22fF
+C23 a_n657_n75# a_n465_n75# 0.08fF
+C24 a_n849_n75# a_n1229_n75# 0.03fF
+C25 a_975_n75# a_687_n75# 0.05fF
+C26 a_975_n75# a_1167_n75# 0.08fF
+C27 a_n177_n75# a_n561_n75# 0.03fF
+C28 a_111_n75# a_303_n75# 0.08fF
+C29 a_111_n75# a_495_n75# 0.03fF
+C30 a_n1041_n75# a_n945_n75# 0.22fF
+C31 a_n369_n75# a_n753_n75# 0.03fF
+C32 a_n369_n75# a_n465_n75# 0.22fF
+C33 a_879_n75# a_1071_n75# 0.08fF
+C34 a_15_n75# a_n369_n75# 0.03fF
+C35 a_n945_n75# a_n657_n75# 0.05fF
+C36 a_591_n75# a_207_n75# 0.03fF
+C37 a_n1041_n75# a_n1137_n75# 0.22fF
+C38 a_303_n75# a_207_n75# 0.22fF
+C39 a_495_n75# a_207_n75# 0.05fF
+C40 a_975_n75# a_783_n75# 0.08fF
+C41 a_n561_n75# a_n753_n75# 0.08fF
+C42 a_n849_n75# a_n753_n75# 0.22fF
+C43 a_n561_n75# a_n465_n75# 0.22fF
+C44 a_n81_n75# a_n273_n75# 0.08fF
+C45 a_687_n75# a_1071_n75# 0.03fF
+C46 a_n849_n75# a_n465_n75# 0.03fF
+C47 a_1167_n75# a_1071_n75# 0.22fF
+C48 a_n273_n75# a_n657_n75# 0.03fF
+C49 a_15_n75# a_303_n75# 0.05fF
+C50 a_687_n75# a_879_n75# 0.08fF
+C51 a_975_n75# a_591_n75# 0.03fF
+C52 a_1167_n75# a_879_n75# 0.05fF
+C53 a_399_n75# a_687_n75# 0.05fF
+C54 a_n945_n75# a_n561_n75# 0.03fF
+C55 a_n849_n75# a_n945_n75# 0.22fF
+C56 a_n1041_n75# a_n657_n75# 0.03fF
+C57 a_1071_n75# a_783_n75# 0.05fF
+C58 a_n273_n75# a_n369_n75# 0.22fF
+C59 a_111_n75# a_n177_n75# 0.05fF
+C60 a_111_n75# a_207_n75# 0.22fF
+C61 a_n849_n75# a_n1137_n75# 0.05fF
+C62 a_879_n75# a_783_n75# 0.22fF
+C63 a_n273_n75# a_n561_n75# 0.05fF
+C64 a_n177_n75# a_207_n75# 0.03fF
+C65 a_399_n75# a_783_n75# 0.03fF
+C66 a_n81_n75# a_n369_n75# 0.05fF
+C67 a_687_n75# a_783_n75# 0.22fF
+C68 a_111_n75# a_15_n75# 0.22fF
+C69 a_n657_n75# a_n369_n75# 0.05fF
+C70 a_1167_n75# a_783_n75# 0.03fF
+C71 a_591_n75# a_879_n75# 0.05fF
+C72 a_n849_n75# a_n1041_n75# 0.08fF
+C73 a_879_n75# a_495_n75# 0.03fF
+C74 a_n177_n75# a_n465_n75# 0.05fF
+C75 a_15_n75# a_n177_n75# 0.08fF
+C76 a_399_n75# a_591_n75# 0.08fF
+C77 a_303_n75# a_399_n75# 0.22fF
+C78 a_15_n75# a_207_n75# 0.08fF
+C79 a_n657_n75# a_n561_n75# 0.22fF
+C80 a_399_n75# a_495_n75# 0.22fF
+C81 a_n849_n75# a_n657_n75# 0.08fF
+C82 a_n81_n75# a_303_n75# 0.03fF
+C83 a_591_n75# a_687_n75# 0.22fF
+C84 a_303_n75# a_687_n75# 0.03fF
+C85 a_687_n75# a_495_n75# 0.08fF
+C86 a_n1229_n75# a_n945_n75# 0.05fF
+C87 a_n465_n75# a_n753_n75# 0.05fF
+C88 a_n561_n75# a_n369_n75# 0.08fF
+C89 a_n1229_n75# a_n1137_n75# 0.22fF
+C90 a_111_n75# a_n273_n75# 0.03fF
+C91 a_591_n75# a_783_n75# 0.08fF
+C92 a_495_n75# a_783_n75# 0.05fF
+C93 a_n273_n75# a_n177_n75# 0.22fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n417_n75# a_n129_n75# 0.05fF
+C1 a_63_n75# a_447_n75# 0.03fF
+C2 a_n417_n75# a_n609_n75# 0.08fF
+C3 a_n513_n75# a_n705_n75# 0.08fF
+C4 a_n225_n75# a_63_n75# 0.05fF
+C5 a_63_n75# a_n33_n75# 0.22fF
+C6 a_n225_n75# a_n33_n75# 0.08fF
+C7 a_n129_n75# a_n321_n75# 0.08fF
+C8 a_735_n75# a_543_n75# 0.08fF
+C9 a_n609_n75# a_n321_n75# 0.05fF
+C10 a_n129_n75# a_255_n75# 0.03fF
+C11 a_33_n101# a_n927_n101# 0.08fF
+C12 a_159_n75# a_255_n75# 0.22fF
+C13 a_n513_n75# a_n129_n75# 0.03fF
+C14 a_159_n75# a_543_n75# 0.03fF
+C15 a_n417_n75# a_n801_n75# 0.03fF
+C16 a_831_n75# a_639_n75# 0.08fF
+C17 a_351_n75# a_255_n75# 0.22fF
+C18 a_n513_n75# a_n609_n75# 0.22fF
+C19 a_351_n75# a_543_n75# 0.08fF
+C20 a_n705_n75# a_n989_n75# 0.05fF
+C21 a_n513_n75# a_n897_n75# 0.03fF
+C22 a_831_n75# a_447_n75# 0.03fF
+C23 a_n417_n75# a_n225_n75# 0.08fF
+C24 a_n417_n75# a_n33_n75# 0.03fF
+C25 a_927_n75# a_831_n75# 0.22fF
+C26 a_639_n75# a_255_n75# 0.03fF
+C27 a_639_n75# a_543_n75# 0.22fF
+C28 a_63_n75# a_n321_n75# 0.03fF
+C29 a_n225_n75# a_n321_n75# 0.22fF
+C30 a_n33_n75# a_n321_n75# 0.05fF
+C31 a_447_n75# a_255_n75# 0.08fF
+C32 a_n609_n75# a_n705_n75# 0.22fF
+C33 a_n513_n75# a_n801_n75# 0.05fF
+C34 a_n897_n75# a_n705_n75# 0.08fF
+C35 a_447_n75# a_543_n75# 0.22fF
+C36 a_927_n75# a_543_n75# 0.03fF
+C37 a_n609_n75# a_n989_n75# 0.03fF
+C38 a_n897_n75# a_n989_n75# 0.22fF
+C39 a_63_n75# a_255_n75# 0.08fF
+C40 a_n33_n75# a_255_n75# 0.05fF
+C41 a_735_n75# a_351_n75# 0.03fF
+C42 a_n513_n75# a_n225_n75# 0.05fF
+C43 a_159_n75# a_n129_n75# 0.05fF
+C44 a_735_n75# a_639_n75# 0.22fF
+C45 a_n705_n75# a_n801_n75# 0.22fF
+C46 a_159_n75# a_351_n75# 0.08fF
+C47 a_n417_n75# a_n321_n75# 0.22fF
+C48 a_n897_n75# a_n609_n75# 0.05fF
+C49 a_n801_n75# a_n989_n75# 0.08fF
+C50 a_735_n75# a_447_n75# 0.05fF
+C51 a_927_n75# a_735_n75# 0.08fF
+C52 a_n417_n75# a_n513_n75# 0.22fF
+C53 a_351_n75# a_639_n75# 0.05fF
+C54 a_n609_n75# a_n801_n75# 0.08fF
+C55 a_831_n75# a_543_n75# 0.05fF
+C56 a_159_n75# a_447_n75# 0.05fF
+C57 a_n897_n75# a_n801_n75# 0.22fF
+C58 a_n129_n75# a_63_n75# 0.08fF
+C59 a_n513_n75# a_n321_n75# 0.08fF
+C60 a_n225_n75# a_n129_n75# 0.22fF
+C61 a_351_n75# a_447_n75# 0.22fF
+C62 a_n129_n75# a_n33_n75# 0.22fF
+C63 a_159_n75# a_63_n75# 0.22fF
+C64 a_159_n75# a_n225_n75# 0.03fF
+C65 a_159_n75# a_n33_n75# 0.08fF
+C66 a_n225_n75# a_n609_n75# 0.03fF
+C67 a_63_n75# a_351_n75# 0.05fF
+C68 a_351_n75# a_n33_n75# 0.03fF
+C69 a_543_n75# a_255_n75# 0.05fF
+C70 a_n417_n75# a_n705_n75# 0.05fF
+C71 a_447_n75# a_639_n75# 0.08fF
+C72 a_927_n75# a_639_n75# 0.05fF
+C73 a_n705_n75# a_n321_n75# 0.03fF
+C74 a_735_n75# a_831_n75# 0.22fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n801_n150# a_n513_n150# 0.10fF
+C1 a_351_n150# a_639_n150# 0.10fF
+C2 a_63_n150# a_n321_n150# 0.07fF
+C3 a_351_n150# a_159_n150# 0.16fF
+C4 a_n897_n150# a_n705_n150# 0.16fF
+C5 a_543_n150# a_735_n150# 0.16fF
+C6 a_639_n150# a_447_n150# 0.16fF
+C7 a_n609_n150# a_n705_n150# 0.43fF
+C8 a_n33_n150# a_n225_n150# 0.16fF
+C9 a_n33_n150# a_255_n150# 0.10fF
+C10 a_n417_n150# a_n705_n150# 0.10fF
+C11 a_159_n150# a_447_n150# 0.10fF
+C12 a_n897_n150# a_n513_n150# 0.07fF
+C13 a_n801_n150# a_n989_n150# 0.16fF
+C14 a_n609_n150# a_n513_n150# 0.43fF
+C15 a_255_n150# a_639_n150# 0.07fF
+C16 a_n609_n150# a_n225_n150# 0.07fF
+C17 a_n417_n150# a_n513_n150# 0.43fF
+C18 a_159_n150# a_n225_n150# 0.07fF
+C19 a_255_n150# a_159_n150# 0.43fF
+C20 a_n417_n150# a_n225_n150# 0.16fF
+C21 a_351_n150# a_63_n150# 0.10fF
+C22 a_n705_n150# a_n321_n150# 0.07fF
+C23 a_351_n150# a_543_n150# 0.16fF
+C24 a_351_n150# a_735_n150# 0.07fF
+C25 a_n897_n150# a_n801_n150# 0.43fF
+C26 a_n129_n150# a_n513_n150# 0.07fF
+C27 a_n609_n150# a_n801_n150# 0.16fF
+C28 a_n129_n150# a_n225_n150# 0.43fF
+C29 a_255_n150# a_n129_n150# 0.07fF
+C30 a_639_n150# a_831_n150# 0.16fF
+C31 a_n801_n150# a_n417_n150# 0.07fF
+C32 a_63_n150# a_447_n150# 0.07fF
+C33 a_n897_n150# a_n989_n150# 0.43fF
+C34 a_543_n150# a_447_n150# 0.43fF
+C35 a_735_n150# a_447_n150# 0.10fF
+C36 a_n609_n150# a_n989_n150# 0.07fF
+C37 a_n321_n150# a_n513_n150# 0.16fF
+C38 a_n321_n150# a_n225_n150# 0.43fF
+C39 a_n33_n150# a_159_n150# 0.16fF
+C40 a_n33_n150# a_n417_n150# 0.07fF
+C41 a_63_n150# a_n225_n150# 0.10fF
+C42 a_255_n150# a_63_n150# 0.16fF
+C43 a_255_n150# a_543_n150# 0.10fF
+C44 a_n609_n150# a_n897_n150# 0.10fF
+C45 a_831_n150# a_927_n150# 0.43fF
+C46 a_n33_n150# a_n129_n150# 0.43fF
+C47 a_n609_n150# a_n417_n150# 0.16fF
+C48 a_351_n150# a_447_n150# 0.43fF
+C49 a_n33_n150# a_n321_n150# 0.10fF
+C50 a_543_n150# a_831_n150# 0.10fF
+C51 a_831_n150# a_735_n150# 0.43fF
+C52 a_639_n150# a_927_n150# 0.10fF
+C53 a_33_n247# a_n927_n247# 0.09fF
+C54 a_n33_n150# a_63_n150# 0.43fF
+C55 a_159_n150# a_n129_n150# 0.10fF
+C56 a_351_n150# a_255_n150# 0.43fF
+C57 a_n417_n150# a_n129_n150# 0.10fF
+C58 a_n705_n150# a_n513_n150# 0.16fF
+C59 a_n609_n150# a_n321_n150# 0.10fF
+C60 a_n417_n150# a_n321_n150# 0.43fF
+C61 a_543_n150# a_639_n150# 0.43fF
+C62 a_255_n150# a_447_n150# 0.16fF
+C63 a_639_n150# a_735_n150# 0.43fF
+C64 a_63_n150# a_159_n150# 0.43fF
+C65 a_543_n150# a_159_n150# 0.07fF
+C66 a_n225_n150# a_n513_n150# 0.10fF
+C67 a_n801_n150# a_n705_n150# 0.43fF
+C68 a_n321_n150# a_n129_n150# 0.16fF
+C69 a_351_n150# a_n33_n150# 0.07fF
+C70 a_n989_n150# a_n705_n150# 0.10fF
+C71 a_63_n150# a_n129_n150# 0.16fF
+C72 a_831_n150# a_447_n150# 0.07fF
+C73 a_543_n150# a_927_n150# 0.07fF
+C74 a_735_n150# a_927_n150# 0.16fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n387_n44# a_n29_n44# 0.04fF
+C1 a_329_n44# a_n29_n44# 0.04fF
+C2 a_n1461_n44# a_n1103_n44# 0.04fF
+C3 a_n1461_n44# a_n1819_n44# 0.04fF
+C4 a_1045_n44# a_687_n44# 0.04fF
+C5 a_n745_n44# a_n1103_n44# 0.04fF
+C6 a_1403_n44# a_1761_n44# 0.04fF
+C7 a_1403_n44# a_1045_n44# 0.04fF
+C8 a_n745_n44# a_n387_n44# 0.04fF
+C9 a_329_n44# a_687_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n849_n150# a_n1137_n150# 0.10fF
+C1 a_n81_n150# a_n273_n150# 0.16fF
+C2 a_n1229_n150# a_n945_n150# 0.10fF
+C3 a_207_n150# a_303_n150# 0.43fF
+C4 a_15_n150# a_n369_n150# 0.07fF
+C5 a_399_n150# a_591_n150# 0.16fF
+C6 a_495_n150# a_303_n150# 0.16fF
+C7 a_111_n150# a_15_n150# 0.43fF
+C8 a_n945_n150# a_n753_n150# 0.16fF
+C9 a_n849_n150# a_n561_n150# 0.10fF
+C10 a_n945_n150# a_n1137_n150# 0.16fF
+C11 a_n657_n150# a_n753_n150# 0.43fF
+C12 a_1071_n150# a_783_n150# 0.10fF
+C13 a_n465_n150# a_n753_n150# 0.10fF
+C14 a_1071_n150# a_1167_n150# 0.43fF
+C15 a_n81_n150# a_207_n150# 0.10fF
+C16 a_591_n150# a_303_n150# 0.10fF
+C17 a_n945_n150# a_n561_n150# 0.07fF
+C18 a_1071_n150# a_975_n150# 0.43fF
+C19 a_n657_n150# a_n561_n150# 0.43fF
+C20 a_n657_n150# a_n273_n150# 0.07fF
+C21 a_207_n150# a_495_n150# 0.10fF
+C22 a_n465_n150# a_n561_n150# 0.43fF
+C23 a_495_n150# a_783_n150# 0.10fF
+C24 a_399_n150# a_687_n150# 0.10fF
+C25 a_n465_n150# a_n273_n150# 0.16fF
+C26 a_783_n150# a_1167_n150# 0.07fF
+C27 a_111_n150# a_399_n150# 0.10fF
+C28 a_1071_n150# w_n1367_n369# 0.07fF
+C29 a_n753_n150# a_n369_n150# 0.07fF
+C30 a_n1229_n150# a_n1041_n150# 0.16fF
+C31 a_399_n150# a_15_n150# 0.07fF
+C32 a_975_n150# a_783_n150# 0.16fF
+C33 a_n177_n150# a_n561_n150# 0.07fF
+C34 a_n177_n150# a_n273_n150# 0.43fF
+C35 a_591_n150# a_207_n150# 0.07fF
+C36 a_n1041_n150# a_n753_n150# 0.10fF
+C37 a_975_n150# a_1167_n150# 0.16fF
+C38 a_n81_n150# a_n465_n150# 0.07fF
+C39 a_591_n150# a_783_n150# 0.16fF
+C40 a_687_n150# a_303_n150# 0.07fF
+C41 a_591_n150# a_495_n150# 0.43fF
+C42 a_n1041_n150# a_n1137_n150# 0.43fF
+C43 a_1071_n150# a_879_n150# 0.16fF
+C44 a_n369_n150# a_n561_n150# 0.16fF
+C45 a_n849_n150# a_n945_n150# 0.43fF
+C46 a_111_n150# a_303_n150# 0.16fF
+C47 a_n369_n150# a_n273_n150# 0.43fF
+C48 a_n657_n150# a_n849_n150# 0.16fF
+C49 a_111_n150# a_n273_n150# 0.07fF
+C50 w_n1367_n369# a_1167_n150# 0.14fF
+C51 a_1071_n150# a_687_n150# 0.07fF
+C52 a_15_n150# a_303_n150# 0.10fF
+C53 a_n849_n150# a_n465_n150# 0.07fF
+C54 a_591_n150# a_975_n150# 0.07fF
+C55 a_n81_n150# a_n177_n150# 0.43fF
+C56 a_15_n150# a_n273_n150# 0.10fF
+C57 w_n1367_n369# a_975_n150# 0.05fF
+C58 a_207_n150# a_n177_n150# 0.07fF
+C59 a_n657_n150# a_n945_n150# 0.10fF
+C60 a_783_n150# a_879_n150# 0.43fF
+C61 a_495_n150# a_879_n150# 0.07fF
+C62 a_n81_n150# a_n369_n150# 0.10fF
+C63 a_111_n150# a_n81_n150# 0.16fF
+C64 a_1167_n150# a_879_n150# 0.10fF
+C65 a_783_n150# a_687_n150# 0.43fF
+C66 a_n657_n150# a_n465_n150# 0.16fF
+C67 a_495_n150# a_687_n150# 0.16fF
+C68 a_n1229_n150# a_n1137_n150# 0.43fF
+C69 a_111_n150# a_207_n150# 0.43fF
+C70 a_n81_n150# a_15_n150# 0.43fF
+C71 a_111_n150# a_495_n150# 0.07fF
+C72 a_975_n150# a_879_n150# 0.43fF
+C73 a_207_n150# a_15_n150# 0.16fF
+C74 a_n753_n150# a_n1137_n150# 0.07fF
+C75 a_591_n150# a_879_n150# 0.10fF
+C76 a_975_n150# a_687_n150# 0.10fF
+C77 a_399_n150# a_303_n150# 0.43fF
+C78 a_n849_n150# a_n1041_n150# 0.16fF
+C79 w_n1367_n369# a_879_n150# 0.04fF
+C80 a_n465_n150# a_n177_n150# 0.10fF
+C81 a_591_n150# a_687_n150# 0.43fF
+C82 a_n753_n150# a_n561_n150# 0.16fF
+C83 a_n657_n150# a_n369_n150# 0.10fF
+C84 a_n1041_n150# a_n945_n150# 0.43fF
+C85 a_n465_n150# a_n369_n150# 0.43fF
+C86 a_n657_n150# a_n1041_n150# 0.07fF
+C87 a_n273_n150# a_n561_n150# 0.10fF
+C88 a_399_n150# a_207_n150# 0.16fF
+C89 a_687_n150# a_879_n150# 0.16fF
+C90 a_399_n150# a_783_n150# 0.07fF
+C91 a_n369_n150# a_n177_n150# 0.16fF
+C92 a_399_n150# a_495_n150# 0.43fF
+C93 a_111_n150# a_n177_n150# 0.10fF
+C94 a_n1229_n150# a_n849_n150# 0.07fF
+C95 a_15_n150# a_n177_n150# 0.16fF
+C96 a_n81_n150# a_303_n150# 0.07fF
+C97 a_n849_n150# a_n753_n150# 0.43fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vdd nUp vss Down biasp out pswitch iref nDown Up
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 out pswitch 4.91fF
+C1 nswitch vdd 0.07fF
+C2 out nUp 0.31fF
+C3 out vdd 6.66fF
+C4 Down nDown 0.13fF
+C5 nswitch out 1.28fF
+C6 iref biasp 0.80fF
+C7 pswitch biasp 3.11fF
+C8 pswitch Up 0.70fF
+C9 Down nUp 0.25fF
+C10 nswitch Down 2.27fF
+C11 pswitch nUp 5.66fF
+C12 Up nUp 0.15fF
+C13 biasp vdd 2.64fF
+C14 iref nswitch 1.91fF
+C15 pswitch vdd 3.98fF
+C16 nswitch biasp 0.03fF
+C17 nswitch pswitch 0.06fF
+C18 nswitch nDown 0.31fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_n111_n156# a_n15_n156# 0.02fF
+C2 a_n81_n125# w_n311_n344# 0.09fF
+C3 a_111_n125# a_n81_n125# 0.13fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_81_n156# a_n15_n156# 0.02fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 a_111_n125# w_n311_n344# 0.14fF
+C8 a_n173_n125# w_n311_n344# 0.14fF
+C9 a_111_n125# a_n173_n125# 0.08fF
+C10 a_15_n125# w_n311_n344# 0.09fF
+C11 a_15_n125# a_111_n125# 0.36fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n15_n151# a_81_n151# 0.02fF
+C1 a_15_n125# a_n81_n125# 0.36fF
+C2 a_n111_n151# a_n15_n151# 0.02fF
+C3 a_n173_n125# a_111_n125# 0.08fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_n173_n125# a_15_n125# 0.13fF
+C6 a_n81_n125# a_111_n125# 0.13fF
+C7 a_15_n125# a_111_n125# 0.36fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 vdd m1_45_n513# 0.69fF
+C1 m1_187_n605# vdd 0.55fF
+C2 m1_187_n605# m1_45_n513# 0.36fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_111_n125# w_n311_n344# 0.14fF
+C2 a_n81_n125# a_n173_n125# 0.36fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_15_n125# w_n311_n344# 0.09fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_n81_n125# w_n311_n344# 0.09fF
+C7 a_111_n125# a_n173_n125# 0.08fF
+C8 w_n311_n344# a_n173_n125# 0.14fF
+C9 a_15_n125# a_n81_n125# 0.36fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n81_n125# 0.13fF
+C1 a_111_n125# a_n173_n125# 0.08fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 a_15_n125# a_n173_n125# 0.13fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 in out 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd CLK_d 0.03fF
+C1 nCLK_d vdd 0.03fF
+C2 vdd inverter_cp_x1_2/in 0.21fF
+C3 CLK inverter_cp_x1_2/in 0.31fF
+C4 CLK_d inverter_cp_x1_2/in 0.12fF
+C5 vdd inverter_cp_x1_0/out 0.28fF
+C6 CLK inverter_cp_x1_0/out 0.31fF
+C7 nCLK_d inverter_cp_x1_0/out 0.11fF
+C8 vdd CLK 0.36fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_n125_n95# 0.28fF
+C1 a_n33_n95# w_n263_n314# 0.08fF
+C2 a_63_n95# a_n33_n95# 0.28fF
+C3 a_n125_n95# w_n263_n314# 0.11fF
+C4 a_63_n95# a_n125_n95# 0.10fF
+C5 a_63_n95# w_n263_n314# 0.11fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n81_n125# 0.36fF
+C1 a_n173_n125# a_n129_n213# 0.02fF
+C2 a_111_n125# a_n173_n125# 0.08fF
+C3 a_15_n125# a_n81_n125# 0.36fF
+C4 a_15_n125# a_n129_n213# 0.10fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_n173_n125# a_15_n125# 0.13fF
+C7 a_n81_n125# a_n129_n213# 0.10fF
+C8 a_111_n125# a_n81_n125# 0.13fF
+C9 a_111_n125# a_n129_n213# 0.01fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n33_n95# 0.88fF
+C1 a_n125_n95# a_n81_n183# 0.16fF
+C2 a_n33_n95# a_n81_n183# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 CLK m1_657_280# 0.24fF
+C1 vdd Q 0.16fF
+C2 Q nD 0.05fF
+C3 D Q 0.05fF
+C4 nQ m1_657_280# 1.41fF
+C5 vdd nQ 0.16fF
+C6 nQ nD 0.05fF
+C7 D nQ 0.05fF
+C8 Q nQ 0.93fF
+C9 Q m1_657_280# 0.94fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
++ nCLK latch_diff_0/nD
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 nQ latch_diff_1/nD 0.08fF
+C1 latch_diff_1/D latch_diff_1/nD 0.33fF
+C2 vdd latch_diff_0/D 0.09fF
+C3 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C4 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C5 latch_diff_1/D latch_diff_1/m1_657_280# 0.32fF
+C6 latch_diff_0/D latch_diff_1/nD 0.04fF
+C7 latch_diff_0/D latch_diff_0/m1_657_280# 0.37fF
+C8 nQ latch_diff_1/D 0.11fF
+C9 vdd latch_diff_0/nD 0.14fF
+C10 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C11 latch_diff_1/D latch_diff_0/D 0.11fF
+C12 latch_diff_0/nD latch_diff_1/D 0.41fF
+C13 vdd latch_diff_1/nD 0.02fF
+C14 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
+C15 Q latch_diff_1/nD 0.01fF
+C16 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C17 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C18 vdd latch_diff_1/D 0.03fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n129_n84# a_63_n84# 0.09fF
+C1 a_159_n84# a_n33_n84# 0.09fF
+C2 a_n221_n84# w_n359_n303# 0.08fF
+C3 a_n221_n84# a_n129_n84# 0.24fF
+C4 w_n359_n303# a_n33_n84# 0.05fF
+C5 a_33_n110# a_129_n110# 0.02fF
+C6 a_n129_n84# a_n33_n84# 0.24fF
+C7 w_n359_n303# a_159_n84# 0.08fF
+C8 a_n221_n84# a_63_n84# 0.05fF
+C9 a_159_n84# a_n129_n84# 0.05fF
+C10 a_n33_n84# a_63_n84# 0.24fF
+C11 a_n63_n110# a_33_n110# 0.02fF
+C12 a_n63_n110# a_n159_n110# 0.02fF
+C13 a_159_n84# a_63_n84# 0.24fF
+C14 w_n359_n303# a_n129_n84# 0.06fF
+C15 a_n221_n84# a_n33_n84# 0.09fF
+C16 w_n359_n303# a_63_n84# 0.06fF
+C17 a_n221_n84# a_159_n84# 0.04fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n129_n42# a_n33_n42# 0.12fF
+C1 a_n221_n42# a_159_n42# 0.02fF
+C2 a_n221_n42# a_63_n42# 0.03fF
+C3 a_n129_n42# a_159_n42# 0.03fF
+C4 a_n129_n42# a_63_n42# 0.05fF
+C5 a_33_n68# a_n63_n68# 0.02fF
+C6 a_159_n42# a_n33_n42# 0.05fF
+C7 a_n33_n42# a_63_n42# 0.12fF
+C8 a_33_n68# a_129_n68# 0.02fF
+C9 a_n63_n68# a_n159_n68# 0.02fF
+C10 a_159_n42# a_63_n42# 0.12fF
+C11 a_n221_n42# a_n129_n42# 0.12fF
+C12 a_n221_n42# a_n33_n42# 0.05fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 out vdd 0.62fF
+C1 in vdd 0.33fF
+C2 in out 0.67fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n125_n42# a_n33_n42# 0.12fF
+C1 a_33_n68# a_n63_n68# 0.02fF
+C2 a_63_n42# a_n33_n42# 0.12fF
+C3 a_63_n42# a_n125_n42# 0.05fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n33_n84# a_63_n84# 0.24fF
+C1 a_n33_n84# w_n263_n303# 0.07fF
+C2 a_63_n84# w_n263_n303# 0.10fF
+C3 a_33_n110# a_n63_n110# 0.02fF
+C4 a_n33_n84# a_n125_n84# 0.24fF
+C5 a_63_n84# a_n125_n84# 0.09fF
+C6 w_n263_n303# a_n125_n84# 0.10fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 out in 0.30fF
+C1 out vdd 0.15fF
+C2 vdd in 0.01fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C1 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
+C2 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C3 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C4 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C5 DFlipFlop_0/latch_diff_0/D DFlipFlop_0/nCLK 0.13fF
+C6 nCLK_2 vdd 0.08fF
+C7 vdd DFlipFlop_0/CLK 0.40fF
+C8 DFlipFlop_0/latch_diff_0/nD nout_div 0.07fF
+C9 vdd DFlipFlop_0/nCLK 0.30fF
+C10 out_div nout_div 0.22fF
+C11 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C12 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C13 out_div o1 0.01fF
+C14 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C15 CLK_2 o1 0.11fF
+C16 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C17 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C18 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C19 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/CLK -0.48fF
+C20 DFlipFlop_0/latch_diff_0/D nout_div 0.09fF
+C21 vdd out_div 0.03fF
+C22 vdd o2 0.14fF
+C23 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C24 vdd CLK_2 0.08fF
+C25 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
+C26 vdd nout_div 0.16fF
+C27 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C28 vdd o1 0.14fF
+C29 nCLK_2 o2 0.11fF
+C30 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C31 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C32 nout_div DFlipFlop_0/CLK 0.42fF
+C33 nout_div DFlipFlop_0/nCLK 0.43fF
+C34 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C35 nCLK_2 vss 1.08fF
+C36 o2 vss 2.21fF
+C37 CLK_2 vss 1.08fF
+C38 o1 vss 2.21fF
+C39 DFlipFlop_0/CLK vss 1.03fF
+C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C42 CLK vss 3.27fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n257_n777# a_n221_n600# 0.25fF
+C1 a_n129_n600# a_n221_n600# 7.87fF
+C2 a_n257_n777# a_n129_n600# 0.29fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n221_n300# a_n129_n300# 4.05fF
+C1 a_n257_n404# a_n129_n300# 0.30fF
+C2 a_n221_n300# a_n257_n404# 0.21fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 in a_678_n100# 0.81fF
+C1 vdd in 0.02fF
+C2 vdd out 47.17fF
+C3 vdd a_678_n100# 0.08fF
+C4 a_3996_n100# out 55.19fF
+C5 a_3996_n100# a_678_n100# 6.52fF
+C6 a_3996_n100# vdd 3.68fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n238# a_n73_n150# 0.02fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 a_15_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n369# a_n33_181# 0.05fF
+C1 a_15_n150# w_n211_n369# 0.20fF
+C2 a_n73_n150# a_n33_181# 0.01fF
+C3 a_n73_n150# a_15_n150# 0.51fF
+C4 a_n73_n150# w_n211_n369# 0.20fF
+C5 a_15_n150# a_n33_181# 0.01fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n129_n150# a_63_n150# 0.16fF
+C1 a_447_n150# a_159_n150# 0.10fF
+C2 a_n321_n150# a_n33_n150# 0.10fF
+C3 a_n225_n150# a_159_n150# 0.07fF
+C4 a_447_n150# a_n465_172# 0.01fF
+C5 a_n225_n150# a_n465_172# 0.10fF
+C6 a_n33_n150# a_159_n150# 0.16fF
+C7 a_n465_172# a_n509_n150# 0.01fF
+C8 a_n417_n150# a_n225_n150# 0.16fF
+C9 a_n321_n150# a_n465_172# 0.10fF
+C10 a_255_n150# a_447_n150# 0.16fF
+C11 a_n33_n150# a_n465_172# 0.10fF
+C12 a_n417_n150# a_n509_n150# 0.43fF
+C13 a_447_n150# a_351_n150# 0.43fF
+C14 a_447_n150# a_63_n150# 0.07fF
+C15 a_n417_n150# a_n321_n150# 0.43fF
+C16 a_n225_n150# a_63_n150# 0.10fF
+C17 a_n417_n150# a_n33_n150# 0.07fF
+C18 a_n465_172# a_159_n150# 0.10fF
+C19 a_n129_n150# a_n225_n150# 0.43fF
+C20 a_255_n150# a_n33_n150# 0.10fF
+C21 a_n321_n150# a_63_n150# 0.07fF
+C22 a_351_n150# a_n33_n150# 0.07fF
+C23 a_n33_n150# a_63_n150# 0.43fF
+C24 a_n129_n150# a_n509_n150# 0.07fF
+C25 a_n321_n150# a_n129_n150# 0.16fF
+C26 a_n417_n150# a_n465_172# 0.10fF
+C27 a_255_n150# a_159_n150# 0.43fF
+C28 a_n129_n150# a_n33_n150# 0.43fF
+C29 a_351_n150# a_159_n150# 0.16fF
+C30 a_159_n150# a_63_n150# 0.43fF
+C31 a_255_n150# a_n465_172# 0.10fF
+C32 a_351_n150# a_n465_172# 0.10fF
+C33 a_n465_172# a_63_n150# 0.10fF
+C34 a_n129_n150# a_159_n150# 0.10fF
+C35 a_n129_n150# a_n465_172# 0.10fF
+C36 a_n225_n150# a_n509_n150# 0.10fF
+C37 a_255_n150# a_351_n150# 0.43fF
+C38 a_255_n150# a_63_n150# 0.16fF
+C39 a_n417_n150# a_n129_n150# 0.10fF
+C40 a_n321_n150# a_n225_n150# 0.43fF
+C41 a_351_n150# a_63_n150# 0.10fF
+C42 a_n225_n150# a_n33_n150# 0.16fF
+C43 a_255_n150# a_n129_n150# 0.07fF
+C44 a_n321_n150# a_n509_n150# 0.16fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n225_n150# a_n321_n150# 0.43fF
+C1 a_n417_n150# a_n33_n150# 0.07fF
+C2 a_n417_n150# w_n647_n369# 0.07fF
+C3 a_n33_n150# a_n321_n150# 0.10fF
+C4 w_n647_n369# a_n321_n150# 0.05fF
+C5 a_63_n150# a_n321_n150# 0.07fF
+C6 a_n129_n150# a_159_n150# 0.10fF
+C7 a_n129_n150# a_n225_n150# 0.43fF
+C8 a_n129_n150# a_255_n150# 0.07fF
+C9 a_n129_n150# a_n33_n150# 0.43fF
+C10 a_n225_n150# a_159_n150# 0.07fF
+C11 a_n129_n150# w_n647_n369# 0.02fF
+C12 a_255_n150# a_159_n150# 0.43fF
+C13 a_447_n150# a_351_n150# 0.43fF
+C14 a_63_n150# a_n129_n150# 0.16fF
+C15 a_n33_n150# a_159_n150# 0.16fF
+C16 w_n647_n369# a_159_n150# 0.04fF
+C17 a_n225_n150# a_n33_n150# 0.16fF
+C18 a_255_n150# a_n33_n150# 0.10fF
+C19 a_n225_n150# w_n647_n369# 0.04fF
+C20 a_n465_n247# a_n417_n150# 0.08fF
+C21 a_63_n150# a_159_n150# 0.43fF
+C22 a_255_n150# w_n647_n369# 0.05fF
+C23 a_63_n150# a_n225_n150# 0.10fF
+C24 a_63_n150# a_255_n150# 0.16fF
+C25 a_n417_n150# a_n509_n150# 0.43fF
+C26 w_n647_n369# a_n33_n150# 0.02fF
+C27 a_n465_n247# a_n321_n150# 0.08fF
+C28 a_63_n150# a_n33_n150# 0.43fF
+C29 a_63_n150# w_n647_n369# 0.02fF
+C30 a_n509_n150# a_n321_n150# 0.16fF
+C31 a_n129_n150# a_n465_n247# 0.08fF
+C32 a_n129_n150# a_n509_n150# 0.07fF
+C33 a_n465_n247# a_159_n150# 0.08fF
+C34 a_n465_n247# a_n225_n150# 0.08fF
+C35 a_255_n150# a_n465_n247# 0.08fF
+C36 a_159_n150# a_351_n150# 0.16fF
+C37 a_n509_n150# a_n225_n150# 0.10fF
+C38 a_n465_n247# a_n33_n150# 0.08fF
+C39 a_255_n150# a_351_n150# 0.43fF
+C40 a_n465_n247# w_n647_n369# 0.47fF
+C41 a_63_n150# a_n465_n247# 0.08fF
+C42 a_n33_n150# a_351_n150# 0.07fF
+C43 a_n509_n150# w_n647_n369# 0.14fF
+C44 w_n647_n369# a_351_n150# 0.07fF
+C45 a_63_n150# a_351_n150# 0.10fF
+C46 a_n417_n150# a_n321_n150# 0.43fF
+C47 a_447_n150# a_159_n150# 0.10fF
+C48 a_255_n150# a_447_n150# 0.16fF
+C49 a_n465_n247# a_351_n150# 0.08fF
+C50 a_n129_n150# a_n417_n150# 0.10fF
+C51 a_447_n150# w_n647_n369# 0.14fF
+C52 a_63_n150# a_447_n150# 0.07fF
+C53 a_n129_n150# a_n321_n150# 0.16fF
+C54 a_n417_n150# a_n225_n150# 0.16fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n73_n11# 0.15fF
+C1 a_n33_n99# a_n73_n11# 0.02fF
+C2 a_n33_n99# a_15_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_n78_n114# 0.20fF
+C1 a_n78_n114# a_20_n114# 0.42fF
+C2 w_n216_n334# a_20_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vdd 0.01fF
+C1 vdd vbulkp 0.04fF
+C2 in vss 0.01fF
+C3 in out 0.11fF
+C4 vbulkp out 0.08fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 vdd inverter_csvco_0/vdd 1.89fF
+C1 inverter_csvco_0/vss out 0.03fF
+C2 inverter_csvco_0/vss in 0.01fF
+C3 vdd cap_vco_0/t 0.04fF
+C4 inverter_csvco_0/vdd vbp 0.75fF
+C5 out D0 0.09fF
+C6 inverter_csvco_0/vss vctrl 0.87fF
+C7 inverter_csvco_0/vdd out 0.02fF
+C8 inverter_csvco_0/vdd in 0.01fF
+C9 inverter_csvco_0/vss D0 0.02fF
+C10 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C11 out in 0.06fF
+C12 out cap_vco_0/t 0.70fF
+C13 vdd vbp 1.21fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vdd vss csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C1 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C2 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
+C3 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C4 csvco_branch_2/vbp vctrl 0.06fF
+C5 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C6 D0 vctrl 4.41fF
+C7 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C8 csvco_branch_2/vbp vdd 1.49fF
+C9 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C10 out_vco csvco_branch_2/in 0.58fF
+C11 csvco_branch_1/cap_vco_0/t out_vco 0.03fF
+C12 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C13 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
+C14 out_vco csvco_branch_1/in 0.76fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 vdd out_pad 0.10fF
+C1 out_div out_pad 0.15fF
+C2 vdd out_div 0.17fF
+C3 vdd o1 0.09fF
+C4 out_div o1 0.11fF
+C5 in_vco vss 0.83fF
+C6 out_pad vss 0.70fF
+C7 out_div vss 3.00fF
+C8 vdd vss 14.54fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_355_368# a_194_125# 0.51fF
+C1 a_355_368# X 0.17fF
+C2 VPWR VPB 0.06fF
+C3 a_355_368# A 0.02fF
+C4 B a_194_125# 0.57fF
+C5 B X 0.13fF
+C6 VGND VPWR 0.01fF
+C7 B A 0.28fF
+C8 X a_194_125# 0.29fF
+C9 B VGND 0.10fF
+C10 A a_194_125# 0.18fF
+C11 a_355_368# VPWR 0.37fF
+C12 a_194_125# a_158_392# 0.06fF
+C13 VGND a_194_125# 0.25fF
+C14 VGND X 0.28fF
+C15 B VPWR 0.09fF
+C16 VGND A 0.31fF
+C17 B a_355_368# 0.08fF
+C18 VPWR a_194_125# 0.33fF
+C19 X VPWR 0.07fF
+C20 A VPWR 0.15fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 A B 0.08fF
+C1 X a_56_136# 0.26fF
+C2 VPB VPWR 0.04fF
+C3 VGND X 0.15fF
+C4 A VPWR 0.07fF
+C5 VPWR B 0.02fF
+C6 X B 0.02fF
+C7 VGND a_56_136# 0.06fF
+C8 A a_56_136# 0.17fF
+C9 VPWR X 0.20fF
+C10 VGND A 0.21fF
+C11 B a_56_136# 0.30fF
+C12 VGND B 0.03fF
+C13 VPWR a_56_136# 0.57fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 a_63_368# a_152_368# 0.03fF
+C1 a_63_368# X 0.33fF
+C2 X VPWR 0.18fF
+C3 a_63_368# A 0.28fF
+C4 A VPWR 0.05fF
+C5 VGND B 0.11fF
+C6 VGND X 0.16fF
+C7 VPB VPWR 0.04fF
+C8 B A 0.10fF
+C9 A X 0.02fF
+C10 a_63_368# VPWR 0.29fF
+C11 a_63_368# B 0.14fF
+C12 B VPWR 0.01fF
+C13 a_63_368# VGND 0.27fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
++ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
++ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
++ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C2 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C3 DFlipFlop_3/nQ CLK 0.01fF
+C4 Q1 DFlipFlop_2/D 0.10fF
+C5 nQ2 DFlipFlop_0/Q 0.09fF
+C6 nQ0 nQ2 0.03fF
+C7 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C8 nCLK DFlipFlop_1/D 0.14fF
+C9 Q1 nQ2 0.07fF
+C10 nQ0 DFlipFlop_1/latch_diff_0/D 0.09fF
+C11 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C12 vdd nQ0 0.11fF
+C13 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
+C14 Q1 DFlipFlop_3/latch_diff_1/D 0.79fF
+C15 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C16 DFlipFlop_1/latch_diff_1/m1_657_280# nQ0 0.21fF
+C17 vdd Q1 9.49fF
+C18 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C19 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C20 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C21 DFlipFlop_3/nQ Q1 0.10fF
+C22 CLK DFlipFlop_0/Q 0.08fF
+C23 CLK nQ0 0.19fF
+C24 DFlipFlop_2/D nCLK 0.41fF
+C25 CLK Q1 -0.10fF
+C26 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C27 nQ2 nCLK 0.10fF
+C28 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C29 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C30 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C31 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C32 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C33 nCLK DFlipFlop_3/latch_diff_1/D 0.14fF
+C34 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
+C35 vdd nCLK 0.34fF
+C36 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C37 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C38 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C39 DFlipFlop_3/nQ nCLK 0.02fF
+C40 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
+C41 nCLK sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.02fF
+C42 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C43 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C44 Q1 DFlipFlop_0/Q 0.13fF
+C45 nQ0 Q1 0.06fF
+C46 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C47 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C48 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C49 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C50 DFlipFlop_3/latch_diff_0/m1_657_280# Q1 0.28fF
+C51 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C52 DFlipFlop_2/latch_diff_1/m1_657_280# Q1 0.03fF
+C53 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C54 CLK_5 vdd 0.15fF
+C55 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C56 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
+C57 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
+C58 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C59 sky130_fd_sc_hs__and2_1_0/a_56_136# Q1 0.14fF
+C60 nCLK DFlipFlop_0/Q 0.11fF
+C61 nQ0 nCLK 0.09fF
+C62 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C63 Q1 nCLK -0.01fF
+C64 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C65 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C66 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C67 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C68 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C69 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C70 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C71 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q1 0.09fF
+C72 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C73 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C74 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C75 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C76 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C77 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C78 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C79 Q0 DFlipFlop_1/D 0.07fF
+C80 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C81 Q0 DFlipFlop_0/D 0.39fF
+C82 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C83 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
+C84 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C85 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C86 vdd Q1_shift 0.10fF
+C87 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C88 Q0 DFlipFlop_2/D 0.25fF
+C89 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
+C90 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C91 DFlipFlop_3/nQ Q1_shift 0.04fF
+C92 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
+C93 vdd DFlipFlop_2/nQ 0.02fF
+C94 Q0 nQ2 0.23fF
+C95 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C96 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
+C97 vdd Q0 5.33fF
+C98 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C99 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C100 CLK DFlipFlop_2/nQ 0.13fF
+C101 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C102 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C103 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q1 0.20fF
+C104 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
+C105 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C106 CLK Q0 0.08fF
+C107 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C108 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
+C109 Q1 Q1_shift 0.36fF
+C110 vdd DFlipFlop_1/D 0.25fF
+C111 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C112 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C113 vdd DFlipFlop_0/D 0.19fF
+C114 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C115 DFlipFlop_2/nQ Q1 0.31fF
+C116 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C117 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C118 Q0 DFlipFlop_0/Q 0.21fF
+C119 CLK DFlipFlop_1/D 0.21fF
+C120 Q0 nQ0 0.33fF
+C121 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C122 Q0 Q1 9.65fF
+C123 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C124 vdd DFlipFlop_2/D 0.07fF
+C125 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C126 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C127 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C128 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
+C129 vdd nQ2 0.04fF
+C130 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C131 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C132 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.08fF
+C133 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C134 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C135 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C136 CLK DFlipFlop_2/D 0.14fF
+C137 DFlipFlop_2/nQ nCLK 0.09fF
+C138 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C139 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C140 nQ0 DFlipFlop_1/D 0.12fF
+C141 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C142 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
+C143 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C144 CLK nQ2 0.17fF
+C145 Q1 DFlipFlop_1/D 0.03fF
+C146 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C147 DFlipFlop_3/nQ vdd 0.02fF
+C148 Q0 nCLK 0.20fF
+C149 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C150 DFlipFlop_0/D Q1 0.13fF
+C151 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C152 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C153 vdd CLK 0.41fF
+C154 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C155 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C156 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 DFlipFlop_2/nQ vss 0.50fF
+C172 Q1 vss 8.55fF
+C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 nQ0 vss 3.42fF
+C183 Q0 vss 0.53fF
+C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n63_n151# a_33_n151# 0.02fF
+C1 a_159_n125# a_255_n125# 0.36fF
+C2 a_n317_n125# a_63_n125# 0.06fF
+C3 a_n129_n125# a_n225_n125# 0.36fF
+C4 a_63_n125# a_159_n125# 0.36fF
+C5 a_n317_n125# a_n33_n125# 0.08fF
+C6 a_63_n125# a_255_n125# 0.13fF
+C7 a_n33_n125# a_159_n125# 0.13fF
+C8 a_n33_n125# a_255_n125# 0.08fF
+C9 a_63_n125# a_n33_n125# 0.36fF
+C10 a_n63_n151# a_n159_n151# 0.02fF
+C11 a_n255_n151# a_n159_n151# 0.02fF
+C12 a_129_n151# a_33_n151# 0.02fF
+C13 a_n317_n125# a_n129_n125# 0.13fF
+C14 a_n129_n125# a_159_n125# 0.08fF
+C15 a_225_n151# a_129_n151# 0.02fF
+C16 a_n129_n125# a_255_n125# 0.06fF
+C17 a_63_n125# a_n129_n125# 0.13fF
+C18 a_n129_n125# a_n33_n125# 0.36fF
+C19 a_n317_n125# a_n225_n125# 0.36fF
+C20 a_n225_n125# a_159_n125# 0.06fF
+C21 a_63_n125# a_n225_n125# 0.08fF
+C22 a_n33_n125# a_n225_n125# 0.13fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n225_n125# a_n33_n125# 0.13fF
+C1 a_63_n125# a_159_n125# 0.36fF
+C2 a_n129_n125# a_n317_n125# 0.13fF
+C3 a_n225_n125# a_63_n125# 0.08fF
+C4 a_n129_n125# a_n33_n125# 0.36fF
+C5 a_n63_n154# a_33_n154# 0.02fF
+C6 a_129_n154# a_33_n154# 0.02fF
+C7 a_n225_n125# a_159_n125# 0.06fF
+C8 a_n159_n154# a_n63_n154# 0.02fF
+C9 a_n129_n125# a_63_n125# 0.13fF
+C10 a_129_n154# a_225_n154# 0.02fF
+C11 a_255_n125# a_n33_n125# 0.08fF
+C12 a_n129_n125# a_159_n125# 0.08fF
+C13 a_n159_n154# a_n255_n154# 0.02fF
+C14 w_n455_n344# a_n317_n125# 0.11fF
+C15 w_n455_n344# a_n33_n125# 0.05fF
+C16 a_n129_n125# a_n225_n125# 0.36fF
+C17 a_255_n125# a_63_n125# 0.13fF
+C18 w_n455_n344# a_63_n125# 0.04fF
+C19 a_255_n125# a_159_n125# 0.36fF
+C20 w_n455_n344# a_159_n125# 0.06fF
+C21 w_n455_n344# a_n225_n125# 0.06fF
+C22 a_n317_n125# a_n33_n125# 0.08fF
+C23 a_n129_n125# a_255_n125# 0.06fF
+C24 a_n129_n125# w_n455_n344# 0.04fF
+C25 a_n317_n125# a_63_n125# 0.06fF
+C26 a_63_n125# a_n33_n125# 0.36fF
+C27 a_n33_n125# a_159_n125# 0.13fF
+C28 a_255_n125# w_n455_n344# 0.11fF
+C29 a_n317_n125# a_n225_n125# 0.36fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 vdd in 0.04fF
+C1 vdd out 0.29fF
+C2 in out 0.85fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 vdd QB 0.02fF
+C1 vdd Down 0.09fF
+C2 nUp Up 0.20fF
+C3 vdd inverter_cp_x1_2/in 0.42fF
+C4 inverter_cp_x1_0/out nDown 0.11fF
+C5 vdd nUp 0.14fF
+C6 nDown Down 0.23fF
+C7 vdd Up 0.60fF
+C8 vdd nDown 0.80fF
+C9 inverter_cp_x1_2/in Up 0.12fF
+C10 inverter_cp_x1_0/out Down 0.12fF
+C11 vdd inverter_cp_x1_0/out 0.25fF
+C12 vdd QA 0.02fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n129_n90# a_63_n90# 0.09fF
+C1 a_n221_n90# a_63_n90# 0.06fF
+C2 w_n359_n309# a_n129_n90# 0.06fF
+C3 a_n221_n90# w_n359_n309# 0.09fF
+C4 a_63_n90# a_159_n90# 0.26fF
+C5 w_n359_n309# a_159_n90# 0.09fF
+C6 w_n359_n309# a_63_n90# 0.06fF
+C7 a_n129_n90# a_n33_n90# 0.26fF
+C8 a_n221_n90# a_n33_n90# 0.09fF
+C9 a_n33_n90# a_159_n90# 0.09fF
+C10 a_n33_n90# a_63_n90# 0.26fF
+C11 a_n221_n90# a_n129_n90# 0.26fF
+C12 w_n359_n309# a_n33_n90# 0.05fF
+C13 a_n129_n90# a_159_n90# 0.06fF
+C14 a_n63_n116# a_n159_n207# 0.12fF
+C15 a_n221_n90# a_159_n90# 0.04fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n33_n45# 0.13fF
+C1 a_n125_n45# a_n33_n45# 0.13fF
+C2 a_63_n45# a_n125_n45# 0.05fF
+C3 a_n129_71# a_33_n71# 0.04fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
+C1 A out 0.06fF
+C2 vdd out 0.11fF
+C3 B out 0.40fF
+C4 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out 0.08fF
+C5 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C6 vdd A 0.09fF
+C7 B A 0.24fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C1 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C2 vdd nor_pfd_2/A -0.01fF
+C3 nor_pfd_2/B Reset 0.43fF
+C4 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C5 Reset Q 0.14fF
+C6 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C7 nor_pfd_2/B nor_pfd_3/A 0.58fF
+C8 nor_pfd_3/A Q 0.98fF
+C9 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C10 vdd nor_pfd_2/B 0.02fF
+C11 vdd Q 0.08fF
+C12 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C13 Q nor_pfd_2/A 1.38fF
+C14 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C15 CLK Q 0.04fF
+C16 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C17 Reset nor_pfd_3/A 0.12fF
+C18 nor_pfd_2/B Q 2.22fF
+C19 vdd nor_pfd_3/A 0.09fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_n45# a_159_n45# 0.03fF
+C1 a_n221_n45# a_159_n45# 0.02fF
+C2 a_63_n45# a_159_n45# 0.13fF
+C3 a_n221_n45# a_n129_n45# 0.13fF
+C4 a_n33_n45# a_159_n45# 0.05fF
+C5 a_63_n45# a_n129_n45# 0.05fF
+C6 a_n63_n71# a_n159_n173# 0.10fF
+C7 a_n33_n45# a_n129_n45# 0.13fF
+C8 a_63_n45# a_n221_n45# 0.03fF
+C9 a_n221_n45# a_n33_n45# 0.05fF
+C10 a_63_n45# a_n33_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n125_n90# a_63_n90# 0.09fF
+C1 a_n33_n90# a_63_n90# 0.26fF
+C2 a_33_n187# a_n99_n187# 0.04fF
+C3 a_n125_n90# a_n33_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_15_n45# a_n73_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n73_n90# w_n211_n309# 0.04fF
+C1 a_15_n90# w_n211_n309# 0.09fF
+C2 a_15_n90# a_n73_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 A vdd 0.05fF
+C1 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C2 out sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.03fF
+C3 B a_656_410# 0.30fF
+C4 out a_656_410# 0.20fF
+C5 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C6 B A 0.33fF
+C7 a_656_410# A 0.04fF
+C8 a_656_410# vdd 0.20fF
+C9 out vdd 0.10fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 Down Up 0.06fF
+C1 vdd Up 1.62fF
+C2 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
+C3 vdd Reset 0.02fF
+C4 dff_pfd_1/nor_pfd_2/B vdd 0.04fF
+C5 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C6 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C7 Down vdd 0.08fF
+C8 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
+C9 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v1_pex_c iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
++ pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
++ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
++ n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 nswitch vdd nUp vss Down biasp vco_vctrl pswitch iref_cp nDown Up charge_pump
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vss
++ vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C1 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C3 n_out_by_2 vco_vctrl 0.52fF
+C4 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
+C5 vco_vctrl nswitch -0.06fF
+C6 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
+C7 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C8 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C9 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
+C10 biasp nUp -0.17fF
+C11 QA vdd -0.04fF
+C12 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
+C13 out_by_2 div_5_nQ0 0.32fF
+C14 out_div_by_5 div_5_Q1 0.01fF
+C15 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C16 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C17 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
+C18 div_5_Q0 vco_vctrl 0.48fF
+C19 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
+C20 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C21 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C22 div_5_Q0 out_by_2 0.09fF
+C23 buffer_salida_0/a_678_n100# vdd 0.24fF
+C24 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C25 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C26 div_by_5_0/DFlipFlop_2/latch_diff_0/D n_out_by_2 0.12fF
+C27 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C28 n_out_by_2 div_5_Q1 1.04fF
+C29 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# n_out_by_2 -0.05fF
+C30 lf_vc vdd 0.02fF
+C31 biasp Down 1.24fF
+C32 nUp vdd 0.05fF
+C33 iref_cp vdd 0.15fF
+C34 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C35 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
+C36 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
+C37 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C38 pswitch nUp 0.85fF
+C39 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C40 buffer_salida_0/a_678_n100# out_to_buffer 0.22fF
+C41 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
+C42 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
+C43 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
+C44 out_by_2 vco_vctrl 0.53fF
+C45 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C46 out_div_by_5 vdd 0.28fF
+C47 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
+C48 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C49 Down iref_cp 0.09fF
+C50 div_5_nQ2 n_out_by_2 0.10fF
+C51 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C52 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C53 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C54 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C55 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
+C56 n_out_by_2 vdd 1.03fF
+C57 biasp nDown 0.26fF
+C58 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
+C59 vco_vctrl div_5_Q1 0.14fF
+C60 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C61 vdd out_to_buffer 0.07fF
+C62 biasp Up 0.26fF
+C63 out_to_div vdd 0.21fF
+C64 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C65 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C66 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C67 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
+C68 out_by_2 div_5_Q1 0.42fF
+C69 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C70 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C71 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
+C72 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
+C73 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C74 vco_D0 vdd 0.03fF
+C75 nUp nDown -0.09fF
+C76 Down nswitch 0.54fF
+C77 Up nUp 2.72fF
+C78 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C79 div_5_nQ0 n_out_by_2 0.10fF
+C80 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C81 div_by_5_0/DFlipFlop_2/latch_diff_1/nD n_out_by_2 0.24fF
+C82 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C83 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
+C84 out_to_div out_to_buffer 0.13fF
+C85 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 0.27fF
+C86 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C87 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
+C88 nUp vco_vctrl 0.02fF
+C89 nDown vdd 0.22fF
+C90 div_by_5_0/DFlipFlop_2/latch_diff_1/D n_out_by_2 0.10fF
+C91 out_by_2 div_5_nQ2 0.16fF
+C92 Up vdd 0.28fF
+C93 div_5_Q0 n_out_by_2 -0.12fF
+C94 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C95 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
+C96 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
+C97 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C98 pswitch nDown 0.53fF
+C99 vco_vctrl vdd -1.02fF
+C100 pswitch Up 1.98fF
+C101 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C102 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C103 Down nDown 2.55fF
+C104 out_by_2 vdd 0.97fF
+C105 div_5_Q1_shift out_div_by_5 0.05fF
+C106 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C107 nDown nswitch 0.76fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.93fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss 1.39fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.76fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 6.05fF
+C141 Up vss 2.16fF
+C142 Down vss 6.16fF
+C143 nDown vss 3.38fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C158 div_5_Q1 vss 4.28fF
+C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_nQ0 vss 0.59fF
+C169 div_5_Q0 vss 0.01fF
+C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_to_buffer vss 1.57fF
+C196 out_to_div vss 4.46fF
+C197 out_first_buffer vss 2.88fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 vco_D0 vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 n_out_buffer_div_2 vss 1.63fF
+C216 out_buffer_div_2 vss 1.60fF
+C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 nswitch vss 3.73fF
+C232 biasp vss 5.44fF
+C233 iref_cp vss 2.81fF
+C234 vco_vctrl vss -19.28fF
+C235 pswitch vss 3.57fF
+C236 lf_vc vss -59.89fF
+C237 loop_filter_0/res_loop_filter_2/out vss 7.90fF
+.ends
+
diff --git a/xschem/simulations/top_pll_v1_pex_no_integration.spice b/xschem/simulations/top_pll_v1_pex_no_integration.spice
new file mode 100644
index 0000000..d618cd6
--- /dev/null
+++ b/xschem/simulations/top_pll_v1_pex_no_integration.spice
@@ -0,0 +1,114 @@
+**.subckt top_pll_v1_pex_no_integration vdd vss in_ref pfd_QA pfd_QB Up nUp Down nDown pfd_reset
+*+ cp_nswitch cp_pswitch cp_biasp iref_cp lf_vc D0_vco vco_vctrl vco_out out_first_buffer out_to_pad out_to_div
+*+ out_by_2 n_out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2 div_5_Q1 div_5_Q1_shift
+*+ div_5_nQ0 div_5_Q0 div_5_nQ2 out_div_by_5 out_to_buffer D0_cap
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.iopin D0_vco
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.opin out_to_pad
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin div_5_Q1
+*.iopin div_5_Q1_shift
+*.iopin div_5_nQ0
+*.iopin div_5_Q0
+*.iopin div_5_nQ2
+*.iopin out_div_by_5
+*.iopin out_to_buffer
+*.iopin D0_cap
+x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD_pex_c
+x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump_pex_c
+x3 vdd vco_out vco_vctrl vss D0_vco csvco_pex_c
+x5 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift
++ div_by_5_pex_c
+x7 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface_pex_c
+x8 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer_pex_c
+x4 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2_pex_c
+x9 vdd out_to_pad out_to_buffer vss buffer_salida_pex_c
+x6 vss vco_vctrl lf_vc D0_cap loop_filter_v2
+**.ends
+
+* expanding symbol: loop_filter_v2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter_v2.sch
+.subckt loop_filter_v2 vss in vc_pex D0_cap
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+*.iopin D0_cap
+x1 in net1 vss res_loop_filter
+x2 vc_pex net1 vss res_loop_filter
+x3 vc_pex net1 vss res_loop_filter
+x4 vc_pex vss cap1_loop_filter
+x5 in vss cap2_loop_filter
+XM1 in D0_cap net2 vss sky130_fd_pr__nfet_01v8 L=0.3 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x6 net2 vss cap3_loop_filter
+.ends
+
+
+* expanding symbol: res_loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sch
+.subckt res_loop_filter in out vss
+*.iopin in
+*.iopin vss
+*.iopin out
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 L=22.92 mult=1 m=1
+.ends
+
+
+* expanding symbol: cap1_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
+.subckt cap1_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+.ends
+
+
+* expanding symbol: cap2_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
+.subckt cap2_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+.ends
+
+
+* expanding symbol: cap3_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sch
+.subckt cap3_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=4 m=4
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/top_pll_v2.spice b/xschem/simulations/top_pll_v2.spice
new file mode 100644
index 0000000..23805c4
--- /dev/null
+++ b/xschem/simulations/top_pll_v2.spice
@@ -0,0 +1,589 @@
+**.subckt top_pll_v2 vdd vss in_ref pfd_QA pfd_QB Up nUp Down nDown pfd_reset cp_nswitch cp_pswitch
+*+ cp_biasp iref_cp lf_vc D0_vco vco_vctrl vco_out out_first_buffer out_to_buffer out_to_div out_by_2
+*+ n_out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2 div_5_Q1 div_5_Q1_shift div_5_nQ0
+*+ div_5_Q0 div_5_nQ2 out_div_by_5 out_to_pad D0_cap
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.iopin D0_vco
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.iopin out_to_buffer
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin div_5_Q1
+*.iopin div_5_Q1_shift
+*.iopin div_5_nQ0
+*.iopin div_5_Q0
+*.iopin div_5_nQ2
+*.iopin out_div_by_5
+*.iopin out_to_pad
+*.ipin D0_cap
+x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD
+x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump
+x3 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface
+x5 vdd vco_out D0_vco vco_vctrl vss csvco
+x6 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer
+x7 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift
++ div_by_5
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2
+x9 vdd out_to_pad out_to_buffer vss buffer_salida
+x4 vss vco_vctrl lf_vc D0_cap loop_filter_v2
+**.ends
+
+* expanding symbol: PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding symbol: charge_pump.sym # of pins=11
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sch
+.subckt charge_pump vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
+*.iopin vss
+*.iopin vdd
+*.ipin Down
+*.ipin nUp
+*.ipin Up
+*.ipin nDown
+*.opin out
+*.iopin nswitch
+*.iopin pswitch
+*.ipin iref
+*.iopin biasp
+XM1 out pswitch vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM2 out nswitch vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM3 pswitch nUp biasp vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 pswitch Up vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM5 nswitch Down iref vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM6 nswitch nDown vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM7 pswitch nUp pswitch vdd sky130_fd_pr__pfet_01v8 L=2 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM8 nswitch Down nswitch vss sky130_fd_pr__nfet_01v8 L=1.5 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM9 iref iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM10 biasp iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM11 biasp biasp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+.ends
+
+
+* expanding symbol: pfd_cp_interface.sym # of pins=8
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
+.subckt pfd_cp_interface Up vdd QA nUp Down QB vss nDown
+*.iopin vdd
+*.iopin vss
+*.ipin QA
+*.ipin QB
+*.opin nDown
+*.opin Down
+*.opin nUp
+*.opin Up
+x5 vdd nDown nQB vss trans_gate
+x3 vdd Up nQA vss inverter_cp_x1
+x1 vdd nQB QB vss inverter_cp_x1
+x2 vdd nQA QA vss inverter_cp_x1
+x4 vdd nUp Up vss inverter_cp_x2
+x6 vdd Down nDown vss inverter_cp_x2
+.ends
+
+
+* expanding symbol: csvco.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sch
+.subckt csvco vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd vbp out out1 vctrl vss D0 csvco_branch
+x2 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x3 vdd vbp out2 out vctrl vss D0 csvco_branch
+.ends
+
+
+* expanding symbol: ring_osc_buffer.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
+.subckt ring_osc_buffer vdd in_vco out_pad out_div vss o1
+*.iopin vdd
+*.iopin vss
+*.ipin in_vco
+*.opin out_pad
+*.opin out_div
+*.iopin o1
+x1 vdd o1 in_vco vss inverter_min_x2
+x2 vdd out_div o1 vss inverter_min_x4
+x3 vdd out_pad out_div vss inverter_min_x4
+.ends
+
+
+* expanding symbol: div_by_5.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
+.subckt div_by_5 vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: buffer_salida.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sch
+.subckt buffer_salida vdd out in vss
+*.iopin vss
+*.ipin in
+*.iopin vdd
+*.opin out
+XM2 net1 in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 net1 in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM3 net2 net1 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM4 net2 net1 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM5 out net2 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+XM6 out net2 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+.ends
+
+
+* expanding symbol: loop_filter_v2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter_v2.sch
+.subckt loop_filter_v2 vss in vc_pex D0_cap
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+*.iopin D0_cap
+x1 in net1 vss res_loop_filter
+x2 vc_pex net1 vss res_loop_filter
+x3 vc_pex net1 vss res_loop_filter
+x4 vc_pex vss cap1_loop_filter
+x5 in vss cap2_loop_filter
+XM1 in D0_cap net2 vss sky130_fd_pr__nfet_01v8 L=0.3 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x6 net2 vss cap3_loop_filter
+.ends
+
+
+* expanding symbol: DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding symbol: and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+
+* expanding symbol: csvco_branch.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sch
+.subckt csvco_branch vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: res_loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sch
+.subckt res_loop_filter in out vss
+*.iopin in
+*.iopin vss
+*.iopin out
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 L=22.92 mult=1 m=1
+.ends
+
+
+* expanding symbol: cap1_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
+.subckt cap1_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+.ends
+
+
+* expanding symbol: cap2_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
+.subckt cap2_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+.ends
+
+
+* expanding symbol: cap3_loop_filter.sym # of pins=2
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sch
+.subckt cap3_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=4 m=4
+.ends
+
+
+* expanding symbol: nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/top_pll_v2_pex_c.spice b/xschem/simulations/top_pll_v2_pex_c.spice
new file mode 100644
index 0000000..dece08e
--- /dev/null
+++ b/xschem/simulations/top_pll_v2_pex_c.spice
@@ -0,0 +1,2927 @@
+* NGSPICE file created from top_pll_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_1803_n486# w_n2457_n634# 0.02fF
+C1 a_n29_n486# w_n2457_n634# 0.02fF
+C2 a_n487_n486# w_n2457_n634# 0.02fF
+C3 a_n945_n486# w_n2457_n634# 0.02fF
+C4 a_n1861_n486# w_n2457_n634# 0.02fF
+C5 a_n1403_n486# w_n2457_n634# 0.02fF
+C6 a_2261_n486# w_n2457_n634# 0.02fF
+C7 a_n2319_n486# w_n2457_n634# 0.02fF
+C8 a_429_n486# w_n2457_n634# 0.02fF
+C9 a_1345_n486# w_n2457_n634# 0.02fF
+C10 a_887_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n81_n75# a_n369_n75# 0.05fF
+C1 a_n849_n75# a_n465_n75# 0.03fF
+C2 a_591_n75# a_879_n75# 0.05fF
+C3 a_495_n75# a_399_n75# 0.22fF
+C4 a_n369_n75# a_n465_n75# 0.22fF
+C5 a_783_n75# a_1167_n75# 0.03fF
+C6 a_687_n75# a_783_n75# 0.22fF
+C7 a_591_n75# a_303_n75# 0.05fF
+C8 a_n657_n75# a_n273_n75# 0.03fF
+C9 a_n945_n75# a_n561_n75# 0.03fF
+C10 a_n177_n75# a_n273_n75# 0.22fF
+C11 a_111_n75# a_15_n75# 0.22fF
+C12 a_1071_n75# a_879_n75# 0.08fF
+C13 a_n753_n75# a_n1041_n75# 0.05fF
+C14 a_n1137_n75# a_n753_n75# 0.03fF
+C15 a_591_n75# a_495_n75# 0.22fF
+C16 a_591_n75# a_399_n75# 0.08fF
+C17 a_n81_n75# a_207_n75# 0.05fF
+C18 a_n753_n75# a_n561_n75# 0.08fF
+C19 a_n273_n75# a_n369_n75# 0.22fF
+C20 a_n753_n75# a_n945_n75# 0.08fF
+C21 a_591_n75# a_975_n75# 0.03fF
+C22 a_879_n75# a_783_n75# 0.22fF
+C23 a_n849_n75# a_n657_n75# 0.08fF
+C24 a_n657_n75# a_n369_n75# 0.05fF
+C25 a_n177_n75# a_n369_n75# 0.08fF
+C26 a_303_n75# a_207_n75# 0.22fF
+C27 a_1071_n75# a_975_n75# 0.22fF
+C28 a_495_n75# a_783_n75# 0.05fF
+C29 a_111_n75# a_n81_n75# 0.08fF
+C30 a_399_n75# a_783_n75# 0.03fF
+C31 a_n561_n75# a_n465_n75# 0.22fF
+C32 a_207_n75# a_495_n75# 0.05fF
+C33 a_15_n75# a_n81_n75# 0.22fF
+C34 a_207_n75# a_399_n75# 0.08fF
+C35 a_975_n75# a_783_n75# 0.08fF
+C36 a_591_n75# a_783_n75# 0.08fF
+C37 a_n177_n75# a_207_n75# 0.03fF
+C38 a_111_n75# a_303_n75# 0.08fF
+C39 a_591_n75# a_207_n75# 0.03fF
+C40 a_n753_n75# a_n465_n75# 0.05fF
+C41 a_111_n75# a_n273_n75# 0.03fF
+C42 a_15_n75# a_303_n75# 0.05fF
+C43 a_n273_n75# a_n561_n75# 0.05fF
+C44 a_n657_n75# a_n1041_n75# 0.03fF
+C45 a_111_n75# a_495_n75# 0.03fF
+C46 a_1071_n75# a_783_n75# 0.05fF
+C47 a_111_n75# a_399_n75# 0.05fF
+C48 a_15_n75# a_n273_n75# 0.05fF
+C49 a_n657_n75# a_n561_n75# 0.22fF
+C50 a_111_n75# a_n177_n75# 0.05fF
+C51 a_n177_n75# a_n561_n75# 0.03fF
+C52 a_n657_n75# a_n945_n75# 0.05fF
+C53 a_15_n75# a_399_n75# 0.03fF
+C54 a_879_n75# a_1167_n75# 0.05fF
+C55 a_n1229_n75# a_n849_n75# 0.03fF
+C56 a_879_n75# a_687_n75# 0.08fF
+C57 a_n81_n75# a_n465_n75# 0.03fF
+C58 a_n849_n75# a_n1041_n75# 0.08fF
+C59 a_n1137_n75# a_n849_n75# 0.05fF
+C60 a_15_n75# a_n177_n75# 0.08fF
+C61 a_687_n75# a_303_n75# 0.03fF
+C62 a_n849_n75# a_n561_n75# 0.05fF
+C63 a_n849_n75# a_n945_n75# 0.22fF
+C64 a_n753_n75# a_n657_n75# 0.22fF
+C65 a_n369_n75# a_n561_n75# 0.08fF
+C66 a_687_n75# a_495_n75# 0.08fF
+C67 a_n81_n75# a_303_n75# 0.03fF
+C68 a_687_n75# a_399_n75# 0.05fF
+C69 a_15_n75# a_n369_n75# 0.03fF
+C70 a_n81_n75# a_n273_n75# 0.08fF
+C71 a_975_n75# a_1167_n75# 0.08fF
+C72 a_n273_n75# a_n465_n75# 0.08fF
+C73 a_975_n75# a_687_n75# 0.05fF
+C74 a_n849_n75# a_n753_n75# 0.22fF
+C75 a_591_n75# a_687_n75# 0.22fF
+C76 a_n753_n75# a_n369_n75# 0.03fF
+C77 a_111_n75# a_207_n75# 0.22fF
+C78 a_n81_n75# a_n177_n75# 0.22fF
+C79 a_n1229_n75# a_n1041_n75# 0.08fF
+C80 a_n1229_n75# a_n1137_n75# 0.22fF
+C81 a_n657_n75# a_n465_n75# 0.08fF
+C82 a_n177_n75# a_n465_n75# 0.05fF
+C83 a_879_n75# a_495_n75# 0.03fF
+C84 a_n1137_n75# a_n1041_n75# 0.22fF
+C85 a_1071_n75# a_1167_n75# 0.22fF
+C86 a_15_n75# a_207_n75# 0.08fF
+C87 a_303_n75# a_495_n75# 0.08fF
+C88 a_1071_n75# a_687_n75# 0.03fF
+C89 a_303_n75# a_399_n75# 0.22fF
+C90 a_n1229_n75# a_n945_n75# 0.05fF
+C91 a_879_n75# a_975_n75# 0.22fF
+C92 a_n1041_n75# a_n945_n75# 0.22fF
+C93 a_n1137_n75# a_n945_n75# 0.08fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_159_n75# a_63_n75# 0.22fF
+C1 a_351_n75# a_735_n75# 0.03fF
+C2 a_n801_n75# a_n417_n75# 0.03fF
+C3 a_831_n75# a_735_n75# 0.22fF
+C4 a_n927_n101# a_33_n101# 0.08fF
+C5 a_543_n75# a_159_n75# 0.03fF
+C6 a_255_n75# a_639_n75# 0.03fF
+C7 a_n513_n75# a_n609_n75# 0.22fF
+C8 a_n897_n75# a_n609_n75# 0.05fF
+C9 a_n225_n75# a_n321_n75# 0.22fF
+C10 a_n801_n75# a_n989_n75# 0.08fF
+C11 a_351_n75# a_n33_n75# 0.03fF
+C12 a_n417_n75# a_n129_n75# 0.05fF
+C13 a_n897_n75# a_n513_n75# 0.03fF
+C14 a_351_n75# a_159_n75# 0.08fF
+C15 a_447_n75# a_639_n75# 0.08fF
+C16 a_447_n75# a_255_n75# 0.08fF
+C17 a_351_n75# a_63_n75# 0.05fF
+C18 a_n801_n75# a_n609_n75# 0.08fF
+C19 a_351_n75# a_543_n75# 0.08fF
+C20 a_543_n75# a_831_n75# 0.05fF
+C21 a_927_n75# a_735_n75# 0.08fF
+C22 a_n801_n75# a_n513_n75# 0.05fF
+C23 a_n321_n75# a_n705_n75# 0.03fF
+C24 a_n33_n75# a_n129_n75# 0.22fF
+C25 a_n801_n75# a_n897_n75# 0.22fF
+C26 a_n225_n75# a_n417_n75# 0.08fF
+C27 a_159_n75# a_n129_n75# 0.05fF
+C28 a_639_n75# a_735_n75# 0.22fF
+C29 a_n321_n75# a_n417_n75# 0.22fF
+C30 a_n129_n75# a_63_n75# 0.08fF
+C31 a_n513_n75# a_n129_n75# 0.03fF
+C32 a_n225_n75# a_n33_n75# 0.08fF
+C33 a_n33_n75# a_255_n75# 0.05fF
+C34 a_447_n75# a_735_n75# 0.05fF
+C35 a_n225_n75# a_159_n75# 0.03fF
+C36 a_n321_n75# a_n33_n75# 0.05fF
+C37 a_543_n75# a_927_n75# 0.03fF
+C38 a_159_n75# a_255_n75# 0.22fF
+C39 a_n225_n75# a_n609_n75# 0.03fF
+C40 a_n417_n75# a_n705_n75# 0.05fF
+C41 a_n225_n75# a_63_n75# 0.05fF
+C42 a_255_n75# a_63_n75# 0.08fF
+C43 a_n321_n75# a_n609_n75# 0.05fF
+C44 a_543_n75# a_639_n75# 0.22fF
+C45 a_n225_n75# a_n513_n75# 0.05fF
+C46 a_543_n75# a_255_n75# 0.05fF
+C47 a_n321_n75# a_63_n75# 0.03fF
+C48 a_n989_n75# a_n705_n75# 0.05fF
+C49 a_447_n75# a_159_n75# 0.05fF
+C50 a_n321_n75# a_n513_n75# 0.08fF
+C51 a_927_n75# a_831_n75# 0.22fF
+C52 a_447_n75# a_63_n75# 0.03fF
+C53 a_351_n75# a_639_n75# 0.05fF
+C54 a_351_n75# a_255_n75# 0.22fF
+C55 a_n609_n75# a_n705_n75# 0.22fF
+C56 a_447_n75# a_543_n75# 0.22fF
+C57 a_831_n75# a_639_n75# 0.08fF
+C58 a_n417_n75# a_n33_n75# 0.03fF
+C59 a_n513_n75# a_n705_n75# 0.08fF
+C60 a_n897_n75# a_n705_n75# 0.08fF
+C61 a_n417_n75# a_n609_n75# 0.08fF
+C62 a_351_n75# a_447_n75# 0.22fF
+C63 a_447_n75# a_831_n75# 0.03fF
+C64 a_n225_n75# a_n129_n75# 0.22fF
+C65 a_n417_n75# a_n513_n75# 0.22fF
+C66 a_n129_n75# a_255_n75# 0.03fF
+C67 a_543_n75# a_735_n75# 0.08fF
+C68 a_n989_n75# a_n609_n75# 0.03fF
+C69 a_n33_n75# a_159_n75# 0.08fF
+C70 a_n801_n75# a_n705_n75# 0.22fF
+C71 a_n321_n75# a_n129_n75# 0.08fF
+C72 a_n33_n75# a_63_n75# 0.22fF
+C73 a_927_n75# a_639_n75# 0.05fF
+C74 a_n989_n75# a_n897_n75# 0.22fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n989_n150# a_n801_n150# 0.16fF
+C1 a_n417_n150# a_n513_n150# 0.43fF
+C2 a_159_n150# a_543_n150# 0.07fF
+C3 a_n129_n150# a_63_n150# 0.16fF
+C4 a_33_n247# a_n927_n247# 0.09fF
+C5 a_n33_n150# a_n417_n150# 0.07fF
+C6 a_n321_n150# a_n705_n150# 0.07fF
+C7 a_n33_n150# a_351_n150# 0.07fF
+C8 a_447_n150# a_351_n150# 0.43fF
+C9 a_63_n150# a_255_n150# 0.16fF
+C10 a_n989_n150# a_n705_n150# 0.10fF
+C11 a_735_n150# a_639_n150# 0.43fF
+C12 a_n225_n150# a_n609_n150# 0.07fF
+C13 a_831_n150# a_447_n150# 0.07fF
+C14 a_n225_n150# a_n417_n150# 0.16fF
+C15 a_n129_n150# a_n321_n150# 0.16fF
+C16 a_927_n150# a_831_n150# 0.43fF
+C17 a_n225_n150# a_n513_n150# 0.10fF
+C18 a_159_n150# a_351_n150# 0.16fF
+C19 a_n225_n150# a_n33_n150# 0.16fF
+C20 a_159_n150# a_n33_n150# 0.16fF
+C21 a_159_n150# a_447_n150# 0.10fF
+C22 a_639_n150# a_255_n150# 0.07fF
+C23 a_735_n150# a_543_n150# 0.16fF
+C24 a_63_n150# a_351_n150# 0.10fF
+C25 a_n897_n150# a_n609_n150# 0.10fF
+C26 a_n129_n150# a_255_n150# 0.07fF
+C27 a_639_n150# a_543_n150# 0.43fF
+C28 a_n801_n150# a_n609_n150# 0.16fF
+C29 a_159_n150# a_n225_n150# 0.07fF
+C30 a_n33_n150# a_63_n150# 0.43fF
+C31 a_447_n150# a_63_n150# 0.07fF
+C32 a_n801_n150# a_n417_n150# 0.07fF
+C33 a_n897_n150# a_n513_n150# 0.07fF
+C34 a_n609_n150# a_n705_n150# 0.43fF
+C35 a_n609_n150# a_n321_n150# 0.10fF
+C36 a_n801_n150# a_n513_n150# 0.10fF
+C37 a_n989_n150# a_n609_n150# 0.07fF
+C38 a_n417_n150# a_n705_n150# 0.10fF
+C39 a_735_n150# a_351_n150# 0.07fF
+C40 a_n417_n150# a_n321_n150# 0.43fF
+C41 a_543_n150# a_255_n150# 0.10fF
+C42 a_n225_n150# a_63_n150# 0.10fF
+C43 a_n513_n150# a_n705_n150# 0.16fF
+C44 a_n321_n150# a_n513_n150# 0.16fF
+C45 a_159_n150# a_63_n150# 0.43fF
+C46 a_639_n150# a_351_n150# 0.10fF
+C47 a_735_n150# a_447_n150# 0.10fF
+C48 a_n33_n150# a_n321_n150# 0.10fF
+C49 a_735_n150# a_831_n150# 0.43fF
+C50 a_735_n150# a_927_n150# 0.16fF
+C51 a_n129_n150# a_n417_n150# 0.10fF
+C52 a_639_n150# a_447_n150# 0.16fF
+C53 a_831_n150# a_639_n150# 0.16fF
+C54 a_n129_n150# a_n513_n150# 0.07fF
+C55 a_927_n150# a_639_n150# 0.10fF
+C56 a_n225_n150# a_n321_n150# 0.43fF
+C57 a_351_n150# a_255_n150# 0.43fF
+C58 a_n129_n150# a_n33_n150# 0.43fF
+C59 a_n33_n150# a_255_n150# 0.10fF
+C60 a_447_n150# a_255_n150# 0.16fF
+C61 a_543_n150# a_351_n150# 0.16fF
+C62 a_n225_n150# a_n129_n150# 0.43fF
+C63 a_159_n150# a_n129_n150# 0.10fF
+C64 a_543_n150# a_447_n150# 0.43fF
+C65 a_n897_n150# a_n801_n150# 0.43fF
+C66 a_831_n150# a_543_n150# 0.10fF
+C67 a_63_n150# a_n321_n150# 0.07fF
+C68 a_927_n150# a_543_n150# 0.07fF
+C69 a_n609_n150# a_n417_n150# 0.16fF
+C70 a_159_n150# a_255_n150# 0.43fF
+C71 a_n897_n150# a_n705_n150# 0.16fF
+C72 a_n609_n150# a_n513_n150# 0.43fF
+C73 a_n801_n150# a_n705_n150# 0.43fF
+C74 a_n897_n150# a_n989_n150# 0.43fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n1103_n44# a_n745_n44# 0.04fF
+C1 a_n1461_n44# a_n1819_n44# 0.04fF
+C2 a_n387_n44# a_n745_n44# 0.04fF
+C3 a_687_n44# a_1045_n44# 0.04fF
+C4 a_329_n44# a_n29_n44# 0.04fF
+C5 a_1403_n44# a_1045_n44# 0.04fF
+C6 a_n387_n44# a_n29_n44# 0.04fF
+C7 a_329_n44# a_687_n44# 0.04fF
+C8 a_n1461_n44# a_n1103_n44# 0.04fF
+C9 a_1403_n44# a_1761_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_207_n150# a_399_n150# 0.16fF
+C1 a_n273_n150# a_n369_n150# 0.43fF
+C2 a_783_n150# a_495_n150# 0.10fF
+C3 a_399_n150# a_303_n150# 0.43fF
+C4 a_591_n150# a_495_n150# 0.43fF
+C5 a_n177_n150# a_n561_n150# 0.07fF
+C6 a_n945_n150# a_n1041_n150# 0.43fF
+C7 a_n81_n150# a_n177_n150# 0.43fF
+C8 a_879_n150# a_783_n150# 0.43fF
+C9 a_111_n150# a_399_n150# 0.10fF
+C10 a_591_n150# a_879_n150# 0.10fF
+C11 a_207_n150# a_15_n150# 0.16fF
+C12 a_n849_n150# a_n465_n150# 0.07fF
+C13 a_15_n150# a_303_n150# 0.10fF
+C14 a_n753_n150# a_n1137_n150# 0.07fF
+C15 a_975_n150# w_n1367_n369# 0.05fF
+C16 a_591_n150# a_783_n150# 0.16fF
+C17 a_1071_n150# w_n1367_n369# 0.07fF
+C18 a_687_n150# a_495_n150# 0.16fF
+C19 a_n849_n150# a_n1041_n150# 0.16fF
+C20 a_1071_n150# a_975_n150# 0.43fF
+C21 a_111_n150# a_15_n150# 0.43fF
+C22 a_n1229_n150# a_n1041_n150# 0.16fF
+C23 a_1167_n150# w_n1367_n369# 0.14fF
+C24 a_879_n150# a_687_n150# 0.16fF
+C25 a_975_n150# a_1167_n150# 0.16fF
+C26 a_207_n150# a_495_n150# 0.10fF
+C27 a_n849_n150# a_n945_n150# 0.43fF
+C28 a_495_n150# a_303_n150# 0.16fF
+C29 a_1071_n150# a_1167_n150# 0.43fF
+C30 a_n1229_n150# a_n945_n150# 0.10fF
+C31 a_n273_n150# a_15_n150# 0.10fF
+C32 a_687_n150# a_783_n150# 0.43fF
+C33 a_591_n150# a_687_n150# 0.43fF
+C34 a_207_n150# a_n177_n150# 0.07fF
+C35 a_n369_n150# a_15_n150# 0.07fF
+C36 a_111_n150# a_495_n150# 0.07fF
+C37 a_n81_n150# a_207_n150# 0.10fF
+C38 a_n753_n150# a_n465_n150# 0.10fF
+C39 a_n81_n150# a_303_n150# 0.07fF
+C40 a_591_n150# a_207_n150# 0.07fF
+C41 a_n657_n150# a_n465_n150# 0.16fF
+C42 a_n1229_n150# a_n849_n150# 0.07fF
+C43 a_591_n150# a_303_n150# 0.10fF
+C44 a_111_n150# a_n177_n150# 0.10fF
+C45 a_n753_n150# a_n1041_n150# 0.10fF
+C46 a_n657_n150# a_n273_n150# 0.07fF
+C47 a_n81_n150# a_111_n150# 0.16fF
+C48 a_n753_n150# a_n369_n150# 0.07fF
+C49 a_n657_n150# a_n1041_n150# 0.07fF
+C50 a_n465_n150# a_n561_n150# 0.43fF
+C51 a_n465_n150# a_n177_n150# 0.10fF
+C52 a_n657_n150# a_n369_n150# 0.10fF
+C53 a_n81_n150# a_n465_n150# 0.07fF
+C54 a_n753_n150# a_n945_n150# 0.16fF
+C55 a_n273_n150# a_n561_n150# 0.10fF
+C56 a_399_n150# a_15_n150# 0.07fF
+C57 a_n273_n150# a_n177_n150# 0.43fF
+C58 a_n657_n150# a_n945_n150# 0.10fF
+C59 a_n81_n150# a_n273_n150# 0.16fF
+C60 a_n369_n150# a_n561_n150# 0.16fF
+C61 a_n177_n150# a_n369_n150# 0.16fF
+C62 a_687_n150# a_303_n150# 0.07fF
+C63 a_n81_n150# a_n369_n150# 0.10fF
+C64 a_879_n150# w_n1367_n369# 0.04fF
+C65 a_n945_n150# a_n561_n150# 0.07fF
+C66 a_879_n150# a_975_n150# 0.43fF
+C67 a_n753_n150# a_n849_n150# 0.43fF
+C68 a_207_n150# a_303_n150# 0.43fF
+C69 a_879_n150# a_1071_n150# 0.16fF
+C70 a_n657_n150# a_n849_n150# 0.16fF
+C71 a_495_n150# a_399_n150# 0.43fF
+C72 a_975_n150# a_783_n150# 0.16fF
+C73 a_591_n150# a_975_n150# 0.07fF
+C74 a_879_n150# a_1167_n150# 0.10fF
+C75 a_1071_n150# a_783_n150# 0.10fF
+C76 a_111_n150# a_207_n150# 0.43fF
+C77 a_n849_n150# a_n561_n150# 0.10fF
+C78 a_n1041_n150# a_n1137_n150# 0.43fF
+C79 a_111_n150# a_303_n150# 0.16fF
+C80 a_1167_n150# a_783_n150# 0.07fF
+C81 a_783_n150# a_399_n150# 0.07fF
+C82 a_591_n150# a_399_n150# 0.16fF
+C83 a_n945_n150# a_n1137_n150# 0.16fF
+C84 a_975_n150# a_687_n150# 0.10fF
+C85 a_n177_n150# a_15_n150# 0.16fF
+C86 a_1071_n150# a_687_n150# 0.07fF
+C87 a_n81_n150# a_15_n150# 0.43fF
+C88 a_111_n150# a_n273_n150# 0.07fF
+C89 a_n753_n150# a_n657_n150# 0.43fF
+C90 a_n849_n150# a_n1137_n150# 0.10fF
+C91 a_n465_n150# a_n273_n150# 0.16fF
+C92 a_n1229_n150# a_n1137_n150# 0.43fF
+C93 a_687_n150# a_399_n150# 0.10fF
+C94 a_n753_n150# a_n561_n150# 0.16fF
+C95 a_n465_n150# a_n369_n150# 0.43fF
+C96 a_879_n150# a_495_n150# 0.07fF
+C97 a_n657_n150# a_n561_n150# 0.43fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch vdd nUp vss Down biasp out pswitch iref nDown Up
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 pswitch vdd 3.98fF
+C1 pswitch nUp 5.66fF
+C2 pswitch nswitch 0.06fF
+C3 nUp Down 0.25fF
+C4 Down nswitch 2.27fF
+C5 vdd nswitch 0.07fF
+C6 iref nswitch 1.91fF
+C7 pswitch biasp 3.11fF
+C8 vdd biasp 2.64fF
+C9 biasp nswitch 0.03fF
+C10 iref biasp 0.80fF
+C11 pswitch out 4.91fF
+C12 nDown Down 0.13fF
+C13 vdd out 6.66fF
+C14 out nUp 0.31fF
+C15 nDown nswitch 0.31fF
+C16 out nswitch 1.28fF
+C17 Up pswitch 0.70fF
+C18 Up nUp 0.15fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C1 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C2 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C3 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C4 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C5 m3_7988_2700# m3_2669_2700# 2.73fF
+C6 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C7 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C8 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C9 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C10 m3_2669_8000# m3_7988_8000# 2.73fF
+C11 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C12 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C13 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C14 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C15 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
+C16 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C17 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C18 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C19 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C20 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
+C21 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C22 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
+C23 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C24 m3_2669_2700# m3_n2650_2700# 2.73fF
+C25 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C26 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C27 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C28 m3_2669_8000# m3_2669_2700# 3.28fF
+C29 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C30 m3_7988_n2600# m3_7988_2700# 3.39fF
+C31 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C32 m3_n2650_8000# m3_2669_8000# 2.73fF
+C33 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C34 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C35 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C36 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C37 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C38 m3_2669_2700# m3_2669_n2600# 3.28fF
+C39 m3_2669_8000# c1_n13188_n13100# 58.61fF
+C40 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C41 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C42 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C43 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C44 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C45 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C46 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C47 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C48 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C49 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C50 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C51 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C52 m3_7988_2700# m3_7988_8000# 3.39fF
+C53 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C54 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
+C55 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C56 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C57 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C58 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C59 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C60 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C61 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C62 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C63 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C64 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C1 m3_n4309_50# m3_10_n4250# 1.75fF
+C2 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C3 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C4 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C5 c1_n4209_n4150# c1_110_n4150# 1.32fF
+C6 m3_10_n4250# c1_110_n4150# 81.11fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 in out 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C1 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C2 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C3 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C4 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C5 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
+C6 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C7 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C8 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C9 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C10 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
+C11 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C12 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C13 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C14 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C15 m3_n6469_2200# m3_n6469_n2100# 2.63fF
+C16 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C17 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C18 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 out in 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_30_n300# a_n88_n300# 0.61fF
+C1 a_n118_n388# a_n88_n300# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 D0_cap in 0.07fF
+C1 cap3_loop_filter_0/in in 0.79fF
+C2 vc_pex in 0.18fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# w_n311_n344# 0.14fF
+C1 a_n81_n125# a_111_n125# 0.13fF
+C2 a_n173_n125# w_n311_n344# 0.14fF
+C3 a_n173_n125# a_n81_n125# 0.36fF
+C4 a_15_n125# w_n311_n344# 0.09fF
+C5 a_15_n125# a_n81_n125# 0.36fF
+C6 a_n173_n125# a_111_n125# 0.08fF
+C7 a_81_n156# a_n15_n156# 0.02fF
+C8 a_15_n125# a_111_n125# 0.36fF
+C9 a_n15_n156# a_n111_n156# 0.02fF
+C10 a_n173_n125# a_15_n125# 0.13fF
+C11 a_n81_n125# w_n311_n344# 0.09fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n81_n125# a_15_n125# 0.36fF
+C2 a_n81_n125# a_111_n125# 0.13fF
+C3 a_n173_n125# a_n81_n125# 0.36fF
+C4 a_n111_n151# a_n15_n151# 0.02fF
+C5 a_15_n125# a_111_n125# 0.36fF
+C6 a_n173_n125# a_15_n125# 0.13fF
+C7 a_81_n151# a_n15_n151# 0.02fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_187_n605# m1_45_n513# 0.36fF
+C1 m1_45_n513# vdd 0.69fF
+C2 m1_187_n605# vdd 0.55fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_111_n125# 0.13fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 w_n311_n344# a_n173_n125# 0.14fF
+C3 a_n81_n125# a_15_n125# 0.36fF
+C4 w_n311_n344# a_111_n125# 0.14fF
+C5 a_111_n125# a_n173_n125# 0.08fF
+C6 a_n81_n125# w_n311_n344# 0.09fF
+C7 a_15_n125# w_n311_n344# 0.09fF
+C8 a_n81_n125# a_n173_n125# 0.36fF
+C9 a_15_n125# a_n173_n125# 0.13fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_111_n125# a_n173_n125# 0.08fF
+C2 a_15_n125# a_111_n125# 0.36fF
+C3 a_n81_n125# a_n173_n125# 0.36fF
+C4 a_15_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 vdd out 0.10fF
+C1 in out 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in CLK_d 0.12fF
+C1 vdd inverter_cp_x1_0/out 0.28fF
+C2 vdd CLK 0.36fF
+C3 inverter_cp_x1_0/out CLK 0.31fF
+C4 vdd nCLK_d 0.03fF
+C5 nCLK_d inverter_cp_x1_0/out 0.11fF
+C6 inverter_cp_x1_2/in vdd 0.21fF
+C7 inverter_cp_x1_2/in CLK 0.31fF
+C8 vdd CLK_d 0.03fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_n125_n95# 0.11fF
+C1 w_n263_n314# a_63_n95# 0.11fF
+C2 a_n33_n95# a_n125_n95# 0.28fF
+C3 a_n33_n95# a_63_n95# 0.28fF
+C4 a_63_n95# a_n125_n95# 0.10fF
+C5 w_n263_n314# a_n33_n95# 0.08fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_n173_n125# 0.36fF
+C1 a_111_n125# a_n173_n125# 0.08fF
+C2 a_n129_n213# a_n81_n125# 0.10fF
+C3 a_n129_n213# a_111_n125# 0.01fF
+C4 a_n129_n213# a_n173_n125# 0.02fF
+C5 a_15_n125# a_n81_n125# 0.36fF
+C6 a_15_n125# a_111_n125# 0.36fF
+C7 a_15_n125# a_n173_n125# 0.13fF
+C8 a_111_n125# a_n81_n125# 0.13fF
+C9 a_n129_n213# a_15_n125# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_n125_n95# 0.88fF
+C1 a_n81_n183# a_n33_n95# 0.10fF
+C2 a_n81_n183# a_n125_n95# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 Q vdd 0.16fF
+C1 Q D 0.05fF
+C2 nD nQ 0.05fF
+C3 CLK m1_657_280# 0.24fF
+C4 m1_657_280# nQ 1.41fF
+C5 nD Q 0.05fF
+C6 Q nQ 0.93fF
+C7 vdd nQ 0.16fF
+C8 nQ D 0.05fF
+C9 Q m1_657_280# 0.94fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
++ nCLK latch_diff_0/nD
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C1 Q latch_diff_1/nD 0.01fF
+C2 latch_diff_0/D latch_diff_1/nD 0.04fF
+C3 latch_diff_1/D nQ 0.11fF
+C4 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
+C5 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C6 nQ latch_diff_1/nD 0.08fF
+C7 latch_diff_1/D vdd 0.03fF
+C8 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C9 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C10 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C11 latch_diff_1/nD vdd 0.02fF
+C12 latch_diff_1/D latch_diff_1/nD 0.33fF
+C13 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C14 latch_diff_0/D vdd 0.09fF
+C15 latch_diff_1/D latch_diff_0/D 0.11fF
+C16 latch_diff_1/D latch_diff_1/m1_657_280# 0.32fF
+C17 latch_diff_0/nD vdd 0.14fF
+C18 latch_diff_0/nD latch_diff_1/D 0.41fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n221_n84# a_n33_n84# 0.09fF
+C1 a_n221_n84# a_159_n84# 0.04fF
+C2 w_n359_n303# a_n33_n84# 0.05fF
+C3 a_33_n110# a_n63_n110# 0.02fF
+C4 w_n359_n303# a_159_n84# 0.08fF
+C5 a_n129_n84# a_63_n84# 0.09fF
+C6 a_n159_n110# a_n63_n110# 0.02fF
+C7 a_159_n84# a_n33_n84# 0.09fF
+C8 a_n221_n84# a_63_n84# 0.05fF
+C9 a_n221_n84# a_n129_n84# 0.24fF
+C10 w_n359_n303# a_63_n84# 0.06fF
+C11 a_n129_n84# w_n359_n303# 0.06fF
+C12 a_n33_n84# a_63_n84# 0.24fF
+C13 a_159_n84# a_63_n84# 0.24fF
+C14 a_129_n110# a_33_n110# 0.02fF
+C15 a_n129_n84# a_n33_n84# 0.24fF
+C16 a_n221_n84# w_n359_n303# 0.08fF
+C17 a_n129_n84# a_159_n84# 0.05fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_63_n42# a_159_n42# 0.12fF
+C1 a_63_n42# a_n33_n42# 0.12fF
+C2 a_n221_n42# a_n129_n42# 0.12fF
+C3 a_159_n42# a_n33_n42# 0.05fF
+C4 a_n221_n42# a_63_n42# 0.03fF
+C5 a_129_n68# a_33_n68# 0.02fF
+C6 a_n221_n42# a_159_n42# 0.02fF
+C7 a_63_n42# a_n129_n42# 0.05fF
+C8 a_n221_n42# a_n33_n42# 0.05fF
+C9 a_33_n68# a_n63_n68# 0.02fF
+C10 a_n63_n68# a_n159_n68# 0.02fF
+C11 a_159_n42# a_n129_n42# 0.03fF
+C12 a_n129_n42# a_n33_n42# 0.12fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 vdd in 0.33fF
+C1 out in 0.67fF
+C2 out vdd 0.62fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_n125_n42# a_n33_n42# 0.12fF
+C2 a_63_n42# a_n125_n42# 0.05fF
+C3 a_63_n42# a_n33_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_63_n84# a_n125_n84# 0.09fF
+C1 w_n263_n303# a_63_n84# 0.10fF
+C2 a_n33_n84# a_63_n84# 0.24fF
+C3 w_n263_n303# a_n125_n84# 0.10fF
+C4 a_n63_n110# a_33_n110# 0.02fF
+C5 a_n33_n84# a_n125_n84# 0.24fF
+C6 w_n263_n303# a_n33_n84# 0.07fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 vdd out 0.15fF
+C1 in out 0.30fF
+C2 in vdd 0.01fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
++ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 vdd CLK_2 0.08fF
+C1 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C2 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
+C3 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C4 vdd DFlipFlop_0/CLK 0.40fF
+C5 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C6 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C7 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C8 vdd out_div 0.03fF
+C9 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C10 DFlipFlop_0/nCLK vdd 0.30fF
+C11 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C12 vdd o2 0.14fF
+C13 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C14 CLK_2 o1 0.11fF
+C15 o2 nCLK_2 0.11fF
+C16 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C17 nout_div DFlipFlop_0/CLK 0.42fF
+C18 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C19 vdd nCLK_2 0.08fF
+C20 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C21 out_div nout_div 0.22fF
+C22 DFlipFlop_0/nCLK nout_div 0.43fF
+C23 out_div o1 0.01fF
+C24 DFlipFlop_0/nCLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.46fF
+C25 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
+C26 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C27 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C28 vdd nout_div 0.16fF
+C29 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C30 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C31 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C32 vdd o1 0.14fF
+C33 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C34 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C35 nCLK_2 vss 1.08fF
+C36 o2 vss 2.21fF
+C37 CLK_2 vss 1.08fF
+C38 o1 vss 2.21fF
+C39 DFlipFlop_0/CLK vss 1.03fF
+C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C42 CLK vss 3.27fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 out_div vss -0.77fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.41fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+C0 a_n257_n777# a_n129_n600# 0.29fF
+C1 a_n257_n777# a_n221_n600# 0.25fF
+C2 a_n129_n600# a_n221_n600# 7.87fF
+C3 a_n129_n600# VSUBS 0.10fF
+C4 a_n221_n600# VSUBS 0.25fF
+C5 a_n257_n777# VSUBS 1.05fF
+C6 w_n257_n702# VSUBS 2.16fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+C0 a_n129_n300# a_n257_n404# 0.30fF
+C1 a_n221_n300# a_n129_n300# 4.05fF
+C2 a_n221_n300# a_n257_n404# 0.21fF
+C3 a_n129_n300# w_n257_n327# 0.11fF
+C4 a_n221_n300# w_n257_n327# 0.25fF
+C5 a_n257_n404# w_n257_n327# 1.11fF
+.ends
+
+.subckt buffer_salida a_678_n100# out in vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+C0 a_678_n100# a_3996_n100# 6.52fF
+C1 vdd a_678_n100# 0.08fF
+C2 a_678_n100# in 0.81fF
+C3 vdd a_3996_n100# 3.68fF
+C4 out a_3996_n100# 55.19fF
+C5 vdd out 47.17fF
+C6 vdd in 0.02fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
+C10 a_678_n100# vss 13.08fF
+C11 in vss 0.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n238# a_n73_n150# 0.02fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 a_15_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n33_181# 0.01fF
+C1 w_n211_n369# a_n33_181# 0.05fF
+C2 a_15_n150# w_n211_n369# 0.20fF
+C3 a_n73_n150# a_n33_181# 0.01fF
+C4 a_n73_n150# a_15_n150# 0.51fF
+C5 a_n73_n150# w_n211_n369# 0.20fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n225_n150# a_n321_n150# 0.43fF
+C1 a_63_n150# a_n465_172# 0.10fF
+C2 a_255_n150# a_n129_n150# 0.07fF
+C3 a_n321_n150# a_n509_n150# 0.16fF
+C4 a_351_n150# a_n33_n150# 0.07fF
+C5 a_159_n150# a_n33_n150# 0.16fF
+C6 a_447_n150# a_351_n150# 0.43fF
+C7 a_447_n150# a_159_n150# 0.10fF
+C8 a_n225_n150# a_159_n150# 0.07fF
+C9 a_n33_n150# a_n129_n150# 0.43fF
+C10 a_n225_n150# a_n129_n150# 0.43fF
+C11 a_n509_n150# a_n129_n150# 0.07fF
+C12 a_n321_n150# a_n129_n150# 0.16fF
+C13 a_255_n150# a_n465_172# 0.10fF
+C14 a_159_n150# a_351_n150# 0.16fF
+C15 a_159_n150# a_n129_n150# 0.10fF
+C16 a_n465_172# a_n33_n150# 0.10fF
+C17 a_447_n150# a_n465_172# 0.01fF
+C18 a_n225_n150# a_n465_172# 0.10fF
+C19 a_n465_172# a_n509_n150# 0.01fF
+C20 a_255_n150# a_63_n150# 0.16fF
+C21 a_n417_n150# a_n33_n150# 0.07fF
+C22 a_n225_n150# a_n417_n150# 0.16fF
+C23 a_n321_n150# a_n465_172# 0.10fF
+C24 a_n417_n150# a_n509_n150# 0.43fF
+C25 a_63_n150# a_n33_n150# 0.43fF
+C26 a_63_n150# a_447_n150# 0.07fF
+C27 a_63_n150# a_n225_n150# 0.10fF
+C28 a_n465_172# a_351_n150# 0.10fF
+C29 a_159_n150# a_n465_172# 0.10fF
+C30 a_n417_n150# a_n321_n150# 0.43fF
+C31 a_n465_172# a_n129_n150# 0.10fF
+C32 a_63_n150# a_n321_n150# 0.07fF
+C33 a_63_n150# a_351_n150# 0.10fF
+C34 a_63_n150# a_159_n150# 0.43fF
+C35 a_n417_n150# a_n129_n150# 0.10fF
+C36 a_255_n150# a_n33_n150# 0.10fF
+C37 a_255_n150# a_447_n150# 0.16fF
+C38 a_63_n150# a_n129_n150# 0.16fF
+C39 a_n225_n150# a_n33_n150# 0.16fF
+C40 a_n225_n150# a_n509_n150# 0.10fF
+C41 a_255_n150# a_351_n150# 0.43fF
+C42 a_255_n150# a_159_n150# 0.43fF
+C43 a_n417_n150# a_n465_172# 0.10fF
+C44 a_n321_n150# a_n33_n150# 0.10fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n647_n369# a_63_n150# 0.02fF
+C1 a_n321_n150# a_n225_n150# 0.43fF
+C2 a_n225_n150# a_n129_n150# 0.43fF
+C3 a_n321_n150# a_n129_n150# 0.16fF
+C4 a_351_n150# a_255_n150# 0.43fF
+C5 a_159_n150# a_351_n150# 0.16fF
+C6 a_n417_n150# a_n509_n150# 0.43fF
+C7 a_n417_n150# w_n647_n369# 0.07fF
+C8 a_255_n150# a_n33_n150# 0.10fF
+C9 a_159_n150# a_n33_n150# 0.16fF
+C10 a_n225_n150# a_n509_n150# 0.10fF
+C11 a_n225_n150# w_n647_n369# 0.04fF
+C12 a_n321_n150# a_n509_n150# 0.16fF
+C13 a_n321_n150# w_n647_n369# 0.05fF
+C14 a_n129_n150# a_n509_n150# 0.07fF
+C15 a_447_n150# a_63_n150# 0.07fF
+C16 a_n129_n150# w_n647_n369# 0.02fF
+C17 a_159_n150# a_255_n150# 0.43fF
+C18 w_n647_n369# a_n509_n150# 0.14fF
+C19 a_n465_n247# a_351_n150# 0.08fF
+C20 a_351_n150# a_63_n150# 0.10fF
+C21 a_n465_n247# a_n33_n150# 0.08fF
+C22 a_63_n150# a_n33_n150# 0.43fF
+C23 a_n465_n247# a_255_n150# 0.08fF
+C24 a_n465_n247# a_159_n150# 0.08fF
+C25 a_n417_n150# a_n33_n150# 0.07fF
+C26 a_63_n150# a_255_n150# 0.16fF
+C27 a_159_n150# a_63_n150# 0.43fF
+C28 a_447_n150# w_n647_n369# 0.14fF
+C29 a_n225_n150# a_n33_n150# 0.16fF
+C30 a_n321_n150# a_n33_n150# 0.10fF
+C31 a_n129_n150# a_n33_n150# 0.43fF
+C32 a_n225_n150# a_159_n150# 0.07fF
+C33 w_n647_n369# a_351_n150# 0.07fF
+C34 a_n129_n150# a_255_n150# 0.07fF
+C35 a_n129_n150# a_159_n150# 0.10fF
+C36 w_n647_n369# a_n33_n150# 0.02fF
+C37 a_n465_n247# a_63_n150# 0.08fF
+C38 w_n647_n369# a_255_n150# 0.05fF
+C39 w_n647_n369# a_159_n150# 0.04fF
+C40 a_n465_n247# a_n417_n150# 0.08fF
+C41 a_447_n150# a_351_n150# 0.43fF
+C42 a_n465_n247# a_n225_n150# 0.08fF
+C43 a_n465_n247# a_n321_n150# 0.08fF
+C44 a_n225_n150# a_63_n150# 0.10fF
+C45 a_n465_n247# a_n129_n150# 0.08fF
+C46 a_n321_n150# a_63_n150# 0.07fF
+C47 a_n129_n150# a_63_n150# 0.16fF
+C48 a_447_n150# a_255_n150# 0.16fF
+C49 a_447_n150# a_159_n150# 0.10fF
+C50 a_n417_n150# a_n225_n150# 0.16fF
+C51 a_n321_n150# a_n417_n150# 0.43fF
+C52 a_n465_n247# w_n647_n369# 0.47fF
+C53 a_351_n150# a_n33_n150# 0.07fF
+C54 a_n417_n150# a_n129_n150# 0.10fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_15_n11# 0.15fF
+C1 a_n33_n99# a_15_n11# 0.02fF
+C2 a_n73_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_20_n114# a_n78_n114# 0.42fF
+C1 a_20_n114# w_n216_n334# 0.20fF
+C2 w_n216_n334# a_n78_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vdd in 0.01fF
+C1 vss in 0.01fF
+C2 out in 0.11fF
+C3 vdd vbulkp 0.04fF
+C4 vbulkp out 0.08fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 out cap_vco_0/t 0.70fF
+C1 vctrl inverter_csvco_0/vss 0.87fF
+C2 D0 inverter_csvco_0/vss 0.02fF
+C3 inverter_csvco_0/vdd vdd 1.89fF
+C4 out inverter_csvco_0/vdd 0.02fF
+C5 out inverter_csvco_0/vss 0.03fF
+C6 inverter_csvco_0/vdd in 0.01fF
+C7 out D0 0.09fF
+C8 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C9 inverter_csvco_0/vdd vbp 0.75fF
+C10 in inverter_csvco_0/vss 0.01fF
+C11 cap_vco_0/t vdd 0.04fF
+C12 vdd vbp 1.21fF
+C13 out in 0.06fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vdd vss csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ D0 csvco_branch_2/cap_vco_0/t out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
+C1 D0 csvco_branch_1/inverter_csvco_0/vss 0.68fF
+C2 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss 0.06fF
+C3 vctrl csvco_branch_2/vbp 0.06fF
+C4 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C5 csvco_branch_2/in out_vco 0.58fF
+C6 csvco_branch_2/vbp vdd 1.49fF
+C7 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
+C8 D0 csvco_branch_0/inverter_csvco_0/vss 0.49fF
+C9 vctrl D0 4.41fF
+C10 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C11 csvco_branch_1/cap_vco_0/t out_vco 0.03fF
+C12 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C13 csvco_branch_1/in out_vco 0.76fF
+C14 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
+C15 csvco_branch_2/in vss 1.60fF
+C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C21 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C22 csvco_branch_1/in vss 1.58fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 out_vco vss 0.67fF
+C25 D0 vss -1.55fF
+C26 vdd vss 31.40fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 vdd o1 0.09fF
+C1 vdd out_pad 0.10fF
+C2 out_div o1 0.11fF
+C3 out_pad out_div 0.15fF
+C4 vdd out_div 0.17fF
+C5 in_vco vss 0.83fF
+C6 out_pad vss 0.70fF
+C7 out_div vss 3.00fF
+C8 vdd vss 14.54fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_194_125# VPWR 0.33fF
+C1 A B 0.28fF
+C2 a_194_125# VGND 0.25fF
+C3 B X 0.13fF
+C4 A a_355_368# 0.02fF
+C5 a_194_125# a_158_392# 0.06fF
+C6 a_355_368# B 0.08fF
+C7 a_355_368# X 0.17fF
+C8 A VPWR 0.15fF
+C9 B VPWR 0.09fF
+C10 VPWR X 0.07fF
+C11 VPWR VPB 0.06fF
+C12 A VGND 0.31fF
+C13 A a_194_125# 0.18fF
+C14 a_355_368# VPWR 0.37fF
+C15 B VGND 0.10fF
+C16 VGND X 0.28fF
+C17 B a_194_125# 0.57fF
+C18 a_194_125# X 0.29fF
+C19 a_355_368# a_194_125# 0.51fF
+C20 VGND VPWR 0.01fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 a_56_136# VPWR 0.57fF
+C1 VPB VPWR 0.04fF
+C2 X VPWR 0.20fF
+C3 VGND B 0.03fF
+C4 VGND A 0.21fF
+C5 A B 0.08fF
+C6 VGND a_56_136# 0.06fF
+C7 a_56_136# B 0.30fF
+C8 A a_56_136# 0.17fF
+C9 VGND X 0.15fF
+C10 X B 0.02fF
+C11 B VPWR 0.02fF
+C12 A VPWR 0.07fF
+C13 X a_56_136# 0.26fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VGND X 0.16fF
+C1 VGND a_63_368# 0.27fF
+C2 a_63_368# X 0.33fF
+C3 X A 0.02fF
+C4 a_63_368# A 0.28fF
+C5 VGND B 0.11fF
+C6 a_63_368# B 0.14fF
+C7 a_63_368# a_152_368# 0.03fF
+C8 X VPWR 0.18fF
+C9 a_63_368# VPWR 0.29fF
+C10 B A 0.10fF
+C11 VPWR A 0.05fF
+C12 B VPWR 0.01fF
+C13 VPB VPWR 0.04fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
++ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
++ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
++ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
++ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C1 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C2 CLK nQ2 0.17fF
+C3 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C4 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C5 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C6 DFlipFlop_3/latch_diff_1/nD Q1 1.24fF
+C7 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
+C8 nQ0 vdd 0.11fF
+C9 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C10 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C11 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C12 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C13 DFlipFlop_0/Q Q1 0.13fF
+C14 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C15 sky130_fd_sc_hs__xor2_1_0/a_355_368# Q0 0.03fF
+C16 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C17 Q1 DFlipFlop_2/D 0.10fF
+C18 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C19 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C20 DFlipFlop_0/latch_diff_0/D Q0 0.42fF
+C21 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C22 nCLK nQ2 0.10fF
+C23 CLK nQ0 0.19fF
+C24 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C25 DFlipFlop_2/nQ Q1 0.31fF
+C26 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C27 DFlipFlop_1/D Q1 0.03fF
+C28 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C29 DFlipFlop_0/Q Q0 0.21fF
+C30 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C31 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C32 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C33 nQ2 nQ0 0.03fF
+C34 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C35 CLK_5 vdd 0.15fF
+C36 Q0 DFlipFlop_2/D 0.25fF
+C37 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C38 DFlipFlop_3/nQ vdd 0.02fF
+C39 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C40 sky130_fd_sc_hs__xor2_1_0/a_355_368# vdd 0.03fF
+C41 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C42 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C43 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C44 nCLK nQ0 0.09fF
+C45 Q1 Q0 9.65fF
+C46 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C47 sky130_fd_sc_hs__and2_1_1/a_56_136# vdd 0.04fF
+C48 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C49 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C50 DFlipFlop_1/D Q0 0.07fF
+C51 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C52 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C53 DFlipFlop_0/latch_diff_1/nD Q1 0.10fF
+C54 CLK DFlipFlop_3/nQ 0.01fF
+C55 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C56 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C57 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C58 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C59 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C60 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C61 Q1 DFlipFlop_0/D 0.13fF
+C62 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C63 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C64 vdd DFlipFlop_2/D 0.07fF
+C65 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C66 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C67 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C68 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C69 DFlipFlop_3/latch_diff_0/m1_657_280# Q1 0.28fF
+C70 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C71 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C72 DFlipFlop_2/nQ vdd 0.02fF
+C73 Q1 vdd 9.49fF
+C74 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C75 CLK DFlipFlop_0/Q 0.08fF
+C76 Q1_shift DFlipFlop_3/nQ 0.04fF
+C77 nCLK DFlipFlop_3/nQ 0.02fF
+C78 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
+C79 DFlipFlop_1/D vdd 0.25fF
+C80 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C81 CLK DFlipFlop_2/D 0.14fF
+C82 Q0 DFlipFlop_0/D 0.39fF
+C83 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C84 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C85 DFlipFlop_3/latch_diff_1/nD nCLK 0.09fF
+C86 CLK DFlipFlop_2/nQ 0.13fF
+C87 CLK Q1 -0.10fF
+C88 DFlipFlop_0/Q nQ2 0.09fF
+C89 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C90 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C91 CLK DFlipFlop_1/D 0.21fF
+C92 Q0 vdd 5.33fF
+C93 DFlipFlop_0/Q nCLK 0.11fF
+C94 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C95 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C96 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C97 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C98 nCLK DFlipFlop_2/D 0.41fF
+C99 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C100 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C101 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C102 nQ2 Q1 0.07fF
+C103 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
+C104 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C105 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C106 vdd DFlipFlop_0/D 0.19fF
+C107 Q1_shift Q1 0.36fF
+C108 CLK Q0 0.08fF
+C109 DFlipFlop_2/nQ nCLK 0.09fF
+C110 nCLK Q1 -0.01fF
+C111 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C112 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C113 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C114 Q1 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C115 DFlipFlop_1/D nCLK 0.14fF
+C116 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C117 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C118 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C119 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.28fF
+C120 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C121 nCLK DFlipFlop_1/latch_diff_1/D 0.08fF
+C122 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C123 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C124 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C125 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C126 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C127 nQ2 Q0 0.23fF
+C128 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C129 Q1 nQ0 0.06fF
+C130 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C131 DFlipFlop_1/D nQ0 0.12fF
+C132 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C133 nCLK Q0 0.20fF
+C134 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C135 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C136 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C137 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C138 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C139 CLK vdd 0.41fF
+C140 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C141 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C142 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C143 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C144 Q0 nQ0 0.33fF
+C145 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C146 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C147 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C148 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C149 nQ2 vdd 0.04fF
+C150 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C151 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C152 Q1 DFlipFlop_3/nQ 0.10fF
+C153 Q1_shift vdd 0.10fF
+C154 nCLK vdd 0.34fF
+C155 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C156 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/nQ vss 0.52fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 DFlipFlop_2/nQ vss 0.50fF
+C172 Q1 vss 8.55fF
+C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 nQ0 vss 3.42fF
+C183 Q0 vss 0.53fF
+C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 nQ2 vss 2.05fF
+C194 DFlipFlop_0/Q vss -0.94fF
+C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C196 nCLK vss 0.96fF
+C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C200 CLK vss 0.20fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n317_n125# a_n33_n125# 0.08fF
+C1 a_n255_n151# a_n159_n151# 0.02fF
+C2 a_255_n125# a_n33_n125# 0.08fF
+C3 a_33_n151# a_n63_n151# 0.02fF
+C4 a_33_n151# a_129_n151# 0.02fF
+C5 a_n129_n125# a_n33_n125# 0.36fF
+C6 a_159_n125# a_n33_n125# 0.13fF
+C7 a_n225_n125# a_n33_n125# 0.13fF
+C8 a_n129_n125# a_n317_n125# 0.13fF
+C9 a_63_n125# a_n33_n125# 0.36fF
+C10 a_n317_n125# a_n225_n125# 0.36fF
+C11 a_n317_n125# a_63_n125# 0.06fF
+C12 a_n129_n125# a_255_n125# 0.06fF
+C13 a_159_n125# a_255_n125# 0.36fF
+C14 a_225_n151# a_129_n151# 0.02fF
+C15 a_n129_n125# a_159_n125# 0.08fF
+C16 a_255_n125# a_63_n125# 0.13fF
+C17 a_n129_n125# a_n225_n125# 0.36fF
+C18 a_159_n125# a_n225_n125# 0.06fF
+C19 a_n129_n125# a_63_n125# 0.13fF
+C20 a_159_n125# a_63_n125# 0.36fF
+C21 a_n159_n151# a_n63_n151# 0.02fF
+C22 a_63_n125# a_n225_n125# 0.08fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n455_n344# a_63_n125# 0.04fF
+C1 w_n455_n344# a_n317_n125# 0.11fF
+C2 w_n455_n344# a_255_n125# 0.11fF
+C3 a_159_n125# a_n33_n125# 0.13fF
+C4 a_159_n125# a_n225_n125# 0.06fF
+C5 a_n33_n125# a_n225_n125# 0.13fF
+C6 a_63_n125# a_n129_n125# 0.13fF
+C7 a_n317_n125# a_n129_n125# 0.13fF
+C8 a_255_n125# a_n129_n125# 0.06fF
+C9 a_63_n125# a_n317_n125# 0.06fF
+C10 a_255_n125# a_63_n125# 0.13fF
+C11 w_n455_n344# a_159_n125# 0.06fF
+C12 a_129_n154# a_225_n154# 0.02fF
+C13 w_n455_n344# a_n33_n125# 0.05fF
+C14 w_n455_n344# a_n225_n125# 0.06fF
+C15 a_n159_n154# a_n255_n154# 0.02fF
+C16 a_159_n125# a_n129_n125# 0.08fF
+C17 a_129_n154# a_33_n154# 0.02fF
+C18 a_n129_n125# a_n33_n125# 0.36fF
+C19 a_n129_n125# a_n225_n125# 0.36fF
+C20 a_159_n125# a_63_n125# 0.36fF
+C21 a_255_n125# a_159_n125# 0.36fF
+C22 a_n63_n154# a_33_n154# 0.02fF
+C23 a_63_n125# a_n33_n125# 0.36fF
+C24 a_n317_n125# a_n33_n125# 0.08fF
+C25 a_255_n125# a_n33_n125# 0.08fF
+C26 a_63_n125# a_n225_n125# 0.08fF
+C27 a_n317_n125# a_n225_n125# 0.36fF
+C28 w_n455_n344# a_n129_n125# 0.04fF
+C29 a_n63_n154# a_n159_n154# 0.02fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 out in 0.85fF
+C1 vdd in 0.04fF
+C2 out vdd 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in Up 0.12fF
+C1 inverter_cp_x1_0/out nDown 0.11fF
+C2 inverter_cp_x1_2/in vdd 0.42fF
+C3 Down vdd 0.09fF
+C4 nDown vdd 0.80fF
+C5 Down nDown 0.23fF
+C6 QB vdd 0.02fF
+C7 nUp Up 0.20fF
+C8 inverter_cp_x1_0/out vdd 0.25fF
+C9 QA vdd 0.02fF
+C10 Down inverter_cp_x1_0/out 0.12fF
+C11 nUp vdd 0.14fF
+C12 Up vdd 0.60fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_63_n90# a_n33_n90# 0.26fF
+C1 a_n129_n90# a_159_n90# 0.06fF
+C2 a_63_n90# a_159_n90# 0.26fF
+C3 a_n159_n207# a_n63_n116# 0.12fF
+C4 a_159_n90# a_n33_n90# 0.09fF
+C5 w_n359_n309# a_n221_n90# 0.09fF
+C6 a_n129_n90# a_n221_n90# 0.26fF
+C7 a_63_n90# a_n221_n90# 0.06fF
+C8 a_n129_n90# w_n359_n309# 0.06fF
+C9 a_63_n90# w_n359_n309# 0.06fF
+C10 a_n33_n90# a_n221_n90# 0.09fF
+C11 a_159_n90# a_n221_n90# 0.04fF
+C12 a_n33_n90# w_n359_n309# 0.05fF
+C13 a_159_n90# w_n359_n309# 0.09fF
+C14 a_n129_n90# a_63_n90# 0.09fF
+C15 a_n129_n90# a_n33_n90# 0.26fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n125_n45# 0.05fF
+C1 a_n33_n45# a_n125_n45# 0.13fF
+C2 a_33_n71# a_n129_71# 0.04fF
+C3 a_63_n45# a_n33_n45# 0.13fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 out A 0.06fF
+C1 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C2 B A 0.24fF
+C3 A vdd 0.09fF
+C4 B out 0.40fF
+C5 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
+C6 out vdd 0.11fF
+C7 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 Q vdd 0.08fF
+C1 Q nor_pfd_2/B 2.22fF
+C2 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C3 Q Reset 0.14fF
+C4 nor_pfd_3/A vdd 0.09fF
+C5 nor_pfd_2/A vdd -0.01fF
+C6 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C7 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C8 Reset nor_pfd_3/A 0.12fF
+C9 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C10 nor_pfd_2/B vdd 0.02fF
+C11 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C12 Q nor_pfd_3/A 0.98fF
+C13 Q nor_pfd_2/A 1.38fF
+C14 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C15 Reset nor_pfd_2/B 0.43fF
+C16 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C17 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C18 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C19 Q CLK 0.04fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_159_n45# a_n33_n45# 0.05fF
+C1 a_63_n45# a_159_n45# 0.13fF
+C2 a_159_n45# a_n221_n45# 0.02fF
+C3 a_n159_n173# a_n63_n71# 0.10fF
+C4 a_63_n45# a_n33_n45# 0.13fF
+C5 a_159_n45# a_n129_n45# 0.03fF
+C6 a_n221_n45# a_n33_n45# 0.05fF
+C7 a_63_n45# a_n221_n45# 0.03fF
+C8 a_n33_n45# a_n129_n45# 0.13fF
+C9 a_63_n45# a_n129_n45# 0.05fF
+C10 a_n221_n45# a_n129_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n125_n90# a_n33_n90# 0.26fF
+C1 a_63_n90# a_n33_n90# 0.26fF
+C2 a_n99_n187# a_33_n187# 0.04fF
+C3 a_n125_n90# a_63_n90# 0.09fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n73_n45# a_15_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_15_n90# w_n211_n309# 0.09fF
+C1 a_n73_n90# w_n211_n309# 0.04fF
+C2 a_15_n90# a_n73_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C1 A vdd 0.05fF
+C2 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C3 a_656_410# A 0.04fF
+C4 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C5 vdd out 0.10fF
+C6 a_656_410# out 0.20fF
+C7 a_656_410# B 0.30fF
+C8 A B 0.33fF
+C9 a_656_410# vdd 0.20fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
+C0 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C1 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C2 Down vdd 0.08fF
+C3 Up Down 0.06fF
+C4 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C5 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
+C6 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
+C7 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C8 Up vdd 1.62fF
+C9 vdd Reset 0.02fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v2_pex_c iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
++ pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
++ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
++ n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer D0_vco
+Xcharge_pump_0 nswitch vdd nUp vss Down biasp vco_vctrl pswitch iref_cp nDown Up charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vss
++ D0_vco ring_osc_0/csvco_branch_2/cap_vco_0/t vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+C0 vdd buffer_salida_0/a_678_n100# 0.24fF
+C1 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C2 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C3 vdd nDown 0.22fF
+C4 nUp vdd 0.05fF
+C5 out_div_by_5 div_5_Q1_shift 0.05fF
+C6 n_out_by_2 vdd 1.03fF
+C7 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C8 biasp Up 0.26fF
+C9 vdd lf_vc 0.02fF
+C10 Down nDown 2.55fF
+C11 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C12 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C13 vco_vctrl out_by_2 0.53fF
+C14 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C15 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C16 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C17 n_out_by_2 div_5_Q0 -0.12fF
+C18 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C19 n_out_by_2 div_5_Q1 1.04fF
+C20 out_to_buffer out_to_div 0.13fF
+C21 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C22 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C23 vco_vctrl vdd -1.02fF
+C24 biasp nDown 0.26fF
+C25 n_out_by_2 div_5_nQ0 0.10fF
+C26 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C27 biasp nUp -0.17fF
+C28 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C29 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C30 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C31 vco_vctrl div_5_Q0 0.48fF
+C32 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
+C33 Up nUp 2.72fF
+C34 vco_vctrl div_5_Q1 0.14fF
+C35 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C36 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C37 nswitch nDown 0.76fF
+C38 vdd D0_vco 0.03fF
+C39 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C40 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C41 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C42 out_by_2 vdd 0.97fF
+C43 n_out_by_2 div_5_nQ2 0.10fF
+C44 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C45 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C46 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C47 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
+C48 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C49 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C50 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C51 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C52 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
+C53 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C54 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C55 out_by_2 div_5_Q0 0.09fF
+C56 nUp nDown -0.09fF
+C57 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C58 out_by_2 div_5_Q1 0.42fF
+C59 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
+C60 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C61 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C62 out_div_by_5 vdd 0.28fF
+C63 nswitch vco_vctrl -0.06fF
+C64 Up pswitch 1.98fF
+C65 div_5_nQ0 out_by_2 0.32fF
+C66 vdd QA -0.04fF
+C67 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
+C68 div_by_5_0/DFlipFlop_1/D out_by_2 0.38fF
+C69 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
+C70 out_div_by_5 div_5_Q1 0.01fF
+C71 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C72 vco_vctrl nUp 0.02fF
+C73 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C74 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C75 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C76 n_out_by_2 vco_vctrl 0.52fF
+C77 pswitch nDown 0.53fF
+C78 vdd out_to_div 0.21fF
+C79 out_by_2 div_5_nQ2 0.16fF
+C80 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C81 nUp pswitch 0.85fF
+C82 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C83 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C84 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C85 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C86 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C87 Up vdd 0.28fF
+C88 biasp Down 1.24fF
+C89 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C90 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C91 vdd iref_cp 0.15fF
+C92 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C93 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C94 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
+C95 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C96 out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.09fF
+C97 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C98 out_to_buffer vdd 0.07fF
+C99 Down iref_cp 0.09fF
+C100 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
+C101 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C102 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C103 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C104 nswitch Down 0.54fF
+C105 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C106 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
+C107 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.93fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C123 out_div_by_5 vss 1.39fF
+C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.76fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C137 in_ref vss 1.19fF
+C138 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C139 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C140 nUp vss 6.05fF
+C141 Up vss 2.16fF
+C142 Down vss 6.16fF
+C143 nDown vss 3.38fF
+C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C148 div_5_Q1_shift vss -0.14fF
+C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C158 div_5_Q1 vss 4.28fF
+C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_nQ0 vss 0.59fF
+C169 div_5_Q0 vss 0.01fF
+C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_5_nQ2 vss 1.24fF
+C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C182 n_out_by_2 vss -2.62fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C186 out_by_2 vss -4.51fF
+C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C192 vdd vss 366.82fF
+C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C195 out_to_buffer vss 1.57fF
+C196 out_to_div vss 4.46fF
+C197 out_first_buffer vss 2.88fF
+C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C201 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C203 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C204 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C205 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C206 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C207 vco_out vss 1.01fF
+C208 D0_vco vss -4.63fF
+C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C214 buffer_salida_0/a_678_n100# vss 13.38fF
+C215 n_out_buffer_div_2 vss 1.63fF
+C216 out_buffer_div_2 vss 1.60fF
+C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 out_div_2 vss -1.30fF
+C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C229 n_out_div_2 vss 1.95fF
+C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C231 lf_vc vss -59.89fF
+C232 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C233 DO_cap vss 0.01fF
+C234 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C235 nswitch vss 3.73fF
+C236 biasp vss 5.44fF
+C237 iref_cp vss 2.81fF
+C238 vco_vctrl vss -21.20fF
+C239 pswitch vss 3.57fF
+.ends
+
diff --git a/xschem/simulations/trans_gate.spice b/xschem/simulations/trans_gate.spice
new file mode 100644
index 0000000..33c6be4
--- /dev/null
+++ b/xschem/simulations/trans_gate.spice
@@ -0,0 +1,14 @@
+**.subckt trans_gate vss in out vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+**.ends
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/user_analog_project_wrapper.spice b/xschem/simulations/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..464abdb
--- /dev/null
+++ b/xschem/simulations/user_analog_project_wrapper.spice
@@ -0,0 +1,1228 @@
+**.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
+*+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0] wbs_ack_o
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0] user_clock2
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0] io_clamp_high[2],io_clamp_high[1],io_clamp_high[0] io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*+ user_irq[2],user_irq[1],user_irq[0]
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+*.iopin vdda1
+*.iopin vdda2
+*.iopin vssa1
+*.iopin vssa2
+*.iopin vccd1
+*.iopin vccd2
+*.iopin vssd1
+*.iopin vssd2
+*.ipin wb_clk_i
+*.ipin wb_rst_i
+*.ipin wbs_stb_i
+*.ipin wbs_cyc_i
+*.ipin wbs_we_i
+*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*.ipin
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*.ipin
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
+*.opin wbs_ack_o
+*.opin
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*.ipin
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*.opin
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*.ipin
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*.ipin
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
+*.ipin user_clock2
+*.opin
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*.opin
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*.iopin
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*.iopin
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*.iopin
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
+*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
+*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*.opin user_irq[2],user_irq[1],user_irq[0]
+*.ipin
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+x1 iref_cp2 vssa1 vdda1 net13 net12 net6 net1 net5 io_analog[10] io_analog[9] net4 net7 net2
++ gpio_noesd[7] net11 net14 net8 net9 net3 net10 net20 net15 net27 net21 net23 net25 net24 net18 net19 net22 net17
++ net26 net16 net28 top_pll_v1
+x2 vdda1 io_analog[5] iref_cp0 iref_cp1 iref_cp2 net29 net30 iref4 iref2 iref3 iref1 iref0 bias
+x3 iref_cp1 vssa1 vdda1 net43 net42 net36 net31 net35 io_analog[10] io_analog[8] net34 net37 net32
++ gpio_noesd[7] net41 net44 net38 net39 net33 net40 net50 net45 net57 net51 net53 net55 net54 net48 net49 net52
++ net47 net56 net46 net58 gpio_noesd[8] top_pll_v2
+x4 iref_cp0 vssa1 vdda1 net71 net70 net64 net59 net63 io_analog[10] io_analog[7] net62 net65 net60
++ gpio_noesd[7] net69 net72 net66 net67 net61 net68 net78 net73 net85 net79 net81 net83 net82 net76 net77 net80
++ net75 net84 net74 net86 top_pll_v1
+XC1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=9 m=9
+XC2 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=9 m=9
+XC3 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=7 m=7
+XC4 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
+XC5 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
+XC6 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
+XC7 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
+XC8 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
+XC9 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
+x5 vdda1 io_analog[3] io_analog[2] io_analog[0] io_analog[1] vssa1 io_analog[6] gpio_noesd[4]
++ gpio_noesd[5] gpio_noesd[6] gpio_noesd[3] gpio_noesd[1] gpio_noesd[2] iref0 io_analog[4] iref1 iref2 iref3 iref4
++ res_amp_top
+XC10 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=10 m=10
+**.ends
+
+* expanding symbol: top_pll_v1.sym # of pins=34
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v1.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v1.sch
+.subckt top_pll_v1 iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
++ pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
++ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
++ n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.iopin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.iopin out_to_buffer
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin div_5_Q1
+*.iopin div_5_Q1_shift
+*.iopin div_5_nQ0
+*.iopin div_5_Q0
+*.iopin div_5_nQ2
+*.iopin out_div_by_5
+*.iopin out_to_pad
+x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD
+x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump
+x3 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface
+x4 vss vco_vctrl lf_vc loop_filter
+x5 vdd vco_out vco_D0 vco_vctrl vss csvco
+x6 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer
+x7 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift
++ div_by_5
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2
+x9 vdd out_to_pad out_to_buffer vss buffer_salida
+.ends
+
+
+* expanding symbol: bias.sym # of pins=12
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/bias.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/bias.sch
+.subckt bias vdd iref iref_0 iref_1 iref_2 iref_3 iref_4 iref_5 iref_6 iref_7 iref_8 iref_9
+*.iopin iref
+*.iopin vdd
+*.opin iref_0
+*.opin iref_1
+*.opin iref_2
+*.opin iref_3
+*.opin iref_4
+*.opin iref_5
+*.opin iref_6
+*.opin iref_7
+*.opin iref_8
+*.opin iref_9
+XM1 iref iref vbp1 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM2 vbp1 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM3 net1 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM4 iref_0 iref net1 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM5 net2 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM6 iref_1 iref net2 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM7 net3 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM8 iref_2 iref net3 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM9 net4 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM10 iref_3 iref net4 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM11 net5 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM12 iref_4 iref net5 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM13 net6 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM14 iref_5 iref net6 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM15 net7 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM16 iref_6 iref net7 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM17 net8 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM18 iref_7 iref net8 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM19 net9 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM20 iref_8 iref net9 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM21 net10 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+XM22 iref_9 iref net10 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25
+.ends
+
+
+* expanding symbol: top_pll_v2.sym # of pins=35
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v2.sch
+.subckt top_pll_v2 iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
++ pfd_QB D0_vco lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
++ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
++ n_out_div_2 div_5_nQ2 out_div_2 out_to_buffer D0_cap
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.iopin D0_vco
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.iopin out_to_buffer
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin div_5_Q1
+*.iopin div_5_Q1_shift
+*.iopin div_5_nQ0
+*.iopin div_5_Q0
+*.iopin div_5_nQ2
+*.iopin out_div_by_5
+*.iopin out_to_pad
+*.ipin D0_cap
+x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD
+x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump
+x3 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface
+x5 vdd vco_out D0_vco vco_vctrl vss csvco
+x6 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer
+x7 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift
++ div_by_5
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2
+x9 vdd out_to_pad out_to_buffer vss buffer_salida
+x4 vss vco_vctrl lf_vc D0_cap loop_filter_v2
+.ends
+
+
+* expanding symbol: res_amp_top.sym # of pins=19
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_top.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_top.sch
+.subckt res_amp_top avdd1p8 inp inn outp outn avss1p8 clkp iref_reg0 iref_reg1 iref_reg2 delay_reg0
++ delay_reg2 delay_reg1 iref0 clkn iref1 iref2 iref3 iref4
+*.ipin inp
+*.ipin inn
+*.ipin clkp
+*.ipin clkn
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin iref0
+*.ipin iref1
+*.ipin iref2
+*.ipin iref3
+*.ipin iref4
+*.opin outn
+*.opin outp
+*.ipin iref_reg0
+*.ipin iref_reg1
+*.ipin iref_reg2
+*.ipin delay_reg0
+*.ipin delay_reg1
+*.ipin delay_reg2
+x2 avdd1p8 rst inp inn outp_amp outn_amp avss1p8 outp_cap outn_cap clk_amp iref_reg0 iref_reg1
++ iref_reg2 delay_reg0 delay_reg2 delay_reg1 iref0 res_amp_lin_prog
+x1 avdd1p8 clkp clkn avss1p8 clk_amp rst res_amp_sync_v2
+x3 avdd1p8 iref1 outp_cap outp avss1p8 outn_cap outn iref2 iref3 iref4 source_follower_buff_diff
+XC1 outp_cap avss1p8 sky130_fd_pr__cap_mim_m3_1 W=5.5 L=7.5 MF=1 m=1
+XC2 outn_cap avss1p8 sky130_fd_pr__cap_mim_m3_1 W=5.5 L=7.5 MF=1 m=1
+.ends
+
+
+* expanding symbol: PFD.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding symbol: charge_pump.sym # of pins=11
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/charge_pump.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/charge_pump.sch
+.subckt charge_pump vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
+*.iopin vss
+*.iopin vdd
+*.ipin Down
+*.ipin nUp
+*.ipin Up
+*.ipin nDown
+*.opin out
+*.iopin nswitch
+*.iopin pswitch
+*.ipin iref
+*.iopin biasp
+XM1 out pswitch vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM2 out nswitch vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM3 pswitch nUp biasp vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 pswitch Up vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM5 nswitch Down iref vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM6 nswitch nDown vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM7 pswitch nUp pswitch vdd sky130_fd_pr__pfet_01v8 L=2 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM8 nswitch Down nswitch vss sky130_fd_pr__nfet_01v8 L=1.5 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM9 iref iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM10 biasp iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+XM11 biasp biasp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25
+.ends
+
+
+* expanding symbol: pfd_cp_interface.sym # of pins=8
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
+.subckt pfd_cp_interface Up vdd QA nUp Down QB vss nDown
+*.iopin vdd
+*.iopin vss
+*.ipin QA
+*.ipin QB
+*.opin nDown
+*.opin Down
+*.opin nUp
+*.opin Up
+x5 vdd nDown nQB vss trans_gate
+x3 vdd Up nQA vss inverter_cp_x1
+x1 vdd nQB QB vss inverter_cp_x1
+x2 vdd nQA QA vss inverter_cp_x1
+x4 vdd nUp Up vss inverter_cp_x2
+x6 vdd Down nDown vss inverter_cp_x2
+.ends
+
+
+* expanding symbol: loop_filter.sym # of pins=3
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter.sch
+.subckt loop_filter vss in vc_pex
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+x1 in net1 vss res_loop_filter
+x2 vc_pex net1 vss res_loop_filter
+x3 vc_pex net1 vss res_loop_filter
+x4 vc_pex vss cap1_loop_filter
+x5 in vss cap2_loop_filter
+.ends
+
+
+* expanding symbol: csvco.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco.sch
+.subckt csvco vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd vbp out out1 vctrl vss D0 csvco_branch
+x2 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x3 vdd vbp out2 out vctrl vss D0 csvco_branch
+.ends
+
+
+* expanding symbol: ring_osc_buffer.sym # of pins=6
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
+.subckt ring_osc_buffer vdd in_vco out_pad out_div vss o1
+*.iopin vdd
+*.iopin vss
+*.ipin in_vco
+*.opin out_pad
+*.opin out_div
+*.iopin o1
+x1 vdd o1 in_vco vss inverter_min_x2
+x2 vdd out_div o1 vss inverter_min_x4
+x3 vdd out_pad out_div vss inverter_min_x4
+.ends
+
+
+* expanding symbol: div_by_5.sym # of pins=10
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_5.sch
+.subckt div_by_5 vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: div_by_2.sym # of pins=9
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding symbol: buffer_salida.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_salida.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_salida.sch
+.subckt buffer_salida vdd out in vss
+*.iopin vss
+*.ipin in
+*.iopin vdd
+*.opin out
+XM2 net1 in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 net1 in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM3 net2 net1 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM4 net2 net1 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=32 m=32
+XM5 out net2 vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=6 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+XM6 out net2 vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=256 m=256
+.ends
+
+
+* expanding symbol: loop_filter_v2.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter_v2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter_v2.sch
+.subckt loop_filter_v2 vss in vc_pex D0_cap
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+*.iopin D0_cap
+x1 in net1 vss res_loop_filter
+x2 vc_pex net1 vss res_loop_filter
+x3 vc_pex net1 vss res_loop_filter
+x4 vc_pex vss cap1_loop_filter
+x5 in vss cap2_loop_filter
+XM1 in D0_cap net2 vss sky130_fd_pr__nfet_01v8 L=0.3 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x6 net2 vss cap3_loop_filter
+.ends
+
+
+* expanding symbol: res_amp_lin_prog.sym # of pins=17
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin_prog.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin_prog.sch
+.subckt res_amp_lin_prog avdd1p8 rst inp inn outp outn avss1p8 outp_cap outn_cap clk iref_reg0
++ iref_reg1 iref_reg2 delay_reg0 delay_reg2 delay_reg1 iref
+*.ipin clk
+*.opin outp
+*.opin outn
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin iref
+*.ipin inp
+*.ipin inn
+*.ipin iref_reg0
+*.ipin iref_reg1
+*.ipin iref_reg2
+*.opin outp_cap
+*.opin outn_cap
+*.ipin delay_reg0
+*.ipin delay_reg1
+*.ipin delay_reg2
+*.ipin rst
+x3 avdd1p8 clk avss1p8 clk_out delay_reg0 delay_reg1 delay_reg2 delay_cell_buff
+XM3 outn_cap rst avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+x4 avdd1p8 clk_out inp inn outp outn avss1p8 vctrl res_amp_lin
+XM1 outp clk_out_b outp_cap avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XM2 outn clk_out_b outn_cap avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5
+XM5 outp_cap clk_out outp avdd1p8 sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM6 outn_cap clk_out outn avdd1p8 sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+x5 avdd1p8 clk_out_b clk_out avss1p8 inverter_min_x4
+XM4 outp_cap rst avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+x7 avdd1p8 iref avss1p8 vctrl iref_reg0 iref_reg1 iref_reg2 iref_ctrl_res_amp
+.ends
+
+
+* expanding symbol: res_amp_sync_v2.sym # of pins=6
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_sync_v2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_sync_v2.sch
+.subckt res_amp_sync_v2 avdd1p8 clkp clkn avss1p8 clk_amp rst
+*.ipin clkn
+*.ipin clkp
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin rst
+*.opin clk_amp
+x4 avdd1p8 net1 net3 net2 avss1p8 nand_logic
+x1 avdd1p8 d1 q1 avss1p8 inverter_min_x4
+x5 avdd1p8 pulse net3 avss1p8 inverter_min_x4
+x21 avdd1p8 pulse net6 clkp avss1p8 nand_logic
+x3 avdd1p8 net2 net7 avss1p8 d1 clkp clkn DFlipFlop
+x6 avdd1p8 net1 net8 avss1p8 q2 clkp clkn DFlipFlop
+x7 avdd1p8 q1 net9 avss1p8 d1 clkp clkn DFlipFlop
+x8 avdd1p8 q2 net10 avss1p8 d2 d1 q1 DFlipFlop
+x9 avdd1p8 net4 net11 avss1p8 pulse clkp clkn DFlipFlop
+x2 avdd1p8 d2 q2 avss1p8 inverter_min_x4
+x10 avdd1p8 rst net6 avss1p8 inverter_min_x4
+x11 avdd1p8 net5 net4 avss1p8 inverter_min_x4
+x12 avdd1p8 clk_amp net5 avss1p8 inverter_min_x16
+.ends
+
+
+* expanding symbol: source_follower_buff_diff.sym # of pins=10
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_diff.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_diff.sch
+.subckt source_follower_buff_diff avdd1p8 iref1 inp outp avss1p8 inn outn iref2 iref3 iref4
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin outp
+*.opin outn
+*.ipin inp
+*.ipin inn
+*.ipin iref1
+*.ipin iref2
+*.ipin iref3
+*.ipin iref4
+x1 avdd1p8 iref1 inp outp_int avss1p8 source_follower_buff_pmos
+x2 avdd1p8 iref2 outp_int outp avss1p8 source_follower_buff_nmos
+x3 avdd1p8 iref3 inn outn_int avss1p8 source_follower_buff_pmos
+x4 avdd1p8 iref4 outn_int outn avss1p8 source_follower_buff_nmos
+.ends
+
+
+* expanding symbol: DFF.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding symbol: and_pfd.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: trans_gate.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x1.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
+* expanding symbol: inverter_cp_x2.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+
+* expanding symbol: res_loop_filter.sym # of pins=3
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_loop_filter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_loop_filter.sch
+.subckt res_loop_filter in out vss
+*.iopin in
+*.iopin vss
+*.iopin out
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+.ends
+
+
+* expanding symbol: cap1_loop_filter.sym # of pins=2
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
+.subckt cap1_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+.ends
+
+
+* expanding symbol: cap2_loop_filter.sym # of pins=2
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
+.subckt cap2_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+.ends
+
+
+* expanding symbol: csvco_branch.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco_branch.sch
+.subckt csvco_branch vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding symbol: inverter_min_x2.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x4.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+.ends
+
+
+* expanding symbol: DFlipFlop.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding symbol: clock_inverter.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding symbol: cap3_loop_filter.sym # of pins=2
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/cap3_loop_filter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/cap3_loop_filter.sch
+.subckt cap3_loop_filter in out
+*.iopin in
+*.iopin out
+XC1 in out sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=4 m=4
+.ends
+
+
+* expanding symbol: delay_cell_buff.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/delay_cell_buff.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/delay_cell_buff.sch
+.subckt delay_cell_buff avdd1p8 clk avss1p8 clk_out reg0 reg1 reg2
+*.ipin clk
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin clk_out
+*.ipin reg2
+*.ipin reg1
+*.ipin reg0
+x1 avdd1p8 reg2 avss1p8 clk3 net1 clk2 mux_2to1_logic
+x2 avdd1p8 reg2 avss1p8 clk1 net2 clk mux_2to1_logic
+x3 avdd1p8 reg1 avss1p8 net1 net3 net2 mux_2to1_logic
+x4 avdd1p8 out_mux clk_out clk avss1p8 nand_logic
+x513 avdd1p8 clk avss1p8 clk1_int buffer_no_inv_x05
+x512 avdd1p8 clk1_int avss1p8 clk1 buffer_no_inv_x05
+x511 avdd1p8 clk1 avss1p8 clk2_int buffer_no_inv_x05
+x510 avdd1p8 clk2_int avss1p8 clk2 buffer_no_inv_x05
+x59 avdd1p8 clk2 avss1p8 clk3_int buffer_no_inv_x05
+x58 avdd1p8 clk3_int avss1p8 clk3 buffer_no_inv_x05
+x57 avdd1p8 clk3 avss1p8 clk4_int buffer_no_inv_x05
+x56 avdd1p8 clk4_int avss1p8 clk4 buffer_no_inv_x05
+x55 avdd1p8 clk4 avss1p8 clk5_int buffer_no_inv_x05
+x54 avdd1p8 clk5_int avss1p8 clk5 buffer_no_inv_x05
+x53 avdd1p8 clk5 avss1p8 clk6_int buffer_no_inv_x05
+x52 avdd1p8 clk6_int avss1p8 clk6 buffer_no_inv_x05
+x51 avdd1p8 clk6 avss1p8 clk7_int buffer_no_inv_x05
+x50 avdd1p8 clk7_int avss1p8 clk7 buffer_no_inv_x05
+x5 avdd1p8 reg2 avss1p8 clk7 net4 clk6 mux_2to1_logic
+x6 avdd1p8 reg2 avss1p8 clk5 net5 clk4 mux_2to1_logic
+x7 avdd1p8 reg1 avss1p8 net4 net6 net5 mux_2to1_logic
+x8 avdd1p8 reg0 avss1p8 net6 out_mux net3 mux_2to1_logic
+.ends
+
+
+* expanding symbol: res_amp_lin.sym # of pins=8
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin.sch
+.subckt res_amp_lin avdd1p8 clk inp inn outp outn avss1p8 vctrl
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin outp
+*.opin outn
+*.ipin inn
+*.ipin inp
+*.ipin clk
+*.ipin vctrl
+XM6 int clk avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XM8 outn clk avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM9 outp clk avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM3 vp vctrl int avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=5 m=5
+XM1 outn inp vp avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=20 m=20
+XM2 outp inn vp avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=20 m=20
+.ends
+
+
+* expanding symbol: iref_ctrl_res_amp.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sch
+.subckt iref_ctrl_res_amp avdd1p8 iref avss1p8 vctrl reg0 reg1 reg2
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin reg0
+*.ipin reg1
+*.ipin reg2
+*.opin vctrl
+*.ipin iref
+XM7 iref iref net1 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6
+XM8 vctrl iref net2 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XM9 vctrl vctrl net3 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XM10 net3 avss1p8 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XM1 vctrl iref net4 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XM2 vctrl iref net5 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=4 m=4
+XM3 net4 reg0 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XM4 net5 reg1 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=4 m=4
+XM5 net2 avdd1p8 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3
+XM6 net1 avdd1p8 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6
+XM11 vctrl iref net6 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+XM12 net6 reg2 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8
+.ends
+
+
+* expanding symbol: nand_logic.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/nand_logic.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/nand_logic.sch
+.subckt nand_logic avdd1p8 in1 out in2 avss1p8
+*.ipin in1
+*.ipin in2
+*.opin out
+*.iopin avdd1p8
+*.iopin avss1p8
+XM4 out in2 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XM5 n1 in1 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in2 n1 avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 out in1 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_min_x16.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x16.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x16.sch
+.subckt inverter_min_x16 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=16 m=16
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=16 m=16
+.ends
+
+
+* expanding symbol: source_follower_buff_pmos.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_pmos.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_pmos.sch
+.subckt source_follower_buff_pmos avdd1p8 iref in out avss1p8
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin out
+*.ipin in
+*.ipin iref
+XM5 net1 net1 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=15 m=15
+XM6 out net1 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=15 m=15
+XM1 avss1p8 in out avdd1p8 sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=20 m=20
+XM2 iref iref avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6
+XM3 net1 iref avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+
+* expanding symbol: source_follower_buff_nmos.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_nmos.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_nmos.sch
+.subckt source_follower_buff_nmos avdd1p8 iref in out avss1p8
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin out
+*.ipin in
+*.ipin iref
+XM2 net1 iref avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6
+XM1 out iref avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=160 m=160
+XM3 avdd1p8 in out avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=80 m=80
+XM4 iref iref net1 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6
+.ends
+
+
+* expanding symbol: nor.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: inverter_csvco.sym # of pins=6
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+
+* expanding symbol: latch_diff.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: mux_2to1_logic.sym # of pins=6
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/mux_2to1_logic.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/mux_2to1_logic.sch
+.subckt mux_2to1_logic avdd1p8 sel avss1p8 DinB out DinA
+*.ipin DinB
+*.ipin DinA
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin sel
+*.opin out
+XM5 out sel_b DinB avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=2.22 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM6 DinB sel out avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.11 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out sel DinA avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=2.22 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM7 DinA sel_b out avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.11 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+x1 avdd1p8 sel_b sel avss1p8 inverter_min
+.ends
+
+
+* expanding symbol: buffer_no_inv_x05.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sch
+.subckt buffer_no_inv_x05 avdd1p8 in avss1p8 out
+*.ipin in
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin out
+x1 avdd1p8 net1 in avss1p8 inverter_min
+x2 avdd1p8 out net1 avss1p8 inverter_min
+.ends
+
+
+* expanding symbol: inverter_min.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min.sch
+.subckt inverter_min vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/vco.spice b/xschem/simulations/vco.spice
new file mode 100644
index 0000000..3597f3d
--- /dev/null
+++ b/xschem/simulations/vco.spice
@@ -0,0 +1,149 @@
+**.subckt vco vctrl
+*.ipin vctrl
+vss vss GND {vss}
+vdd vdd vss {vdd}
+C1 out vss 10f m=1
+Vctrl vctrl vss DC {vctrl}
+x5 vdd out out4 vss inverter_min_x2
+x4 vdd out4 out3 vss inverter_min_x2
+C2 out_wp vss 10f m=1
+x6 vdd out_wp out4_wp vss inverter_min_x2
+x7 vdd out4_wp out3_wp vss inverter_min_x2
+XM1 net1 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8
+XM7 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net11 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8
+XM3 net12 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8
+XM4 net2 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM5 net3 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM6 net4 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM9 net5 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8
+XM10 net6 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8
+XM11 net7 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8
+XM12 net8 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM13 net9 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+XM14 net10 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4
+x1 net1 out1 out3 net2 vdd vss inverter_csvco
+x2 net11 out2 out1 net3 vdd vss inverter_csvco
+x3 net12 out3 out2 net4 vdd vss inverter_csvco
+x8 net7 out1_wp out3_wp net8 vdd vss inverter_csvco_pex_c
+x9 net5 out2_wp out1_wp net9 vdd vss inverter_csvco_pex_c
+x10 net6 out3_wp out2_wp net10 vdd vss inverter_csvco_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vctrl = 1.0
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/sky130-mpw2-fulgor/inverter_csvco/sch/simulations/inverter_csvco_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(out1) = 0.0
+.ic v(out2) = 0.0
+.ic v(out3) = 0.0
+.ic v(out4) = 0.0
+.ic v(out) = 0.0
+.ic v(out1_wp) = 0.0
+.ic v(out2_wp) = 0.0
+.ic v(out3_wp) = 0.0
+.ic v(out4_wp) = 0.0
+.ic v(out_wp) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 50ns
+ meas tran To trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ meas tran To_wp trig v(out_wp) val=0.9 fall=5 targ v(out_wp) val=0.9 fall=15
+ let T = To/10.0
+ let T_wp = To_wp/10.0
+ let f = 1/T
+ let f_wp = 1/T_wp
+ echo .
+ echo --- VCO ----
+ print T f
+ echo --- VCO_wp ----
+ print T_wp f_wp
+ plot v(out) v(out_wp)+2
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: inverter_min_x2/sch/inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sch
+.subckt inverter_min_x2 vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2
+.ends
+
+
+* expanding symbol: inverter_csvco/sch/inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sch
+.subckt inverter_csvco vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/source_follower_buff_diff.sch b/xschem/source_follower_buff_diff.sch
new file mode 100644
index 0000000..0324ad0
--- /dev/null
+++ b/xschem/source_follower_buff_diff.sch
@@ -0,0 +1,58 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1140 -470 1210 -470 { lab=inp}
+N 1340 -470 1410 -470 { lab=outp_int}
+N 1260 -570 1260 -520 { lab=avdd1p8}
+N 1330 -470 1340 -470 { lab=outp_int}
+N 1410 -470 1490 -470 { lab=outp_int}
+N 1260 -420 1260 -370 { lab=avss1p8}
+N 1240 -420 1240 -370 { lab=iref1}
+N 1490 -470 1560 -470 { lab=outp_int}
+N 1690 -470 1760 -470 { lab=outp}
+N 1610 -570 1610 -520 { lab=avdd1p8}
+N 1680 -470 1690 -470 { lab=outp}
+N 1760 -470 1840 -470 { lab=outp}
+N 1610 -420 1610 -370 { lab=avss1p8}
+N 1590 -420 1590 -370 { lab=iref2}
+N 1140 -200 1210 -200 { lab=inn}
+N 1340 -200 1410 -200 { lab=outn_int}
+N 1260 -300 1260 -250 { lab=avdd1p8}
+N 1330 -200 1340 -200 { lab=outn_int}
+N 1410 -200 1490 -200 { lab=outn_int}
+N 1260 -150 1260 -100 { lab=avss1p8}
+N 1240 -150 1240 -100 { lab=iref3}
+N 1490 -200 1560 -200 { lab=outn_int}
+N 1690 -200 1760 -200 { lab=outn}
+N 1610 -300 1610 -250 { lab=avdd1p8}
+N 1680 -200 1690 -200 { lab=outn}
+N 1760 -200 1840 -200 { lab=outn}
+N 1610 -150 1610 -100 { lab=avss1p8}
+N 1590 -150 1590 -100 { lab=iref4}
+C {iopin.sym} 1260 -570 0 0 {name=p5 lab=avdd1p8}
+C {iopin.sym} 1260 -370 0 0 {name=p6 lab=avss1p8}
+C {opin.sym} 1840 -470 2 1 {name=p10 lab=outp}
+C {source_follower_buff_pmos.sym} 1300 -300 0 0 {name=x1}
+C {lab_wire.sym} 1430 -470 0 0 {name=l12 sig_type=std_logic lab=outp_int}
+C {ngspice_probe.sym} 1450 -470 0 0 {name=r12}
+C {lab_wire.sym} 1610 -560 2 0 {name=l11 sig_type=std_logic lab=avdd1p8}
+C {source_follower_buff_nmos.sym} 1650 -300 0 0 {name=x2}
+C {lab_wire.sym} 1610 -380 2 0 {name=l14 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 1260 -290 2 0 {name=l21 sig_type=std_logic lab=avdd1p8}
+C {source_follower_buff_pmos.sym} 1300 -30 0 0 {name=x3}
+C {lab_wire.sym} 1430 -200 0 0 {name=l22 sig_type=std_logic lab=outn_int}
+C {lab_wire.sym} 1260 -110 2 0 {name=l23 sig_type=std_logic lab=avss1p8}
+C {ngspice_probe.sym} 1450 -200 0 0 {name=r17}
+C {lab_wire.sym} 1610 -290 2 0 {name=l26 sig_type=std_logic lab=avdd1p8}
+C {source_follower_buff_nmos.sym} 1650 -30 0 0 {name=x4}
+C {lab_wire.sym} 1610 -110 2 0 {name=l28 sig_type=std_logic lab=avss1p8}
+C {opin.sym} 1840 -200 2 1 {name=p2 lab=outn}
+C {ipin.sym} 1140 -470 0 0 {name=p3 lab=inp}
+C {ipin.sym} 1140 -200 0 0 {name=p4 lab=inn}
+C {ipin.sym} 1240 -370 3 0 {name=p7 lab=iref1}
+C {ipin.sym} 1590 -370 3 0 {name=p8 lab=iref2}
+C {ipin.sym} 1240 -100 3 0 {name=p9 lab=iref3}
+C {ipin.sym} 1590 -100 3 0 {name=p11 lab=iref4}
diff --git a/xschem/source_follower_buff_diff.sym b/xschem/source_follower_buff_diff.sym
new file mode 100644
index 0000000..676890a
--- /dev/null
+++ b/xschem/source_follower_buff_diff.sym
@@ -0,0 +1,64 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 110 -170 130 -170 {}
+L 4 -160 -170 -140 -170 {}
+L 4 -70 -210 -70 -130 {}
+L 4 -70 -130 10 -170 {}
+L 4 -70 -210 10 -170 {}
+L 4 -110 10 -110 30 {}
+L 4 -140 -240 110 -240 {}
+L 4 -30 -130 50 -170 {}
+L 4 -30 -210 50 -170 {}
+L 4 50 -170 110 -170 {}
+L 4 -140 -170 -70 -170 {}
+L 4 -70 -100 -70 -20 {}
+L 4 -70 -20 10 -60 {}
+L 4 -70 -100 10 -60 {}
+L 4 -30 -20 50 -60 {}
+L 4 -30 -100 50 -60 {}
+L 4 50 -60 110 -60 {}
+L 4 -140 -60 -70 -60 {}
+L 4 -140 10 110 10 {}
+L 4 110 -240 110 10 {}
+L 4 -140 -240 -140 10 {}
+L 4 -160 -60 -140 -60 {}
+L 4 110 -60 130 -60 {}
+L 4 -30 -100 -30 -80 {}
+L 4 -30 -40 -30 -20 {}
+L 4 -30 -150 -30 -130 {}
+L 4 -30 -210 -30 -190 {}
+L 4 -90 10 -90 30 {}
+L 4 -70 10 -70 30 {}
+L 4 -50 10 -50 30 {}
+L 7 0 -260 0 -240 {}
+L 7 0 10 0 30 {}
+B 5 -2.5 -262.5 2.5 -257.5 {name=avdd1p8 dir=inout }
+B 5 -112.5 27.5 -107.5 32.5 {name=iref1 dir=in}
+B 5 -162.5 -172.5 -157.5 -167.5 {name=inp dir=in }
+B 5 127.5 -172.5 132.5 -167.5 {name=outp dir=out }
+B 5 -2.5 27.5 2.5 32.5 {name=avss1p8 dir=inout }
+B 5 -162.5 -62.5 -157.5 -57.5 {name=inn dir=in }
+B 5 127.5 -62.5 132.5 -57.5 {name=outn dir=out }
+B 5 -92.5 27.5 -87.5 32.5 {name=iref2 dir=in}
+B 5 -72.5 27.5 -67.5 32.5 {name=iref3 dir=in}
+B 5 -52.5 27.5 -47.5 32.5 {name=iref4 dir=in}
+T {@symname} 11 -226 0 0 0.3 0.3 {}
+T {@name} -65 -172 0 0 0.2 0.2 {}
+T {avdd1p8} 35 -284 0 1 0.2 0.2 {}
+T {iref1} -105 56 1 1 0.2 0.2 {}
+T {inp} -175 -164 0 0 0.2 0.2 {}
+T {outp} 155 -164 0 1 0.2 0.2 {}
+T {avss1p8} 35 36 0 1 0.2 0.2 {}
+T {@name} -65 -62 0 0 0.2 0.2 {}
+T {inn} -175 -54 0 0 0.2 0.2 {}
+T {outn} 155 -54 0 1 0.2 0.2 {}
+T {iref2} -85 56 1 1 0.2 0.2 {}
+T {iref3} -65 56 1 1 0.2 0.2 {}
+T {iref4} -45 56 1 1 0.2 0.2 {}
diff --git a/xschem/source_follower_buff_nmos.sch b/xschem/source_follower_buff_nmos.sch
new file mode 100644
index 0000000..f91bb38
--- /dev/null
+++ b/xschem/source_follower_buff_nmos.sch
@@ -0,0 +1,130 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 790 -260 790 -190 { lab=avss1p8}
+N 790 -350 790 -320 { lab=out}
+N 790 -420 790 -370 { lab=out}
+N 790 -530 790 -480 { lab=avdd1p8}
+N 690 -290 750 -290 { lab=iref}
+N 790 -290 800 -290 { lab=avss1p8}
+N 800 -290 800 -240 { lab=avss1p8}
+N 790 -370 790 -350 { lab=out}
+N 790 -360 860 -360 { lab=out}
+N 520 -350 520 -320 { lab=#net1}
+N 690 -450 750 -450 { lab=in}
+N 560 -290 690 -290 { lab=iref}
+N 510 -290 520 -290 { lab=avss1p8}
+N 510 -290 510 -240 { lab=avss1p8}
+N 520 -190 790 -190 { lab=avss1p8}
+N 670 -190 670 -170 { lab=avss1p8}
+N 510 -240 510 -190 { lab=avss1p8}
+N 510 -190 520 -190 { lab=avss1p8}
+N 520 -260 520 -190 { lab=avss1p8}
+N 800 -240 800 -190 { lab=avss1p8}
+N 790 -190 800 -190 { lab=avss1p8}
+N 790 -450 800 -450 { lab=avss1p8}
+N 800 -450 840 -450 { lab=avss1p8}
+N 520 -370 520 -350 { lab=#net1}
+N 580 -400 580 -290 { lab=iref}
+N 520 -460 520 -430 { lab=iref}
+N 520 -450 580 -450 { lab=iref}
+N 580 -450 580 -400 { lab=iref}
+N 510 -400 520 -400 { lab=avss1p8}
+N 510 -400 510 -290 { lab=avss1p8}
+N 560 -400 580 -400 { lab=iref}
+N 520 -510 520 -460 { lab=iref}
+C {iopin.sym} 790 -530 0 0 {name=p5 lab=avdd1p8}
+C {iopin.sym} 670 -170 0 0 {name=p6 lab=avss1p8}
+C {opin.sym} 860 -360 2 1 {name=p10 lab=out}
+C {ipin.sym} 690 -450 0 0 {name=p12 lab=in}
+C {ngspice_get_value.sym} 325 -255 0 0 {name=r21 node="v(@M.X2.XM2.msky130_fd_pr__nfet_01v8_lvt[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 325 -225 0 0 {name=r22 node="v(@M.X2.XM2.msky130_fd_pr__nfet_01v8_lvt[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 395 -255 0 0 {name=r23 node="v(@M.X2.XM2.msky130_fd_pr__nfet_01v8_lvt[vdsat])"
+descr="vdsat="}
+C {ngspice_get_value.sym} 395 -225 0 0 {name=r24 node="i(@M.X2.XM2.msky130_fd_pr__nfet_01v8_lvt[id])"
+descr="id="}
+C {ngspice_get_value.sym} 325 -195 0 0 {name=r25 node="v(@M.X2.XM2.msky130_fd_pr__nfet_01v8_lvt[vth])"
+descr="vth="}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 540 -290 0 1 {name=M2
+L=0.15
+W=1
+nf=1
+mult=6
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 770 -290 0 0 {name=M1
+L=0.15
+W=1
+nf=1
+mult=160
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 770 -450 0 0 {name=M3
+L=0.15
+W=1
+nf=1
+mult=80
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {ngspice_get_value.sym} 885 -285 0 0 {name=r1 node="v(@M.X2.XM1.msky130_fd_pr__nfet_01v8_lvt[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 885 -255 0 0 {name=r2 node="v(@M.X2.XM1.msky130_fd_pr__nfet_01v8_lvt[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 955 -285 0 0 {name=r3 node="v(@M.X2.XM1.msky130_fd_pr__nfet_01v8_lvt[vdsat])"
+descr="vdsat="}
+C {ngspice_get_value.sym} 955 -255 0 0 {name=r9 node="i(@M.X2.XM1.msky130_fd_pr__nfet_01v8_lvt[id])"
+descr="id="}
+C {ngspice_get_value.sym} 885 -225 0 0 {name=r10 node="v(@M.X2.XM1.msky130_fd_pr__nfet_01v8_lvt[vth])"
+descr="vth="}
+C {ngspice_get_value.sym} 905 -475 0 0 {name=r4 node="v(@M.X2.XM3.msky130_fd_pr__nfet_01v8_lvt[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 905 -445 0 0 {name=r5 node="v(@M.X2.XM3.msky130_fd_pr__nfet_01v8_lvt[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 975 -475 0 0 {name=r6 node="v(@M.X2.XM3.msky130_fd_pr__nfet_01v8_lvt[vdsat])"
+descr="vdsat="}
+C {ngspice_get_value.sym} 975 -445 0 0 {name=r7 node="i(@M.X2.XM3.msky130_fd_pr__nfet_01v8_lvt[id])"
+descr="id="}
+C {ngspice_get_value.sym} 905 -415 0 0 {name=r8 node="v(@M.X2.XM3.msky130_fd_pr__nfet_01v8_lvt[vth])"
+descr="vth="}
+C {lab_wire.sym} 825 -450 2 0 {name=l1 sig_type=std_logic lab=avss1p8}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 540 -400 0 1 {name=M4
+L=0.15
+W=1
+nf=1
+mult=6
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {ipin.sym} 520 -510 1 0 {name=p1 lab=iref}
diff --git a/xschem/source_follower_buff_nmos.sym b/xschem/source_follower_buff_nmos.sym
new file mode 100644
index 0000000..a9c72c6
--- /dev/null
+++ b/xschem/source_follower_buff_nmos.sym
@@ -0,0 +1,29 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 10 -170 30 -170 {}
+L 4 -90 -170 -70 -170 {}
+L 4 -70 -210 -70 -130 {}
+L 4 -70 -130 10 -170 {}
+L 4 -70 -210 10 -170 {}
+L 4 -60 -140 -60 -120 {}
+L 7 -40 -220 -40 -200 {}
+L 7 -40 -140 -40 -120 {}
+B 5 -42.5 -222.5 -37.5 -217.5 {name=avdd1p8 dir=inout }
+B 5 -62.5 -122.5 -57.5 -117.5 {name=iref dir=in}
+B 5 -92.5 -172.5 -87.5 -167.5 {name=in dir=in }
+B 5 27.5 -172.5 32.5 -167.5 {name=out dir=out }
+B 5 -42.5 -122.5 -37.5 -117.5 {name=avss1p8 dir=inout }
+T {@symname} -19 -216 0 0 0.3 0.3 {}
+T {@name} -65 -172 0 0 0.2 0.2 {}
+T {avdd1p8} -5 -244 0 1 0.2 0.2 {}
+T {iref} -65 -114 0 1 0.2 0.2 {}
+T {in} -105 -164 0 0 0.2 0.2 {}
+T {out} 55 -164 0 1 0.2 0.2 {}
+T {avss1p8} -5 -114 0 1 0.2 0.2 {}
diff --git a/xschem/source_follower_buff_pmos.sch b/xschem/source_follower_buff_pmos.sch
new file mode 100644
index 0000000..2767164
--- /dev/null
+++ b/xschem/source_follower_buff_pmos.sch
@@ -0,0 +1,182 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 790 -260 790 -190 { lab=avss1p8}
+N 790 -350 790 -320 { lab=out}
+N 790 -420 790 -370 { lab=out}
+N 790 -530 790 -480 { lab=avdd1p8}
+N 690 -290 750 -290 { lab=in}
+N 520 -420 520 -390 { lab=#net1}
+N 790 -290 800 -290 { lab=avdd1p8}
+N 800 -290 800 -240 { lab=avdd1p8}
+N 510 -450 520 -450 { lab=avdd1p8}
+N 510 -500 510 -450 { lab=avdd1p8}
+N 790 -190 790 -130 { lab=avss1p8}
+N 790 -370 790 -350 { lab=out}
+N 790 -360 860 -360 { lab=out}
+N 560 -450 750 -450 { lab=#net1}
+N 520 -410 580 -410 { lab=#net1}
+N 580 -450 580 -410 { lab=#net1}
+N 520 -200 520 -130 { lab=avss1p8}
+N 520 -290 520 -260 { lab=#net1}
+N 420 -230 480 -230 { lab=iref}
+N 520 -230 530 -230 { lab=avss1p8}
+N 530 -230 530 -180 { lab=avss1p8}
+N 250 -290 250 -260 { lab=iref}
+N 250 -280 290 -280 { lab=iref}
+N 290 -230 420 -230 { lab=iref}
+N 290 -280 310 -280 { lab=iref}
+N 310 -280 310 -230 { lab=iref}
+N 240 -230 250 -230 { lab=avss1p8}
+N 240 -230 240 -180 { lab=avss1p8}
+N 250 -130 520 -130 { lab=avss1p8}
+N 240 -180 240 -130 { lab=avss1p8}
+N 240 -130 250 -130 { lab=avss1p8}
+N 250 -200 250 -130 { lab=avss1p8}
+N 530 -180 530 -130 { lab=avss1p8}
+N 520 -130 530 -130 { lab=avss1p8}
+N 520 -390 520 -290 { lab=#net1}
+N 250 -355 250 -290 { lab=iref}
+N 535 -130 790 -130 { lab=avss1p8}
+N 530 -130 535 -130 { lab=avss1p8}
+N 585 -130 585 -80 { lab=avss1p8}
+N 520 -530 790 -530 { lab=avdd1p8}
+N 520 -530 520 -480 { lab=avdd1p8}
+N 510 -530 510 -500 { lab=avdd1p8}
+N 510 -530 520 -530 { lab=avdd1p8}
+N 620 -560 620 -530 { lab=avdd1p8}
+N 795 -450 800 -450 { lab=avdd1p8}
+N 800 -530 800 -450 { lab=avdd1p8}
+N 790 -530 800 -530 { lab=avdd1p8}
+N 790 -450 795 -450 { lab=avdd1p8}
+C {iopin.sym} 620 -560 0 0 {name=p5 lab=avdd1p8}
+C {iopin.sym} 585 -80 0 0 {name=p6 lab=avss1p8}
+C {ngspice_get_value.sym} 710 -360 0 0 {name=r1 node="v(@M.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 710 -330 0 0 {name=r2 node="v(@M.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 640 -360 0 0 {name=r11 node="i(@M.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[id])"
+descr="id="}
+C {opin.sym} 860 -360 2 1 {name=p10 lab=out}
+C {ipin.sym} 690 -290 0 0 {name=p12 lab=in}
+C {ipin.sym} 250 -355 1 0 {name=p14 lab=iref}
+C {lab_wire.sym} 800 -280 1 1 {name=l13 sig_type=std_logic lab=avdd1p8}
+C {ngspice_get_value.sym} 350 -460 0 0 {name=r21 node="v(@M.X1.XM5.msky130_fd_pr__pfet_01v8[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 350 -430 0 0 {name=r22 node="v(@M.X1.XM5.msky130_fd_pr__pfet_01v8[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 420 -460 0 0 {name=r23 node="v(@M.X1.XM5.msky130_fd_pr__pfet_01v8[vdsat])"
+descr="vdsat="}
+C {ngspice_get_value.sym} 420 -430 0 0 {name=r24 node="i(@M.X1.XM5.msky130_fd_pr__pfet_01v8[id])"
+descr="id="}
+C {ngspice_get_value.sym} 350 -400 0 0 {name=r25 node="v(@M.X1.XM5.msky130_fd_pr__pfet_01v8[vth])"
+descr="vth="}
+C {ngspice_get_value.sym} 640 -300 0 0 {name=r3 node="v(@M.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[vth])"
+descr="vth="}
+C {sky130_fd_pr/pfet_01v8.sym} 540 -450 0 1 {name=M5
+L=0.15
+W=1
+nf=1
+mult=15
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 770 -450 0 0 {name=M6
+L=0.15
+W=1
+nf=1
+mult=15
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {ngspice_get_value.sym} 640 -330 0 0 {name=r33 node="@M.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[gm]"
+descr="gm="}
+C {ngspice_get_value.sym} 710 -300 0 0 {name=r35 node="@M.X1.XM1.msky130_fd_pr__pfet_01v8_lvt[gds]"
+descr="gds="}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 770 -290 0 0 {name=M1
+L=0.35
+W=1
+nf=1
+mult=20
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {ngspice_get_value.sym} 900 -460 0 0 {name=r4 node="v(@M.X1.XM6.msky130_fd_pr__pfet_01v8[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 900 -430 0 0 {name=r5 node="v(@M.X1.XM6.msky130_fd_pr__pfet_01v8[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 970 -460 0 0 {name=r6 node="v(@M.X1.XM6.msky130_fd_pr__pfet_01v8[vdsat])"
+descr="vdsat="}
+C {ngspice_get_value.sym} 970 -430 0 0 {name=r7 node="i(@M.X1.XM6.msky130_fd_pr__pfet_01v8[id])"
+descr="id="}
+C {ngspice_get_value.sym} 900 -400 0 0 {name=r8 node="v(@M.X1.XM6.msky130_fd_pr__pfet_01v8[vth])"
+descr="vth="}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 270 -230 0 1 {name=M2
+L=0.15
+W=1
+nf=1
+mult=6
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8_lvt.sym} 500 -230 0 0 {name=M3
+L=0.15
+W=1
+nf=1
+mult=6
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {ngspice_get_value.sym} 115 -290 0 0 {name=r9 node="v(@M.X1.XM2.msky130_fd_pr__nfet_01v8_lvt[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 115 -260 0 0 {name=r10 node="v(@M.X1.XM2.msky130_fd_pr__nfet_01v8_lvt[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 185 -290 0 0 {name=r12 node="v(@M.X1.XM2.msky130_fd_pr__nfet_01v8_lvt[vdsat])"
+descr="vdsat="}
+C {ngspice_get_value.sym} 185 -260 0 0 {name=r13 node="i(@M.X1.XM2.msky130_fd_pr__nfet_01v8_lvt[id])"
+descr="id="}
+C {ngspice_get_value.sym} 115 -230 0 0 {name=r14 node="v(@M.X1.XM2.msky130_fd_pr__nfet_01v8_lvt[vth])"
+descr="vth="}
+C {ngspice_get_value.sym} 605 -205 0 0 {name=r15 node="v(@M.X1.XM3.msky130_fd_pr__nfet_01v8_lvt[vgs])"
+descr="vgs="}
+C {ngspice_get_value.sym} 605 -175 0 0 {name=r16 node="v(@M.X1.XM3.msky130_fd_pr__nfet_01v8_lvt[vds])"
+descr="vds="}
+C {ngspice_get_value.sym} 675 -205 0 0 {name=r17 node="v(@M.X1.XM3.msky130_fd_pr__nfet_01v8_lvt[vdsat])"
+descr="vdsat="}
+C {ngspice_get_value.sym} 675 -175 0 0 {name=r18 node="i(@M.X1.XM3.msky130_fd_pr__nfet_01v8_lvt[id])"
+descr="id="}
+C {ngspice_get_value.sym} 605 -145 0 0 {name=r19 node="v(@M.X1.XM3.msky130_fd_pr__nfet_01v8_lvt[vth])"
+descr="vth="}
diff --git a/xschem/source_follower_buff_pmos.sym b/xschem/source_follower_buff_pmos.sym
new file mode 100644
index 0000000..e61acf1
--- /dev/null
+++ b/xschem/source_follower_buff_pmos.sym
@@ -0,0 +1,29 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 10 -170 30 -170 {}
+L 4 -90 -170 -70 -170 {}
+L 4 -70 -210 -70 -130 {}
+L 4 -70 -130 10 -170 {}
+L 4 -70 -210 10 -170 {}
+L 4 -60 -140 -60 -120 {}
+L 7 -40 -220 -40 -200 {}
+L 7 -40 -140 -40 -120 {}
+B 5 -42.5 -222.5 -37.5 -217.5 {name=avdd1p8 dir=inout }
+B 5 -62.5 -122.5 -57.5 -117.5 {name=iref dir=out }
+B 5 -92.5 -172.5 -87.5 -167.5 {name=in dir=in }
+B 5 27.5 -172.5 32.5 -167.5 {name=out dir=out }
+B 5 -42.5 -122.5 -37.5 -117.5 {name=avss1p8 dir=inout }
+T {@symname} -19 -216 0 0 0.3 0.3 {}
+T {@name} -65 -172 0 0 0.2 0.2 {}
+T {avdd1p8} -5 -244 0 1 0.2 0.2 {}
+T {iref} -65 -114 0 1 0.2 0.2 {}
+T {in} -105 -164 0 0 0.2 0.2 {}
+T {out} 55 -164 0 1 0.2 0.2 {}
+T {avss1p8} -5 -114 0 1 0.2 0.2 {}
diff --git a/xschem/tb_DFF.sch b/xschem/tb_DFF.sch
new file mode 100644
index 0000000..3a14b17
--- /dev/null
+++ b/xschem/tb_DFF.sch
@@ -0,0 +1,101 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -350 -370 -350 -340 { lab=GND}
+N -200 -370 -200 -340 { lab=vss}
+N 370 -370 370 -340 { lab=vss}
+N -280 -370 -280 -340 { lab=vss}
+N -350 -460 -350 -430 { lab=vss}
+N -200 -460 -200 -430 { lab=B}
+N 370 -460 370 -430 { lab=A}
+N -280 -460 -280 -430 { lab=vdd}
+N -60 -170 -20 -170 { lab=vdd}
+N -50 -140 -20 -140 { lab=A}
+N 30 -80 30 -50 { lab=B}
+N 30 -230 30 -200 { lab=vss}
+N 80 -170 150 -170 { lab=Q}
+N 220 -30 220 0 { lab=vss}
+N 220 -260 220 -230 { lab=vdd}
+N 390 -190 390 -130 { lab=Up}
+N 290 -190 390 -190 { lab=Up}
+N 390 -70 390 -40 { lab=vss}
+C {vsource.sym} -350 -400 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -280 -400 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} 370 -400 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {vsource.sym} -200 -400 0 0 {name=Vdiv
+value="PULSE(0 \{vin\} 0 1p 1p \{1.05*Tref/2\} \{1.05*Tref\}) DC \{vin\} AC 0"
+}
+C {gnd.sym} -350 -340 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -350 -460 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 -340 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 370 -340 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -200 -340 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 -460 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -200 -460 3 1 {name=l8 sig_type=std_logic lab=B}
+C {lab_pin.sym} 370 -460 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} -380 -200 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = 1.8
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 1f
+
+.options TEMP = 50.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/dff_pfd_pex_c.spice
+
+.ic v(net3) = 0.0
+.ic v(net4) = 0.0
+.ic v(Q) = 0.0
+
+* Data to save
+.save all
+
+* Simulation
+.control
+ tran 0.1ns 200ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ write tb_DFF_nor_tran.raw
+ plot v(A)+2 v(B)+2 v(Q)
+.endc
+
+.end
+"}
+C {lab_pin.sym} -60 -170 0 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -50 -140 2 1 {name=l9 sig_type=std_logic lab=A}
+C {lab_pin.sym} 30 -50 3 0 {name=l10 sig_type=std_logic lab=B}
+C {lab_pin.sym} 30 -230 1 0 {name=l11 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 120 -170 0 0 {name=l18 sig_type=std_logic lab=Q}
+C {lab_pin.sym} 220 -260 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 220 0 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {noconn.sym} 290 -70 2 0 {name=l15}
+C {noconn.sym} 290 -110 2 0 {name=l16}
+C {noconn.sym} 290 -150 2 0 {name=l17}
+C {noconn.sym} 150 -90 0 0 {name=l20}
+C {capa.sym} 390 -100 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 390 -40 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 370 -190 0 0 {name=l21 sig_type=std_logic lab=Up}
+C {pfd_cp_interface_pex_c.sym} 220 -130 0 0 {name=x2}
+C {dff_pfd_pex_c.sym} 30 -140 0 0 {name=x1}
diff --git a/xschem/tb_PFD.sch b/xschem/tb_PFD.sch
new file mode 100644
index 0000000..9902432
--- /dev/null
+++ b/xschem/tb_PFD.sch
@@ -0,0 +1,86 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 570 -250 570 -220 { lab=GND}
+N -350 -160 -350 -130 { lab=vss}
+N -350 -360 -350 -330 { lab=vss}
+N 640 -250 640 -220 { lab=vss}
+N 570 -340 570 -310 { lab=vss}
+N -350 -250 -350 -220 { lab=B}
+N -350 -450 -350 -420 { lab=A}
+N 640 -340 640 -310 { lab=vdd}
+N 170 -410 170 -380 { lab=vss}
+N 30 -320 70 -320 { lab=A}
+N 70 -320 80 -320 { lab=A}
+N 30 -240 80 -240 { lab=B}
+N 130 -410 130 -380 { lab=vdd}
+N 220 -320 340 -320 { lab=QA}
+N 220 -240 340 -240 { lab=QB}
+N 410 -180 410 -150 { lab=vss}
+N 410 -410 410 -380 { lab=vdd}
+N 150 -180 150 -140 { lab=Reset}
+C {PFD.sym} 150 -280 0 0 {name=x1}
+C {vsource.sym} 570 -280 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} 640 -280 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -350 -390 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} 570 -220 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 570 -340 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 640 -220 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 -330 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 -130 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 640 -340 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -350 -250 3 1 {name=l8 sig_type=std_logic lab=B}
+C {lab_pin.sym} -350 -450 3 1 {name=l14 sig_type=std_logic lab=A}
+C {lab_pin.sym} 30 -320 2 1 {name=l15 sig_type=std_logic lab=A}
+C {lab_pin.sym} 30 -240 2 1 {name=l16 sig_type=std_logic lab=B}
+C {lab_pin.sym} 130 -410 1 0 {name=l17 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 170 -410 1 0 {name=l18 sig_type=std_logic lab=vss}
+C {netlist_not_shown.sym} 750 -330 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 10f
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 400ns
+ write tb_PFD_tran.raw
+ plot v(Reset) v(QB)+2 v(QA)+4 v(A)+6 v(B)+6
+
+.endc
+
+.end
+"}
+C {vsource.sym} -350 -190 0 0 {name=Vdiv value="PULSE(0 \{vin\} 0 1p 1p \{1.05*Tref/2\} \{1.05*Tref\}) DC \{vin\} AC 0"}
+C {lab_wire.sym} 290 -320 0 0 {name=l37 sig_type=std_logic lab=QA}
+C {lab_wire.sym} 290 -240 0 0 {name=l38 sig_type=std_logic lab=QB}
+C {lab_pin.sym} 410 -410 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -150 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {noconn.sym} 480 -220 2 0 {name=l9}
+C {noconn.sym} 480 -260 2 0 {name=l10}
+C {noconn.sym} 480 -300 2 0 {name=l12}
+C {noconn.sym} 480 -340 2 0 {name=l13}
+C {pfd_cp_interface_pex_c.sym} 410 -280 0 0 {name=x2}
+C {lab_wire.sym} 150 -170 3 0 {name=l19 sig_type=std_logic lab=Reset}
+C {noconn.sym} 150 -140 3 0 {name=l20}
diff --git a/xschem/tb_PFD_pex.sch b/xschem/tb_PFD_pex.sch
new file mode 100644
index 0000000..31356ab
--- /dev/null
+++ b/xschem/tb_PFD_pex.sch
@@ -0,0 +1,95 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -350 -370 -350 -340 { lab=GND}
+N -350 20 -350 50 { lab=vss}
+N -350 -180 -350 -150 { lab=vss}
+N -280 -370 -280 -340 { lab=vss}
+N -350 -460 -350 -430 { lab=vss}
+N -350 -70 -350 -40 { lab=B}
+N -350 -270 -350 -240 { lab=A}
+N -280 -460 -280 -430 { lab=vdd}
+N 210 -370 210 -340 { lab=vss}
+N 70 -280 110 -280 { lab=A}
+N 110 -280 120 -280 { lab=A}
+N 70 -200 120 -200 { lab=B}
+N 170 -370 170 -340 { lab=vdd}
+N 260 -280 380 -280 { lab=QA}
+N 260 -200 380 -200 { lab=QB}
+N 450 -140 450 -110 { lab=vss}
+N 450 -370 450 -340 { lab=vdd}
+N 190 -140 190 -110 { lab=Reset}
+C {vsource.sym} -350 -400 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -280 -400 0 0 {name=VDD value=\{vdd\}}
+C {gnd.sym} -350 -340 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -350 -460 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 -340 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 -150 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 50 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 -460 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -350 -70 3 1 {name=l8 sig_type=std_logic lab=B}
+C {lab_pin.sym} -350 -270 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} -170 -450 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 10f
+
+.options TEMP = 100.0
+.option RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+
+* Simulation
+.control
+ tran 0.001ns 400ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ write tb_PFD_pex_tran.raw
+ plot v(Reset) v(QB)+2 v(QA)+4 v(A)+6 v(B)+6
+.endc
+
+.end
+"}
+C {lab_pin.sym} 70 -280 2 1 {name=l41 sig_type=std_logic lab=A}
+C {lab_pin.sym} 70 -200 2 1 {name=l42 sig_type=std_logic lab=B}
+C {lab_pin.sym} 170 -370 1 0 {name=l43 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 210 -370 1 0 {name=l44 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 330 -280 0 0 {name=l63 sig_type=std_logic lab=QA}
+C {lab_wire.sym} 330 -200 0 0 {name=l64 sig_type=std_logic lab=QB}
+C {vsource.sym} -350 -10 0 0 {name=Vdiv value="PULSE(0 \{vin\} 0 1p 1p \{1.05*Tref/2\} \{1.05*Tref\}) DC \{vin\} AC 0"}
+C {vsource.sym} -350 -210 0 0 {name=Vref1 value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} 450 -370 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 450 -110 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {noconn.sym} 520 -180 2 0 {name=l9}
+C {noconn.sym} 520 -220 2 0 {name=l10}
+C {noconn.sym} 520 -260 2 0 {name=l12}
+C {noconn.sym} 520 -300 2 0 {name=l13}
+C {pfd_cp_interface_pex_c.sym} 450 -240 0 0 {name=x2}
+C {PFD_pex_c.sym} 190 -240 0 0 {name=x1}
+C {lab_wire.sym} 190 -130 3 0 {name=l15 sig_type=std_logic lab=Reset}
+C {noconn.sym} 190 -110 3 0 {name=l16}
diff --git a/xschem/tb_buffer_salida.sch b/xschem/tb_buffer_salida.sch
new file mode 100644
index 0000000..c215ac1
--- /dev/null
+++ b/xschem/tb_buffer_salida.sch
@@ -0,0 +1,90 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 40 50 40 80 { lab=vss}
+N 40 -80 40 -50 { lab=vdd}
+N 600 0 680 0 { lab=out}
+N -60 -0 0 0 { lab=pll_out}
+N 40 80 40 100 { lab=vss}
+N 40 -100 40 -80 { lab=vdd}
+N -440 120 -440 170 { lab=GND}
+N -260 120 -260 170 { lab=vss}
+N -350 120 -350 170 { lab=vss}
+N -440 10 -440 60 { lab=vss}
+N -260 10 -260 60 { lab=pll_out}
+N -350 10 -350 60 { lab=vdd}
+N 680 0 680 20 { lab=out}
+N 680 80 680 100 { lab=vss}
+N 260 50 260 80 { lab=vss}
+N 260 -80 260 -50 { lab=vdd}
+N 260 80 260 100 { lab=vss}
+N 260 -100 260 -80 { lab=vdd}
+N 130 0 220 -0 { lab=in}
+N 350 0 430 -0 { lab=int1}
+N 430 -0 450 -0 { lab=int1}
+N 580 -0 600 0 { lab=out}
+N 490 -90 490 -50 { lab=vdd}
+N 260 -90 490 -90 { lab=vdd}
+N 490 50 490 80 { lab=vss}
+N 260 80 490 80 { lab=vss}
+C {lab_pin.sym} 40 -100 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 40 100 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 650 0 0 0 {name=l3 sig_type=std_logic lab=out}
+C {vsource.sym} -440 90 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -350 90 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -260 90 0 0 {name=VIN value="PULSE(0 \{vin\} 0 1p 1p \{T/2\} \{T\}) DC \{vin\} AC 0"}
+C {gnd.sym} -440 170 0 0 {name=l9 lab=GND}
+C {lab_pin.sym} -350 170 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -260 170 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 10 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -260 10 1 0 {name=l13 sig_type=std_logic lab=pll_out}
+C {lab_pin.sym} -440 10 1 0 {name=l14 sig_type=std_logic lab=vss}
+C {netlist_not_shown.sym} -400 -180 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param vdd = 1.8
+.param vss = 0
+.param vin = 1.8
+.param T = 1n
+.param C = 10f
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+
+
+* Simulation
+.control
+
+ reset
+
+ tran .001ns 10ns
+
+
+ plot v(in) v(int1)+2 v(out)+4
+.endc
+
+.end
+"}
+C {capa.sym} 680 50 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 680 100 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 190 0 0 0 {name=l5 sig_type=std_logic lab=in}
+C {inverter_min_x4.sym} 60 0 0 0 {name=x1}
+C {lab_pin.sym} 260 -100 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 260 100 3 0 {name=l7 sig_type=std_logic lab=vss}
+C {inverter_min_x4.sym} 280 0 0 0 {name=x3}
+C {lab_pin.sym} -40 0 0 0 {name=l18 sig_type=std_logic lab=pll_out}
+C {lab_pin.sym} 400 0 0 0 {name=l19 sig_type=std_logic lab=int1}
+C {buffer_salida.sym} 510 0 0 0 {name=x2}
diff --git a/xschem/tb_buffer_salida_pex_c.sch b/xschem/tb_buffer_salida_pex_c.sch
new file mode 100644
index 0000000..eeee5fe
--- /dev/null
+++ b/xschem/tb_buffer_salida_pex_c.sch
@@ -0,0 +1,92 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 40 50 40 80 { lab=vss}
+N 40 -80 40 -50 { lab=vdd}
+N 600 0 680 0 { lab=out}
+N -60 -0 0 0 { lab=pll_out}
+N 40 80 40 100 { lab=vss}
+N 40 -100 40 -80 { lab=vdd}
+N -440 120 -440 170 { lab=GND}
+N -260 120 -260 170 { lab=vss}
+N -350 120 -350 170 { lab=vss}
+N -440 10 -440 60 { lab=vss}
+N -260 10 -260 60 { lab=pll_out}
+N -350 10 -350 60 { lab=vdd}
+N 680 0 680 20 { lab=out}
+N 680 80 680 100 { lab=vss}
+N 260 50 260 80 { lab=vss}
+N 260 -80 260 -50 { lab=vdd}
+N 260 80 260 100 { lab=vss}
+N 260 -100 260 -80 { lab=vdd}
+N 130 0 220 -0 { lab=in}
+N 350 0 430 -0 { lab=int1}
+N 430 -0 450 -0 { lab=int1}
+N 580 -0 600 0 { lab=out}
+N 490 -90 490 -50 { lab=vdd}
+N 260 -90 490 -90 { lab=vdd}
+N 490 50 490 80 { lab=vss}
+N 260 80 490 80 { lab=vss}
+C {lab_pin.sym} 40 -100 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 40 100 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 650 0 0 0 {name=l3 sig_type=std_logic lab=out}
+C {vsource.sym} -440 90 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -350 90 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -260 90 0 0 {name=VIN value="PULSE(0 \{vin\} 0 1p 1p \{T/2\} \{T\}) DC \{vin\} AC 0"}
+C {gnd.sym} -440 170 0 0 {name=l9 lab=GND}
+C {lab_pin.sym} -350 170 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -260 170 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 10 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -260 10 1 0 {name=l13 sig_type=std_logic lab=pll_out}
+C {lab_pin.sym} -440 10 1 0 {name=l14 sig_type=std_logic lab=vss}
+C {netlist_not_shown.sym} -400 -180 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param vdd = 1.8
+.param vss = 0
+.param vin = 1.8
+.param T = 1n
+.param C = 10f
+
+.options TEMP = 27.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/caravel_analog_fulgor/xschem/simulations/buffer_salida_pex_c.spice
+
+
+* Data to save
+.save all
+
+
+* Simulation
+.control
+
+ reset
+
+ tran .001ns 10ns
+
+
+ plot v(in) v(int1)+2 v(out)+4
+.endc
+
+.end
+"}
+C {capa.sym} 680 50 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 680 100 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 190 0 0 0 {name=l5 sig_type=std_logic lab=in}
+C {inverter_min_x4.sym} 60 0 0 0 {name=x1}
+C {lab_pin.sym} 260 -100 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 260 100 3 0 {name=l7 sig_type=std_logic lab=vss}
+C {inverter_min_x4.sym} 280 0 0 0 {name=x3}
+C {lab_pin.sym} -40 0 0 0 {name=l18 sig_type=std_logic lab=pll_out}
+C {lab_pin.sym} 400 0 0 0 {name=l19 sig_type=std_logic lab=int1}
+C {buffer_salida_pex_c.sym} 510 0 0 0 {name=x2}
diff --git a/xschem/tb_charge_pump.sch b/xschem/tb_charge_pump.sch
new file mode 100644
index 0000000..f3f1075
--- /dev/null
+++ b/xschem/tb_charge_pump.sch
@@ -0,0 +1,252 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -210 -640 -210 -610 { lab=GND}
+N 530 -640 530 -610 { lab=vss}
+N 160 -640 160 -610 { lab=vss}
+N -140 -640 -140 -610 { lab=vss}
+N -210 -730 -210 -700 { lab=vss}
+N 530 -730 530 -700 { lab=#net1}
+N 160 -730 160 -700 { lab=#net2}
+N -140 -730 -140 -700 { lab=vdd}
+N 450 -310 540 -310 { lab=nUp}
+N 450 -270 540 -270 { lab=Down}
+N 490 -230 540 -230 { lab=nDown}
+N 490 -350 540 -350 { lab=Up}
+N 640 -420 640 -390 { lab=vdd}
+N 670 -420 670 -390 { lab=vss}
+N 970 -290 970 -220 { lab=vctrl}
+N 880 -290 880 -270 { lab=vctrl}
+N 880 -210 880 -170 { lab=#net3}
+N 880 -110 880 -80 { lab=vss}
+N 970 -160 970 -130 { lab=vss}
+N 880 -290 970 -290 { lab=vctrl}
+N 450 -350 490 -350 { lab=Up}
+N 450 -230 490 -230 { lab=nDown}
+N 580 -430 580 -390 { lab=iref_cp}
+N 270 -330 310 -330 { lab=QA}
+N 270 -250 310 -250 { lab=QB}
+N 380 -420 380 -390 { lab=vdd}
+N 380 -190 380 -160 { lab=vss}
+N 120 -420 120 -390 { lab=vdd}
+N 160 -420 160 -390 { lab=vss}
+N 80 -770 110 -770 { lab=vdd}
+N 210 -770 240 -770 { lab=vss}
+N 160 -890 160 -860 { lab=#net4}
+N 80 -930 110 -930 { lab=vdd}
+N 210 -930 240 -930 { lab=vss}
+N 160 -1060 160 -1020 { lab=QA}
+N 530 -760 530 -730 { lab=#net1}
+N 450 -800 480 -800 { lab=vdd}
+N 580 -800 610 -800 { lab=vss}
+N 530 -920 530 -890 { lab=#net5}
+N 450 -960 480 -960 { lab=vdd}
+N 580 -960 610 -960 { lab=vss}
+N 530 -1090 530 -1050 { lab=QB}
+N 710 -290 750 -290 { lab=cp_out}
+N 750 -290 770 -290 { lab=cp_out}
+N 830 -290 880 -290 { lab=vctrl}
+N 590 -190 590 -140 { lab=nswitch}
+N 620 -190 620 -140 { lab=pswitch}
+N 140 -190 140 -140 { lab=Reset}
+N 650 -190 650 -140 { lab=biasp}
+N -180 -490 -180 -460 { lab=vdd}
+N -200 -100 -200 -70 { lab=vss}
+N -120 -420 -80 -420 { lab=iref_cp}
+N -200 -190 -200 -160 { lab=#net6}
+N -200 -200 -200 -190 { lab=#net6}
+N -160 -200 -160 -170 { lab=vss}
+N -120 -400 -80 -400 { lab=#net7}
+N -120 -380 -80 -380 { lab=#net8}
+N -120 -360 -80 -360 { lab=#net9}
+N -120 -340 -80 -340 { lab=#net10}
+N -120 -320 -80 -320 { lab=#net11}
+N -120 -300 -80 -300 { lab=#net12}
+N -120 -280 -80 -280 { lab=#net13}
+N -120 -260 -80 -260 { lab=#net14}
+N -120 -240 -80 -240 { lab=#net15}
+C {vsource.sym} -210 -670 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -140 -670 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} 160 -670 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -210 -610 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -210 -730 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -140 -610 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 160 -610 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 530 -610 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -140 -730 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 530 -1090 3 1 {name=l8 sig_type=std_logic lab=QB}
+C {lab_pin.sym} 160 -1060 3 1 {name=l14 sig_type=std_logic lab=QA}
+C {netlist_not_shown.sym} -30 -720 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param Cn = 0.0001fF
+.param Cp = 0.0001fF
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+*.include ~/caravel_analog_fulgor/xschem/simulations/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/charge_pump_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+.ic v(vctrl) = 0.0
+
+* Simulation
+.control
+ op
+ echo .
+ echo ---- M1 bias ----
+ print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[id]
+ print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vds]
+ print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+ print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vgs]
+ echo ---- M2 bias ----
+ print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[id]
+ print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vds]
+ print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+ print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vgs]
+ echo ---- M3 bias ----
+ print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[id]
+ print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vds]
+ print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+ print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vgs]
+ echo ---- M4 bias ----
+ print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[id]
+ print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vds]
+ print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+ print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vgs]
+ echo ---- M5 bias ----
+ print @M.X4.XM5.msky130_fd_pr__nfet_01v8[id]
+ print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vds]
+ print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vdsat]
+ print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vgs]
+ echo ---- M6 bias ----
+ print @M.X4.XM6.msky130_fd_pr__nfet_01v8[id]
+ print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vds]
+ print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vdsat]
+ print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vgs]
+ echo ---- M7 bias ----
+ print @M.X4.XM7.msky130_fd_pr__pfet_01v8[id]
+ print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vds]
+ print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vdsat]
+ print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vgs]
+ echo --- Cgs ---
+ print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgs]
+ print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgs]
+ echo --- Cgs ---
+ print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgd]
+ print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgd]
+ echo --- Cgs ---
+ print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgb]
+ print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgb]
+ echo --- Cgs ---
+ print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgg]
+ print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgg]
+
+ reset
+
+
+ tran 0.01ns 400ns
+ write tb_cp_gate_switched_tran.raw
+ plot i(v.x2.vm1) i(v.x2.vm2)
+ plot v(vctrl) v(nDown)+2 v(Down)+4 v(nUp)+6 v(Up)+8 v(QB)+10 v(QA)+12
+ plot v(pswitch) v(nswitch) xlimit 4ns 44ns
+.endc
+
+.end
+"}
+C {lab_wire.sym} 490 -350 0 0 {name=l20 sig_type=std_logic lab=Up}
+C {lab_wire.sym} 510 -270 0 0 {name=l21 sig_type=std_logic lab=Down}
+C {vsource.sym} 530 -670 0 0 {name=Vdiv value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} 640 -420 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 670 -420 1 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 490 -310 0 0 {name=l29 sig_type=std_logic lab=nUp}
+C {lab_wire.sym} 520 -230 0 0 {name=l30 sig_type=std_logic lab=nDown}
+C {capa.sym} 880 -140 0 0 {name=C1
+m=1
+value=33.5p
+footprint=1206
+device="ceramic capacitor"}
+C {res.sym} 880 -240 0 0 {name=R1
+value=2k
+footprint=1206
+device=resistor
+m=1}
+C {capa.sym} 970 -190 0 0 {name=C2
+m=1
+value=6.7p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 880 -80 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 970 -130 3 0 {name=l36 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 960 -290 0 0 {name=l37 sig_type=std_logic lab=vctrl}
+C {vsource.sym} 800 -290 3 0 {name=vout value=0}
+C {lab_pin.sym} 580 -430 1 0 {name=l25 sig_type=std_logic lab=iref_cp}
+C {PFD.sym} 140 -290 0 0 {name=x1}
+C {lab_pin.sym} 380 -420 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 380 -160 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 120 -420 1 0 {name=l15 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 160 -420 1 0 {name=l17 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 300 -330 0 0 {name=l31 sig_type=std_logic lab=QA}
+C {lab_wire.sym} 300 -250 0 0 {name=l32 sig_type=std_logic lab=QB}
+C {inverter_cp_x2.sym} 160 -790 3 0 {name=x5}
+C {lab_pin.sym} 80 -770 0 0 {name=l44 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 240 -770 2 0 {name=l45 sig_type=std_logic lab=vss}
+C {inverter_cp_x2.sym} 160 -950 3 0 {name=x6}
+C {lab_pin.sym} 80 -930 0 0 {name=l46 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 240 -930 2 0 {name=l47 sig_type=std_logic lab=vss}
+C {inverter_cp_x2.sym} 530 -820 3 0 {name=x7}
+C {lab_pin.sym} 450 -800 0 0 {name=l48 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 610 -800 2 0 {name=l49 sig_type=std_logic lab=vss}
+C {inverter_cp_x2.sym} 530 -980 3 0 {name=x8}
+C {lab_pin.sym} 450 -960 0 0 {name=l50 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 610 -960 2 0 {name=l51 sig_type=std_logic lab=vss}
+C {pfd_cp_interface_pex_c.sym} 380 -290 0 0 {name=x3}
+C {noconn.sym} 210 -330 2 0 {name=l33}
+C {noconn.sym} 210 -250 2 0 {name=l34}
+C {lab_wire.sym} 760 -290 0 0 {name=l42 sig_type=std_logic lab=cp_out}
+C {noconn.sym} 590 -140 3 0 {name=l38}
+C {noconn.sym} 620 -140 3 0 {name=l39}
+C {lab_wire.sym} 590 -180 3 0 {name=l40 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} 620 -180 3 0 {name=l41 sig_type=std_logic lab=pswitch}
+C {noconn.sym} 70 -250 0 0 {name=l18}
+C {noconn.sym} 70 -330 0 0 {name=l26}
+C {noconn.sym} 140 -140 3 0 {name=l13}
+C {lab_wire.sym} 140 -180 3 0 {name=l16 sig_type=std_logic lab=Reset}
+C {noconn.sym} 650 -140 3 0 {name=l19}
+C {lab_wire.sym} 650 -180 3 0 {name=l23 sig_type=std_logic lab=biasp}
+C {charge_pump_pex_c.sym} 620 -290 0 0 {name=x2}
+C {lab_pin.sym} -180 -490 1 0 {name=l10 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -200 -70 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -80 -420 2 0 {name=l12 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -200 -130 0 0 {name=I0 value=100u}
+C {lab_pin.sym} -160 -170 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {noconn.sym} -80 -400 2 0 {name=l75}
+C {noconn.sym} -80 -380 2 0 {name=l76}
+C {noconn.sym} -80 -360 2 0 {name=l77}
+C {noconn.sym} -80 -340 2 0 {name=l78}
+C {noconn.sym} -80 -320 2 0 {name=l79}
+C {noconn.sym} -80 -300 2 0 {name=l80}
+C {noconn.sym} -80 -280 2 0 {name=l81}
+C {noconn.sym} -80 -260 2 0 {name=l82}
+C {noconn.sym} -80 -240 2 0 {name=l83}
+C {bias_pex_c.sym} -180 -330 0 0 {name=x4}
diff --git a/xschem/tb_csvco.sch b/xschem/tb_csvco.sch
new file mode 100644
index 0000000..9a26ee9
--- /dev/null
+++ b/xschem/tb_csvco.sch
@@ -0,0 +1,182 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 70 30 70 70 { lab=GND}
+N 70 -60 70 -30 { lab=vss}
+N 150 -60 150 -30 { lab=vdd}
+N 150 30 150 70 { lab=vss}
+N 760 0 850 0 { lab=out_ro_n}
+N 670 50 670 80 { lab=vss}
+N 670 80 890 80 { lab=vss}
+N 890 50 890 80 { lab=vss}
+N 1050 0 1050 50 { lab=out_ro_buf}
+N 980 0 1050 0 { lab=out_ro_buf}
+N 1050 110 1050 150 { lab=vss}
+N 240 -60 240 -30 { lab=vctrl}
+N 240 30 240 70 { lab=vss}
+N 510 80 670 80 { lab=vss}
+N 380 0 410 0 { lab=vctrl}
+N 280 -370 280 -340 { lab=D0}
+N 280 -280 280 -240 { lab=vss}
+N 580 -0 630 -0 { lab=out_ro}
+N 510 70 510 80 { lab=vss}
+N 410 -0 440 -0 { lab=vctrl}
+N 510 -100 510 -70 { lab=vdd}
+N 670 -80 670 -50 { lab=vdd}
+N 890 -80 890 -50 { lab=vdd}
+N 410 40 440 40 { lab=D0}
+C {netlist_not_shown.sym} 80 -320 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+ tran 0.01ns 50ns
+ meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+ meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+ let T = Tosc/10.0
+ let Tbuf = Toscbuf/10.0
+ let f = 1/T
+ let fbuf = 1/Tbuf
+ let Td = 1/(2*3*f)
+ print T Tbuf f fbuf Td
+ let i = i + 0.1
+ alterparam vctrl = $&i
+ reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+* let i = 0
+* let j = 0
+* while j < 2
+* while i < 2
+* tran 0.1ns 100us
+* meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+* meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+* let T = Tosc/10.0
+* let Tbuf = Toscbuf/10.0
+* let f = 1/T
+* let fbuf = 1/Tbuf
+* let Td = 1/(2*3*f)
+* print T Tbuf f fbuf Td
+* let i = i + 1
+* alterparam vctrl = 1.8
+* reset
+* end
+* alterparam vctrl = 0.7
+* alterparam vd0 = 0.0
+* alterparam vd1 = 1.8
+* alterparam vd2 = 1.8
+* alterpatam vd3 = 0.0
+* let i = 0
+* let j = j + 1
+* reset
+* end
+* plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+* plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+* plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+* plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+* print tran1.f tran2.f tran3.f tran4.f
+* let frange_vtun_0 = tran2.f - tran1.f
+* let frange_vtun_1 = tran4.f - tran3.f
+* print frange_vtun_0 frange_vtun_1
+.endc
+
+.end
+"}
+C {vsource.sym} 70 0 0 0 {name=vss value=\{vss\}}
+C {gnd.sym} 70 70 0 0 {name=l7 lab=GND}
+C {vsource.sym} 150 0 0 0 {name=vdd value=\{vdd\}}
+C {lab_pin.sym} 70 -60 1 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 150 -60 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 70 3 0 {name=l12 sig_type=std_logic lab=vss}
+C {inverter_min_x2.sym} 690 0 0 0 {name=x1}
+C {inverter_min_x4.sym} 910 0 0 0 {name=x2}
+C {capa.sym} 1050 80 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1050 150 3 0 {name=l23 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 830 0 0 0 {name=l24 sig_type=std_logic lab=out_ro_n}
+C {lab_wire.sym} 1040 0 0 0 {name=l25 sig_type=std_logic lab=out_ro_buf}
+C {lab_wire.sym} 820 80 0 0 {name=l27 sig_type=std_logic lab=vss}
+C {vsource.sym} 240 0 0 0 {name=Vctrl value="DC \{vctrl\}" }
+C {lab_pin.sym} 240 -60 1 0 {name=l49 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 240 70 3 0 {name=l50 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 380 0 0 0 {name=l1 sig_type=std_logic lab=vctrl}
+C {lab_wire.sym} 620 0 0 0 {name=l2 sig_type=std_logic lab=out_ro}
+C {vsource.sym} 280 -310 0 0 {name=VD0 value="DC \{vd0\}" }
+C {lab_pin.sym} 280 -370 1 0 {name=l3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 280 -240 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 510 -100 1 0 {name=l30 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 670 -80 1 0 {name=l26 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 890 -80 1 0 {name=l43 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 40 0 0 {name=l11 sig_type=std_logic lab=D0}
+C {csvco.sym} 510 0 0 0 {name=x3}
diff --git a/xschem/tb_csvco_pex_c.sch b/xschem/tb_csvco_pex_c.sch
new file mode 100644
index 0000000..8fadb37
--- /dev/null
+++ b/xschem/tb_csvco_pex_c.sch
@@ -0,0 +1,183 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 70 30 70 70 { lab=GND}
+N 70 -60 70 -30 { lab=vss}
+N 150 -60 150 -30 { lab=vdd}
+N 150 30 150 70 { lab=vss}
+N 760 0 850 0 { lab=out_ro_n}
+N 670 50 670 80 { lab=vss}
+N 670 80 890 80 { lab=vss}
+N 890 50 890 80 { lab=vss}
+N 1050 0 1050 50 { lab=out_ro_buf}
+N 980 0 1050 0 { lab=out_ro_buf}
+N 1050 110 1050 150 { lab=vss}
+N 240 -60 240 -30 { lab=vctrl}
+N 240 30 240 70 { lab=vss}
+N 510 80 670 80 { lab=vss}
+N 380 0 410 0 { lab=vctrl}
+N 280 -370 280 -340 { lab=D0}
+N 280 -280 280 -240 { lab=vss}
+N 580 -0 630 -0 { lab=out_ro}
+N 510 70 510 80 { lab=vss}
+N 410 -0 440 -0 { lab=vctrl}
+N 510 -100 510 -70 { lab=vdd}
+N 670 -80 670 -50 { lab=vdd}
+N 890 -80 890 -50 { lab=vdd}
+N 410 40 440 40 { lab=D0}
+C {netlist_not_shown.sym} 80 -320 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+ tran 0.01ns 50ns
+ meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+ meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+ let T = Tosc/10.0
+ let Tbuf = Toscbuf/10.0
+ let f = 1/T
+ let fbuf = 1/Tbuf
+ let Td = 1/(2*3*f)
+ print T Tbuf f fbuf Td
+ let i = i + 0.1
+ alterparam vctrl = $&i
+ reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+* let i = 0
+* let j = 0
+* while j < 2
+* while i < 2
+* tran 0.1ns 100us
+* meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+* meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+* let T = Tosc/10.0
+* let Tbuf = Toscbuf/10.0
+* let f = 1/T
+* let fbuf = 1/Tbuf
+* let Td = 1/(2*3*f)
+* print T Tbuf f fbuf Td
+* let i = i + 1
+* alterparam vctrl = 1.8
+* reset
+* end
+* alterparam vctrl = 0.7
+* alterparam vd0 = 0.0
+* alterparam vd1 = 1.8
+* alterparam vd2 = 1.8
+* alterpatam vd3 = 0.0
+* let i = 0
+* let j = j + 1
+* reset
+* end
+* plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+* plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+* plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+* plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+* print tran1.f tran2.f tran3.f tran4.f
+* let frange_vtun_0 = tran2.f - tran1.f
+* let frange_vtun_1 = tran4.f - tran3.f
+* print frange_vtun_0 frange_vtun_1
+.endc
+
+.end
+"}
+C {vsource.sym} 70 0 0 0 {name=vss value=\{vss\}}
+C {gnd.sym} 70 70 0 0 {name=l7 lab=GND}
+C {vsource.sym} 150 0 0 0 {name=vdd value=\{vdd\}}
+C {lab_pin.sym} 70 -60 1 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 150 -60 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 70 3 0 {name=l12 sig_type=std_logic lab=vss}
+C {inverter_min_x2.sym} 690 0 0 0 {name=x1}
+C {inverter_min_x4.sym} 910 0 0 0 {name=x2}
+C {capa.sym} 1050 80 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1050 150 3 0 {name=l23 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 830 0 0 0 {name=l24 sig_type=std_logic lab=out_ro_n}
+C {lab_wire.sym} 1040 0 0 0 {name=l25 sig_type=std_logic lab=out_ro_buf}
+C {lab_wire.sym} 820 80 0 0 {name=l27 sig_type=std_logic lab=vss}
+C {vsource.sym} 240 0 0 0 {name=Vctrl value="DC \{vctrl\}" }
+C {lab_pin.sym} 240 -60 1 0 {name=l49 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 240 70 3 0 {name=l50 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 380 0 0 0 {name=l1 sig_type=std_logic lab=vctrl}
+C {lab_wire.sym} 620 0 0 0 {name=l2 sig_type=std_logic lab=out_ro}
+C {vsource.sym} 280 -310 0 0 {name=VD0 value="DC \{vd0\}" }
+C {lab_pin.sym} 280 -370 1 0 {name=l3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 280 -240 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 510 -100 1 0 {name=l30 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 670 -80 1 0 {name=l26 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 890 -80 1 0 {name=l43 sig_type=std_logic lab=vdd}
+C {csvco_pex_c.sym} 510 0 0 0 {name=x3}
+C {lab_pin.sym} 410 40 0 0 {name=l5 sig_type=std_logic lab=D0}
diff --git a/xschem/tb_csvco_v2.sch b/xschem/tb_csvco_v2.sch
new file mode 100644
index 0000000..325ca90
--- /dev/null
+++ b/xschem/tb_csvco_v2.sch
@@ -0,0 +1,184 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 70 30 70 70 { lab=GND}
+N 70 -60 70 -30 { lab=vss}
+N 150 -60 150 -30 { lab=vdd}
+N 150 30 150 70 { lab=vss}
+N 760 0 850 0 { lab=out_ro_n}
+N 670 50 670 80 { lab=vss}
+N 670 80 890 80 { lab=vss}
+N 890 50 890 80 { lab=vss}
+N 1050 0 1050 50 { lab=out_ro_buf}
+N 980 0 1050 0 { lab=out_ro_buf}
+N 1050 110 1050 150 { lab=vss}
+N 240 -60 240 -30 { lab=vctrl}
+N 240 30 240 70 { lab=vss}
+N 510 80 670 80 { lab=vss}
+N 380 0 410 0 { lab=vctrl}
+N 280 -370 280 -340 { lab=D0}
+N 280 -280 280 -240 { lab=vss}
+N 580 -0 630 -0 { lab=out_ro}
+N 510 70 510 80 { lab=vss}
+N 410 -0 440 -0 { lab=vctrl}
+N 510 -100 510 -70 { lab=vdd}
+N 670 -80 670 -50 { lab=vdd}
+N 890 -80 890 -50 { lab=vdd}
+N 410 40 440 40 { lab=D0}
+C {netlist_not_shown.sym} 80 -320 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_csvco_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+ tran 0.01ns 50ns
+ meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+ meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+ let T = Tosc/10.0
+ let Tbuf = Toscbuf/10.0
+ let f = 1/T
+ let fbuf = 1/Tbuf
+ let Td = 1/(2*3*f)
+ print T Tbuf f fbuf Td
+ let i = i + 0.1
+ alterparam vctrl = $&i
+ reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+* let i = 0
+* let j = 0
+* while j < 2
+* while i < 2
+* tran 0.1ns 100us
+* meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+* meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+* let T = Tosc/10.0
+* let Tbuf = Toscbuf/10.0
+* let f = 1/T
+* let fbuf = 1/Tbuf
+* let Td = 1/(2*3*f)
+* print T Tbuf f fbuf Td
+* let i = i + 1
+* alterparam vctrl = 1.8
+* reset
+* end
+* alterparam vctrl = 0.7
+* alterparam vd0 = 0.0
+* alterparam vd1 = 1.8
+* alterparam vd2 = 1.8
+* alterpatam vd3 = 0.0
+* let i = 0
+* let j = j + 1
+* reset
+* end
+* plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+* plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+* plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+* plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+* print tran1.f tran2.f tran3.f tran4.f
+* let frange_vtun_0 = tran2.f - tran1.f
+* let frange_vtun_1 = tran4.f - tran3.f
+* print frange_vtun_0 frange_vtun_1
+.endc
+
+.end
+"}
+C {vsource.sym} 70 0 0 0 {name=vss value=\{vss\}}
+C {gnd.sym} 70 70 0 0 {name=l7 lab=GND}
+C {vsource.sym} 150 0 0 0 {name=vdd value=\{vdd\}}
+C {lab_pin.sym} 70 -60 1 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 150 -60 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 70 3 0 {name=l12 sig_type=std_logic lab=vss}
+C {inverter_min_x2.sym} 690 0 0 0 {name=x1}
+C {inverter_min_x4.sym} 910 0 0 0 {name=x2}
+C {capa.sym} 1050 80 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1050 150 3 0 {name=l23 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 830 0 0 0 {name=l24 sig_type=std_logic lab=out_ro_n}
+C {lab_wire.sym} 1040 0 0 0 {name=l25 sig_type=std_logic lab=out_ro_buf}
+C {lab_wire.sym} 820 80 0 0 {name=l27 sig_type=std_logic lab=vss}
+C {vsource.sym} 240 0 0 0 {name=Vctrl value="DC \{vctrl\}" }
+C {lab_pin.sym} 240 -60 1 0 {name=l49 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 240 70 3 0 {name=l50 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 380 0 0 0 {name=l1 sig_type=std_logic lab=vctrl}
+C {lab_wire.sym} 620 0 0 0 {name=l2 sig_type=std_logic lab=out_ro}
+C {vsource.sym} 280 -310 0 0 {name=VD0 value="DC \{vd0\}" }
+C {lab_pin.sym} 280 -370 1 0 {name=l3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 280 -240 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 510 -100 1 0 {name=l30 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 670 -80 1 0 {name=l26 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 890 -80 1 0 {name=l43 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 40 0 0 {name=l11 sig_type=std_logic lab=D0}
+C {csvco_v2.sym} 510 0 0 0 {name=x3}
diff --git a/xschem/tb_csvco_v2_pex_c.sch b/xschem/tb_csvco_v2_pex_c.sch
new file mode 100644
index 0000000..3611bd2
--- /dev/null
+++ b/xschem/tb_csvco_v2_pex_c.sch
@@ -0,0 +1,184 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 70 30 70 70 { lab=GND}
+N 70 -60 70 -30 { lab=vss}
+N 150 -60 150 -30 { lab=vdd}
+N 150 30 150 70 { lab=vss}
+N 760 0 850 0 { lab=out_ro_n}
+N 670 50 670 80 { lab=vss}
+N 670 80 890 80 { lab=vss}
+N 890 50 890 80 { lab=vss}
+N 1050 0 1050 50 { lab=out_ro_buf}
+N 980 0 1050 0 { lab=out_ro_buf}
+N 1050 110 1050 150 { lab=vss}
+N 240 -60 240 -30 { lab=vctrl}
+N 240 30 240 70 { lab=vss}
+N 510 80 670 80 { lab=vss}
+N 380 0 410 0 { lab=vctrl}
+N 280 -370 280 -340 { lab=D0}
+N 280 -280 280 -240 { lab=vss}
+N 580 -0 630 -0 { lab=out_ro}
+N 510 70 510 80 { lab=vss}
+N 410 -0 440 -0 { lab=vctrl}
+N 510 -100 510 -70 { lab=vdd}
+N 670 -80 670 -50 { lab=vdd}
+N 890 -80 890 -50 { lab=vdd}
+N 410 40 440 40 { lab=D0}
+C {netlist_not_shown.sym} 80 -320 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+.options TEMP = 0.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_v2_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+ tran 0.01ns 200ns
+ meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+ meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+ let T = Tosc/10.0
+ let Tbuf = Toscbuf/10.0
+ let f = 1/T
+ let fbuf = 1/Tbuf
+ let Td = 1/(2*3*f)
+ print T Tbuf f fbuf Td
+ let i = i + 0.1
+ alterparam vctrl = $&i
+ reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+* let i = 0
+* let j = 0
+* while j < 2
+* while i < 2
+* tran 0.1ns 100us
+* meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+* meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+* let T = Tosc/10.0
+* let Tbuf = Toscbuf/10.0
+* let f = 1/T
+* let fbuf = 1/Tbuf
+* let Td = 1/(2*3*f)
+* print T Tbuf f fbuf Td
+* let i = i + 1
+* alterparam vctrl = 1.8
+* reset
+* end
+* alterparam vctrl = 0.7
+* alterparam vd0 = 0.0
+* alterparam vd1 = 1.8
+* alterparam vd2 = 1.8
+* alterpatam vd3 = 0.0
+* let i = 0
+* let j = j + 1
+* reset
+* end
+* plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+* plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+* plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+* plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+* print tran1.f tran2.f tran3.f tran4.f
+* let frange_vtun_0 = tran2.f - tran1.f
+* let frange_vtun_1 = tran4.f - tran3.f
+* print frange_vtun_0 frange_vtun_1
+.endc
+
+.end
+"}
+C {vsource.sym} 70 0 0 0 {name=vss value=\{vss\}}
+C {gnd.sym} 70 70 0 0 {name=l7 lab=GND}
+C {vsource.sym} 150 0 0 0 {name=vdd value=\{vdd\}}
+C {lab_pin.sym} 70 -60 1 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 150 -60 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 70 3 0 {name=l12 sig_type=std_logic lab=vss}
+C {inverter_min_x2.sym} 690 0 0 0 {name=x1}
+C {inverter_min_x4.sym} 910 0 0 0 {name=x2}
+C {capa.sym} 1050 80 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1050 150 3 0 {name=l23 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 830 0 0 0 {name=l24 sig_type=std_logic lab=out_ro_n}
+C {lab_wire.sym} 1040 0 0 0 {name=l25 sig_type=std_logic lab=out_ro_buf}
+C {lab_wire.sym} 820 80 0 0 {name=l27 sig_type=std_logic lab=vss}
+C {vsource.sym} 240 0 0 0 {name=Vctrl value="DC \{vctrl\}" }
+C {lab_pin.sym} 240 -60 1 0 {name=l49 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 240 70 3 0 {name=l50 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 380 0 0 0 {name=l1 sig_type=std_logic lab=vctrl}
+C {lab_wire.sym} 620 0 0 0 {name=l2 sig_type=std_logic lab=out_ro}
+C {vsource.sym} 280 -310 0 0 {name=VD0 value="DC \{vd0\}" }
+C {lab_pin.sym} 280 -370 1 0 {name=l3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 280 -240 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 510 -100 1 0 {name=l30 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 670 -80 1 0 {name=l26 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 890 -80 1 0 {name=l43 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 40 0 0 {name=l5 sig_type=std_logic lab=D0}
+C {csvco_v2_pex_c.sym} 510 0 0 0 {name=x3}
diff --git a/xschem/tb_div_by_2.sch b/xschem/tb_div_by_2.sch
new file mode 100644
index 0000000..2c5d47a
--- /dev/null
+++ b/xschem/tb_div_by_2.sch
@@ -0,0 +1,116 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -100 -520 -100 -490 { lab=GND}
+N -230 -230 -230 -200 { lab=vss}
+N -30 -520 -30 -490 { lab=vss}
+N -100 -610 -100 -580 { lab=vss}
+N -230 -320 -230 -290 { lab=#net1}
+N -30 -610 -30 -580 { lab=vdd}
+N 450 -320 480 -320 { lab=A}
+N 100 -270 100 -240 { lab=vss}
+N 100 -400 100 -370 { lab=vdd}
+N 620 -340 720 -340 { lab=out}
+N 620 -300 660 -300 { lab=nout}
+N 190 -320 270 -320 { lab=#net2}
+N 310 -270 310 -240 { lab=vss}
+N 310 -400 310 -370 { lab=vdd}
+N -230 -320 60 -320 { lab=#net1}
+N 400 -320 450 -320 { lab=A}
+N 570 -430 570 -400 { lab=vss}
+N 530 -430 530 -400 { lab=vdd}
+N 660 -300 720 -300 { lab=nout}
+N 520 -240 520 -190 { lab=out_div}
+N 540 -240 540 -190 { lab=#net3}
+N 560 -240 560 -190 { lab=#net4}
+N 580 -240 580 -190 { lab=#net5}
+N 720 -300 720 -280 { lab=nout}
+N 800 -340 800 -280 { lab=out}
+N 720 -340 800 -340 { lab=out}
+N 720 -220 720 -190 { lab=vss}
+N 800 -220 800 -190 { lab=vss}
+C {vsource.sym} -100 -550 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -30 -550 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -230 -260 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -100 -490 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -100 -610 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -490 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -230 -200 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -610 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 440 -320 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 80 -600 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 200ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ write tb_div_by_2_tran.raw
+ plot v(out) v(A) v(nout)+2 v(A)+2
+ plot v(out_div) v(out)
+.endc
+
+.end
+"}
+C {lab_pin.sym} 100 -240 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 100 -400 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {div_by_2.sym} 550 -320 0 0 {name=x1}
+C {inverter_min_x2_pex_c.sym} 120 -320 0 0 {name=x2}
+C {inverter_min_x4_pex_c.sym} 330 -320 0 0 {name=x3}
+C {lab_pin.sym} 310 -240 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 310 -400 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 570 -430 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 530 -430 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {noconn.sym} 520 -190 1 1 {name=l20}
+C {noconn.sym} 540 -190 1 1 {name=l21}
+C {noconn.sym} 560 -190 1 1 {name=l22}
+C {noconn.sym} 580 -190 1 1 {name=l23}
+C {lab_pin.sym} 680 -340 3 1 {name=l24 sig_type=std_logic lab=out}
+C {lab_pin.sym} 690 -300 1 1 {name=l25 sig_type=std_logic lab=nout}
+C {lab_pin.sym} 520 -210 2 1 {name=l26 sig_type=std_logic lab=out_div}
+C {capa.sym} 720 -250 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {capa.sym} 800 -250 0 0 {name=C2
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 720 -190 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 800 -190 3 0 {name=l8 sig_type=std_logic lab=vss}
diff --git a/xschem/tb_div_by_2_pex_c.sch b/xschem/tb_div_by_2_pex_c.sch
new file mode 100644
index 0000000..975c397
--- /dev/null
+++ b/xschem/tb_div_by_2_pex_c.sch
@@ -0,0 +1,135 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -100 -520 -100 -490 { lab=GND}
+N -30 -520 -30 -490 { lab=vss}
+N -100 -610 -100 -580 { lab=vss}
+N -30 -610 -30 -580 { lab=vdd}
+N 270 -300 300 -300 { lab=A}
+N 390 -410 390 -380 { lab=vss}
+N 350 -410 350 -380 { lab=vdd}
+N 440 -280 480 -280 { lab=nout}
+N 680 -300 730 -300 { lab=#net1}
+N 630 -410 630 -380 { lab=vss}
+N 590 -410 590 -380 { lab=vdd}
+N -440 -210 -440 -180 { lab=vss}
+N -440 -300 -440 -270 { lab=#net2}
+N 240 -300 270 -300 { lab=A}
+N -110 -250 -110 -220 { lab=vss}
+N -110 -380 -110 -350 { lab=vdd}
+N -20 -300 60 -300 { lab=#net3}
+N 100 -250 100 -220 { lab=vss}
+N 100 -380 100 -350 { lab=vdd}
+N -440 -300 -150 -300 { lab=#net2}
+N 190 -300 240 -300 { lab=A}
+N 440 -320 530 -320 { lab=out}
+N 480 -280 530 -280 { lab=nout}
+N 570 -220 570 -170 { lab=#net4}
+N 590 -220 590 -170 { lab=#net5}
+N 610 -220 610 -170 { lab=#net6}
+N 630 -220 630 -170 { lab=#net7}
+N 650 -220 650 -170 { lab=#net8}
+N 340 -220 340 -170 { lab=#net9}
+N 360 -220 360 -170 { lab=#net10}
+N 380 -220 380 -170 { lab=#net11}
+N 400 -220 400 -170 { lab=#net12}
+C {vsource.sym} -100 -550 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -30 -550 0 0 {name=VDD value=\{vdd\}}
+C {gnd.sym} -100 -490 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -100 -610 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -490 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -610 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {netlist_not_shown.sym} 80 -600 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(x2.q0) = 0.0
+.ic v(x2.nq0) = 0.0
+.ic v(x2.q1) = 0.0
+.ic v(x2.nq1) = 0.0
+.ic v(x2.q1_shift) = 0.0
+.ic v(x2.nq1_shift) = 0.0
+.ic v(x2.q2) = 0.0
+.ic v(x2.nq2) = 0.0
+.ic v(x2.x1.a) = 0.0
+.ic v(x2.x1.na) = 0.0
+.ic v(x2.x1.D_d) = 0.0
+.ic v(x2.x1.nD_d) = 0.0
+.ic v(out) = 0.0
+.ic v(nout) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 200ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ write tb_div_by_2_tran.raw
+ plot v(out) v(A) v(nout)+2 v(A)+2
+.endc
+
+.end
+"}
+C {lab_pin.sym} 390 -410 1 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -410 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 450 -320 0 1 {name=l15 sig_type=std_logic lab=out}
+C {lab_wire.sym} 450 -280 0 1 {name=l8 sig_type=std_logic lab=nout}
+C {div_by_2_pex_c.sym} 370 -300 0 0 {name=x1}
+C {netlist_not_shown.sym} 290 -590 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {lab_pin.sym} 630 -410 1 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 590 -410 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {noconn.sym} 730 -300 2 0 {name=l12}
+C {vsource.sym} -440 -240 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} -440 -180 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 230 -300 3 1 {name=l14 sig_type=std_logic lab=A}
+C {lab_pin.sym} -110 -220 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -110 -380 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {inverter_min_x2_pex_c.sym} -90 -300 0 0 {name=x3}
+C {inverter_min_x4_pex_c.sym} 120 -300 0 0 {name=x4}
+C {lab_pin.sym} 100 -220 3 0 {name=l17 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 100 -380 1 0 {name=l18 sig_type=std_logic lab=vdd}
+C {noconn.sym} 570 -170 3 0 {name=l7}
+C {noconn.sym} 590 -170 3 0 {name=l19}
+C {noconn.sym} 610 -170 3 0 {name=l20}
+C {noconn.sym} 630 -170 3 0 {name=l21}
+C {noconn.sym} 650 -170 3 0 {name=l22}
+C {noconn.sym} 340 -170 3 0 {name=l23}
+C {noconn.sym} 360 -170 3 0 {name=l24}
+C {noconn.sym} 380 -170 3 0 {name=l25}
+C {noconn.sym} 400 -170 3 0 {name=l26}
+C {div_by_5_pex_c.sym} 610 -300 0 0 {name=x2}
diff --git a/xschem/tb_div_by_5.sch b/xschem/tb_div_by_5.sch
new file mode 100644
index 0000000..c95644c
--- /dev/null
+++ b/xschem/tb_div_by_5.sch
@@ -0,0 +1,115 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -290 -350 -290 -320 { lab=GND}
+N -260 -120 -260 -90 { lab=vss}
+N -220 -350 -220 -320 { lab=vss}
+N -290 -440 -290 -410 { lab=vss}
+N -260 -210 -260 -180 { lab=CLK}
+N -220 -440 -220 -410 { lab=vdd}
+N 100 -240 130 -240 { lab=CLK}
+N 390 -350 390 -320 { lab=vdd}
+N 520 -170 520 -140 { lab=vss}
+N 180 -350 180 -320 { lab=vdd}
+N 220 -350 220 -320 { lab=vss}
+N 270 -260 330 -260 { lab=clk_2}
+N 520 -240 520 -230 { lab=clk_10}
+N 480 -240 520 -240 { lab=clk_10}
+N 430 -350 430 -320 { lab=vss}
+N 270 -220 330 -220 { lab=nclk_2}
+C {vsource.sym} -290 -380 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -220 -380 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -260 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -290 -320 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -290 -440 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -220 -320 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -260 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -220 -440 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -260 -210 3 1 {name=l14 sig_type=std_logic lab=CLK}
+C {netlist_not_shown.sym} -120 -540 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+
+.ic v(CLK) = 0.0
+.ic v(x1.q2) = 0.0
+.ic v(x1.q1) = 0.0
+.ic v(x1.q1_shift) = 0.0
+.ic v(x1.q0) = 0.0
+.ic v(x1.x1.a) = 0.0
+.ic v(x1.x1.D_d) = 0.0
+.ic v(x1.x1.nD_d) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 600ns
+ *meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+ *meas tran Td1 trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+ *meas tran Td2 trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+ *meas tran Td3 trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ *let T = Tosc/10.0
+ *let f = 1/T
+ *let Td = 1/(2*3*f)
+ *print T f Td
+ write tb_div_by_5_tran.raw
+ plot v(clk_10) v(clk) v(clk_2) v(clk_2)+3 v(clk)+6
+ plot v(x1.Q2) v(x1.Q1)+2 v(clk_Q0)+4 v(x1.Q1_shift)+6 v(clk_10)+8
+
+.endc
+
+.end
+"}
+C {lab_pin.sym} 100 -240 2 1 {name=l7 sig_type=std_logic lab=CLK}
+C {lab_pin.sym} 390 -350 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {capa.sym} 520 -200 0 0 {name=C2
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 520 -140 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 520 -240 0 1 {name=l15 sig_type=std_logic lab=clk_10}
+C {lab_pin.sym} 180 -350 1 0 {name=l21 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 220 -350 1 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 430 -350 1 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 280 -260 0 1 {name=l5 sig_type=std_logic lab=clk_2}
+C {lab_wire.sym} 280 -220 0 1 {name=l12 sig_type=std_logic lab=nclk_2}
+C {launcher.sym} 330 -490 0 0 {name=h2
+descr="sky130_models.tcl"
+tclcommand="eval exec $editor scripts/sky130_models.tcl"
+}
+C {netlist_not_shown.sym} -120 -360 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {div_by_2.sym} 200 -240 0 0 {name=x2}
+C {div_by_5.sym} 410 -240 0 0 {name=x1}
+C {noconn.sym} 370 -160 3 0 {name=l8}
+C {noconn.sym} 390 -160 3 0 {name=l9}
+C {noconn.sym} 410 -160 3 0 {name=l16}
+C {noconn.sym} 430 -160 3 0 {name=l17}
+C {noconn.sym} 450 -160 3 0 {name=l18}
+C {noconn.sym} 170 -160 3 0 {name=l19}
+C {noconn.sym} 190 -160 3 0 {name=l20}
+C {noconn.sym} 210 -160 3 0 {name=l23}
+C {noconn.sym} 230 -160 3 0 {name=l24}
diff --git a/xschem/tb_div_by_5_pex_c.sch b/xschem/tb_div_by_5_pex_c.sch
new file mode 100644
index 0000000..a408506
--- /dev/null
+++ b/xschem/tb_div_by_5_pex_c.sch
@@ -0,0 +1,172 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -100 -520 -100 -490 { lab=GND}
+N -30 -520 -30 -490 { lab=vss}
+N -100 -610 -100 -580 { lab=vss}
+N -30 -610 -30 -580 { lab=vdd}
+N 270 -300 300 -300 { lab=A}
+N 390 -410 390 -380 { lab=vss}
+N 350 -410 350 -380 { lab=vdd}
+N 440 -280 480 -280 { lab=nclk_2}
+N 1130 -420 1130 -390 { lab=vss}
+N 1090 -420 1090 -390 { lab=vdd}
+N -440 -210 -440 -180 { lab=vss}
+N -440 -300 -440 -270 { lab=#net1}
+N 240 -300 270 -300 { lab=A}
+N -110 -250 -110 -220 { lab=vss}
+N -110 -380 -110 -350 { lab=vdd}
+N -20 -300 60 -300 { lab=#net2}
+N 100 -250 100 -220 { lab=vss}
+N 100 -380 100 -350 { lab=vdd}
+N -440 -300 -150 -300 { lab=#net1}
+N 190 -300 240 -300 { lab=A}
+N 440 -320 530 -320 { lab=clk_2}
+N 480 -280 530 -280 { lab=nclk_2}
+N 1070 -230 1070 -180 { lab=#net3}
+N 1090 -230 1090 -180 { lab=#net4}
+N 1110 -230 1110 -180 { lab=#net5}
+N 1130 -230 1130 -180 { lab=#net6}
+N 1150 -230 1150 -180 { lab=#net7}
+N 1190 -310 1230 -310 { lab=clk_5}
+N 1320 -480 1320 -450 { lab=vss}
+N 1280 -480 1280 -450 { lab=vdd}
+N 1300 -250 1300 -200 { lab=#net8}
+N 1370 -310 1420 -310 { lab=#net9}
+N 1370 -390 1420 -390 { lab=#net10}
+N 1180 -390 1230 -390 { lab=#net11}
+N 570 -380 570 -350 { lab=vss}
+N 570 -510 570 -480 { lab=vdd}
+N 660 -430 740 -430 { lab=#net12}
+N 780 -380 780 -350 { lab=vss}
+N 780 -510 780 -480 { lab=vdd}
+N 870 -430 920 -430 { lab=clk_2_buf}
+N 570 -120 570 -90 { lab=vss}
+N 570 -250 570 -220 { lab=vdd}
+N 660 -170 740 -170 { lab=#net13}
+N 780 -120 780 -90 { lab=vss}
+N 780 -250 780 -220 { lab=vdd}
+N 870 -170 920 -170 { lab=nclk_2_buf}
+N 530 -280 530 -170 { lab=nclk_2}
+N 530 -430 530 -320 { lab=clk_2}
+N 930 -330 1030 -330 { lab=clk_2_buf}
+N 930 -430 930 -330 { lab=clk_2_buf}
+N 920 -430 930 -430 { lab=clk_2_buf}
+N 930 -290 1030 -290 { lab=nclk_2_buf}
+N 930 -290 930 -170 { lab=nclk_2_buf}
+N 920 -170 930 -170 { lab=nclk_2_buf}
+N 340 -220 340 -170 { lab=#net14}
+N 360 -220 360 -170 { lab=#net15}
+N 380 -220 380 -170 { lab=#net16}
+N 400 -220 400 -170 { lab=#net17}
+C {vsource.sym} -100 -550 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -30 -550 0 0 {name=VDD value=\{vdd\}}
+C {gnd.sym} -100 -490 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -100 -610 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -490 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -610 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {netlist_not_shown.sym} 80 -600 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(x2.q0) = 0.0
+.ic v(x2.nq0) = 0.0
+.ic v(x2.q1) = 0.0
+.ic v(x2.nq1) = 0.0
+.ic v(x2.q1_shift) = 0.0
+.ic v(x2.nq1_shift) = 0.0
+.ic v(x2.q2) = 0.0
+.ic v(x2.nq2) = 0.0
+.ic v(x2.x1.a) = 0.0
+.ic v(x2.x1.na) = 0.0
+.ic v(x2.x1.D_d) = 0.0
+.ic v(x2.x1.nD_d) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(clk_5)
+
+* Simulation
+.control
+ tran 0.01ns 200ns
+ write tb_div_by_5_tran.raw
+ plot v(clk_2) v(A) v(nclk_2)+2 v(A)+2
+ plot v(clk_5) v(clk_2_buf) v(A)
+.endc
+
+.end
+"}
+C {lab_pin.sym} 390 -410 1 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -410 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 450 -320 0 1 {name=l15 sig_type=std_logic lab=clk_2}
+C {lab_wire.sym} 450 -280 0 1 {name=l8 sig_type=std_logic lab=nclk_2}
+C {div_by_2_pex_c.sym} 370 -300 0 0 {name=x1}
+C {lab_pin.sym} 1130 -420 1 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1090 -420 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {vsource.sym} -440 -240 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} -440 -180 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 230 -300 3 1 {name=l14 sig_type=std_logic lab=A}
+C {lab_pin.sym} -110 -220 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -110 -380 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {inverter_min_x2_pex_c.sym} -90 -300 0 0 {name=x3}
+C {inverter_min_x4_pex_c.sym} 120 -300 0 0 {name=x4}
+C {lab_pin.sym} 100 -220 3 0 {name=l17 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 100 -380 1 0 {name=l18 sig_type=std_logic lab=vdd}
+C {noconn.sym} 1070 -180 3 0 {name=l7}
+C {noconn.sym} 1090 -180 3 0 {name=l19}
+C {noconn.sym} 1110 -180 3 0 {name=l20}
+C {noconn.sym} 1130 -180 3 0 {name=l21}
+C {noconn.sym} 1150 -180 3 0 {name=l22}
+C {PFD_pex_c.sym} 1300 -350 0 0 {name=x5}
+C {lab_pin.sym} 1320 -480 1 0 {name=l12 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1280 -480 1 0 {name=l23 sig_type=std_logic lab=vdd}
+C {noconn.sym} 1300 -200 3 0 {name=l24}
+C {noconn.sym} 1420 -310 2 0 {name=l25}
+C {noconn.sym} 1420 -390 2 0 {name=l26}
+C {noconn.sym} 1180 -390 0 0 {name=l27}
+C {lab_wire.sym} 1200 -310 0 1 {name=l28 sig_type=std_logic lab=clk_5}
+C {div_by_5_pex_c.sym} 1110 -310 0 0 {name=x2}
+C {lab_pin.sym} 570 -350 3 0 {name=l30 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 570 -510 1 0 {name=l31 sig_type=std_logic lab=vdd}
+C {inverter_min_x2_pex_c.sym} 590 -430 0 0 {name=x6}
+C {inverter_min_x4_pex_c.sym} 800 -430 0 0 {name=x7}
+C {lab_pin.sym} 780 -350 3 0 {name=l32 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 780 -510 1 0 {name=l33 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 570 -90 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 570 -250 1 0 {name=l36 sig_type=std_logic lab=vdd}
+C {inverter_min_x2_pex_c.sym} 590 -170 0 0 {name=x8}
+C {inverter_min_x4_pex_c.sym} 800 -170 0 0 {name=x9}
+C {lab_pin.sym} 780 -90 3 0 {name=l37 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 780 -250 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 960 -330 0 1 {name=l29 sig_type=std_logic lab=clk_2_buf}
+C {lab_wire.sym} 960 -290 0 1 {name=l34 sig_type=std_logic lab=nclk_2_buf}
+C {noconn.sym} 340 -170 3 0 {name=l39}
+C {noconn.sym} 360 -170 3 0 {name=l40}
+C {noconn.sym} 380 -170 3 0 {name=l41}
+C {noconn.sym} 400 -170 3 0 {name=l42}
diff --git a/xschem/tb_inverter_csvco.sch b/xschem/tb_inverter_csvco.sch
new file mode 100644
index 0000000..6761b76
--- /dev/null
+++ b/xschem/tb_inverter_csvco.sch
@@ -0,0 +1,152 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 150 -450 150 -420 { lab=vss}
+N 150 -580 150 -550 { lab=vdd}
+N 240 -500 320 -500 { lab=out}
+N 50 -500 110 -500 { lab=in}
+N 150 -420 150 -400 { lab=vss}
+N 150 -600 150 -580 { lab=vdd}
+N 320 -790 320 -740 { lab=GND}
+N 500 -790 500 -740 { lab=vss}
+N 410 -790 410 -740 { lab=vss}
+N 320 -900 320 -850 { lab=vss}
+N 500 -900 500 -850 { lab=in}
+N 410 -900 410 -850 { lab=vdd}
+N 320 -500 320 -480 { lab=out}
+N 320 -420 320 -400 { lab=vss}
+N 190 -560 190 -530 { lab=vdd}
+N 190 -580 190 -560 { lab=vdd}
+N 190 -470 190 -440 { lab=vss}
+N 190 -440 190 -420 { lab=vss}
+N 570 -450 570 -420 { lab=vss}
+N 570 -580 570 -550 { lab=vdd}
+N 660 -500 740 -500 { lab=out_pex_c}
+N 470 -500 530 -500 { lab=in}
+N 570 -420 570 -400 { lab=vss}
+N 570 -600 570 -580 { lab=vdd}
+N 740 -500 740 -480 { lab=out_pex_c}
+N 740 -420 740 -400 { lab=vss}
+N 610 -560 610 -530 { lab=vdd}
+N 610 -580 610 -560 { lab=vdd}
+N 610 -470 610 -440 { lab=vss}
+N 610 -440 610 -420 { lab=vss}
+C {lab_pin.sym} 150 -600 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 -400 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 290 -500 0 0 {name=l3 sig_type=std_logic lab=out}
+C {vsource.sym} 320 -820 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} 410 -820 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} 500 -820 0 0 {name=VIN value="PULSE(0 \{vin\} 0 1p 1p \{T/2\} \{T\}) DC \{vin\} AC 0"}
+C {gnd.sym} 320 -740 0 0 {name=l9 lab=GND}
+C {lab_pin.sym} 410 -740 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 500 -740 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 410 -900 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 500 -900 1 0 {name=l13 sig_type=std_logic lab=in}
+C {lab_pin.sym} 320 -900 1 0 {name=l14 sig_type=std_logic lab=vss}
+C {netlist_not_shown.sym} 130 -860 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0
+.param vin = vdd
+.param T = 100n
+
+.options TEMP = 50.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/sky130-mpw2-fulgor/inverter_csvco/sch/simulations/inverter_csvco_pex_c.spice
+
+* Initial Conditions
+.ic v(out) = 0.0
+.ic v(out_wp) = 0.0
+.ic v(out_wp_rc) = 0.0
+.ic v(out_pex_c) = 0.0
+
+* Data to save
+.save all
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[id]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgs]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgs]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgd]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgd]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[csb]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[csb]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[cdb]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[cdb]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgg]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgg]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgb]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgb]
+
+* Simulation
+.control
+ set filetype = ascii
+ op
+ write tb_inverter_min.raw
+ echo .
+ echo ------ OP Results -----
+ print all
+
+ reset
+
+ dc vin 0 1.8 0.01
+ setplot dc1
+ plot v(in) v(out) v(out_pex_c)
+ write tb_inverter_min_dc.raw
+
+ reset
+
+ tran 1ns 1us
+ meas tran tpLH trig v(in) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+ meas tran tpHL trig v(in) val=0.9 rise=5 targ v(out) val=0.9 fall=4
+ meas tran tpLHc trig v(in) val=0.9 fall=5 targ v(out_pex_c) val=0.9 rise=5
+ meas tran tpHLc trig v(in) val=0.9 rise=5 targ v(out_pex_c) val=0.9 fall=4
+ let tp = (0.5*(tpLH + tpHL))
+ let tp_c = (0.5*(tpLHc + tpHLc))
+ echo .
+ echo ---- tp Ideal ----
+ print tpLH tpHL tp
+ echo .
+ echo ---- tp PEX C ----
+ print tpLHc tpHLc tp_c
+ write tb_inverter_tran.raw
+ plot v(in) v(out) v(out_pex_c)+2
+
+.endc
+
+.end
+"}
+C {capa.sym} 320 -450 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 320 -400 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 50 -500 0 0 {name=l5 sig_type=std_logic lab=in}
+C {inverter_csvco.sym} 170 -500 0 0 {name=x1}
+C {lab_pin.sym} 190 -580 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 190 -420 3 0 {name=l28 sig_type=std_logic lab=vss}
+C {inverter_csvco/sch/inverter_csvco_pex_c.sym} 590 -500 0 0 {name=x2}
+C {lab_pin.sym} 570 -600 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 570 -400 3 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 710 -500 0 0 {name=l8 sig_type=std_logic lab=out_pex_c}
+C {capa.sym} 740 -450 0 0 {name=C2
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 740 -400 3 0 {name=l15 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 470 -500 0 0 {name=l16 sig_type=std_logic lab=in}
+C {lab_pin.sym} 610 -580 1 0 {name=l17 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 610 -420 3 0 {name=l18 sig_type=std_logic lab=vss}
diff --git a/xschem/tb_loop_filter.sch b/xschem/tb_loop_filter.sch
new file mode 100644
index 0000000..db158dc
--- /dev/null
+++ b/xschem/tb_loop_filter.sch
@@ -0,0 +1,76 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -180 -90 -180 -60 { lab=GND}
+N -180 -180 -180 -150 { lab=vss}
+N -90 -90 -90 -60 { lab=vss}
+N -90 -180 -90 -150 { lab=vdd}
+N 130 80 130 110 { lab=vss}
+N 130 -80 130 -60 { lab=A}
+N 20 -110 20 -80 { lab=vss}
+N 20 -200 20 -170 { lab=A}
+N 190 10 240 10 { lab=vc}
+N 390 80 390 110 { lab=vss}
+N 390 -80 390 -60 { lab=A}
+N 450 10 500 10 { lab=vc_pex}
+C {vsource.sym} -180 -120 0 0 {name=VSS value=\{vss\}}
+C {gnd.sym} -180 -60 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -180 -180 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {netlist_not_shown.sym} 390 -220 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 5e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param R1 = 1.6k
+.param C1 = 33.5p
+.param C2 = 6.7p
+
+.options TEMP = 50.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/caravel_analog_fulgor/xschem/simulations/loop_filter_pex_c.spice
+
+* Data to save
+
+
+* Simulation
+.control
+
+ tran 0.01ns 200ns
+ meas tran t1 when v(vc)=0.63
+ meas tran t2 when v(vc_pex)=0.63
+ let R = t1/0.5p
+ let Rpex = t2/05.p
+ print R Rpex
+ plot v(vc) v(vc_pex)
+.endc
+.end
+"}
+C {vsource.sym} -90 -120 0 0 {name=vdd value=\{vdd\}}
+C {lab_pin.sym} -90 -180 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -90 -60 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 130 110 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {vsource.sym} 20 -140 0 0 {name=Vref value="PULSE(0 1.0 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} 20 -80 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 20 -200 3 1 {name=l14 sig_type=std_logic lab=A}
+C {lab_pin.sym} 130 -80 3 1 {name=l6 sig_type=std_logic lab=A}
+C {loop_filter.sym} 130 10 0 0 {name=x1}
+C {noconn.sym} 240 10 2 0 {name=l83}
+C {lab_pin.sym} 390 110 3 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 390 -80 3 1 {name=l8 sig_type=std_logic lab=A}
+C {noconn.sym} 500 10 2 0 {name=l9}
+C {lab_pin.sym} 220 10 1 0 {name=l11 sig_type=std_logic lab=vc}
+C {lab_pin.sym} 480 10 1 0 {name=l12 sig_type=std_logic lab=vc_pex}
+C {loop_filter_pex_c.sym} 390 10 0 0 {name=x2}
diff --git a/xschem/tb_top_pll_v1.sch b/xschem/tb_top_pll_v1.sch
new file mode 100644
index 0000000..188f759
--- /dev/null
+++ b/xschem/tb_top_pll_v1.sch
@@ -0,0 +1,250 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -620 -120 -620 -90 { lab=GND}
+N -470 -120 -470 -90 { lab=vss}
+N -550 -120 -550 -90 { lab=vss}
+N -620 -210 -620 -180 { lab=vss}
+N -470 -210 -470 -180 { lab=A}
+N -550 -210 -550 -180 { lab=vdd}
+N -100 -110 -100 -80 { lab=vss}
+N -100 -200 -100 -170 { lab=D0}
+N -590 50 -590 80 { lab=vdd}
+N -610 440 -610 470 { lab=vss}
+N -530 120 -490 120 { lab=iref_cp}
+N -610 350 -610 380 { lab=#net1}
+N -610 340 -610 350 { lab=#net1}
+N -570 340 -570 370 { lab=vss}
+N -530 140 -490 140 { lab=#net2}
+N -530 160 -490 160 { lab=#net3}
+N -530 180 -490 180 { lab=#net4}
+N -530 200 -490 200 { lab=#net5}
+N -530 220 -490 220 { lab=#net6}
+N -530 240 -490 240 { lab=#net7}
+N -530 260 -490 260 { lab=#net8}
+N -530 280 -490 280 { lab=#net9}
+N -530 300 -490 300 { lab=#net10}
+N 180 90 180 120 { lab=vdd}
+N 240 90 240 120 { lab=vss}
+N -280 80 -280 120 { lab=iref_cp}
+N -200 90 -200 120 { lab=D0}
+N -370 250 -340 250 { lab=A}
+N 420 250 460 250 { lab=out_to_pad}
+N 460 250 510 250 { lab=out_to_pad}
+N 280 380 280 430 { lab=div_5_nQ2}
+N 260 380 260 430 { lab=div_5_Q1_shift}
+N 240 380 240 430 { lab=div_5_Q1}
+N 220 380 220 430 { lab=div_5_nQ0}
+N 200 380 200 430 { lab=div_5_Q0}
+N 130 380 130 430 { lab=n_out_buffer_div_2}
+N 110 380 110 430 { lab=out_buffer_div_2}
+N 90 380 90 430 { lab=n_out_div_2}
+N 70 380 70 430 { lab=out_div_2}
+N -120 430 -120 480 { lab=nswitch}
+N -100 430 -100 480 { lab=pswitch}
+N -80 430 -80 480 { lab=biasp}
+N -80 380 -80 430 { lab=biasp}
+N -100 380 -100 430 { lab=pswitch}
+N -120 380 -120 430 { lab=nswitch}
+N -280 430 -280 480 { lab=pfd_reset}
+N -280 380 -280 430 { lab=pfd_reset}
+N -260 430 -260 480 { lab=QA}
+N -260 380 -260 430 { lab=QA}
+N -240 430 -240 480 { lab=QB}
+N -240 380 -240 430 { lab=QB}
+N -210 430 -210 480 { lab=Up}
+N -210 380 -210 430 { lab=Up}
+N -190 430 -190 480 { lab=nUp}
+N -190 380 -190 430 { lab=nUp}
+N -170 430 -170 480 { lab=Down}
+N -170 380 -170 430 { lab=Down}
+N -150 430 -150 480 { lab=nDown}
+N -150 380 -150 430 { lab=nDown}
+N -50 380 -50 430 { lab=lf_vc}
+N -20 430 -20 480 { lab=vctrl}
+N -20 380 -20 430 { lab=vctrl}
+N 0 430 0 480 { lab=vco_out}
+N 0 380 0 430 { lab=vco_out}
+N 20 430 20 480 { lab=vco_buffer_out}
+N 20 380 20 430 { lab=vco_buffer_out}
+N 40 430 40 480 { lab=out_to_div}
+N 40 380 40 430 { lab=out_to_div}
+N 150 430 150 480 { lab=out_by_2}
+N 150 380 150 430 { lab=out_by_2}
+N 170 430 170 480 { lab=n_out_by_2}
+N 170 380 170 430 { lab=n_out_by_2}
+N 300 430 300 480 { lab=out_by_5}
+N 300 380 300 430 { lab=out_by_5}
+N 510 250 510 280 { lab=out_to_pad}
+N 510 340 510 370 { lab=vss}
+N 350 380 350 430 { lab=out_to_buffer}
+C {vsource.sym} -620 -150 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -550 -150 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -470 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -620 -90 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -620 -210 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -90 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -470 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -210 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -470 -210 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 60 -170 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+ let T = Tosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14 v(out_by_5)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+ plot v(out_by_5) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+.end
+"}
+C {vsource.sym} -100 -140 0 0 {name=VD0 value=\{vd0\}}
+C {lab_pin.sym} -100 -80 3 0 {name=l52 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -100 -200 1 0 {name=l53 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -590 50 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -610 470 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -490 120 2 0 {name=l23 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -610 410 0 0 {name=I0 value=\{iref\}}
+C {lab_pin.sym} -570 370 3 0 {name=l36 sig_type=std_logic lab=vss}
+C {noconn.sym} -490 140 2 0 {name=l75}
+C {noconn.sym} -490 160 2 0 {name=l76}
+C {noconn.sym} -490 180 2 0 {name=l77}
+C {noconn.sym} -490 200 2 0 {name=l78}
+C {noconn.sym} -490 220 2 0 {name=l79}
+C {noconn.sym} -490 240 2 0 {name=l80}
+C {noconn.sym} -490 260 2 0 {name=l81}
+C {noconn.sym} -490 280 2 0 {name=l82}
+C {noconn.sym} -490 300 2 0 {name=l83}
+C {top_pll_v1.sym} 10 250 0 0 {name=x1}
+C {lab_pin.sym} 180 90 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 240 90 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 80 1 0 {name=l9 sig_type=std_logic lab=iref_cp}
+C {lab_pin.sym} -200 90 1 0 {name=l10 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -370 250 2 1 {name=l11 sig_type=std_logic lab=A}
+C {lab_wire.sym} 470 250 0 1 {name=l61 sig_type=std_logic lab=out_to_pad}
+C {noconn.sym} 280 430 1 1 {name=l66}
+C {noconn.sym} 260 430 1 1 {name=l67}
+C {noconn.sym} 240 430 1 1 {name=l68}
+C {noconn.sym} 220 430 1 1 {name=l69}
+C {noconn.sym} 200 430 1 1 {name=l70}
+C {noconn.sym} 130 430 1 1 {name=l24}
+C {noconn.sym} 110 430 1 1 {name=l42}
+C {noconn.sym} 90 430 1 1 {name=l43}
+C {noconn.sym} 70 430 1 1 {name=l44}
+C {noconn.sym} -120 480 3 0 {name=l33}
+C {noconn.sym} -100 480 3 0 {name=l34}
+C {lab_wire.sym} -120 440 3 0 {name=l50 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} -100 440 3 0 {name=l51 sig_type=std_logic lab=pswitch}
+C {noconn.sym} -80 480 3 0 {name=l56}
+C {lab_wire.sym} -80 440 3 0 {name=l57 sig_type=std_logic lab=biasp}
+C {noconn.sym} -280 480 3 0 {name=l54}
+C {lab_wire.sym} -280 440 3 0 {name=l55 sig_type=std_logic lab=pfd_reset}
+C {noconn.sym} -260 480 3 0 {name=l12}
+C {lab_wire.sym} -260 440 3 0 {name=l13 sig_type=std_logic lab=QA}
+C {noconn.sym} -240 480 3 0 {name=l15}
+C {lab_wire.sym} -240 440 3 0 {name=l16 sig_type=std_logic lab=QB}
+C {noconn.sym} -210 480 3 0 {name=l17}
+C {lab_wire.sym} -210 440 3 0 {name=l18 sig_type=std_logic lab=Up}
+C {noconn.sym} -190 480 3 0 {name=l20}
+C {lab_wire.sym} -190 440 3 0 {name=l21 sig_type=std_logic lab=nUp}
+C {noconn.sym} -170 480 3 0 {name=l22}
+C {lab_wire.sym} -170 440 3 0 {name=l25 sig_type=std_logic lab=Down}
+C {noconn.sym} -150 480 3 0 {name=l26}
+C {lab_wire.sym} -150 440 3 0 {name=l27 sig_type=std_logic lab=nDown}
+C {noconn.sym} -50 430 1 1 {name=l28}
+C {noconn.sym} -20 480 3 0 {name=l29}
+C {lab_wire.sym} -20 440 3 0 {name=l30 sig_type=std_logic lab=vctrl}
+C {noconn.sym} 0 480 3 0 {name=l31}
+C {lab_wire.sym} 0 440 3 0 {name=l32 sig_type=std_logic lab=vco_out}
+C {noconn.sym} 20 480 3 0 {name=l35}
+C {lab_wire.sym} 20 440 3 0 {name=l37 sig_type=std_logic lab=vco_buffer_out}
+C {noconn.sym} 40 480 3 0 {name=l38}
+C {lab_wire.sym} 40 440 3 0 {name=l39 sig_type=std_logic lab=out_to_div}
+C {noconn.sym} 150 480 3 0 {name=l40}
+C {lab_wire.sym} 150 440 3 0 {name=l41 sig_type=std_logic lab=out_by_2}
+C {noconn.sym} 170 480 3 0 {name=l45}
+C {lab_wire.sym} 170 440 3 0 {name=l46 sig_type=std_logic lab=n_out_by_2}
+C {noconn.sym} 300 480 3 0 {name=l47}
+C {lab_wire.sym} 300 440 3 0 {name=l49 sig_type=std_logic lab=out_by_5}
+C {lab_wire.sym} -50 390 3 0 {name=l58 sig_type=std_logic lab=lf_vc}
+C {lab_wire.sym} 70 420 3 0 {name=l59 sig_type=std_logic lab=out_div_2}
+C {lab_wire.sym} 90 420 3 0 {name=l60 sig_type=std_logic lab=n_out_div_2}
+C {lab_wire.sym} 110 420 3 0 {name=l62 sig_type=std_logic lab=out_buffer_div_2}
+C {lab_wire.sym} 130 420 3 0 {name=l63 sig_type=std_logic lab=n_out_buffer_div_2}
+C {lab_wire.sym} 200 420 3 0 {name=l64 sig_type=std_logic lab=div_5_Q0}
+C {lab_wire.sym} 220 420 3 0 {name=l65 sig_type=std_logic lab=div_5_nQ0}
+C {lab_wire.sym} 240 420 3 0 {name=l71 sig_type=std_logic lab=div_5_Q1}
+C {lab_wire.sym} 260 420 3 0 {name=l72 sig_type=std_logic lab=div_5_Q1_shift}
+C {lab_wire.sym} 280 420 3 0 {name=l73 sig_type=std_logic lab=div_5_nQ2}
+C {bias.sym} -590 210 0 0 {name=x2}
+C {netlist_not_shown.sym} 230 -170 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {capa.sym} 510 310 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 510 370 3 0 {name=l48 sig_type=std_logic lab=vss}
+C {noconn.sym} 350 430 3 0 {name=l74}
+C {lab_wire.sym} 350 390 3 0 {name=l84 sig_type=std_logic lab=out_to_buffer}
diff --git a/xschem/tb_top_pll_v1_pex_c.sch b/xschem/tb_top_pll_v1_pex_c.sch
new file mode 100644
index 0000000..8814e0f
--- /dev/null
+++ b/xschem/tb_top_pll_v1_pex_c.sch
@@ -0,0 +1,247 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -620 -120 -620 -90 { lab=GND}
+N -470 -120 -470 -90 { lab=vss}
+N -550 -120 -550 -90 { lab=vss}
+N -620 -210 -620 -180 { lab=vss}
+N -470 -210 -470 -180 { lab=A}
+N -550 -210 -550 -180 { lab=vdd}
+N -100 -110 -100 -80 { lab=vss}
+N -100 -200 -100 -170 { lab=D0}
+N -590 50 -590 80 { lab=vdd}
+N -610 440 -610 470 { lab=vss}
+N -530 120 -490 120 { lab=iref_cp}
+N -610 350 -610 380 { lab=#net1}
+N -610 340 -610 350 { lab=#net1}
+N -570 340 -570 370 { lab=vss}
+N -530 140 -490 140 { lab=#net2}
+N -530 160 -490 160 { lab=#net3}
+N -530 180 -490 180 { lab=#net4}
+N -530 200 -490 200 { lab=#net5}
+N -530 220 -490 220 { lab=#net6}
+N -530 240 -490 240 { lab=#net7}
+N -530 260 -490 260 { lab=#net8}
+N -530 280 -490 280 { lab=#net9}
+N -530 300 -490 300 { lab=#net10}
+N 180 90 180 120 { lab=vdd}
+N 240 90 240 120 { lab=vss}
+N -280 80 -280 120 { lab=iref_cp}
+N -200 90 -200 120 { lab=D0}
+N -370 250 -340 250 { lab=A}
+N 280 380 280 430 { lab=div_5_nQ2}
+N 260 380 260 430 { lab=div_5_Q1_shift}
+N 240 380 240 430 { lab=div_5_Q1}
+N 220 380 220 430 { lab=div_5_nQ0}
+N 200 380 200 430 { lab=div_5_Q0}
+N 130 380 130 430 { lab=n_out_buffer_div_2}
+N 110 380 110 430 { lab=out_buffer_div_2}
+N 90 380 90 430 { lab=n_out_div_2}
+N 70 380 70 430 { lab=out_div_2}
+N -120 430 -120 480 { lab=nswitch}
+N -100 430 -100 480 { lab=pswitch}
+N -80 430 -80 480 { lab=biasp}
+N -80 380 -80 430 { lab=biasp}
+N -100 380 -100 430 { lab=pswitch}
+N -120 380 -120 430 { lab=nswitch}
+N -280 430 -280 480 { lab=pfd_reset}
+N -280 380 -280 430 { lab=pfd_reset}
+N -260 430 -260 480 { lab=QA}
+N -260 380 -260 430 { lab=QA}
+N -240 430 -240 480 { lab=QB}
+N -240 380 -240 430 { lab=QB}
+N -210 430 -210 480 { lab=Up}
+N -210 380 -210 430 { lab=Up}
+N -190 430 -190 480 { lab=nUp}
+N -190 380 -190 430 { lab=nUp}
+N -170 430 -170 480 { lab=Down}
+N -170 380 -170 430 { lab=Down}
+N -150 430 -150 480 { lab=nDown}
+N -150 380 -150 430 { lab=nDown}
+N -50 380 -50 430 { lab=lf_vc}
+N -20 430 -20 480 { lab=vctrl}
+N -20 380 -20 430 { lab=vctrl}
+N 0 430 0 480 { lab=vco_out}
+N 0 380 0 430 { lab=vco_out}
+N 20 430 20 480 { lab=vco_buffer_out}
+N 20 380 20 430 { lab=vco_buffer_out}
+N 40 430 40 480 { lab=out_to_div}
+N 40 380 40 430 { lab=out_to_div}
+N 150 430 150 480 { lab=out_by_2}
+N 150 380 150 430 { lab=out_by_2}
+N 170 430 170 480 { lab=n_out_by_2}
+N 170 380 170 430 { lab=n_out_by_2}
+N 300 430 300 480 { lab=out_by_5}
+N 300 380 300 430 { lab=out_by_5}
+N 420 250 460 250 { lab=out_to_pad}
+N 460 250 510 250 { lab=out_to_pad}
+N 510 250 510 280 { lab=out_to_pad}
+N 510 340 510 370 { lab=vss}
+N 350 380 350 430 { lab=out_to_buffer}
+C {vsource.sym} -620 -150 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -550 -150 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -470 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -620 -90 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -620 -210 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -90 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -470 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -210 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -470 -210 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 60 -170 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SF
+.include ~/caravel_analog_fulgor/xschem/simulations/top_pll_v1_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_div) val=0.9 fall=1005 targ v(out_to_div) val=0.9 fall=1105
+ let T = Tosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14 v(out_by_5)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 (out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+ plot v(out_by_5) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+.end
+"}
+C {vsource.sym} -100 -140 0 0 {name=VD0 value=\{vd0\}}
+C {lab_pin.sym} -100 -80 3 0 {name=l52 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -100 -200 1 0 {name=l53 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -590 50 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -610 470 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -490 120 2 0 {name=l23 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -610 410 0 0 {name=I0 value=\{iref\}}
+C {lab_pin.sym} -570 370 3 0 {name=l36 sig_type=std_logic lab=vss}
+C {noconn.sym} -490 140 2 0 {name=l75}
+C {noconn.sym} -490 160 2 0 {name=l76}
+C {noconn.sym} -490 180 2 0 {name=l77}
+C {noconn.sym} -490 200 2 0 {name=l78}
+C {noconn.sym} -490 220 2 0 {name=l79}
+C {noconn.sym} -490 240 2 0 {name=l80}
+C {noconn.sym} -490 260 2 0 {name=l81}
+C {noconn.sym} -490 280 2 0 {name=l82}
+C {noconn.sym} -490 300 2 0 {name=l83}
+C {lab_pin.sym} 180 90 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 240 90 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 80 1 0 {name=l9 sig_type=std_logic lab=iref_cp}
+C {lab_pin.sym} -200 90 1 0 {name=l10 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -370 250 2 1 {name=l11 sig_type=std_logic lab=A}
+C {noconn.sym} 280 430 1 1 {name=l66}
+C {noconn.sym} 260 430 1 1 {name=l67}
+C {noconn.sym} 240 430 1 1 {name=l68}
+C {noconn.sym} 220 430 1 1 {name=l69}
+C {noconn.sym} 200 430 1 1 {name=l70}
+C {noconn.sym} 130 430 1 1 {name=l24}
+C {noconn.sym} 110 430 1 1 {name=l42}
+C {noconn.sym} 90 430 1 1 {name=l43}
+C {noconn.sym} 70 430 1 1 {name=l44}
+C {noconn.sym} -120 480 3 0 {name=l33}
+C {noconn.sym} -100 480 3 0 {name=l34}
+C {lab_wire.sym} -120 440 3 0 {name=l50 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} -100 440 3 0 {name=l51 sig_type=std_logic lab=pswitch}
+C {noconn.sym} -80 480 3 0 {name=l56}
+C {lab_wire.sym} -80 440 3 0 {name=l57 sig_type=std_logic lab=biasp}
+C {noconn.sym} -280 480 3 0 {name=l54}
+C {lab_wire.sym} -280 440 3 0 {name=l55 sig_type=std_logic lab=pfd_reset}
+C {noconn.sym} -260 480 3 0 {name=l12}
+C {lab_wire.sym} -260 440 3 0 {name=l13 sig_type=std_logic lab=QA}
+C {noconn.sym} -240 480 3 0 {name=l15}
+C {lab_wire.sym} -240 440 3 0 {name=l16 sig_type=std_logic lab=QB}
+C {noconn.sym} -210 480 3 0 {name=l17}
+C {lab_wire.sym} -210 440 3 0 {name=l18 sig_type=std_logic lab=Up}
+C {noconn.sym} -190 480 3 0 {name=l20}
+C {lab_wire.sym} -190 440 3 0 {name=l21 sig_type=std_logic lab=nUp}
+C {noconn.sym} -170 480 3 0 {name=l22}
+C {lab_wire.sym} -170 440 3 0 {name=l25 sig_type=std_logic lab=Down}
+C {noconn.sym} -150 480 3 0 {name=l26}
+C {lab_wire.sym} -150 440 3 0 {name=l27 sig_type=std_logic lab=nDown}
+C {noconn.sym} -50 430 1 1 {name=l28}
+C {noconn.sym} -20 480 3 0 {name=l29}
+C {lab_wire.sym} -20 440 3 0 {name=l30 sig_type=std_logic lab=vctrl}
+C {noconn.sym} 0 480 3 0 {name=l31}
+C {lab_wire.sym} 0 440 3 0 {name=l32 sig_type=std_logic lab=vco_out}
+C {noconn.sym} 20 480 3 0 {name=l35}
+C {lab_wire.sym} 20 440 3 0 {name=l37 sig_type=std_logic lab=vco_buffer_out}
+C {noconn.sym} 40 480 3 0 {name=l38}
+C {lab_wire.sym} 40 440 3 0 {name=l39 sig_type=std_logic lab=out_to_div}
+C {noconn.sym} 150 480 3 0 {name=l40}
+C {lab_wire.sym} 150 440 3 0 {name=l41 sig_type=std_logic lab=out_by_2}
+C {noconn.sym} 170 480 3 0 {name=l45}
+C {lab_wire.sym} 170 440 3 0 {name=l46 sig_type=std_logic lab=n_out_by_2}
+C {noconn.sym} 300 480 3 0 {name=l47}
+C {lab_wire.sym} 300 440 3 0 {name=l49 sig_type=std_logic lab=out_by_5}
+C {lab_wire.sym} -50 390 3 0 {name=l58 sig_type=std_logic lab=lf_vc}
+C {lab_wire.sym} 70 420 3 0 {name=l59 sig_type=std_logic lab=out_div_2}
+C {lab_wire.sym} 90 420 3 0 {name=l60 sig_type=std_logic lab=n_out_div_2}
+C {lab_wire.sym} 110 420 3 0 {name=l62 sig_type=std_logic lab=out_buffer_div_2}
+C {lab_wire.sym} 130 420 3 0 {name=l63 sig_type=std_logic lab=n_out_buffer_div_2}
+C {lab_wire.sym} 200 420 3 0 {name=l64 sig_type=std_logic lab=div_5_Q0}
+C {lab_wire.sym} 220 420 3 0 {name=l65 sig_type=std_logic lab=div_5_nQ0}
+C {lab_wire.sym} 240 420 3 0 {name=l71 sig_type=std_logic lab=div_5_Q1}
+C {lab_wire.sym} 260 420 3 0 {name=l72 sig_type=std_logic lab=div_5_Q1_shift}
+C {lab_wire.sym} 280 420 3 0 {name=l73 sig_type=std_logic lab=div_5_nQ2}
+C {top_pll_v1_pex_c.sym} 10 250 0 0 {name=x1}
+C {bias_pex_c.sym} -590 210 0 0 {name=x9}
+C {lab_wire.sym} 470 250 0 1 {name=l74 sig_type=std_logic lab=out_to_pad}
+C {capa.sym} 510 310 0 0 {name=C1
+m=1
+value=10p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 510 370 3 0 {name=l84 sig_type=std_logic lab=vss}
+C {noconn.sym} 350 430 3 0 {name=l85}
+C {lab_wire.sym} 350 390 3 0 {name=l86 sig_type=std_logic lab=out_to_buffer}
diff --git a/xschem/tb_top_pll_v1_pex_no_integration.sch b/xschem/tb_top_pll_v1_pex_no_integration.sch
new file mode 100644
index 0000000..630563d
--- /dev/null
+++ b/xschem/tb_top_pll_v1_pex_no_integration.sch
@@ -0,0 +1,260 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -620 -120 -620 -90 { lab=GND}
+N -470 -120 -470 -90 { lab=vss}
+N -550 -120 -550 -90 { lab=vss}
+N -620 -210 -620 -180 { lab=vss}
+N -470 -210 -470 -180 { lab=A}
+N -550 -210 -550 -180 { lab=vdd}
+N -100 -110 -100 -80 { lab=vss}
+N -100 -200 -100 -170 { lab=D0}
+N -590 50 -590 80 { lab=vdd}
+N -610 440 -610 470 { lab=vss}
+N -530 120 -490 120 { lab=iref_cp}
+N -610 350 -610 380 { lab=#net1}
+N -610 340 -610 350 { lab=#net1}
+N -570 340 -570 370 { lab=vss}
+N -530 140 -490 140 { lab=#net2}
+N -530 160 -490 160 { lab=#net3}
+N -530 180 -490 180 { lab=#net4}
+N -530 200 -490 200 { lab=#net5}
+N -530 220 -490 220 { lab=#net6}
+N -530 240 -490 240 { lab=#net7}
+N -530 260 -490 260 { lab=#net8}
+N -530 280 -490 280 { lab=#net9}
+N -530 300 -490 300 { lab=#net10}
+N 180 90 180 120 { lab=vdd}
+N 240 90 240 120 { lab=vss}
+N -280 80 -280 120 { lab=iref_cp}
+N -200 90 -200 120 { lab=D0}
+N -370 250 -340 250 { lab=A}
+N 280 380 280 430 { lab=div_5_nQ2}
+N 260 380 260 430 { lab=div_5_Q1_shift}
+N 240 380 240 430 { lab=div_5_Q1}
+N 220 380 220 430 { lab=div_5_nQ0}
+N 200 380 200 430 { lab=div_5_Q0}
+N 130 380 130 430 { lab=n_out_buffer_div_2}
+N 110 380 110 430 { lab=out_buffer_div_2}
+N 90 380 90 430 { lab=n_out_div_2}
+N 70 380 70 430 { lab=out_div_2}
+N -120 430 -120 480 { lab=nswitch}
+N -100 430 -100 480 { lab=pswitch}
+N -80 430 -80 480 { lab=biasp}
+N -80 380 -80 430 { lab=biasp}
+N -100 380 -100 430 { lab=pswitch}
+N -120 380 -120 430 { lab=nswitch}
+N -280 430 -280 480 { lab=pfd_reset}
+N -280 380 -280 430 { lab=pfd_reset}
+N -260 430 -260 480 { lab=QA}
+N -260 380 -260 430 { lab=QA}
+N -240 430 -240 480 { lab=QB}
+N -240 380 -240 430 { lab=QB}
+N -210 430 -210 480 { lab=Up}
+N -210 380 -210 430 { lab=Up}
+N -190 430 -190 480 { lab=nUp}
+N -190 380 -190 430 { lab=nUp}
+N -170 430 -170 480 { lab=Down}
+N -170 380 -170 430 { lab=Down}
+N -150 430 -150 480 { lab=nDown}
+N -150 380 -150 430 { lab=nDown}
+N -50 380 -50 430 { lab=lf_vc}
+N -20 430 -20 480 { lab=vctrl}
+N -20 380 -20 430 { lab=vctrl}
+N 0 430 0 480 { lab=vco_out}
+N 0 380 0 430 { lab=vco_out}
+N 20 430 20 480 { lab=vco_buffer_out}
+N 20 380 20 430 { lab=vco_buffer_out}
+N 40 430 40 480 { lab=out_to_div}
+N 40 380 40 430 { lab=out_to_div}
+N 150 430 150 480 { lab=out_by_2}
+N 150 380 150 430 { lab=out_by_2}
+N 170 430 170 480 { lab=n_out_by_2}
+N 170 380 170 430 { lab=n_out_by_2}
+N 300 430 300 480 { lab=out_by_5}
+N 300 380 300 430 { lab=out_by_5}
+N 420 250 460 250 { lab=out_to_pad}
+N 460 250 510 250 { lab=out_to_pad}
+N 510 250 510 280 { lab=out_to_pad}
+N 510 340 510 370 { lab=vss}
+N 350 380 350 430 { lab=out_to_buffer}
+C {vsource.sym} -620 -150 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -550 -150 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -470 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -620 -90 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -620 -210 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -90 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -470 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -210 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -470 -210 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 60 -170 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/charge_pump_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/loop_filter_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/ring_osc_buffer_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/buffer_salida_pex_c.spice
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+ let T = Tosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14 v(out_by_5)+16
+ plot v(out_to_pad)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+ plot v(out_by_5) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+.end
+"}
+C {vsource.sym} -100 -140 0 0 {name=VD0 value=\{vd0\}}
+C {lab_pin.sym} -100 -80 3 0 {name=l52 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -100 -200 1 0 {name=l53 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -590 50 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -610 470 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -490 120 2 0 {name=l23 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -610 410 0 0 {name=I0 value=\{iref\}}
+C {lab_pin.sym} -570 370 3 0 {name=l36 sig_type=std_logic lab=vss}
+C {noconn.sym} -490 140 2 0 {name=l75}
+C {noconn.sym} -490 160 2 0 {name=l76}
+C {noconn.sym} -490 180 2 0 {name=l77}
+C {noconn.sym} -490 200 2 0 {name=l78}
+C {noconn.sym} -490 220 2 0 {name=l79}
+C {noconn.sym} -490 240 2 0 {name=l80}
+C {noconn.sym} -490 260 2 0 {name=l81}
+C {noconn.sym} -490 280 2 0 {name=l82}
+C {noconn.sym} -490 300 2 0 {name=l83}
+C {lab_pin.sym} 180 90 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 240 90 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 80 1 0 {name=l9 sig_type=std_logic lab=iref_cp}
+C {lab_pin.sym} -200 90 1 0 {name=l10 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -370 250 2 1 {name=l11 sig_type=std_logic lab=A}
+C {noconn.sym} 280 430 1 1 {name=l66}
+C {noconn.sym} 260 430 1 1 {name=l67}
+C {noconn.sym} 240 430 1 1 {name=l68}
+C {noconn.sym} 220 430 1 1 {name=l69}
+C {noconn.sym} 200 430 1 1 {name=l70}
+C {noconn.sym} 130 430 1 1 {name=l24}
+C {noconn.sym} 110 430 1 1 {name=l42}
+C {noconn.sym} 90 430 1 1 {name=l43}
+C {noconn.sym} 70 430 1 1 {name=l44}
+C {noconn.sym} -120 480 3 0 {name=l33}
+C {noconn.sym} -100 480 3 0 {name=l34}
+C {lab_wire.sym} -120 440 3 0 {name=l50 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} -100 440 3 0 {name=l51 sig_type=std_logic lab=pswitch}
+C {noconn.sym} -80 480 3 0 {name=l56}
+C {lab_wire.sym} -80 440 3 0 {name=l57 sig_type=std_logic lab=biasp}
+C {noconn.sym} -280 480 3 0 {name=l54}
+C {lab_wire.sym} -280 440 3 0 {name=l55 sig_type=std_logic lab=pfd_reset}
+C {noconn.sym} -260 480 3 0 {name=l12}
+C {lab_wire.sym} -260 440 3 0 {name=l13 sig_type=std_logic lab=QA}
+C {noconn.sym} -240 480 3 0 {name=l15}
+C {lab_wire.sym} -240 440 3 0 {name=l16 sig_type=std_logic lab=QB}
+C {noconn.sym} -210 480 3 0 {name=l17}
+C {lab_wire.sym} -210 440 3 0 {name=l18 sig_type=std_logic lab=Up}
+C {noconn.sym} -190 480 3 0 {name=l20}
+C {lab_wire.sym} -190 440 3 0 {name=l21 sig_type=std_logic lab=nUp}
+C {noconn.sym} -170 480 3 0 {name=l22}
+C {lab_wire.sym} -170 440 3 0 {name=l25 sig_type=std_logic lab=Down}
+C {noconn.sym} -150 480 3 0 {name=l26}
+C {lab_wire.sym} -150 440 3 0 {name=l27 sig_type=std_logic lab=nDown}
+C {noconn.sym} -50 430 1 1 {name=l28}
+C {noconn.sym} -20 480 3 0 {name=l29}
+C {lab_wire.sym} -20 440 3 0 {name=l30 sig_type=std_logic lab=vctrl}
+C {noconn.sym} 0 480 3 0 {name=l31}
+C {lab_wire.sym} 0 440 3 0 {name=l32 sig_type=std_logic lab=vco_out}
+C {noconn.sym} 20 480 3 0 {name=l35}
+C {lab_wire.sym} 20 440 3 0 {name=l37 sig_type=std_logic lab=vco_buffer_out}
+C {noconn.sym} 40 480 3 0 {name=l38}
+C {lab_wire.sym} 40 440 3 0 {name=l39 sig_type=std_logic lab=out_to_div}
+C {noconn.sym} 150 480 3 0 {name=l40}
+C {lab_wire.sym} 150 440 3 0 {name=l41 sig_type=std_logic lab=out_by_2}
+C {noconn.sym} 170 480 3 0 {name=l45}
+C {lab_wire.sym} 170 440 3 0 {name=l46 sig_type=std_logic lab=n_out_by_2}
+C {noconn.sym} 300 480 3 0 {name=l47}
+C {lab_wire.sym} 300 440 3 0 {name=l49 sig_type=std_logic lab=out_by_5}
+C {lab_wire.sym} -50 390 3 0 {name=l58 sig_type=std_logic lab=lf_vc}
+C {lab_wire.sym} 70 420 3 0 {name=l59 sig_type=std_logic lab=out_div_2}
+C {lab_wire.sym} 90 420 3 0 {name=l60 sig_type=std_logic lab=n_out_div_2}
+C {lab_wire.sym} 110 420 3 0 {name=l62 sig_type=std_logic lab=out_buffer_div_2}
+C {lab_wire.sym} 130 420 3 0 {name=l63 sig_type=std_logic lab=n_out_buffer_div_2}
+C {lab_wire.sym} 200 420 3 0 {name=l64 sig_type=std_logic lab=div_5_Q0}
+C {lab_wire.sym} 220 420 3 0 {name=l65 sig_type=std_logic lab=div_5_nQ0}
+C {lab_wire.sym} 240 420 3 0 {name=l71 sig_type=std_logic lab=div_5_Q1}
+C {lab_wire.sym} 260 420 3 0 {name=l72 sig_type=std_logic lab=div_5_Q1_shift}
+C {lab_wire.sym} 280 420 3 0 {name=l73 sig_type=std_logic lab=div_5_nQ2}
+C {netlist_not_shown.sym} 230 -170 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {bias_pex_c.sym} -590 210 0 0 {name=x2}
+C {top_pll_v1_pex_no_integration.sym} 10 250 0 0 {name=x1}
+C {lab_wire.sym} 470 250 0 1 {name=l61 sig_type=std_logic lab=out_to_pad}
+C {capa.sym} 510 310 0 0 {name=C1
+m=1
+value=20p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 510 370 3 0 {name=l48 sig_type=std_logic lab=vss}
+C {noconn.sym} 350 430 3 0 {name=l74}
+C {lab_wire.sym} 350 390 3 0 {name=l84 sig_type=std_logic lab=out_to_buffer}
diff --git a/xschem/tb_top_pll_v2_pex_c.sch b/xschem/tb_top_pll_v2_pex_c.sch
new file mode 100644
index 0000000..e663688
--- /dev/null
+++ b/xschem/tb_top_pll_v2_pex_c.sch
@@ -0,0 +1,255 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -620 -120 -620 -90 { lab=GND}
+N -470 -120 -470 -90 { lab=vss}
+N -550 -120 -550 -90 { lab=vss}
+N -620 -210 -620 -180 { lab=vss}
+N -470 -210 -470 -180 { lab=A}
+N -550 -210 -550 -180 { lab=vdd}
+N -100 -110 -100 -80 { lab=vss}
+N -100 -200 -100 -170 { lab=D0_vco}
+N -590 50 -590 80 { lab=vdd}
+N -610 440 -610 470 { lab=vss}
+N -530 120 -490 120 { lab=iref_cp}
+N -610 350 -610 380 { lab=#net1}
+N -610 340 -610 350 { lab=#net1}
+N -570 340 -570 370 { lab=vss}
+N -530 140 -490 140 { lab=#net2}
+N -530 160 -490 160 { lab=#net3}
+N -530 180 -490 180 { lab=#net4}
+N -530 200 -490 200 { lab=#net5}
+N -530 220 -490 220 { lab=#net6}
+N -530 240 -490 240 { lab=#net7}
+N -530 260 -490 260 { lab=#net8}
+N -530 280 -490 280 { lab=#net9}
+N -530 300 -490 300 { lab=#net10}
+N 180 90 180 120 { lab=vdd}
+N 240 90 240 120 { lab=vss}
+N -280 80 -280 120 { lab=iref_cp}
+N -200 90 -200 120 { lab=D0_vco}
+N -370 250 -340 250 { lab=A}
+N 280 380 280 430 { lab=div_5_nQ2}
+N 260 380 260 430 { lab=div_5_Q1_shift}
+N 240 380 240 430 { lab=div_5_Q1}
+N 220 380 220 430 { lab=div_5_nQ0}
+N 200 380 200 430 { lab=div_5_Q0}
+N 130 380 130 430 { lab=n_out_buffer_div_2}
+N 110 380 110 430 { lab=out_buffer_div_2}
+N 90 380 90 430 { lab=n_out_div_2}
+N 70 380 70 430 { lab=out_div_2}
+N -120 430 -120 480 { lab=nswitch}
+N -100 430 -100 480 { lab=pswitch}
+N -80 430 -80 480 { lab=biasp}
+N -80 380 -80 430 { lab=biasp}
+N -100 380 -100 430 { lab=pswitch}
+N -120 380 -120 430 { lab=nswitch}
+N -280 430 -280 480 { lab=pfd_reset}
+N -280 380 -280 430 { lab=pfd_reset}
+N -260 430 -260 480 { lab=QA}
+N -260 380 -260 430 { lab=QA}
+N -240 430 -240 480 { lab=QB}
+N -240 380 -240 430 { lab=QB}
+N -210 430 -210 480 { lab=Up}
+N -210 380 -210 430 { lab=Up}
+N -190 430 -190 480 { lab=nUp}
+N -190 380 -190 430 { lab=nUp}
+N -170 430 -170 480 { lab=Down}
+N -170 380 -170 430 { lab=Down}
+N -150 430 -150 480 { lab=nDown}
+N -150 380 -150 430 { lab=nDown}
+N -50 380 -50 430 { lab=lf_vc}
+N -20 430 -20 480 { lab=vctrl}
+N -20 380 -20 430 { lab=vctrl}
+N 0 430 0 480 { lab=vco_out}
+N 0 380 0 430 { lab=vco_out}
+N 20 430 20 480 { lab=vco_buffer_out}
+N 20 380 20 430 { lab=vco_buffer_out}
+N 40 430 40 480 { lab=out_to_div}
+N 40 380 40 430 { lab=out_to_div}
+N 150 430 150 480 { lab=out_by_2}
+N 150 380 150 430 { lab=out_by_2}
+N 170 430 170 480 { lab=n_out_by_2}
+N 170 380 170 430 { lab=n_out_by_2}
+N 300 430 300 480 { lab=out_by_5}
+N 300 380 300 430 { lab=out_by_5}
+N 420 250 460 250 { lab=out_to_pad}
+N 460 250 510 250 { lab=out_to_pad}
+N 510 250 510 280 { lab=out_to_pad}
+N 510 340 510 370 { lab=vss}
+N 350 380 350 430 { lab=out_to_buffer}
+N -140 90 -140 120 { lab=D0_cap}
+N -20 -110 -20 -80 { lab=vss}
+N -20 -200 -20 -170 { lab=D0_cap}
+C {vsource.sym} -620 -150 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -550 -150 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -470 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -620 -90 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -620 -210 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -90 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -470 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -210 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -470 -210 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 60 -170 0 0 {name=simulation only_toplevel=false
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param vd1 = 0.0
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.include ~/caravel_analog_fulgor/xschem/simulations/top_pll_v2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+ tran 0.01ns 1.5us
+ meas tran Tosc trig v(out_to_div) val=0.9 fall=1005 targ v(out_to_div) val=0.9 fall=1105
+ let T = Tosc/100.0
+ let f = 1/T
+ echo .
+ echo ------ PLL simulation ------
+ print T f
+ *write tb_PLL_tran.raw
+ plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14 v(out_by_5)+16
+ plot v(out_to_pad)+12 v(out_to_buffer)+9 (out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+ plot v(out_by_5) v(out_by_2) v(out_to_div)
+ plot v(vctrl)
+ plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+.end
+"}
+C {vsource.sym} -100 -140 0 0 {name=VD0 value=\{vd0\}}
+C {lab_pin.sym} -100 -80 3 0 {name=l52 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -100 -200 1 0 {name=l53 sig_type=std_logic lab=D0_vco}
+C {lab_pin.sym} -590 50 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -610 470 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -490 120 2 0 {name=l23 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -610 410 0 0 {name=I0 value=\{iref\}}
+C {lab_pin.sym} -570 370 3 0 {name=l36 sig_type=std_logic lab=vss}
+C {noconn.sym} -490 140 2 0 {name=l75}
+C {noconn.sym} -490 160 2 0 {name=l76}
+C {noconn.sym} -490 180 2 0 {name=l77}
+C {noconn.sym} -490 200 2 0 {name=l78}
+C {noconn.sym} -490 220 2 0 {name=l79}
+C {noconn.sym} -490 240 2 0 {name=l80}
+C {noconn.sym} -490 260 2 0 {name=l81}
+C {noconn.sym} -490 280 2 0 {name=l82}
+C {noconn.sym} -490 300 2 0 {name=l83}
+C {lab_pin.sym} 180 90 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 240 90 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 80 1 0 {name=l9 sig_type=std_logic lab=iref_cp}
+C {lab_pin.sym} -200 90 1 0 {name=l10 sig_type=std_logic lab=D0_vco}
+C {lab_pin.sym} -370 250 2 1 {name=l11 sig_type=std_logic lab=A}
+C {noconn.sym} 280 430 1 1 {name=l66}
+C {noconn.sym} 260 430 1 1 {name=l67}
+C {noconn.sym} 240 430 1 1 {name=l68}
+C {noconn.sym} 220 430 1 1 {name=l69}
+C {noconn.sym} 200 430 1 1 {name=l70}
+C {noconn.sym} 130 430 1 1 {name=l24}
+C {noconn.sym} 110 430 1 1 {name=l42}
+C {noconn.sym} 90 430 1 1 {name=l43}
+C {noconn.sym} 70 430 1 1 {name=l44}
+C {noconn.sym} -120 480 3 0 {name=l33}
+C {noconn.sym} -100 480 3 0 {name=l34}
+C {lab_wire.sym} -120 440 3 0 {name=l50 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} -100 440 3 0 {name=l51 sig_type=std_logic lab=pswitch}
+C {noconn.sym} -80 480 3 0 {name=l56}
+C {lab_wire.sym} -80 440 3 0 {name=l57 sig_type=std_logic lab=biasp}
+C {noconn.sym} -280 480 3 0 {name=l54}
+C {lab_wire.sym} -280 440 3 0 {name=l55 sig_type=std_logic lab=pfd_reset}
+C {noconn.sym} -260 480 3 0 {name=l12}
+C {lab_wire.sym} -260 440 3 0 {name=l13 sig_type=std_logic lab=QA}
+C {noconn.sym} -240 480 3 0 {name=l15}
+C {lab_wire.sym} -240 440 3 0 {name=l16 sig_type=std_logic lab=QB}
+C {noconn.sym} -210 480 3 0 {name=l17}
+C {lab_wire.sym} -210 440 3 0 {name=l18 sig_type=std_logic lab=Up}
+C {noconn.sym} -190 480 3 0 {name=l20}
+C {lab_wire.sym} -190 440 3 0 {name=l21 sig_type=std_logic lab=nUp}
+C {noconn.sym} -170 480 3 0 {name=l22}
+C {lab_wire.sym} -170 440 3 0 {name=l25 sig_type=std_logic lab=Down}
+C {noconn.sym} -150 480 3 0 {name=l26}
+C {lab_wire.sym} -150 440 3 0 {name=l27 sig_type=std_logic lab=nDown}
+C {noconn.sym} -50 430 1 1 {name=l28}
+C {noconn.sym} -20 480 3 0 {name=l29}
+C {lab_wire.sym} -20 440 3 0 {name=l30 sig_type=std_logic lab=vctrl}
+C {noconn.sym} 0 480 3 0 {name=l31}
+C {lab_wire.sym} 0 440 3 0 {name=l32 sig_type=std_logic lab=vco_out}
+C {noconn.sym} 20 480 3 0 {name=l35}
+C {lab_wire.sym} 20 440 3 0 {name=l37 sig_type=std_logic lab=vco_buffer_out}
+C {noconn.sym} 40 480 3 0 {name=l38}
+C {lab_wire.sym} 40 440 3 0 {name=l39 sig_type=std_logic lab=out_to_div}
+C {noconn.sym} 150 480 3 0 {name=l40}
+C {lab_wire.sym} 150 440 3 0 {name=l41 sig_type=std_logic lab=out_by_2}
+C {noconn.sym} 170 480 3 0 {name=l45}
+C {lab_wire.sym} 170 440 3 0 {name=l46 sig_type=std_logic lab=n_out_by_2}
+C {noconn.sym} 300 480 3 0 {name=l47}
+C {lab_wire.sym} 300 440 3 0 {name=l49 sig_type=std_logic lab=out_by_5}
+C {lab_wire.sym} -50 390 3 0 {name=l58 sig_type=std_logic lab=lf_vc}
+C {lab_wire.sym} 70 420 3 0 {name=l59 sig_type=std_logic lab=out_div_2}
+C {lab_wire.sym} 90 420 3 0 {name=l60 sig_type=std_logic lab=n_out_div_2}
+C {lab_wire.sym} 110 420 3 0 {name=l62 sig_type=std_logic lab=out_buffer_div_2}
+C {lab_wire.sym} 130 420 3 0 {name=l63 sig_type=std_logic lab=n_out_buffer_div_2}
+C {lab_wire.sym} 200 420 3 0 {name=l64 sig_type=std_logic lab=div_5_Q0}
+C {lab_wire.sym} 220 420 3 0 {name=l65 sig_type=std_logic lab=div_5_nQ0}
+C {lab_wire.sym} 240 420 3 0 {name=l71 sig_type=std_logic lab=div_5_Q1}
+C {lab_wire.sym} 260 420 3 0 {name=l72 sig_type=std_logic lab=div_5_Q1_shift}
+C {lab_wire.sym} 280 420 3 0 {name=l73 sig_type=std_logic lab=div_5_nQ2}
+C {bias_pex_c.sym} -590 210 0 0 {name=x9}
+C {lab_wire.sym} 470 250 0 1 {name=l74 sig_type=std_logic lab=out_to_pad}
+C {capa.sym} 510 310 0 0 {name=C1
+m=1
+value=10p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 510 370 3 0 {name=l84 sig_type=std_logic lab=vss}
+C {noconn.sym} 350 430 3 0 {name=l85}
+C {lab_wire.sym} 350 390 3 0 {name=l86 sig_type=std_logic lab=out_to_buffer}
+C {top_pll_v2_pex_c.sym} 10 250 0 0 {name=x1}
+C {lab_pin.sym} -140 90 1 0 {name=l48 sig_type=std_logic lab=D0_cap}
+C {vsource.sym} -20 -140 0 0 {name=VD1 value=\{vd1\}}
+C {lab_pin.sym} -20 -80 3 0 {name=l61 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -20 -200 1 0 {name=l87 sig_type=std_logic lab=D0_cap}
diff --git a/xschem/test.data b/xschem/test.data
deleted file mode 100644
index c9cde37..0000000
--- a/xschem/test.data
+++ /dev/null
@@ -1,101 +0,0 @@
- 7.00000000e-01 -8.93059159e-08 7.00000000e-01 7.00000000e-01
- 7.01000000e-01 -9.08452852e-08 7.01000000e-01 7.01000000e-01
- 7.02000000e-01 -9.24385447e-08 7.02000000e-01 7.02000000e-01
- 7.03000000e-01 -9.40459956e-08 7.03000000e-01 7.03000000e-01
- 7.04000000e-01 -9.56814959e-08 7.04000000e-01 7.04000000e-01
- 7.05000000e-01 -9.73455368e-08 7.05000000e-01 7.05000000e-01
- 7.06000000e-01 -9.90386085e-08 7.06000000e-01 7.06000000e-01
- 7.07000000e-01 -1.00761227e-07 7.07000000e-01 7.07000000e-01
- 7.08000000e-01 -1.02513882e-07 7.08000000e-01 7.08000000e-01
- 7.09000000e-01 -1.04297110e-07 7.09000000e-01 7.09000000e-01
- 7.10000000e-01 -1.06111443e-07 7.10000000e-01 7.10000000e-01
- 7.11000000e-01 -1.07957415e-07 7.11000000e-01 7.11000000e-01
- 7.12000000e-01 -1.09835552e-07 7.12000000e-01 7.12000000e-01
- 7.13000000e-01 -1.11746436e-07 7.13000000e-01 7.13000000e-01
- 7.14000000e-01 -1.13690603e-07 7.14000000e-01 7.14000000e-01
- 7.15000000e-01 -1.15668634e-07 7.15000000e-01 7.15000000e-01
- 7.16000000e-01 -1.17681129e-07 7.16000000e-01 7.16000000e-01
- 7.17000000e-01 -1.19728657e-07 7.17000000e-01 7.17000000e-01
- 7.18000000e-01 -1.21811839e-07 7.18000000e-01 7.18000000e-01
- 7.19000000e-01 -1.23931259e-07 7.19000000e-01 7.19000000e-01
- 7.20000000e-01 -1.26087554e-07 7.20000000e-01 7.20000000e-01
- 7.21000000e-01 -1.28281358e-07 7.21000000e-01 7.21000000e-01
- 7.22000000e-01 -1.30513286e-07 7.22000000e-01 7.22000000e-01
- 7.23000000e-01 -1.32784003e-07 7.23000000e-01 7.23000000e-01
- 7.24000000e-01 -1.35094165e-07 7.24000000e-01 7.24000000e-01
- 7.25000000e-01 -1.37444453e-07 7.25000000e-01 7.25000000e-01
- 7.26000000e-01 -1.39835535e-07 7.26000000e-01 7.26000000e-01
- 7.27000000e-01 -1.42268085e-07 7.27000000e-01 7.27000000e-01
- 7.28000000e-01 -1.44742842e-07 7.28000000e-01 7.28000000e-01
- 7.29000000e-01 -1.47260486e-07 7.29000000e-01 7.29000000e-01
- 7.30000000e-01 -1.49821761e-07 7.30000000e-01 7.30000000e-01
- 7.31000000e-01 -1.52427364e-07 7.31000000e-01 7.31000000e-01
- 7.32000000e-01 -1.55078077e-07 7.32000000e-01 7.32000000e-01
- 7.33000000e-01 -1.57774611e-07 7.33000000e-01 7.33000000e-01
- 7.34000000e-01 -1.60517775e-07 7.34000000e-01 7.34000000e-01
- 7.35000000e-01 -1.63308337e-07 7.35000000e-01 7.35000000e-01
- 7.36000000e-01 -1.66147061e-07 7.36000000e-01 7.36000000e-01
- 7.37000000e-01 -1.69034765e-07 7.37000000e-01 7.37000000e-01
- 7.38000000e-01 -1.71972266e-07 7.38000000e-01 7.38000000e-01
- 7.39000000e-01 -1.74960357e-07 7.39000000e-01 7.39000000e-01
- 7.40000000e-01 -1.77999888e-07 7.40000000e-01 7.40000000e-01
- 7.41000000e-01 -1.81091703e-07 7.41000000e-01 7.41000000e-01
- 7.42000000e-01 -1.84236664e-07 7.42000000e-01 7.42000000e-01
- 7.43000000e-01 -1.87435634e-07 7.43000000e-01 7.43000000e-01
- 7.44000000e-01 -1.90689493e-07 7.44000000e-01 7.44000000e-01
- 7.45000000e-01 -1.93999127e-07 7.45000000e-01 7.45000000e-01
- 7.46000000e-01 -1.97365464e-07 7.46000000e-01 7.46000000e-01
- 7.47000000e-01 -2.00789378e-07 7.47000000e-01 7.47000000e-01
- 7.48000000e-01 -2.04271837e-07 7.48000000e-01 7.48000000e-01
- 7.49000000e-01 -2.07813739e-07 7.49000000e-01 7.49000000e-01
- 7.50000000e-01 -2.11416073e-07 7.50000000e-01 7.50000000e-01
- 7.51000000e-01 -2.15079797e-07 7.51000000e-01 7.51000000e-01
- 7.52000000e-01 -2.18805863e-07 7.52000000e-01 7.52000000e-01
- 7.53000000e-01 -2.22595278e-07 7.53000000e-01 7.53000000e-01
- 7.54000000e-01 -2.26449036e-07 7.54000000e-01 7.54000000e-01
- 7.55000000e-01 -2.30368144e-07 7.55000000e-01 7.55000000e-01
- 7.56000000e-01 -2.34353630e-07 7.56000000e-01 7.56000000e-01
- 7.57000000e-01 -2.38406548e-07 7.57000000e-01 7.57000000e-01
- 7.58000000e-01 -2.42527913e-07 7.58000000e-01 7.58000000e-01
- 7.59000000e-01 -2.46718795e-07 7.59000000e-01 7.59000000e-01
- 7.60000000e-01 -2.50980278e-07 7.60000000e-01 7.60000000e-01
- 7.61000000e-01 -2.55313430e-07 7.61000000e-01 7.61000000e-01
- 7.62000000e-01 -2.59719344e-07 7.62000000e-01 7.62000000e-01
- 7.63000000e-01 -2.64199148e-07 7.63000000e-01 7.63000000e-01
- 7.64000000e-01 -2.68753946e-07 7.64000000e-01 7.64000000e-01
- 7.65000000e-01 -2.73384860e-07 7.65000000e-01 7.65000000e-01
- 7.66000000e-01 -2.78093044e-07 7.66000000e-01 7.66000000e-01
- 7.67000000e-01 -2.82879650e-07 7.67000000e-01 7.67000000e-01
- 7.68000000e-01 -2.87745826e-07 7.68000000e-01 7.68000000e-01
- 7.69000000e-01 -2.92692776e-07 7.69000000e-01 7.69000000e-01
- 7.70000000e-01 -2.97721660e-07 7.70000000e-01 7.70000000e-01
- 7.71000000e-01 -3.02833688e-07 7.71000000e-01 7.71000000e-01
- 7.72000000e-01 -3.08030053e-07 7.72000000e-01 7.72000000e-01
- 7.73000000e-01 -3.13311974e-07 7.73000000e-01 7.73000000e-01
- 7.74000000e-01 -3.18680710e-07 7.74000000e-01 7.74000000e-01
- 7.75000000e-01 -3.24137468e-07 7.75000000e-01 7.75000000e-01
- 7.76000000e-01 -3.29683509e-07 7.76000000e-01 7.76000000e-01
- 7.77000000e-01 -3.35320078e-07 7.77000000e-01 7.77000000e-01
- 7.78000000e-01 -3.41048451e-07 7.78000000e-01 7.78000000e-01
- 7.79000000e-01 -3.46869908e-07 7.79000000e-01 7.79000000e-01
- 7.80000000e-01 -3.52785731e-07 7.80000000e-01 7.80000000e-01
- 7.81000000e-01 -3.58797218e-07 7.81000000e-01 7.81000000e-01
- 7.82000000e-01 -3.64905663e-07 7.82000000e-01 7.82000000e-01
- 7.83000000e-01 -3.71112381e-07 7.83000000e-01 7.83000000e-01
- 7.84000000e-01 -3.77418703e-07 7.84000000e-01 7.84000000e-01
- 7.85000000e-01 -3.83825919e-07 7.85000000e-01 7.85000000e-01
- 7.86000000e-01 -3.90335390e-07 7.86000000e-01 7.86000000e-01
- 7.87000000e-01 -3.96948455e-07 7.87000000e-01 7.87000000e-01
- 7.88000000e-01 -4.03666461e-07 7.88000000e-01 7.88000000e-01
- 7.89000000e-01 -4.10490750e-07 7.89000000e-01 7.89000000e-01
- 7.90000000e-01 -4.17422681e-07 7.90000000e-01 7.90000000e-01
- 7.91000000e-01 -4.24463629e-07 7.91000000e-01 7.91000000e-01
- 7.92000000e-01 -4.31614946e-07 7.92000000e-01 7.92000000e-01
- 7.93000000e-01 -4.38878017e-07 7.93000000e-01 7.93000000e-01
- 7.94000000e-01 -4.46254218e-07 7.94000000e-01 7.94000000e-01
- 7.95000000e-01 -4.53744916e-07 7.95000000e-01 7.95000000e-01
- 7.96000000e-01 -4.61351506e-07 7.96000000e-01 7.96000000e-01
- 7.97000000e-01 -4.69075369e-07 7.97000000e-01 7.97000000e-01
- 7.98000000e-01 -4.76917893e-07 7.98000000e-01 7.98000000e-01
- 7.99000000e-01 -4.84880471e-07 7.99000000e-01 7.99000000e-01
- 8.00000000e-01 -4.92964482e-07 8.00000000e-01 8.00000000e-01
diff --git a/xschem/top_pll_v1.sch b/xschem/top_pll_v1.sch
new file mode 100644
index 0000000..e0c4c51
--- /dev/null
+++ b/xschem/top_pll_v1.sch
@@ -0,0 +1,158 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -750 -360 -750 -330 { lab=vss}
+N -890 -270 -850 -270 { lab=in_ref}
+N -850 -270 -840 -270 { lab=in_ref}
+N -890 -190 -840 -190 { lab=out_div_by_5}
+N -790 -360 -790 -330 { lab=vdd}
+N -400 -250 -310 -250 { lab=nUp}
+N -400 -210 -310 -210 { lab=Down}
+N -360 -170 -310 -170 { lab=nDown}
+N -360 -290 -310 -290 { lab=Up}
+N 410 -330 410 -300 { lab=vdd}
+N 410 -160 410 -130 { lab=vss}
+N 530 260 570 260 { lab=out_to_div}
+N 330 -190 340 -190 { lab=vco_D0}
+N 230 -230 340 -230 { lab=vco_vctrl}
+N 480 -230 520 -230 { lab=vco_out}
+N -460 -170 -360 -170 { lab=nDown}
+N -460 -210 -400 -210 { lab=Down}
+N -460 -250 -400 -250 { lab=nUp}
+N -460 -290 -360 -290 { lab=Up}
+N -700 -190 -600 -190 { lab=pfd_QB}
+N -530 -360 -530 -330 { lab=vdd}
+N -530 -130 -530 -100 { lab=vss}
+N -890 -190 -890 260 { lab=out_div_by_5}
+N 330 -190 330 -150 { lab=vco_D0}
+N 180 150 180 180 { lab=vdd}
+N -210 -360 -210 -330 { lab=vdd}
+N -180 -360 -180 -330 { lab=vss}
+N -50 -230 -30 -230 { lab=vco_vctrl}
+N -270 -370 -270 -330 { lab=iref_cp}
+N 10 280 90 280 { lab=n_out_by_2}
+N 10 240 90 240 { lab=out_by_2}
+N -60 240 10 240 { lab=out_by_2}
+N -60 280 10 280 { lab=n_out_by_2}
+N -190 150 -190 180 { lab=vss}
+N -150 150 -150 180 { lab=vdd}
+N -90 240 -60 240 { lab=out_by_2}
+N -90 280 -60 280 { lab=n_out_by_2}
+N -890 260 -470 260 { lab=out_div_by_5}
+N 60 -70 60 -40 { lab=vss}
+N 30 -230 90 -230 { lab=vco_vctrl}
+N 90 -230 230 -230 { lab=vco_vctrl}
+N 60 -230 60 -210 { lab=vco_vctrl}
+N 120 -140 160 -140 { lab=lf_vc}
+N 520 -230 580 -230 { lab=vco_out}
+N 620 -330 620 -300 { lab=vdd}
+N 660 -330 660 -300 { lab=vss}
+N 700 -250 740 -250 { lab=out_to_buffer}
+N 700 -210 750 -210 { lab=out_to_div}
+N 870 -210 870 260 { lab=out_to_div}
+N 570 260 750 260 { lab=out_to_div}
+N 640 -160 640 -120 { lab=out_first_buffer}
+N 750 -210 870 -210 { lab=out_to_div}
+N 750 260 870 260 { lab=out_to_div}
+N 230 260 530 260 { lab=out_to_div}
+N -470 260 -250 260 { lab=out_div_by_5}
+N 140 150 140 180 { lab=vss}
+N -640 -300 -640 -270 { lab=pfd_QA}
+N -640 -190 -640 -160 { lab=pfd_QB}
+N -450 -310 -440 -310 { lab=Up}
+N -450 -310 -450 -290 { lab=Up}
+N -450 -270 -440 -270 { lab=nUp}
+N -450 -270 -450 -250 { lab=nUp}
+N -450 -230 -440 -230 { lab=Down}
+N -450 -230 -450 -210 { lab=Down}
+N -450 -190 -440 -190 { lab=nDown}
+N -450 -190 -450 -170 { lab=nDown}
+N -770 -130 -770 -100 { lab=pfd_reset}
+N -700 -270 -600 -270 { lab=pfd_QA}
+N -260 -130 -260 -100 { lab=cp_nswitch}
+N -230 -130 -230 -100 { lab=cp_pswitch}
+N -200 -130 -200 -100 { lab=cp_biasp}
+N -140 -230 -50 -230 { lab=vco_vctrl}
+N -30 -230 30 -230 { lab=vco_vctrl}
+N 160 -320 160 -240 { lab=vco_vctrl}
+N 160 -240 160 -230 { lab=vco_vctrl}
+N 520 -320 520 -230 { lab=vco_out}
+N 370 220 370 260 { lab=out_to_div}
+N 0 200 0 240 { lab=out_by_2}
+N 0 280 0 320 { lab=n_out_by_2}
+N 190 340 190 380 { lab=out_div_2}
+N 170 340 170 380 { lab=n_out_div_2}
+N 150 340 150 380 { lab=out_buffer_div_2}
+N 130 340 130 380 { lab=n_out_buffer_div_2}
+N -150 340 -150 380 { lab=div_5_Q1}
+N -170 340 -170 380 { lab=div_5_Q1_shift}
+N -190 340 -190 380 { lab=div_5_nQ0}
+N -210 340 -210 380 { lab=div_5_Q0}
+N -130 340 -130 380 { lab=div_5_nQ2}
+N -390 260 -390 300 { lab=out_div_by_5}
+N 740 -250 930 -250 { lab=out_to_buffer}
+N 810 -300 810 -250 { lab=out_to_buffer}
+N 970 -330 970 -300 { lab=vdd}
+N 970 -200 970 -170 { lab=vss}
+N 1060 -250 1100 -250 { lab=out_to_pad}
+C {lab_pin.sym} 410 -330 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -130 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -530 -360 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -530 -100 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 180 150 1 0 {name=l45 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -210 -360 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -180 -360 1 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -190 150 3 1 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -150 150 3 1 {name=l25 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 60 -40 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 620 -330 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 660 -330 1 0 {name=l40 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 150 1 0 {name=l12 sig_type=std_logic lab=vss}
+C {iopin.sym} -790 -360 3 0 {name=p1 lab=vdd}
+C {iopin.sym} -750 -360 3 0 {name=p2 lab=vss}
+C {ipin.sym} -890 -270 0 0 {name=p3 lab=in_ref}
+C {iopin.sym} -640 -300 3 0 {name=p4 lab=pfd_QA}
+C {iopin.sym} -640 -160 1 0 {name=p5 lab=pfd_QB}
+C {iopin.sym} -440 -310 0 0 {name=p6 lab=Up}
+C {iopin.sym} -440 -270 0 0 {name=p7 lab=nUp}
+C {iopin.sym} -440 -230 0 0 {name=p8 lab=Down}
+C {iopin.sym} -440 -190 0 0 {name=p9 lab=nDown}
+C {iopin.sym} -770 -100 1 0 {name=p10 lab=pfd_reset}
+C {iopin.sym} -260 -100 1 0 {name=p11 lab=cp_nswitch}
+C {iopin.sym} -230 -100 1 0 {name=p12 lab=cp_pswitch}
+C {iopin.sym} -200 -100 1 0 {name=p13 lab=cp_biasp}
+C {ipin.sym} -270 -370 1 0 {name=p14 lab=iref_cp}
+C {iopin.sym} 160 -140 0 0 {name=p15 lab=lf_vc}
+C {iopin.sym} 330 -150 1 0 {name=p16 lab=vco_D0}
+C {iopin.sym} 160 -320 3 0 {name=p17 lab=vco_vctrl}
+C {iopin.sym} 520 -320 3 0 {name=p18 lab=vco_out}
+C {iopin.sym} 640 -120 1 0 {name=p19 lab=out_first_buffer}
+C {iopin.sym} 810 -300 3 0 {name=p20 lab=out_to_buffer}
+C {iopin.sym} 370 220 3 0 {name=p21 lab=out_to_div}
+C {iopin.sym} 0 200 3 0 {name=p22 lab=out_by_2}
+C {iopin.sym} 0 320 1 0 {name=p23 lab=n_out_by_2}
+C {iopin.sym} 190 380 1 0 {name=p24 lab=out_div_2}
+C {iopin.sym} 170 380 1 0 {name=p25 lab=n_out_div_2}
+C {iopin.sym} 150 380 1 0 {name=p26 lab=out_buffer_div_2}
+C {iopin.sym} 130 380 1 0 {name=p27 lab=n_out_buffer_div_2}
+C {iopin.sym} -150 380 1 0 {name=p28 lab=div_5_Q1}
+C {iopin.sym} -170 380 1 0 {name=p29 lab=div_5_Q1_shift}
+C {iopin.sym} -190 380 1 0 {name=p30 lab=div_5_nQ0}
+C {iopin.sym} -210 380 1 0 {name=p31 lab=div_5_Q0}
+C {iopin.sym} -130 380 1 0 {name=p32 lab=div_5_nQ2}
+C {iopin.sym} -390 300 1 0 {name=p33 lab=out_div_by_5}
+C {PFD.sym} -770 -230 0 0 {name=x1}
+C {charge_pump.sym} -230 -230 0 0 {name=x2}
+C {pfd_cp_interface.sym} -530 -230 0 0 {name=x3}
+C {loop_filter.sym} 60 -140 0 0 {name=x4}
+C {csvco.sym} 410 -230 0 0 {name=x5}
+C {ring_osc_buffer.sym} 640 -230 0 0 {name=x6}
+C {div_by_5.sym} -170 260 0 1 {name=x7}
+C {div_by_2.sym} 160 260 0 1 {name=x8}
+C {buffer_salida.sym} 990 -250 0 0 {name=x9}
+C {lab_pin.sym} 970 -330 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 970 -170 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {iopin.sym} 1100 -250 0 0 {name=p35 lab=out_to_pad}
diff --git a/xschem/top_pll_v1.sym b/xschem/top_pll_v1.sym
new file mode 100644
index 0000000..48dfee1
--- /dev/null
+++ b/xschem/top_pll_v1.sym
@@ -0,0 +1,166 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -240 110 20 110 {}
+L 4 -290 -130 -290 -110 {}
+L 4 -350 0 -330 0 {}
+L 4 390 0 410 0 {}
+L 4 -300 90 -300 110 {}
+L 4 -300 90 -240 90 {}
+L 4 -240 90 -240 110 {}
+L 4 -230 90 -230 110 {}
+L 4 -230 90 -150 90 {}
+L 4 -150 90 -150 110 {}
+L 4 -140 90 -140 110 {}
+L 4 -140 90 -80 90 {}
+L 4 -80 90 -80 110 {}
+L 4 -70 90 -70 110 {}
+L 4 -70 90 -50 90 {}
+L 4 -50 90 -50 110 {}
+L 4 -40 90 -40 110 {}
+L 4 -40 90 40 90 {}
+L 4 40 90 40 110 {}
+L 4 20 110 50 110 {}
+L 4 50 110 170 110 {}
+L 4 170 90 170 110 {}
+L 4 50 90 170 90 {}
+L 4 50 90 50 110 {}
+L 4 170 110 300 110 {}
+L 4 180 90 180 110 {}
+L 4 180 90 300 90 {}
+L 4 300 90 300 110 {}
+L 4 300 110 330 110 {}
+L 4 -330 110 -300 110 {}
+L 4 -300 110 -240 110 {}
+L 4 -330 -0 -330 110 {}
+L 4 -330 -110 -330 0 {}
+L 4 -330 -110 330 -110 {}
+L 4 390 -110 390 110 {}
+L 4 -240 -110 -240 -90 {}
+L 4 -240 -90 -120 -90 {}
+L 4 -120 -110 -120 -90 {}
+L 4 -320 70 -320 110 {}
+L 4 -320 70 320 70 {}
+L 4 380 70 380 110 {}
+L 4 320 90 320 110 {}
+L 4 320 90 360 90 {}
+L 4 360 90 360 110 {}
+L 4 330 110 390 110 {}
+L 4 320 70 380 70 {}
+L 4 330 -110 390 -110 {}
+L 4 -210 -130 -210 -110 {}
+L 7 230 -130 230 -110 {}
+L 7 170 -130 170 -110 {}
+L 7 -10 110 -10 130 {}
+L 7 -30 110 -30 130 {}
+L 7 -220 110 -220 130 {}
+L 7 -250 110 -250 130 {}
+L 7 -200 110 -200 130 {}
+L 7 -180 110 -180 130 {}
+L 7 -160 110 -160 130 {}
+L 7 -270 110 -270 130 {}
+L 7 -60 110 -60 130 {}
+L 7 10 110 10 130 {}
+L 7 -90 110 -90 130 {}
+L 7 -110 110 -110 130 {}
+L 7 -290 110 -290 130 {}
+L 7 -130 110 -130 130 {}
+L 7 140 110 140 130 {}
+L 7 30 110 30 130 {}
+L 7 290 110 290 130 {}
+L 7 160 110 160 130 {}
+L 7 210 110 210 130 {}
+L 7 250 110 250 130 {}
+L 7 230 110 230 130 {}
+L 7 100 110 100 130 {}
+L 7 120 110 120 130 {}
+L 7 190 110 190 130 {}
+L 7 80 110 80 130 {}
+L 7 270 110 270 130 {}
+L 7 60 110 60 130 {}
+L 7 340 110 340 130 {}
+B 5 -292.5 -132.5 -287.5 -127.5 {name=iref_cp dir=in }
+B 5 227.5 -132.5 232.5 -127.5 {name=vss dir=inout }
+B 5 167.5 -132.5 172.5 -127.5 {name=vdd dir=inout }
+B 5 -12.5 127.5 -7.5 132.5 {name=vco_out dir=inout }
+B 5 -32.5 127.5 -27.5 132.5 {name=vco_vctrl dir=inout }
+B 5 -222.5 127.5 -217.5 132.5 {name=Up dir=inout }
+B 5 -252.5 127.5 -247.5 132.5 {name=pfd_QA dir=inout }
+B 5 -202.5 127.5 -197.5 132.5 {name=nUp dir=inout }
+B 5 -352.5 -2.5 -347.5 2.5 {name=in_ref dir=in }
+B 5 407.5 -2.5 412.5 2.5 {name=out_to_pad dir=out }
+B 5 -182.5 127.5 -177.5 132.5 {name=Down dir=inout }
+B 5 -162.5 127.5 -157.5 132.5 {name=nDown dir=inout }
+B 5 -272.5 127.5 -267.5 132.5 {name=pfd_QB dir=inout }
+B 5 -212.5 -132.5 -207.5 -127.5 {name=vco_D0 dir=in}
+B 5 -62.5 127.5 -57.5 132.5 {name=lf_vc dir=inout }
+B 5 7.5 127.5 12.5 132.5 {name=out_first_buffer dir=inout }
+B 5 -92.5 127.5 -87.5 132.5 {name=cp_biasp dir=inout }
+B 5 -112.5 127.5 -107.5 132.5 {name=cp_pswitch dir=inout }
+B 5 -292.5 127.5 -287.5 132.5 {name=pfd_reset dir=inout }
+B 5 -132.5 127.5 -127.5 132.5 {name=cp_nswitch dir=inout }
+B 5 137.5 127.5 142.5 132.5 {name=out_by_2 dir=inout }
+B 5 27.5 127.5 32.5 132.5 {name=out_to_div dir=inout }
+B 5 287.5 127.5 292.5 132.5 {name=out_div_by_5 dir=inout }
+B 5 157.5 127.5 162.5 132.5 {name=n_out_by_2 dir=inout }
+B 5 207.5 127.5 212.5 132.5 {name=div_5_nQ0 dir=inout }
+B 5 247.5 127.5 252.5 132.5 {name=div_5_Q1_shift dir=inout }
+B 5 227.5 127.5 232.5 132.5 {name=div_5_Q1 dir=inout }
+B 5 97.5 127.5 102.5 132.5 {name=n_out_buffer_div_2 dir=inout }
+B 5 117.5 127.5 122.5 132.5 {name=out_buffer_div_2 dir=inout }
+B 5 187.5 127.5 192.5 132.5 {name=div_5_Q0 dir=inout }
+B 5 77.5 127.5 82.5 132.5 {name=n_out_div_2 dir=inout }
+B 5 267.5 127.5 272.5 132.5 {name=div_5_nQ2 dir=inout }
+B 5 57.5 127.5 62.5 132.5 {name=out_div_2 dir=inout }
+B 5 337.5 127.5 342.5 132.5 {name=out_to_buffer dir=inout }
+T {@symname} -30 -10 0 0 0.3 0.3 {}
+T {@name} -15 -92 0 0 0.2 0.2 {}
+T {iref_cp} -296 -145 1 0 0.2 0.2 {}
+T {vss} 213.5 -130 3 1 0.2 0.2 {}
+T {vdd} 153.5 -132.5 3 1 0.2 0.2 {}
+T {vco_out} -22.5 112.5 3 1 0.2 0.2 {}
+T {vco_vctrl} -32.5 160 1 1 0.2 0.2 {}
+T {Up} -235 132.5 3 0 0.2 0.2 {}
+T {pfd_QA} -252.5 150 1 1 0.2 0.2 {}
+T {nUp} -215 132.5 3 0 0.2 0.2 {}
+T {in_ref} -325 -12.5 0 0 0.2 0.2 {}
+T {out_to_pad} 447.5 -12.5 0 1 0.2 0.2 {}
+T {Down} -195 140 3 0 0.2 0.2 {}
+T {nDown} -175 147.5 3 0 0.2 0.2 {}
+T {pfd_QB} -272.5 150 1 1 0.2 0.2 {}
+T {vco_D0} -227.5 -150 3 1 0.2 0.2 {}
+T {lf_vc} -62.5 135 1 1 0.2 0.2 {}
+T {out_first_buffer} 7.5 190 1 1 0.2 0.2 {}
+T {cp_biasp} -92.5 157.5 1 1 0.2 0.2 {}
+T {cp_pswitch} -112.5 170 1 1 0.2 0.2 {}
+T {pfd_reset} -292.5 160 1 1 0.2 0.2 {}
+T {cp_nswitch} -132.5 170 1 1 0.2 0.2 {}
+T {out_by_2} 137.5 160 1 1 0.2 0.2 {}
+T {out_to_div} 27.5 165 1 1 0.2 0.2 {}
+T {out_div_by_5} 287.5 180 1 1 0.2 0.2 {}
+T {n_out_by_2} 147.5 112.5 3 1 0.2 0.2 {}
+T {div_5_nQ0} 207.5 167.5 1 1 0.2 0.2 {}
+T {div_5_Q1_shift} 247.5 190 1 1 0.2 0.2 {}
+T {div_5_Q1} 227.5 160 1 1 0.2 0.2 {}
+T {n_out_buffer_div_2} 97.5 210 1 1 0.2 0.2 {}
+T {out_buffer_div_2} 117.5 197.5 1 1 0.2 0.2 {}
+T {div_5_Q0} 187.5 160 1 1 0.2 0.2 {}
+T {n_out_div_2} 77.5 175 1 1 0.2 0.2 {}
+T {div_5_nQ2} 267.5 167.5 1 1 0.2 0.2 {}
+T {out_div_2} 57.5 162.5 1 1 0.2 0.2 {}
+T {PFD} -280 105 2 1 0.2 0.2 {}
+T {Interface} -210 105 2 1 0.2 0.2 {}
+T {CP} -120 105 2 1 0.2 0.2 {}
+T {LF} -65 105 2 1 0.2 0.2 {}
+T {VCO} -10 105 2 1 0.2 0.2 {}
+T {DIV_BY_2} 87.5 105 2 1 0.2 0.2 {}
+T {DIV_BY_5} 212.5 105 2 1 0.2 0.2 {}
+T {Debug} -17.5 85 2 1 0.2 0.2 {}
+T {Config} -197.5 -92.5 2 1 0.2 0.2 {}
+T {out_to_buffer} 337.5 180 1 1 0.2 0.2 {}
diff --git a/xschem/top_pll_v1_pex_c.sym b/xschem/top_pll_v1_pex_c.sym
new file mode 100644
index 0000000..db970bf
--- /dev/null
+++ b/xschem/top_pll_v1_pex_c.sym
@@ -0,0 +1,166 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
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+B 5 -252.5 127.5 -247.5 132.5 {name=pfd_QA dir=inout }
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+B 5 7.5 127.5 12.5 132.5 {name=out_first_buffer dir=inout }
+B 5 -92.5 127.5 -87.5 132.5 {name=cp_biasp dir=inout }
+B 5 -112.5 127.5 -107.5 132.5 {name=cp_pswitch dir=inout }
+B 5 -292.5 127.5 -287.5 132.5 {name=pfd_reset dir=inout }
+B 5 -132.5 127.5 -127.5 132.5 {name=cp_nswitch dir=inout }
+B 5 137.5 127.5 142.5 132.5 {name=out_by_2 dir=inout }
+B 5 27.5 127.5 32.5 132.5 {name=out_to_div dir=inout }
+B 5 287.5 127.5 292.5 132.5 {name=out_div_by_5 dir=inout }
+B 5 157.5 127.5 162.5 132.5 {name=n_out_by_2 dir=inout }
+B 5 207.5 127.5 212.5 132.5 {name=div_5_nQ0 dir=inout }
+B 5 247.5 127.5 252.5 132.5 {name=div_5_Q1_shift dir=inout }
+B 5 227.5 127.5 232.5 132.5 {name=div_5_Q1 dir=inout }
+B 5 97.5 127.5 102.5 132.5 {name=n_out_buffer_div_2 dir=inout }
+B 5 117.5 127.5 122.5 132.5 {name=out_buffer_div_2 dir=inout }
+B 5 187.5 127.5 192.5 132.5 {name=div_5_Q0 dir=inout }
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+B 5 267.5 127.5 272.5 132.5 {name=div_5_nQ2 dir=inout }
+B 5 57.5 127.5 62.5 132.5 {name=out_div_2 dir=inout }
+B 5 337.5 127.5 342.5 132.5 {name=out_to_buffer dir=inout }
+T {@symname} -30 -10 0 0 0.3 0.3 {}
+T {@name} -15 -92 0 0 0.2 0.2 {}
+T {iref_cp} -296 -145 1 0 0.2 0.2 {}
+T {vss} 213.5 -130 3 1 0.2 0.2 {}
+T {vdd} 153.5 -132.5 3 1 0.2 0.2 {}
+T {vco_out} -22.5 112.5 3 1 0.2 0.2 {}
+T {vco_vctrl} -32.5 160 1 1 0.2 0.2 {}
+T {Up} -235 132.5 3 0 0.2 0.2 {}
+T {pfd_QA} -252.5 150 1 1 0.2 0.2 {}
+T {nUp} -215 132.5 3 0 0.2 0.2 {}
+T {in_ref} -325 -12.5 0 0 0.2 0.2 {}
+T {out_to_pad} 447.5 -12.5 0 1 0.2 0.2 {}
+T {Down} -195 140 3 0 0.2 0.2 {}
+T {nDown} -175 147.5 3 0 0.2 0.2 {}
+T {pfd_QB} -272.5 150 1 1 0.2 0.2 {}
+T {vco_D0} -227.5 -150 3 1 0.2 0.2 {}
+T {lf_vc} -62.5 135 1 1 0.2 0.2 {}
+T {out_first_buffer} 7.5 190 1 1 0.2 0.2 {}
+T {cp_biasp} -92.5 157.5 1 1 0.2 0.2 {}
+T {cp_pswitch} -112.5 170 1 1 0.2 0.2 {}
+T {pfd_reset} -292.5 160 1 1 0.2 0.2 {}
+T {cp_nswitch} -132.5 170 1 1 0.2 0.2 {}
+T {out_by_2} 137.5 160 1 1 0.2 0.2 {}
+T {out_to_div} 27.5 165 1 1 0.2 0.2 {}
+T {out_div_by_5} 287.5 180 1 1 0.2 0.2 {}
+T {n_out_by_2} 147.5 112.5 3 1 0.2 0.2 {}
+T {div_5_nQ0} 207.5 167.5 1 1 0.2 0.2 {}
+T {div_5_Q1_shift} 247.5 190 1 1 0.2 0.2 {}
+T {div_5_Q1} 227.5 160 1 1 0.2 0.2 {}
+T {n_out_buffer_div_2} 97.5 210 1 1 0.2 0.2 {}
+T {out_buffer_div_2} 117.5 197.5 1 1 0.2 0.2 {}
+T {div_5_Q0} 187.5 160 1 1 0.2 0.2 {}
+T {n_out_div_2} 77.5 175 1 1 0.2 0.2 {}
+T {div_5_nQ2} 267.5 167.5 1 1 0.2 0.2 {}
+T {out_div_2} 57.5 162.5 1 1 0.2 0.2 {}
+T {PFD} -280 105 2 1 0.2 0.2 {}
+T {Interface} -210 105 2 1 0.2 0.2 {}
+T {CP} -120 105 2 1 0.2 0.2 {}
+T {LF} -65 105 2 1 0.2 0.2 {}
+T {VCO} -10 105 2 1 0.2 0.2 {}
+T {DIV_BY_2} 87.5 105 2 1 0.2 0.2 {}
+T {DIV_BY_5} 212.5 105 2 1 0.2 0.2 {}
+T {Debug} -17.5 85 2 1 0.2 0.2 {}
+T {Config} -197.5 -92.5 2 1 0.2 0.2 {}
+T {out_to_buffer} 337.5 180 1 1 0.2 0.2 {}
diff --git a/xschem/top_pll_v1_pex_no_integration.sch b/xschem/top_pll_v1_pex_no_integration.sch
new file mode 100644
index 0000000..e3b8fe5
--- /dev/null
+++ b/xschem/top_pll_v1_pex_no_integration.sch
@@ -0,0 +1,161 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -750 -360 -750 -330 { lab=vss}
+N -890 -270 -850 -270 { lab=in_ref}
+N -850 -270 -840 -270 { lab=in_ref}
+N -890 -190 -840 -190 { lab=out_div_by_5}
+N -790 -360 -790 -330 { lab=vdd}
+N -400 -250 -310 -250 { lab=nUp}
+N -400 -210 -310 -210 { lab=Down}
+N -360 -170 -310 -170 { lab=nDown}
+N -360 -290 -310 -290 { lab=Up}
+N 410 -330 410 -300 { lab=vdd}
+N 410 -160 410 -130 { lab=vss}
+N 530 260 570 260 { lab=out_to_div}
+N 330 -190 340 -190 { lab=D0_vco}
+N 230 -230 340 -230 { lab=vco_vctrl}
+N 480 -230 520 -230 { lab=vco_out}
+N -460 -170 -360 -170 { lab=nDown}
+N -460 -210 -400 -210 { lab=Down}
+N -460 -250 -400 -250 { lab=nUp}
+N -460 -290 -360 -290 { lab=Up}
+N -700 -190 -600 -190 { lab=pfd_QB}
+N -530 -360 -530 -330 { lab=vdd}
+N -530 -130 -530 -100 { lab=vss}
+N -890 -190 -890 260 { lab=out_div_by_5}
+N 330 -190 330 -150 { lab=D0_vco}
+N 180 150 180 180 { lab=vdd}
+N -210 -360 -210 -330 { lab=vdd}
+N -180 -360 -180 -330 { lab=vss}
+N -50 -230 -30 -230 { lab=vco_vctrl}
+N -270 -370 -270 -330 { lab=iref_cp}
+N 10 280 90 280 { lab=n_out_by_2}
+N 10 240 90 240 { lab=out_by_2}
+N -60 240 10 240 { lab=out_by_2}
+N -60 280 10 280 { lab=n_out_by_2}
+N -190 150 -190 180 { lab=vss}
+N -150 150 -150 180 { lab=vdd}
+N -90 240 -60 240 { lab=out_by_2}
+N -90 280 -60 280 { lab=n_out_by_2}
+N -890 260 -470 260 { lab=out_div_by_5}
+N 60 -70 60 -40 { lab=vss}
+N 30 -230 90 -230 { lab=vco_vctrl}
+N 90 -230 230 -230 { lab=vco_vctrl}
+N 60 -230 60 -210 { lab=vco_vctrl}
+N 120 -140 160 -140 { lab=lf_vc}
+N 520 -230 580 -230 { lab=vco_out}
+N 620 -330 620 -300 { lab=vdd}
+N 660 -330 660 -300 { lab=vss}
+N 1050 -250 1090 -250 { lab=out_to_pad}
+N 700 -210 750 -210 { lab=out_to_div}
+N 870 -210 870 260 { lab=out_to_div}
+N 570 260 750 260 { lab=out_to_div}
+N 640 -160 640 -120 { lab=out_first_buffer}
+N 750 -210 870 -210 { lab=out_to_div}
+N 750 260 870 260 { lab=out_to_div}
+N 230 260 530 260 { lab=out_to_div}
+N -470 260 -250 260 { lab=out_div_by_5}
+N 140 150 140 180 { lab=vss}
+N -640 -300 -640 -270 { lab=pfd_QA}
+N -640 -190 -640 -160 { lab=pfd_QB}
+N -450 -310 -440 -310 { lab=Up}
+N -450 -310 -450 -290 { lab=Up}
+N -450 -270 -440 -270 { lab=nUp}
+N -450 -270 -450 -250 { lab=nUp}
+N -450 -230 -440 -230 { lab=Down}
+N -450 -230 -450 -210 { lab=Down}
+N -450 -190 -440 -190 { lab=nDown}
+N -450 -190 -450 -170 { lab=nDown}
+N -770 -130 -770 -100 { lab=pfd_reset}
+N -700 -270 -600 -270 { lab=pfd_QA}
+N -260 -130 -260 -100 { lab=cp_nswitch}
+N -230 -130 -230 -100 { lab=cp_pswitch}
+N -200 -130 -200 -100 { lab=cp_biasp}
+N -140 -230 -50 -230 { lab=vco_vctrl}
+N -30 -230 30 -230 { lab=vco_vctrl}
+N 160 -320 160 -240 { lab=vco_vctrl}
+N 160 -240 160 -230 { lab=vco_vctrl}
+N 520 -320 520 -230 { lab=vco_out}
+N 370 220 370 260 { lab=out_to_div}
+N 0 200 0 240 { lab=out_by_2}
+N 0 280 0 320 { lab=n_out_by_2}
+N 190 340 190 380 { lab=out_div_2}
+N 170 340 170 380 { lab=n_out_div_2}
+N 150 340 150 380 { lab=out_buffer_div_2}
+N 130 340 130 380 { lab=n_out_buffer_div_2}
+N -150 340 -150 380 { lab=div_5_Q1}
+N -170 340 -170 380 { lab=div_5_Q1_shift}
+N -190 340 -190 380 { lab=div_5_nQ0}
+N -210 340 -210 380 { lab=div_5_Q0}
+N -130 340 -130 380 { lab=div_5_nQ2}
+N -390 260 -390 300 { lab=out_div_by_5}
+N 960 -200 960 -170 { lab=vss}
+N 960 -330 960 -300 { lab=vdd}
+N 700 -250 920 -250 { lab=out_to_buffer}
+N 810 -340 810 -250 { lab=out_to_buffer}
+N -20 -140 0 -140 { lab=D0_vco}
+N -20 -190 -20 -140 { lab=D0_vco}
+N -30 -190 -20 -190 { lab=D0_vco}
+C {lab_pin.sym} 410 -330 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -130 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -530 -360 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -530 -100 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 180 150 1 0 {name=l45 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -210 -360 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -180 -360 1 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -190 150 3 1 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -150 150 3 1 {name=l25 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 60 -40 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 620 -330 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 660 -330 1 0 {name=l40 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 150 1 0 {name=l12 sig_type=std_logic lab=vss}
+C {iopin.sym} -790 -360 3 0 {name=p1 lab=vdd}
+C {iopin.sym} -750 -360 3 0 {name=p2 lab=vss}
+C {ipin.sym} -890 -270 0 0 {name=p3 lab=in_ref}
+C {iopin.sym} -640 -300 3 0 {name=p4 lab=pfd_QA}
+C {iopin.sym} -640 -160 1 0 {name=p5 lab=pfd_QB}
+C {iopin.sym} -440 -310 0 0 {name=p6 lab=Up}
+C {iopin.sym} -440 -270 0 0 {name=p7 lab=nUp}
+C {iopin.sym} -440 -230 0 0 {name=p8 lab=Down}
+C {iopin.sym} -440 -190 0 0 {name=p9 lab=nDown}
+C {iopin.sym} -770 -100 1 0 {name=p10 lab=pfd_reset}
+C {iopin.sym} -260 -100 1 0 {name=p11 lab=cp_nswitch}
+C {iopin.sym} -230 -100 1 0 {name=p12 lab=cp_pswitch}
+C {iopin.sym} -200 -100 1 0 {name=p13 lab=cp_biasp}
+C {ipin.sym} -270 -370 1 0 {name=p14 lab=iref_cp}
+C {iopin.sym} 160 -140 0 0 {name=p15 lab=lf_vc}
+C {iopin.sym} 330 -150 1 0 {name=p16 lab=D0_vco}
+C {iopin.sym} 160 -320 3 0 {name=p17 lab=vco_vctrl}
+C {iopin.sym} 520 -320 3 0 {name=p18 lab=vco_out}
+C {iopin.sym} 640 -120 1 0 {name=p19 lab=out_first_buffer}
+C {opin.sym} 1090 -250 0 0 {name=p20 lab=out_to_pad}
+C {iopin.sym} 370 220 3 0 {name=p21 lab=out_to_div}
+C {iopin.sym} 0 200 3 0 {name=p22 lab=out_by_2}
+C {iopin.sym} 0 320 1 0 {name=p23 lab=n_out_by_2}
+C {iopin.sym} 190 380 1 0 {name=p24 lab=out_div_2}
+C {iopin.sym} 170 380 1 0 {name=p25 lab=n_out_div_2}
+C {iopin.sym} 150 380 1 0 {name=p26 lab=out_buffer_div_2}
+C {iopin.sym} 130 380 1 0 {name=p27 lab=n_out_buffer_div_2}
+C {iopin.sym} -150 380 1 0 {name=p28 lab=div_5_Q1}
+C {iopin.sym} -170 380 1 0 {name=p29 lab=div_5_Q1_shift}
+C {iopin.sym} -190 380 1 0 {name=p30 lab=div_5_nQ0}
+C {iopin.sym} -210 380 1 0 {name=p31 lab=div_5_Q0}
+C {iopin.sym} -130 380 1 0 {name=p32 lab=div_5_nQ2}
+C {iopin.sym} -390 300 1 0 {name=p33 lab=out_div_by_5}
+C {PFD_pex_c.sym} -770 -230 0 0 {name=x1}
+C {charge_pump_pex_c.sym} -230 -230 0 0 {name=x2}
+C {csvco_pex_c.sym} 410 -230 0 0 {name=x3}
+C {div_by_5_pex_c.sym} -170 260 0 1 {name=x5}
+C {pfd_cp_interface_pex_c.sym} -530 -230 0 0 {name=x7}
+C {ring_osc_buffer_pex_c.sym} 640 -230 0 0 {name=x8}
+C {div_by_2_pex_c.sym} 160 260 0 1 {name=x4}
+C {buffer_salida_pex_c.sym} 980 -250 0 0 {name=x9}
+C {lab_pin.sym} 960 -170 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 960 -330 1 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 810 -340 3 0 {name=p34 lab=out_to_buffer}
+C {loop_filter_v2.sym} 60 -140 0 0 {name=x6}
+C {iopin.sym} -30 -190 2 0 {name=p35 lab=D0_cap}
diff --git a/xschem/top_pll_v1_pex_no_integration.sym b/xschem/top_pll_v1_pex_no_integration.sym
new file mode 100644
index 0000000..3fee5b2
--- /dev/null
+++ b/xschem/top_pll_v1_pex_no_integration.sym
@@ -0,0 +1,166 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -240 110 20 110 {}
+L 4 -290 -130 -290 -110 {}
+L 4 -350 0 -330 0 {}
+L 4 390 0 410 0 {}
+L 4 -300 90 -300 110 {}
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+L 4 -140 90 -80 90 {}
+L 4 -80 90 -80 110 {}
+L 4 -70 90 -70 110 {}
+L 4 -70 90 -50 90 {}
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+L 4 -40 90 -40 110 {}
+L 4 -40 90 40 90 {}
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+L 4 170 110 300 110 {}
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+L 4 180 90 300 90 {}
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+L 4 300 110 330 110 {}
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+L 4 -300 110 -240 110 {}
+L 4 -330 -0 -330 110 {}
+L 4 -330 -110 -330 0 {}
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+L 4 390 -110 390 110 {}
+L 4 -240 -110 -240 -90 {}
+L 4 -240 -90 -120 -90 {}
+L 4 -120 -110 -120 -90 {}
+L 4 -320 70 -320 110 {}
+L 4 -320 70 320 70 {}
+L 4 380 70 380 110 {}
+L 4 320 90 320 110 {}
+L 4 320 90 360 90 {}
+L 4 360 90 360 110 {}
+L 4 330 110 390 110 {}
+L 4 320 70 380 70 {}
+L 4 330 -110 390 -110 {}
+L 7 230 -130 230 -110 {}
+L 7 170 -130 170 -110 {}
+L 7 -10 110 -10 130 {}
+L 7 -30 110 -30 130 {}
+L 7 -220 110 -220 130 {}
+L 7 -250 110 -250 130 {}
+L 7 -200 110 -200 130 {}
+L 7 -180 110 -180 130 {}
+L 7 -160 110 -160 130 {}
+L 7 -270 110 -270 130 {}
+L 7 -210 -130 -210 -110 {}
+L 7 -60 110 -60 130 {}
+L 7 10 110 10 130 {}
+L 7 -90 110 -90 130 {}
+L 7 -110 110 -110 130 {}
+L 7 -290 110 -290 130 {}
+L 7 -130 110 -130 130 {}
+L 7 140 110 140 130 {}
+L 7 30 110 30 130 {}
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+L 7 160 110 160 130 {}
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+L 7 230 110 230 130 {}
+L 7 100 110 100 130 {}
+L 7 120 110 120 130 {}
+L 7 190 110 190 130 {}
+L 7 80 110 80 130 {}
+L 7 270 110 270 130 {}
+L 7 60 110 60 130 {}
+L 7 340 110 340 130 {}
+B 5 -292.5 -132.5 -287.5 -127.5 {name=iref_cp dir=in }
+B 5 227.5 -132.5 232.5 -127.5 {name=vss dir=inout }
+B 5 167.5 -132.5 172.5 -127.5 {name=vdd dir=inout }
+B 5 -12.5 127.5 -7.5 132.5 {name=vco_out dir=inout }
+B 5 -32.5 127.5 -27.5 132.5 {name=vco_vctrl dir=inout }
+B 5 -222.5 127.5 -217.5 132.5 {name=Up dir=inout }
+B 5 -252.5 127.5 -247.5 132.5 {name=pfd_QA dir=inout }
+B 5 -202.5 127.5 -197.5 132.5 {name=nUp dir=inout }
+B 5 -352.5 -2.5 -347.5 2.5 {name=in_ref dir=in }
+B 5 407.5 -2.5 412.5 2.5 {name=out_to_pad dir=out }
+B 5 -182.5 127.5 -177.5 132.5 {name=Down dir=inout }
+B 5 -162.5 127.5 -157.5 132.5 {name=nDown dir=inout }
+B 5 -272.5 127.5 -267.5 132.5 {name=pfd_QB dir=inout }
+B 5 -212.5 -132.5 -207.5 -127.5 {name=vco_D0 dir=inout }
+B 5 -62.5 127.5 -57.5 132.5 {name=lf_vc dir=inout }
+B 5 7.5 127.5 12.5 132.5 {name=out_first_buffer dir=inout }
+B 5 -92.5 127.5 -87.5 132.5 {name=cp_biasp dir=inout }
+B 5 -112.5 127.5 -107.5 132.5 {name=cp_pswitch dir=inout }
+B 5 -292.5 127.5 -287.5 132.5 {name=pfd_reset dir=inout }
+B 5 -132.5 127.5 -127.5 132.5 {name=cp_nswitch dir=inout }
+B 5 137.5 127.5 142.5 132.5 {name=out_by_2 dir=inout }
+B 5 27.5 127.5 32.5 132.5 {name=out_to_div dir=inout }
+B 5 287.5 127.5 292.5 132.5 {name=out_div_by_5 dir=inout }
+B 5 157.5 127.5 162.5 132.5 {name=n_out_by_2 dir=inout }
+B 5 207.5 127.5 212.5 132.5 {name=div_5_nQ0 dir=inout }
+B 5 247.5 127.5 252.5 132.5 {name=div_5_Q1_shift dir=inout }
+B 5 227.5 127.5 232.5 132.5 {name=div_5_Q1 dir=inout }
+B 5 97.5 127.5 102.5 132.5 {name=n_out_buffer_div_2 dir=inout }
+B 5 117.5 127.5 122.5 132.5 {name=out_buffer_div_2 dir=inout }
+B 5 187.5 127.5 192.5 132.5 {name=div_5_Q0 dir=inout }
+B 5 77.5 127.5 82.5 132.5 {name=n_out_div_2 dir=inout }
+B 5 267.5 127.5 272.5 132.5 {name=div_5_nQ2 dir=inout }
+B 5 57.5 127.5 62.5 132.5 {name=out_div_2 dir=inout }
+B 5 337.5 127.5 342.5 132.5 {name=out_to_buffer dir=inout }
+T {@symname} -30 -10 0 0 0.3 0.3 {}
+T {@name} -15 -92 0 0 0.2 0.2 {}
+T {iref_cp} -296 -145 1 0 0.2 0.2 {}
+T {vss} 213.5 -130 3 1 0.2 0.2 {}
+T {vdd} 153.5 -132.5 3 1 0.2 0.2 {}
+T {vco_out} -22.5 112.5 3 1 0.2 0.2 {}
+T {vco_vctrl} -32.5 160 1 1 0.2 0.2 {}
+T {Up} -235 132.5 3 0 0.2 0.2 {}
+T {pfd_QA} -252.5 150 1 1 0.2 0.2 {}
+T {nUp} -215 132.5 3 0 0.2 0.2 {}
+T {in_ref} -325 -12.5 0 0 0.2 0.2 {}
+T {out_to_pad} 447.5 -12.5 0 1 0.2 0.2 {}
+T {Down} -195 140 3 0 0.2 0.2 {}
+T {nDown} -175 147.5 3 0 0.2 0.2 {}
+T {pfd_QB} -272.5 150 1 1 0.2 0.2 {}
+T {vco_D0} -227.5 -150 3 1 0.2 0.2 {}
+T {lf_vc} -62.5 135 1 1 0.2 0.2 {}
+T {out_first_buffer} 7.5 190 1 1 0.2 0.2 {}
+T {cp_biasp} -92.5 157.5 1 1 0.2 0.2 {}
+T {cp_pswitch} -112.5 170 1 1 0.2 0.2 {}
+T {pfd_reset} -292.5 160 1 1 0.2 0.2 {}
+T {cp_nswitch} -132.5 170 1 1 0.2 0.2 {}
+T {out_by_2} 137.5 160 1 1 0.2 0.2 {}
+T {out_to_div} 27.5 165 1 1 0.2 0.2 {}
+T {out_div_by_5} 287.5 180 1 1 0.2 0.2 {}
+T {n_out_by_2} 147.5 112.5 3 1 0.2 0.2 {}
+T {div_5_nQ0} 207.5 167.5 1 1 0.2 0.2 {}
+T {div_5_Q1_shift} 247.5 190 1 1 0.2 0.2 {}
+T {div_5_Q1} 227.5 160 1 1 0.2 0.2 {}
+T {n_out_buffer_div_2} 97.5 210 1 1 0.2 0.2 {}
+T {out_buffer_div_2} 117.5 197.5 1 1 0.2 0.2 {}
+T {div_5_Q0} 187.5 160 1 1 0.2 0.2 {}
+T {n_out_div_2} 77.5 175 1 1 0.2 0.2 {}
+T {div_5_nQ2} 267.5 167.5 1 1 0.2 0.2 {}
+T {out_div_2} 57.5 162.5 1 1 0.2 0.2 {}
+T {PFD} -280 105 2 1 0.2 0.2 {}
+T {Interface} -210 105 2 1 0.2 0.2 {}
+T {CP} -120 105 2 1 0.2 0.2 {}
+T {LF} -65 105 2 1 0.2 0.2 {}
+T {VCO} -10 105 2 1 0.2 0.2 {}
+T {DIV_BY_2} 87.5 105 2 1 0.2 0.2 {}
+T {DIV_BY_5} 212.5 105 2 1 0.2 0.2 {}
+T {Debug} -17.5 85 2 1 0.2 0.2 {}
+T {Config} -197.5 -92.5 2 1 0.2 0.2 {}
+T {out_to_buffer} 337.5 180 1 1 0.2 0.2 {}
diff --git a/xschem/top_pll_v2.sch b/xschem/top_pll_v2.sch
new file mode 100644
index 0000000..c31b438
--- /dev/null
+++ b/xschem/top_pll_v2.sch
@@ -0,0 +1,162 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -750 -360 -750 -330 { lab=vss}
+N -890 -270 -850 -270 { lab=in_ref}
+N -850 -270 -840 -270 { lab=in_ref}
+N -890 -190 -840 -190 { lab=out_div_by_5}
+N -790 -360 -790 -330 { lab=vdd}
+N -400 -250 -310 -250 { lab=nUp}
+N -400 -210 -310 -210 { lab=Down}
+N -360 -170 -310 -170 { lab=nDown}
+N -360 -290 -310 -290 { lab=Up}
+N 410 -330 410 -300 { lab=vdd}
+N 410 -160 410 -130 { lab=vss}
+N 530 260 570 260 { lab=out_to_div}
+N 330 -190 340 -190 { lab=vco_D0}
+N 230 -230 340 -230 { lab=vco_vctrl}
+N 480 -230 520 -230 { lab=vco_out}
+N -460 -170 -360 -170 { lab=nDown}
+N -460 -210 -400 -210 { lab=Down}
+N -460 -250 -400 -250 { lab=nUp}
+N -460 -290 -360 -290 { lab=Up}
+N -700 -190 -600 -190 { lab=pfd_QB}
+N -530 -360 -530 -330 { lab=vdd}
+N -530 -130 -530 -100 { lab=vss}
+N -890 -190 -890 260 { lab=out_div_by_5}
+N 330 -190 330 -150 { lab=vco_D0}
+N 180 150 180 180 { lab=vdd}
+N -210 -360 -210 -330 { lab=vdd}
+N -180 -360 -180 -330 { lab=vss}
+N -50 -230 -30 -230 { lab=vco_vctrl}
+N -270 -370 -270 -330 { lab=iref_cp}
+N 10 280 90 280 { lab=n_out_by_2}
+N 10 240 90 240 { lab=out_by_2}
+N -60 240 10 240 { lab=out_by_2}
+N -60 280 10 280 { lab=n_out_by_2}
+N -190 150 -190 180 { lab=vss}
+N -150 150 -150 180 { lab=vdd}
+N -90 240 -60 240 { lab=out_by_2}
+N -90 280 -60 280 { lab=n_out_by_2}
+N -890 260 -470 260 { lab=out_div_by_5}
+N 60 -70 60 -40 { lab=vss}
+N 30 -230 90 -230 { lab=vco_vctrl}
+N 90 -230 230 -230 { lab=vco_vctrl}
+N 60 -230 60 -210 { lab=vco_vctrl}
+N 120 -140 160 -140 { lab=lf_vc}
+N 520 -230 580 -230 { lab=vco_out}
+N 620 -330 620 -300 { lab=vdd}
+N 660 -330 660 -300 { lab=vss}
+N 700 -250 740 -250 { lab=out_to_buffer}
+N 700 -210 750 -210 { lab=out_to_div}
+N 870 -210 870 260 { lab=out_to_div}
+N 570 260 750 260 { lab=out_to_div}
+N 640 -160 640 -120 { lab=out_first_buffer}
+N 750 -210 870 -210 { lab=out_to_div}
+N 750 260 870 260 { lab=out_to_div}
+N 230 260 530 260 { lab=out_to_div}
+N -470 260 -250 260 { lab=out_div_by_5}
+N 140 150 140 180 { lab=vss}
+N -640 -300 -640 -270 { lab=pfd_QA}
+N -640 -190 -640 -160 { lab=pfd_QB}
+N -450 -310 -440 -310 { lab=Up}
+N -450 -310 -450 -290 { lab=Up}
+N -450 -270 -440 -270 { lab=nUp}
+N -450 -270 -450 -250 { lab=nUp}
+N -450 -230 -440 -230 { lab=Down}
+N -450 -230 -450 -210 { lab=Down}
+N -450 -190 -440 -190 { lab=nDown}
+N -450 -190 -450 -170 { lab=nDown}
+N -770 -130 -770 -100 { lab=pfd_reset}
+N -700 -270 -600 -270 { lab=pfd_QA}
+N -260 -130 -260 -100 { lab=cp_nswitch}
+N -230 -130 -230 -100 { lab=cp_pswitch}
+N -200 -130 -200 -100 { lab=cp_biasp}
+N -140 -230 -50 -230 { lab=vco_vctrl}
+N -30 -230 30 -230 { lab=vco_vctrl}
+N 160 -320 160 -240 { lab=vco_vctrl}
+N 160 -240 160 -230 { lab=vco_vctrl}
+N 520 -320 520 -230 { lab=vco_out}
+N 370 220 370 260 { lab=out_to_div}
+N 0 200 0 240 { lab=out_by_2}
+N 0 280 0 320 { lab=n_out_by_2}
+N 190 340 190 380 { lab=out_div_2}
+N 170 340 170 380 { lab=n_out_div_2}
+N 150 340 150 380 { lab=out_buffer_div_2}
+N 130 340 130 380 { lab=n_out_buffer_div_2}
+N -150 340 -150 380 { lab=div_5_Q1}
+N -170 340 -170 380 { lab=div_5_Q1_shift}
+N -190 340 -190 380 { lab=div_5_nQ0}
+N -210 340 -210 380 { lab=div_5_Q0}
+N -130 340 -130 380 { lab=div_5_nQ2}
+N -390 260 -390 300 { lab=out_div_by_5}
+N 740 -250 930 -250 { lab=out_to_buffer}
+N 810 -300 810 -250 { lab=out_to_buffer}
+N 970 -330 970 -300 { lab=vdd}
+N 970 -200 970 -170 { lab=vss}
+N 1060 -250 1100 -250 { lab=out_to_pad}
+N -40 -170 -20 -170 { lab=D0_cap}
+N -20 -170 -20 -140 { lab=D0_cap}
+N -20 -140 0 -140 { lab=D0_cap}
+C {lab_pin.sym} 410 -330 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -130 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -530 -360 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -530 -100 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 180 150 1 0 {name=l45 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -210 -360 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -180 -360 1 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -190 150 3 1 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -150 150 3 1 {name=l25 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 60 -40 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 620 -330 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 660 -330 1 0 {name=l40 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 150 1 0 {name=l12 sig_type=std_logic lab=vss}
+C {iopin.sym} -790 -360 3 0 {name=p1 lab=vdd}
+C {iopin.sym} -750 -360 3 0 {name=p2 lab=vss}
+C {ipin.sym} -890 -270 0 0 {name=p3 lab=in_ref}
+C {iopin.sym} -640 -300 3 0 {name=p4 lab=pfd_QA}
+C {iopin.sym} -640 -160 1 0 {name=p5 lab=pfd_QB}
+C {iopin.sym} -440 -310 0 0 {name=p6 lab=Up}
+C {iopin.sym} -440 -270 0 0 {name=p7 lab=nUp}
+C {iopin.sym} -440 -230 0 0 {name=p8 lab=Down}
+C {iopin.sym} -440 -190 0 0 {name=p9 lab=nDown}
+C {iopin.sym} -770 -100 1 0 {name=p10 lab=pfd_reset}
+C {iopin.sym} -260 -100 1 0 {name=p11 lab=cp_nswitch}
+C {iopin.sym} -230 -100 1 0 {name=p12 lab=cp_pswitch}
+C {iopin.sym} -200 -100 1 0 {name=p13 lab=cp_biasp}
+C {ipin.sym} -270 -370 1 0 {name=p14 lab=iref_cp}
+C {iopin.sym} 160 -140 0 0 {name=p15 lab=lf_vc}
+C {iopin.sym} 330 -150 1 0 {name=p16 lab=D0_vco}
+C {iopin.sym} 160 -320 3 0 {name=p17 lab=vco_vctrl}
+C {iopin.sym} 520 -320 3 0 {name=p18 lab=vco_out}
+C {iopin.sym} 640 -120 1 0 {name=p19 lab=out_first_buffer}
+C {iopin.sym} 810 -300 3 0 {name=p20 lab=out_to_buffer}
+C {iopin.sym} 370 220 3 0 {name=p21 lab=out_to_div}
+C {iopin.sym} 0 200 3 0 {name=p22 lab=out_by_2}
+C {iopin.sym} 0 320 1 0 {name=p23 lab=n_out_by_2}
+C {iopin.sym} 190 380 1 0 {name=p24 lab=out_div_2}
+C {iopin.sym} 170 380 1 0 {name=p25 lab=n_out_div_2}
+C {iopin.sym} 150 380 1 0 {name=p26 lab=out_buffer_div_2}
+C {iopin.sym} 130 380 1 0 {name=p27 lab=n_out_buffer_div_2}
+C {iopin.sym} -150 380 1 0 {name=p28 lab=div_5_Q1}
+C {iopin.sym} -170 380 1 0 {name=p29 lab=div_5_Q1_shift}
+C {iopin.sym} -190 380 1 0 {name=p30 lab=div_5_nQ0}
+C {iopin.sym} -210 380 1 0 {name=p31 lab=div_5_Q0}
+C {iopin.sym} -130 380 1 0 {name=p32 lab=div_5_nQ2}
+C {iopin.sym} -390 300 1 0 {name=p33 lab=out_div_by_5}
+C {PFD.sym} -770 -230 0 0 {name=x1}
+C {charge_pump.sym} -230 -230 0 0 {name=x2}
+C {pfd_cp_interface.sym} -530 -230 0 0 {name=x3}
+C {csvco.sym} 410 -230 0 0 {name=x5}
+C {ring_osc_buffer.sym} 640 -230 0 0 {name=x6}
+C {div_by_5.sym} -170 260 0 1 {name=x7}
+C {div_by_2.sym} 160 260 0 1 {name=x8}
+C {buffer_salida.sym} 990 -250 0 0 {name=x9}
+C {lab_pin.sym} 970 -330 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 970 -170 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {iopin.sym} 1100 -250 0 0 {name=p35 lab=out_to_pad}
+C {loop_filter_v2.sym} 60 -140 0 0 {name=x4}
+C {ipin.sym} -40 -170 0 0 {name=p34 lab=D0_cap}
diff --git a/xschem/top_pll_v2.sym b/xschem/top_pll_v2.sym
new file mode 100644
index 0000000..ae36f3f
--- /dev/null
+++ b/xschem/top_pll_v2.sym
@@ -0,0 +1,169 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -240 110 20 110 {}
+L 4 -290 -130 -290 -110 {}
+L 4 -350 0 -330 0 {}
+L 4 390 0 410 0 {}
+L 4 -300 90 -300 110 {}
+L 4 -300 90 -240 90 {}
+L 4 -240 90 -240 110 {}
+L 4 -230 90 -230 110 {}
+L 4 -230 90 -150 90 {}
+L 4 -150 90 -150 110 {}
+L 4 -140 90 -140 110 {}
+L 4 -140 90 -80 90 {}
+L 4 -80 90 -80 110 {}
+L 4 -70 90 -70 110 {}
+L 4 -70 90 -50 90 {}
+L 4 -50 90 -50 110 {}
+L 4 -40 90 -40 110 {}
+L 4 -40 90 40 90 {}
+L 4 40 90 40 110 {}
+L 4 20 110 50 110 {}
+L 4 50 110 170 110 {}
+L 4 170 90 170 110 {}
+L 4 50 90 170 90 {}
+L 4 50 90 50 110 {}
+L 4 170 110 300 110 {}
+L 4 180 90 180 110 {}
+L 4 180 90 300 90 {}
+L 4 300 90 300 110 {}
+L 4 300 110 330 110 {}
+L 4 -330 110 -300 110 {}
+L 4 -300 110 -240 110 {}
+L 4 -330 -0 -330 110 {}
+L 4 -330 -110 -330 0 {}
+L 4 -330 -110 330 -110 {}
+L 4 390 -110 390 110 {}
+L 4 -240 -110 -240 -90 {}
+L 4 -240 -90 -120 -90 {}
+L 4 -120 -110 -120 -90 {}
+L 4 -320 70 -320 110 {}
+L 4 -320 70 320 70 {}
+L 4 380 70 380 110 {}
+L 4 320 90 320 110 {}
+L 4 320 90 360 90 {}
+L 4 360 90 360 110 {}
+L 4 330 110 390 110 {}
+L 4 320 70 380 70 {}
+L 4 330 -110 390 -110 {}
+L 4 -210 -130 -210 -110 {}
+L 4 -150 -130 -150 -110 {}
+L 7 230 -130 230 -110 {}
+L 7 170 -130 170 -110 {}
+L 7 -10 110 -10 130 {}
+L 7 -30 110 -30 130 {}
+L 7 -220 110 -220 130 {}
+L 7 -250 110 -250 130 {}
+L 7 -200 110 -200 130 {}
+L 7 -180 110 -180 130 {}
+L 7 -160 110 -160 130 {}
+L 7 -270 110 -270 130 {}
+L 7 -60 110 -60 130 {}
+L 7 10 110 10 130 {}
+L 7 -90 110 -90 130 {}
+L 7 -110 110 -110 130 {}
+L 7 -290 110 -290 130 {}
+L 7 -130 110 -130 130 {}
+L 7 140 110 140 130 {}
+L 7 30 110 30 130 {}
+L 7 290 110 290 130 {}
+L 7 160 110 160 130 {}
+L 7 210 110 210 130 {}
+L 7 250 110 250 130 {}
+L 7 230 110 230 130 {}
+L 7 100 110 100 130 {}
+L 7 120 110 120 130 {}
+L 7 190 110 190 130 {}
+L 7 80 110 80 130 {}
+L 7 270 110 270 130 {}
+L 7 60 110 60 130 {}
+L 7 340 110 340 130 {}
+B 5 -292.5 -132.5 -287.5 -127.5 {name=iref_cp dir=in }
+B 5 227.5 -132.5 232.5 -127.5 {name=vss dir=inout }
+B 5 167.5 -132.5 172.5 -127.5 {name=vdd dir=inout }
+B 5 -12.5 127.5 -7.5 132.5 {name=vco_out dir=inout }
+B 5 -32.5 127.5 -27.5 132.5 {name=vco_vctrl dir=inout }
+B 5 -222.5 127.5 -217.5 132.5 {name=Up dir=inout }
+B 5 -252.5 127.5 -247.5 132.5 {name=pfd_QA dir=inout }
+B 5 -202.5 127.5 -197.5 132.5 {name=nUp dir=inout }
+B 5 -352.5 -2.5 -347.5 2.5 {name=in_ref dir=in }
+B 5 407.5 -2.5 412.5 2.5 {name=out_to_pad dir=out }
+B 5 -182.5 127.5 -177.5 132.5 {name=Down dir=inout }
+B 5 -162.5 127.5 -157.5 132.5 {name=nDown dir=inout }
+B 5 -272.5 127.5 -267.5 132.5 {name=pfd_QB dir=inout }
+B 5 -212.5 -132.5 -207.5 -127.5 {name=D0_vco dir=in}
+B 5 -62.5 127.5 -57.5 132.5 {name=lf_vc dir=inout }
+B 5 7.5 127.5 12.5 132.5 {name=out_first_buffer dir=inout }
+B 5 -92.5 127.5 -87.5 132.5 {name=cp_biasp dir=inout }
+B 5 -112.5 127.5 -107.5 132.5 {name=cp_pswitch dir=inout }
+B 5 -292.5 127.5 -287.5 132.5 {name=pfd_reset dir=inout }
+B 5 -132.5 127.5 -127.5 132.5 {name=cp_nswitch dir=inout }
+B 5 137.5 127.5 142.5 132.5 {name=out_by_2 dir=inout }
+B 5 27.5 127.5 32.5 132.5 {name=out_to_div dir=inout }
+B 5 287.5 127.5 292.5 132.5 {name=out_div_by_5 dir=inout }
+B 5 157.5 127.5 162.5 132.5 {name=n_out_by_2 dir=inout }
+B 5 207.5 127.5 212.5 132.5 {name=div_5_nQ0 dir=inout }
+B 5 247.5 127.5 252.5 132.5 {name=div_5_Q1_shift dir=inout }
+B 5 227.5 127.5 232.5 132.5 {name=div_5_Q1 dir=inout }
+B 5 97.5 127.5 102.5 132.5 {name=n_out_buffer_div_2 dir=inout }
+B 5 117.5 127.5 122.5 132.5 {name=out_buffer_div_2 dir=inout }
+B 5 187.5 127.5 192.5 132.5 {name=div_5_Q0 dir=inout }
+B 5 77.5 127.5 82.5 132.5 {name=n_out_div_2 dir=inout }
+B 5 267.5 127.5 272.5 132.5 {name=div_5_nQ2 dir=inout }
+B 5 57.5 127.5 62.5 132.5 {name=out_div_2 dir=inout }
+B 5 337.5 127.5 342.5 132.5 {name=out_to_buffer dir=inout }
+B 5 -152.5 -132.5 -147.5 -127.5 {name=D0_cap dir=in}
+T {@symname} -30 -10 0 0 0.3 0.3 {}
+T {@name} -15 -92 0 0 0.2 0.2 {}
+T {iref_cp} -296 -145 1 0 0.2 0.2 {}
+T {vss} 213.5 -130 3 1 0.2 0.2 {}
+T {vdd} 153.5 -132.5 3 1 0.2 0.2 {}
+T {vco_out} -22.5 112.5 3 1 0.2 0.2 {}
+T {vco_vctrl} -32.5 160 1 1 0.2 0.2 {}
+T {Up} -235 132.5 3 0 0.2 0.2 {}
+T {pfd_QA} -252.5 150 1 1 0.2 0.2 {}
+T {nUp} -215 132.5 3 0 0.2 0.2 {}
+T {in_ref} -325 -12.5 0 0 0.2 0.2 {}
+T {out_to_pad} 447.5 -12.5 0 1 0.2 0.2 {}
+T {Down} -195 140 3 0 0.2 0.2 {}
+T {nDown} -175 147.5 3 0 0.2 0.2 {}
+T {pfd_QB} -272.5 150 1 1 0.2 0.2 {}
+T {D0_vco} -227.5 -150 3 1 0.2 0.2 {}
+T {lf_vc} -62.5 135 1 1 0.2 0.2 {}
+T {out_first_buffer} 7.5 190 1 1 0.2 0.2 {}
+T {cp_biasp} -92.5 157.5 1 1 0.2 0.2 {}
+T {cp_pswitch} -112.5 170 1 1 0.2 0.2 {}
+T {pfd_reset} -292.5 160 1 1 0.2 0.2 {}
+T {cp_nswitch} -132.5 170 1 1 0.2 0.2 {}
+T {out_by_2} 137.5 160 1 1 0.2 0.2 {}
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+T {Interface} -210 105 2 1 0.2 0.2 {}
+T {CP} -120 105 2 1 0.2 0.2 {}
+T {LF} -65 105 2 1 0.2 0.2 {}
+T {VCO} -10 105 2 1 0.2 0.2 {}
+T {DIV_BY_2} 87.5 105 2 1 0.2 0.2 {}
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+T {Config} -197.5 -92.5 2 1 0.2 0.2 {}
+T {out_to_buffer} 337.5 180 1 1 0.2 0.2 {}
+T {D0_cap} -167.5 -150 3 1 0.2 0.2 {}
diff --git a/xschem/top_pll_v2_pex_c.sym b/xschem/top_pll_v2_pex_c.sym
new file mode 100644
index 0000000..74fb1b8
--- /dev/null
+++ b/xschem/top_pll_v2_pex_c.sym
@@ -0,0 +1,169 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
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+T {@symname} -30 -10 0 0 0.3 0.3 {}
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+T {out_by_2} 137.5 160 1 1 0.2 0.2 {}
+T {out_to_div} 27.5 165 1 1 0.2 0.2 {}
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+T {out_buffer_div_2} 117.5 197.5 1 1 0.2 0.2 {}
+T {div_5_Q0} 187.5 160 1 1 0.2 0.2 {}
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+T {PFD} -280 105 2 1 0.2 0.2 {}
+T {Interface} -210 105 2 1 0.2 0.2 {}
+T {CP} -120 105 2 1 0.2 0.2 {}
+T {LF} -65 105 2 1 0.2 0.2 {}
+T {VCO} -10 105 2 1 0.2 0.2 {}
+T {DIV_BY_2} 87.5 105 2 1 0.2 0.2 {}
+T {DIV_BY_5} 212.5 105 2 1 0.2 0.2 {}
+T {Debug} -17.5 85 2 1 0.2 0.2 {}
+T {Config} -197.5 -92.5 2 1 0.2 0.2 {}
+T {out_to_buffer} 337.5 180 1 1 0.2 0.2 {}
+T {D0_cap} -167.5 -150 3 1 0.2 0.2 {}
diff --git a/xschem/top_pll_v2_pex_no_integration.sym b/xschem/top_pll_v2_pex_no_integration.sym
new file mode 100644
index 0000000..ae36f3f
--- /dev/null
+++ b/xschem/top_pll_v2_pex_no_integration.sym
@@ -0,0 +1,169 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -240 110 20 110 {}
+L 4 -290 -130 -290 -110 {}
+L 4 -350 0 -330 0 {}
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+B 5 -252.5 127.5 -247.5 132.5 {name=pfd_QA dir=inout }
+B 5 -202.5 127.5 -197.5 132.5 {name=nUp dir=inout }
+B 5 -352.5 -2.5 -347.5 2.5 {name=in_ref dir=in }
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+B 5 137.5 127.5 142.5 132.5 {name=out_by_2 dir=inout }
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+B 5 287.5 127.5 292.5 132.5 {name=out_div_by_5 dir=inout }
+B 5 157.5 127.5 162.5 132.5 {name=n_out_by_2 dir=inout }
+B 5 207.5 127.5 212.5 132.5 {name=div_5_nQ0 dir=inout }
+B 5 247.5 127.5 252.5 132.5 {name=div_5_Q1_shift dir=inout }
+B 5 227.5 127.5 232.5 132.5 {name=div_5_Q1 dir=inout }
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+B 5 117.5 127.5 122.5 132.5 {name=out_buffer_div_2 dir=inout }
+B 5 187.5 127.5 192.5 132.5 {name=div_5_Q0 dir=inout }
+B 5 77.5 127.5 82.5 132.5 {name=n_out_div_2 dir=inout }
+B 5 267.5 127.5 272.5 132.5 {name=div_5_nQ2 dir=inout }
+B 5 57.5 127.5 62.5 132.5 {name=out_div_2 dir=inout }
+B 5 337.5 127.5 342.5 132.5 {name=out_to_buffer dir=inout }
+B 5 -152.5 -132.5 -147.5 -127.5 {name=D0_cap dir=in}
+T {@symname} -30 -10 0 0 0.3 0.3 {}
+T {@name} -15 -92 0 0 0.2 0.2 {}
+T {iref_cp} -296 -145 1 0 0.2 0.2 {}
+T {vss} 213.5 -130 3 1 0.2 0.2 {}
+T {vdd} 153.5 -132.5 3 1 0.2 0.2 {}
+T {vco_out} -22.5 112.5 3 1 0.2 0.2 {}
+T {vco_vctrl} -32.5 160 1 1 0.2 0.2 {}
+T {Up} -235 132.5 3 0 0.2 0.2 {}
+T {pfd_QA} -252.5 150 1 1 0.2 0.2 {}
+T {nUp} -215 132.5 3 0 0.2 0.2 {}
+T {in_ref} -325 -12.5 0 0 0.2 0.2 {}
+T {out_to_pad} 447.5 -12.5 0 1 0.2 0.2 {}
+T {Down} -195 140 3 0 0.2 0.2 {}
+T {nDown} -175 147.5 3 0 0.2 0.2 {}
+T {pfd_QB} -272.5 150 1 1 0.2 0.2 {}
+T {D0_vco} -227.5 -150 3 1 0.2 0.2 {}
+T {lf_vc} -62.5 135 1 1 0.2 0.2 {}
+T {out_first_buffer} 7.5 190 1 1 0.2 0.2 {}
+T {cp_biasp} -92.5 157.5 1 1 0.2 0.2 {}
+T {cp_pswitch} -112.5 170 1 1 0.2 0.2 {}
+T {pfd_reset} -292.5 160 1 1 0.2 0.2 {}
+T {cp_nswitch} -132.5 170 1 1 0.2 0.2 {}
+T {out_by_2} 137.5 160 1 1 0.2 0.2 {}
+T {out_to_div} 27.5 165 1 1 0.2 0.2 {}
+T {out_div_by_5} 287.5 180 1 1 0.2 0.2 {}
+T {n_out_by_2} 147.5 112.5 3 1 0.2 0.2 {}
+T {div_5_nQ0} 207.5 167.5 1 1 0.2 0.2 {}
+T {div_5_Q1_shift} 247.5 190 1 1 0.2 0.2 {}
+T {div_5_Q1} 227.5 160 1 1 0.2 0.2 {}
+T {n_out_buffer_div_2} 97.5 210 1 1 0.2 0.2 {}
+T {out_buffer_div_2} 117.5 197.5 1 1 0.2 0.2 {}
+T {div_5_Q0} 187.5 160 1 1 0.2 0.2 {}
+T {n_out_div_2} 77.5 175 1 1 0.2 0.2 {}
+T {div_5_nQ2} 267.5 167.5 1 1 0.2 0.2 {}
+T {out_div_2} 57.5 162.5 1 1 0.2 0.2 {}
+T {PFD} -280 105 2 1 0.2 0.2 {}
+T {Interface} -210 105 2 1 0.2 0.2 {}
+T {CP} -120 105 2 1 0.2 0.2 {}
+T {LF} -65 105 2 1 0.2 0.2 {}
+T {VCO} -10 105 2 1 0.2 0.2 {}
+T {DIV_BY_2} 87.5 105 2 1 0.2 0.2 {}
+T {DIV_BY_5} 212.5 105 2 1 0.2 0.2 {}
+T {Debug} -17.5 85 2 1 0.2 0.2 {}
+T {Config} -197.5 -92.5 2 1 0.2 0.2 {}
+T {out_to_buffer} 337.5 180 1 1 0.2 0.2 {}
+T {D0_cap} -167.5 -150 3 1 0.2 0.2 {}
diff --git a/xschem/trans_gate.sch b/xschem/trans_gate.sch
new file mode 100644
index 0000000..138ab52
--- /dev/null
+++ b/xschem/trans_gate.sch
@@ -0,0 +1,62 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 380 -100 380 -70 { lab=vss}
+N 380 70 380 100 { lab=vdd}
+N 310 -100 350 -100 { lab=in}
+N 310 -100 310 -40 { lab=in}
+N 280 -40 310 -40 { lab=in}
+N 280 -40 280 0 { lab=in}
+N 310 100 350 100 { lab=in}
+N 310 40 310 100 { lab=in}
+N 280 40 310 40 { lab=in}
+N 280 0 280 40 { lab=in}
+N 410 100 450 100 { lab=out}
+N 450 40 450 100 { lab=out}
+N 450 40 480 40 { lab=out}
+N 480 0 480 40 { lab=out}
+N 410 -100 450 -100 { lab=out}
+N 450 -100 450 -40 { lab=out}
+N 450 -40 480 -40 { lab=out}
+N 480 -40 480 0 { lab=out}
+N 480 -0 540 0 { lab=out}
+N 220 -0 280 0 { lab=in}
+N 380 140 380 170 { lab=vss}
+N 380 -170 380 -140 { lab=vdd}
+C {sky130_fd_pr/pfet_01v8.sym} 380 120 3 0 {name=M2
+L=0.15
+W=1.25
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 380 170 1 0 {name=p1 lab=vss}
+C {ipin.sym} 220 0 0 0 {name=p2 lab=in}
+C {opin.sym} 540 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 380 -120 1 0 {name=M1
+L=0.15
+W=1.25
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 380 -70 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 380 70 1 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 380 -170 3 0 {name=p4 lab=vdd}
diff --git a/xschem/trans_gate.sym b/xschem/trans_gate.sym
new file mode 100644
index 0000000..54b0866
--- /dev/null
+++ b/xschem/trans_gate.sym
@@ -0,0 +1,49 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 0 90 0 {}
+L 4 -90 0 -70 0 {}
+L 4 -20 -50 20 -50 {}
+L 4 -20 -40 20 -40 {}
+L 4 20 -40 20 -20 {}
+L 4 20 -20 40 -20 {}
+L 4 40 -20 40 0 {}
+L 4 40 0 60 0 {}
+L 4 -20 -40 -20 -20 {}
+L 4 -40 -20 -20 -20 {}
+L 4 -40 -20 -40 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -20 50 20 50 {}
+L 4 -20 40 20 40 {}
+L 4 -20 20 -20 40 {}
+L 4 -40 20 -20 20 {}
+L 4 -40 0 -40 20 {}
+L 4 20 20 20 40 {}
+L 4 20 20 40 20 {}
+L 4 40 0 40 20 {}
+L 4 0 -60 -0 -50 {}
+L 4 0 60 0 70 {}
+L 4 -70 80 -0 80 {}
+L 4 -70 -70 -70 80 {}
+L 4 -70 -70 70 -70 {}
+L 4 70 -70 70 80 {}
+L 4 0 80 70 80 {}
+L 7 0 -90 0 -70 {}
+L 7 0 80 0 100 {}
+B 5 -2.5 -92.5 2.5 -87.5 {name=vdd dir=inout }
+B 5 87.5 -2.5 92.5 2.5 {name=out dir=out }
+B 5 -92.5 -2.5 -87.5 2.5 {name=in dir=in }
+B 5 -2.5 97.5 2.5 102.5 {name=vss dir=inout }
+A 4 0 55.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} 14 90 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -14 -95 3 1 0.2 0.2 {}
+T {out} 87 -13 0 1 0.2 0.2 {}
+T {in} -86 -14 0 0 0.2 0.2 {}
+T {vss} -2 104 1 1 0.2 0.2 {}
diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch
index e0da610..62d50fa 100644
--- a/xschem/user_analog_project_wrapper.sch
+++ b/xschem/user_analog_project_wrapper.sch
@@ -4,67 +4,455 @@
V {}
S {}
E {}
-N 3830 -460 3830 -390 { lab=vdda1}
-N 3730 -460 3830 -460 { lab=vdda1}
-N 3860 -230 3860 -180 { lab=vssa1}
-N 3770 -180 3860 -180 { lab=vssa1}
-N 3890 -460 3890 -390 { lab=vccd1}
-N 3890 -460 3960 -460 { lab=vccd1}
-N 3890 -130 3890 -60 { lab=vccd1}
-N 3890 -130 3950 -130 { lab=vccd1}
-N 3830 -130 3830 -60 { lab=io_analog[4]}
-N 3790 -130 3830 -130 { lab=io_analog[4]}
-N 3860 100 3860 150 { lab=vssa1}
-N 3800 150 3860 150 { lab=vssa1}
-N 4010 -10 4110 -10 { lab=gpio_analog[7]}
-N 4010 20 4110 20 { lab=io_out[15]}
-N 4010 50 4110 50 { lab=io_out[16]}
-N 4010 -340 4130 -340 { lab=gpio_analog[3]}
-N 4010 -310 4130 -310 { lab=io_out[11]}
-N 4010 -280 4130 -280 { lab=io_out[12]}
-C {example_por.sym} 3860 -310 0 0 {name=x1}
-C {example_por.sym} 3860 20 0 0 {name=x2}
-C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
-C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
-C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
-C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
-C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
-C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
-C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
-C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
-C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
-C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
-C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
-C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
-C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
-C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
-C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
-C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
-C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
-C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
-C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
-C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
-C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
-C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
-C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
-C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
-C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
-C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
-C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
-C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
-C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
-C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
-C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
-C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
-C {devices/lab_pin.sym} 3730 -460 0 0 {name=l1 sig_type=std_logic lab=vdda1}
-C {devices/lab_pin.sym} 3770 -180 0 0 {name=l2 sig_type=std_logic lab=vssa1}
-C {devices/lab_pin.sym} 3960 -460 0 1 {name=l3 sig_type=std_logic lab=vccd1}
-C {devices/lab_pin.sym} 3950 -130 0 1 {name=l4 sig_type=std_logic lab=vccd1}
-C {devices/lab_pin.sym} 3790 -130 0 0 {name=l5 sig_type=std_logic lab=io_analog[4]}
-C {devices/lab_pin.sym} 3800 150 0 0 {name=l6 sig_type=std_logic lab=vssa1}
-C {devices/lab_pin.sym} 4130 -340 0 1 {name=l7 sig_type=std_logic lab=gpio_analog[3]}
-C {devices/lab_pin.sym} 4130 -310 0 1 {name=l8 sig_type=std_logic lab=io_out[11]}
-C {devices/lab_pin.sym} 4130 -280 0 1 {name=l9 sig_type=std_logic lab=io_out[12]}
-C {devices/lab_pin.sym} 4110 -10 0 1 {name=l10 sig_type=std_logic lab=gpio_analog[7]}
-C {devices/lab_pin.sym} 4110 20 0 1 {name=l11 sig_type=std_logic lab=io_out[15]}
-C {devices/lab_pin.sym} 4110 50 0 1 {name=l12 sig_type=std_logic lab=io_out[16]}
+N 4410 160 4410 220 { lab=vdda1}
+N 4470 160 4470 220 { lab=vssa1}
+N 3990 530 3990 580 { lab=#net1}
+N 3990 480 3990 530 { lab=#net1}
+N 3970 530 3970 580 { lab=#net2}
+N 3970 480 3970 530 { lab=#net2}
+N 3950 530 3950 580 { lab=#net3}
+N 3950 480 3950 530 { lab=#net3}
+N 4060 530 4060 580 { lab=#net4}
+N 4060 480 4060 530 { lab=#net4}
+N 4040 530 4040 580 { lab=#net5}
+N 4040 480 4040 530 { lab=#net5}
+N 4020 530 4020 580 { lab=#net6}
+N 4020 480 4020 530 { lab=#net6}
+N 4080 530 4080 580 { lab=#net7}
+N 4080 480 4080 530 { lab=#net7}
+N 4150 530 4150 580 { lab=#net8}
+N 4150 480 4150 530 { lab=#net8}
+N 4130 530 4130 580 { lab=#net9}
+N 4130 480 4130 530 { lab=#net9}
+N 4110 530 4110 580 { lab=#net10}
+N 4110 480 4110 530 { lab=#net10}
+N 4180 530 4180 580 { lab=#net11}
+N 4180 480 4180 530 { lab=#net11}
+N 4210 530 4210 580 { lab=#net12}
+N 4210 480 4210 530 { lab=#net12}
+N 4230 530 4230 580 { lab=#net13}
+N 4230 480 4230 530 { lab=#net13}
+N 4250 530 4250 580 { lab=#net14}
+N 4250 480 4250 530 { lab=#net14}
+N 4270 530 4270 580 { lab=#net15}
+N 4270 480 4270 530 { lab=#net15}
+N 4300 530 4300 580 { lab=#net16}
+N 4300 480 4300 530 { lab=#net16}
+N 4320 530 4320 580 { lab=#net17}
+N 4320 480 4320 530 { lab=#net17}
+N 4340 530 4340 580 { lab=#net18}
+N 4340 480 4340 530 { lab=#net18}
+N 4360 530 4360 580 { lab=#net19}
+N 4360 480 4360 530 { lab=#net19}
+N 4380 530 4380 580 { lab=#net20}
+N 4380 480 4380 530 { lab=#net20}
+N 4400 530 4400 580 { lab=#net21}
+N 4400 480 4400 530 { lab=#net21}
+N 4430 530 4430 580 { lab=#net22}
+N 4430 480 4430 530 { lab=#net22}
+N 4450 530 4450 580 { lab=#net23}
+N 4450 480 4450 530 { lab=#net23}
+N 4470 530 4470 580 { lab=#net24}
+N 4470 480 4470 530 { lab=#net24}
+N 4490 530 4490 580 { lab=#net25}
+N 4490 480 4490 530 { lab=#net25}
+N 4510 530 4510 580 { lab=#net26}
+N 4510 480 4510 530 { lab=#net26}
+N 4530 530 4530 580 { lab=#net27}
+N 4530 480 4530 530 { lab=#net27}
+N 4580 530 4580 580 { lab=#net28}
+N 4580 480 4580 530 { lab=#net28}
+N 4700 350 4750 350 { lab=io_analog[9]}
+N 4650 350 4700 350 { lab=io_analog[9]}
+N 3820 350 3890 350 { lab=io_analog[10]}
+N 3950 150 3950 220 { lab=iref_cp2}
+N 4030 150 4030 220 { lab=gpio_noesd[7]}
+N 3890 -430 3890 -370 { lab=vdda1}
+N 3950 -290 3990 -290 { lab=iref_cp2}
+N 3780 350 3820 350 { lab=io_analog[10]}
+N 3890 -110 3890 -50 { lab=io_analog[5]}
+N 4000 -270 4050 -270 { lab=#net29}
+N 3950 -270 4000 -270 { lab=#net29}
+N 4000 -250 4050 -250 { lab=#net30}
+N 3950 -250 4000 -250 { lab=#net30}
+N 4000 -230 4050 -230 { lab=iref4}
+N 3950 -230 4000 -230 { lab=iref4}
+N 4000 -210 4050 -210 { lab=iref2}
+N 3950 -210 4000 -210 { lab=iref2}
+N 4000 -190 4050 -190 { lab=iref3}
+N 3950 -190 4000 -190 { lab=iref3}
+N 4000 -170 4050 -170 { lab=iref1}
+N 3950 -170 4000 -170 { lab=iref1}
+N 4000 -150 4050 -150 { lab=iref0}
+N 3950 -150 4000 -150 { lab=iref0}
+N 5660 160 5660 220 { lab=vdda1}
+N 5720 160 5720 220 { lab=vssa1}
+N 5240 530 5240 580 { lab=#net31}
+N 5240 480 5240 530 { lab=#net31}
+N 5220 530 5220 580 { lab=#net32}
+N 5220 480 5220 530 { lab=#net32}
+N 5200 530 5200 580 { lab=#net33}
+N 5200 480 5200 530 { lab=#net33}
+N 5310 530 5310 580 { lab=#net34}
+N 5310 480 5310 530 { lab=#net34}
+N 5290 530 5290 580 { lab=#net35}
+N 5290 480 5290 530 { lab=#net35}
+N 5270 530 5270 580 { lab=#net36}
+N 5270 480 5270 530 { lab=#net36}
+N 5330 530 5330 580 { lab=#net37}
+N 5330 480 5330 530 { lab=#net37}
+N 5400 530 5400 580 { lab=#net38}
+N 5400 480 5400 530 { lab=#net38}
+N 5380 530 5380 580 { lab=#net39}
+N 5380 480 5380 530 { lab=#net39}
+N 5360 530 5360 580 { lab=#net40}
+N 5360 480 5360 530 { lab=#net40}
+N 5430 530 5430 580 { lab=#net41}
+N 5430 480 5430 530 { lab=#net41}
+N 5460 530 5460 580 { lab=#net42}
+N 5460 480 5460 530 { lab=#net42}
+N 5480 530 5480 580 { lab=#net43}
+N 5480 480 5480 530 { lab=#net43}
+N 5500 530 5500 580 { lab=#net44}
+N 5500 480 5500 530 { lab=#net44}
+N 5520 530 5520 580 { lab=#net45}
+N 5520 480 5520 530 { lab=#net45}
+N 5550 530 5550 580 { lab=#net46}
+N 5550 480 5550 530 { lab=#net46}
+N 5570 530 5570 580 { lab=#net47}
+N 5570 480 5570 530 { lab=#net47}
+N 5590 530 5590 580 { lab=#net48}
+N 5590 480 5590 530 { lab=#net48}
+N 5610 530 5610 580 { lab=#net49}
+N 5610 480 5610 530 { lab=#net49}
+N 5630 530 5630 580 { lab=#net50}
+N 5630 480 5630 530 { lab=#net50}
+N 5650 530 5650 580 { lab=#net51}
+N 5650 480 5650 530 { lab=#net51}
+N 5680 530 5680 580 { lab=#net52}
+N 5680 480 5680 530 { lab=#net52}
+N 5700 530 5700 580 { lab=#net53}
+N 5700 480 5700 530 { lab=#net53}
+N 5720 530 5720 580 { lab=#net54}
+N 5720 480 5720 530 { lab=#net54}
+N 5740 530 5740 580 { lab=#net55}
+N 5740 480 5740 530 { lab=#net55}
+N 5760 530 5760 580 { lab=#net56}
+N 5760 480 5760 530 { lab=#net56}
+N 5780 530 5780 580 { lab=#net57}
+N 5780 480 5780 530 { lab=#net57}
+N 5830 530 5830 580 { lab=#net58}
+N 5830 480 5830 530 { lab=#net58}
+N 5950 350 6000 350 { lab=io_analog[8]}
+N 5900 350 5950 350 { lab=io_analog[8]}
+N 5070 350 5140 350 { lab=io_analog[10]}
+N 5200 150 5200 220 { lab=iref_cp1}
+N 5280 150 5280 220 { lab=gpio_noesd[7]}
+N 5030 350 5070 350 { lab=io_analog[10]}
+N 3950 -310 3990 -310 { lab=iref_cp1}
+N 5340 150 5340 220 { lab=gpio_noesd[8]}
+N 6880 160 6880 220 { lab=vdda1}
+N 6940 160 6940 220 { lab=vssa1}
+N 6460 530 6460 580 { lab=#net59}
+N 6460 480 6460 530 { lab=#net59}
+N 6440 530 6440 580 { lab=#net60}
+N 6440 480 6440 530 { lab=#net60}
+N 6420 530 6420 580 { lab=#net61}
+N 6420 480 6420 530 { lab=#net61}
+N 6530 530 6530 580 { lab=#net62}
+N 6530 480 6530 530 { lab=#net62}
+N 6510 530 6510 580 { lab=#net63}
+N 6510 480 6510 530 { lab=#net63}
+N 6490 530 6490 580 { lab=#net64}
+N 6490 480 6490 530 { lab=#net64}
+N 6550 530 6550 580 { lab=#net65}
+N 6550 480 6550 530 { lab=#net65}
+N 6620 530 6620 580 { lab=#net66}
+N 6620 480 6620 530 { lab=#net66}
+N 6600 530 6600 580 { lab=#net67}
+N 6600 480 6600 530 { lab=#net67}
+N 6580 530 6580 580 { lab=#net68}
+N 6580 480 6580 530 { lab=#net68}
+N 6650 530 6650 580 { lab=#net69}
+N 6650 480 6650 530 { lab=#net69}
+N 6680 530 6680 580 { lab=#net70}
+N 6680 480 6680 530 { lab=#net70}
+N 6700 530 6700 580 { lab=#net71}
+N 6700 480 6700 530 { lab=#net71}
+N 6720 530 6720 580 { lab=#net72}
+N 6720 480 6720 530 { lab=#net72}
+N 6740 530 6740 580 { lab=#net73}
+N 6740 480 6740 530 { lab=#net73}
+N 6770 530 6770 580 { lab=#net74}
+N 6770 480 6770 530 { lab=#net74}
+N 6790 530 6790 580 { lab=#net75}
+N 6790 480 6790 530 { lab=#net75}
+N 6810 530 6810 580 { lab=#net76}
+N 6810 480 6810 530 { lab=#net76}
+N 6830 530 6830 580 { lab=#net77}
+N 6830 480 6830 530 { lab=#net77}
+N 6850 530 6850 580 { lab=#net78}
+N 6850 480 6850 530 { lab=#net78}
+N 6870 530 6870 580 { lab=#net79}
+N 6870 480 6870 530 { lab=#net79}
+N 6900 530 6900 580 { lab=#net80}
+N 6900 480 6900 530 { lab=#net80}
+N 6920 530 6920 580 { lab=#net81}
+N 6920 480 6920 530 { lab=#net81}
+N 6940 530 6940 580 { lab=#net82}
+N 6940 480 6940 530 { lab=#net82}
+N 6960 530 6960 580 { lab=#net83}
+N 6960 480 6960 530 { lab=#net83}
+N 6980 530 6980 580 { lab=#net84}
+N 6980 480 6980 530 { lab=#net84}
+N 7000 530 7000 580 { lab=#net85}
+N 7000 480 7000 530 { lab=#net85}
+N 7050 530 7050 580 { lab=#net86}
+N 7050 480 7050 530 { lab=#net86}
+N 7170 350 7220 350 { lab=io_analog[7]}
+N 7120 350 7170 350 { lab=io_analog[7]}
+N 6290 350 6360 350 { lab=io_analog[10]}
+N 6420 150 6420 220 { lab=iref_cp0}
+N 6500 150 6500 220 { lab=gpio_noesd[7]}
+N 6250 350 6290 350 { lab=io_analog[10]}
+N 3950 -330 3990 -330 { lab=iref_cp0}
+N 4540 -360 4540 -300 { lab=vdda1}
+N 4540 -240 4540 -180 { lab=vssa1}
+N 4680 -360 4680 -300 { lab=vdda1}
+N 4680 -240 4680 -180 { lab=vssa1}
+N 4820 -360 4820 -300 { lab=vdda1}
+N 4820 -240 4820 -180 { lab=vssa1}
+N 5050 -360 5050 -300 { lab=vdda1}
+N 5050 -240 5050 -180 { lab=vssa1}
+N 5190 -360 5190 -300 { lab=vdda1}
+N 5190 -240 5190 -180 { lab=vssa1}
+N 5330 -360 5330 -300 { lab=vdda1}
+N 5330 -240 5330 -180 { lab=vssa1}
+N 5470 -360 5470 -300 { lab=vdda1}
+N 5470 -240 5470 -180 { lab=vssa1}
+N 5600 -360 5600 -300 { lab=vdda1}
+N 5600 -240 5600 -180 { lab=vssa1}
+N 5750 -360 5750 -300 { lab=vdda1}
+N 5750 -240 5750 -180 { lab=vssa1}
+N 6680 -510 6680 -460 { lab=vdda1}
+N 6720 -230 6720 -180 { lab=vssa1}
+N 6850 -350 6960 -350 { lab=io_analog[0]}
+N 6850 -370 6960 -370 { lab=io_analog[1]}
+N 6450 -410 6560 -410 { lab=io_analog[4]}
+N 6450 -430 6560 -430 { lab=io_analog[6]}
+N 6450 -350 6560 -350 { lab=io_analog[2]}
+N 6450 -370 6560 -370 { lab=io_analog[3]}
+N 6450 -280 6560 -280 { lab=iref2}
+N 6450 -300 6560 -300 { lab=iref0}
+N 6450 -270 6560 -270 { lab=iref3}
+N 6450 -290 6560 -290 { lab=iref1}
+N 6450 -260 6560 -260 { lab=iref4}
+N 6610 -230 6610 -120 { lab=gpio_noesd[6]}
+N 6630 -230 6630 -120 { lab=gpio_noesd[2]}
+N 6600 -230 6600 -120 { lab=gpio_noesd[5]}
+N 6620 -230 6620 -120 { lab=gpio_noesd[3]}
+N 6590 -230 6590 -120 { lab=gpio_noesd[4]}
+N 6640 -230 6640 -120 { lab=gpio_noesd[1]}
+N 5880 -360 5880 -300 { lab=vdda1}
+N 5880 -240 5880 -180 { lab=vssa1}
+C {iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {top_pll_v1.sym} 4240 350 0 0 {name=x1}
+C {lab_pin.sym} 4410 160 1 0 {name=l13 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4470 160 1 0 {name=l14 sig_type=std_logic lab=vssa1}
+C {noconn.sym} 3990 580 3 0 {name=l15}
+C {noconn.sym} 3970 580 3 0 {name=l6}
+C {noconn.sym} 3950 580 3 0 {name=l16}
+C {noconn.sym} 4060 580 3 0 {name=l17}
+C {noconn.sym} 4040 580 3 0 {name=l18}
+C {noconn.sym} 4020 580 3 0 {name=l19}
+C {noconn.sym} 4080 580 3 0 {name=l20}
+C {noconn.sym} 4150 580 3 0 {name=l21}
+C {noconn.sym} 4130 580 3 0 {name=l22}
+C {noconn.sym} 4110 580 3 0 {name=l23}
+C {noconn.sym} 4180 580 3 0 {name=l24}
+C {noconn.sym} 4210 580 3 0 {name=l25}
+C {noconn.sym} 4230 580 3 0 {name=l26}
+C {noconn.sym} 4250 580 3 0 {name=l27}
+C {noconn.sym} 4270 580 3 0 {name=l28}
+C {noconn.sym} 4300 580 3 0 {name=l29}
+C {noconn.sym} 4320 580 3 0 {name=l30}
+C {noconn.sym} 4340 580 3 0 {name=l31}
+C {noconn.sym} 4360 580 3 0 {name=l32}
+C {noconn.sym} 4380 580 3 0 {name=l33}
+C {noconn.sym} 4400 580 3 0 {name=l34}
+C {noconn.sym} 4430 580 3 0 {name=l35}
+C {noconn.sym} 4450 580 3 0 {name=l36}
+C {noconn.sym} 4470 580 3 0 {name=l37}
+C {noconn.sym} 4490 580 3 0 {name=l38}
+C {noconn.sym} 4510 580 3 0 {name=l39}
+C {noconn.sym} 4530 580 3 0 {name=l40}
+C {noconn.sym} 4580 580 3 0 {name=l41}
+C {bias.sym} 3890 -240 0 0 {name=x2}
+C {lab_pin.sym} 3890 -430 1 0 {name=l42 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 3990 -290 2 0 {name=l43 sig_type=std_logic lab=iref_cp2}
+C {lab_pin.sym} 3950 150 1 0 {name=l44 sig_type=std_logic lab=iref_cp2}
+C {noconn.sym} 4050 -270 2 0 {name=l48}
+C {noconn.sym} 4050 -250 2 0 {name=l49}
+C {lab_pin.sym} 3780 350 0 0 {name=l45 sig_type=std_logic lab=io_analog[10]}
+C {lab_pin.sym} 4750 350 2 0 {name=l55 sig_type=std_logic lab=io_analog[9]}
+C {lab_pin.sym} 4030 150 3 1 {name=l56 sig_type=std_logic lab=gpio_noesd[7]}
+C {lab_pin.sym} 3890 -50 3 0 {name=l1 sig_type=std_logic lab=io_analog[5]}
+C {lab_pin.sym} 5660 160 1 0 {name=l2 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5720 160 1 0 {name=l3 sig_type=std_logic lab=vssa1}
+C {noconn.sym} 5240 580 3 0 {name=l4}
+C {noconn.sym} 5220 580 3 0 {name=l5}
+C {noconn.sym} 5200 580 3 0 {name=l7}
+C {noconn.sym} 5310 580 3 0 {name=l8}
+C {noconn.sym} 5290 580 3 0 {name=l9}
+C {noconn.sym} 5270 580 3 0 {name=l10}
+C {noconn.sym} 5330 580 3 0 {name=l11}
+C {noconn.sym} 5400 580 3 0 {name=l12}
+C {noconn.sym} 5380 580 3 0 {name=l57}
+C {noconn.sym} 5360 580 3 0 {name=l58}
+C {noconn.sym} 5430 580 3 0 {name=l59}
+C {noconn.sym} 5460 580 3 0 {name=l60}
+C {noconn.sym} 5480 580 3 0 {name=l61}
+C {noconn.sym} 5500 580 3 0 {name=l62}
+C {noconn.sym} 5520 580 3 0 {name=l63}
+C {noconn.sym} 5550 580 3 0 {name=l64}
+C {noconn.sym} 5570 580 3 0 {name=l65}
+C {noconn.sym} 5590 580 3 0 {name=l66}
+C {noconn.sym} 5610 580 3 0 {name=l67}
+C {noconn.sym} 5630 580 3 0 {name=l68}
+C {noconn.sym} 5650 580 3 0 {name=l69}
+C {noconn.sym} 5680 580 3 0 {name=l70}
+C {noconn.sym} 5700 580 3 0 {name=l71}
+C {noconn.sym} 5720 580 3 0 {name=l72}
+C {noconn.sym} 5740 580 3 0 {name=l73}
+C {noconn.sym} 5760 580 3 0 {name=l74}
+C {noconn.sym} 5780 580 3 0 {name=l75}
+C {noconn.sym} 5830 580 3 0 {name=l76}
+C {lab_pin.sym} 5200 150 1 0 {name=l77 sig_type=std_logic lab=iref_cp1}
+C {lab_pin.sym} 5030 350 0 0 {name=l78 sig_type=std_logic lab=io_analog[10]}
+C {lab_pin.sym} 6000 350 2 0 {name=l79 sig_type=std_logic lab=io_analog[8]}
+C {lab_pin.sym} 5280 150 3 1 {name=l80 sig_type=std_logic lab=gpio_noesd[7]}
+C {lab_pin.sym} 3990 -310 2 0 {name=l81 sig_type=std_logic lab=iref_cp1}
+C {top_pll_v2.sym} 5490 350 0 0 {name=x3}
+C {lab_pin.sym} 5340 150 3 1 {name=l47 sig_type=std_logic lab=gpio_noesd[8]}
+C {top_pll_v1.sym} 6710 350 0 0 {name=x4}
+C {lab_pin.sym} 6880 160 1 0 {name=l82 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 6940 160 1 0 {name=l83 sig_type=std_logic lab=vssa1}
+C {noconn.sym} 6460 580 3 0 {name=l84}
+C {noconn.sym} 6440 580 3 0 {name=l85}
+C {noconn.sym} 6420 580 3 0 {name=l86}
+C {noconn.sym} 6530 580 3 0 {name=l87}
+C {noconn.sym} 6510 580 3 0 {name=l88}
+C {noconn.sym} 6490 580 3 0 {name=l89}
+C {noconn.sym} 6550 580 3 0 {name=l90}
+C {noconn.sym} 6620 580 3 0 {name=l91}
+C {noconn.sym} 6600 580 3 0 {name=l92}
+C {noconn.sym} 6580 580 3 0 {name=l93}
+C {noconn.sym} 6650 580 3 0 {name=l94}
+C {noconn.sym} 6680 580 3 0 {name=l95}
+C {noconn.sym} 6700 580 3 0 {name=l96}
+C {noconn.sym} 6720 580 3 0 {name=l97}
+C {noconn.sym} 6740 580 3 0 {name=l98}
+C {noconn.sym} 6770 580 3 0 {name=l99}
+C {noconn.sym} 6790 580 3 0 {name=l100}
+C {noconn.sym} 6810 580 3 0 {name=l101}
+C {noconn.sym} 6830 580 3 0 {name=l102}
+C {noconn.sym} 6850 580 3 0 {name=l103}
+C {noconn.sym} 6870 580 3 0 {name=l104}
+C {noconn.sym} 6900 580 3 0 {name=l105}
+C {noconn.sym} 6920 580 3 0 {name=l106}
+C {noconn.sym} 6940 580 3 0 {name=l107}
+C {noconn.sym} 6960 580 3 0 {name=l108}
+C {noconn.sym} 6980 580 3 0 {name=l109}
+C {noconn.sym} 7000 580 3 0 {name=l110}
+C {noconn.sym} 7050 580 3 0 {name=l111}
+C {lab_pin.sym} 6420 150 1 0 {name=l112 sig_type=std_logic lab=iref_cp0}
+C {lab_pin.sym} 6250 350 0 0 {name=l113 sig_type=std_logic lab=io_analog[10]}
+C {lab_pin.sym} 7220 350 2 0 {name=l114 sig_type=std_logic lab=io_analog[7]}
+C {lab_pin.sym} 6500 150 3 1 {name=l115 sig_type=std_logic lab=gpio_noesd[7]}
+C {lab_pin.sym} 3990 -330 2 0 {name=l46 sig_type=std_logic lab=iref_cp0}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 4540 -270 0 0 {name=C1 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X}
+C {lab_pin.sym} 4540 -360 1 0 {name=l116 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4540 -180 3 0 {name=l117 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 4680 -270 0 0 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X}
+C {lab_pin.sym} 4680 -360 1 0 {name=l118 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4680 -180 3 0 {name=l119 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 4820 -270 0 0 {name=C3 model=cap_mim_m3_2 W=30 L=30 MF=7 spiceprefix=X}
+C {lab_pin.sym} 4820 -360 1 0 {name=l120 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4820 -180 3 0 {name=l121 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5050 -270 0 0 {name=C4 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5050 -360 1 0 {name=l122 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5050 -180 3 0 {name=l123 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5190 -270 0 0 {name=C5 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5190 -360 1 0 {name=l124 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5190 -180 3 0 {name=l125 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5330 -270 0 0 {name=C6 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5330 -360 1 0 {name=l126 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5330 -180 3 0 {name=l127 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5470 -270 0 0 {name=C7 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5470 -360 1 0 {name=l128 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5470 -180 3 0 {name=l129 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5600 -270 0 0 {name=C8 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5600 -360 1 0 {name=l130 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5600 -180 3 0 {name=l131 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5750 -270 0 0 {name=C9 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5750 -360 1 0 {name=l132 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5750 -180 3 0 {name=l133 sig_type=std_logic lab=vssa1}
+C {lab_pin.sym} 6680 -490 2 0 {name=l134 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 6720 -190 2 0 {name=l135 sig_type=std_logic lab=vssa1}
+C {res_amp_top.sym} 6730 -190 0 0 {name=x5}
+C {lab_pin.sym} 6960 -370 2 0 {name=l136 sig_type=std_logic lab=io_analog[1]}
+C {lab_pin.sym} 6960 -350 2 0 {name=l137 sig_type=std_logic lab=io_analog[0]}
+C {lab_pin.sym} 6450 -410 0 0 {name=l138 sig_type=std_logic lab=io_analog[4]}
+C {lab_pin.sym} 6450 -430 0 0 {name=l139 sig_type=std_logic lab=io_analog[6]}
+C {lab_pin.sym} 6450 -350 0 0 {name=l140 sig_type=std_logic lab=io_analog[2]}
+C {lab_pin.sym} 6450 -370 0 0 {name=l141 sig_type=std_logic lab=io_analog[3]}
+C {lab_pin.sym} 4050 -150 2 0 {name=l50 sig_type=std_logic lab=iref0}
+C {lab_pin.sym} 4050 -170 2 0 {name=l51 sig_type=std_logic lab=iref1}
+C {lab_pin.sym} 4050 -190 2 0 {name=l52 sig_type=std_logic lab=iref3}
+C {lab_pin.sym} 4050 -210 2 0 {name=l53 sig_type=std_logic lab=iref2}
+C {lab_pin.sym} 4050 -230 2 0 {name=l54 sig_type=std_logic lab=iref4}
+C {lab_pin.sym} 6450 -280 0 0 {name=l142 sig_type=std_logic lab=iref2}
+C {lab_pin.sym} 6450 -300 0 0 {name=l143 sig_type=std_logic lab=iref0}
+C {lab_pin.sym} 6450 -270 0 0 {name=l144 sig_type=std_logic lab=iref3}
+C {lab_pin.sym} 6450 -290 0 0 {name=l145 sig_type=std_logic lab=iref1}
+C {lab_pin.sym} 6450 -260 0 0 {name=l146 sig_type=std_logic lab=iref4}
+C {lab_pin.sym} 6610 -120 3 0 {name=l147 sig_type=std_logic lab=gpio_noesd[6]}
+C {lab_pin.sym} 6600 -120 3 0 {name=l148 sig_type=std_logic lab=gpio_noesd[5]}
+C {lab_pin.sym} 6590 -120 3 0 {name=l149 sig_type=std_logic lab=gpio_noesd[4]}
+C {lab_pin.sym} 6640 -120 3 0 {name=l150 sig_type=std_logic lab=gpio_noesd[1]}
+C {lab_pin.sym} 6630 -120 3 0 {name=l151 sig_type=std_logic lab=gpio_noesd[2]}
+C {lab_pin.sym} 6620 -120 3 0 {name=l152 sig_type=std_logic lab=gpio_noesd[3]}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5880 -270 0 0 {name=C10 model=cap_mim_m3_2 W=30 L=30 MF=10 spiceprefix=X}
+C {lab_pin.sym} 5880 -360 1 0 {name=l153 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5880 -180 3 0 {name=l154 sig_type=std_logic lab=vssa1}
diff --git a/xschem/user_analog_project_wrapper.spice b/xschem/user_analog_project_wrapper.spice
deleted file mode 100644
index 917d69e..0000000
--- a/xschem/user_analog_project_wrapper.spice
+++ /dev/null
@@ -1,121 +0,0 @@
-**.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa1 vccd1 vccd2 vssd1 vssd2 wb_clk_i
-*+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
-*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
-*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0] wbs_ack_o
-*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
-*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
-*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
-*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
-*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0] user_clock2
-*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
-*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
-*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
-*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
-*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0] io_clamp_high[2],io_clamp_high[1],io_clamp_high[0] io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
-*+ user_irq[2],user_irq[1],user_irq[0]
-*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
-*.iopin vdda1
-*.iopin vdda2
-*.iopin vssa1
-*.iopin vssa1
-*.iopin vccd1
-*.iopin vccd2
-*.iopin vssd1
-*.iopin vssd2
-*.ipin wb_clk_i
-*.ipin wb_rst_i
-*.ipin wbs_stb_i
-*.ipin wbs_cyc_i
-*.ipin wbs_we_i
-*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
-*.ipin
-*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
-*.ipin
-*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
-*.opin wbs_ack_o
-*.opin
-*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
-*.ipin
-*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
-*.opin
-*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
-*.ipin
-*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
-*.ipin
-*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
-*.ipin user_clock2
-*.opin
-*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
-*.opin
-*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
-*.iopin
-*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
-*.iopin
-*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
-*.iopin
-*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
-*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
-*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
-*.opin user_irq[2],user_irq[1],user_irq[0]
-*.ipin
-*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
-x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por
-x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por
-**.ends
-
-* expanding symbol: example_por.sym # of pins=6
-* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
-* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
-.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
-*.iopin vdd3v3
-*.iopin vss
-*.opin porb_h
-*.opin porb_l
-*.opin por_l
-*.iopin vdd1v8
-XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
-XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
-XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=500 mult=1 m=1
-XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=150 mult=1 m=1
-XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=25 mult=2 m=2
-x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
-x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
-x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
-x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1
-.ends
-
-** flattened .save nodes
-.end
diff --git a/xschem/user_analog_project_wrapper_backup.sch b/xschem/user_analog_project_wrapper_backup.sch
new file mode 100644
index 0000000..1d46956
--- /dev/null
+++ b/xschem/user_analog_project_wrapper_backup.sch
@@ -0,0 +1,414 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 4410 160 4410 220 { lab=vdda1}
+N 4470 160 4470 220 { lab=vssa1}
+N 3990 530 3990 580 { lab=#net1}
+N 3990 480 3990 530 { lab=#net1}
+N 3970 530 3970 580 { lab=#net2}
+N 3970 480 3970 530 { lab=#net2}
+N 3950 530 3950 580 { lab=#net3}
+N 3950 480 3950 530 { lab=#net3}
+N 4060 530 4060 580 { lab=#net4}
+N 4060 480 4060 530 { lab=#net4}
+N 4040 530 4040 580 { lab=#net5}
+N 4040 480 4040 530 { lab=#net5}
+N 4020 530 4020 580 { lab=#net6}
+N 4020 480 4020 530 { lab=#net6}
+N 4080 530 4080 580 { lab=#net7}
+N 4080 480 4080 530 { lab=#net7}
+N 4150 530 4150 580 { lab=#net8}
+N 4150 480 4150 530 { lab=#net8}
+N 4130 530 4130 580 { lab=#net9}
+N 4130 480 4130 530 { lab=#net9}
+N 4110 530 4110 580 { lab=#net10}
+N 4110 480 4110 530 { lab=#net10}
+N 4180 530 4180 580 { lab=#net11}
+N 4180 480 4180 530 { lab=#net11}
+N 4210 530 4210 580 { lab=#net12}
+N 4210 480 4210 530 { lab=#net12}
+N 4230 530 4230 580 { lab=#net13}
+N 4230 480 4230 530 { lab=#net13}
+N 4250 530 4250 580 { lab=#net14}
+N 4250 480 4250 530 { lab=#net14}
+N 4270 530 4270 580 { lab=#net15}
+N 4270 480 4270 530 { lab=#net15}
+N 4300 530 4300 580 { lab=#net16}
+N 4300 480 4300 530 { lab=#net16}
+N 4320 530 4320 580 { lab=#net17}
+N 4320 480 4320 530 { lab=#net17}
+N 4340 530 4340 580 { lab=#net18}
+N 4340 480 4340 530 { lab=#net18}
+N 4360 530 4360 580 { lab=#net19}
+N 4360 480 4360 530 { lab=#net19}
+N 4380 530 4380 580 { lab=#net20}
+N 4380 480 4380 530 { lab=#net20}
+N 4400 530 4400 580 { lab=#net21}
+N 4400 480 4400 530 { lab=#net21}
+N 4430 530 4430 580 { lab=#net22}
+N 4430 480 4430 530 { lab=#net22}
+N 4450 530 4450 580 { lab=#net23}
+N 4450 480 4450 530 { lab=#net23}
+N 4470 530 4470 580 { lab=#net24}
+N 4470 480 4470 530 { lab=#net24}
+N 4490 530 4490 580 { lab=#net25}
+N 4490 480 4490 530 { lab=#net25}
+N 4510 530 4510 580 { lab=#net26}
+N 4510 480 4510 530 { lab=#net26}
+N 4530 530 4530 580 { lab=#net27}
+N 4530 480 4530 530 { lab=#net27}
+N 4580 530 4580 580 { lab=#net28}
+N 4580 480 4580 530 { lab=#net28}
+N 4700 350 4750 350 { lab=io_analog[9]}
+N 4650 350 4700 350 { lab=io_analog[9]}
+N 3820 350 3890 350 { lab=io_analog[10]}
+N 3950 150 3950 220 { lab=iref_cp2}
+N 4030 150 4030 220 { lab=gpio_noesd[7]}
+N 3890 -430 3890 -370 { lab=vdda1}
+N 3950 -290 3990 -290 { lab=iref_cp2}
+N 3780 350 3820 350 { lab=io_analog[10]}
+N 3890 -110 3890 -50 { lab=io_analog[5]}
+N 4000 -270 4050 -270 { lab=#net29}
+N 3950 -270 4000 -270 { lab=#net29}
+N 4000 -250 4050 -250 { lab=#net30}
+N 3950 -250 4000 -250 { lab=#net30}
+N 4000 -230 4050 -230 { lab=#net31}
+N 3950 -230 4000 -230 { lab=#net31}
+N 4000 -210 4050 -210 { lab=#net32}
+N 3950 -210 4000 -210 { lab=#net32}
+N 4000 -190 4050 -190 { lab=#net33}
+N 3950 -190 4000 -190 { lab=#net33}
+N 4000 -170 4050 -170 { lab=#net34}
+N 3950 -170 4000 -170 { lab=#net34}
+N 4000 -150 4050 -150 { lab=#net35}
+N 3950 -150 4000 -150 { lab=#net35}
+N 5660 160 5660 220 { lab=vdda1}
+N 5720 160 5720 220 { lab=vssa1}
+N 5240 530 5240 580 { lab=#net36}
+N 5240 480 5240 530 { lab=#net36}
+N 5220 530 5220 580 { lab=#net37}
+N 5220 480 5220 530 { lab=#net37}
+N 5200 530 5200 580 { lab=#net38}
+N 5200 480 5200 530 { lab=#net38}
+N 5310 530 5310 580 { lab=#net39}
+N 5310 480 5310 530 { lab=#net39}
+N 5290 530 5290 580 { lab=#net40}
+N 5290 480 5290 530 { lab=#net40}
+N 5270 530 5270 580 { lab=#net41}
+N 5270 480 5270 530 { lab=#net41}
+N 5330 530 5330 580 { lab=#net42}
+N 5330 480 5330 530 { lab=#net42}
+N 5400 530 5400 580 { lab=#net43}
+N 5400 480 5400 530 { lab=#net43}
+N 5380 530 5380 580 { lab=#net44}
+N 5380 480 5380 530 { lab=#net44}
+N 5360 530 5360 580 { lab=#net45}
+N 5360 480 5360 530 { lab=#net45}
+N 5430 530 5430 580 { lab=#net46}
+N 5430 480 5430 530 { lab=#net46}
+N 5460 530 5460 580 { lab=#net47}
+N 5460 480 5460 530 { lab=#net47}
+N 5480 530 5480 580 { lab=#net48}
+N 5480 480 5480 530 { lab=#net48}
+N 5500 530 5500 580 { lab=#net49}
+N 5500 480 5500 530 { lab=#net49}
+N 5520 530 5520 580 { lab=#net50}
+N 5520 480 5520 530 { lab=#net50}
+N 5550 530 5550 580 { lab=#net51}
+N 5550 480 5550 530 { lab=#net51}
+N 5570 530 5570 580 { lab=#net52}
+N 5570 480 5570 530 { lab=#net52}
+N 5590 530 5590 580 { lab=#net53}
+N 5590 480 5590 530 { lab=#net53}
+N 5610 530 5610 580 { lab=#net54}
+N 5610 480 5610 530 { lab=#net54}
+N 5630 530 5630 580 { lab=#net55}
+N 5630 480 5630 530 { lab=#net55}
+N 5650 530 5650 580 { lab=#net56}
+N 5650 480 5650 530 { lab=#net56}
+N 5680 530 5680 580 { lab=#net57}
+N 5680 480 5680 530 { lab=#net57}
+N 5700 530 5700 580 { lab=#net58}
+N 5700 480 5700 530 { lab=#net58}
+N 5720 530 5720 580 { lab=#net59}
+N 5720 480 5720 530 { lab=#net59}
+N 5740 530 5740 580 { lab=#net60}
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+N 5780 480 5780 530 { lab=#net62}
+N 5830 530 5830 580 { lab=#net63}
+N 5830 480 5830 530 { lab=#net63}
+N 5950 350 6000 350 { lab=io_analog[8]}
+N 5900 350 5950 350 { lab=io_analog[8]}
+N 5070 350 5140 350 { lab=io_analog[10]}
+N 5200 150 5200 220 { lab=iref_cp1}
+N 5280 150 5280 220 { lab=gpio_noesd[7]}
+N 5030 350 5070 350 { lab=io_analog[10]}
+N 3950 -310 3990 -310 { lab=iref_cp1}
+N 5340 150 5340 220 { lab=gpio_noesd[8]}
+N 6880 160 6880 220 { lab=vdda1}
+N 6940 160 6940 220 { lab=vssa1}
+N 6460 530 6460 580 { lab=#net64}
+N 6460 480 6460 530 { lab=#net64}
+N 6440 530 6440 580 { lab=#net65}
+N 6440 480 6440 530 { lab=#net65}
+N 6420 530 6420 580 { lab=#net66}
+N 6420 480 6420 530 { lab=#net66}
+N 6530 530 6530 580 { lab=#net67}
+N 6530 480 6530 530 { lab=#net67}
+N 6510 530 6510 580 { lab=#net68}
+N 6510 480 6510 530 { lab=#net68}
+N 6490 530 6490 580 { lab=#net69}
+N 6490 480 6490 530 { lab=#net69}
+N 6550 530 6550 580 { lab=#net70}
+N 6550 480 6550 530 { lab=#net70}
+N 6620 530 6620 580 { lab=#net71}
+N 6620 480 6620 530 { lab=#net71}
+N 6600 530 6600 580 { lab=#net72}
+N 6600 480 6600 530 { lab=#net72}
+N 6580 530 6580 580 { lab=#net73}
+N 6580 480 6580 530 { lab=#net73}
+N 6650 530 6650 580 { lab=#net74}
+N 6650 480 6650 530 { lab=#net74}
+N 6680 530 6680 580 { lab=#net75}
+N 6680 480 6680 530 { lab=#net75}
+N 6700 530 6700 580 { lab=#net76}
+N 6700 480 6700 530 { lab=#net76}
+N 6720 530 6720 580 { lab=#net77}
+N 6720 480 6720 530 { lab=#net77}
+N 6740 530 6740 580 { lab=#net78}
+N 6740 480 6740 530 { lab=#net78}
+N 6770 530 6770 580 { lab=#net79}
+N 6770 480 6770 530 { lab=#net79}
+N 6790 530 6790 580 { lab=#net80}
+N 6790 480 6790 530 { lab=#net80}
+N 6810 530 6810 580 { lab=#net81}
+N 6810 480 6810 530 { lab=#net81}
+N 6830 530 6830 580 { lab=#net82}
+N 6830 480 6830 530 { lab=#net82}
+N 6850 530 6850 580 { lab=#net83}
+N 6850 480 6850 530 { lab=#net83}
+N 6870 530 6870 580 { lab=#net84}
+N 6870 480 6870 530 { lab=#net84}
+N 6900 530 6900 580 { lab=#net85}
+N 6900 480 6900 530 { lab=#net85}
+N 6920 530 6920 580 { lab=#net86}
+N 6920 480 6920 530 { lab=#net86}
+N 6940 530 6940 580 { lab=#net87}
+N 6940 480 6940 530 { lab=#net87}
+N 6960 530 6960 580 { lab=#net88}
+N 6960 480 6960 530 { lab=#net88}
+N 6980 530 6980 580 { lab=#net89}
+N 6980 480 6980 530 { lab=#net89}
+N 7000 530 7000 580 { lab=#net90}
+N 7000 480 7000 530 { lab=#net90}
+N 7050 530 7050 580 { lab=#net91}
+N 7050 480 7050 530 { lab=#net91}
+N 7170 350 7220 350 { lab=io_analog[7]}
+N 7120 350 7170 350 { lab=io_analog[7]}
+N 6290 350 6360 350 { lab=io_analog[10]}
+N 6420 150 6420 220 { lab=iref_cp0}
+N 6500 150 6500 220 { lab=gpio_noesd[7]}
+N 6250 350 6290 350 { lab=io_analog[10]}
+N 3950 -330 3990 -330 { lab=iref_cp0}
+N 4540 -360 4540 -300 { lab=vdda1}
+N 4540 -240 4540 -180 { lab=vssa1}
+N 4680 -360 4680 -300 { lab=vdda1}
+N 4680 -240 4680 -180 { lab=vssa1}
+N 4820 -360 4820 -300 { lab=vdda1}
+N 4820 -240 4820 -180 { lab=vssa1}
+N 5050 -360 5050 -300 { lab=vdda1}
+N 5050 -240 5050 -180 { lab=vssa1}
+N 5190 -360 5190 -300 { lab=vdda1}
+N 5190 -240 5190 -180 { lab=vssa1}
+N 5330 -360 5330 -300 { lab=vdda1}
+N 5330 -240 5330 -180 { lab=vssa1}
+N 5470 -360 5470 -300 { lab=vdda1}
+N 5470 -240 5470 -180 { lab=vssa1}
+N 5600 -360 5600 -300 { lab=vdda1}
+N 5600 -240 5600 -180 { lab=vssa1}
+N 5750 -360 5750 -300 { lab=vdda1}
+N 5750 -240 5750 -180 { lab=vssa1}
+C {iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {top_pll_v1.sym} 4240 350 0 0 {name=x1}
+C {lab_pin.sym} 4410 160 1 0 {name=l13 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4470 160 1 0 {name=l14 sig_type=std_logic lab=vssa1}
+C {noconn.sym} 3990 580 3 0 {name=l15}
+C {noconn.sym} 3970 580 3 0 {name=l6}
+C {noconn.sym} 3950 580 3 0 {name=l16}
+C {noconn.sym} 4060 580 3 0 {name=l17}
+C {noconn.sym} 4040 580 3 0 {name=l18}
+C {noconn.sym} 4020 580 3 0 {name=l19}
+C {noconn.sym} 4080 580 3 0 {name=l20}
+C {noconn.sym} 4150 580 3 0 {name=l21}
+C {noconn.sym} 4130 580 3 0 {name=l22}
+C {noconn.sym} 4110 580 3 0 {name=l23}
+C {noconn.sym} 4180 580 3 0 {name=l24}
+C {noconn.sym} 4210 580 3 0 {name=l25}
+C {noconn.sym} 4230 580 3 0 {name=l26}
+C {noconn.sym} 4250 580 3 0 {name=l27}
+C {noconn.sym} 4270 580 3 0 {name=l28}
+C {noconn.sym} 4300 580 3 0 {name=l29}
+C {noconn.sym} 4320 580 3 0 {name=l30}
+C {noconn.sym} 4340 580 3 0 {name=l31}
+C {noconn.sym} 4360 580 3 0 {name=l32}
+C {noconn.sym} 4380 580 3 0 {name=l33}
+C {noconn.sym} 4400 580 3 0 {name=l34}
+C {noconn.sym} 4430 580 3 0 {name=l35}
+C {noconn.sym} 4450 580 3 0 {name=l36}
+C {noconn.sym} 4470 580 3 0 {name=l37}
+C {noconn.sym} 4490 580 3 0 {name=l38}
+C {noconn.sym} 4510 580 3 0 {name=l39}
+C {noconn.sym} 4530 580 3 0 {name=l40}
+C {noconn.sym} 4580 580 3 0 {name=l41}
+C {bias.sym} 3890 -240 0 0 {name=x2}
+C {lab_pin.sym} 3890 -430 1 0 {name=l42 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 3990 -290 2 0 {name=l43 sig_type=std_logic lab=iref_cp2}
+C {lab_pin.sym} 3950 150 1 0 {name=l44 sig_type=std_logic lab=iref_cp2}
+C {noconn.sym} 4050 -270 2 0 {name=l48}
+C {noconn.sym} 4050 -250 2 0 {name=l49}
+C {noconn.sym} 4050 -230 2 0 {name=l50}
+C {noconn.sym} 4050 -210 2 0 {name=l51}
+C {noconn.sym} 4050 -190 2 0 {name=l52}
+C {noconn.sym} 4050 -170 2 0 {name=l53}
+C {noconn.sym} 4050 -150 2 0 {name=l54}
+C {lab_pin.sym} 3780 350 0 0 {name=l45 sig_type=std_logic lab=io_analog[10]}
+C {lab_pin.sym} 4750 350 2 0 {name=l55 sig_type=std_logic lab=io_analog[9]}
+C {lab_pin.sym} 4030 150 3 1 {name=l56 sig_type=std_logic lab=gpio_noesd[7]}
+C {lab_pin.sym} 3890 -50 3 0 {name=l1 sig_type=std_logic lab=io_analog[5]}
+C {lab_pin.sym} 5660 160 1 0 {name=l2 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5720 160 1 0 {name=l3 sig_type=std_logic lab=vssa1}
+C {noconn.sym} 5240 580 3 0 {name=l4}
+C {noconn.sym} 5220 580 3 0 {name=l5}
+C {noconn.sym} 5200 580 3 0 {name=l7}
+C {noconn.sym} 5310 580 3 0 {name=l8}
+C {noconn.sym} 5290 580 3 0 {name=l9}
+C {noconn.sym} 5270 580 3 0 {name=l10}
+C {noconn.sym} 5330 580 3 0 {name=l11}
+C {noconn.sym} 5400 580 3 0 {name=l12}
+C {noconn.sym} 5380 580 3 0 {name=l57}
+C {noconn.sym} 5360 580 3 0 {name=l58}
+C {noconn.sym} 5430 580 3 0 {name=l59}
+C {noconn.sym} 5460 580 3 0 {name=l60}
+C {noconn.sym} 5480 580 3 0 {name=l61}
+C {noconn.sym} 5500 580 3 0 {name=l62}
+C {noconn.sym} 5520 580 3 0 {name=l63}
+C {noconn.sym} 5550 580 3 0 {name=l64}
+C {noconn.sym} 5570 580 3 0 {name=l65}
+C {noconn.sym} 5590 580 3 0 {name=l66}
+C {noconn.sym} 5610 580 3 0 {name=l67}
+C {noconn.sym} 5630 580 3 0 {name=l68}
+C {noconn.sym} 5650 580 3 0 {name=l69}
+C {noconn.sym} 5680 580 3 0 {name=l70}
+C {noconn.sym} 5700 580 3 0 {name=l71}
+C {noconn.sym} 5720 580 3 0 {name=l72}
+C {noconn.sym} 5740 580 3 0 {name=l73}
+C {noconn.sym} 5760 580 3 0 {name=l74}
+C {noconn.sym} 5780 580 3 0 {name=l75}
+C {noconn.sym} 5830 580 3 0 {name=l76}
+C {lab_pin.sym} 5200 150 1 0 {name=l77 sig_type=std_logic lab=iref_cp1}
+C {lab_pin.sym} 5030 350 0 0 {name=l78 sig_type=std_logic lab=io_analog[10]}
+C {lab_pin.sym} 6000 350 2 0 {name=l79 sig_type=std_logic lab=io_analog[8]}
+C {lab_pin.sym} 5280 150 3 1 {name=l80 sig_type=std_logic lab=gpio_noesd[7]}
+C {lab_pin.sym} 3990 -310 2 0 {name=l81 sig_type=std_logic lab=iref_cp1}
+C {top_pll_v2.sym} 5490 350 0 0 {name=x3}
+C {lab_pin.sym} 5340 150 3 1 {name=l47 sig_type=std_logic lab=gpio_noesd[8]}
+C {top_pll_v1.sym} 6710 350 0 0 {name=x4}
+C {lab_pin.sym} 6880 160 1 0 {name=l82 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 6940 160 1 0 {name=l83 sig_type=std_logic lab=vssa1}
+C {noconn.sym} 6460 580 3 0 {name=l84}
+C {noconn.sym} 6440 580 3 0 {name=l85}
+C {noconn.sym} 6420 580 3 0 {name=l86}
+C {noconn.sym} 6530 580 3 0 {name=l87}
+C {noconn.sym} 6510 580 3 0 {name=l88}
+C {noconn.sym} 6490 580 3 0 {name=l89}
+C {noconn.sym} 6550 580 3 0 {name=l90}
+C {noconn.sym} 6620 580 3 0 {name=l91}
+C {noconn.sym} 6600 580 3 0 {name=l92}
+C {noconn.sym} 6580 580 3 0 {name=l93}
+C {noconn.sym} 6650 580 3 0 {name=l94}
+C {noconn.sym} 6680 580 3 0 {name=l95}
+C {noconn.sym} 6700 580 3 0 {name=l96}
+C {noconn.sym} 6720 580 3 0 {name=l97}
+C {noconn.sym} 6740 580 3 0 {name=l98}
+C {noconn.sym} 6770 580 3 0 {name=l99}
+C {noconn.sym} 6790 580 3 0 {name=l100}
+C {noconn.sym} 6810 580 3 0 {name=l101}
+C {noconn.sym} 6830 580 3 0 {name=l102}
+C {noconn.sym} 6850 580 3 0 {name=l103}
+C {noconn.sym} 6870 580 3 0 {name=l104}
+C {noconn.sym} 6900 580 3 0 {name=l105}
+C {noconn.sym} 6920 580 3 0 {name=l106}
+C {noconn.sym} 6940 580 3 0 {name=l107}
+C {noconn.sym} 6960 580 3 0 {name=l108}
+C {noconn.sym} 6980 580 3 0 {name=l109}
+C {noconn.sym} 7000 580 3 0 {name=l110}
+C {noconn.sym} 7050 580 3 0 {name=l111}
+C {lab_pin.sym} 6420 150 1 0 {name=l112 sig_type=std_logic lab=iref_cp0}
+C {lab_pin.sym} 6250 350 0 0 {name=l113 sig_type=std_logic lab=io_analog[10]}
+C {lab_pin.sym} 7220 350 2 0 {name=l114 sig_type=std_logic lab=io_analog[7]}
+C {lab_pin.sym} 6500 150 3 1 {name=l115 sig_type=std_logic lab=gpio_noesd[7]}
+C {lab_pin.sym} 3990 -330 2 0 {name=l46 sig_type=std_logic lab=iref_cp0}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 4540 -270 0 0 {name=C1 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X}
+C {lab_pin.sym} 4540 -360 1 0 {name=l116 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4540 -180 3 0 {name=l117 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 4680 -270 0 0 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X}
+C {lab_pin.sym} 4680 -360 1 0 {name=l118 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4680 -180 3 0 {name=l119 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 4820 -270 0 0 {name=C3 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X}
+C {lab_pin.sym} 4820 -360 1 0 {name=l120 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4820 -180 3 0 {name=l121 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5050 -270 0 0 {name=C4 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5050 -360 1 0 {name=l122 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5050 -180 3 0 {name=l123 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5190 -270 0 0 {name=C5 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5190 -360 1 0 {name=l124 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5190 -180 3 0 {name=l125 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5330 -270 0 0 {name=C6 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5330 -360 1 0 {name=l126 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5330 -180 3 0 {name=l127 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5470 -270 0 0 {name=C7 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5470 -360 1 0 {name=l128 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5470 -180 3 0 {name=l129 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5600 -270 0 0 {name=C8 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5600 -360 1 0 {name=l130 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5600 -180 3 0 {name=l131 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5750 -270 0 0 {name=C9 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5750 -360 1 0 {name=l132 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5750 -180 3 0 {name=l133 sig_type=std_logic lab=vssa1}
diff --git a/xschem/xschemrc b/xschem/xschemrc
index 98fead5..1401099 100644
--- a/xschem/xschemrc
+++ b/xschem/xschemrc
@@ -14,26 +14,23 @@
###########################################################################
#### XSCHEM SYSTEM-WIDE DESIGN LIBRARY PATHS: XSCHEM_LIBRARY_PATH
###########################################################################
-#### If unset xschem starts with XSCHEM_LIBRARY_PATH set to the default, typically:
-# /home/schippes/.xschem/xschem_library
-# /home/schippes/share/xschem/xschem_library/devices
-# /home/schippes/share/doc/xschem/examples
-# /home/schippes/share/doc/xschem/ngspice
-# /home/schippes/share/doc/xschem/logic
-# /home/schippes/share/doc/xschem/xschem_simulator
-# /home/schippes/share/doc/xschem/binto7seg
-# /home/schippes/share/doc/xschem/pcb
-# /home/schippes/share/doc/xschem/rom8k
-
-#### Flush any previous definition
set XSCHEM_LIBRARY_PATH {}
-#### include devices/*.sym
-append XSCHEM_LIBRARY_PATH ${XSCHEM_SHAREDIR}/xschem_library
-#### include skywater libraries. Here i use [pwd]. This works if i start xschem from here.
+### GENERAL PURPOSE LIB
+append XSCHEM_LIBRARY_PATH :${XSCHEM_SHAREDIR}/xschem_library
+### EXAMPLES LIB
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/examples
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/ngspice
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/logic
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/xschem_simulator
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/binto7seg
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/pcb
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/rom8k
+### SKY130 PDK SYMBOLS LIB
+append XSCHEM_LIBRARY_PATH :~/skywater/xschem_sky130
+### USERs CELLS LIB
+append XSCHEM_LIBRARY_PATH :~/caravel_analog_fulgor/xschem
+### CURRENT CELL LIB
append XSCHEM_LIBRARY_PATH :$env(PWD)
-append XSCHEM_LIBRARY_PATH :/usr/share/pdk/sky130A/libs.tech/xschem
-#### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem)
-append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library
###########################################################################
#### SET CUSTOM COLORS FOR XSCHEM LIBRARIES MATCHING CERTAIN PATTERNS
@@ -47,6 +44,7 @@
set dircolor(xschem_sky130$) blue
set dircolor(xschem_library$) red
set dircolor(devices$) red
+set dircolor(sky130-mpw2-fulgor) green
###########################################################################
#### WINDOW TO OPEN ON STARTUP: XSCHEM_START_WINDOW
@@ -54,14 +52,14 @@
#### Start without a design if no filename given on command line:
#### To avoid absolute paths, use a path that is relative to one of the
#### XSCHEM_LIBRARY_PATH directories. Default: empty
-set XSCHEM_START_WINDOW {sky130_tests/top.sch}
+# set XSCHEM_START_WINDOW {sky130_tests/top.sch}
###########################################################################
#### DIRECTORY WHERE SIMULATIONS, NETLIST AND SIMULATOR OUTPUTS ARE PLACED
###########################################################################
#### If unset $USER_CONF_DIR/simulations is assumed (normally ~/.xschem/simulations)
# set netlist_dir $env(HOME)/.xschem/simulations
-set netlist_dir .
+set netlist_dir $env(PWD)/simulations
###########################################################################
#### CHANGE DEFAULT [] WITH SOME OTHER CHARACTERS FOR BUSSED SIGNALS
@@ -237,7 +235,7 @@
###########################################################################
#### set gaw address for socket connection: {host port}
#### default: set to localhost, port 2020
-# set gaw_tcp_address {localhost 2020}
+ set gaw_tcp_address {localhost 2020}
###########################################################################
#### XSCHEM LISTEN TO TCP PORT
@@ -258,7 +256,7 @@
#### list of tcl files to preload.
# lappend tcl_files ${XSCHEM_SHAREDIR}/change_index.tcl
lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl
-lappend tcl_files /usr/share/pdk/sky130A/libs.tech/xschem/scripts/sky130_models.tcl
+lappend tcl_files ~/skywater/pdk/skywater130/sky130A/libs.tech/xschem/scripts/sky130_models.tcl
###########################################################################
#### XSCHEM TOOLBAR
###########################################################################
@@ -269,5 +267,5 @@
###########################################################################
#### SKYWATER PDK SPECIFIC VARIABLES
###########################################################################
-set SKYWATER_MODELS ~/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest
-set SKYWATER_STDCELLS ~/skywater-pdk/libraries/sky130_fd_sc_hd/latest
+set SKYWATER_MODELS ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest
+set SKYWATER_STDCELLS ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest
