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sky130
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mpw-002
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slot-029
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5c4153e4dbb0e06e50a362ba02b6dc52814a81a6
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xschem
tree: 94ec40f87bde2a96674c1b207f877e91b143f896 [
path history
]
[
tgz
]
afernandez_residue_amplifier/
simulations/
.spiceinit
analog_wrapper_tb.sch
and_pfd.sch
and_pfd.sym
bias.sch
bias.sym
bias_pex_c.sym
buffer_salida.sch
buffer_salida.sym
buffer_salida_pex_c.sym
cap1_loop_filter.sch
cap1_loop_filter.sym
cap2_loop_filter.sch
cap2_loop_filter.sym
cap3_loop_filter.sch
cap3_loop_filter.sym
charge_pump.sch
charge_pump.sym
charge_pump_pex_c.sym
clock_inverter.sch
clock_inverter.sym
csvco.sch
csvco.sym
csvco_branch.sch
csvco_branch.sym
csvco_branch_v2.sch
csvco_branch_v2.sym
csvco_pex_c.sym
csvco_v2.sch
csvco_v2.sym
csvco_v2_pex_c.sym
DFF.sch
DFF.sym
dff_pfd_pex_c.sym
DFlipFlop.sch
DFlipFlop.sym
div_by_2.sch
div_by_2.sym
div_by_2_pex_c.sym
div_by_5.sch
div_by_5.sym
div_by_5_pex_c.sym
example_por.sch
example_por.sym
example_por_tb.sch
example_por_tb.spice.orig
inverter_cp_x1.sch
inverter_cp_x1.sym
inverter_cp_x2.sch
inverter_cp_x2.sym
inverter_csvco.sch
inverter_csvco.sym
inverter_csvco_pex_c.sym
inverter_min_x2.sch
inverter_min_x2.sym
inverter_min_x2_pex_c.sym
inverter_min_x4.sch
inverter_min_x4.sym
inverter_min_x4_pex_c.sym
latch_diff.sch
latch_diff.sym
loop_filter.sch
loop_filter.sym
loop_filter_pex_c.sym
loop_filter_v2.sch
loop_filter_v2.sym
nor.sch
nor.sym
PFD.sch
PFD.sym
pfd_cp_interface.sch
pfd_cp_interface.sym
pfd_cp_interface_pex_c.sym
PFD_pex_c.sym
res_loop_filter.sch
res_loop_filter.sym
ring_osc_buffer.sch
ring_osc_buffer.sym
ring_osc_buffer_pex_c.sym
tb_buffer_salida.sch
tb_buffer_salida_pex_c.sch
tb_charge_pump.sch
tb_csvco.sch
tb_csvco_pex_c.sch
tb_csvco_v2.sch
tb_csvco_v2_pex_c.sch
tb_DFF.sch
tb_div_by_2.sch
tb_div_by_2_pex_c.sch
tb_div_by_5.sch
tb_div_by_5_pex_c.sch
tb_inverter_csvco.sch
tb_loop_filter.sch
tb_PFD.sch
tb_PFD_pex.sch
tb_top_pll_v1.sch
tb_top_pll_v1_pex_c.sch
tb_top_pll_v1_pex_no_integration.sch
tb_top_pll_v2_pex_c.sch
top_pll_v1.sch
top_pll_v1.sym
top_pll_v1_pex_c.sym
top_pll_v1_pex_no_integration.sch
top_pll_v1_pex_no_integration.sym
top_pll_v2.sch
top_pll_v2.sym
top_pll_v2_pex_c.sym
top_pll_v2_pex_no_integration.sym
trans_gate.sch
trans_gate.sym
user_analog_project_wrapper.sch
user_analog_project_wrapper.sym
xschemrc