PLL v3 Final
diff --git a/checks/user_analog_project_wrapper.magic.drc.mag b/checks/user_analog_project_wrapper.magic.drc.mag
index a847a77..0dbcdb3 100644
--- a/checks/user_analog_project_wrapper.magic.drc.mag
+++ b/checks/user_analog_project_wrapper.magic.drc.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624402378
+timestamp 1624899567
<< checkpaint >>
rect -4732 -4732 588732 708732
<< nwell >>
@@ -210,10 +210,10 @@
rect 119059 659956 119177 660062
rect 125643 660015 133067 660062
rect 112601 659944 119177 659956
-rect 157073 659872 198016 659901
-rect 157073 659500 157102 659872
-rect 197986 659500 198016 659872
-rect 157073 659472 198016 659500
+rect 157078 659797 192335 659803
+rect 157078 659489 157112 659797
+rect 192300 659489 192335 659797
+rect 157078 659483 192335 659489
rect 12990 659361 14703 659415
rect 12990 659117 13082 659361
rect 14606 659270 14703 659361
@@ -276,6 +276,7 @@
rect 149987 657421 150019 658497
rect 152311 658062 156268 658497
rect 152311 657778 157347 658062
+rect 206380 657846 208306 658174
rect 152311 657421 156268 657778
rect 149987 657395 156268 657421
rect 149997 657379 156268 657395
@@ -288,7 +289,6 @@
rect 112660 657160 112812 657175
rect 112685 656533 112741 657160
rect 197704 657121 199952 657125
-rect 156207 656708 157418 657036
rect 197704 657005 197714 657121
rect 199942 657005 199952 657121
rect 197704 657001 199952 657005
@@ -296,35 +296,25 @@
rect 112626 656350 112658 656530
rect 112774 656350 112807 656530
rect 112626 656348 112807 656350
-rect 156207 656248 156786 656708
-rect 186130 656688 186235 656702
-rect 186130 656636 186156 656688
-rect 186208 656636 186235 656688
-rect 186130 656623 186235 656636
-rect 186152 656414 186208 656623
-rect 186119 656391 186251 656414
-rect 186119 656339 186159 656391
-rect 186211 656339 186251 656391
-rect 186119 656316 186251 656339
rect 12125 655528 13406 655533
rect 12125 655200 14468 655528
rect 133382 655200 135242 655528
rect 12125 652870 13406 655200
rect 134093 653281 135239 655200
-rect 207475 654986 208245 655013
-rect 206694 654658 208245 654986
rect 12125 651670 15784 652870
rect 132088 652146 135239 653281
-rect 207475 652403 208245 654658
rect 132558 652135 135239 652146
rect 12125 651669 15583 651670
rect 12125 651650 13406 651669
-rect 205405 651403 208245 652403
-rect 205405 651383 207885 651403
+rect 207978 650936 208306 657846
+rect 204923 650607 208306 650936
rect 124847 637259 125452 637281
rect 124847 637079 124867 637259
rect 125431 637079 125452 637259
rect 124847 637057 125452 637079
+rect 198050 633274 198749 633275
+rect 198050 633158 198085 633274
+rect 198713 633158 198749 633274
<< via1 >>
rect 202971 687844 206543 688216
rect 207137 687822 210581 688194
@@ -368,7 +358,7 @@
rect 112698 660105 119059 660211
rect 120283 660121 133007 660213
rect 112671 659956 119059 660105
-rect 157102 659500 197986 659872
+rect 157112 659489 192300 659797
rect 13082 659117 14606 659361
rect 133095 659181 133339 659297
rect 66198 657901 68554 659105
@@ -383,9 +373,8 @@
rect 112742 657175 112794 657227
rect 197714 657005 199942 657121
rect 112658 656350 112774 656530
-rect 186156 656636 186208 656688
-rect 186159 656339 186211 656391
rect 124867 637079 125431 637259
+rect 198085 633158 198713 633274
<< metal2 >>
rect 211169 688677 214642 688713
rect 207123 688597 210596 688633
@@ -478,7 +467,6 @@
rect 23042 660091 64025 660111
rect 83756 660453 83777 660482
rect 124073 660455 124085 660820
-rect 157083 660495 197708 660512
rect 83756 660017 83774 660453
rect 124073 660429 133038 660455
rect 112306 660017 112671 660204
@@ -491,9 +479,12 @@
rect 119059 659999 120418 660096
rect 119059 659956 119074 659999
rect 112657 659943 119074 659956
+rect 157088 659949 192325 659970
rect 2509 659751 14155 659826
rect 2509 658735 2684 659751
rect 5060 659386 14155 659751
+rect 157088 659797 157118 659949
+rect 192294 659797 192325 659949
rect 133210 659530 140004 659630
rect 5060 659361 14624 659386
rect 5060 659117 13082 659361
@@ -516,12 +507,9 @@
rect 82306 658010 82308 658946
rect 133210 658914 137615 659165
rect 139911 658914 140004 659530
-rect 157083 659479 157087 660495
-rect 197703 659911 197708 660495
-rect 197703 659872 198006 659911
-rect 197986 659500 198006 659872
-rect 197703 659479 198006 659500
-rect 157083 659462 198006 659479
+rect 157088 659489 157112 659797
+rect 192300 659489 192325 659797
+rect 157088 659473 192325 659489
rect 133210 658850 140004 658914
rect 206714 659004 212383 659085
rect 206714 658768 209991 659004
@@ -582,33 +570,47 @@
rect 73065 656237 73099 656678
rect 74035 656488 74069 657013
rect 197714 656991 199942 657005
-rect 186140 656691 186225 656712
-rect 186140 656688 188420 656691
-rect 186140 656636 186156 656688
-rect 186208 656636 188420 656688
-rect 186140 656635 188420 656636
-rect 186140 656613 186225 656635
+rect 152610 656633 153833 656668
rect 112636 656530 112797 656543
rect 112636 656488 112658 656530
rect 74035 656363 112658 656488
rect 74035 656237 74069 656363
rect 112636 656350 112658 656363
rect 112774 656350 112797 656530
+rect 152610 656497 152633 656633
+rect 153809 656631 153833 656633
+rect 188217 656631 188447 656703
+rect 153809 656572 188447 656631
+rect 153809 656500 188350 656572
+rect 153809 656497 153833 656500
+rect 152610 656462 153833 656497
rect 112636 656338 112797 656350
-rect 152623 656393 186037 656431
-rect 186129 656393 186241 656424
-rect 152623 656391 186241 656393
-rect 152623 656376 186159 656391
-rect 152623 656300 152664 656376
rect 73065 656212 74069 656237
-rect 152633 656160 152664 656300
-rect 153760 656339 186159 656376
-rect 186211 656339 186241 656391
-rect 153760 656337 186241 656339
-rect 153760 656300 186037 656337
-rect 186129 656306 186241 656337
-rect 153760 656160 153791 656300
-rect 152633 656124 153791 656160
+rect 227813 652897 229004 652923
+rect 227813 652892 227820 652897
+rect 206387 652765 227820 652892
+rect 227813 652761 227820 652765
+rect 228996 652892 229004 652897
+rect 228996 652765 229031 652892
+rect 228996 652761 229004 652765
+rect 227813 652735 229004 652761
+rect 242313 649992 243530 650024
+rect 242313 649986 242333 649992
+rect 190876 649859 242333 649986
+rect 242313 649856 242333 649859
+rect 243509 649856 243530 649992
+rect 242313 649825 243530 649856
+rect 181565 649795 181650 649802
+rect 235261 649800 236482 649821
+rect 235261 649795 235283 649800
+rect 181562 649759 235283 649795
+rect 181562 649703 181579 649759
+rect 181635 649703 235283 649759
+rect 181562 649668 235283 649703
+rect 181565 649661 181650 649668
+rect 235261 649664 235283 649668
+rect 236459 649664 236482 649800
+rect 235261 649643 236482 649664
rect 144160 637398 145498 637413
rect 144160 637369 144161 637398
rect 125227 637291 144161 637369
@@ -630,6 +632,18 @@
rect 368680 633602 368719 633658
rect 368775 633602 368815 633658
rect 368680 633573 368815 633602
+rect 198060 633274 198739 633285
+rect 198060 633158 198085 633274
+rect 198713 633264 198739 633274
+rect 198713 633158 198742 633264
+rect 198060 633148 198742 633158
+rect 144162 632611 145484 632657
+rect 144162 631515 144195 632611
+rect 145451 632587 145484 632611
+rect 198066 632587 198742 633148
+rect 145451 631539 198743 632587
+rect 145451 631515 145484 631539
+rect 144162 631470 145484 631515
rect 152624 510668 153820 510686
rect 152624 510561 152634 510668
rect 1323 510535 152634 510561
@@ -649,6 +663,37 @@
rect 145449 467018 145524 467314
rect 2155 467017 145524 467018
rect 1326 466990 145524 467017
+rect 227798 424148 229007 424169
+rect 227798 424126 227814 424148
+rect 939 424100 227814 424126
+rect 939 423804 992 424100
+rect 1768 423804 227814 424100
+rect 939 423777 227814 423804
+rect 227798 423772 227814 423777
+rect 228990 424126 229007 424148
+rect 228990 423777 229019 424126
+rect 228990 423772 229007 423777
+rect 227798 423752 229007 423772
+rect 235266 380914 236476 380933
+rect 235266 380904 235283 380914
+rect 1129 380878 235283 380904
+rect 1129 380582 1182 380878
+rect 1958 380582 235283 380878
+rect 1129 380555 235283 380582
+rect 235266 380538 235283 380555
+rect 236459 380904 236476 380914
+rect 236459 380555 236523 380904
+rect 236459 380538 236476 380555
+rect 235266 380520 236476 380538
+rect 242303 337677 243532 337700
+rect 1042 337653 243556 337677
+rect 1042 337651 242329 337653
+rect 1042 337355 1095 337651
+rect 1871 337357 242329 337651
+rect 243505 337357 243556 337653
+rect 1871 337355 243556 337357
+rect 1042 337328 243556 337355
+rect 242303 337310 243532 337328
rect 524 -800 636 480
rect 1706 -800 1818 480
rect 2888 -800 3000 480
@@ -1181,6 +1226,7 @@
rect 119059 660204 120283 660328
rect 120283 660204 124073 660429
rect 2684 658735 5060 659751
+rect 157118 659797 192294 659949
rect 66188 659105 68564 659131
rect 66188 657901 66198 659105
rect 66198 657901 68554 659105
@@ -1190,10 +1236,7 @@
rect 79868 658010 82288 658946
rect 82288 658010 82306 658946
rect 137615 658914 139911 659530
-rect 157087 659872 197703 660495
-rect 157087 659500 157102 659872
-rect 157102 659500 197703 659872
-rect 157087 659479 197703 659500
+rect 157118 659493 192294 659797
rect 21167 657656 23623 657679
rect 21167 657543 21190 657656
rect 21190 657543 23610 657656
@@ -1236,15 +1279,26 @@
rect 199720 657035 199776 657091
rect 199800 657035 199856 657091
rect 199880 657035 199936 657091
-rect 152664 656160 153760 656376
+rect 152633 656497 153809 656633
+rect 227820 652761 228996 652897
+rect 242333 649856 243509 649992
+rect 181579 649703 181635 649759
+rect 235283 649664 236459 649800
rect 144161 636942 145497 637398
rect 368720 635440 368776 635496
rect 368719 633602 368775 633658
+rect 144195 631515 145451 632611
rect 1376 510239 2152 510535
rect 73033 510292 74049 510508
rect 152634 510212 153810 510668
rect 1379 467017 2155 467313
rect 144193 467018 145449 467314
+rect 992 423804 1768 424100
+rect 227814 423772 228990 424148
+rect 1182 380582 1958 380878
+rect 235283 380538 236459 380914
+rect 1095 337355 1871 337651
+rect 242329 337357 243505 337653
<< metal3 >>
rect 16194 702300 21194 704800
rect 68194 702300 73194 704800
@@ -1402,10 +1456,13 @@
rect 190367 664818 190393 667282
rect 192857 664818 192884 667282
rect 190367 664796 192884 664818
-rect 157073 660499 197718 660507
-rect 157073 659475 157083 660499
-rect 197707 659475 197718 660499
-rect 157073 659467 197718 659475
+rect 157078 660211 192337 660235
+rect 157078 659507 157115 660211
+rect 192299 659507 192337 660211
+rect 157078 659493 157118 659507
+rect 192294 659493 192337 659507
+rect 157078 659483 192337 659493
+rect 157078 659478 192335 659483
rect 149955 657411 150017 658507
rect 152313 657411 152455 658507
rect 149955 657301 152455 657411
@@ -1502,15 +1559,19 @@
rect 199856 657035 199880 657091
rect 199936 657035 199952 657091
rect 197704 656996 199952 657035
-rect 152609 656376 153837 656431
-rect 152609 656160 152664 656376
-rect 153760 656160 153837 656376
+rect 152600 656633 153843 656663
+rect 152600 656497 152633 656633
+rect 153809 656497 153843 656633
+rect 152600 656467 153843 656497
rect 137480 607191 137770 611815
rect 139754 607191 139980 611815
rect 137480 607076 139980 607191
rect 144145 637398 145521 637418
rect 144145 636942 144161 637398
rect 145497 636942 145521 637398
+rect 144145 632611 145521 636942
+rect 144145 631515 144195 632611
+rect 145451 631515 145521 632611
rect 72999 510292 73033 510508
rect 74049 510292 74122 510508
rect 72999 510192 74122 510292
@@ -1527,12 +1588,17 @@
rect 1351 467017 1379 467118
rect 2155 467017 2184 467313
rect 1351 467009 2184 467017
-rect 144145 467314 145521 636942
-rect 152609 510668 153837 656160
-rect 156490 624090 206846 624128
-rect 156490 620746 156516 624090
-rect 206820 620746 206846 624090
-rect 156490 620709 206846 620746
+rect 144145 467314 145521 631515
+rect 152609 510668 153837 656467
+rect 181564 649797 181652 653612
+rect 181555 649759 181660 649797
+rect 181555 649703 181579 649759
+rect 181635 649703 181660 649759
+rect 181555 649666 181660 649703
+rect 155874 620699 207412 620718
+rect 155874 618155 155891 620699
+rect 207395 618155 207412 620699
+rect 155874 618137 207412 618155
rect 209899 611719 212399 658388
rect 296890 658340 299390 688285
rect 301225 661655 303725 691142
@@ -1581,6 +1647,26 @@
rect 296880 655858 296908 658322
rect 299372 655858 299400 658322
rect 296880 655840 299400 655858
+rect 209899 607175 210159 611719
+rect 212223 607175 212399 611719
+rect 209899 606979 212399 607175
+rect 227791 652897 229019 652943
+rect 227791 652761 227820 652897
+rect 228996 652761 229019 652897
+rect 152609 510212 152634 510668
+rect 153810 510212 153837 510668
+rect 152609 510169 153837 510212
+rect 144145 467018 144193 467314
+rect 145449 467018 145521 467314
+rect 144145 466948 145521 467018
+rect -800 465944 480 466056
+rect -800 464872 1188 464874
+rect -800 464762 1508 464872
+rect 253 464760 1508 464762
+rect -800 463580 480 463692
+rect -800 462398 480 462510
+rect -800 425086 480 425198
+rect 227791 424164 229019 652761
rect 325555 650863 328055 692621
rect 582300 681668 584800 682984
rect 576277 681650 584800 681668
@@ -1610,6 +1696,54 @@
rect 367507 655858 367520 658322
rect 366150 655840 367520 655858
rect 325545 650845 328065 650863
+rect 242308 650019 243536 650034
+rect 242303 649992 243540 650019
+rect 242303 649856 242333 649992
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+rect 255 424016 992 424017
+rect -800 423905 992 424016
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+rect -800 419176 480 419288
+rect -800 381864 480 381976
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+rect 1154 380582 1182 380683
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+rect -800 379500 480 379612
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+rect -800 377136 480 377248
+rect -800 375954 480 376066
+rect -800 338642 480 338754
+rect 242308 337695 243536 649830
rect 325545 648381 325573 650845
rect 328037 648381 328065 650845
rect 325545 648363 328065 648381
@@ -1689,35 +1823,18 @@
rect 352226 613265 360609 613751
rect 360123 612028 360609 613265
rect 365504 613072 365990 614551
-rect 209899 607175 210159 611719
-rect 212223 607175 212399 611719
-rect 209899 606979 212399 607175
-rect 152609 510212 152634 510668
-rect 153810 510212 153837 510668
-rect 152609 510169 153837 510212
-rect 144145 467018 144193 467314
-rect 145449 467018 145521 467314
-rect 144145 466948 145521 467018
-rect -800 465944 480 466056
-rect -800 464872 1188 464874
-rect -800 464762 1508 464872
-rect 253 464760 1508 464762
-rect -800 463580 480 463692
-rect -800 462398 480 462510
-rect -800 425086 480 425198
-rect -800 423904 480 424016
-rect -800 422722 480 422834
-rect -800 421540 480 421652
-rect -800 420358 480 420470
-rect -800 419176 480 419288
-rect -800 381864 480 381976
-rect -800 380682 480 380794
-rect -800 379500 480 379612
-rect -800 378318 480 378430
-rect -800 377136 480 377248
-rect -800 375954 480 376066
-rect -800 338642 480 338754
-rect -800 337460 480 337572
+rect 1067 337651 1900 337659
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rect -800 336278 480 336390
rect -800 335096 480 335208
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@@ -1909,11 +2026,10 @@
rect 223943 694942 226247 697326
rect 207618 690349 209922 692333
rect 190393 664818 192857 667282
-rect 157083 660495 197707 660499
-rect 157083 659479 157087 660495
-rect 157087 659479 197703 660495
-rect 197703 659479 197707 660495
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+rect 157115 659949 192299 660211
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+rect 192294 659507 192299 659949
rect 242750 699652 245214 702116
rect 228987 694956 231291 697340
rect 227301 688638 230725 688661
@@ -1927,7 +2043,7 @@
rect 202813 684733 247033 684734
rect 202809 684094 247033 684733
rect 137770 607191 139754 611815
-rect 156516 620746 206820 624090
+rect 155891 618155 207395 620699
rect 510534 696916 525638 703060
rect 567893 696734 570357 698718
rect 414582 693939 417046 696403
@@ -1937,6 +2053,7 @@
rect 305196 662188 307660 664652
rect 301243 659173 303707 661637
rect 296908 655858 299372 658322
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rect 576304 679186 578288 681650
rect 373478 669246 374822 671710
rect 371791 665676 373135 668140
@@ -1951,7 +2068,6 @@
rect 360271 628385 360655 628609
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-rect 210159 607175 212223 611719
rect 578781 540220 583165 555644
rect 578420 225391 583284 240335
rect 578908 136621 583772 151565
@@ -2107,17 +2223,17 @@
rect 64001 660133 64018 661237
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rect 124070 660201 124085 661465
-rect 157083 661364 197702 661420
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@@ -2256,15 +2372,15 @@
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rect 259670 617214 259688 625130
rect 275284 625028 275302 625130
rect 275284 624590 345528 625028
@@ -2476,8 +2592,8 @@
rect 83807 661465 124043 662744
rect 23091 660233 63967 661237
rect 83807 660268 124043 661465
-rect 157114 660499 197670 661364
-rect 157114 659528 197670 660499
+rect 157154 660211 192270 660453
+rect 157154 659577 192270 660211
rect 356712 643658 356948 643894
rect 359098 643658 359334 643894
rect 360343 637289 360579 637525
@@ -2500,8 +2616,10 @@
rect 83169 622046 133393 624590
rect 133393 622046 133468 624590
rect 82992 617995 133468 622046
-rect 156528 620746 206684 623973
-rect 156528 619257 206684 620746
+rect 156014 620699 207450 620875
+rect 156014 618155 207395 620699
+rect 207395 618155 207450 620699
+rect 156014 617119 207450 618155
rect 259688 617214 275284 625130
rect 311401 617634 345237 624590
rect 380249 623593 380485 623829
@@ -2691,26 +2809,26 @@
rect 100463 432468 116619 583242
rect 124759 599200 126962 599322
rect 147647 599200 151189 672301
-rect 171295 661444 184887 673086
+rect 171295 660571 184887 673086
rect 216554 673059 216598 677775
rect 232194 673059 232247 677775
rect 216554 673051 232247 673059
rect 259666 678032 275332 678276
rect 216554 672970 232239 673051
-rect 157059 661364 197726 661444
-rect 157059 659528 157114 661364
-rect 197670 659528 197726 661364
-rect 157059 659448 197726 659528
-rect 156352 624096 206860 624111
-rect 156352 623973 207124 624096
-rect 156352 619257 156528 623973
-rect 206684 619257 207124 623973
-rect 156352 619120 207124 619257
+rect 157064 660453 192360 660571
+rect 157064 659577 157154 660453
+rect 192270 659577 192360 660453
+rect 157064 659459 192360 659577
+rect 171295 659368 184887 659459
+rect 155860 620875 207605 620993
+rect 155860 617119 156014 620875
+rect 207450 617119 207605 620875
+rect 155860 617001 207605 617119
rect 154493 599200 154813 599217
rect 124759 599156 154813 599200
rect 124759 583560 124972 599156
rect 154648 583560 154813 599156
-rect 172171 598789 188327 619120
+rect 172171 598789 188327 617001
rect 218723 615607 222084 672970
rect 259666 672036 260541 678032
rect 274857 672036 275332 678032
@@ -3453,72 +3571,72 @@
rect 338617 136437 354407 136579
use mimcap_decoup_1x5 mimcap_decoup_1x5_6
array 0 0 34500 0 2 6522
-timestamp 1624402378
+timestamp 1624899567
transform 1 0 38481 0 1 560871
box 0 -159 34500 6363
-use top_pll_v1 top_pll_v1_1
-timestamp 1624402378
+use top_pll_v1 top_pll_v1_0
+timestamp 1624899567
transform 1 0 14782 0 1 657248
box -656 -33693 50195 2860
use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_2
array 0 0 6724 0 8 6522
-timestamp 1624402378
+timestamp 1624899567
transform 1 0 74005 0 1 616157
box -3351 -3261 3373 3261
use top_pll_v2 top_pll_v2_0
-timestamp 1624402378
+timestamp 1624899567
transform -1 0 133068 0 1 657248
box -656 -33693 50195 2860
+use top_pll_v3 top_pll_v3_0
+timestamp 1624899567
+transform -1 0 206380 0 1 656706
+box -656 -37093 50195 2860
use mimcap_decoup_1x5 mimcap_decoup_1x5_5
array 0 0 34500 0 2 6522
-timestamp 1624402378
+timestamp 1624899567
transform 1 0 126717 0 1 559996
box 0 -159 34500 6363
use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_1
array 0 0 6724 0 8 6522
-timestamp 1624402378
+timestamp 1624899567
transform 1 0 144463 0 1 616442
box -3351 -3261 3373 3261
-use top_pll_v1 top_pll_v1_0
-timestamp 1624402378
-transform -1 0 206380 0 1 656706
-box -656 -33693 50195 2860
use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_0
array 0 0 6724 0 6 6522
-timestamp 1624402378
+timestamp 1624899567
transform 1 0 220679 0 1 616773
box -3351 -3261 3373 3261
use mimcap_decoup_1x5 mimcap_decoup_1x5_4
array 0 0 34500 0 2 6522
-timestamp 1624402378
+timestamp 1624899567
transform 1 0 197202 0 1 560156
box 0 -159 34500 6363
use bias bias_0
-timestamp 1624402378
+timestamp 1624899567
transform 1 0 202834 0 -1 687483
box -54 -412 44317 2238
use mimcap_decoup_1x5 mimcap_decoup_1x5_3
array 0 0 34500 0 1 6522
-timestamp 1624402378
+timestamp 1624899567
transform -1 0 345445 0 1 602155
box 0 -159 34500 6363
use mimcap_decoup_1x5 mimcap_decoup_1x5_2
array 0 0 34500 0 2 6522
-timestamp 1624402378
+timestamp 1624899567
transform 1 0 291410 0 1 559700
box 0 -159 34500 6363
use res_amp_top res_amp_top_0
-timestamp 1624402378
+timestamp 1624899567
transform 1 0 349695 0 1 630386
box -5005 -972 31038 12726
use mimcap_decoup_1x5 mimcap_decoup_1x5_1
array 0 0 34500 0 2 6522
-timestamp 1624402378
+timestamp 1624899567
transform 1 0 382888 0 1 560156
box 0 -159 34500 6363
use mimcap_decoup_1x5 mimcap_decoup_1x5_0
array 0 0 34500 0 2 6522
-timestamp 1624402378
+timestamp 1624899567
transform 1 0 489384 0 1 560611
box 0 -159 34500 6363
<< labels >>
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index d028b24..cd1a469 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/afernandez_residue_amplifier/res_amp_sync_v2.mag b/mag/afernandez_residue_amplifier/res_amp_sync_v2.mag
index eefade3..432787b 100644
--- a/mag/afernandez_residue_amplifier/res_amp_sync_v2.mag
+++ b/mag/afernandez_residue_amplifier/res_amp_sync_v2.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624402156
+timestamp 1624896651
<< nwell >>
rect 3636 6239 4733 7015
rect 7538 6935 8332 7015
@@ -352,24 +352,24 @@
rect 2926 -1313 5650 -1241
rect 5909 -1313 5910 -1241
rect -92 -1314 5910 -1313
-use DFlipFlop DFlipFlop_4
-timestamp 1624049879
-transform 1 0 4910 0 -1 879
+use DFlipFlop DFlipFlop_2
+timestamp 1624885207
+transform 1 0 1926 0 1 879
box -1244 0 1740 3068
use DFlipFlop DFlipFlop_3
-timestamp 1624049879
+timestamp 1624885207
transform 1 0 1926 0 -1 879
box -1244 0 1740 3068
-use DFlipFlop DFlipFlop_2
-timestamp 1624049879
-transform 1 0 1926 0 1 879
+use DFlipFlop DFlipFlop_4
+timestamp 1624885207
+transform 1 0 4910 0 -1 879
box -1244 0 1740 3068
use nand_logic nand_logic_0
timestamp 1623952422
transform 1 0 3885 0 1 3205
box -219 -731 833 707
use DFlipFlop DFlipFlop_0
-timestamp 1624049879
+timestamp 1624885207
transform 1 0 1926 0 1 3947
box -1244 0 1740 3068
use inverter_min_x16 inverter_min_x16_0
@@ -393,7 +393,7 @@
transform 1 0 4771 0 1 3224
box -53 -616 665 643
use DFlipFlop DFlipFlop_1
-timestamp 1624049879
+timestamp 1624885207
transform 1 0 5798 0 1 3947
box -1244 0 1740 3068
use inverter_min_x4 inverter_min_x4_0
diff --git a/mag/afernandez_residue_amplifier/res_amp_top.mag b/mag/afernandez_residue_amplifier/res_amp_top.mag
index cf22c7f..2327992 100644
--- a/mag/afernandez_residue_amplifier/res_amp_top.mag
+++ b/mag/afernandez_residue_amplifier/res_amp_top.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624471326
+timestamp 1624896651
<< nwell >>
rect 18234 4138 21604 4172
<< pwell >>
@@ -906,26 +906,26 @@
rect 20467 -611 20491 -605
rect 19795 -635 20491 -611
rect -4958 -972 -4262 -948
-use sky130_fd_pr__cap_mim_m3_1_U5ZKVF sky130_fd_pr__cap_mim_m3_1_U5ZKVF_0
-timestamp 1624471326
-transform 1 0 16786 0 1 6344
-box -700 -850 699 850
-use sky130_fd_pr__cap_mim_m3_1_U5ZKVF sky130_fd_pr__cap_mim_m3_1_U5ZKVF_1
-timestamp 1624471326
-transform 1 0 16786 0 1 1968
-box -700 -850 699 850
use res_amp_lin_prog res_amp_lin_prog_0
-timestamp 1624397222
+timestamp 1624402156
transform 1 0 -5726 0 1 -7077
box 5835 7077 21302 14799
use res_amp_sync_v2 res_amp_sync_v2_0
-timestamp 1624397222
+timestamp 1624896651
transform 1 0 -899 0 1 4870
box -92 -2189 8342 7015
use source_follower_buff_diff source_follower_buff_diff_0
timestamp 1624113565
transform 1 0 17170 0 1 1168
box 863 -174 10692 6158
+use sky130_fd_pr__cap_mim_m3_1_U5ZKVF sky130_fd_pr__cap_mim_m3_1_U5ZKVF_1
+timestamp 1624471326
+transform 1 0 16786 0 1 1968
+box -700 -850 699 850
+use sky130_fd_pr__cap_mim_m3_1_U5ZKVF sky130_fd_pr__cap_mim_m3_1_U5ZKVF_0
+timestamp 1624471326
+transform 1 0 16786 0 1 6344
+box -700 -850 699 850
<< labels >>
rlabel metal4 8534 12559 8597 12604 1 inn
rlabel metal4 8060 12573 8123 12618 1 inp
diff --git a/mag/div_by_2.mag b/mag/div_by_2.mag
index 8cfb92f..f11de61 100644
--- a/mag/div_by_2.mag
+++ b/mag/div_by_2.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624885207
+timestamp 1624896651
<< nwell >>
rect 2984 2989 4228 3068
rect 3203 118 4219 142
@@ -167,30 +167,30 @@
rect -76 712 -75 744
rect 2082 743 2148 744
rect -141 711 -75 712
-use clock_inverter clock_inverter_0
-timestamp 1624885207
-transform 1 0 -1244 0 1 0
-box 0 0 1244 3068
-use inverter_min_x2 inverter_min_x2_0
-timestamp 1624049879
-transform 1 0 3037 0 -1 723
-box -53 -615 473 655
-use inverter_min_x2 inverter_min_x2_1
-timestamp 1624049879
-transform 1 0 3037 0 1 2345
-box -53 -615 473 655
-use inverter_min_x4 inverter_min_x4_1
-timestamp 1624049879
-transform 1 0 3563 0 -1 723
-box -53 -616 665 643
-use inverter_min_x4 inverter_min_x4_0
-timestamp 1624049879
-transform 1 0 3563 0 1 2346
-box -53 -616 665 643
use DFlipFlop DFlipFlop_0
timestamp 1624885207
transform 1 0 1244 0 -1 3068
box -1244 0 1740 3068
+use inverter_min_x4 inverter_min_x4_0
+timestamp 1624049879
+transform 1 0 3563 0 1 2346
+box -53 -616 665 643
+use inverter_min_x4 inverter_min_x4_1
+timestamp 1624049879
+transform 1 0 3563 0 -1 723
+box -53 -616 665 643
+use inverter_min_x2 inverter_min_x2_1
+timestamp 1624049879
+transform 1 0 3037 0 1 2345
+box -53 -615 473 655
+use inverter_min_x2 inverter_min_x2_0
+timestamp 1624049879
+transform 1 0 3037 0 -1 723
+box -53 -615 473 655
+use clock_inverter clock_inverter_0
+timestamp 1624885207
+transform 1 0 -1244 0 1 0
+box 0 0 1244 3068
<< labels >>
rlabel metal1 -1244 2944 2984 2998 1 vdd
rlabel metal1 -1244 1498 1313 1570 1 vss
diff --git a/mag/div_by_5.mag b/mag/div_by_5.mag
index 439235d..358c13c 100644
--- a/mag/div_by_5.mag
+++ b/mag/div_by_5.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624885207
+timestamp 1624896651
<< nwell >>
rect -556 2925 0 3068
rect -556 2664 57 2925
@@ -317,22 +317,6 @@
rect 9599 884 12343 948
rect 12583 884 12584 948
rect 1990 883 12584 884
-use sky130_fd_sc_hs__xor2_1 sky130_fd_sc_hs__xor2_1_0
-timestamp 1624049879
-transform -1 0 7330 0 1 1960
-box -38 -49 806 715
-use sky130_fd_sc_hs__or2_1 sky130_fd_sc_hs__or2_1_0
-timestamp 1624049879
-transform 1 0 13374 0 1 1960
-box -38 -49 518 715
-use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_0
-timestamp 1624049879
-transform 1 0 -518 0 1 1960
-box -38 -49 518 715
-use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_1
-timestamp 1624049879
-transform 1 0 3022 0 -1 1108
-box -38 -49 518 715
use DFlipFlop DFlipFlop_0
timestamp 1624885207
transform 1 0 1244 0 1 0
@@ -349,6 +333,22 @@
timestamp 1624885207
transform 1 0 11596 0 -1 3068
box -1244 0 1740 3068
+use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_1
+timestamp 1624049879
+transform 1 0 3022 0 -1 1108
+box -38 -49 518 715
+use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_0
+timestamp 1624049879
+transform 1 0 -518 0 1 1960
+box -38 -49 518 715
+use sky130_fd_sc_hs__or2_1 sky130_fd_sc_hs__or2_1_0
+timestamp 1624049879
+transform 1 0 13374 0 1 1960
+box -38 -49 518 715
+use sky130_fd_sc_hs__xor2_1 sky130_fd_sc_hs__xor2_1_0
+timestamp 1624049879
+transform -1 0 7330 0 1 1960
+box -38 -49 806 715
<< labels >>
rlabel metal2 7175 2568 10572 2700 1 Q1
rlabel metal1 6263 2308 7075 2367 1 Q0
diff --git a/mag/extractions/user_analog_project_wrapper_lvs.spice b/mag/extractions/user_analog_project_wrapper_lvs.spice
index 2c675c4..9bb8482 100644
--- a/mag/extractions/user_analog_project_wrapper_lvs.spice
+++ b/mag/extractions/user_analog_project_wrapper_lvs.spice
@@ -73,7 +73,7 @@
Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
.ends
-.subckt DFlipFlop vss nQ Q D vdd CLK nCLK
+.subckt DFlipFlop vss vdd nQ nCLK Q D CLK
Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
+ latch_diff
@@ -174,14 +174,14 @@
.ends
.subckt res_amp_sync_v2 vss avdd1p8 clk_amp clkn clkp rst
-XDFlipFlop_0 vss DFlipFlop_0/nQ DFlipFlop_0/Q DFlipFlop_3/D avdd1p8 clkp clkn DFlipFlop
-XDFlipFlop_1 vss DFlipFlop_1/nQ DFlipFlop_2/D DFlipFlop_1/D avdd1p8 DFlipFlop_3/D
-+ DFlipFlop_0/Q DFlipFlop
-XDFlipFlop_2 vss DFlipFlop_2/nQ DFlipFlop_2/Q DFlipFlop_2/D avdd1p8 clkp clkn DFlipFlop
-XDFlipFlop_3 vss DFlipFlop_3/nQ DFlipFlop_3/Q DFlipFlop_3/D avdd1p8 clkp clkn DFlipFlop
+XDFlipFlop_0 vss avdd1p8 DFlipFlop_0/nQ clkn DFlipFlop_0/Q DFlipFlop_3/D clkp DFlipFlop
+XDFlipFlop_1 vss avdd1p8 DFlipFlop_1/nQ DFlipFlop_0/Q DFlipFlop_2/D DFlipFlop_1/D
++ DFlipFlop_3/D DFlipFlop
+XDFlipFlop_2 vss avdd1p8 DFlipFlop_2/nQ clkn DFlipFlop_2/Q DFlipFlop_2/D clkp DFlipFlop
+XDFlipFlop_3 vss avdd1p8 DFlipFlop_3/nQ clkn DFlipFlop_3/Q DFlipFlop_3/D clkp DFlipFlop
Xinverter_min_x4_0 avdd1p8 DFlipFlop_0/Q vss DFlipFlop_3/D inverter_min_x4
Xinverter_min_x4_1 avdd1p8 nand_logic_0/out vss DFlipFlop_4/D inverter_min_x4
-XDFlipFlop_4 vss DFlipFlop_4/nQ DFlipFlop_4/Q DFlipFlop_4/D avdd1p8 clkp clkn DFlipFlop
+XDFlipFlop_4 vss avdd1p8 DFlipFlop_4/nQ clkn DFlipFlop_4/Q DFlipFlop_4/D clkp DFlipFlop
Xinverter_min_x4_2 avdd1p8 DFlipFlop_2/D vss DFlipFlop_1/D inverter_min_x4
Xinverter_min_x4_3 avdd1p8 nand_logic_1/out vss rst inverter_min_x4
Xinverter_min_x4_4 avdd1p8 DFlipFlop_4/Q vss inverter_min_x4_4/out inverter_min_x4
@@ -817,77 +817,6 @@
+ outn res_amp_lin_prog_0/outp_cap outp source_follower_buff_diff
.ends
-.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
-+ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
-+ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
-+ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
-+ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
-X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-.ends
-
-.subckt cap1_loop_filter VSUBS in out
-Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
-+ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
-.ends
-
-.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
-+ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
-+ m3_n6469_n6400#
-X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-.ends
-
-.subckt cap2_loop_filter VSUBS in out
-Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
-.ends
-
-.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
-X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
-.ends
-
-.subckt res_loop_filter vss out in
-Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
-.ends
-
-.subckt loop_filter vc_pex in vss
-Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
-Xcap2_loop_filter_0 vss in vss cap2_loop_filter
-Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
-Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
-Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
-.ends
-
.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
+ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
+ a_n1403_n486# a_2261_n486# a_n1861_n486#
@@ -1034,7 +963,8 @@
X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
.ends
-.subckt charge_pump Down out iref pswitch nDown biasp Up nswitch vss vdd nUp
+.subckt charge_pump vdd Down out iref pswitch nDown biasp Up nswitch vss w_6648_570#
++ nUp
Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
+ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
@@ -1076,8 +1006,8 @@
Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
.ends
-.subckt div_by_2 vss vdd CLK_2 nCLK_2 o1 CLK out_div o2 nout_div
-XDFlipFlop_0 vss nout_div out_div nout_div vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK DFlipFlop
+.subckt div_by_2 vss vdd nout_div CLK_2 nCLK_2 o1 CLK out_div o2
+XDFlipFlop_0 vss vdd nout_div DFlipFlop_0/nCLK out_div nout_div DFlipFlop_0/CLK DFlipFlop
Xinverter_min_x4_1 vdd o2 vss nCLK_2 inverter_min_x4
Xinverter_min_x4_0 vdd o1 vss CLK_2 inverter_min_x4
Xclock_inverter_0 vss CLK vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
@@ -1085,6 +1015,95 @@
Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
.ends
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
+ w_n257_n702#
X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
@@ -1249,6 +1268,108 @@
Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
.ends
+.subckt trans_gate_mux2to8 in vss en_pos en_neg out vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss en_neg in out out vdd en_neg en_neg in sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 en_pos vss en_pos in out out en_pos in sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt mux2to1 vss select_0_neg out_a_0 out_a_1 select_0 vdd in_a
+Xtrans_gate_mux2to8_0 in_a vss select_0_neg select_0 out_a_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss select_0 select_0_neg out_a_1 vdd trans_gate_mux2to8
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt div_by_5 nCLK vss vdd Q0 CLK nQ0 CLK_5 nQ2 Q1 Q1_shift
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 vss vdd nQ2 nCLK DFlipFlop_0/Q DFlipFlop_0/D CLK DFlipFlop
+XDFlipFlop_1 vss vdd nQ0 nCLK Q0 DFlipFlop_1/D CLK DFlipFlop
+XDFlipFlop_2 vss vdd DFlipFlop_2/nQ nCLK Q1 DFlipFlop_2/D CLK DFlipFlop
+XDFlipFlop_3 vss vdd DFlipFlop_3/nQ CLK Q1_shift Q1 nCLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt mux2to4 vss out_b_1 vdd select_0 select_0_neg out_a_0 out_a_1 in_a in_b out_b_0
+Xtrans_gate_mux2to8_0 in_a vss select_0_neg select_0 out_a_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss select_0 select_0_neg out_a_1 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_b vss select_0_neg select_0 out_b_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_3 in_b vss select_0 select_0_neg out_b_1 vdd trans_gate_mux2to8
+.ends
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt prescaler_23 nCLK vss vdd CLK_23 CLK MC
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 vss vdd DFlipFlop_0/nQ nCLK Q1 nCLK_23 CLK DFlipFlop
+XDFlipFlop_2 vss vdd DFlipFlop_2/nQ CLK Q2_d Q2 nCLK DFlipFlop
+XDFlipFlop_1 vss vdd nCLK_23 nCLK Q2 DFlipFlop_1/D CLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt freq_div vss vdd s_0 s_1 prescaler_23_0/MC clk_d clk_0 clk_pre s_0_n clk_out_mux21
++ n_clk_0 n_clk_1 out s_1_n clk_1 clk_2 in_a clk_5 in_b
+Xdiv_by_2_0 vss vdd div_by_2_0/nout_div clk_2 div_by_2_0/nCLK_2 div_by_2_0/o1 clk_out_mux21
++ div_by_2_0/out_div div_by_2_0/o2 div_by_2
+Xmux2to1_0 vss s_0_n clk_pre clk_5 s_0 vdd clk_out_mux21 mux2to1
+Xinverter_min_x4_0 vdd inverter_min_x4_0/in vss clk_d inverter_min_x4
+Xmux2to1_1 vss s_1_n clk_d clk_2 s_1 vdd out mux2to1
+Xinverter_min_x2_0 clk_out_mux21 inverter_min_x4_0/in vss vdd inverter_min_x2
+Xinverter_min_x2_1 s_1 s_1_n vss vdd inverter_min_x2
+Xinverter_min_x2_2 s_0 s_0_n vss vdd inverter_min_x2
+Xdiv_by_5_0 n_clk_1 vss vdd div_by_5_0/Q0 clk_1 div_by_5_0/nQ0 clk_5 div_by_5_0/nQ2
++ div_by_5_0/Q1 div_by_5_0/Q1_shift div_by_5
+Xmux2to4_0 vss n_clk_1 vdd s_0 s_0_n clk_0 clk_1 in_a in_b n_clk_0 mux2to4
+Xprescaler_23_0 n_clk_0 vss vdd clk_pre clk_0 prescaler_23_0/MC prescaler_23
+.ends
+
.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
.ends
@@ -1311,8 +1432,7 @@
*C2 b VSUBS 0.09fF
.ends
-
-.subckt csvco_branch vctrl in vbp D0 out vss vdd
+.subckt csvco_branch vctrl in vbp D0 vss out vdd
Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
+ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
+ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
@@ -1324,13 +1444,13 @@
Xcap_vco_0 cap_vco_0/t vss vss cap_vco
.ends
-.subckt ring_osc vctrl vdd vss D0 out_vco
+.subckt ring_osc vctrl vss vdd D0 out_vco
Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
+ sky130_fd_pr__pfet_01v8_4757AC
-Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp D0 csvco_branch_1/in vss vdd csvco_branch
-Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp D0 out_vco vss vdd csvco_branch
-Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp D0 csvco_branch_2/in vss
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp D0 vss csvco_branch_1/in vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp D0 vss out_vco vdd csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp D0 vss csvco_branch_2/in
+ vdd csvco_branch
.ends
@@ -1340,48 +1460,6 @@
Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
.ends
-.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X
-X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-.ends
-
-.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X
-X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
-X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
-X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-.ends
-
-.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X
-X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-.ends
-
-.subckt div_by_5 nCLK vss vdd Q0 CLK nQ0 CLK_5 nQ2 Q1 Q1_shift
-Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
-XDFlipFlop_0 vss nQ2 DFlipFlop_0/Q DFlipFlop_0/D vdd CLK nCLK DFlipFlop
-XDFlipFlop_2 vss DFlipFlop_2/nQ Q1 DFlipFlop_2/D vdd CLK nCLK DFlipFlop
-XDFlipFlop_1 vss nQ0 Q0 DFlipFlop_1/D vdd CLK nCLK DFlipFlop
-XDFlipFlop_3 vss DFlipFlop_3/nQ Q1_shift Q1 vdd nCLK CLK DFlipFlop
-Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
-Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
-Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
-.ends
-
.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
+ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
+ a_129_n151# a_159_n125# a_n317_n125#
@@ -1416,8 +1494,8 @@
Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
Xinverter_cp_x1_0 QB vss inverter_cp_x1_0/out vdd inverter_cp_x1
-Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
+Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
.ends
.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS w_n359_n309# a_n63_n116# a_n159_n207#
@@ -1434,16 +1512,16 @@
X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
.ends
-.subckt nor_pfd out vss vdd A B
+.subckt nor_pfd vdd out vss A B
Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss vdd B A out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
.ends
.subckt dff_pfd vdd vss Q CLK Reset
-Xnor_pfd_0 nor_pfd_2/A vss vdd CLK Q nor_pfd
-Xnor_pfd_1 Q vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
-Xnor_pfd_2 nor_pfd_3/A vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
-Xnor_pfd_3 nor_pfd_2/B vss vdd nor_pfd_3/A Reset nor_pfd
+Xnor_pfd_0 vdd nor_pfd_2/A vss CLK Q nor_pfd
+Xnor_pfd_1 vdd Q vss nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 vdd nor_pfd_3/A vss nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 vdd nor_pfd_2/B vss nor_pfd_3/A Reset nor_pfd
.ends
.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
@@ -1475,24 +1553,48 @@
Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
.ends
-.subckt PFD vss vdd Down Up A B Reset
+.subckt PFD vss vdd Reset Down Up A B
Xdff_pfd_0 vdd vss Up A Reset dff_pfd
Xdff_pfd_1 vdd vss Down B Reset dff_pfd
Xand_pfd_0 vss Reset vdd Up Down and_pfd
.ends
+.subckt top_pll_v3 s_0 in_ref vss s_1 vco_D0 lf_D0 iref_cp vdd out_to_pad MC
+Xcharge_pump_0 vdd Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vss nUp
++ charge_pump
+Xdiv_by_2_0 vss vdd n_out_div_2 out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2
++ n_out_buffer_div_2 div_by_2
+Xloop_filter_v2_0 lf_vc lf_D0 vco_vctrl vss loop_filter_v2
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xfreq_div_0 vss vdd s_0 s_1 MC clk_d clk_0 clk_pre s_0_n clk_out_mux21 n_clk_0 n_clk_1
++ out_div s_1_n clk_1 clk_2_f out_by_2 clk_5 n_out_by_2 freq_div
+Xring_osc_0 vco_vctrl vss vdd vco_D0 vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div PFD
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
.subckt top_pll_v1 vdd in_ref w_13905_n238# vss vco_D0 iref_cp out_to_pad
Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
-Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
-Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
-+ n_out_div_2 div_by_2
+Xcharge_pump_0 vdd Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss charge_pump_0/w_6648_570#
++ nUp charge_pump
+Xdiv_by_2_0 vss vdd n_out_div_2 out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2
++ n_out_buffer_div_2 div_by_2
Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
-Xring_osc_0 vco_vctrl vdd vss vco_D0 vco_out ring_osc
+Xring_osc_0 vco_vctrl vss vdd vco_D0 vco_out ring_osc
Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
Xdiv_by_5_0 n_out_by_2 vss vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2
+ div_5_Q1 div_5_Q1_shift div_by_5
Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
-XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div_by_5 PFD
.ends
.subckt sky130_fd_pr__cap_mim_m3_2_2Y8F6P VSUBS c2_n3251_n3000# m4_n3351_n3100#
@@ -1586,44 +1688,19 @@
Xdecap[4] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
.ends
-.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
-+ c1_110_n4150# m3_10_n4250#
-X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-.ends
-
-.subckt cap3_loop_filter VSUBS in out
-Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
-X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
-.ends
-
-.subckt loop_filter_v2 vc_pex D0_cap in vss
-Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
-Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
-Xcap2_loop_filter_0 vss in vss cap2_loop_filter
-Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
-Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
-Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
-Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
-.ends
-
.subckt top_pll_v2 vdd in_ref w_13905_n238# vss D0_vco iref_cp DO_cap out_to_pad
-Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
+Xcharge_pump_0 vdd Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss charge_pump_0/w_6648_570#
++ nUp charge_pump
+Xdiv_by_2_0 vss vdd n_out_div_2 out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2
++ n_out_buffer_div_2 div_by_2
Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
-Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
-+ n_out_div_2 div_by_2
Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
-Xring_osc_0 vco_vctrl vdd vss D0_vco vco_out ring_osc
+Xring_osc_0 vco_vctrl vss vdd D0_vco vco_out ring_osc
Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
Xdiv_by_5_0 n_out_by_2 vss vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2
+ div_5_Q1 div_5_Q1_shift div_by_5
Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
-XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div_by_5 PFD
.ends
*.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
@@ -1634,110 +1711,111 @@
*+ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
*+ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
*+ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7]
-*+ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
-*+ io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
-*+ io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
-*+ io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9]
-*+ io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14]
-*+ io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1]
-*+ io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25]
-*+ io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7]
-*+ io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
-*+ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20]
-*+ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3]
-*+ io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10]
-*+ io_out[11] io_out[12] io_out[13] io_out[14] io_out[15] io_out[16] io_out[17] io_out[18]
-*+ io_out[19] io_out[1] io_out[20] io_out[21] io_out[22] io_out[23] io_out[24] io_out[25]
-*+ io_out[26] io_out[2] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8]
-*+ io_out[9] la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103]
-*+ la_data_in[104] la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108]
-*+ la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113]
-*+ la_data_in[114] la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118]
-*+ la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123]
-*+ la_data_in[124] la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13]
-*+ la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19]
-*+ la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24]
-*+ la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2]
-*+ la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35]
-*+ la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40]
-*+ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46]
-*+ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51]
-*+ la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57]
-*+ la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62]
-*+ la_data_in[63] la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68]
-*+ la_data_in[69] la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73]
-*+ la_data_in[74] la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79]
-*+ la_data_in[7] la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84]
-*+ la_data_in[85] la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8]
-*+ la_data_in[90] la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95]
-*+ la_data_in[96] la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0]
-*+ la_data_out[100] la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104]
-*+ la_data_out[105] la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109]
-*+ la_data_out[10] la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113]
-*+ la_data_out[114] la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118]
-*+ la_data_out[119] la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122]
-*+ la_data_out[123] la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127]
-*+ la_data_out[12] la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16]
-*+ la_data_out[17] la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21]
-*+ la_data_out[22] la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26]
-*+ la_data_out[27] la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31]
-*+ la_data_out[32] la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36]
-*+ la_data_out[37] la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41]
-*+ la_data_out[42] la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46]
-*+ la_data_out[47] la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51]
-*+ la_data_out[52] la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56]
-*+ la_data_out[57] la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61]
-*+ la_data_out[62] la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66]
-*+ la_data_out[67] la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71]
-*+ la_data_out[72] la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76]
-*+ la_data_out[77] la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81]
-*+ la_data_out[82] la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86]
-*+ la_data_out[87] la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91]
-*+ la_data_out[92] la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96]
-*+ la_data_out[97] la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100]
-*+ la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107]
-*+ la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113]
-*+ la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11]
-*+ la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126]
-*+ la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17]
-*+ la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23]
-*+ la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2]
-*+ la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36]
-*+ la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42]
-*+ la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49]
-*+ la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55]
-*+ la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61]
-*+ la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68]
-*+ la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74]
-*+ la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80]
-*+ la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87]
-*+ la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93]
-*+ la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9]
-*+ user_clock2 user_irq[0] user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2
-*+ vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11]
-*+ wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17]
-*+ wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22]
-*+ wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28]
-*+ wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4]
-*+ wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0]
-*+ wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15]
-*+ wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20]
-*+ wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26]
-*+ wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31]
-*+ wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9]
-*+ wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14]
-*+ wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1]
-*+ wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25]
-*+ wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
-*+ wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
-*+ wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+*+ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
+*+ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
+*+ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
+*+ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
+*+ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
+*+ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
+*+ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
+*+ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
+*+ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
+*+ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
+*+ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
+*+ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
+*+ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
+*+ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
+*+ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
+*+ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
+*+ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
+*+ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
+*+ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
+*+ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
+*+ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
+*+ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
+*+ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
+*+ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
+*+ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
+*+ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
+*+ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
+*+ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
+*+ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
+*+ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
+*+ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
+*+ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
+*+ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
+*+ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
+*+ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
+*+ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
+*+ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
+*+ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
+*+ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
+*+ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
+*+ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
+*+ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
+*+ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
+*+ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
+*+ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
+*+ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
+*+ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
+*+ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
+*+ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
+*+ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
+*+ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
+*+ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
+*+ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
+*+ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
+*+ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
+*+ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
+*+ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
+*+ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
+*+ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
+*+ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
+*+ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
+*+ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
+*+ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
+*+ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
+*+ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
+*+ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
+*+ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
+*+ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
+*+ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
+*+ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
+*+ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
+*+ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
+*+ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
+*+ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
+*+ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
+*+ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
+*+ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
+*+ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
+*+ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
+*+ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
+*+ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
+*+ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
+*+ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
+*+ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
+*+ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
+*+ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
+*+ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
+*+ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
+*+ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
+*+ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
+*+ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
+*+ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
+*+ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
+*+ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
+*+ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
+*+ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
+*+ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
+*+ wbs_stb_i wbs_we_i
Xres_amp_top_0 bias_0/iref_9 bias_0/iref_8 vssa1 bias_0/iref_6 bias_0/iref_7 bias_0/iref_5
+ vdda1 io_analog[6] gpio_noesd[4] gpio_noesd[5] gpio_noesd[6] gpio_noesd[3] gpio_noesd[2]
+ io_analog[2] io_analog[0] gpio_noesd[1] io_analog[1] io_analog[3] io_analog[4] res_amp_top
+Xtop_pll_v3_0 gpio_noesd[10] io_analog[10] vssa1 gpio_noesd[9] gpio_noesd[7] gpio_noesd[8]
++ bias_0/iref_0 vdda1 io_analog[7] gpio_noesd[11] top_pll_v3
Xtop_pll_v1_0 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_2 io_analog[9]
+ top_pll_v1
-Xtop_pll_v1_1 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_0 io_analog[7]
-+ top_pll_v1
Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
diff --git a/mag/extractions/user_analog_project_wrapper_pex_c.spice b/mag/extractions/user_analog_project_wrapper_pex_c.spice
index 03ec8de..b9d51c8 100644
--- a/mag/extractions/user_analog_project_wrapper_pex_c.spice
+++ b/mag/extractions/user_analog_project_wrapper_pex_c.spice
@@ -5,18 +5,18 @@
X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n111_n156# a_n15_n156# 0.02fF
-C1 a_n81_n125# a_15_n125# 0.36fF
-C2 a_n81_n125# a_111_n125# 0.13fF
-C3 w_n311_n344# a_n81_n125# 0.09fF
-C4 a_15_n125# a_111_n125# 0.36fF
-C5 w_n311_n344# a_15_n125# 0.09fF
-C6 w_n311_n344# a_111_n125# 0.14fF
-C7 a_n173_n125# a_n81_n125# 0.36fF
-C8 a_n173_n125# a_15_n125# 0.13fF
-C9 a_n173_n125# a_111_n125# 0.08fF
-C10 a_n15_n156# a_81_n156# 0.02fF
-C11 w_n311_n344# a_n173_n125# 0.14fF
+C0 a_n81_n125# w_n311_n344# 0.09fF
+C1 a_n15_n156# a_81_n156# 0.02fF
+C2 w_n311_n344# a_n173_n125# 0.14fF
+C3 a_15_n125# w_n311_n344# 0.09fF
+C4 a_n81_n125# a_n173_n125# 0.36fF
+C5 a_111_n125# w_n311_n344# 0.14fF
+C6 a_n81_n125# a_15_n125# 0.36fF
+C7 a_n81_n125# a_111_n125# 0.13fF
+C8 a_n111_n156# a_n15_n156# 0.02fF
+C9 a_15_n125# a_n173_n125# 0.13fF
+C10 a_111_n125# a_n173_n125# 0.08fF
+C11 a_15_n125# a_111_n125# 0.36fF
C12 a_111_n125# VSUBS 0.03fF
C13 a_15_n125# VSUBS 0.03fF
C14 a_n81_n125# VSUBS 0.03fF
@@ -32,14 +32,14 @@
X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_111_n125# a_n173_n125# 0.08fF
-C1 a_111_n125# a_n81_n125# 0.13fF
-C2 a_15_n125# a_n173_n125# 0.13fF
-C3 a_15_n125# a_n81_n125# 0.36fF
-C4 a_n173_n125# a_n81_n125# 0.36fF
-C5 a_111_n125# a_15_n125# 0.36fF
-C6 a_81_n151# a_n15_n151# 0.02fF
-C7 a_n111_n151# a_n15_n151# 0.02fF
+C0 a_n111_n151# a_n15_n151# 0.02fF
+C1 a_n173_n125# a_111_n125# 0.08fF
+C2 a_n15_n151# a_81_n151# 0.02fF
+C3 a_n173_n125# a_n81_n125# 0.36fF
+C4 a_n81_n125# a_111_n125# 0.13fF
+C5 a_n173_n125# a_15_n125# 0.13fF
+C6 a_15_n125# a_111_n125# 0.36fF
+C7 a_n81_n125# a_15_n125# 0.36fF
C8 a_111_n125# w_n311_n335# 0.17fF
C9 a_15_n125# w_n311_n335# 0.12fF
C10 a_n81_n125# w_n311_n335# 0.12fF
@@ -49,13 +49,13 @@
C14 a_n111_n151# w_n311_n335# 0.05fF
.ends
-.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+.subckt trans_gate m1_187_n605# vss m1_45_n513# vdd
Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
+ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
+ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
-C0 vdd m1_187_n605# 0.55fF
-C1 vdd m1_45_n513# 0.69fF
+C0 m1_187_n605# vdd 0.55fF
+C1 m1_45_n513# vdd 0.69fF
C2 m1_45_n513# m1_187_n605# 0.36fF
C3 m1_187_n605# vss 0.93fF
C4 m1_45_n513# vss 1.31fF
@@ -67,16 +67,16 @@
X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n173_n125# a_111_n125# 0.08fF
-C1 a_15_n125# w_n311_n344# 0.09fF
-C2 a_15_n125# a_111_n125# 0.36fF
-C3 w_n311_n344# a_n81_n125# 0.09fF
-C4 a_n173_n125# a_15_n125# 0.13fF
-C5 a_111_n125# a_n81_n125# 0.13fF
-C6 a_n173_n125# a_n81_n125# 0.36fF
-C7 a_15_n125# a_n81_n125# 0.36fF
-C8 w_n311_n344# a_111_n125# 0.14fF
-C9 a_n173_n125# w_n311_n344# 0.14fF
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 w_n311_n344# a_n81_n125# 0.09fF
+C2 a_15_n125# w_n311_n344# 0.09fF
+C3 w_n311_n344# a_n173_n125# 0.14fF
+C4 a_n81_n125# a_111_n125# 0.13fF
+C5 a_15_n125# a_111_n125# 0.36fF
+C6 a_n173_n125# a_111_n125# 0.08fF
+C7 w_n311_n344# a_111_n125# 0.14fF
+C8 a_15_n125# a_n81_n125# 0.36fF
+C9 a_n81_n125# a_n173_n125# 0.36fF
C10 a_111_n125# VSUBS 0.03fF
C11 a_15_n125# VSUBS 0.03fF
C12 a_n81_n125# VSUBS 0.03fF
@@ -90,11 +90,11 @@
X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n173_n125# a_n81_n125# 0.36fF
-C1 a_n173_n125# a_15_n125# 0.13fF
-C2 a_111_n125# a_n81_n125# 0.13fF
-C3 a_111_n125# a_15_n125# 0.36fF
-C4 a_n173_n125# a_111_n125# 0.08fF
+C0 a_111_n125# a_n81_n125# 0.13fF
+C1 a_15_n125# a_n173_n125# 0.13fF
+C2 a_111_n125# a_n173_n125# 0.08fF
+C3 a_n81_n125# a_n173_n125# 0.36fF
+C4 a_111_n125# a_15_n125# 0.36fF
C5 a_15_n125# a_n81_n125# 0.36fF
C6 a_111_n125# w_n311_n335# 0.17fF
C7 a_15_n125# w_n311_n335# 0.12fF
@@ -106,8 +106,8 @@
.subckt inverter_cp_x1 out in vss vdd
Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
-C0 out vdd 0.10fF
-C1 out in 0.32fF
+C0 out in 0.32fF
+C1 out vdd 0.10fF
C2 out vss 0.77fF
C3 in vss 0.95fF
C4 vdd vss 3.13fF
@@ -115,37 +115,37 @@
.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
+ nCLK_d
-Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xtrans_gate_0 nCLK_d vss inverter_cp_x1_0/out vdd trans_gate
Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
-C0 inverter_cp_x1_2/in CLK 0.31fF
-C1 inverter_cp_x1_2/in CLK_d 0.12fF
-C2 inverter_cp_x1_2/in vdd 0.21fF
-C3 CLK inverter_cp_x1_0/out 0.31fF
-C4 nCLK_d inverter_cp_x1_0/out 0.11fF
-C5 vdd CLK 0.36fF
-C6 vdd nCLK_d 0.03fF
-C7 vdd CLK_d 0.03fF
-C8 vdd inverter_cp_x1_0/out 0.28fF
+C0 vdd inverter_cp_x1_2/in 0.21fF
+C1 CLK inverter_cp_x1_2/in 0.31fF
+C2 inverter_cp_x1_0/out vdd 0.28fF
+C3 CLK_d inverter_cp_x1_2/in 0.12fF
+C4 vdd CLK 0.36fF
+C5 nCLK_d vdd 0.03fF
+C6 inverter_cp_x1_0/out CLK 0.31fF
+C7 CLK_d vdd 0.03fF
+C8 nCLK_d inverter_cp_x1_0/out 0.11fF
C9 inverter_cp_x1_2/in vss 2.01fF
C10 CLK_d vss 0.96fF
C11 inverter_cp_x1_0/out vss 1.97fF
C12 CLK vss 3.03fF
-C13 nCLK_d vss 1.44fF
-C14 vdd vss 16.51fF
+C13 vdd vss 16.51fF
+C14 nCLK_d vss 1.44fF
.ends
.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
+ a_n63_n192#
X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-C0 a_63_n95# w_n263_n314# 0.11fF
-C1 w_n263_n314# a_n125_n95# 0.11fF
-C2 a_n33_n95# a_63_n95# 0.28fF
-C3 a_n33_n95# a_n125_n95# 0.28fF
-C4 a_63_n95# a_n125_n95# 0.10fF
-C5 a_n33_n95# w_n263_n314# 0.08fF
+C0 a_n125_n95# w_n263_n314# 0.11fF
+C1 a_n125_n95# a_63_n95# 0.10fF
+C2 a_n125_n95# a_n33_n95# 0.28fF
+C3 w_n263_n314# a_63_n95# 0.11fF
+C4 w_n263_n314# a_n33_n95# 0.08fF
+C5 a_63_n95# a_n33_n95# 0.28fF
C6 a_63_n95# VSUBS 0.03fF
C7 a_n33_n95# VSUBS 0.03fF
C8 a_n125_n95# VSUBS 0.03fF
@@ -158,16 +158,16 @@
X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n173_n125# a_111_n125# 0.08fF
-C1 a_15_n125# a_n173_n125# 0.13fF
-C2 a_n81_n125# a_n173_n125# 0.36fF
-C3 a_n129_n213# a_n173_n125# 0.02fF
-C4 a_15_n125# a_111_n125# 0.36fF
+C0 a_n81_n125# a_n173_n125# 0.36fF
+C1 a_n173_n125# a_n129_n213# 0.02fF
+C2 a_n173_n125# a_111_n125# 0.08fF
+C3 a_n173_n125# a_15_n125# 0.13fF
+C4 a_n81_n125# a_n129_n213# 0.10fF
C5 a_n81_n125# a_111_n125# 0.13fF
-C6 a_15_n125# a_n81_n125# 0.36fF
+C6 a_n81_n125# a_15_n125# 0.36fF
C7 a_n129_n213# a_111_n125# 0.01fF
-C8 a_15_n125# a_n129_n213# 0.10fF
-C9 a_n81_n125# a_n129_n213# 0.10fF
+C8 a_n129_n213# a_15_n125# 0.10fF
+C9 a_111_n125# a_15_n125# 0.36fF
C10 a_111_n125# w_n311_n335# 0.05fF
C11 a_15_n125# w_n311_n335# 0.05fF
C12 a_n81_n125# w_n311_n335# 0.05fF
@@ -178,9 +178,9 @@
.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-C0 a_n81_n183# a_n33_n95# 0.10fF
-C1 a_n33_n95# a_n125_n95# 0.88fF
-C2 a_n81_n183# a_n125_n95# 0.16fF
+C0 a_n33_n95# a_n125_n95# 0.88fF
+C1 a_n125_n95# a_n81_n183# 0.16fF
+C2 a_n33_n95# a_n81_n183# 0.10fF
C3 a_n33_n95# w_n263_n305# 0.07fF
C4 a_n125_n95# w_n263_n305# 0.13fF
C5 a_n81_n183# w_n263_n305# 0.31fF
@@ -192,67 +192,67 @@
Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
-C0 m1_657_280# CLK 0.24fF
-C1 nQ nD 0.05fF
-C2 D Q 0.05fF
-C3 vdd Q 0.16fF
-C4 D nQ 0.05fF
-C5 nQ Q 0.93fF
-C6 nQ vdd 0.16fF
-C7 m1_657_280# Q 0.94fF
-C8 nD Q 0.05fF
-C9 m1_657_280# nQ 1.41fF
-C10 nQ vss 1.16fF
-C11 D vss 0.53fF
-C12 Q vss -0.55fF
-C13 m1_657_280# vss 1.88fF
-C14 nD vss 0.16fF
-C15 CLK vss 0.87fF
+C0 nQ D 0.05fF
+C1 m1_657_280# nQ 1.41fF
+C2 vdd nQ 0.16fF
+C3 nD Q 0.05fF
+C4 Q D 0.05fF
+C5 m1_657_280# Q 0.94fF
+C6 vdd Q 0.16fF
+C7 nQ Q 0.93fF
+C8 nD nQ 0.05fF
+C9 m1_657_280# CLK 0.24fF
+C10 D vss 0.53fF
+C11 Q vss -0.55fF
+C12 m1_657_280# vss 1.88fF
+C13 nD vss 0.16fF
+C14 CLK vss 0.87fF
+C15 nQ vss 1.16fF
C16 vdd vss 5.98fF
.ends
.subckt DFlipFlop latch_diff_0/m1_657_280# vss vdd latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
-+ nQ latch_diff_0/nD Q latch_diff_1/nD latch_diff_1/m1_657_280# D latch_diff_0/D CLK
-+ clock_inverter_0/inverter_cp_x1_0/out nCLK
++ nQ nCLK latch_diff_0/nD Q latch_diff_1/nD latch_diff_1/m1_657_280# D latch_diff_0/D
++ CLK clock_inverter_0/inverter_cp_x1_0/out
Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
+ latch_diff_0/D latch_diff_0/nD clock_inverter
Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
+ latch_diff_0/nD latch_diff_0/D latch_diff
Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
+ latch_diff
-C0 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
-C1 latch_diff_1/D latch_diff_0/nD 0.41fF
-C2 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C0 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C1 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C2 latch_diff_0/nD vdd 0.14fF
C3 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
-C4 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
-C5 nQ latch_diff_1/D 0.11fF
-C6 latch_diff_1/D latch_diff_1/nD 0.33fF
-C7 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
-C8 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
-C9 latch_diff_1/D latch_diff_0/D 0.11fF
-C10 latch_diff_1/D vdd 0.03fF
-C11 latch_diff_0/nD vdd 0.14fF
-C12 latch_diff_1/nD Q 0.01fF
-C13 nQ latch_diff_1/nD 0.08fF
-C14 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
-C15 latch_diff_1/nD latch_diff_0/D 0.04fF
-C16 latch_diff_1/nD vdd 0.02fF
-C17 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
-C18 latch_diff_0/D vdd 0.09fF
-C19 nQ vss 0.57fF
-C20 Q vss -0.92fF
-C21 latch_diff_1/m1_657_280# vss 0.64fF
-C22 nCLK vss 0.83fF
-C23 latch_diff_1/nD vss 1.83fF
-C24 latch_diff_1/D vss -0.30fF
-C25 latch_diff_0/m1_657_280# vss 0.72fF
-C26 CLK vss 0.83fF
+C4 latch_diff_0/nD latch_diff_1/D 0.41fF
+C5 nQ latch_diff_1/nD 0.08fF
+C6 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C7 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C8 latch_diff_0/D latch_diff_1/nD 0.04fF
+C9 latch_diff_1/D nQ 0.11fF
+C10 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C11 Q latch_diff_1/nD 0.01fF
+C12 vdd latch_diff_0/D 0.09fF
+C13 latch_diff_1/D latch_diff_0/D 0.11fF
+C14 vdd latch_diff_1/nD 0.02fF
+C15 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C16 latch_diff_1/D latch_diff_1/nD 0.33fF
+C17 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C18 vdd latch_diff_1/D 0.03fF
+C19 Q vss -0.92fF
+C20 latch_diff_1/m1_657_280# vss 0.64fF
+C21 nCLK vss 0.83fF
+C22 nQ vss 0.57fF
+C23 latch_diff_1/D vss -0.30fF
+C24 latch_diff_0/m1_657_280# vss 0.72fF
+C25 CLK vss 0.83fF
+C26 latch_diff_1/nD vss 1.83fF
C27 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C28 latch_diff_0/D vss 1.29fF
C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
C30 D vss 3.27fF
-C31 latch_diff_0/nD vss 1.74fF
-C32 vdd vss 32.62fF
+C31 vdd vss 32.62fF
+C32 latch_diff_0/nD vss 1.74fF
.ends
.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
@@ -261,24 +261,24 @@
X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_n129_n84# a_n221_n84# 0.24fF
-C1 a_n221_n84# w_n359_n303# 0.08fF
-C2 a_n129_n84# w_n359_n303# 0.06fF
-C3 a_n33_n84# a_63_n84# 0.24fF
-C4 a_n63_n110# a_33_n110# 0.02fF
-C5 a_63_n84# a_n221_n84# 0.05fF
-C6 a_n129_n84# a_63_n84# 0.09fF
-C7 a_n63_n110# a_n159_n110# 0.02fF
-C8 a_63_n84# w_n359_n303# 0.06fF
-C9 a_n33_n84# a_159_n84# 0.09fF
-C10 a_n221_n84# a_159_n84# 0.04fF
-C11 a_n129_n84# a_159_n84# 0.05fF
-C12 w_n359_n303# a_159_n84# 0.08fF
-C13 a_33_n110# a_129_n110# 0.02fF
-C14 a_63_n84# a_159_n84# 0.24fF
-C15 a_n33_n84# a_n221_n84# 0.09fF
-C16 a_n33_n84# a_n129_n84# 0.24fF
-C17 a_n33_n84# w_n359_n303# 0.05fF
+C0 w_n359_n303# a_n129_n84# 0.06fF
+C1 w_n359_n303# a_159_n84# 0.08fF
+C2 w_n359_n303# a_n221_n84# 0.08fF
+C3 w_n359_n303# a_n33_n84# 0.05fF
+C4 a_159_n84# a_n129_n84# 0.05fF
+C5 a_63_n84# w_n359_n303# 0.06fF
+C6 a_n129_n84# a_n221_n84# 0.24fF
+C7 a_n129_n84# a_n33_n84# 0.24fF
+C8 a_n63_n110# a_33_n110# 0.02fF
+C9 a_63_n84# a_n129_n84# 0.09fF
+C10 a_129_n110# a_33_n110# 0.02fF
+C11 a_159_n84# a_n221_n84# 0.04fF
+C12 a_159_n84# a_n33_n84# 0.09fF
+C13 a_63_n84# a_159_n84# 0.24fF
+C14 a_n33_n84# a_n221_n84# 0.09fF
+C15 a_n159_n110# a_n63_n110# 0.02fF
+C16 a_63_n84# a_n221_n84# 0.05fF
+C17 a_63_n84# a_n33_n84# 0.24fF
C18 a_159_n84# VSUBS 0.03fF
C19 a_63_n84# VSUBS 0.03fF
C20 a_n33_n84# VSUBS 0.03fF
@@ -297,19 +297,19 @@
X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-C0 a_n33_n42# a_63_n42# 0.12fF
-C1 a_n33_n42# a_n221_n42# 0.05fF
-C2 a_n221_n42# a_63_n42# 0.03fF
-C3 a_n33_n42# a_n129_n42# 0.12fF
-C4 a_n129_n42# a_63_n42# 0.05fF
-C5 a_n63_n68# a_33_n68# 0.02fF
-C6 a_n129_n42# a_n221_n42# 0.12fF
+C0 a_n33_n42# a_159_n42# 0.05fF
+C1 a_n221_n42# a_n129_n42# 0.12fF
+C2 a_n33_n42# a_63_n42# 0.12fF
+C3 a_n221_n42# a_n33_n42# 0.05fF
+C4 a_33_n68# a_n63_n68# 0.02fF
+C5 a_n129_n42# a_n33_n42# 0.12fF
+C6 a_159_n42# a_63_n42# 0.12fF
C7 a_129_n68# a_33_n68# 0.02fF
-C8 a_n63_n68# a_n159_n68# 0.02fF
-C9 a_n33_n42# a_159_n42# 0.05fF
-C10 a_159_n42# a_63_n42# 0.12fF
-C11 a_159_n42# a_n221_n42# 0.02fF
-C12 a_159_n42# a_n129_n42# 0.03fF
+C8 a_n221_n42# a_159_n42# 0.02fF
+C9 a_n129_n42# a_159_n42# 0.03fF
+C10 a_n159_n68# a_n63_n68# 0.02fF
+C11 a_n221_n42# a_63_n42# 0.03fF
+C12 a_n129_n42# a_63_n42# 0.05fF
C13 a_159_n42# w_n359_n252# 0.07fF
C14 a_63_n42# w_n359_n252# 0.06fF
C15 a_n33_n42# w_n359_n252# 0.06fF
@@ -324,11 +324,11 @@
.subckt inverter_min_x4 vdd in vss out
Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
-C0 out vdd 0.62fF
-C1 in vdd 0.33fF
+C0 in vdd 0.33fF
+C1 out vdd 0.62fF
C2 in out 0.67fF
-C3 in vss 1.89fF
-C4 out vss 0.66fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
C5 vdd vss 3.87fF
.ends
@@ -352,72 +352,72 @@
X13 a_447_n84# a_n753_n181# a_351_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X14 a_639_n84# a_n753_n181# a_543_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X15 a_735_n84# a_n753_n181# a_639_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_255_n84# a_351_n84# 0.24fF
-C1 a_n417_n84# a_n705_n84# 0.05fF
-C2 a_639_n84# w_n935_n303# 0.04fF
-C3 a_351_n84# a_159_n84# 0.09fF
-C4 a_n321_n84# a_n705_n84# 0.04fF
-C5 a_n225_n84# a_n513_n84# 0.05fF
-C6 a_n33_n84# a_63_n84# 0.24fF
-C7 a_735_n84# a_543_n84# 0.09fF
-C8 a_n609_n84# a_n705_n84# 0.24fF
-C9 a_543_n84# a_447_n84# 0.24fF
-C10 a_n417_n84# a_n225_n84# 0.09fF
-C11 a_543_n84# a_255_n84# 0.05fF
-C12 a_735_n84# a_447_n84# 0.05fF
-C13 a_n225_n84# a_n129_n84# 0.24fF
-C14 a_n417_n84# a_n513_n84# 0.24fF
-C15 a_159_n84# a_n225_n84# 0.04fF
-C16 a_351_n84# a_63_n84# 0.05fF
-C17 a_n321_n84# a_n225_n84# 0.24fF
-C18 a_255_n84# a_447_n84# 0.09fF
-C19 a_543_n84# a_159_n84# 0.04fF
-C20 w_n935_n303# a_n705_n84# 0.04fF
-C21 a_n129_n84# a_n513_n84# 0.04fF
-C22 a_n225_n84# a_n609_n84# 0.04fF
-C23 a_n321_n84# a_n513_n84# 0.09fF
-C24 a_159_n84# a_447_n84# 0.05fF
-C25 a_255_n84# a_n129_n84# 0.04fF
-C26 a_n417_n84# a_n129_n84# 0.05fF
-C27 a_255_n84# a_159_n84# 0.24fF
-C28 a_n417_n84# a_n321_n84# 0.24fF
-C29 a_n797_n84# a_n705_n84# 0.24fF
-C30 a_n513_n84# a_n609_n84# 0.24fF
-C31 a_351_n84# a_639_n84# 0.05fF
-C32 a_63_n84# a_n225_n84# 0.05fF
-C33 a_159_n84# a_n129_n84# 0.05fF
-C34 a_n417_n84# a_n609_n84# 0.09fF
-C35 a_n321_n84# a_n129_n84# 0.09fF
-C36 a_543_n84# w_n935_n303# 0.03fF
-C37 a_63_n84# a_447_n84# 0.04fF
-C38 a_n321_n84# a_n609_n84# 0.05fF
-C39 a_255_n84# a_63_n84# 0.09fF
-C40 a_735_n84# w_n935_n303# 0.08fF
-C41 a_n513_n84# w_n935_n303# 0.02fF
-C42 a_447_n84# w_n935_n303# 0.02fF
-C43 a_n33_n84# a_351_n84# 0.04fF
-C44 a_63_n84# a_n129_n84# 0.09fF
-C45 a_543_n84# a_639_n84# 0.24fF
-C46 a_n797_n84# a_n513_n84# 0.05fF
-C47 a_159_n84# a_63_n84# 0.24fF
-C48 a_n321_n84# a_63_n84# 0.04fF
-C49 a_n417_n84# a_n797_n84# 0.04fF
-C50 a_735_n84# a_639_n84# 0.24fF
-C51 a_447_n84# a_639_n84# 0.09fF
-C52 a_255_n84# a_639_n84# 0.04fF
-C53 w_n935_n303# a_n609_n84# 0.03fF
-C54 a_n33_n84# a_n225_n84# 0.09fF
-C55 a_n797_n84# a_n609_n84# 0.09fF
-C56 a_n33_n84# a_255_n84# 0.05fF
-C57 a_n417_n84# a_n33_n84# 0.04fF
-C58 a_543_n84# a_351_n84# 0.09fF
-C59 a_n797_n84# w_n935_n303# 0.08fF
-C60 a_n33_n84# a_n129_n84# 0.24fF
-C61 a_735_n84# a_351_n84# 0.04fF
-C62 a_n33_n84# a_159_n84# 0.09fF
-C63 a_n513_n84# a_n705_n84# 0.09fF
-C64 a_n33_n84# a_n321_n84# 0.05fF
-C65 a_351_n84# a_447_n84# 0.24fF
+C0 a_543_n84# a_255_n84# 0.05fF
+C1 a_n417_n84# a_n225_n84# 0.09fF
+C2 a_639_n84# a_351_n84# 0.05fF
+C3 a_351_n84# a_63_n84# 0.05fF
+C4 a_63_n84# a_n129_n84# 0.09fF
+C5 a_543_n84# w_n935_n303# 0.03fF
+C6 a_735_n84# a_447_n84# 0.05fF
+C7 a_n417_n84# a_n705_n84# 0.05fF
+C8 a_639_n84# a_543_n84# 0.24fF
+C9 a_n417_n84# a_n797_n84# 0.04fF
+C10 a_159_n84# a_351_n84# 0.09fF
+C11 a_159_n84# a_n129_n84# 0.05fF
+C12 a_n225_n84# a_n321_n84# 0.24fF
+C13 a_n417_n84# a_n513_n84# 0.24fF
+C14 a_159_n84# a_543_n84# 0.04fF
+C15 a_n705_n84# a_n321_n84# 0.04fF
+C16 a_n417_n84# a_n33_n84# 0.04fF
+C17 a_63_n84# a_n225_n84# 0.05fF
+C18 a_351_n84# a_543_n84# 0.09fF
+C19 a_n705_n84# w_n935_n303# 0.04fF
+C20 a_n513_n84# a_n321_n84# 0.09fF
+C21 a_n797_n84# w_n935_n303# 0.08fF
+C22 a_255_n84# a_447_n84# 0.09fF
+C23 a_159_n84# a_n225_n84# 0.04fF
+C24 a_447_n84# w_n935_n303# 0.02fF
+C25 a_n513_n84# w_n935_n303# 0.02fF
+C26 a_n33_n84# a_n321_n84# 0.05fF
+C27 a_639_n84# a_447_n84# 0.09fF
+C28 a_255_n84# a_n33_n84# 0.05fF
+C29 a_n225_n84# a_n609_n84# 0.04fF
+C30 a_735_n84# w_n935_n303# 0.08fF
+C31 a_63_n84# a_447_n84# 0.04fF
+C32 a_n225_n84# a_n129_n84# 0.24fF
+C33 a_n417_n84# a_n321_n84# 0.24fF
+C34 a_735_n84# a_639_n84# 0.24fF
+C35 a_n609_n84# a_n705_n84# 0.24fF
+C36 a_159_n84# a_447_n84# 0.05fF
+C37 a_n797_n84# a_n609_n84# 0.09fF
+C38 a_63_n84# a_n33_n84# 0.24fF
+C39 a_n609_n84# a_n513_n84# 0.24fF
+C40 a_351_n84# a_447_n84# 0.24fF
+C41 a_159_n84# a_n33_n84# 0.09fF
+C42 a_n129_n84# a_n513_n84# 0.04fF
+C43 a_735_n84# a_351_n84# 0.04fF
+C44 a_543_n84# a_447_n84# 0.24fF
+C45 a_351_n84# a_n33_n84# 0.04fF
+C46 a_n129_n84# a_n33_n84# 0.24fF
+C47 a_63_n84# a_n321_n84# 0.04fF
+C48 a_639_n84# a_255_n84# 0.04fF
+C49 a_735_n84# a_543_n84# 0.09fF
+C50 a_255_n84# a_63_n84# 0.09fF
+C51 a_n417_n84# a_n609_n84# 0.09fF
+C52 a_n417_n84# a_n129_n84# 0.05fF
+C53 a_639_n84# w_n935_n303# 0.04fF
+C54 a_159_n84# a_255_n84# 0.24fF
+C55 a_n609_n84# a_n321_n84# 0.05fF
+C56 a_n797_n84# a_n705_n84# 0.24fF
+C57 a_n225_n84# a_n513_n84# 0.05fF
+C58 a_n129_n84# a_n321_n84# 0.09fF
+C59 a_351_n84# a_255_n84# 0.24fF
+C60 a_255_n84# a_n129_n84# 0.04fF
+C61 a_n705_n84# a_n513_n84# 0.09fF
+C62 a_159_n84# a_63_n84# 0.24fF
+C63 a_n609_n84# w_n935_n303# 0.03fF
+C64 a_n225_n84# a_n33_n84# 0.09fF
+C65 a_n797_n84# a_n513_n84# 0.05fF
C66 a_735_n84# VSUBS 0.03fF
C67 a_639_n84# VSUBS 0.03fF
C68 a_543_n84# VSUBS 0.03fF
@@ -459,64 +459,64 @@
X13 a_n225_n42# a_n757_64# a_n321_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
X14 a_n129_n42# a_n757_64# a_n225_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
X15 a_n609_n42# a_n757_64# a_n705_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-C0 a_351_n42# a_159_n42# 0.05fF
-C1 a_n797_n42# a_n609_n42# 0.05fF
-C2 a_n417_n42# a_n225_n42# 0.05fF
-C3 a_n129_n42# a_255_n42# 0.02fF
-C4 a_n33_n42# a_351_n42# 0.02fF
-C5 a_159_n42# a_255_n42# 0.12fF
-C6 a_n513_n42# a_n417_n42# 0.12fF
-C7 a_n417_n42# a_n705_n42# 0.03fF
-C8 a_351_n42# a_543_n42# 0.05fF
-C9 a_543_n42# a_639_n42# 0.12fF
-C10 a_n129_n42# a_n225_n42# 0.12fF
-C11 a_n33_n42# a_255_n42# 0.03fF
-C12 a_351_n42# a_639_n42# 0.03fF
-C13 a_n225_n42# a_159_n42# 0.02fF
-C14 a_543_n42# a_255_n42# 0.03fF
-C15 a_n129_n42# a_n513_n42# 0.02fF
-C16 a_n129_n42# a_63_n42# 0.05fF
-C17 a_351_n42# a_255_n42# 0.12fF
-C18 a_n417_n42# a_n321_n42# 0.12fF
-C19 a_639_n42# a_255_n42# 0.02fF
-C20 a_n33_n42# a_n225_n42# 0.05fF
-C21 a_n513_n42# a_n797_n42# 0.03fF
-C22 a_n797_n42# a_n705_n42# 0.12fF
-C23 a_159_n42# a_63_n42# 0.12fF
-C24 a_n609_n42# a_n225_n42# 0.02fF
-C25 a_n129_n42# a_n321_n42# 0.05fF
-C26 a_735_n42# a_447_n42# 0.03fF
-C27 a_n33_n42# a_63_n42# 0.12fF
-C28 a_n513_n42# a_n609_n42# 0.12fF
-C29 a_n609_n42# a_n705_n42# 0.12fF
-C30 a_159_n42# a_447_n42# 0.03fF
-C31 a_351_n42# a_63_n42# 0.03fF
-C32 a_n33_n42# a_n321_n42# 0.03fF
-C33 a_543_n42# a_447_n42# 0.12fF
-C34 a_255_n42# a_63_n42# 0.05fF
-C35 a_n129_n42# a_n417_n42# 0.03fF
-C36 a_n609_n42# a_n321_n42# 0.03fF
-C37 a_351_n42# a_447_n42# 0.12fF
-C38 a_639_n42# a_447_n42# 0.05fF
-C39 a_n513_n42# a_n225_n42# 0.03fF
-C40 a_n417_n42# a_n797_n42# 0.02fF
-C41 a_n225_n42# a_63_n42# 0.03fF
-C42 a_n513_n42# a_n705_n42# 0.05fF
-C43 a_447_n42# a_255_n42# 0.05fF
-C44 a_n33_n42# a_n417_n42# 0.02fF
-C45 a_n129_n42# a_159_n42# 0.03fF
-C46 a_n225_n42# a_n321_n42# 0.12fF
-C47 a_n417_n42# a_n609_n42# 0.05fF
-C48 a_n129_n42# a_n33_n42# 0.12fF
-C49 a_543_n42# a_735_n42# 0.05fF
-C50 a_n513_n42# a_n321_n42# 0.05fF
-C51 a_n705_n42# a_n321_n42# 0.02fF
-C52 a_n33_n42# a_159_n42# 0.05fF
-C53 a_n321_n42# a_63_n42# 0.02fF
-C54 a_351_n42# a_735_n42# 0.02fF
-C55 a_735_n42# a_639_n42# 0.12fF
-C56 a_447_n42# a_63_n42# 0.02fF
-C57 a_543_n42# a_159_n42# 0.02fF
+C0 a_255_n42# a_543_n42# 0.03fF
+C1 a_351_n42# a_447_n42# 0.12fF
+C2 a_n225_n42# a_n321_n42# 0.12fF
+C3 a_159_n42# a_255_n42# 0.12fF
+C4 a_n129_n42# a_159_n42# 0.03fF
+C5 a_447_n42# a_543_n42# 0.12fF
+C6 a_639_n42# a_255_n42# 0.02fF
+C7 a_n321_n42# a_n33_n42# 0.03fF
+C8 a_159_n42# a_447_n42# 0.03fF
+C9 a_n129_n42# a_255_n42# 0.02fF
+C10 a_n417_n42# a_n321_n42# 0.12fF
+C11 a_n225_n42# a_63_n42# 0.03fF
+C12 a_639_n42# a_447_n42# 0.05fF
+C13 a_255_n42# a_447_n42# 0.05fF
+C14 a_63_n42# a_n33_n42# 0.12fF
+C15 a_n513_n42# a_n321_n42# 0.05fF
+C16 a_n705_n42# a_n417_n42# 0.03fF
+C17 a_n321_n42# a_n609_n42# 0.03fF
+C18 a_n225_n42# a_n33_n42# 0.05fF
+C19 a_n417_n42# a_n225_n42# 0.05fF
+C20 a_n705_n42# a_n513_n42# 0.05fF
+C21 a_351_n42# a_63_n42# 0.03fF
+C22 a_n417_n42# a_n33_n42# 0.02fF
+C23 a_n129_n42# a_n321_n42# 0.05fF
+C24 a_n513_n42# a_n225_n42# 0.03fF
+C25 a_159_n42# a_63_n42# 0.12fF
+C26 a_n705_n42# a_n797_n42# 0.12fF
+C27 a_n705_n42# a_n609_n42# 0.12fF
+C28 a_255_n42# a_63_n42# 0.05fF
+C29 a_n129_n42# a_63_n42# 0.05fF
+C30 a_n417_n42# a_n513_n42# 0.12fF
+C31 a_n225_n42# a_n609_n42# 0.02fF
+C32 a_447_n42# a_63_n42# 0.02fF
+C33 a_351_n42# a_n33_n42# 0.02fF
+C34 a_159_n42# a_n225_n42# 0.02fF
+C35 a_n417_n42# a_n797_n42# 0.02fF
+C36 a_n417_n42# a_n609_n42# 0.05fF
+C37 a_159_n42# a_n33_n42# 0.05fF
+C38 a_n129_n42# a_n225_n42# 0.12fF
+C39 a_351_n42# a_735_n42# 0.02fF
+C40 a_n797_n42# a_n513_n42# 0.03fF
+C41 a_n513_n42# a_n609_n42# 0.12fF
+C42 a_255_n42# a_n33_n42# 0.03fF
+C43 a_n129_n42# a_n33_n42# 0.12fF
+C44 a_735_n42# a_543_n42# 0.05fF
+C45 a_n129_n42# a_n417_n42# 0.03fF
+C46 a_639_n42# a_735_n42# 0.12fF
+C47 a_351_n42# a_543_n42# 0.05fF
+C48 a_n797_n42# a_n609_n42# 0.05fF
+C49 a_63_n42# a_n321_n42# 0.02fF
+C50 a_n129_n42# a_n513_n42# 0.02fF
+C51 a_351_n42# a_159_n42# 0.05fF
+C52 a_351_n42# a_639_n42# 0.03fF
+C53 a_159_n42# a_543_n42# 0.02fF
+C54 a_447_n42# a_735_n42# 0.03fF
+C55 a_n705_n42# a_n321_n42# 0.02fF
+C56 a_351_n42# a_255_n42# 0.12fF
+C57 a_639_n42# a_543_n42# 0.12fF
C58 a_735_n42# w_n935_n252# 0.07fF
C59 a_639_n42# w_n935_n252# 0.05fF
C60 a_543_n42# w_n935_n252# 0.05fF
@@ -542,9 +542,9 @@
+ out vdd out vdd out out out sky130_fd_pr__pfet_01v8_BDRUME
Xsky130_fd_pr__nfet_01v8_QQE8KM_0 out vss out out out out vss vss out vss in vss vss
+ out vss out vss out vss sky130_fd_pr__nfet_01v8_QQE8KM
-C0 vdd in 1.15fF
+C0 in out 1.40fF
C1 vdd out 1.63fF
-C2 in out 1.40fF
+C2 vdd in 1.15fF
C3 out vss 0.98fF
C4 in vss 7.30fF
C5 vdd vss 10.49fF
@@ -556,22 +556,22 @@
X1 a_63_n102# a_25_n199# a_n33_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
X2 a_n129_n102# a_n177_n199# a_n221_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
X3 a_n33_n102# a_n177_n199# a_n129_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
-C0 a_n129_n102# w_n359_n321# 0.07fF
-C1 a_n33_n102# a_n129_n102# 0.30fF
-C2 a_159_n102# w_n359_n321# 0.10fF
-C3 a_159_n102# a_n33_n102# 0.11fF
-C4 a_63_n102# w_n359_n321# 0.07fF
-C5 a_63_n102# a_n33_n102# 0.30fF
-C6 a_159_n102# a_n129_n102# 0.07fF
+C0 a_63_n102# a_159_n102# 0.30fF
+C1 a_63_n102# a_n221_n102# 0.07fF
+C2 a_n33_n102# a_n129_n102# 0.30fF
+C3 w_n359_n321# a_n129_n102# 0.07fF
+C4 a_n177_n199# a_25_n199# 0.07fF
+C5 a_159_n102# a_n129_n102# 0.07fF
+C6 a_n221_n102# a_n129_n102# 0.30fF
C7 a_63_n102# a_n129_n102# 0.11fF
-C8 a_n177_n199# a_25_n199# 0.07fF
-C9 a_63_n102# a_159_n102# 0.30fF
-C10 a_n221_n102# w_n359_n321# 0.10fF
-C11 a_n221_n102# a_n33_n102# 0.11fF
-C12 a_n221_n102# a_n129_n102# 0.30fF
-C13 a_n33_n102# w_n359_n321# 0.06fF
-C14 a_159_n102# a_n221_n102# 0.05fF
-C15 a_63_n102# a_n221_n102# 0.07fF
+C8 a_n33_n102# w_n359_n321# 0.06fF
+C9 a_n33_n102# a_159_n102# 0.11fF
+C10 a_n221_n102# a_n33_n102# 0.11fF
+C11 w_n359_n321# a_159_n102# 0.10fF
+C12 a_n221_n102# w_n359_n321# 0.10fF
+C13 a_n221_n102# a_159_n102# 0.05fF
+C14 a_63_n102# a_n33_n102# 0.30fF
+C15 a_63_n102# w_n359_n321# 0.07fF
C16 a_159_n102# VSUBS 0.03fF
C17 a_63_n102# VSUBS 0.03fF
C18 a_n33_n102# VSUBS 0.03fF
@@ -586,8 +586,8 @@
+ a_n81_124#
X0 a_n33_n102# a_n81_124# a_n125_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
X1 a_63_n102# a_n81_124# a_n33_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
-C0 a_n125_n102# a_63_n102# 0.11fF
-C1 a_n125_n102# a_n33_n102# 0.30fF
+C0 a_63_n102# a_n125_n102# 0.11fF
+C1 a_n33_n102# a_n125_n102# 0.30fF
C2 a_n33_n102# a_63_n102# 0.30fF
C3 a_63_n102# w_n263_n312# 0.06fF
C4 a_n33_n102# w_n263_n312# 0.08fF
@@ -600,14 +600,14 @@
+ avdd1p8 sky130_fd_pr__pfet_01v8_75PKJG
Xsky130_fd_pr__nfet_01v8_XRJ78J_0 m1_21_n341# avss1p8 avss1p8 avss1p8 in1 sky130_fd_pr__nfet_01v8_XRJ78J
Xsky130_fd_pr__nfet_01v8_XRJ78J_1 out avss1p8 m1_21_n341# m1_21_n341# in2 sky130_fd_pr__nfet_01v8_XRJ78J
-C0 out m1_21_n341# 0.13fF
-C1 out avdd1p8 0.20fF
-C2 avdd1p8 in2 0.02fF
-C3 out in1 0.10fF
+C0 avdd1p8 out 0.20fF
+C1 in1 out 0.10fF
+C2 in2 avdd1p8 0.02fF
+C3 in2 out 0.37fF
C4 m1_21_n341# avdd1p8 0.01fF
-C5 in1 in2 0.07fF
-C6 m1_21_n341# in1 0.25fF
-C7 out in2 0.37fF
+C5 m1_21_n341# out 0.13fF
+C6 in2 in1 0.07fF
+C7 m1_21_n341# in1 0.25fF
C8 m1_21_n341# avss1p8 0.92fF
C9 out avss1p8 0.47fF
C10 in2 avss1p8 0.91fF
@@ -622,32 +622,32 @@
+ DFlipFlop_4/latch_diff_0/D DFlipFlop_3/latch_diff_1/D clk_amp DFlipFlop_3/nQ clkp
+ rst
XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_0/latch_diff_1/D
-+ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ clkn DFlipFlop_0/latch_diff_0/nD
+ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_3/D
+ DFlipFlop_0/latch_diff_0/D clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ clkn DFlipFlop
++ DFlipFlop
XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_1/latch_diff_1/D
-+ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/nQ DFlipFlop_1/latch_diff_0/nD
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/nQ DFlipFlop_0/Q DFlipFlop_1/latch_diff_0/nD
+ DFlipFlop_2/D DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
+ DFlipFlop_1/latch_diff_0/D DFlipFlop_3/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_0/Q DFlipFlop
++ DFlipFlop
XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_2/latch_diff_1/D
-+ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ clkn DFlipFlop_2/latch_diff_0/nD
+ DFlipFlop_2/Q DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
+ DFlipFlop_2/latch_diff_0/D clkp DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
-+ clkn DFlipFlop
++ DFlipFlop
XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_3/latch_diff_1/D
-+ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ clkn DFlipFlop_3/latch_diff_0/nD
+ DFlipFlop_3/Q DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/D
+ DFlipFlop_3/latch_diff_0/D clkp DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
-+ clkn DFlipFlop
++ DFlipFlop
Xinverter_min_x4_0 avdd1p8 DFlipFlop_0/Q vss DFlipFlop_3/D inverter_min_x4
Xinverter_min_x4_1 avdd1p8 nand_logic_0/out vss DFlipFlop_4/D inverter_min_x4
XDFlipFlop_4 DFlipFlop_4/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_4/latch_diff_1/D
-+ DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_4/nQ DFlipFlop_4/latch_diff_0/nD
++ DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_4/nQ clkn DFlipFlop_4/latch_diff_0/nD
+ DFlipFlop_4/Q DFlipFlop_4/latch_diff_1/nD DFlipFlop_4/latch_diff_1/m1_657_280# DFlipFlop_4/D
+ DFlipFlop_4/latch_diff_0/D clkp DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out
-+ clkn DFlipFlop
++ DFlipFlop
Xinverter_min_x4_2 avdd1p8 DFlipFlop_2/D vss DFlipFlop_1/D inverter_min_x4
Xinverter_min_x4_3 avdd1p8 nand_logic_1/out vss rst inverter_min_x4
Xinverter_min_x4_4 avdd1p8 DFlipFlop_4/Q vss inverter_min_x4_4/out inverter_min_x4
@@ -656,200 +656,200 @@
+ nand_logic
Xnand_logic_1 vss DFlipFlop_4/D avdd1p8 clkp nand_logic_1/out nand_logic_1/m1_21_n341#
+ nand_logic
-C0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
-C1 DFlipFlop_1/D DFlipFlop_1/latch_diff_1/D 0.02fF
-C2 clkp avdd1p8 0.53fF
-C3 DFlipFlop_1/latch_diff_0/D DFlipFlop_0/Q 0.74fF
-C4 DFlipFlop_3/Q clkn 0.12fF
-C5 DFlipFlop_2/D DFlipFlop_2/nQ 0.03fF
-C6 nand_logic_1/m1_21_n341# nand_logic_1/out 0.01fF
-C7 DFlipFlop_4/Q avdd1p8 4.03fF
-C8 clkn DFlipFlop_4/latch_diff_1/D 0.08fF
-C9 nand_logic_0/out DFlipFlop_2/Q 0.02fF
+C0 clkp nand_logic_1/out 0.03fF
+C1 DFlipFlop_3/nQ avdd1p8 0.03fF
+C2 clkp DFlipFlop_2/nQ 0.13fF
+C3 DFlipFlop_1/latch_diff_0/m1_657_280# DFlipFlop_3/D 0.28fF
+C4 DFlipFlop_3/D DFlipFlop_2/D 0.06fF
+C5 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/D 0.08fF
+C6 DFlipFlop_1/D DFlipFlop_1/nQ 0.02fF
+C7 DFlipFlop_3/Q DFlipFlop_2/nQ 0.02fF
+C8 clkn DFlipFlop_4/nQ 0.02fF
+C9 clkn DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
C10 DFlipFlop_0/Q avdd1p8 0.66fF
-C11 clkp DFlipFlop_4/nQ 0.02fF
-C12 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_3/D 0.43fF
-C13 clkp DFlipFlop_2/Q 0.11fF
-C14 clkp DFlipFlop_3/D 0.35fF
-C15 clkp DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
-C16 DFlipFlop_0/latch_diff_0/D DFlipFlop_3/D 0.31fF
-C17 nand_logic_1/out avdd1p8 0.04fF
-C18 nand_logic_1/m1_21_n341# DFlipFlop_4/D 0.09fF
-C19 DFlipFlop_3/nQ avdd1p8 0.03fF
-C20 DFlipFlop_2/D avdd1p8 4.16fF
-C21 clkp DFlipFlop_4/latch_diff_0/nD 0.08fF
-C22 clk_amp inverter_min_x4_4/out 0.12fF
-C23 clkn DFlipFlop_3/latch_diff_1/nD 0.17fF
-C24 DFlipFlop_3/Q nand_logic_0/out 0.01fF
-C25 DFlipFlop_4/Q DFlipFlop_4/nQ 0.06fF
-C26 DFlipFlop_4/latch_diff_1/nD clkn 0.17fF
-C27 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.03fF
-C28 clkp DFlipFlop_2/latch_diff_0/nD 0.08fF
-C29 DFlipFlop_3/latch_diff_1/m1_657_280# clkn 0.30fF
-C30 clkp DFlipFlop_3/Q 0.17fF
-C31 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/D 0.49fF
-C32 DFlipFlop_1/nQ DFlipFlop_3/D 0.05fF
-C33 clkp DFlipFlop_0/latch_diff_0/nD 0.08fF
-C34 DFlipFlop_3/Q nand_logic_0/m1_21_n341# 0.07fF
-C35 DFlipFlop_4/D avdd1p8 0.52fF
-C36 DFlipFlop_3/D DFlipFlop_0/Q 0.38fF
-C37 clkp DFlipFlop_4/latch_diff_1/D 0.15fF
-C38 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/D 0.10fF
-C39 clkp clkn 0.22fF
-C40 DFlipFlop_0/latch_diff_0/D clkn 0.12fF
-C41 clkp DFlipFlop_2/latch_diff_0/m1_657_280# 0.30fF
-C42 DFlipFlop_4/Q DFlipFlop_3/Q 0.11fF
-C43 DFlipFlop_2/latch_diff_1/D DFlipFlop_3/Q 0.03fF
-C44 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.03fF
-C45 DFlipFlop_3/D DFlipFlop_2/D 0.06fF
-C46 clkp inverter_min_x4_4/out 0.43fF
-C47 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/D 0.54fF
-C48 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.02fF
-C49 clkp clk_amp 0.52fF
+C11 DFlipFlop_2/latch_diff_0/D DFlipFlop_2/D -0.07fF
+C12 clkn DFlipFlop_3/latch_diff_1/nD 0.17fF
+C13 nand_logic_1/out DFlipFlop_4/D 0.01fF
+C14 clkp DFlipFlop_4/latch_diff_0/m1_657_280# 0.30fF
+C15 DFlipFlop_2/D avdd1p8 4.16fF
+C16 clkp DFlipFlop_0/latch_diff_0/nD 0.08fF
+C17 nand_logic_0/out DFlipFlop_2/Q 0.02fF
+C18 clkn DFlipFlop_3/D 0.35fF
+C19 DFlipFlop_3/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.43fF
+C20 clkn DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C21 nand_logic_0/out avdd1p8 0.03fF
+C22 DFlipFlop_1/latch_diff_1/D DFlipFlop_0/Q 0.10fF
+C23 avdd1p8 clk_amp 0.10fF
+C24 clkn DFlipFlop_4/latch_diff_1/D 0.08fF
+C25 clkp DFlipFlop_3/Q 0.17fF
+C26 DFlipFlop_0/latch_diff_0/D DFlipFlop_3/D 0.31fF
+C27 clkp DFlipFlop_3/latch_diff_0/m1_657_280# 0.30fF
+C28 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/Q 0.55fF
+C29 clkn DFlipFlop_0/nQ 0.02fF
+C30 clkn DFlipFlop_2/latch_diff_0/D 0.12fF
+C31 nand_logic_0/m1_21_n341# DFlipFlop_3/Q 0.07fF
+C32 clkp DFlipFlop_2/latch_diff_0/m1_657_280# 0.30fF
+C33 DFlipFlop_4/latch_diff_1/nD clkn 0.17fF
+C34 clkp DFlipFlop_4/D 0.24fF
+C35 inverter_min_x4_4/out avdd1p8 0.09fF
+C36 clkn avdd1p8 -1.00fF
+C37 avdd1p8 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.01fF
+C38 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/nD 0.19fF
+C39 nand_logic_0/m1_21_n341# DFlipFlop_4/D 0.02fF
+C40 clkn DFlipFlop_3/latch_diff_1/D 0.08fF
+C41 DFlipFlop_4/Q inverter_min_x4_4/out 0.01fF
+C42 DFlipFlop_3/Q DFlipFlop_4/D 0.94fF
+C43 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/D 0.49fF
+C44 clkp DFlipFlop_4/latch_diff_0/nD 0.08fF
+C45 clkn DFlipFlop_0/latch_diff_1/nD 0.17fF
+C46 clkp DFlipFlop_4/nQ 0.02fF
+C47 DFlipFlop_1/D DFlipFlop_3/D 0.28fF
+C48 clkn DFlipFlop_3/nQ 0.10fF
+C49 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
C50 clkp DFlipFlop_3/latch_diff_1/nD 0.10fF
-C51 DFlipFlop_2/latch_diff_1/D clkn 0.08fF
+C51 clkn DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
C52 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
-C53 DFlipFlop_4/latch_diff_1/nD clkp 0.10fF
-C54 DFlipFlop_1/nQ DFlipFlop_1/D 0.02fF
-C55 DFlipFlop_2/latch_diff_0/D clkn 0.12fF
-C56 DFlipFlop_4/Q inverter_min_x4_4/out 0.01fF
-C57 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/nD 0.17fF
-C58 DFlipFlop_0/Q DFlipFlop_1/D 0.72fF
-C59 DFlipFlop_3/nQ clkn 0.10fF
-C60 clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
-C61 nand_logic_0/out nand_logic_0/m1_21_n341# 0.01fF
-C62 rst nand_logic_1/out 0.04fF
-C63 DFlipFlop_2/D clkn 0.15fF
-C64 DFlipFlop_2/D DFlipFlop_1/D 0.02fF
-C65 DFlipFlop_4/D DFlipFlop_3/Q 0.94fF
-C66 DFlipFlop_0/nQ DFlipFlop_3/D 0.08fF
-C67 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
-C68 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/nD 0.02fF
-C69 clkp DFlipFlop_3/latch_diff_0/nD 0.08fF
-C70 DFlipFlop_0/latch_diff_1/D DFlipFlop_3/D 0.08fF
-C71 clkp DFlipFlop_4/latch_diff_0/m1_657_280# 0.30fF
-C72 DFlipFlop_4/D clkn 0.15fF
-C73 DFlipFlop_4/Q clkp 0.20fF
-C74 clkp DFlipFlop_2/latch_diff_1/D 0.15fF
-C75 DFlipFlop_0/latch_diff_1/nD clkn 0.17fF
-C76 DFlipFlop_0/latch_diff_1/m1_657_280# clkn 0.30fF
-C77 DFlipFlop_3/Q DFlipFlop_2/latch_diff_1/m1_657_280# 0.04fF
-C78 DFlipFlop_3/Q DFlipFlop_2/nQ 0.02fF
-C79 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/m1_657_280# 0.25fF
-C80 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in clkn -0.33fF
-C81 avdd1p8 DFlipFlop_2/Q 0.05fF
-C82 DFlipFlop_3/D DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
-C83 DFlipFlop_3/D avdd1p8 4.16fF
-C84 clkp nand_logic_1/out 0.03fF
-C85 DFlipFlop_0/nQ clkn 0.02fF
-C86 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
-C87 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/D 0.41fF
+C53 nand_logic_1/out avdd1p8 0.04fF
+C54 clkp DFlipFlop_3/D 0.35fF
+C55 DFlipFlop_1/nQ DFlipFlop_3/D 0.05fF
+C56 rst avdd1p8 0.02fF
+C57 clkp DFlipFlop_4/latch_diff_1/D 0.15fF
+C58 DFlipFlop_1/D avdd1p8 2.55fF
+C59 clkn DFlipFlop_4/latch_diff_1/m1_657_280# 0.30fF
+C60 clkp DFlipFlop_0/nQ 0.02fF
+C61 DFlipFlop_2/latch_diff_1/D DFlipFlop_2/D 0.03fF
+C62 DFlipFlop_3/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.54fF
+C63 clkp DFlipFlop_4/latch_diff_1/nD 0.10fF
+C64 clkn DFlipFlop_2/D 0.15fF
+C65 clkn DFlipFlop_0/latch_diff_1/D 0.08fF
+C66 inverter_min_x4_4/out clk_amp 0.12fF
+C67 clkp DFlipFlop_2/Q 0.11fF
+C68 clkp avdd1p8 0.53fF
+C69 DFlipFlop_1/D DFlipFlop_1/latch_diff_1/D 0.02fF
+C70 clkn DFlipFlop_4/latch_diff_0/D 0.12fF
+C71 clkp DFlipFlop_3/latch_diff_1/D 0.15fF
+C72 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.41fF
+C73 clkp DFlipFlop_4/Q 0.20fF
+C74 DFlipFlop_2/latch_diff_1/nD clkn 0.17fF
+C75 DFlipFlop_1/latch_diff_0/D DFlipFlop_0/Q 0.74fF
+C76 DFlipFlop_3/Q DFlipFlop_2/Q 0.09fF
+C77 DFlipFlop_3/Q avdd1p8 0.76fF
+C78 clkn DFlipFlop_2/latch_diff_1/D 0.08fF
+C79 clkp DFlipFlop_0/latch_diff_1/nD 0.10fF
+C80 clkp DFlipFlop_2/latch_diff_0/nD 0.08fF
+C81 nand_logic_1/out nand_logic_1/m1_21_n341# 0.01fF
+C82 DFlipFlop_3/Q DFlipFlop_4/Q 0.11fF
+C83 clkp DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C84 clkn DFlipFlop_0/latch_diff_0/D 0.12fF
+C85 rst nand_logic_1/m1_21_n341# 0.02fF
+C86 DFlipFlop_4/D avdd1p8 0.52fF
+C87 clkn DFlipFlop_3/latch_diff_1/m1_657_280# 0.30fF
C88 clkp DFlipFlop_3/nQ 0.13fF
-C89 DFlipFlop_2/latch_diff_1/m1_657_280# clkn 0.30fF
-C90 clkn DFlipFlop_2/nQ 0.02fF
-C91 clkp DFlipFlop_2/D 0.15fF
-C92 DFlipFlop_0/latch_diff_1/D clkn 0.08fF
-C93 clkp DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
-C94 DFlipFlop_1/nQ DFlipFlop_0/Q 0.01fF
-C95 DFlipFlop_4/D nand_logic_0/out 0.04fF
-C96 DFlipFlop_3/Q avdd1p8 0.76fF
-C97 DFlipFlop_3/latch_diff_1/D clkn 0.08fF
-C98 nand_logic_1/m1_21_n341# rst 0.02fF
-C99 DFlipFlop_4/latch_diff_0/D clkn 0.12fF
-C100 clkp DFlipFlop_4/D 0.24fF
-C101 clkn DFlipFlop_2/latch_diff_1/nD 0.17fF
-C102 DFlipFlop_2/latch_diff_1/D DFlipFlop_2/D 0.03fF
-C103 clkp DFlipFlop_0/latch_diff_0/m1_657_280# 0.32fF
-C104 clkp DFlipFlop_3/latch_diff_0/m1_657_280# 0.30fF
-C105 clkp DFlipFlop_0/latch_diff_1/nD 0.10fF
-C106 DFlipFlop_4/D nand_logic_0/m1_21_n341# 0.02fF
-C107 DFlipFlop_3/latch_diff_0/D clkn 0.12fF
-C108 DFlipFlop_2/D DFlipFlop_2/latch_diff_0/D -0.07fF
-C109 avdd1p8 clkn -1.00fF
-C110 DFlipFlop_1/D avdd1p8 2.55fF
-C111 rst avdd1p8 0.02fF
-C112 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/D 0.03fF
-C113 avdd1p8 inverter_min_x4_4/out 0.09fF
-C114 DFlipFlop_4/Q DFlipFlop_4/D 0.27fF
-C115 clkp DFlipFlop_0/nQ 0.02fF
-C116 clk_amp avdd1p8 0.10fF
-C117 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
-C118 clkp DFlipFlop_2/nQ 0.13fF
-C119 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
-C120 clkp DFlipFlop_0/latch_diff_1/D 0.15fF
-C121 DFlipFlop_3/Q DFlipFlop_2/Q 0.09fF
-C122 clkp DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
-C123 nand_logic_1/m1_21_n341# clkp 0.09fF
-C124 DFlipFlop_4/D nand_logic_1/out 0.01fF
-C125 clkp DFlipFlop_3/latch_diff_1/D 0.15fF
-C126 DFlipFlop_4/nQ clkn 0.02fF
-C127 clkp DFlipFlop_2/latch_diff_1/nD 0.20fF
-C128 DFlipFlop_3/D clkn 0.35fF
-C129 DFlipFlop_3/D DFlipFlop_1/D 0.28fF
-C130 DFlipFlop_0/Q DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.55fF
-C131 avdd1p8 nand_logic_0/out 0.03fF
-C132 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/nD 0.19fF
-C133 DFlipFlop_4/D DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out 0.42fF
-C134 DFlipFlop_4/latch_diff_1/m1_657_280# clkn 0.30fF
+C89 DFlipFlop_1/D DFlipFlop_0/Q 0.72fF
+C90 DFlipFlop_4/Q DFlipFlop_4/D 0.27fF
+C91 DFlipFlop_2/D DFlipFlop_2/nQ 0.03fF
+C92 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_0/Q 0.25fF
+C93 clkn DFlipFlop_2/latch_diff_1/m1_657_280# 0.30fF
+C94 DFlipFlop_1/D DFlipFlop_2/D 0.02fF
+C95 clkp nand_logic_1/m1_21_n341# 0.09fF
+C96 DFlipFlop_1/nQ DFlipFlop_0/Q 0.01fF
+C97 clkp DFlipFlop_0/latch_diff_0/m1_657_280# 0.32fF
+C98 DFlipFlop_4/D DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out 0.42fF
+C99 clkn DFlipFlop_2/nQ 0.02fF
+C100 clkp DFlipFlop_2/D 0.15fF
+C101 clkp DFlipFlop_0/latch_diff_1/D 0.15fF
+C102 DFlipFlop_0/nQ DFlipFlop_3/D 0.08fF
+C103 clkp clk_amp 0.52fF
+C104 DFlipFlop_4/nQ DFlipFlop_4/Q 0.06fF
+C105 nand_logic_0/out nand_logic_0/m1_21_n341# 0.01fF
+C106 DFlipFlop_4/D nand_logic_1/m1_21_n341# 0.09fF
+C107 DFlipFlop_3/D avdd1p8 4.16fF
+C108 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.03fF
+C109 nand_logic_0/out DFlipFlop_3/Q 0.01fF
+C110 DFlipFlop_2/latch_diff_1/nD clkp 0.20fF
+C111 clkp DFlipFlop_2/latch_diff_1/D 0.15fF
+C112 clkp inverter_min_x4_4/out 0.43fF
+C113 DFlipFlop_3/latch_diff_0/nD clkp 0.08fF
+C114 clkp clkn 0.22fF
+C115 clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C116 nand_logic_0/out DFlipFlop_4/D 0.04fF
+C117 DFlipFlop_0/latch_diff_1/nD DFlipFlop_3/D 0.17fF
+C118 DFlipFlop_3/Q DFlipFlop_2/latch_diff_1/D 0.03fF
+C119 DFlipFlop_1/latch_diff_1/D DFlipFlop_3/D 0.03fF
+C120 clkn DFlipFlop_3/latch_diff_0/D 0.12fF
+C121 DFlipFlop_2/Q avdd1p8 0.05fF
+C122 clkn DFlipFlop_3/Q 0.12fF
+C123 clkn DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C124 DFlipFlop_4/Q avdd1p8 4.03fF
+C125 nand_logic_1/out rst 0.04fF
+C126 DFlipFlop_0/latch_diff_1/m1_657_280# clkn 0.30fF
+C127 clkn DFlipFlop_4/D 0.15fF
+C128 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out clkp 0.16fF
+C129 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/nD 0.02fF
+C130 DFlipFlop_0/Q DFlipFlop_3/D 0.38fF
+C131 avdd1p8 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C132 clkp DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C133 DFlipFlop_3/Q DFlipFlop_2/latch_diff_1/m1_657_280# 0.04fF
+C134 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.02fF
C135 nand_logic_1/m1_21_n341# vss 0.86fF
C136 nand_logic_0/m1_21_n341# vss 0.90fF
C137 clk_amp vss 0.43fF
C138 inverter_min_x4_4/out vss 5.90fF
-C139 nand_logic_1/out vss 1.76fF
-C140 rst vss 0.71fF
-C141 DFlipFlop_4/nQ vss 0.48fF
-C142 DFlipFlop_4/Q vss -2.08fF
-C143 DFlipFlop_4/latch_diff_1/m1_657_280# vss 0.57fF
-C144 DFlipFlop_4/latch_diff_1/nD vss 0.57fF
-C145 DFlipFlop_4/latch_diff_1/D vss -1.73fF
-C146 DFlipFlop_4/latch_diff_0/m1_657_280# vss 0.57fF
+C139 rst vss 0.71fF
+C140 nand_logic_1/out vss 1.76fF
+C141 DFlipFlop_4/Q vss -2.08fF
+C142 DFlipFlop_4/latch_diff_1/m1_657_280# vss 0.57fF
+C143 DFlipFlop_4/nQ vss 0.48fF
+C144 DFlipFlop_4/latch_diff_1/D vss -1.73fF
+C145 DFlipFlop_4/latch_diff_0/m1_657_280# vss 0.57fF
+C146 DFlipFlop_4/latch_diff_1/nD vss 0.57fF
C147 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
C148 DFlipFlop_4/latch_diff_0/D vss 0.96fF
C149 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
C150 DFlipFlop_4/D vss 4.59fF
C151 DFlipFlop_4/latch_diff_0/nD vss 1.14fF
C152 nand_logic_0/out vss 1.26fF
-C153 DFlipFlop_0/Q vss -3.86fF
-C154 DFlipFlop_3/nQ vss 0.50fF
-C155 DFlipFlop_3/Q vss -2.01fF
-C156 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.72fF
-C157 clkn vss -2.25fF
-C158 DFlipFlop_3/latch_diff_1/nD vss 0.58fF
-C159 DFlipFlop_3/latch_diff_1/D vss -1.72fF
-C160 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
-C161 clkp vss -22.80fF
-C162 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C163 DFlipFlop_3/latch_diff_0/D vss 0.96fF
-C164 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C165 DFlipFlop_3/D vss 1.64fF
+C153 DFlipFlop_3/Q vss -2.01fF
+C154 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.72fF
+C155 clkn vss -2.25fF
+C156 DFlipFlop_3/nQ vss 0.50fF
+C157 DFlipFlop_3/latch_diff_1/D vss -1.72fF
+C158 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C159 clkp vss -22.80fF
+C160 DFlipFlop_3/latch_diff_1/nD vss 0.58fF
+C161 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C162 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C163 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C164 DFlipFlop_3/D vss 1.64fF
+C165 avdd1p8 vss 196.01fF
C166 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C167 avdd1p8 vss 196.01fF
-C168 DFlipFlop_2/nQ vss 0.48fF
-C169 DFlipFlop_2/Q vss -1.05fF
-C170 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.65fF
-C171 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
-C172 DFlipFlop_2/latch_diff_1/D vss -1.73fF
-C173 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C174 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C175 DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C176 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C177 DFlipFlop_2/D vss -0.35fF
-C178 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C167 DFlipFlop_2/Q vss -1.05fF
+C168 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.65fF
+C169 DFlipFlop_2/nQ vss 0.48fF
+C170 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C171 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C172 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C173 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C174 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C175 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C176 DFlipFlop_2/D vss -0.35fF
+C177 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C178 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.59fF
C179 DFlipFlop_1/nQ vss 0.48fF
-C180 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.59fF
-C181 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C182 DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C183 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C184 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
-C185 DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C186 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C187 DFlipFlop_1/D vss -1.00fF
-C188 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
-C189 DFlipFlop_0/nQ vss 0.48fF
-C190 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.59fF
-C191 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C192 DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C193 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C180 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C181 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C182 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C183 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C184 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C185 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C186 DFlipFlop_1/D vss -1.00fF
+C187 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C188 DFlipFlop_0/Q vss -3.86fF
+C189 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.59fF
+C190 DFlipFlop_0/nQ vss 0.48fF
+C191 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C192 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C193 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
C194 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C195 DFlipFlop_0/latch_diff_0/D vss 0.96fF
C196 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
@@ -863,29 +863,29 @@
X2 a_35_n200# a_n291_n238# a_n93_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
X3 a_163_n200# a_n291_n238# a_35_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
X4 a_n93_n200# a_n291_n238# a_n221_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
-C0 a_n221_n200# a_35_n200# 0.15fF
-C1 w_n487_n419# a_291_n200# 0.18fF
-C2 a_n93_n200# a_n291_n238# 0.08fF
-C3 a_291_n200# a_163_n200# 0.36fF
-C4 w_n487_n419# a_163_n200# 0.08fF
-C5 a_35_n200# a_n291_n238# 0.08fF
-C6 a_n221_n200# w_n487_n419# 0.08fF
-C7 a_n221_n200# a_163_n200# 0.09fF
-C8 a_n291_n238# w_n487_n419# 0.30fF
-C9 a_n291_n238# a_163_n200# 0.08fF
-C10 a_n93_n200# a_n349_n200# 0.15fF
-C11 a_n221_n200# a_n291_n238# 0.08fF
-C12 a_35_n200# a_n349_n200# 0.09fF
-C13 w_n487_n419# a_n349_n200# 0.18fF
-C14 a_n221_n200# a_n349_n200# 0.36fF
-C15 a_n93_n200# a_35_n200# 0.36fF
-C16 a_n93_n200# a_291_n200# 0.09fF
-C17 a_n93_n200# w_n487_n419# 0.06fF
+C0 a_n93_n200# a_n291_n238# 0.08fF
+C1 a_n349_n200# a_35_n200# 0.09fF
+C2 a_n349_n200# a_n221_n200# 0.36fF
+C3 a_n349_n200# w_n487_n419# 0.18fF
+C4 a_n93_n200# a_n349_n200# 0.15fF
+C5 a_291_n200# a_35_n200# 0.15fF
+C6 a_291_n200# a_163_n200# 0.36fF
+C7 a_291_n200# w_n487_n419# 0.18fF
+C8 a_n93_n200# a_291_n200# 0.09fF
+C9 a_35_n200# a_163_n200# 0.36fF
+C10 a_n221_n200# a_35_n200# 0.15fF
+C11 a_35_n200# w_n487_n419# 0.06fF
+C12 a_35_n200# a_n291_n238# 0.08fF
+C13 a_n221_n200# a_163_n200# 0.09fF
+C14 a_n93_n200# a_35_n200# 0.36fF
+C15 w_n487_n419# a_163_n200# 0.08fF
+C16 a_n221_n200# w_n487_n419# 0.08fF
+C17 a_n291_n238# a_163_n200# 0.08fF
C18 a_n93_n200# a_163_n200# 0.15fF
-C19 a_35_n200# a_291_n200# 0.15fF
-C20 a_35_n200# w_n487_n419# 0.06fF
-C21 a_n93_n200# a_n221_n200# 0.36fF
-C22 a_35_n200# a_163_n200# 0.36fF
+C19 a_n221_n200# a_n291_n238# 0.08fF
+C20 a_n93_n200# a_n221_n200# 0.36fF
+C21 w_n487_n419# a_n291_n238# 0.30fF
+C22 a_n93_n200# w_n487_n419# 0.06fF
C23 a_291_n200# VSUBS 0.03fF
C24 a_163_n200# VSUBS 0.03fF
C25 a_35_n200# VSUBS 0.03fF
@@ -898,9 +898,9 @@
.subckt sky130_fd_pr__nfet_01v8_L78GGD a_n73_n73# w_n211_n221# a_15_n73# a_n33_33#
X0 a_15_n73# a_n33_33# a_n73_n73# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-C0 a_n73_n73# a_n33_33# 0.02fF
-C1 a_n33_33# a_15_n73# 0.02fF
-C2 a_n73_n73# a_15_n73# 0.15fF
+C0 a_n33_33# a_15_n73# 0.02fF
+C1 a_n73_n73# a_15_n73# 0.15fF
+C2 a_n33_33# a_n73_n73# 0.02fF
C3 a_15_n73# w_n211_n221# 0.11fF
C4 a_n73_n73# w_n211_n221# 0.11fF
C5 a_n33_33# w_n211_n221# 0.18fF
@@ -908,12 +908,12 @@
.subckt sky130_fd_pr__pfet_01v8_6RX2PQ VSUBS w_n211_n268# a_15_n48# a_n33_n145# a_n73_n48#
X0 a_15_n48# a_n33_n145# a_n73_n48# w_n211_n268# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_n73_n48# a_15_n48# 0.29fF
-C1 a_n33_n145# a_n73_n48# 0.01fF
-C2 a_n73_n48# w_n211_n268# 0.13fF
-C3 a_n33_n145# a_15_n48# 0.01fF
-C4 a_15_n48# w_n211_n268# 0.13fF
-C5 a_n33_n145# w_n211_n268# 0.06fF
+C0 w_n211_n268# a_15_n48# 0.13fF
+C1 w_n211_n268# a_n73_n48# 0.13fF
+C2 a_n33_n145# a_15_n48# 0.01fF
+C3 a_n33_n145# a_n73_n48# 0.01fF
+C4 w_n211_n268# a_n33_n145# 0.06fF
+C5 a_n73_n48# a_15_n48# 0.29fF
C6 a_15_n48# VSUBS 0.03fF
C7 a_n73_n48# VSUBS 0.03fF
C8 a_n33_n145# VSUBS 0.12fF
@@ -923,7 +923,7 @@
.subckt inverter_min vdd out in vss
XXM1 vss vss out in sky130_fd_pr__nfet_01v8_L78GGD
XXM2 vss vdd out in vdd sky130_fd_pr__pfet_01v8_6RX2PQ
-C0 vdd out 0.20fF
+C0 out vdd 0.20fF
C1 vdd in 0.13fF
C2 out in 0.67fF
C3 out vss 0.52fF
@@ -934,10 +934,10 @@
.subckt buffer_no_inv_x05 VSUBS in avdd1p8 inverter_min_1/in out
Xinverter_min_1 avdd1p8 out inverter_min_1/in VSUBS inverter_min
Xinverter_min_0 avdd1p8 inverter_min_1/in in VSUBS inverter_min
-C0 out inverter_min_1/in 0.12fF
-C1 inverter_min_1/in avdd1p8 0.09fF
-C2 out avdd1p8 0.02fF
-C3 in inverter_min_1/in 0.07fF
+C0 inverter_min_1/in avdd1p8 0.09fF
+C1 avdd1p8 out 0.02fF
+C2 in inverter_min_1/in 0.07fF
+C3 inverter_min_1/in out 0.12fF
C4 in VSUBS 0.63fF
C5 avdd1p8 VSUBS 4.78fF
C6 out VSUBS 0.45fF
@@ -948,17 +948,17 @@
+ w_n263_n330# a_n33_n111#
X0 a_n33_n111# a_n87_142# a_n125_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
X1 a_63_n111# a_21_142# a_n33_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
-C0 a_21_142# a_63_n111# 0.02fF
-C1 a_21_142# w_n263_n330# 0.05fF
-C2 w_n263_n330# a_n87_142# 0.05fF
-C3 a_n125_n111# a_n87_142# 0.02fF
-C4 a_63_n111# w_n263_n330# 0.14fF
-C5 a_n33_n111# a_63_n111# 0.32fF
-C6 a_63_n111# a_n125_n111# 0.12fF
-C7 a_n33_n111# w_n263_n330# 0.10fF
-C8 w_n263_n330# a_n125_n111# 0.14fF
-C9 a_n33_n111# a_n125_n111# 0.32fF
-C10 a_21_142# a_n87_142# 0.14fF
+C0 a_n125_n111# a_n87_142# 0.02fF
+C1 a_21_142# a_63_n111# 0.02fF
+C2 a_n125_n111# a_n33_n111# 0.32fF
+C3 w_n263_n330# a_21_142# 0.05fF
+C4 a_n125_n111# a_63_n111# 0.12fF
+C5 w_n263_n330# a_n87_142# 0.05fF
+C6 a_n33_n111# a_63_n111# 0.32fF
+C7 a_n125_n111# w_n263_n330# 0.14fF
+C8 a_21_142# a_n87_142# 0.14fF
+C9 a_n33_n111# w_n263_n330# 0.10fF
+C10 w_n263_n330# a_63_n111# 0.14fF
C11 a_63_n111# VSUBS 0.03fF
C12 a_n33_n111# VSUBS 0.03fF
C13 a_n125_n111# VSUBS 0.03fF
@@ -969,9 +969,9 @@
.subckt sky130_fd_pr__nfet_01v8_HAN8QX a_15_n142# a_n33_102# a_n73_n142# w_n211_n290#
X0 a_15_n142# a_n33_102# a_n73_n142# w_n211_n290# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
-C0 a_n73_n142# a_n33_102# 0.03fF
-C1 a_15_n142# a_n73_n142# 0.38fF
-C2 a_15_n142# a_n33_102# 0.03fF
+C0 a_n33_102# a_15_n142# 0.03fF
+C1 a_n33_102# a_n73_n142# 0.03fF
+C2 a_15_n142# a_n73_n142# 0.38fF
C3 a_15_n142# w_n211_n290# 0.19fF
C4 a_n73_n142# w_n211_n290# 0.19fF
C5 a_n33_102# w_n211_n290# 0.21fF
@@ -983,25 +983,25 @@
Xsky130_fd_pr__pfet_01v8_XA7ZMQ_1 avss1p8 sel_b DinB sel_b DinB avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
Xsky130_fd_pr__nfet_01v8_HAN8QX_0 out sel_b DinA avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
Xsky130_fd_pr__nfet_01v8_HAN8QX_1 out sel DinB avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
-C0 DinA DinB 0.07fF
-C1 sel_b DinA 0.56fF
-C2 out DinA 0.30fF
-C3 sel_b DinB 0.27fF
-C4 sel DinA 0.07fF
-C5 out DinB 0.37fF
-C6 out sel_b 0.58fF
-C7 sel DinB 0.02fF
-C8 sel_b sel 0.32fF
-C9 out sel 0.53fF
-C10 avdd1p8 DinA 0.26fF
-C11 avdd1p8 DinB 0.16fF
-C12 sel_b avdd1p8 0.74fF
-C13 out avdd1p8 0.23fF
-C14 avdd1p8 sel 0.72fF
+C0 DinB sel 0.02fF
+C1 out DinA 0.30fF
+C2 out avdd1p8 0.23fF
+C3 sel_b DinA 0.56fF
+C4 sel_b avdd1p8 0.74fF
+C5 out sel 0.53fF
+C6 sel_b sel 0.32fF
+C7 DinA avdd1p8 0.26fF
+C8 DinA sel 0.07fF
+C9 avdd1p8 sel 0.72fF
+C10 out DinB 0.37fF
+C11 sel_b DinB 0.27fF
+C12 DinA DinB 0.07fF
+C13 avdd1p8 DinB 0.16fF
+C14 out sel_b 0.58fF
C15 DinA avss1p8 0.63fF
-C16 sel_b avss1p8 2.16fF
-C17 out avss1p8 1.11fF
-C18 DinB avss1p8 -0.09fF
+C16 out avss1p8 1.11fF
+C17 DinB avss1p8 -0.09fF
+C18 sel_b avss1p8 2.16fF
C19 sel avss1p8 2.55fF
C20 avdd1p8 avss1p8 8.26fF
.ends
@@ -1058,246 +1058,246 @@
+ buffer_no_inv_x05_7/in buffer_no_inv_x05
Xbuffer_no_inv_x05_7 avss1p8 buffer_no_inv_x05_7/in avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in
+ mux_2to1_logic_3/DinA buffer_no_inv_x05
-C0 mux_2to1_logic_5/out nand_logic_0/in1 0.38fF
-C1 mux_2to1_logic_4/sel_b mux_2to1_logic_4/DinB 0.20fF
-C2 avdd1p8 buffer_no_inv_x05_9/inverter_min_1/in 0.03fF
-C3 reg2 mux_2to1_logic_4/DinB 0.05fF
-C4 buffer_no_inv_x05_8/inverter_min_1/in mux_2to1_logic_4/sel_b 0.01fF
-C5 avdd1p8 mux_2to1_logic_4/DinB 2.49fF
-C6 buffer_no_inv_x05_1/inverter_min_1/in mux_2to1_logic_0/DinB 0.08fF
-C7 mux_2to1_logic_0/out reg1 0.63fF
-C8 avdd1p8 mux_2to1_logic_6/sel_b 0.05fF
-C9 clk mux_2to1_logic_0/out 0.05fF
-C10 avdd1p8 buffer_no_inv_x05_8/inverter_min_1/in 0.03fF
-C11 reg2 mux_2to1_logic_1/DinA 0.18fF
-C12 mux_2to1_logic_4/DinA mux_2to1_logic_4/out 0.27fF
-C13 mux_2to1_logic_4/DinA mux_2to1_logic_3/DinA 0.07fF
-C14 mux_2to1_logic_0/out mux_2to1_logic_0/DinB 0.14fF
-C15 reg1 mux_2to1_logic_4/out 0.37fF
-C16 buffer_no_inv_x05_3/inverter_min_1/in mux_2to1_logic_1/DinA 0.23fF
-C17 reg0 mux_2to1_logic_4/DinB -0.24fF
-C18 clk mux_2to1_logic_4/DinA 0.01fF
-C19 clk mux_2to1_logic_3/DinA 0.01fF
-C20 mux_2to1_logic_5/sel_b mux_2to1_logic_4/out 0.20fF
-C21 avdd1p8 mux_2to1_logic_1/DinA 0.55fF
-C22 reg0 mux_2to1_logic_6/sel_b 0.06fF
-C23 mux_2to1_logic_0/out mux_2to1_logic_1/out 1.27fF
-C24 mux_2to1_logic_5/sel_b reg1 0.06fF
-C25 clk mux_2to1_logic_0/DinB 0.01fF
-C26 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinB 0.03fF
-C27 buffer_no_inv_x05_7/inverter_min_1/in buffer_no_inv_x05_7/in 0.12fF
-C28 reg1 mux_2to1_logic_1/out 0.36fF
-C29 avdd1p8 buffer_no_inv_x05_6/inverter_min_1/in 0.03fF
-C30 mux_2to1_logic_0/out mux_2to1_logic_1/sel_b 0.26fF
-C31 avdd1p8 buffer_no_inv_x05_2/inverter_min_1/in 0.03fF
-C32 mux_2to1_logic_3/DinB buffer_no_inv_x05_9/inverter_min_1/in 0.18fF
-C33 avdd1p8 buffer_no_inv_x05_11/inverter_min_1/in 0.03fF
-C34 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b 0.22fF
-C35 mux_2to1_logic_3/out mux_2to1_logic_4/sel_b 0.23fF
-C36 reg2 mux_2to1_logic_2/out 0.85fF
-C37 reg2 mux_2to1_logic_3/out 0.36fF
-C38 mux_2to1_logic_1/DinB buffer_no_inv_x05_5/inverter_min_1/in 0.23fF
-C39 mux_2to1_logic_3/DinB mux_2to1_logic_4/DinB 0.29fF
-C40 mux_2to1_logic_1/sel_b mux_2to1_logic_0/DinB 0.04fF
-C41 reg2 mux_2to1_logic_0/sel_b 0.14fF
-C42 reg0 buffer_no_inv_x05_11/inverter_min_1/in 0.01fF
-C43 mux_2to1_logic_5/out mux_2to1_logic_4/out 0.45fF
-C44 avdd1p8 mux_2to1_logic_2/out 0.41fF
-C45 avdd1p8 mux_2to1_logic_3/out 0.39fF
-C46 mux_2to1_logic_5/out mux_2to1_logic_4/DinA 0.23fF
-C47 mux_2to1_logic_3/DinB buffer_no_inv_x05_8/inverter_min_1/in 0.10fF
-C48 mux_2to1_logic_3/sel_b mux_2to1_logic_1/out 0.04fF
-C49 avdd1p8 mux_2to1_logic_0/sel_b 0.05fF
-C50 buffer_no_inv_x05_13/inverter_min_1/in mux_2to1_logic_4/DinB 0.11fF
-C51 mux_2to1_logic_1/DinB buffer_no_inv_x05_4/inverter_min_1/in 0.15fF
-C52 mux_2to1_logic_2/out reg0 0.44fF
-C53 buffer_no_inv_x05_9/in buffer_no_inv_x05_9/inverter_min_1/in 0.12fF
-C54 buffer_no_inv_x05_3/inverter_min_1/in buffer_no_inv_x05_3/in 0.12fF
-C55 avdd1p8 buffer_no_inv_x05_3/in 0.11fF
-C56 mux_2to1_logic_3/DinB buffer_no_inv_x05_6/inverter_min_1/in 0.02fF
-C57 avdd1p8 buffer_no_inv_x05_7/in 0.09fF
-C58 buffer_no_inv_x05_9/in buffer_no_inv_x05_8/inverter_min_1/in 0.07fF
-C59 mux_2to1_logic_2/out nand_logic_0/in1 0.06fF
-C60 buffer_no_inv_x05_5/inverter_min_1/in buffer_no_inv_x05_5/in 0.12fF
-C61 avdd1p8 buffer_no_inv_x05_5/inverter_min_1/in 0.03fF
-C62 mux_2to1_logic_3/out mux_2to1_logic_3/DinB 0.13fF
-C63 buffer_no_inv_x05_13/in buffer_no_inv_x05_12/inverter_min_1/in 0.07fF
-C64 avdd1p8 buffer_no_inv_x05_11/in 0.10fF
-C65 mux_2to1_logic_4/out mux_2to1_logic_4/DinB 0.65fF
-C66 mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB 1.68fF
-C67 reg1 mux_2to1_logic_4/DinB 0.40fF
-C68 buffer_no_inv_x05_5/in buffer_no_inv_x05_4/inverter_min_1/in 0.07fF
-C69 avdd1p8 buffer_no_inv_x05_4/inverter_min_1/in 0.03fF
-C70 mux_2to1_logic_4/out mux_2to1_logic_6/sel_b 0.04fF
-C71 mux_2to1_logic_4/DinA mux_2to1_logic_6/sel_b 0.01fF
-C72 clk mux_2to1_logic_4/DinB 0.12fF
-C73 buffer_no_inv_x05_8/inverter_min_1/in mux_2to1_logic_3/DinA 0.12fF
-C74 mux_2to1_logic_0/out mux_2to1_logic_1/DinA 0.12fF
-C75 mux_2to1_logic_5/sel_b mux_2to1_logic_4/DinB 0.31fF
-C76 mux_2to1_logic_3/DinB buffer_no_inv_x05_7/in 0.10fF
-C77 clk mux_2to1_logic_1/DinA 0.01fF
-C78 mux_2to1_logic_1/DinA mux_2to1_logic_0/DinB 0.11fF
-C79 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_3/DinA 0.04fF
-C80 reg2 mux_2to1_logic_1/DinB 0.07fF
-C81 mux_2to1_logic_1/out mux_2to1_logic_1/DinA 0.05fF
-C82 buffer_no_inv_x05_3/inverter_min_1/in mux_2to1_logic_1/DinB 0.15fF
-C83 avdd1p8 buffer_no_inv_x05_0/inverter_min_1/in 0.01fF
-C84 avdd1p8 mux_2to1_logic_1/DinB 1.09fF
-C85 mux_2to1_logic_1/DinB buffer_no_inv_x05_5/in 0.15fF
-C86 mux_2to1_logic_4/DinA buffer_no_inv_x05_11/inverter_min_1/in 0.08fF
-C87 avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in 0.04fF
-C88 avdd1p8 buffer_no_inv_x05_13/in 0.10fF
-C89 mux_2to1_logic_0/sel_b buffer_no_inv_x05_1/inverter_min_1/in 0.01fF
-C90 avdd1p8 buffer_no_inv_x05_12/inverter_min_1/in 0.03fF
-C91 mux_2to1_logic_0/out mux_2to1_logic_2/out 0.05fF
-C92 mux_2to1_logic_5/out mux_2to1_logic_4/DinB 0.52fF
-C93 buffer_no_inv_x05_2/inverter_min_1/in mux_2to1_logic_0/DinB 0.12fF
-C94 mux_2to1_logic_5/out mux_2to1_logic_6/sel_b 0.20fF
-C95 mux_2to1_logic_2/out mux_2to1_logic_4/out 0.26fF
-C96 mux_2to1_logic_3/out mux_2to1_logic_4/out 1.18fF
-C97 mux_2to1_logic_3/out mux_2to1_logic_3/DinA 0.05fF
-C98 mux_2to1_logic_3/out mux_2to1_logic_4/DinA 0.12fF
-C99 reg1 mux_2to1_logic_2/out 1.41fF
-C100 mux_2to1_logic_3/out reg1 0.47fF
-C101 mux_2to1_logic_5/sel_b mux_2to1_logic_2/out 0.20fF
-C102 mux_2to1_logic_5/sel_b mux_2to1_logic_3/out 0.37fF
-C103 mux_2to1_logic_3/sel_b buffer_no_inv_x05_6/inverter_min_1/in 0.01fF
-C104 mux_2to1_logic_0/sel_b mux_2to1_logic_0/DinB 0.06fF
-C105 mux_2to1_logic_2/out mux_2to1_logic_1/out 0.35fF
-C106 mux_2to1_logic_2/sel_b mux_2to1_logic_1/DinB 0.04fF
-C107 reg2 mux_2to1_logic_4/sel_b 0.06fF
-C108 mux_2to1_logic_3/DinA buffer_no_inv_x05_7/in 0.13fF
-C109 avdd1p8 mux_2to1_logic_4/sel_b 0.07fF
-C110 reg2 avdd1p8 0.14fF
-C111 mux_2to1_logic_3/sel_b mux_2to1_logic_2/out 0.33fF
-C112 clk_out nand_logic_0/m1_21_n341# 0.02fF
-C113 buffer_no_inv_x05_3/inverter_min_1/in avdd1p8 0.03fF
-C114 buffer_no_inv_x05_7/inverter_min_1/in mux_2to1_logic_3/DinB 0.10fF
-C115 avdd1p8 buffer_no_inv_x05_5/in 0.09fF
-C116 mux_2to1_logic_5/out mux_2to1_logic_2/out 1.29fF
-C117 mux_2to1_logic_5/out mux_2to1_logic_3/out 0.07fF
-C118 buffer_no_inv_x05_13/in buffer_no_inv_x05_13/inverter_min_1/in 0.12fF
-C119 avdd1p8 reg0 0.05fF
-C120 buffer_no_inv_x05_3/in mux_2to1_logic_1/sel_b 0.01fF
-C121 mux_2to1_logic_6/sel_b mux_2to1_logic_4/DinB 0.28fF
-C122 reg2 mux_2to1_logic_2/sel_b 0.07fF
-C123 reg1 buffer_no_inv_x05_4/inverter_min_1/in 0.01fF
-C124 mux_2to1_logic_2/sel_b buffer_no_inv_x05_5/in 0.01fF
-C125 avdd1p8 mux_2to1_logic_2/sel_b 0.07fF
-C126 buffer_no_inv_x05_10/inverter_min_1/in buffer_no_inv_x05_11/in 0.07fF
-C127 mux_2to1_logic_3/DinB mux_2to1_logic_4/sel_b 0.04fF
-C128 avdd1p8 clk_out 0.04fF
-C129 reg2 mux_2to1_logic_3/DinB 0.08fF
-C130 buffer_no_inv_x05_1/in buffer_no_inv_x05_0/inverter_min_1/in 0.07fF
-C131 avdd1p8 mux_2to1_logic_3/DinB 0.82fF
-C132 mux_2to1_logic_0/out mux_2to1_logic_1/DinB 0.12fF
-C133 mux_2to1_logic_1/DinB mux_2to1_logic_3/DinA 0.07fF
-C134 avdd1p8 buffer_no_inv_x05_13/inverter_min_1/in 0.03fF
-C135 buffer_no_inv_x05_7/inverter_min_1/in mux_2to1_logic_3/DinA 0.21fF
-C136 mux_2to1_logic_4/DinA buffer_no_inv_x05_12/inverter_min_1/in 0.12fF
-C137 clk mux_2to1_logic_1/DinB 0.01fF
-C138 mux_2to1_logic_2/out mux_2to1_logic_4/DinB 0.07fF
-C139 mux_2to1_logic_3/out mux_2to1_logic_4/DinB 0.18fF
-C140 mux_2to1_logic_1/DinA buffer_no_inv_x05_2/inverter_min_1/in 0.10fF
-C141 clk buffer_no_inv_x05_13/in 0.07fF
-C142 mux_2to1_logic_2/out mux_2to1_logic_6/sel_b 0.31fF
-C143 avdd1p8 buffer_no_inv_x05_9/in 0.10fF
-C144 mux_2to1_logic_1/DinB mux_2to1_logic_1/out 0.23fF
-C145 reg2 buffer_no_inv_x05_1/in 0.01fF
-C146 mux_2to1_logic_1/DinB mux_2to1_logic_1/sel_b -0.06fF
-C147 mux_2to1_logic_0/out reg2 0.45fF
-C148 avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in 0.03fF
-C149 avdd1p8 buffer_no_inv_x05_1/in 0.09fF
-C150 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinA 0.16fF
-C151 reg2 mux_2to1_logic_3/DinA 0.33fF
-C152 reg2 mux_2to1_logic_4/DinA 0.31fF
-C153 mux_2to1_logic_0/out avdd1p8 0.43fF
-C154 reg2 reg1 2.15fF
-C155 clk reg2 0.12fF
-C156 avdd1p8 mux_2to1_logic_4/out 0.76fF
-C157 reg2 mux_2to1_logic_0/DinB 0.06fF
+C0 reg0 mux_2to1_logic_6/sel_b 0.06fF
+C1 mux_2to1_logic_4/out mux_2to1_logic_5/out 0.45fF
+C2 mux_2to1_logic_2/sel_b mux_2to1_logic_0/out 0.15fF
+C3 mux_2to1_logic_6/sel_b mux_2to1_logic_4/DinA 0.01fF
+C4 avdd1p8 reg1 0.08fF
+C5 mux_2to1_logic_0/DinB mux_2to1_logic_0/sel_b 0.06fF
+C6 reg2 mux_2to1_logic_3/DinA 0.33fF
+C7 reg2 mux_2to1_logic_1/DinA 0.18fF
+C8 buffer_no_inv_x05_13/in clk 0.07fF
+C9 mux_2to1_logic_2/out reg0 0.44fF
+C10 mux_2to1_logic_4/DinB mux_2to1_logic_3/out 0.18fF
+C11 mux_2to1_logic_4/DinB buffer_no_inv_x05_13/inverter_min_1/in 0.11fF
+C12 buffer_no_inv_x05_9/in buffer_no_inv_x05_8/inverter_min_1/in 0.07fF
+C13 buffer_no_inv_x05_7/in buffer_no_inv_x05_7/inverter_min_1/in 0.12fF
+C14 mux_2to1_logic_4/out avdd1p8 0.76fF
+C15 mux_2to1_logic_1/DinA mux_2to1_logic_1/out 0.05fF
+C16 mux_2to1_logic_4/sel_b mux_2to1_logic_3/DinB 0.04fF
+C17 mux_2to1_logic_3/out mux_2to1_logic_3/DinA 0.05fF
+C18 mux_2to1_logic_4/DinB reg1 0.40fF
+C19 mux_2to1_logic_1/DinB mux_2to1_logic_0/out 0.12fF
+C20 buffer_no_inv_x05_11/in buffer_no_inv_x05_10/inverter_min_1/in 0.07fF
+C21 avdd1p8 mux_2to1_logic_4/sel_b 0.07fF
+C22 mux_2to1_logic_6/sel_b mux_2to1_logic_5/out 0.20fF
+C23 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinA 0.16fF
+C24 avdd1p8 buffer_no_inv_x05_12/inverter_min_1/in 0.03fF
+C25 avdd1p8 buffer_no_inv_x05_11/inverter_min_1/in 0.03fF
+C26 reg2 mux_2to1_logic_3/out 0.36fF
+C27 mux_2to1_logic_2/out nand_logic_0/in1 0.06fF
+C28 reg2 mux_2to1_logic_0/sel_b 0.14fF
+C29 mux_2to1_logic_2/sel_b buffer_no_inv_x05_5/in 0.01fF
+C30 mux_2to1_logic_4/DinA clk 0.01fF
+C31 mux_2to1_logic_3/sel_b mux_2to1_logic_3/DinB 0.21fF
+C32 avdd1p8 mux_2to1_logic_0/out 0.43fF
+C33 mux_2to1_logic_2/out mux_2to1_logic_5/out 1.29fF
+C34 buffer_no_inv_x05_5/in buffer_no_inv_x05_4/inverter_min_1/in 0.07fF
+C35 reg2 reg1 2.15fF
+C36 mux_2to1_logic_4/out mux_2to1_logic_4/DinB 0.65fF
+C37 mux_2to1_logic_3/sel_b avdd1p8 0.09fF
+C38 mux_2to1_logic_3/DinB buffer_no_inv_x05_7/inverter_min_1/in 0.10fF
+C39 avdd1p8 mux_2to1_logic_6/sel_b 0.05fF
+C40 mux_2to1_logic_4/DinB mux_2to1_logic_4/sel_b 0.20fF
+C41 mux_2to1_logic_3/DinB mux_2to1_logic_5/sel_b 0.01fF
+C42 mux_2to1_logic_4/DinB buffer_no_inv_x05_12/inverter_min_1/in 0.07fF
+C43 mux_2to1_logic_0/DinB mux_2to1_logic_0/out 0.14fF
+C44 avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in 0.04fF
+C45 mux_2to1_logic_1/out reg1 0.36fF
+C46 avdd1p8 mux_2to1_logic_5/sel_b 0.09fF
+C47 avdd1p8 buffer_no_inv_x05_13/in 0.10fF
+C48 buffer_no_inv_x05_9/in mux_2to1_logic_3/DinB 0.10fF
+C49 mux_2to1_logic_3/out reg1 0.47fF
+C50 mux_2to1_logic_2/out avdd1p8 0.41fF
+C51 reg0 mux_2to1_logic_5/out 0.23fF
+C52 buffer_no_inv_x05_5/in mux_2to1_logic_1/DinB 0.15fF
+C53 mux_2to1_logic_1/DinB mux_2to1_logic_1/sel_b -0.06fF
+C54 avdd1p8 buffer_no_inv_x05_9/in 0.10fF
+C55 mux_2to1_logic_4/DinA mux_2to1_logic_5/out 0.23fF
+C56 mux_2to1_logic_3/sel_b buffer_no_inv_x05_6/inverter_min_1/in 0.01fF
+C57 reg2 mux_2to1_logic_4/sel_b 0.06fF
+C58 mux_2to1_logic_4/DinB mux_2to1_logic_6/sel_b 0.28fF
+C59 mux_2to1_logic_1/DinB clk 0.01fF
+C60 clk_out clk 0.33fF
+C61 buffer_no_inv_x05_1/inverter_min_1/in buffer_no_inv_x05_1/in 0.12fF
+C62 mux_2to1_logic_3/DinB buffer_no_inv_x05_8/inverter_min_1/in 0.10fF
+C63 buffer_no_inv_x05_11/in avdd1p8 0.10fF
+C64 mux_2to1_logic_1/sel_b avdd1p8 0.09fF
+C65 buffer_no_inv_x05_5/in avdd1p8 0.09fF
+C66 mux_2to1_logic_1/DinA mux_2to1_logic_0/out 0.12fF
+C67 buffer_no_inv_x05_10/inverter_min_1/in mux_2to1_logic_3/DinB 0.12fF
+C68 avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in 0.03fF
+C69 mux_2to1_logic_4/out mux_2to1_logic_3/out 1.18fF
+C70 mux_2to1_logic_3/DinB clk 0.01fF
+C71 mux_2to1_logic_4/DinA mux_2to1_logic_3/DinB 0.90fF
+C72 mux_2to1_logic_2/sel_b mux_2to1_logic_1/DinB 0.04fF
+C73 mux_2to1_logic_4/DinB buffer_no_inv_x05_13/in 0.11fF
+C74 mux_2to1_logic_4/DinB mux_2to1_logic_5/sel_b 0.31fF
+C75 reg2 mux_2to1_logic_0/out 0.45fF
+C76 nand_logic_0/in1 mux_2to1_logic_5/out 0.38fF
+C77 avdd1p8 buffer_no_inv_x05_8/inverter_min_1/in 0.03fF
+C78 mux_2to1_logic_1/DinB buffer_no_inv_x05_4/inverter_min_1/in 0.15fF
+C79 reg0 avdd1p8 0.05fF
+C80 avdd1p8 buffer_no_inv_x05_10/inverter_min_1/in 0.03fF
+C81 mux_2to1_logic_2/out mux_2to1_logic_4/DinB 0.07fF
+C82 avdd1p8 mux_2to1_logic_4/DinA 1.95fF
+C83 mux_2to1_logic_4/sel_b mux_2to1_logic_3/out 0.23fF
+C84 avdd1p8 clk 1.01fF
+C85 mux_2to1_logic_3/sel_b reg2 0.13fF
+C86 buffer_no_inv_x05_7/inverter_min_1/in mux_2to1_logic_3/DinA 0.21fF
+C87 buffer_no_inv_x05_7/in mux_2to1_logic_3/DinB 0.10fF
+C88 mux_2to1_logic_0/DinB mux_2to1_logic_1/sel_b 0.04fF
+C89 mux_2to1_logic_0/DinB buffer_no_inv_x05_1/inverter_min_1/in 0.08fF
+C90 mux_2to1_logic_4/out reg1 0.37fF
+C91 buffer_no_inv_x05_0/inverter_min_1/in buffer_no_inv_x05_1/in 0.07fF
+C92 mux_2to1_logic_1/out mux_2to1_logic_0/out 1.27fF
+C93 mux_2to1_logic_2/sel_b avdd1p8 0.07fF
+C94 avdd1p8 buffer_no_inv_x05_7/in 0.09fF
+C95 buffer_no_inv_x05_0/inverter_min_1/in avdd1p8 0.01fF
+C96 avdd1p8 buffer_no_inv_x05_4/inverter_min_1/in 0.03fF
+C97 mux_2to1_logic_0/DinB clk 0.01fF
+C98 mux_2to1_logic_3/sel_b mux_2to1_logic_1/out 0.04fF
+C99 mux_2to1_logic_1/DinB buffer_no_inv_x05_3/inverter_min_1/in 0.15fF
+C100 buffer_no_inv_x05_5/in buffer_no_inv_x05_5/inverter_min_1/in 0.12fF
+C101 mux_2to1_logic_2/out reg2 0.85fF
+C102 reg0 mux_2to1_logic_4/DinB -0.24fF
+C103 mux_2to1_logic_4/DinB mux_2to1_logic_4/DinA 1.68fF
+C104 mux_2to1_logic_4/DinB clk 0.12fF
+C105 avdd1p8 buffer_no_inv_x05_2/inverter_min_1/in 0.03fF
+C106 buffer_no_inv_x05_9/inverter_min_1/in buffer_no_inv_x05_9/in 0.12fF
+C107 avdd1p8 mux_2to1_logic_5/out 0.64fF
+C108 reg1 mux_2to1_logic_0/out 0.63fF
+C109 mux_2to1_logic_2/out mux_2to1_logic_1/out 0.35fF
+C110 avdd1p8 buffer_no_inv_x05_3/inverter_min_1/in 0.03fF
+C111 buffer_no_inv_x05_7/in buffer_no_inv_x05_6/inverter_min_1/in 0.07fF
+C112 buffer_no_inv_x05_8/inverter_min_1/in mux_2to1_logic_3/DinA 0.12fF
+C113 mux_2to1_logic_3/out mux_2to1_logic_5/sel_b 0.37fF
+C114 buffer_no_inv_x05_13/inverter_min_1/in buffer_no_inv_x05_13/in 0.12fF
+C115 reg2 mux_2to1_logic_1/sel_b 0.13fF
+C116 mux_2to1_logic_1/DinB avdd1p8 1.09fF
+C117 clk mux_2to1_logic_3/DinA 0.01fF
+C118 mux_2to1_logic_4/DinA mux_2to1_logic_3/DinA 0.07fF
+C119 mux_2to1_logic_2/out mux_2to1_logic_3/out 0.99fF
+C120 avdd1p8 clk_out 0.04fF
+C121 mux_2to1_logic_0/DinB buffer_no_inv_x05_2/inverter_min_1/in 0.12fF
+C122 mux_2to1_logic_1/DinA clk 0.01fF
+C123 reg2 clk 0.12fF
+C124 reg2 mux_2to1_logic_4/DinA 0.31fF
+C125 avdd1p8 mux_2to1_logic_3/DinB 0.82fF
+C126 buffer_no_inv_x05_7/in mux_2to1_logic_3/DinA 0.13fF
+C127 avdd1p8 buffer_no_inv_x05_1/in 0.09fF
+C128 mux_2to1_logic_5/sel_b reg1 0.06fF
+C129 mux_2to1_logic_2/out reg1 1.41fF
+C130 mux_2to1_logic_1/DinA buffer_no_inv_x05_4/inverter_min_1/in 0.12fF
+C131 mux_2to1_logic_4/DinB mux_2to1_logic_5/out 0.52fF
+C132 mux_2to1_logic_2/sel_b reg2 0.07fF
+C133 buffer_no_inv_x05_3/in mux_2to1_logic_1/sel_b 0.01fF
+C134 mux_2to1_logic_4/out mux_2to1_logic_6/sel_b 0.04fF
+C135 mux_2to1_logic_1/DinB buffer_no_inv_x05_6/inverter_min_1/in 0.12fF
+C136 buffer_no_inv_x05_1/inverter_min_1/in mux_2to1_logic_0/sel_b 0.01fF
+C137 mux_2to1_logic_1/DinB buffer_no_inv_x05_5/inverter_min_1/in 0.23fF
+C138 mux_2to1_logic_0/DinB avdd1p8 1.33fF
+C139 mux_2to1_logic_4/DinA mux_2to1_logic_3/out 0.12fF
+C140 mux_2to1_logic_3/DinB buffer_no_inv_x05_6/inverter_min_1/in 0.02fF
+C141 mux_2to1_logic_4/out mux_2to1_logic_5/sel_b 0.20fF
+C142 mux_2to1_logic_2/sel_b mux_2to1_logic_1/out 0.19fF
+C143 mux_2to1_logic_1/DinA buffer_no_inv_x05_2/inverter_min_1/in 0.10fF
+C144 mux_2to1_logic_4/DinB mux_2to1_logic_3/DinB 0.29fF
+C145 mux_2to1_logic_4/out mux_2to1_logic_2/out 0.26fF
+C146 mux_2to1_logic_1/DinA buffer_no_inv_x05_3/inverter_min_1/in 0.23fF
+C147 mux_2to1_logic_1/DinB mux_2to1_logic_3/DinA 0.07fF
+C148 avdd1p8 buffer_no_inv_x05_6/inverter_min_1/in 0.03fF
+C149 reg0 reg1 0.01fF
+C150 mux_2to1_logic_1/DinB mux_2to1_logic_1/DinA 0.66fF
+C151 mux_2to1_logic_4/DinB avdd1p8 2.49fF
+C152 buffer_no_inv_x05_13/in buffer_no_inv_x05_12/inverter_min_1/in 0.07fF
+C153 avdd1p8 buffer_no_inv_x05_5/inverter_min_1/in 0.03fF
+C154 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b 0.22fF
+C155 reg2 mux_2to1_logic_1/DinB 0.07fF
+C156 mux_2to1_logic_3/DinB mux_2to1_logic_3/DinA 1.18fF
+C157 mux_2to1_logic_2/sel_b reg1 0.06fF
C158 avdd1p8 mux_2to1_logic_3/DinA 0.81fF
-C159 avdd1p8 mux_2to1_logic_4/DinA 1.95fF
-C160 avdd1p8 reg1 0.08fF
-C161 mux_2to1_logic_3/out mux_2to1_logic_2/out 0.99fF
-C162 buffer_no_inv_x05_6/inverter_min_1/in buffer_no_inv_x05_7/in 0.07fF
-C163 clk avdd1p8 1.01fF
-C164 mux_2to1_logic_5/sel_b avdd1p8 0.09fF
-C165 buffer_no_inv_x05_9/in mux_2to1_logic_3/DinB 0.10fF
-C166 avdd1p8 mux_2to1_logic_0/DinB 1.33fF
-C167 reg1 reg0 0.01fF
-C168 buffer_no_inv_x05_3/in buffer_no_inv_x05_2/inverter_min_1/in 0.07fF
-C169 avdd1p8 buffer_no_inv_x05_10/inverter_min_1/in 0.03fF
-C170 avdd1p8 mux_2to1_logic_1/out 0.84fF
-C171 mux_2to1_logic_0/out mux_2to1_logic_2/sel_b 0.15fF
-C172 reg2 mux_2to1_logic_1/sel_b 0.13fF
-C173 reg2 mux_2to1_logic_3/sel_b 0.13fF
-C174 mux_2to1_logic_1/DinA buffer_no_inv_x05_4/inverter_min_1/in 0.12fF
-C175 avdd1p8 mux_2to1_logic_1/sel_b 0.09fF
-C176 avdd1p8 mux_2to1_logic_3/sel_b 0.09fF
-C177 mux_2to1_logic_2/sel_b reg1 0.06fF
-C178 clk clk_out 0.33fF
-C179 mux_2to1_logic_5/out avdd1p8 0.64fF
-C180 mux_2to1_logic_3/DinB mux_2to1_logic_3/DinA 1.18fF
-C181 mux_2to1_logic_2/sel_b mux_2to1_logic_1/out 0.19fF
-C182 mux_2to1_logic_4/DinA mux_2to1_logic_3/DinB 0.90fF
-C183 buffer_no_inv_x05_11/inverter_min_1/in buffer_no_inv_x05_11/in 0.14fF
-C184 buffer_no_inv_x05_13/in mux_2to1_logic_4/DinB 0.11fF
-C185 clk mux_2to1_logic_3/DinB 0.01fF
-C186 buffer_no_inv_x05_12/inverter_min_1/in mux_2to1_logic_4/DinB 0.07fF
-C187 mux_2to1_logic_5/sel_b mux_2to1_logic_3/DinB 0.01fF
-C188 mux_2to1_logic_5/out reg0 0.23fF
-C189 mux_2to1_logic_3/DinB buffer_no_inv_x05_10/inverter_min_1/in 0.12fF
-C190 mux_2to1_logic_1/DinB mux_2to1_logic_1/DinA 0.66fF
-C191 mux_2to1_logic_1/DinB buffer_no_inv_x05_6/inverter_min_1/in 0.12fF
-C192 mux_2to1_logic_3/sel_b mux_2to1_logic_3/DinB 0.21fF
-C193 buffer_no_inv_x05_1/inverter_min_1/in buffer_no_inv_x05_1/in 0.12fF
+C159 reg2 mux_2to1_logic_3/DinB 0.08fF
+C160 buffer_no_inv_x05_4/inverter_min_1/in reg1 0.01fF
+C161 reg2 buffer_no_inv_x05_1/in 0.01fF
+C162 avdd1p8 mux_2to1_logic_1/DinA 0.55fF
+C163 mux_2to1_logic_3/out mux_2to1_logic_5/out 0.07fF
+C164 mux_2to1_logic_2/out mux_2to1_logic_0/out 0.05fF
+C165 buffer_no_inv_x05_3/in buffer_no_inv_x05_2/inverter_min_1/in 0.07fF
+C166 mux_2to1_logic_1/DinB mux_2to1_logic_1/out 0.23fF
+C167 reg2 avdd1p8 0.14fF
+C168 buffer_no_inv_x05_9/inverter_min_1/in mux_2to1_logic_3/DinB 0.18fF
+C169 buffer_no_inv_x05_11/in buffer_no_inv_x05_11/inverter_min_1/in 0.14fF
+C170 buffer_no_inv_x05_3/in buffer_no_inv_x05_3/inverter_min_1/in 0.12fF
+C171 mux_2to1_logic_4/out mux_2to1_logic_4/DinA 0.27fF
+C172 mux_2to1_logic_3/sel_b mux_2to1_logic_2/out 0.33fF
+C173 mux_2to1_logic_4/sel_b buffer_no_inv_x05_8/inverter_min_1/in 0.01fF
+C174 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinB 0.03fF
+C175 buffer_no_inv_x05_9/inverter_min_1/in avdd1p8 0.03fF
+C176 mux_2to1_logic_2/out mux_2to1_logic_6/sel_b 0.31fF
+C177 mux_2to1_logic_0/DinB mux_2to1_logic_1/DinA 0.11fF
+C178 reg0 buffer_no_inv_x05_11/inverter_min_1/in 0.01fF
+C179 reg2 mux_2to1_logic_0/DinB 0.06fF
+C180 mux_2to1_logic_4/DinA buffer_no_inv_x05_12/inverter_min_1/in 0.12fF
+C181 mux_2to1_logic_4/DinA buffer_no_inv_x05_11/inverter_min_1/in 0.08fF
+C182 mux_2to1_logic_3/DinB mux_2to1_logic_3/out 0.13fF
+C183 avdd1p8 mux_2to1_logic_1/out 0.84fF
+C184 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_3/DinA 0.04fF
+C185 nand_logic_0/m1_21_n341# clk_out 0.02fF
+C186 mux_2to1_logic_1/sel_b mux_2to1_logic_0/out 0.26fF
+C187 mux_2to1_logic_2/out mux_2to1_logic_5/sel_b 0.20fF
+C188 avdd1p8 mux_2to1_logic_3/out 0.39fF
+C189 buffer_no_inv_x05_13/inverter_min_1/in avdd1p8 0.03fF
+C190 buffer_no_inv_x05_3/in avdd1p8 0.11fF
+C191 avdd1p8 mux_2to1_logic_0/sel_b 0.05fF
+C192 clk mux_2to1_logic_0/out 0.05fF
+C193 reg2 mux_2to1_logic_4/DinB 0.05fF
C194 buffer_no_inv_x05_7/in avss1p8 1.12fF
-C195 buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.05fF
-C196 buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.04fF
-C197 buffer_no_inv_x05_5/in avss1p8 1.12fF
-C198 buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.04fF
-C199 buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.04fF
-C200 buffer_no_inv_x05_3/in avss1p8 1.13fF
-C201 buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.04fF
-C202 buffer_no_inv_x05_1/in avss1p8 1.12fF
-C203 buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.04fF
-C204 buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.05fF
-C205 clk avss1p8 2.54fF
-C206 buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
-C207 buffer_no_inv_x05_13/in avss1p8 1.12fF
-C208 mux_2to1_logic_4/DinB avss1p8 -7.83fF
-C209 buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.04fF
-C210 buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.04fF
-C211 buffer_no_inv_x05_11/in avss1p8 1.12fF
-C212 buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.04fF
-C213 nand_logic_0/m1_21_n341# avss1p8 0.72fF
-C214 clk_out avss1p8 0.27fF
-C215 buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.04fF
-C216 mux_2to1_logic_6/sel_b avss1p8 2.08fF
+C195 mux_2to1_logic_3/DinA avss1p8 0.02fF
+C196 buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.05fF
+C197 buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.04fF
+C198 buffer_no_inv_x05_5/in avss1p8 1.12fF
+C199 buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.04fF
+C200 buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.04fF
+C201 buffer_no_inv_x05_3/in avss1p8 1.13fF
+C202 buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.04fF
+C203 buffer_no_inv_x05_1/in avss1p8 1.12fF
+C204 buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.04fF
+C205 buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.05fF
+C206 clk avss1p8 2.54fF
+C207 buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C208 buffer_no_inv_x05_13/in avss1p8 1.12fF
+C209 mux_2to1_logic_4/DinB avss1p8 -7.83fF
+C210 buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.04fF
+C211 buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.04fF
+C212 buffer_no_inv_x05_11/in avss1p8 1.12fF
+C213 buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.04fF
+C214 nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C215 clk_out avss1p8 0.27fF
+C216 buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.04fF
C217 nand_logic_0/in1 avss1p8 1.63fF
-C218 reg0 avss1p8 3.16fF
-C219 mux_2to1_logic_5/sel_b avss1p8 2.05fF
+C218 mux_2to1_logic_6/sel_b avss1p8 2.08fF
+C219 reg0 avss1p8 3.16fF
C220 mux_2to1_logic_5/out avss1p8 -1.59fF
-C221 mux_2to1_logic_4/DinA avss1p8 -2.53fF
-C222 mux_2to1_logic_4/sel_b avss1p8 2.05fF
+C221 mux_2to1_logic_5/sel_b avss1p8 2.05fF
+C222 mux_2to1_logic_4/DinA avss1p8 -2.53fF
C223 mux_2to1_logic_4/out avss1p8 -2.14fF
-C224 mux_2to1_logic_3/DinA avss1p8 0.02fF
-C225 mux_2to1_logic_3/sel_b avss1p8 2.05fF
-C226 mux_2to1_logic_3/out avss1p8 -2.13fF
-C227 mux_2to1_logic_3/DinB avss1p8 -4.89fF
-C228 mux_2to1_logic_2/sel_b avss1p8 2.05fF
-C229 mux_2to1_logic_2/out avss1p8 -1.34fF
+C224 mux_2to1_logic_4/sel_b avss1p8 2.05fF
+C225 mux_2to1_logic_3/out avss1p8 -2.13fF
+C226 mux_2to1_logic_3/DinB avss1p8 -4.89fF
+C227 mux_2to1_logic_3/sel_b avss1p8 2.05fF
+C228 mux_2to1_logic_2/out avss1p8 -1.34fF
+C229 mux_2to1_logic_2/sel_b avss1p8 2.05fF
C230 reg1 avss1p8 4.95fF
C231 mux_2to1_logic_1/DinA avss1p8 0.68fF
-C232 mux_2to1_logic_1/sel_b avss1p8 2.05fF
-C233 mux_2to1_logic_1/out avss1p8 -2.38fF
-C234 mux_2to1_logic_1/DinB avss1p8 -3.84fF
+C232 mux_2to1_logic_1/out avss1p8 -2.38fF
+C233 mux_2to1_logic_1/DinB avss1p8 -3.84fF
+C234 mux_2to1_logic_1/sel_b avss1p8 2.05fF
C235 reg2 avss1p8 13.29fF
C236 avdd1p8 avss1p8 125.49fF
-C237 mux_2to1_logic_0/sel_b avss1p8 2.04fF
-C238 mux_2to1_logic_0/out avss1p8 0.32fF
-C239 mux_2to1_logic_0/DinB avss1p8 -0.89fF
+C237 mux_2to1_logic_0/out avss1p8 0.32fF
+C238 mux_2to1_logic_0/DinB avss1p8 -0.89fF
+C239 mux_2to1_logic_0/sel_b avss1p8 2.04fF
C240 buffer_no_inv_x05_9/in avss1p8 1.12fF
C241 buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.04fF
C242 buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.04fF
@@ -1308,14 +1308,14 @@
X0 a_15_n100# a_n128_122# a_n81_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X1 a_n81_n100# a_n128_122# a_n173_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X2 a_111_n100# a_n128_122# a_15_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n81_n100# a_n173_n100# 0.29fF
-C1 a_111_n100# a_15_n100# 0.29fF
-C2 a_n81_n100# a_15_n100# 0.29fF
-C3 a_n128_122# a_15_n100# 0.10fF
-C4 a_n173_n100# a_15_n100# 0.11fF
-C5 a_n81_n100# a_111_n100# 0.11fF
+C0 a_n128_122# a_n81_n100# 0.10fF
+C1 a_15_n100# a_111_n100# 0.29fF
+C2 a_15_n100# a_n81_n100# 0.29fF
+C3 a_n81_n100# a_111_n100# 0.11fF
+C4 a_15_n100# a_n173_n100# 0.11fF
+C5 a_15_n100# a_n128_122# 0.10fF
C6 a_111_n100# a_n173_n100# 0.06fF
-C7 a_n81_n100# a_n128_122# 0.10fF
+C7 a_n81_n100# a_n173_n100# 0.29fF
C8 a_111_n100# w_n311_n310# 0.15fF
C9 a_15_n100# w_n311_n310# 0.11fF
C10 a_n81_n100# w_n311_n310# 0.11fF
@@ -1328,19 +1328,19 @@
X0 a_15_n100# a_n129_131# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X1 a_111_n100# a_n129_131# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X2 a_n81_n100# a_n129_131# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n81_n100# a_15_n100# 0.29fF
-C1 a_n81_n100# a_n173_n100# 0.29fF
-C2 a_n81_n100# w_n311_n319# 0.08fF
-C3 a_n81_n100# a_n129_131# 0.08fF
-C4 a_15_n100# a_n173_n100# 0.11fF
-C5 a_15_n100# w_n311_n319# 0.08fF
-C6 a_15_n100# a_n129_131# 0.08fF
-C7 w_n311_n319# a_n173_n100# 0.12fF
-C8 w_n311_n319# a_n129_131# 0.16fF
-C9 a_n81_n100# a_111_n100# 0.11fF
-C10 a_15_n100# a_111_n100# 0.29fF
-C11 a_111_n100# a_n173_n100# 0.06fF
-C12 w_n311_n319# a_111_n100# 0.12fF
+C0 w_n311_n319# a_n173_n100# 0.12fF
+C1 a_n81_n100# a_15_n100# 0.29fF
+C2 a_111_n100# w_n311_n319# 0.12fF
+C3 a_n81_n100# a_n173_n100# 0.29fF
+C4 w_n311_n319# a_n129_131# 0.16fF
+C5 a_n173_n100# a_15_n100# 0.11fF
+C6 a_111_n100# a_n81_n100# 0.11fF
+C7 a_n81_n100# a_n129_131# 0.08fF
+C8 a_n81_n100# w_n311_n319# 0.08fF
+C9 a_111_n100# a_15_n100# 0.29fF
+C10 a_15_n100# a_n129_131# 0.08fF
+C11 w_n311_n319# a_15_n100# 0.08fF
+C12 a_111_n100# a_n173_n100# 0.06fF
C13 a_111_n100# VSUBS 0.03fF
C14 a_15_n100# VSUBS 0.03fF
C15 a_n81_n100# VSUBS 0.03fF
@@ -1356,31 +1356,31 @@
X2 a_111_n100# a_n225_131# a_15_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X3 a_n81_n100# a_n225_131# a_n177_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X4 a_n177_n100# a_n225_131# a_n269_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n269_n100# a_111_n100# 0.05fF
-C1 a_111_n100# a_207_n100# 0.29fF
-C2 a_15_n100# a_111_n100# 0.29fF
-C3 a_n225_131# a_n177_n100# 0.08fF
-C4 a_n81_n100# w_n407_n319# 0.06fF
-C5 a_n269_n100# a_15_n100# 0.06fF
-C6 a_n81_n100# a_111_n100# 0.11fF
-C7 a_15_n100# a_207_n100# 0.11fF
-C8 a_n225_131# w_n407_n319# 0.25fF
-C9 a_n177_n100# w_n407_n319# 0.05fF
-C10 a_n225_131# a_111_n100# 0.08fF
-C11 a_n269_n100# a_n81_n100# 0.11fF
-C12 a_n81_n100# a_207_n100# 0.06fF
-C13 a_15_n100# a_n81_n100# 0.29fF
-C14 a_111_n100# a_n177_n100# 0.06fF
-C15 a_15_n100# a_n225_131# 0.08fF
-C16 a_111_n100# w_n407_n319# 0.05fF
-C17 a_n269_n100# a_n177_n100# 0.29fF
-C18 a_207_n100# a_n177_n100# 0.05fF
-C19 a_15_n100# a_n177_n100# 0.11fF
-C20 a_n225_131# a_n81_n100# 0.08fF
-C21 a_n269_n100# w_n407_n319# 0.10fF
-C22 a_207_n100# w_n407_n319# 0.10fF
-C23 a_15_n100# w_n407_n319# 0.06fF
-C24 a_n81_n100# a_n177_n100# 0.29fF
+C0 a_111_n100# a_n81_n100# 0.11fF
+C1 w_n407_n319# a_n269_n100# 0.10fF
+C2 a_n177_n100# a_n81_n100# 0.29fF
+C3 a_111_n100# a_n269_n100# 0.05fF
+C4 a_15_n100# a_n225_131# 0.08fF
+C5 a_15_n100# w_n407_n319# 0.06fF
+C6 a_n177_n100# a_n269_n100# 0.29fF
+C7 w_n407_n319# a_n225_131# 0.25fF
+C8 a_15_n100# a_207_n100# 0.11fF
+C9 a_15_n100# a_111_n100# 0.29fF
+C10 a_111_n100# a_n225_131# 0.08fF
+C11 w_n407_n319# a_207_n100# 0.10fF
+C12 a_n269_n100# a_n81_n100# 0.11fF
+C13 a_15_n100# a_n177_n100# 0.11fF
+C14 w_n407_n319# a_111_n100# 0.05fF
+C15 a_n177_n100# a_n225_131# 0.08fF
+C16 a_111_n100# a_207_n100# 0.29fF
+C17 a_n177_n100# w_n407_n319# 0.05fF
+C18 a_n177_n100# a_207_n100# 0.05fF
+C19 a_15_n100# a_n81_n100# 0.29fF
+C20 a_n81_n100# a_n225_131# 0.08fF
+C21 a_n177_n100# a_111_n100# 0.06fF
+C22 w_n407_n319# a_n81_n100# 0.06fF
+C23 a_15_n100# a_n269_n100# 0.06fF
+C24 a_n81_n100# a_207_n100# 0.06fF
C25 a_207_n100# VSUBS 0.03fF
C26 a_111_n100# VSUBS 0.03fF
C27 a_15_n100# VSUBS 0.03fF
@@ -1393,9 +1393,9 @@
.subckt sky130_fd_pr__nfet_01v8_lvt_2AP43D a_15_n81# a_n33_41# w_n211_n229# a_n73_n81#
X0 a_15_n81# a_n33_41# a_n73_n81# w_n211_n229# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=500000u l=150000u
-C0 a_15_n81# a_n73_n81# 0.17fF
-C1 a_n73_n81# a_n33_41# 0.02fF
-C2 a_15_n81# a_n33_41# 0.02fF
+C0 a_n73_n81# a_n33_41# 0.02fF
+C1 a_n33_41# a_15_n81# 0.02fF
+C2 a_n73_n81# a_15_n81# 0.17fF
C3 a_15_n81# w_n211_n229# 0.12fF
C4 a_n73_n81# w_n211_n229# 0.12fF
C5 a_n33_41# w_n211_n229# 0.18fF
@@ -1416,32 +1416,32 @@
Xsky130_fd_pr__pfet_01v8_2XUYGK_6 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
Xsky130_fd_pr__pfet_01v8_2XUYGK_7 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
Xsky130_fd_pr__pfet_01v8_2XUYGK_8 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
-C0 avdd1p8 inn 1.05fF
-C1 vctrl clk 0.02fF
-C2 clk avdd1p8 2.36fF
-C3 vctrl a_3747_261# 0.76fF
-C4 outn avdd1p8 1.33fF
-C5 a_3747_261# avdd1p8 1.24fF
-C6 vp avdd1p8 6.92fF
-C7 avdd1p8 inp 1.02fF
-C8 avdd1p8 outp 1.56fF
-C9 outn inn 1.15fF
-C10 vp inn 0.84fF
-C11 inp inn 2.67fF
-C12 clk outn 0.71fF
-C13 clk a_3747_261# 0.44fF
-C14 vp clk 0.79fF
-C15 clk inp 0.06fF
-C16 vp a_3747_261# 1.08fF
-C17 vp outn 4.23fF
-C18 outn inp 5.59fF
-C19 outp inn 5.76fF
-C20 vp inp 0.78fF
-C21 vctrl avdd1p8 1.19fF
-C22 clk outp 0.56fF
-C23 outn outp 4.18fF
+C0 avdd1p8 outp 1.56fF
+C1 clk vctrl 0.02fF
+C2 inp outp 1.28fF
+C3 outn inn 1.15fF
+C4 vp outn 4.23fF
+C5 clk outn 0.71fF
+C6 avdd1p8 vctrl 1.19fF
+C7 avdd1p8 outn 1.33fF
+C8 vp inn 0.84fF
+C9 clk vp 0.79fF
+C10 a_3747_261# vctrl 0.76fF
+C11 inp outn 5.59fF
+C12 avdd1p8 inn 1.05fF
+C13 avdd1p8 vp 6.92fF
+C14 avdd1p8 clk 2.36fF
+C15 inp inn 2.67fF
+C16 vp inp 0.78fF
+C17 clk inp 0.06fF
+C18 outn outp 4.18fF
+C19 vp a_3747_261# 1.08fF
+C20 clk a_3747_261# 0.44fF
+C21 avdd1p8 inp 1.02fF
+C22 avdd1p8 a_3747_261# 1.24fF
+C23 inn outp 5.76fF
C24 vp outp 4.81fF
-C25 inp outp 1.28fF
+C25 clk outp 0.56fF
C26 outn avss1p8 0.69fF
C27 inp avss1p8 -0.11fF
C28 outp avss1p8 -0.62fF
@@ -1460,24 +1460,24 @@
X2 a_n81_n100# a_n225_n188# a_n177_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X3 a_111_n100# a_n225_n188# a_15_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X4 a_n177_n100# a_n225_n188# a_n269_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n81_n100# a_n177_n100# 0.29fF
-C1 a_n177_n100# a_n269_n100# 0.29fF
-C2 a_15_n100# a_n81_n100# 0.29fF
-C3 a_15_n100# a_n269_n100# 0.06fF
-C4 a_n225_n188# a_n81_n100# 0.10fF
-C5 a_111_n100# a_n81_n100# 0.11fF
-C6 a_15_n100# a_n177_n100# 0.11fF
-C7 a_111_n100# a_n269_n100# 0.05fF
-C8 a_n225_n188# a_n177_n100# 0.10fF
-C9 a_15_n100# a_n225_n188# 0.10fF
-C10 a_111_n100# a_n177_n100# 0.06fF
-C11 a_15_n100# a_111_n100# 0.29fF
-C12 a_n81_n100# a_207_n100# 0.06fF
-C13 a_n225_n188# a_111_n100# 0.10fF
-C14 a_n177_n100# a_207_n100# 0.05fF
-C15 a_15_n100# a_207_n100# 0.11fF
-C16 a_n81_n100# a_n269_n100# 0.11fF
-C17 a_111_n100# a_207_n100# 0.29fF
+C0 a_n225_n188# a_n177_n100# 0.10fF
+C1 a_n81_n100# a_15_n100# 0.29fF
+C2 a_111_n100# a_n177_n100# 0.06fF
+C3 a_n269_n100# a_n177_n100# 0.29fF
+C4 a_n225_n188# a_15_n100# 0.10fF
+C5 a_111_n100# a_15_n100# 0.29fF
+C6 a_n269_n100# a_15_n100# 0.06fF
+C7 a_n225_n188# a_n81_n100# 0.10fF
+C8 a_111_n100# a_n81_n100# 0.11fF
+C9 a_207_n100# a_n177_n100# 0.05fF
+C10 a_n269_n100# a_n81_n100# 0.11fF
+C11 a_n225_n188# a_111_n100# 0.10fF
+C12 a_207_n100# a_15_n100# 0.11fF
+C13 a_n269_n100# a_111_n100# 0.05fF
+C14 a_207_n100# a_n81_n100# 0.06fF
+C15 a_n177_n100# a_15_n100# 0.11fF
+C16 a_n177_n100# a_n81_n100# 0.29fF
+C17 a_207_n100# a_111_n100# 0.29fF
C18 a_207_n100# w_n407_n310# 0.13fF
C19 a_111_n100# w_n407_n310# 0.08fF
C20 a_15_n100# w_n407_n310# 0.09fF
@@ -1495,29 +1495,29 @@
X3 a_255_n100# a_n271_122# a_159_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X4 a_n225_n100# a_n271_122# a_n317_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X5 a_n129_n100# a_n271_122# a_n225_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n129_n100# a_255_n100# 0.05fF
-C1 a_n129_n100# a_n33_n100# 0.29fF
-C2 a_255_n100# a_159_n100# 0.29fF
-C3 a_n33_n100# a_159_n100# 0.11fF
-C4 a_n225_n100# a_n33_n100# 0.11fF
-C5 a_255_n100# a_63_n100# 0.11fF
-C6 a_n33_n100# a_63_n100# 0.29fF
-C7 a_n129_n100# a_159_n100# 0.06fF
-C8 a_n225_n100# a_n129_n100# 0.29fF
-C9 a_n225_n100# a_159_n100# 0.05fF
-C10 a_n129_n100# a_63_n100# 0.11fF
-C11 a_63_n100# a_159_n100# 0.29fF
-C12 a_n225_n100# a_63_n100# 0.06fF
-C13 a_n33_n100# a_n271_122# 0.10fF
-C14 a_n129_n100# a_n271_122# 0.10fF
-C15 a_n271_122# a_159_n100# 0.10fF
-C16 a_n225_n100# a_n271_122# 0.10fF
-C17 a_n33_n100# a_n317_n100# 0.06fF
-C18 a_n271_122# a_63_n100# 0.10fF
-C19 a_n129_n100# a_n317_n100# 0.11fF
+C0 a_159_n100# a_63_n100# 0.29fF
+C1 a_n317_n100# a_n33_n100# 0.06fF
+C2 a_n129_n100# a_n225_n100# 0.29fF
+C3 a_159_n100# a_n33_n100# 0.11fF
+C4 a_n129_n100# a_63_n100# 0.11fF
+C5 a_n225_n100# a_63_n100# 0.06fF
+C6 a_n129_n100# a_n33_n100# 0.29fF
+C7 a_n271_122# a_159_n100# 0.10fF
+C8 a_n225_n100# a_n33_n100# 0.11fF
+C9 a_159_n100# a_255_n100# 0.29fF
+C10 a_n33_n100# a_63_n100# 0.29fF
+C11 a_n271_122# a_n129_n100# 0.10fF
+C12 a_n129_n100# a_255_n100# 0.05fF
+C13 a_n271_122# a_n225_n100# 0.10fF
+C14 a_n271_122# a_63_n100# 0.10fF
+C15 a_255_n100# a_63_n100# 0.11fF
+C16 a_n317_n100# a_n129_n100# 0.11fF
+C17 a_159_n100# a_n129_n100# 0.06fF
+C18 a_n317_n100# a_n225_n100# 0.29fF
+C19 a_n271_122# a_n33_n100# 0.10fF
C20 a_n33_n100# a_255_n100# 0.06fF
-C21 a_n225_n100# a_n317_n100# 0.29fF
-C22 a_63_n100# a_n317_n100# 0.05fF
+C21 a_159_n100# a_n225_n100# 0.05fF
+C22 a_n317_n100# a_63_n100# 0.05fF
C23 a_255_n100# w_n455_n310# 0.13fF
C24 a_159_n100# w_n455_n310# 0.08fF
C25 a_63_n100# w_n455_n310# 0.07fF
@@ -1532,11 +1532,11 @@
+ a_n125_n100#
X0 a_63_n100# a_n79_122# a_n33_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X1 a_n33_n100# a_n79_122# a_n125_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n125_n100# a_n33_n100# 0.29fF
-C1 a_n33_n100# a_n79_122# 0.11fF
-C2 a_n33_n100# a_63_n100# 0.29fF
-C3 a_n125_n100# a_n79_122# 0.02fF
-C4 a_n125_n100# a_63_n100# 0.11fF
+C0 a_63_n100# a_n33_n100# 0.29fF
+C1 a_n79_122# a_n33_n100# 0.11fF
+C2 a_63_n100# a_n125_n100# 0.11fF
+C3 a_n79_122# a_n125_n100# 0.02fF
+C4 a_n125_n100# a_n33_n100# 0.29fF
C5 a_n79_122# a_63_n100# 0.02fF
C6 a_63_n100# w_n263_n310# 0.16fF
C7 a_n33_n100# w_n263_n310# 0.12fF
@@ -1554,39 +1554,39 @@
X5 a_n321_n100# a_n368_122# a_n413_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X6 a_n225_n100# a_n368_122# a_n321_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X7 a_n129_n100# a_n368_122# a_n225_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n225_n100# a_63_n100# 0.06fF
-C1 a_n129_n100# a_n33_n100# 0.29fF
-C2 a_n33_n100# a_255_n100# 0.06fF
-C3 a_n321_n100# a_n129_n100# 0.11fF
-C4 a_351_n100# a_159_n100# 0.11fF
-C5 a_n129_n100# a_n413_n100# 0.06fF
-C6 a_n368_122# a_n33_n100# 0.10fF
-C7 a_n368_122# a_n321_n100# 0.10fF
-C8 a_351_n100# a_63_n100# 0.06fF
-C9 a_n129_n100# a_255_n100# 0.05fF
-C10 a_n33_n100# a_159_n100# 0.11fF
-C11 a_n368_122# a_n129_n100# 0.10fF
-C12 a_n368_122# a_255_n100# 0.10fF
-C13 a_n33_n100# a_n225_n100# 0.11fF
-C14 a_n321_n100# a_n225_n100# 0.29fF
-C15 a_n33_n100# a_63_n100# 0.29fF
-C16 a_n413_n100# a_n225_n100# 0.11fF
-C17 a_n321_n100# a_63_n100# 0.05fF
-C18 a_n129_n100# a_159_n100# 0.06fF
-C19 a_159_n100# a_255_n100# 0.29fF
-C20 a_n129_n100# a_n225_n100# 0.29fF
-C21 a_n33_n100# a_351_n100# 0.05fF
-C22 a_n368_122# a_159_n100# 0.10fF
-C23 a_n129_n100# a_63_n100# 0.11fF
-C24 a_255_n100# a_63_n100# 0.11fF
-C25 a_n368_122# a_n225_n100# 0.10fF
-C26 a_n368_122# a_63_n100# 0.10fF
-C27 a_351_n100# a_255_n100# 0.29fF
-C28 a_n321_n100# a_n33_n100# 0.06fF
-C29 a_n225_n100# a_159_n100# 0.05fF
-C30 a_n413_n100# a_n33_n100# 0.05fF
-C31 a_159_n100# a_63_n100# 0.29fF
-C32 a_n321_n100# a_n413_n100# 0.29fF
+C0 a_n225_n100# a_n321_n100# 0.29fF
+C1 a_n368_122# a_n33_n100# 0.10fF
+C2 a_159_n100# a_255_n100# 0.29fF
+C3 a_n321_n100# a_n33_n100# 0.06fF
+C4 a_n368_122# a_n321_n100# 0.10fF
+C5 a_63_n100# a_n129_n100# 0.11fF
+C6 a_n225_n100# a_n129_n100# 0.29fF
+C7 a_351_n100# a_255_n100# 0.29fF
+C8 a_159_n100# a_351_n100# 0.11fF
+C9 a_n33_n100# a_n129_n100# 0.29fF
+C10 a_63_n100# a_255_n100# 0.11fF
+C11 a_159_n100# a_63_n100# 0.29fF
+C12 a_n225_n100# a_n413_n100# 0.11fF
+C13 a_n368_122# a_n129_n100# 0.10fF
+C14 a_159_n100# a_n225_n100# 0.05fF
+C15 a_n413_n100# a_n33_n100# 0.05fF
+C16 a_n33_n100# a_255_n100# 0.06fF
+C17 a_n321_n100# a_n129_n100# 0.11fF
+C18 a_159_n100# a_n33_n100# 0.11fF
+C19 a_351_n100# a_63_n100# 0.06fF
+C20 a_n368_122# a_255_n100# 0.10fF
+C21 a_n368_122# a_159_n100# 0.10fF
+C22 a_n413_n100# a_n321_n100# 0.29fF
+C23 a_351_n100# a_n33_n100# 0.05fF
+C24 a_n225_n100# a_63_n100# 0.06fF
+C25 a_63_n100# a_n33_n100# 0.29fF
+C26 a_n225_n100# a_n33_n100# 0.11fF
+C27 a_n413_n100# a_n129_n100# 0.06fF
+C28 a_n368_122# a_63_n100# 0.10fF
+C29 a_255_n100# a_n129_n100# 0.05fF
+C30 a_159_n100# a_n129_n100# 0.06fF
+C31 a_n368_122# a_n225_n100# 0.10fF
+C32 a_63_n100# a_n321_n100# 0.05fF
C33 a_351_n100# w_n551_n310# 0.13fF
C34 a_255_n100# w_n551_n310# 0.08fF
C35 a_159_n100# w_n551_n310# 0.07fF
@@ -1604,19 +1604,19 @@
X0 a_15_n100# a_n129_n197# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X1 a_111_n100# a_n129_n197# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X2 a_n81_n100# a_n129_n197# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_111_n100# a_n81_n100# 0.11fF
-C1 a_15_n100# a_n81_n100# 0.29fF
-C2 a_111_n100# a_15_n100# 0.29fF
-C3 a_n129_n197# a_n81_n100# 0.08fF
-C4 a_n129_n197# a_15_n100# 0.08fF
-C5 w_n311_n319# a_n81_n100# 0.08fF
-C6 a_111_n100# w_n311_n319# 0.12fF
-C7 a_n173_n100# a_n81_n100# 0.29fF
-C8 a_111_n100# a_n173_n100# 0.06fF
-C9 w_n311_n319# a_15_n100# 0.08fF
-C10 a_n129_n197# w_n311_n319# 0.17fF
-C11 a_n173_n100# a_15_n100# 0.11fF
-C12 a_n173_n100# w_n311_n319# 0.12fF
+C0 a_111_n100# w_n311_n319# 0.12fF
+C1 w_n311_n319# a_n173_n100# 0.12fF
+C2 a_n81_n100# a_15_n100# 0.29fF
+C3 a_111_n100# a_n173_n100# 0.06fF
+C4 a_n129_n197# w_n311_n319# 0.17fF
+C5 a_n81_n100# w_n311_n319# 0.08fF
+C6 a_111_n100# a_n81_n100# 0.11fF
+C7 a_n81_n100# a_n173_n100# 0.29fF
+C8 a_n81_n100# a_n129_n197# 0.08fF
+C9 a_15_n100# w_n311_n319# 0.08fF
+C10 a_111_n100# a_15_n100# 0.29fF
+C11 a_15_n100# a_n173_n100# 0.11fF
+C12 a_n129_n197# a_15_n100# 0.08fF
C13 a_111_n100# VSUBS 0.03fF
C14 a_15_n100# VSUBS 0.03fF
C15 a_n81_n100# VSUBS 0.03fF
@@ -1631,19 +1631,19 @@
X1 a_n33_n100# a_n176_122# a_n129_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X2 a_159_n100# a_n176_122# a_63_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X3 a_n129_n100# a_n176_122# a_n221_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n129_n100# a_n33_n100# 0.29fF
-C1 a_n129_n100# a_159_n100# 0.06fF
-C2 a_n129_n100# a_n221_n100# 0.29fF
-C3 a_159_n100# a_n33_n100# 0.11fF
-C4 a_n129_n100# a_63_n100# 0.11fF
-C5 a_n33_n100# a_n221_n100# 0.11fF
-C6 a_n129_n100# a_n176_122# 0.10fF
-C7 a_159_n100# a_n221_n100# 0.05fF
-C8 a_63_n100# a_n33_n100# 0.29fF
-C9 a_159_n100# a_63_n100# 0.29fF
-C10 a_n176_122# a_n33_n100# 0.10fF
-C11 a_63_n100# a_n221_n100# 0.06fF
-C12 a_63_n100# a_n176_122# 0.10fF
+C0 a_n176_122# a_n129_n100# 0.10fF
+C1 a_n33_n100# a_63_n100# 0.29fF
+C2 a_159_n100# a_n129_n100# 0.06fF
+C3 a_159_n100# a_n221_n100# 0.05fF
+C4 a_n221_n100# a_n129_n100# 0.29fF
+C5 a_n33_n100# a_n176_122# 0.10fF
+C6 a_159_n100# a_n33_n100# 0.11fF
+C7 a_n33_n100# a_n129_n100# 0.29fF
+C8 a_n33_n100# a_n221_n100# 0.11fF
+C9 a_63_n100# a_n176_122# 0.10fF
+C10 a_159_n100# a_63_n100# 0.29fF
+C11 a_63_n100# a_n129_n100# 0.11fF
+C12 a_n221_n100# a_63_n100# 0.06fF
C13 a_159_n100# w_n359_n310# 0.13fF
C14 a_63_n100# w_n359_n310# 0.10fF
C15 a_n33_n100# w_n359_n310# 0.10fF
@@ -1656,14 +1656,14 @@
+ a_63_n100# a_n125_n100#
X0 a_63_n100# a_n81_n197# a_n33_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X1 a_n33_n100# a_n81_n197# a_n125_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n33_n100# w_n263_n319# 0.09fF
-C1 a_n81_n197# w_n263_n319# 0.11fF
-C2 a_63_n100# a_n125_n100# 0.11fF
-C3 a_n33_n100# a_n125_n100# 0.29fF
-C4 a_n33_n100# a_63_n100# 0.29fF
+C0 w_n263_n319# a_n125_n100# 0.13fF
+C1 a_n33_n100# a_63_n100# 0.29fF
+C2 a_n81_n197# w_n263_n319# 0.11fF
+C3 a_n33_n100# w_n263_n319# 0.09fF
+C4 a_n33_n100# a_n125_n100# 0.29fF
C5 a_n33_n100# a_n81_n197# 0.08fF
-C6 w_n263_n319# a_n125_n100# 0.13fF
-C7 w_n263_n319# a_63_n100# 0.13fF
+C6 a_63_n100# w_n263_n319# 0.13fF
+C7 a_63_n100# a_n125_n100# 0.11fF
C8 a_63_n100# VSUBS 0.03fF
C9 a_n33_n100# VSUBS 0.03fF
C10 a_n125_n100# VSUBS 0.03fF
@@ -1672,7 +1672,7 @@
.ends
.subckt iref_ctrl_res_amp m1_n356_n363# avss1p8 vctrl reg2 avdd1p8 reg0 m1_1996_n363#
-+ reg1 iref m1_964_n363# m1_511_801# m1_1384_n363#
++ reg1 iref m1_511_801# m1_964_n363# m1_1384_n363#
Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 iref m1_n356_n363# m1_n356_n363# iref iref iref
+ avss1p8 iref m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_n356_n363# m1_n356_n363# avdd1p8
@@ -1694,42 +1694,42 @@
Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_1 avss1p8 m1_1384_n363# avss1p8 m1_1384_n363#
+ avss1p8 reg1 avss1p8 sky130_fd_pr__nfet_01v8_lvt_B2JNY3
Xsky130_fd_pr__pfet_01v8_XACJHL_0 avss1p8 vctrl avdd1p8 m1_511_801# vctrl vctrl sky130_fd_pr__pfet_01v8_XACJHL
-C0 m1_448_n363# m1_964_n363# 0.24fF
-C1 m1_1996_n363# m1_1384_n363# 0.18fF
-C2 m1_964_n363# reg0 0.47fF
-C3 iref reg2 0.03fF
-C4 m1_448_n363# vctrl 1.16fF
-C5 reg1 m1_1384_n363# 0.85fF
-C6 vctrl reg0 0.04fF
-C7 m1_448_n363# m1_n356_n363# 0.17fF
-C8 m1_448_n363# avdd1p8 0.77fF
-C9 m1_511_801# vctrl 1.08fF
-C10 avdd1p8 reg0 0.03fF
-C11 iref m1_1384_n363# 0.22fF
-C12 m1_511_801# avdd1p8 1.05fF
-C13 vctrl m1_964_n363# 0.52fF
-C14 reg1 reg0 0.04fF
-C15 vctrl m1_n356_n363# 0.08fF
-C16 vctrl avdd1p8 0.52fF
-C17 iref m1_448_n363# 0.29fF
-C18 avdd1p8 m1_n356_n363# 1.41fF
-C19 iref reg0 0.02fF
-C20 vctrl m1_1996_n363# 1.72fF
-C21 iref m1_511_801# 0.05fF
-C22 iref m1_964_n363# 0.11fF
-C23 vctrl reg1 0.06fF
-C24 m1_1384_n363# reg0 0.06fF
-C25 m1_1996_n363# reg1 0.06fF
-C26 iref vctrl 2.27fF
-C27 vctrl reg2 0.07fF
-C28 iref m1_n356_n363# 1.89fF
-C29 iref avdd1p8 0.32fF
-C30 m1_1384_n363# m1_964_n363# 0.18fF
-C31 iref m1_1996_n363# 0.41fF
-C32 m1_1996_n363# reg2 1.30fF
-C33 vctrl m1_1384_n363# 0.95fF
-C34 iref reg1 0.03fF
-C35 reg1 reg2 0.04fF
+C0 m1_1996_n363# reg2 1.30fF
+C1 m1_1384_n363# reg1 0.85fF
+C2 m1_448_n363# m1_n356_n363# 0.17fF
+C3 m1_964_n363# iref 0.11fF
+C4 vctrl reg1 0.06fF
+C5 m1_964_n363# reg0 0.47fF
+C6 iref reg0 0.02fF
+C7 iref m1_n356_n363# 1.89fF
+C8 m1_448_n363# vctrl 1.16fF
+C9 m1_1996_n363# reg1 0.06fF
+C10 m1_964_n363# m1_1384_n363# 0.18fF
+C11 m1_1384_n363# iref 0.22fF
+C12 reg2 reg1 0.04fF
+C13 m1_448_n363# avdd1p8 0.77fF
+C14 m1_964_n363# vctrl 0.52fF
+C15 m1_1384_n363# reg0 0.06fF
+C16 vctrl iref 2.27fF
+C17 avdd1p8 iref 0.32fF
+C18 vctrl reg0 0.04fF
+C19 vctrl m1_n356_n363# 0.08fF
+C20 m1_511_801# iref 0.05fF
+C21 avdd1p8 reg0 0.03fF
+C22 avdd1p8 m1_n356_n363# 1.41fF
+C23 m1_1996_n363# iref 0.41fF
+C24 reg2 iref 0.03fF
+C25 m1_1384_n363# vctrl 0.95fF
+C26 avdd1p8 vctrl 0.52fF
+C27 m1_1996_n363# m1_1384_n363# 0.18fF
+C28 m1_511_801# vctrl 1.08fF
+C29 avdd1p8 m1_511_801# 1.05fF
+C30 m1_1996_n363# vctrl 1.72fF
+C31 reg1 iref 0.03fF
+C32 vctrl reg2 0.07fF
+C33 reg1 reg0 0.04fF
+C34 m1_448_n363# m1_964_n363# 0.24fF
+C35 m1_448_n363# iref 0.29fF
C36 m1_511_801# avss1p8 -1.62fF
C37 m1_1384_n363# avss1p8 1.30fF
C38 reg1 avss1p8 1.36fF
@@ -1745,10 +1745,10 @@
.ends
.subckt res_amp_lin_prog delay_cell_buff_0/mux_2to1_logic_0/out iref_ctrl_res_amp_0/m1_964_n363#
-+ delay_reg2 avdd1p8 inp delay_cell_buff_0/mux_2to1_logic_3/DinA delay_cell_buff_0/mux_2to1_logic_3/out
-+ res_amp_lin_0/vctrl iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_0/clk delay_cell_buff_0/nand_logic_0/in1
-+ outp_cap avss1p8 outn_cap clk delay_cell_buff_0/mux_2to1_logic_1/sel_b delay_reg0
-+ delay_cell_buff_0/mux_2to1_logic_4/DinA delay_cell_buff_0/mux_2to1_logic_4/DinB
++ delay_reg2 avdd1p8 inp delay_cell_buff_0/mux_2to1_logic_3/DinA res_amp_lin_0/vctrl
++ delay_cell_buff_0/mux_2to1_logic_3/out iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_0/clk
++ delay_cell_buff_0/nand_logic_0/in1 outp_cap avss1p8 outn_cap clk delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ delay_reg0 delay_cell_buff_0/mux_2to1_logic_4/DinA delay_cell_buff_0/mux_2to1_logic_4/DinB
+ outn delay_cell_buff_0/mux_2to1_logic_1/DinA outp delay_cell_buff_0/mux_2to1_logic_5/out
+ delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in delay_cell_buff_0/mux_2to1_logic_3/DinB
+ iref_reg0 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in iref_reg1 iref_reg2
@@ -1786,29 +1786,29 @@
Xsky130_fd_pr__nfet_01v8_lvt_595QY5_1 outp outp outp outp_cap outp_cap avss1p8 outp_cap
+ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
Xiref_ctrl_res_amp_0 iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 res_amp_lin_0/vctrl
-+ iref_reg2 avdd1p8 iref_reg0 iref_ctrl_res_amp_0/m1_1996_n363# iref_reg1 iref iref_ctrl_res_amp_0/m1_964_n363#
-+ iref_ctrl_res_amp_0/m1_511_801# iref_ctrl_res_amp_0/m1_1384_n363# iref_ctrl_res_amp
-C0 outn_cap outn 1.90fF
++ iref_reg2 avdd1p8 iref_reg0 iref_ctrl_res_amp_0/m1_1996_n363# iref_reg1 iref iref_ctrl_res_amp_0/m1_511_801#
++ iref_ctrl_res_amp_0/m1_964_n363# iref_ctrl_res_amp_0/m1_1384_n363# iref_ctrl_res_amp
+C0 outp res_amp_lin_0/clk 0.09fF
C1 inverter_min_x4_0/out rst 0.01fF
-C2 res_amp_lin_0/clk avdd1p8 1.99fF
-C3 outn_cap inverter_min_x4_0/out 0.57fF
-C4 outn_cap avdd1p8 0.26fF
-C5 res_amp_lin_0/vctrl avdd1p8 1.42fF
-C6 outp outp_cap 1.90fF
-C7 res_amp_lin_0/vctrl iref 0.10fF
-C8 res_amp_lin_0/clk outn_cap 1.04fF
-C9 inverter_min_x4_0/out outp_cap 0.57fF
-C10 outn_cap rst 0.34fF
-C11 outn inverter_min_x4_0/out 0.32fF
-C12 inverter_min_x4_0/out outp 0.32fF
-C13 avdd1p8 outp_cap 0.25fF
-C14 outn avdd1p8 0.36fF
-C15 res_amp_lin_0/clk outp_cap 1.04fF
-C16 outp avdd1p8 0.34fF
-C17 res_amp_lin_0/clk outn 0.09fF
-C18 res_amp_lin_0/clk outp 0.09fF
-C19 rst outp_cap 0.34fF
-C20 res_amp_lin_0/clk inverter_min_x4_0/out 0.14fF
+C2 avdd1p8 outn_cap 0.26fF
+C3 outp_cap avdd1p8 0.25fF
+C4 inverter_min_x4_0/out outn_cap 0.57fF
+C5 outp_cap inverter_min_x4_0/out 0.57fF
+C6 rst outn_cap 0.34fF
+C7 outp_cap rst 0.34fF
+C8 res_amp_lin_0/clk avdd1p8 1.99fF
+C9 avdd1p8 outn 0.36fF
+C10 res_amp_lin_0/clk inverter_min_x4_0/out 0.14fF
+C11 inverter_min_x4_0/out outn 0.32fF
+C12 outp avdd1p8 0.34fF
+C13 outp inverter_min_x4_0/out 0.32fF
+C14 res_amp_lin_0/clk outn_cap 1.04fF
+C15 outn_cap outn 1.90fF
+C16 outp_cap res_amp_lin_0/clk 1.04fF
+C17 res_amp_lin_0/vctrl iref 0.10fF
+C18 res_amp_lin_0/clk outn 0.09fF
+C19 avdd1p8 res_amp_lin_0/vctrl 1.42fF
+C20 outp_cap outp 1.90fF
C21 iref_ctrl_res_amp_0/m1_511_801# avss1p8 -1.87fF
C22 iref_ctrl_res_amp_0/m1_1384_n363# avss1p8 0.47fF
C23 iref_reg1 avss1p8 0.47fF
@@ -1828,53 +1828,53 @@
C37 res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
C38 outn_cap avss1p8 -1.33fF
C39 rst avss1p8 0.58fF
-C40 res_amp_lin_0/clk avss1p8 5.34fF
-C41 inverter_min_x4_0/out avss1p8 7.53fF
+C40 inverter_min_x4_0/out avss1p8 7.53fF
+C41 res_amp_lin_0/clk avss1p8 5.34fF
C42 delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
-C43 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
-C44 delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
-C45 delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
-C46 delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
-C47 delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
-C48 delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
-C49 delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
-C50 delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
-C51 delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
-C52 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
-C53 clk avss1p8 -4.09fF
-C54 delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
-C55 delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
-C56 delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
-C57 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
-C58 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
-C59 delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
-C60 delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
-C61 delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
-C62 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
-C63 delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C43 delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C44 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C45 delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C46 delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C47 delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C48 delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C49 delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C50 delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C51 delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C52 delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C53 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C54 clk avss1p8 -4.09fF
+C55 delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C56 delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C57 delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C58 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C59 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C60 delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C61 delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C62 delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C63 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
C64 delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
-C65 delay_reg0 avss1p8 2.77fF
-C66 delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C65 delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C66 delay_reg0 avss1p8 2.77fF
C67 delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
-C68 delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
-C69 delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C68 delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C69 delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
C70 delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
-C71 delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
-C72 delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
-C73 delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
-C74 delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
-C75 delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
-C76 delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C71 delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C72 delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C73 delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C74 delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C75 delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C76 delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
C77 delay_reg1 avss1p8 3.80fF
C78 delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
-C79 delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
-C80 delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
-C81 delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C79 delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C80 delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C81 delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
C82 delay_reg2 avss1p8 11.07fF
C83 avdd1p8 avss1p8 177.60fF
-C84 delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.03fF
-C85 delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
-C86 delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C84 delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C85 delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C86 delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.03fF
C87 delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
C88 delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
C89 delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
@@ -1883,7 +1883,7 @@
.subckt sky130_fd_pr__cap_mim_m3_1_U5ZKVF VSUBS m3_n700_n850# c1_n600_n750#
X0 c1_n600_n750# m3_n700_n850# sky130_fd_pr__cap_mim_m3_1 l=7.5e+06u w=5.5e+06u
-C0 m3_n700_n850# c1_n600_n750# 5.48fF
+C0 c1_n600_n750# m3_n700_n850# 5.48fF
C1 m3_n700_n850# VSUBS 1.98fF
.ends
@@ -1900,54 +1900,54 @@
X7 a_n29_n236# a_n611_n262# a_n157_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
X8 a_n413_n236# a_n611_n262# a_n541_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
X9 a_n541_n236# a_n611_n262# a_n669_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
-C0 a_611_n236# a_355_n236# 0.15fF
-C1 a_n413_n236# a_n157_n236# 0.15fF
-C2 a_n29_n236# a_n157_n236# 0.36fF
-C3 a_n541_n236# a_n157_n236# 0.09fF
-C4 a_99_n236# w_n807_n384# 0.02fF
-C5 a_483_n236# a_611_n236# 0.36fF
-C6 a_n285_n236# a_n157_n236# 0.36fF
-C7 a_355_n236# w_n807_n384# 0.06fF
-C8 a_n611_n262# w_n807_n384# 0.60fF
-C9 a_355_n236# a_99_n236# 0.15fF
-C10 a_n611_n262# a_99_n236# 0.08fF
-C11 a_483_n236# w_n807_n384# 0.09fF
-C12 a_483_n236# a_99_n236# 0.09fF
-C13 a_n611_n262# a_355_n236# 0.08fF
-C14 a_227_n236# a_n157_n236# 0.09fF
-C15 a_n413_n236# w_n807_n384# 0.06fF
-C16 a_n29_n236# w_n807_n384# 0.02fF
-C17 a_n541_n236# w_n807_n384# 0.09fF
-C18 a_n29_n236# a_99_n236# 0.36fF
-C19 a_483_n236# a_355_n236# 0.36fF
-C20 a_n285_n236# w_n807_n384# 0.02fF
-C21 a_483_n236# a_n611_n262# 0.08fF
-C22 a_n285_n236# a_99_n236# 0.09fF
-C23 a_227_n236# a_611_n236# 0.09fF
-C24 a_n29_n236# a_355_n236# 0.09fF
-C25 a_n611_n262# a_n413_n236# 0.08fF
-C26 a_n29_n236# a_n611_n262# 0.08fF
-C27 a_n669_n236# w_n807_n384# 0.19fF
-C28 a_n611_n262# a_n541_n236# 0.08fF
-C29 a_n611_n262# a_n285_n236# 0.08fF
-C30 a_227_n236# w_n807_n384# 0.02fF
-C31 a_n29_n236# a_n413_n236# 0.09fF
-C32 a_227_n236# a_99_n236# 0.36fF
-C33 a_n413_n236# a_n541_n236# 0.36fF
-C34 a_n157_n236# w_n807_n384# 0.02fF
-C35 a_n413_n236# a_n285_n236# 0.36fF
-C36 a_n29_n236# a_n285_n236# 0.15fF
-C37 a_n285_n236# a_n541_n236# 0.15fF
-C38 a_99_n236# a_n157_n236# 0.15fF
-C39 a_227_n236# a_355_n236# 0.36fF
-C40 a_227_n236# a_n611_n262# 0.08fF
-C41 a_n413_n236# a_n669_n236# 0.15fF
-C42 a_611_n236# w_n807_n384# 0.19fF
-C43 a_n541_n236# a_n669_n236# 0.36fF
-C44 a_227_n236# a_483_n236# 0.15fF
-C45 a_n611_n262# a_n157_n236# 0.08fF
-C46 a_n285_n236# a_n669_n236# 0.09fF
-C47 a_n29_n236# a_227_n236# 0.15fF
+C0 a_483_n236# a_227_n236# 0.15fF
+C1 a_n541_n236# a_n285_n236# 0.15fF
+C2 a_n157_n236# a_n541_n236# 0.09fF
+C3 a_n413_n236# a_n285_n236# 0.36fF
+C4 a_n157_n236# a_n413_n236# 0.15fF
+C5 a_n29_n236# a_355_n236# 0.09fF
+C6 a_n29_n236# w_n807_n384# 0.02fF
+C7 a_355_n236# a_99_n236# 0.15fF
+C8 a_n29_n236# a_227_n236# 0.15fF
+C9 w_n807_n384# a_99_n236# 0.02fF
+C10 a_355_n236# a_611_n236# 0.15fF
+C11 a_227_n236# a_99_n236# 0.36fF
+C12 w_n807_n384# a_611_n236# 0.19fF
+C13 a_n541_n236# a_n413_n236# 0.36fF
+C14 a_227_n236# a_611_n236# 0.09fF
+C15 a_n669_n236# w_n807_n384# 0.19fF
+C16 a_n611_n262# a_355_n236# 0.08fF
+C17 a_n611_n262# w_n807_n384# 0.60fF
+C18 a_n611_n262# a_227_n236# 0.08fF
+C19 a_n29_n236# a_n285_n236# 0.15fF
+C20 a_99_n236# a_n285_n236# 0.09fF
+C21 a_n29_n236# a_n157_n236# 0.36fF
+C22 a_n157_n236# a_99_n236# 0.15fF
+C23 a_n669_n236# a_n285_n236# 0.09fF
+C24 a_n611_n262# a_n285_n236# 0.08fF
+C25 a_355_n236# w_n807_n384# 0.06fF
+C26 a_n611_n262# a_n157_n236# 0.08fF
+C27 a_355_n236# a_227_n236# 0.36fF
+C28 a_227_n236# w_n807_n384# 0.02fF
+C29 a_n29_n236# a_n413_n236# 0.09fF
+C30 a_n669_n236# a_n541_n236# 0.36fF
+C31 a_n611_n262# a_n541_n236# 0.08fF
+C32 a_483_n236# a_99_n236# 0.09fF
+C33 a_n669_n236# a_n413_n236# 0.15fF
+C34 w_n807_n384# a_n285_n236# 0.02fF
+C35 a_483_n236# a_611_n236# 0.36fF
+C36 a_n611_n262# a_n413_n236# 0.08fF
+C37 a_n157_n236# w_n807_n384# 0.02fF
+C38 a_n157_n236# a_227_n236# 0.09fF
+C39 a_483_n236# a_n611_n262# 0.08fF
+C40 a_n29_n236# a_99_n236# 0.36fF
+C41 a_n541_n236# w_n807_n384# 0.09fF
+C42 a_n157_n236# a_n285_n236# 0.36fF
+C43 w_n807_n384# a_n413_n236# 0.06fF
+C44 a_n29_n236# a_n611_n262# 0.08fF
+C45 a_483_n236# a_355_n236# 0.36fF
+C46 a_n611_n262# a_99_n236# 0.08fF
+C47 a_483_n236# w_n807_n384# 0.09fF
C48 a_611_n236# VSUBS 0.03fF
C49 a_483_n236# VSUBS 0.03fF
C50 a_355_n236# VSUBS 0.03fF
@@ -1981,91 +1981,91 @@
X12 a_n273_n100# a_n705_n197# a_n369_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X13 a_n81_n100# a_n705_n197# a_n177_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X14 a_n177_n100# a_n705_n197# a_n273_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_495_n100# a_399_n100# 0.29fF
-C1 a_495_n100# a_591_n100# 0.29fF
-C2 a_303_n100# a_n705_n197# 0.08fF
-C3 a_303_n100# a_n81_n100# 0.05fF
-C4 a_15_n100# w_n887_n319# 0.02fF
-C5 a_n273_n100# a_15_n100# 0.06fF
-C6 w_n887_n319# a_111_n100# 0.02fF
-C7 a_n273_n100# a_111_n100# 0.05fF
-C8 a_303_n100# a_399_n100# 0.29fF
-C9 a_303_n100# a_591_n100# 0.06fF
-C10 a_111_n100# a_495_n100# 0.05fF
-C11 a_n369_n100# a_n749_n100# 0.05fF
-C12 w_n887_n319# a_n465_n100# 0.03fF
-C13 a_n273_n100# w_n887_n319# 0.02fF
-C14 a_n273_n100# a_n465_n100# 0.11fF
-C15 a_303_n100# a_15_n100# 0.06fF
-C16 w_n887_n319# a_495_n100# 0.04fF
-C17 a_303_n100# a_111_n100# 0.11fF
-C18 a_n369_n100# a_n177_n100# 0.11fF
-C19 a_n369_n100# a_n561_n100# 0.11fF
-C20 w_n887_n319# a_n657_n100# 0.05fF
-C21 a_n369_n100# a_n705_n197# 0.08fF
-C22 a_n465_n100# a_n657_n100# 0.11fF
-C23 a_n273_n100# a_n657_n100# 0.05fF
-C24 a_n177_n100# a_207_n100# 0.05fF
-C25 a_n369_n100# a_n81_n100# 0.06fF
-C26 a_n749_n100# a_n561_n100# 0.11fF
-C27 a_207_n100# a_n705_n197# 0.08fF
-C28 a_207_n100# a_n81_n100# 0.06fF
-C29 a_303_n100# w_n887_n319# 0.02fF
-C30 a_303_n100# a_495_n100# 0.11fF
-C31 a_207_n100# a_399_n100# 0.11fF
-C32 a_207_n100# a_591_n100# 0.05fF
-C33 a_687_n100# a_399_n100# 0.06fF
-C34 a_n177_n100# a_n561_n100# 0.05fF
-C35 a_687_n100# a_591_n100# 0.29fF
-C36 a_n177_n100# a_n705_n197# 0.08fF
-C37 a_n705_n197# a_n561_n100# 0.08fF
-C38 a_15_n100# a_n369_n100# 0.05fF
-C39 a_n177_n100# a_n81_n100# 0.29fF
-C40 a_n81_n100# a_n705_n197# 0.08fF
-C41 a_15_n100# a_207_n100# 0.11fF
-C42 a_111_n100# a_207_n100# 0.29fF
-C43 a_n705_n197# a_399_n100# 0.08fF
-C44 a_591_n100# a_n705_n197# 0.08fF
-C45 w_n887_n319# a_n369_n100# 0.02fF
-C46 a_n369_n100# a_n465_n100# 0.29fF
-C47 a_n273_n100# a_n369_n100# 0.29fF
-C48 a_591_n100# a_399_n100# 0.11fF
-C49 w_n887_n319# a_207_n100# 0.02fF
-C50 w_n887_n319# a_n749_n100# 0.10fF
-C51 a_15_n100# a_n177_n100# 0.11fF
-C52 a_n465_n100# a_n749_n100# 0.06fF
-C53 a_15_n100# a_n705_n197# 0.08fF
-C54 a_207_n100# a_495_n100# 0.06fF
-C55 a_n177_n100# a_111_n100# 0.06fF
-C56 a_15_n100# a_n81_n100# 0.29fF
-C57 w_n887_n319# a_687_n100# 0.10fF
-C58 a_111_n100# a_n705_n197# 0.08fF
-C59 a_n369_n100# a_n657_n100# 0.06fF
-C60 a_111_n100# a_n81_n100# 0.11fF
-C61 a_687_n100# a_495_n100# 0.11fF
-C62 a_15_n100# a_399_n100# 0.05fF
-C63 a_n749_n100# a_n657_n100# 0.29fF
-C64 a_111_n100# a_399_n100# 0.06fF
-C65 w_n887_n319# a_n177_n100# 0.02fF
-C66 a_n177_n100# a_n465_n100# 0.06fF
-C67 a_n273_n100# a_n177_n100# 0.29fF
-C68 w_n887_n319# a_n561_n100# 0.04fF
-C69 a_n465_n100# a_n561_n100# 0.29fF
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C85 a_687_n100# VSUBS 0.03fF
C86 a_591_n100# VSUBS 0.03fF
C87 a_495_n100# VSUBS 0.03fF
@@ -2098,17 +2098,17 @@
+ m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
Xsky130_fd_pr__pfet_01v8_VCU74W_1 avss1p8 out out avdd1p8 out avdd1p8 out out avdd1p8
+ avdd1p8 avdd1p8 out m1_957_828# out avdd1p8 avdd1p8 avdd1p8 out avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
-C0 m1_957_828# iref 0.88fF
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-C2 avdd1p8 iref 0.29fF
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-C4 m1_957_828# out 1.52fF
-C5 avdd1p8 in 0.32fF
-C6 out in 1.16fF
-C7 avdd1p8 out 3.96fF
-C8 out avss1p8 -1.64fF
-C9 in avss1p8 1.94fF
-C10 avdd1p8 avss1p8 15.90fF
+C0 m1_957_828# avdd1p8 1.12fF
+C1 in m1_957_828# 0.52fF
+C2 m1_957_828# out 1.52fF
+C3 m1_957_828# iref 0.88fF
+C4 in avdd1p8 0.32fF
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+C10 in avss1p8 1.94fF
C11 m1_957_828# avss1p8 -34.25fF
C12 iref avss1p8 4.22fF
.ends
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@@ -2825,745 +2825,745 @@
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+C682 a_447_109# a_159_109# 0.06fF
+C683 a_543_n309# a_255_n309# 0.06fF
+C684 a_n1665_109# a_n1665_n309# 0.01fF
+C685 a_n705_109# a_n513_109# 0.11fF
+C686 a_n1473_n727# a_n1377_n727# 0.29fF
+C687 a_1695_109# a_1503_109# 0.11fF
+C688 a_255_n727# a_351_n727# 0.29fF
+C689 a_735_n727# a_351_n727# 0.05fF
+C690 a_1119_n309# a_735_n309# 0.05fF
+C691 a_1791_109# a_1887_109# 0.29fF
+C692 a_n1857_n309# a_n1857_109# 0.01fF
+C693 a_1599_109# a_1215_109# 0.05fF
+C694 a_n513_n309# a_n225_n309# 0.06fF
+C695 a_n129_n309# a_n321_n309# 0.11fF
+C696 a_543_527# a_543_109# 0.01fF
+C697 a_n993_n727# a_n993_n309# 0.01fF
+C698 a_1407_n727# a_1503_n727# 0.29fF
+C699 a_n225_109# a_n33_109# 0.11fF
+C700 a_255_n727# a_63_n727# 0.11fF
+C701 a_639_109# a_927_109# 0.06fF
+C702 a_1599_n309# a_1695_n309# 0.29fF
+C703 a_n1185_n309# a_n993_n309# 0.11fF
+C704 a_n225_527# a_n129_527# 0.29fF
+C705 a_1215_n309# a_1503_n309# 0.06fF
+C706 a_735_n309# a_927_n309# 0.11fF
+C707 a_1695_n727# a_1791_n727# 0.29fF
+C708 a_639_n309# a_735_n309# 0.29fF
+C709 a_n513_n727# a_n705_n727# 0.11fF
+C710 a_n1569_n727# a_n1281_n727# 0.06fF
+C711 a_351_109# a_639_109# 0.06fF
+C712 a_n1185_109# a_n1185_527# 0.01fF
+C713 a_n705_527# a_n705_109# 0.01fF
+C714 a_1599_109# a_1407_109# 0.11fF
+C715 a_543_527# a_447_527# 0.29fF
+C716 a_n417_n309# a_n225_n309# 0.11fF
+C717 a_1599_n727# a_1215_n727# 0.05fF
+C718 a_1311_109# a_927_109# 0.05fF
+C719 a_63_n309# a_63_n727# 0.01fF
+C720 a_447_n309# a_447_n727# 0.01fF
+C721 a_1407_n309# a_1791_n309# 0.05fF
+C722 a_n1281_527# a_n993_527# 0.06fF
+C723 a_n705_n727# a_n705_n309# 0.01fF
+C724 a_n417_n727# a_n801_n727# 0.05fF
+C725 a_n1857_527# a_n1949_527# 0.29fF
+C726 a_255_n309# a_351_n309# 0.29fF
+C727 a_735_n727# a_543_n727# 0.11fF
+C728 a_1791_109# a_1599_109# 0.11fF
+C729 a_255_n727# a_543_n727# 0.06fF
+C730 a_n417_109# a_n33_109# 0.05fF
+C731 a_159_n727# a_n129_n727# 0.06fF
+C732 a_n1949_n727# a_n1761_n727# 0.11fF
+C733 a_927_n727# a_1023_n727# 0.29fF
+C734 a_n1665_n309# a_n1665_n727# 0.01fF
+C735 a_n321_109# a_63_109# 0.05fF
+C736 a_255_527# a_n129_527# 0.05fF
+C737 a_159_n309# a_n225_n309# 0.05fF
+C738 a_n1473_n727# a_n1473_n309# 0.01fF
C739 a_1887_n727# w_n2087_n937# 0.12fF
C740 a_1791_n727# w_n2087_n937# 0.08fF
C741 a_1695_n727# w_n2087_n937# 0.06fF
@@ -3757,12 +3757,12 @@
+ out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8 out out out out avss1p8 out avss1p8
+ avss1p8 out out out out out avss1p8 avss1p8 out avss1p8 out avss1p8 out out avss1p8
+ avss1p8 avss1p8 avss1p8 avss1p8 out out out avss1p8 avss1p8 out sky130_fd_pr__nfet_01v8_lvt_CAF2P9
-C0 iref out 22.08fF
-C1 in out 10.03fF
-C2 in iref 0.11fF
-C3 out avdd1p8 9.98fF
-C4 in avdd1p8 2.17fF
-C5 iref m1_460_n1129# 2.64fF
+C0 iref m1_460_n1129# 2.64fF
+C1 out in 10.03fF
+C2 iref in 0.11fF
+C3 out iref 22.08fF
+C4 avdd1p8 in 2.17fF
+C5 avdd1p8 out 9.98fF
C6 iref avss1p8 18.70fF
C7 in avss1p8 -31.17fF
C8 out avss1p8 -28.37fF
@@ -3786,22 +3786,22 @@
+ VSUBS source_follower_buff_nmos_1/in source_follower_buff_nmos_1/m1_460_n1129# iref2
+ source_follower_buff_nmos_1/w_2049_850# source_follower_buff_nmos_1/w_2250_1287#
+ source_follower_buff_nmos_1/w_2250_355# source_follower_buff_nmos
-C0 avdd1p8 source_follower_buff_nmos_0/in 0.63fF
-C1 inn source_follower_buff_pmos_0/m1_957_828# 0.08fF
-C2 iref3 inn 0.01fF
-C3 source_follower_buff_nmos_0/in outn 0.11fF
-C4 source_follower_buff_nmos_1/w_2250_n1147# outp 0.09fF
-C5 avdd1p8 source_follower_buff_nmos_1/in 0.63fF
-C6 source_follower_buff_nmos_0/in inn -0.25fF
-C7 inp iref1 0.01fF
-C8 avdd1p8 outn 0.18fF
-C9 avdd1p8 inn 0.07fF
-C10 avdd1p8 source_follower_buff_nmos_0/w_2049_850# 0.16fF
-C11 avdd1p8 source_follower_buff_nmos_0/w_2250_1287# 0.18fF
-C12 source_follower_buff_nmos_1/in outp 0.11fF
-C13 inp source_follower_buff_nmos_1/in -0.25fF
-C14 avdd1p8 inp 0.07fF
-C15 inp source_follower_buff_pmos_1/m1_957_828# 0.08fF
+C0 source_follower_buff_nmos_1/in avdd1p8 0.63fF
+C1 inp avdd1p8 0.07fF
+C2 outn avdd1p8 0.18fF
+C3 outp source_follower_buff_nmos_1/w_2250_n1147# 0.09fF
+C4 inp source_follower_buff_pmos_1/m1_957_828# 0.08fF
+C5 inn source_follower_buff_nmos_0/in -0.25fF
+C6 source_follower_buff_nmos_0/w_2049_850# avdd1p8 0.16fF
+C7 outn source_follower_buff_nmos_0/in 0.11fF
+C8 inp source_follower_buff_nmos_1/in -0.25fF
+C9 inn source_follower_buff_pmos_0/m1_957_828# 0.08fF
+C10 outp source_follower_buff_nmos_1/in 0.11fF
+C11 source_follower_buff_nmos_0/w_2250_1287# avdd1p8 0.18fF
+C12 iref3 inn 0.01fF
+C13 inn avdd1p8 0.07fF
+C14 source_follower_buff_nmos_0/in avdd1p8 0.63fF
+C15 inp iref1 0.01fF
C16 iref2 VSUBS 11.84fF
C17 source_follower_buff_nmos_1/in VSUBS -32.98fF
C18 outp VSUBS 0.56fF
@@ -3850,7 +3850,7 @@
+ res_amp_sync_v2_0/clkp res_amp_sync_v2_0/rst res_amp_sync_v2
Xres_amp_lin_prog_0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363#
+ delay_reg2 avdd1p8 inp res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA
-+ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_lin_prog_0/res_amp_lin_0/vctrl res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out
+ res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_prog_0/res_amp_lin_0/clk
+ res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 res_amp_lin_prog_0/outp_cap
+ avss1p8 res_amp_lin_prog_0/outn_cap res_amp_lin_prog_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b
@@ -3877,59 +3877,59 @@
+ source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# source_follower_buff_diff_0/source_follower_buff_nmos_1/in
+ source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# res_amp_lin_prog_0/outn_cap
+ source_follower_buff_diff
-C0 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# avdd1p8 1.10fF
-C1 inn inp 1.68fF
-C2 res_amp_sync_v2_0/rst inn 0.09fF
-C3 iref0 res_amp_lin_prog_0/res_amp_lin_0/vctrl -0.03fF
-C4 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# iref4 0.13fF
-C5 res_amp_sync_v2_0/DFlipFlop_3/D avdd1p8 0.89fF
-C6 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/Q 0.44fF
-C7 source_follower_buff_diff_0/source_follower_buff_nmos_0/in avdd1p8 0.39fF
-C8 iref2 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# 0.12fF
-C9 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/D 0.08fF
-C10 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D 0.20fF
-C11 res_amp_lin_prog_0/clk avdd1p8 9.77fF
-C12 res_amp_sync_v2_0/DFlipFlop_1/D avdd1p8 0.29fF
-C13 delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.04fF
-C14 outn avdd1p8 0.30fF
-C15 delay_reg1 delay_reg2 0.23fF
-C16 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/nQ 0.20fF
-C17 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D 0.47fF
-C18 source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# outn 0.15fF
-C19 delay_reg2 avdd1p8 0.08fF
-C20 iref0 avdd1p8 -0.63fF
-C21 iref_reg2 avdd1p8 -0.57fF
-C22 res_amp_sync_v2_0/clkp clkn 0.06fF
-C23 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# iref1 0.10fF
-C24 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/Q 0.25fF
-C25 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/D 0.07fF
-C26 inp avdd1p8 0.46fF
-C27 res_amp_sync_v2_0/rst avdd1p8 0.80fF
-C28 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D 0.47fF
-C29 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD 0.25fF
-C30 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in res_amp_lin_prog_0/clk 0.48fF
-C31 outp avdd1p8 0.31fF
-C32 res_amp_lin_prog_0/outn_cap res_amp_sync_v2_0/rst 0.06fF
-C33 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# 0.06fF
-C34 inn avdd1p8 0.46fF
-C35 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD 0.28fF
-C36 iref0 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.02fF
-C37 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D 0.23fF
-C38 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/nQ 0.22fF
-C39 res_amp_lin_prog_0/res_amp_lin_0/vctrl avdd1p8 0.03fF
-C40 clkn avdd1p8 0.74fF
-C41 res_amp_sync_v2_0/clkp avdd1p8 1.19fF
-C42 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# iref3 0.10fF
-C43 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# avdd1p8 0.02fF
-C44 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# avdd1p8 0.02fF
-C45 iref_reg1 avdd1p8 0.05fF
-C46 delay_reg2 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out 0.03fF
-C47 delay_reg1 avdd1p8 0.04fF
-C48 res_amp_sync_v2_0/rst res_amp_lin_prog_0/outp_cap 0.13fF
-C49 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in 0.48fF
-C50 res_amp_sync_v2_0/rst inp 0.09fF
-C51 res_amp_lin_prog_0/clk clkn 0.07fF
-C52 source_follower_buff_diff_0/source_follower_buff_nmos_1/in avdd1p8 0.40fF
+C0 res_amp_sync_v2_0/DFlipFlop_3/D res_amp_lin_prog_0/clk 0.07fF
+C1 avdd1p8 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# 0.02fF
+C2 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD 0.25fF
+C3 res_amp_lin_prog_0/res_amp_lin_0/vctrl iref0 -0.03fF
+C4 delay_reg1 avdd1p8 0.04fF
+C5 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# avdd1p8 1.10fF
+C6 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D res_amp_lin_prog_0/clk 0.23fF
+C7 avdd1p8 res_amp_lin_prog_0/clk 9.77fF
+C8 avdd1p8 clkn 0.74fF
+C9 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out delay_reg2 0.03fF
+C10 inp res_amp_sync_v2_0/rst 0.09fF
+C11 avdd1p8 delay_reg2 0.08fF
+C12 res_amp_sync_v2_0/DFlipFlop_4/Q res_amp_lin_prog_0/clk 0.44fF
+C13 avdd1p8 source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.40fF
+C14 res_amp_sync_v2_0/clkp clkn 0.06fF
+C15 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD 0.28fF
+C16 res_amp_sync_v2_0/rst avdd1p8 0.80fF
+C17 delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.04fF
+C18 res_amp_sync_v2_0/rst res_amp_lin_prog_0/outp_cap 0.13fF
+C19 avdd1p8 res_amp_sync_v2_0/DFlipFlop_3/D 0.89fF
+C20 iref3 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# 0.10fF
+C21 inp avdd1p8 0.46fF
+C22 avdd1p8 res_amp_sync_v2_0/DFlipFlop_1/D 0.29fF
+C23 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/Q 0.25fF
+C24 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.48fF
+C25 res_amp_sync_v2_0/DFlipFlop_3/nQ res_amp_lin_prog_0/clk 0.20fF
+C26 res_amp_sync_v2_0/rst res_amp_lin_prog_0/outn_cap 0.06fF
+C27 outn source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# 0.15fF
+C28 avdd1p8 outp 0.31fF
+C29 iref_reg1 avdd1p8 0.05fF
+C30 res_amp_sync_v2_0/clkp avdd1p8 1.19fF
+C31 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# res_amp_lin_prog_0/clk 0.06fF
+C32 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# avdd1p8 0.02fF
+C33 avdd1p8 source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.39fF
+C34 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D res_amp_lin_prog_0/clk 0.20fF
+C35 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D res_amp_lin_prog_0/clk 0.47fF
+C36 iref0 avdd1p8 -0.63fF
+C37 iref2 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# 0.12fF
+C38 outn avdd1p8 0.30fF
+C39 iref0 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.02fF
+C40 iref4 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# 0.13fF
+C41 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D res_amp_lin_prog_0/clk 0.47fF
+C42 iref1 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# 0.10fF
+C43 res_amp_sync_v2_0/DFlipFlop_4/D res_amp_lin_prog_0/clk 0.08fF
+C44 res_amp_sync_v2_0/rst inn 0.09fF
+C45 res_amp_sync_v2_0/DFlipFlop_4/nQ res_amp_lin_prog_0/clk 0.22fF
+C46 res_amp_lin_prog_0/clk clkn 0.07fF
+C47 inp inn 1.68fF
+C48 delay_reg1 delay_reg2 0.23fF
+C49 res_amp_lin_prog_0/res_amp_lin_0/vctrl avdd1p8 0.03fF
+C50 avdd1p8 iref_reg2 -0.57fF
+C51 avdd1p8 inn 0.46fF
+C52 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in res_amp_lin_prog_0/clk 0.48fF
C53 iref2 avss1p8 12.17fF
C54 source_follower_buff_diff_0/source_follower_buff_nmos_1/in avss1p8 -32.88fF
C55 outp avss1p8 -1.74fF
@@ -3961,51 +3961,51 @@
C81 inn avss1p8 -6.68fF
C82 res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
C83 res_amp_lin_prog_0/outn_cap avss1p8 1.00fF
-C84 res_amp_lin_prog_0/res_amp_lin_0/clk avss1p8 4.30fF
-C85 res_amp_lin_prog_0/inverter_min_x4_0/out avss1p8 4.87fF
+C84 res_amp_lin_prog_0/inverter_min_x4_0/out avss1p8 4.87fF
+C85 res_amp_lin_prog_0/res_amp_lin_0/clk avss1p8 4.30fF
C86 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
-C87 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
-C88 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
-C89 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
-C90 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
-C91 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
-C92 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
-C93 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
-C94 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
-C95 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
-C96 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
-C97 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.04fF
-C98 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
-C99 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
-C100 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
-C101 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
-C102 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
-C103 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
-C104 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
-C105 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
-C106 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C87 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C88 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C89 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C90 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C91 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C92 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C93 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C94 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C95 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C96 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C97 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C98 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.04fF
+C99 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C100 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C101 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C102 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C103 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C104 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C105 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C106 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
C107 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
-C108 delay_reg0 avss1p8 2.90fF
-C109 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C108 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C109 delay_reg0 avss1p8 2.90fF
C110 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
-C111 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
-C112 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C111 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C112 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
C113 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
-C114 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
-C115 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
-C116 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
-C117 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
-C118 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
-C119 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C114 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C115 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C116 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C117 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C118 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C119 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
C120 delay_reg1 avss1p8 3.97fF
C121 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
-C122 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
-C123 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
-C124 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C122 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C123 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C124 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
C125 delay_reg2 avss1p8 11.33fF
-C126 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.04fF
-C127 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
-C128 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C126 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C127 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C128 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.04fF
C129 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
C130 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
C131 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
@@ -4014,272 +4014,67 @@
C134 res_amp_sync_v2_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
C135 res_amp_lin_prog_0/clk avss1p8 -6.90fF
C136 res_amp_sync_v2_0/inverter_min_x4_4/out avss1p8 5.85fF
-C137 res_amp_sync_v2_0/nand_logic_1/out avss1p8 1.70fF
-C138 res_amp_sync_v2_0/rst avss1p8 -3.03fF
-C139 res_amp_sync_v2_0/DFlipFlop_4/nQ avss1p8 0.48fF
-C140 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 -2.08fF
-C141 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# avss1p8 0.57fF
-C142 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD avss1p8 0.57fF
-C143 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D avss1p8 -1.73fF
-C144 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C137 res_amp_sync_v2_0/rst avss1p8 -3.03fF
+C138 res_amp_sync_v2_0/nand_logic_1/out avss1p8 1.70fF
+C139 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 -2.08fF
+C140 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C141 res_amp_sync_v2_0/DFlipFlop_4/nQ avss1p8 0.48fF
+C142 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D avss1p8 -1.73fF
+C143 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C144 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD avss1p8 0.57fF
C145 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
C146 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D avss1p8 0.96fF
C147 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
C148 res_amp_sync_v2_0/DFlipFlop_4/D avss1p8 1.83fF
C149 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD avss1p8 1.14fF
C150 res_amp_sync_v2_0/nand_logic_0/out avss1p8 1.20fF
-C151 res_amp_sync_v2_0/DFlipFlop_0/Q avss1p8 -4.73fF
-C152 res_amp_sync_v2_0/DFlipFlop_3/nQ avss1p8 0.48fF
-C153 res_amp_sync_v2_0/DFlipFlop_3/Q avss1p8 -2.94fF
-C154 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# avss1p8 0.57fF
-C155 clkn avss1p8 -7.50fF
-C156 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD avss1p8 0.57fF
-C157 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D avss1p8 -1.73fF
-C158 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# avss1p8 0.57fF
-C159 res_amp_sync_v2_0/clkp avss1p8 -28.00fF
-C160 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
-C161 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D avss1p8 0.96fF
-C162 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
-C163 res_amp_sync_v2_0/DFlipFlop_3/D avss1p8 1.33fF
+C151 res_amp_sync_v2_0/DFlipFlop_3/Q avss1p8 -2.94fF
+C152 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C153 clkn avss1p8 -7.50fF
+C154 res_amp_sync_v2_0/DFlipFlop_3/nQ avss1p8 0.48fF
+C155 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D avss1p8 -1.73fF
+C156 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C157 res_amp_sync_v2_0/clkp avss1p8 -28.00fF
+C158 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD avss1p8 0.57fF
+C159 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C160 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D avss1p8 0.96fF
+C161 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C162 res_amp_sync_v2_0/DFlipFlop_3/D avss1p8 1.33fF
+C163 avdd1p8 avss1p8 415.30fF
C164 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD avss1p8 1.14fF
-C165 avdd1p8 avss1p8 415.30fF
-C166 res_amp_sync_v2_0/DFlipFlop_2/nQ avss1p8 0.48fF
-C167 res_amp_sync_v2_0/DFlipFlop_2/Q avss1p8 -1.08fF
-C168 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# avss1p8 0.57fF
-C169 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD avss1p8 0.57fF
-C170 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D avss1p8 -1.73fF
-C171 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# avss1p8 0.57fF
-C172 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
-C173 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D avss1p8 0.96fF
-C174 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
-C175 res_amp_sync_v2_0/DFlipFlop_2/D avss1p8 -0.38fF
-C176 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD avss1p8 1.14fF
+C165 res_amp_sync_v2_0/DFlipFlop_2/Q avss1p8 -1.08fF
+C166 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C167 res_amp_sync_v2_0/DFlipFlop_2/nQ avss1p8 0.48fF
+C168 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D avss1p8 -1.73fF
+C169 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C170 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD avss1p8 0.57fF
+C171 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C172 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D avss1p8 0.96fF
+C173 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C174 res_amp_sync_v2_0/DFlipFlop_2/D avss1p8 -0.38fF
+C175 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD avss1p8 1.14fF
+C176 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# avss1p8 0.57fF
C177 res_amp_sync_v2_0/DFlipFlop_1/nQ avss1p8 0.48fF
-C178 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# avss1p8 0.57fF
-C179 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD avss1p8 0.57fF
-C180 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D avss1p8 -1.73fF
-C181 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# avss1p8 0.57fF
-C182 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
-C183 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D avss1p8 0.96fF
-C184 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
-C185 res_amp_sync_v2_0/DFlipFlop_1/D avss1p8 -1.02fF
-C186 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD avss1p8 1.14fF
-C187 res_amp_sync_v2_0/DFlipFlop_0/nQ avss1p8 0.48fF
-C188 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# avss1p8 0.57fF
-C189 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD avss1p8 0.57fF
-C190 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D avss1p8 -1.73fF
-C191 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C178 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D avss1p8 -1.73fF
+C179 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C180 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD avss1p8 0.57fF
+C181 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C182 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D avss1p8 0.96fF
+C183 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C184 res_amp_sync_v2_0/DFlipFlop_1/D avss1p8 -1.02fF
+C185 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD avss1p8 1.14fF
+C186 res_amp_sync_v2_0/DFlipFlop_0/Q avss1p8 -4.73fF
+C187 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C188 res_amp_sync_v2_0/DFlipFlop_0/nQ avss1p8 0.48fF
+C189 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D avss1p8 -1.73fF
+C190 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C191 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD avss1p8 0.57fF
C192 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
C193 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D avss1p8 0.96fF
C194 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
C195 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD avss1p8 1.14fF
.ends
-.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
-+ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
-+ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
-+ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
-+ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
-X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-C0 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
-C1 m3_2669_n13200# m3_7988_n13200# 2.73fF
-C2 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
-C3 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
-C4 m3_2669_n7900# m3_n2650_n7900# 2.73fF
-C5 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
-C6 m3_7988_2700# c1_n13188_n13100# 61.01fF
-C7 m3_7988_8000# c1_n13188_n13100# 60.75fF
-C8 m3_2669_2700# m3_n2650_2700# 2.73fF
-C9 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
-C10 m3_7988_2700# m3_7988_8000# 3.39fF
-C11 m3_n2650_8000# m3_2669_8000# 2.73fF
-C12 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
-C13 m3_n2650_8000# m3_n7969_8000# 2.73fF
-C14 m3_n13288_8000# c1_n13188_n13100# 58.36fF
-C15 m3_7988_n7900# m3_7988_n2600# 3.39fF
-C16 m3_n7969_8000# m3_n7969_2700# 3.28fF
-C17 m3_7988_n13200# c1_n13188_n13100# 60.75fF
-C18 m3_7988_n7900# m3_2669_n7900# 2.73fF
-C19 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
-C20 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
-C21 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
-C22 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
-C23 m3_2669_2700# c1_n13188_n13100# 58.86fF
-C24 m3_n7969_n2600# m3_n7969_2700# 3.28fF
-C25 m3_2669_n13200# m3_n2650_n13200# 2.73fF
-C26 m3_n2650_2700# m3_n2650_8000# 3.28fF
-C27 m3_2669_2700# m3_7988_2700# 2.73fF
-C28 m3_n2650_2700# m3_n7969_2700# 2.73fF
-C29 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
-C30 m3_7988_n2600# m3_2669_n2600# 2.73fF
-C31 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
-C32 m3_7988_n7900# c1_n13188_n13100# 61.01fF
-C33 m3_n2650_n2600# m3_2669_n2600# 2.73fF
-C34 m3_2669_n7900# m3_2669_n2600# 3.28fF
-C35 m3_n2650_8000# c1_n13188_n13100# 58.61fF
-C36 c1_n13188_n13100# m3_n7969_2700# 58.86fF
-C37 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
-C38 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
-C39 m3_7988_n7900# m3_7988_n13200# 3.39fF
-C40 c1_n13188_n13100# m3_2669_n2600# 58.86fF
-C41 c1_n13188_n13100# m3_n13288_2700# 58.61fF
-C42 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
-C43 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
-C44 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
-C45 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
-C46 m3_2669_n13200# m3_2669_n7900# 3.28fF
-C47 m3_n13288_8000# m3_n13288_2700# 3.28fF
-C48 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
-C49 m3_n2650_2700# m3_n2650_n2600# 3.28fF
-C50 m3_2669_2700# m3_2669_n2600# 3.28fF
-C51 m3_2669_8000# c1_n13188_n13100# 58.61fF
-C52 m3_n7969_8000# c1_n13188_n13100# 58.61fF
-C53 m3_7988_8000# m3_2669_8000# 2.73fF
-C54 m3_n13288_2700# m3_n13288_n2600# 3.28fF
-C55 m3_7988_n2600# c1_n13188_n13100# 61.01fF
-C56 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
-C57 m3_7988_n2600# m3_7988_2700# 3.39fF
-C58 m3_2669_n13200# c1_n13188_n13100# 58.61fF
-C59 m3_2669_n7900# c1_n13188_n13100# 58.86fF
-C60 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
-C61 m3_n2650_2700# c1_n13188_n13100# 58.86fF
-C62 m3_n7969_8000# m3_n13288_8000# 2.73fF
-C63 m3_n13288_2700# m3_n7969_2700# 2.73fF
-C64 m3_2669_2700# m3_2669_8000# 3.28fF
-C65 c1_n13188_n13100# VSUBS 2.51fF
-C66 m3_7988_n13200# VSUBS 12.57fF
-C67 m3_2669_n13200# VSUBS 12.37fF
-C68 m3_n2650_n13200# VSUBS 12.37fF
-C69 m3_n7969_n13200# VSUBS 12.37fF
-C70 m3_n13288_n13200# VSUBS 12.37fF
-C71 m3_7988_n7900# VSUBS 12.57fF
-C72 m3_2669_n7900# VSUBS 12.37fF
-C73 m3_n2650_n7900# VSUBS 12.37fF
-C74 m3_n7969_n7900# VSUBS 12.37fF
-C75 m3_n13288_n7900# VSUBS 12.37fF
-C76 m3_7988_n2600# VSUBS 12.57fF
-C77 m3_2669_n2600# VSUBS 12.37fF
-C78 m3_n2650_n2600# VSUBS 12.37fF
-C79 m3_n7969_n2600# VSUBS 12.37fF
-C80 m3_n13288_n2600# VSUBS 12.37fF
-C81 m3_7988_2700# VSUBS 12.57fF
-C82 m3_2669_2700# VSUBS 12.37fF
-C83 m3_n2650_2700# VSUBS 12.37fF
-C84 m3_n7969_2700# VSUBS 12.37fF
-C85 m3_n13288_2700# VSUBS 12.37fF
-C86 m3_7988_8000# VSUBS 12.57fF
-C87 m3_2669_8000# VSUBS 12.37fF
-C88 m3_n2650_8000# VSUBS 12.37fF
-C89 m3_n7969_8000# VSUBS 12.37fF
-C90 m3_n13288_8000# VSUBS 12.37fF
-.ends
-
-.subckt cap1_loop_filter VSUBS in out
-Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
-+ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
-C0 out in 2.17fF
-C1 in VSUBS -10.03fF
-C2 out VSUBS 62.40fF
-.ends
-
-.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
-+ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
-+ m3_n6469_n6400#
-X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 m3_n2150_n2100# m3_n2150_2200# 2.63fF
-C1 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
-C2 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
-C3 m3_2169_n6400# m3_n2150_2200# 1.75fF
-C4 m3_n6469_2200# c1_n6369_n6300# 38.10fF
-C5 c1_n2050_n6300# c1_2269_n6300# 1.99fF
-C6 m3_2169_n6400# m3_n2150_n2100# 1.75fF
-C7 m3_n6469_2200# m3_n2150_2200# 1.75fF
-C8 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
-C9 m3_2169_n6400# m3_n2150_n6400# 1.75fF
-C10 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
-C11 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
-C12 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
-C13 c1_n2050_n6300# m3_n2150_2200# 38.10fF
-C14 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
-C15 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
-C16 m3_2169_n6400# c1_2269_n6300# 121.67fF
-C17 m3_n6469_n2100# m3_n6469_2200# 2.63fF
-C18 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
-C19 c1_2269_n6300# VSUBS 0.16fF
-C20 c1_n2050_n6300# VSUBS 0.16fF
-C21 c1_n6369_n6300# VSUBS 0.16fF
-C22 m3_n2150_n6400# VSUBS 8.68fF
-C23 m3_n6469_n6400# VSUBS 8.68fF
-C24 m3_n2150_n2100# VSUBS 8.68fF
-C25 m3_n6469_n2100# VSUBS 8.68fF
-C26 m3_2169_n6400# VSUBS 26.86fF
-C27 m3_n2150_2200# VSUBS 8.68fF
-C28 m3_n6469_2200# VSUBS 8.68fF
-.ends
-
-.subckt cap2_loop_filter VSUBS in out
-Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
-C0 in out 8.08fF
-C1 in VSUBS -16.59fF
-C2 out VSUBS 13.00fF
-.ends
-
-.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
-X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
-C0 a_n573_n2724# w_n739_n2890# 1.98fF
-C1 a_n573_2292# w_n739_n2890# 1.98fF
-.ends
-
-.subckt res_loop_filter vss out in
-Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
-C0 out vss 3.87fF
-C1 in vss 3.02fF
-.ends
-
-.subckt loop_filter vc_pex in vss
-Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
-Xcap2_loop_filter_0 vss in vss cap2_loop_filter
-Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
-Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
-Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
-C0 vc_pex in 0.18fF
-C1 vc_pex vss -38.13fF
-C2 res_loop_filter_2/out vss 8.49fF
-C3 in vss -18.79fF
-.ends
-
.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
+ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
+ a_n1403_n486# a_2261_n486# a_n1861_n486#
@@ -4293,17 +4088,17 @@
X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
-C0 w_n2457_n634# a_1345_n486# 0.02fF
-C1 w_n2457_n634# a_n1861_n486# 0.02fF
-C2 a_n29_n486# w_n2457_n634# 0.02fF
-C3 a_2261_n486# w_n2457_n634# 0.02fF
-C4 w_n2457_n634# a_n945_n486# 0.02fF
-C5 a_887_n486# w_n2457_n634# 0.02fF
-C6 w_n2457_n634# a_n1403_n486# 0.02fF
-C7 w_n2457_n634# a_1803_n486# 0.02fF
-C8 a_n2319_n486# w_n2457_n634# 0.02fF
-C9 a_n487_n486# w_n2457_n634# 0.02fF
-C10 w_n2457_n634# a_429_n486# 0.02fF
+C0 w_n2457_n634# a_n1861_n486# 0.02fF
+C1 a_n945_n486# w_n2457_n634# 0.02fF
+C2 w_n2457_n634# a_n487_n486# 0.02fF
+C3 w_n2457_n634# a_n1403_n486# 0.02fF
+C4 a_429_n486# w_n2457_n634# 0.02fF
+C5 a_n29_n486# w_n2457_n634# 0.02fF
+C6 w_n2457_n634# a_2261_n486# 0.02fF
+C7 a_n2319_n486# w_n2457_n634# 0.02fF
+C8 w_n2457_n634# a_887_n486# 0.02fF
+C9 w_n2457_n634# a_1345_n486# 0.02fF
+C10 a_1803_n486# w_n2457_n634# 0.02fF
C11 a_2261_n486# VSUBS 0.03fF
C12 a_1803_n486# VSUBS 0.03fF
C13 a_1345_n486# VSUBS 0.03fF
@@ -4349,100 +4144,100 @@
X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
-C0 a_n1229_n75# a_n1041_n75# 0.08fF
-C1 a_1071_n75# a_1167_n75# 0.22fF
-C2 a_n753_n75# a_n1137_n75# 0.03fF
-C3 a_591_n75# a_783_n75# 0.08fF
-C4 a_1167_n75# a_879_n75# 0.05fF
-C5 a_n753_n75# a_n945_n75# 0.08fF
-C6 a_n1229_n75# a_n1137_n75# 0.22fF
-C7 a_n177_n75# a_111_n75# 0.05fF
-C8 a_n1229_n75# a_n945_n75# 0.05fF
-C9 a_n753_n75# a_n561_n75# 0.08fF
-C10 a_n465_n75# a_n369_n75# 0.22fF
-C11 a_n849_n75# a_n657_n75# 0.08fF
-C12 a_n849_n75# a_n1041_n75# 0.08fF
-C13 a_783_n75# a_399_n75# 0.03fF
-C14 a_1071_n75# a_975_n75# 0.22fF
-C15 a_879_n75# a_495_n75# 0.03fF
-C16 a_n1041_n75# a_n657_n75# 0.03fF
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+C3 a_n1137_n150# a_n1229_n150# 0.43fF
+C4 a_n465_n150# a_n273_n150# 0.16fF
+C5 a_1167_n150# a_879_n150# 0.10fF
+C6 a_n177_n150# a_n369_n150# 0.16fF
+C7 a_783_n150# a_1167_n150# 0.07fF
+C8 w_n1367_n369# a_1071_n150# 0.07fF
+C9 a_n465_n150# a_n81_n150# 0.07fF
+C10 a_495_n150# a_207_n150# 0.10fF
+C11 a_783_n150# a_399_n150# 0.07fF
+C12 a_207_n150# a_591_n150# 0.07fF
+C13 a_399_n150# a_687_n150# 0.10fF
+C14 a_n657_n150# a_n561_n150# 0.43fF
+C15 a_n849_n150# a_n1137_n150# 0.10fF
+C16 a_495_n150# a_399_n150# 0.43fF
+C17 a_n657_n150# a_n753_n150# 0.43fF
+C18 a_399_n150# a_591_n150# 0.16fF
+C19 a_n177_n150# a_n273_n150# 0.43fF
+C20 a_n1041_n150# a_n1229_n150# 0.16fF
+C21 a_n177_n150# a_207_n150# 0.07fF
+C22 a_n753_n150# a_n561_n150# 0.16fF
+C23 a_303_n150# a_687_n150# 0.07fF
+C24 a_n657_n150# a_n465_n150# 0.16fF
+C25 a_n945_n150# a_n1229_n150# 0.10fF
+C26 a_111_n150# a_n273_n150# 0.07fF
+C27 a_975_n150# a_879_n150# 0.43fF
+C28 a_303_n150# a_495_n150# 0.16fF
+C29 a_111_n150# a_207_n150# 0.43fF
+C30 a_303_n150# a_591_n150# 0.10fF
+C31 a_n177_n150# a_n81_n150# 0.43fF
+C32 a_n465_n150# a_n561_n150# 0.43fF
+C33 a_n465_n150# a_n753_n150# 0.10fF
+C34 a_111_n150# a_399_n150# 0.10fF
+C35 a_783_n150# a_975_n150# 0.16fF
+C36 a_975_n150# a_687_n150# 0.10fF
+C37 a_n849_n150# a_n1041_n150# 0.16fF
+C38 a_111_n150# a_n81_n150# 0.16fF
+C39 a_1071_n150# a_1167_n150# 0.43fF
+C40 a_n177_n150# a_15_n150# 0.16fF
+C41 a_975_n150# a_591_n150# 0.07fF
+C42 w_n1367_n369# a_1167_n150# 0.14fF
+C43 a_n849_n150# a_n945_n150# 0.43fF
+C44 a_783_n150# a_879_n150# 0.43fF
+C45 a_303_n150# a_111_n150# 0.16fF
+C46 a_879_n150# a_687_n150# 0.16fF
+C47 a_111_n150# a_15_n150# 0.43fF
+C48 a_n1041_n150# a_n1137_n150# 0.43fF
+C49 a_495_n150# a_879_n150# 0.07fF
+C50 a_879_n150# a_591_n150# 0.10fF
+C51 a_n177_n150# a_n561_n150# 0.07fF
+C52 a_n945_n150# a_n1137_n150# 0.16fF
+C53 a_783_n150# a_687_n150# 0.43fF
+C54 a_n369_n150# a_n273_n150# 0.43fF
+C55 a_783_n150# a_495_n150# 0.10fF
+C56 a_495_n150# a_687_n150# 0.16fF
+C57 a_783_n150# a_591_n150# 0.16fF
+C58 a_591_n150# a_687_n150# 0.43fF
+C59 a_n465_n150# a_n177_n150# 0.10fF
+C60 a_n849_n150# a_n657_n150# 0.16fF
+C61 a_495_n150# a_591_n150# 0.43fF
+C62 a_n81_n150# a_n369_n150# 0.10fF
+C63 a_n849_n150# a_n561_n150# 0.10fF
+C64 a_1071_n150# a_975_n150# 0.43fF
+C65 a_n849_n150# a_n753_n150# 0.43fF
+C66 w_n1367_n369# a_975_n150# 0.05fF
+C67 a_399_n150# a_207_n150# 0.16fF
+C68 a_n1041_n150# a_n945_n150# 0.43fF
+C69 a_1071_n150# a_879_n150# 0.16fF
+C70 a_15_n150# a_n369_n150# 0.07fF
+C71 a_n849_n150# a_n465_n150# 0.07fF
+C72 a_n81_n150# a_n273_n150# 0.16fF
+C73 a_495_n150# a_111_n150# 0.07fF
+C74 w_n1367_n369# a_879_n150# 0.04fF
+C75 a_n753_n150# a_n1137_n150# 0.07fF
+C76 a_n81_n150# a_207_n150# 0.10fF
+C77 a_n657_n150# a_n369_n150# 0.10fF
+C78 a_783_n150# a_1071_n150# 0.10fF
+C79 a_303_n150# a_207_n150# 0.43fF
+C80 a_n561_n150# a_n369_n150# 0.16fF
+C81 a_1071_n150# a_687_n150# 0.07fF
+C82 a_n753_n150# a_n369_n150# 0.07fF
+C83 a_15_n150# a_n273_n150# 0.10fF
+C84 a_n177_n150# a_111_n150# 0.10fF
+C85 a_15_n150# a_207_n150# 0.16fF
+C86 a_303_n150# a_399_n150# 0.43fF
+C87 a_n657_n150# a_n273_n150# 0.07fF
+C88 a_n657_n150# a_n1041_n150# 0.07fF
+C89 a_15_n150# a_399_n150# 0.07fF
+C90 a_303_n150# a_n81_n150# 0.07fF
+C91 a_n465_n150# a_n369_n150# 0.43fF
+C92 a_n849_n150# a_n1229_n150# 0.07fF
+C93 a_n561_n150# a_n273_n150# 0.10fF
+C94 a_n81_n150# a_15_n150# 0.43fF
+C95 a_975_n150# a_1167_n150# 0.16fF
+C96 a_n657_n150# a_n945_n150# 0.10fF
+C97 a_n1041_n150# a_n753_n150# 0.10fF
C98 a_1167_n150# VSUBS 0.03fF
C99 a_1071_n150# VSUBS 0.03fF
C100 a_975_n150# VSUBS 0.03fF
@@ -4917,7 +4712,7 @@
.ends
.subckt charge_pump vss pswitch nswitch out vdd biasp nUp Down w_2544_775# iref nDown
-+ Up w_1008_774#
++ Up w_1008_774# w_6648_570#
Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
+ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
@@ -4940,25 +4735,25 @@
Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
+ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
+ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
-C0 out vdd 6.66fF
-C1 Down nswitch 2.27fF
-C2 pswitch Up 0.70fF
-C3 biasp iref 0.80fF
-C4 Down nUp 0.25fF
-C5 vdd biasp 2.64fF
-C6 pswitch nswitch 0.06fF
-C7 Up nUp 0.15fF
-C8 pswitch nUp 5.66fF
-C9 out pswitch 4.91fF
-C10 out nswitch 1.28fF
-C11 pswitch biasp 3.11fF
-C12 Down nDown 0.13fF
-C13 out nUp 0.31fF
-C14 biasp nswitch 0.03fF
-C15 pswitch vdd 3.98fF
-C16 iref nswitch 1.91fF
-C17 vdd nswitch 0.07fF
-C18 nswitch nDown 0.31fF
+C0 nUp Up 0.15fF
+C1 nswitch pswitch 0.06fF
+C2 out pswitch 4.91fF
+C3 vdd biasp 2.64fF
+C4 nswitch biasp 0.03fF
+C5 nswitch iref 1.91fF
+C6 Down nDown 0.13fF
+C7 nUp Down 0.25fF
+C8 pswitch biasp 3.11fF
+C9 pswitch Up 0.70fF
+C10 nswitch nDown 0.31fF
+C11 out nUp 0.31fF
+C12 pswitch nUp 5.66fF
+C13 nswitch vdd 0.07fF
+C14 vdd out 6.66fF
+C15 iref biasp 0.80fF
+C16 vdd pswitch 3.98fF
+C17 nswitch Down 2.27fF
+C18 nswitch out 1.28fF
C19 vdd vss 35.71fF
C20 Down vss 4.77fF
C21 Up vss 1.17fF
@@ -4975,10 +4770,10 @@
+ a_n125_n42# a_63_n42#
X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-C0 a_n63_n68# a_33_n68# 0.02fF
-C1 a_n33_n42# a_n125_n42# 0.12fF
-C2 a_n33_n42# a_63_n42# 0.12fF
-C3 a_n125_n42# a_63_n42# 0.05fF
+C0 a_63_n42# a_n125_n42# 0.05fF
+C1 a_n125_n42# a_n33_n42# 0.12fF
+C2 a_n63_n68# a_33_n68# 0.02fF
+C3 a_63_n42# a_n33_n42# 0.12fF
C4 a_63_n42# w_n263_n252# 0.09fF
C5 a_n33_n42# w_n263_n252# 0.07fF
C6 a_n125_n42# w_n263_n252# 0.09fF
@@ -4990,13 +4785,13 @@
+ w_n263_n303# a_n33_n84#
X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_n33_n84# a_n125_n84# 0.24fF
-C1 a_n125_n84# a_63_n84# 0.09fF
-C2 a_n33_n84# w_n263_n303# 0.07fF
-C3 a_33_n110# a_n63_n110# 0.02fF
-C4 w_n263_n303# a_63_n84# 0.10fF
-C5 a_n125_n84# w_n263_n303# 0.10fF
-C6 a_n33_n84# a_63_n84# 0.24fF
+C0 a_63_n84# a_n33_n84# 0.24fF
+C1 a_63_n84# a_n125_n84# 0.09fF
+C2 a_63_n84# w_n263_n303# 0.10fF
+C3 a_n33_n84# a_n125_n84# 0.24fF
+C4 a_n33_n84# w_n263_n303# 0.07fF
+C5 a_33_n110# a_n63_n110# 0.02fF
+C6 w_n263_n303# a_n125_n84# 0.10fF
C7 a_63_n84# VSUBS 0.03fF
C8 a_n33_n84# VSUBS 0.03fF
C9 a_n125_n84# VSUBS 0.03fF
@@ -5008,82 +4803,329 @@
.subckt inverter_min_x2 in out vss vdd
Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
-C0 vdd in 0.01fF
+C0 out vdd 0.15fF
C1 out in 0.30fF
-C2 out vdd 0.15fF
+C2 in vdd 0.01fF
C3 vdd vss 2.93fF
C4 out vss 0.66fF
C5 in vss 0.72fF
.ends
-.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
-+ out_div o2 nout_div clock_inverter_0/inverter_cp_x1_0/out
+.subckt div_by_2 vss vdd nout_div clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2
++ o1 CLK out_div o2 clock_inverter_0/inverter_cp_x1_0/out
XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
-+ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD
+ out_div DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# nout_div
+ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_0/nCLK DFlipFlop
++ DFlipFlop
Xinverter_min_x4_1 vdd o2 vss nCLK_2 inverter_min_x4
Xinverter_min_x4_0 vdd o1 vss CLK_2 inverter_min_x4
Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
+ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
-C0 nout_div vdd 0.16fF
-C1 o1 vdd 0.14fF
-C2 o2 vdd 0.14fF
-C3 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
-C4 nout_div out_div 0.22fF
-C5 DFlipFlop_0/CLK vdd 0.40fF
-C6 DFlipFlop_0/nCLK nout_div 0.43fF
-C7 o1 out_div 0.01fF
-C8 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
-C9 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
-C10 nout_div DFlipFlop_0/latch_diff_1/m1_657_280# 0.21fF
-C11 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
-C12 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
-C13 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
-C14 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
-C15 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
-C16 o1 CLK_2 0.11fF
-C17 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/nD 0.11fF
-C18 o2 nCLK_2 0.11fF
-C19 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
-C20 vdd out_div 0.03fF
-C21 DFlipFlop_0/nCLK vdd 0.30fF
-C22 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
-C23 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
-C24 nout_div DFlipFlop_0/CLK 0.42fF
-C25 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
-C26 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
-C27 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
-C28 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
-C29 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
-C30 CLK_2 vdd 0.08fF
-C31 vdd nCLK_2 0.08fF
-C32 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
-C33 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
-C34 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C0 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C1 out_div vdd 0.03fF
+C2 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
+C3 DFlipFlop_0/latch_diff_0/nD nout_div 0.07fF
+C4 vdd DFlipFlop_0/CLK 0.40fF
+C5 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C6 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C7 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C8 o1 out_div 0.01fF
+C9 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/CLK -0.48fF
+C10 DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.29fF
+C11 o2 vdd 0.14fF
+C12 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C13 out_div nout_div 0.22fF
+C14 DFlipFlop_0/nCLK vdd 0.30fF
+C15 DFlipFlop_0/CLK nout_div 0.42fF
+C16 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C17 vdd CLK_2 0.08fF
+C18 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C19 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C20 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C21 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
+C22 o2 nCLK_2 0.11fF
+C23 DFlipFlop_0/latch_diff_0/D nout_div 0.09fF
+C24 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C25 DFlipFlop_0/nCLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.46fF
+C26 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
+C27 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C28 vdd nCLK_2 0.08fF
+C29 o1 vdd 0.14fF
+C30 vdd nout_div 0.16fF
+C31 DFlipFlop_0/nCLK nout_div 0.43fF
+C32 o1 CLK_2 0.11fF
+C33 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C34 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
C35 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C36 DFlipFlop_0/CLK vss 1.03fF
C37 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
C38 CLK vss 3.27fF
C39 DFlipFlop_0/nCLK vss 1.76fF
-C40 o1 vss 2.21fF
-C41 CLK_2 vss 1.08fF
-C42 o2 vss 2.21fF
-C43 nCLK_2 vss 1.08fF
+C40 CLK_2 vss 1.08fF
+C41 o1 vss 2.21fF
+C42 nCLK_2 vss 1.08fF
+C43 o2 vss 2.21fF
C44 out_div vss -0.77fF
C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
-C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
-C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C46 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C47 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C48 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
C50 DFlipFlop_0/latch_diff_0/D vss 0.96fF
C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
C52 nout_div vss 4.41fF
-C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
-C54 vdd vss 64.43fF
+C53 vdd vss 64.43fF
+C54 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C1 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C2 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C3 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C4 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C5 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C6 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C7 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C8 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C9 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C10 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C11 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C12 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C13 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C14 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C15 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C16 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C17 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C18 m3_7988_2700# m3_2669_2700# 2.73fF
+C19 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C20 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C21 m3_n2650_2700# m3_2669_2700# 2.73fF
+C22 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C23 m3_2669_8000# m3_2669_2700# 3.28fF
+C24 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C25 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C26 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C27 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C28 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C29 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C30 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C31 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C32 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C33 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C34 m3_7988_n2600# m3_7988_2700# 3.39fF
+C35 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C36 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C37 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C38 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C39 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C40 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C41 m3_7988_n2600# m3_7988_n7900# 3.39fF
+C42 m3_n7969_2700# c1_n13188_n13100# 58.86fF
+C43 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C44 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C45 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C46 m3_2669_2700# m3_2669_n2600# 3.28fF
+C47 m3_n2650_n2600# m3_n2650_n7900# 3.28fF
+C48 m3_n13288_n2600# c1_n13188_n13100# 58.61fF
+C49 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C50 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C51 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C52 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C53 m3_n7969_2700# m3_n7969_8000# 3.28fF
+C54 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C55 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C56 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C57 m3_2669_8000# m3_n2650_8000# 2.73fF
+C58 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C59 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C60 m3_7988_2700# m3_7988_8000# 3.39fF
+C61 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C62 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C63 m3_7988_8000# m3_2669_8000# 2.73fF
+C64 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 in out 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 c1_n4209_n4150# c1_110_n4150# 1.32fF
+C1 m3_n4309_n4250# m3_10_n4250# 1.75fF
+C2 c1_n4209_n4150# m3_n4309_50# 38.10fF
+C3 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C4 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C5 c1_110_n4150# m3_10_n4250# 81.11fF
+C6 m3_n4309_50# m3_10_n4250# 1.75fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 in out 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n2150_2200# m3_n6469_2200# 1.75fF
+C1 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C2 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C3 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C4 c1_n6369_n6300# m3_n6469_2200# 38.10fF
+C5 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
+C6 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
+C7 m3_n2150_2200# m3_n2150_n2100# 2.63fF
+C8 c1_2269_n6300# m3_2169_n6400# 121.67fF
+C9 m3_n2150_2200# m3_2169_n6400# 1.75fF
+C10 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C11 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C12 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C13 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C14 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
+C15 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C16 c1_2269_n6300# c1_n2050_n6300# 1.99fF
+C17 m3_n2150_2200# c1_n2050_n6300# 38.10fF
+C18 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 in out 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_n88_n300# a_n118_n388# 0.11fF
+C1 a_n88_n300# a_30_n300# 0.61fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss cap3_loop_filter_0/in
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 cap3_loop_filter_0/in in 0.79fF
+C1 in D0_cap 0.07fF
+C2 vc_pex in 0.18fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
.ends
.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
@@ -5092,9 +5134,9 @@
X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
-C0 a_n129_n600# a_n221_n600# 7.87fF
-C1 a_n221_n600# a_n257_n777# 0.25fF
-C2 a_n129_n600# a_n257_n777# 0.29fF
+C0 a_n257_n777# a_n221_n600# 0.25fF
+C1 a_n221_n600# a_n129_n600# 7.87fF
+C2 a_n257_n777# a_n129_n600# 0.29fF
C3 a_n129_n600# VSUBS 0.10fF
C4 a_n221_n600# VSUBS 0.25fF
C5 a_n257_n777# VSUBS 1.05fF
@@ -5106,15 +5148,15 @@
X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
-C0 a_n129_n300# a_n221_n300# 4.05fF
-C1 a_n257_n404# a_n221_n300# 0.21fF
-C2 a_n129_n300# a_n257_n404# 0.30fF
+C0 a_n221_n300# a_n129_n300# 4.05fF
+C1 a_n257_n404# a_n129_n300# 0.30fF
+C2 a_n257_n404# a_n221_n300# 0.21fF
C3 a_n129_n300# w_n257_n327# 0.11fF
C4 a_n221_n300# w_n257_n327# 0.25fF
C5 a_n257_n404# w_n257_n327# 1.11fF
.ends
-.subckt buffer_salida a_678_n100# out in a_3996_n100# vss vdd
+.subckt buffer_salida a_678_n100# a_3996_n100# out vdd in vss
Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
@@ -5261,25 +5303,982 @@
Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
-C0 vdd in 0.02fF
-C1 vdd a_678_n100# 0.08fF
-C2 a_678_n100# a_3996_n100# 6.52fF
-C3 vdd a_3996_n100# 3.68fF
-C4 out vdd 47.17fF
-C5 out a_3996_n100# 55.19fF
-C6 a_678_n100# in 0.81fF
-C7 a_3996_n100# vss 49.53fF
-C8 vdd vss 20.93fF
-C9 out vss 35.17fF
+C0 vdd a_678_n100# 0.08fF
+C1 a_678_n100# a_3996_n100# 6.52fF
+C2 vdd a_3996_n100# 3.68fF
+C3 vdd out 47.17fF
+C4 in a_678_n100# 0.81fF
+C5 vdd in 0.02fF
+C6 out a_3996_n100# 55.19fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
C10 a_678_n100# vss 13.08fF
C11 in vss 0.87fF
.ends
+.subckt trans_gate_mux2to8 in vss out en_pos en_neg vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss en_neg in out out vdd en_neg en_neg in sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 en_pos vss en_pos in out out en_pos in sky130_fd_pr__nfet_01v8_BHR94T
+C0 in vdd 0.05fF
+C1 out en_neg 0.07fF
+C2 vdd en_neg 0.01fF
+C3 out en_pos 0.27fF
+C4 in en_neg 0.28fF
+C5 in en_pos 0.07fF
+C6 out vdd 0.68fF
+C7 en_pos en_neg 0.04fF
+C8 out in 0.36fF
+C9 vdd vss 2.75fF
+C10 en_pos vss 0.30fF
+C11 in vss 1.53fF
+C12 out vss 0.88fF
+C13 en_neg vss 0.31fF
+.ends
+
+.subckt mux2to1 vss select_0_neg in_a out_a_0 out_a_1 select_0 vdd
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 vdd out_a_1 0.09fF
+C1 select_0 in_a 0.31fF
+C2 select_0 select_0_neg 0.17fF
+C3 out_a_0 vdd 0.09fF
+C4 in_a select_0_neg 0.11fF
+C5 select_0 vdd 0.04fF
+C6 in_a vdd 0.14fF
+C7 select_0 out_a_1 0.14fF
+C8 in_a out_a_1 0.08fF
+C9 in_a out_a_0 0.08fF
+C10 select_0_neg out_a_0 0.05fF
+C11 out_a_1 vss 1.03fF
+C12 vdd vss 6.09fF
+C13 select_0_neg vss 1.12fF
+C14 in_a vss 2.43fF
+C15 out_a_0 vss 1.03fF
+C16 select_0 vss 1.03fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_194_125# A 0.18fF
+C1 A VPWR 0.15fF
+C2 a_158_392# a_194_125# 0.06fF
+C3 a_194_125# VPWR 0.33fF
+C4 a_194_125# X 0.29fF
+C5 X VPWR 0.07fF
+C6 A VGND 0.31fF
+C7 a_194_125# VGND 0.25fF
+C8 VGND VPWR 0.01fF
+C9 X VGND 0.28fF
+C10 A B 0.28fF
+C11 VPWR VPB 0.06fF
+C12 a_194_125# B 0.57fF
+C13 VPWR B 0.09fF
+C14 A a_355_368# 0.02fF
+C15 a_194_125# a_355_368# 0.51fF
+C16 VPWR a_355_368# 0.37fF
+C17 X B 0.13fF
+C18 VGND B 0.10fF
+C19 X a_355_368# 0.17fF
+C20 B a_355_368# 0.08fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 VPWR A 0.07fF
+C1 A a_56_136# 0.17fF
+C2 VPWR a_56_136# 0.57fF
+C3 VGND B 0.03fF
+C4 VGND X 0.15fF
+C5 VPWR VPB 0.04fF
+C6 A B 0.08fF
+C7 VPWR B 0.02fF
+C8 X VPWR 0.20fF
+C9 a_56_136# B 0.30fF
+C10 X a_56_136# 0.26fF
+C11 VGND A 0.21fF
+C12 VGND a_56_136# 0.06fF
+C13 X B 0.02fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 a_63_368# A 0.28fF
+C1 X A 0.02fF
+C2 B A 0.10fF
+C3 VPWR a_63_368# 0.29fF
+C4 VPWR X 0.18fF
+C5 VPWR B 0.01fF
+C6 X a_63_368# 0.33fF
+C7 a_63_368# B 0.14fF
+C8 VPWR VPB 0.04fF
+C9 a_63_368# VGND 0.27fF
+C10 X VGND 0.16fF
+C11 B VGND 0.11fF
+C12 VPWR A 0.05fF
+C13 a_63_368# a_152_368# 0.03fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/latch_diff_1/nD vss vdd DFlipFlop_2/latch_diff_0/nD Q0 Q1 CLK DFlipFlop_0/Q
++ DFlipFlop_2/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ nQ0 DFlipFlop_3/latch_diff_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/nD DFlipFlop_1/latch_diff_0/D DFlipFlop_2/latch_diff_0/m1_657_280#
++ CLK_5 Q1_shift nQ2 DFlipFlop_2/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D DFlipFlop_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/latch_diff_0/nD sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_0/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_2/nQ DFlipFlop_3/latch_diff_0/nD DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_2/latch_diff_0/D DFlipFlop_0/latch_diff_0/D sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368# DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_1/a_143_136# sky130_fd_sc_hs__or2_1_0/a_152_368# sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_3/nQ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 nCLK DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/D
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss vdd DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ nCLK DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss vdd DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ CLK DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# Q1 DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 vdd nCLK 0.34fF
+C1 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C2 DFlipFlop_2/nQ nCLK 0.09fF
+C3 DFlipFlop_1/D Q1 0.03fF
+C4 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C5 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C6 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C7 CLK vdd 0.41fF
+C8 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C9 DFlipFlop_2/latch_diff_0/D Q1 0.42fF
+C10 CLK DFlipFlop_2/nQ 0.13fF
+C11 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
+C12 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK 0.14fF
+C13 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C14 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.08fF
+C15 DFlipFlop_0/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C16 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C17 Q1 nCLK -0.01fF
+C18 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C19 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C20 vdd DFlipFlop_0/D 0.19fF
+C21 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C22 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C23 DFlipFlop_2/D Q0 0.25fF
+C24 DFlipFlop_0/Q Q0 0.21fF
+C25 DFlipFlop_3/latch_diff_1/nD nCLK 0.09fF
+C26 nQ0 DFlipFlop_1/D 0.12fF
+C27 DFlipFlop_3/nQ nCLK 0.02fF
+C28 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C29 nQ2 DFlipFlop_0/Q 0.09fF
+C30 CLK Q1 -0.10fF
+C31 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C32 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C33 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
+C34 nQ2 Q0 0.23fF
+C35 vdd Q1_shift 0.10fF
+C36 sky130_fd_sc_hs__and2_1_1/a_143_136# CLK 0.03fF
+C37 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C38 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C39 CLK DFlipFlop_3/nQ 0.01fF
+C40 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C41 Q1 DFlipFlop_0/D 0.13fF
+C42 DFlipFlop_0/latch_diff_0/D Q0 0.42fF
+C43 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C44 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C45 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C46 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C47 nQ0 nCLK 0.09fF
+C48 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C49 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C50 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C51 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C52 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q1 0.20fF
+C53 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
+C54 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C55 DFlipFlop_2/D vdd 0.07fF
+C56 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C57 Q1 Q1_shift 0.36fF
+C58 nQ0 CLK 0.19fF
+C59 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C60 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C61 DFlipFlop_1/D nCLK 0.14fF
+C62 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C63 vdd Q0 5.33fF
+C64 nQ2 vdd 0.04fF
+C65 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C66 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C67 DFlipFlop_3/nQ Q1_shift 0.04fF
+C68 DFlipFlop_2/latch_diff_0/D nCLK 0.11fF
+C69 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
+C70 DFlipFlop_1/D CLK 0.21fF
+C71 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C72 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C73 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
+C74 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.08fF
+C75 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q0 0.42fF
+C76 DFlipFlop_2/D Q1 0.10fF
+C77 DFlipFlop_0/Q Q1 0.13fF
+C78 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C79 Q1 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C80 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C81 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C82 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
+C83 Q1 Q0 9.65fF
+C84 nQ2 Q1 0.07fF
+C85 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C86 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C87 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C88 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C89 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C90 DFlipFlop_2/nQ vdd 0.02fF
+C91 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C92 sky130_fd_sc_hs__xor2_1_0/a_355_368# Q0 0.03fF
+C93 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C94 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C95 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C96 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C97 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C98 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C99 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C100 nQ0 Q0 0.33fF
+C101 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C102 vdd Q1 9.49fF
+C103 nQ2 nQ0 0.03fF
+C104 DFlipFlop_2/nQ Q1 0.31fF
+C105 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C106 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C107 DFlipFlop_3/latch_diff_0/m1_657_280# Q1 0.28fF
+C108 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C109 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C110 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C111 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C112 vdd DFlipFlop_3/nQ 0.02fF
+C113 DFlipFlop_2/latch_diff_1/m1_657_280# Q1 0.03fF
+C114 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C115 DFlipFlop_1/D Q0 0.07fF
+C116 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C117 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C118 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C119 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C120 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C121 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C122 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C123 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C124 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C125 DFlipFlop_2/D nCLK 0.41fF
+C126 DFlipFlop_0/Q nCLK 0.11fF
+C127 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C128 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C129 nQ0 vdd 0.11fF
+C130 sky130_fd_sc_hs__and2_1_0/a_56_136# Q1 0.14fF
+C131 nQ0 DFlipFlop_1/latch_diff_0/m1_657_280# 0.25fF
+C132 DFlipFlop_3/latch_diff_1/nD Q1 1.24fF
+C133 Q1 DFlipFlop_3/nQ 0.10fF
+C134 nCLK Q0 0.20fF
+C135 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C136 nQ2 nCLK 0.10fF
+C137 DFlipFlop_2/D CLK 0.14fF
+C138 CLK DFlipFlop_0/Q 0.08fF
+C139 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C140 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C141 Q1 DFlipFlop_3/latch_diff_1/m1_657_280# 0.28fF
+C142 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C143 CLK_5 vdd 0.15fF
+C144 CLK Q0 0.08fF
+C145 DFlipFlop_1/D vdd 0.25fF
+C146 nQ2 CLK 0.17fF
+C147 nQ0 Q1 0.06fF
+C148 DFlipFlop_1/latch_diff_0/nD CLK 0.08fF
+C149 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C150 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C151 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C152 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C153 DFlipFlop_0/D Q0 0.39fF
+C154 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C155 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C156 DFlipFlop_0/latch_diff_1/nD Q1 0.10fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 Q1_shift vss -0.29fF
+C162 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C163 DFlipFlop_3/nQ vss 0.52fF
+C164 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C165 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C166 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C168 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 Q1 vss 8.55fF
+C172 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C173 DFlipFlop_2/nQ vss 0.50fF
+C174 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C175 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C176 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C177 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C178 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 Q0 vss 0.53fF
+C183 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C184 nQ0 vss 3.42fF
+C185 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C186 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C187 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C188 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 DFlipFlop_0/Q vss -0.94fF
+C194 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C195 nCLK vss 0.96fF
+C196 nQ2 vss 2.05fF
+C197 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C198 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C199 CLK vss 0.20fF
+C200 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C202 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 vdd vss 146.76fF
+C206 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt mux2to4 vss out_b_1 vdd select_0 select_0_neg in_a out_a_0 out_a_1 out_b_0
++ in_b
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_b vss out_b_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_3 in_b vss out_b_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 in_b select_0_neg 0.10fF
+C1 out_b_0 out_a_1 0.88fF
+C2 select_0_neg out_a_0 0.05fF
+C3 in_b vdd 0.17fF
+C4 select_0_neg select_0 0.49fF
+C5 vdd out_a_0 0.09fF
+C6 out_b_0 in_a 0.11fF
+C7 in_a out_a_1 0.08fF
+C8 vdd select_0 0.08fF
+C9 select_0_neg vdd 0.08fF
+C10 out_b_0 in_b 0.08fF
+C11 in_b out_a_1 0.08fF
+C12 in_b out_b_1 0.08fF
+C13 out_b_0 select_0 0.03fF
+C14 out_a_1 select_0 0.18fF
+C15 out_b_0 select_0_neg -0.13fF
+C16 select_0_neg out_a_1 0.12fF
+C17 in_a out_a_0 0.08fF
+C18 select_0 out_b_1 0.14fF
+C19 in_a select_0 0.31fF
+C20 out_b_0 vdd 0.15fF
+C21 vdd out_a_1 0.16fF
+C22 in_a select_0_neg 0.22fF
+C23 vdd out_b_1 0.09fF
+C24 in_a vdd 0.17fF
+C25 in_b select_0 0.24fF
+C26 out_b_1 vss 1.03fF
+C27 in_b vss 2.46fF
+C28 out_b_0 vss 0.84fF
+C29 out_a_1 vss 0.32fF
+C30 vdd vss 12.14fF
+C31 select_0_neg vss 2.57fF
+C32 in_a vss 2.46fF
+C33 out_a_0 vss 1.03fF
+C34 select_0 vss 2.24fF
+.ends
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X a_304_74# a_443_74# a_524_368#
++ a_27_112#
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 a_27_112# A0 0.07fF
+C1 VPWR VGND 0.02fF
+C2 VPWR A1 0.01fF
+C3 a_223_368# a_304_74# 0.05fF
+C4 VPWR a_304_74# 0.13fF
+C5 a_443_74# A1 0.07fF
+C6 VGND S 0.07fF
+C7 S A1 0.10fF
+C8 VGND A0 0.02fF
+C9 A1 A0 0.31fF
+C10 a_443_74# a_304_74# 0.12fF
+C11 X a_27_112# 0.08fF
+C12 VGND a_27_112# 0.18fF
+C13 a_27_112# A1 0.18fF
+C14 S a_304_74# 0.18fF
+C15 A0 a_304_74# 0.23fF
+C16 a_524_368# a_27_112# 0.06fF
+C17 a_27_112# a_304_74# 0.58fF
+C18 VPWR VPB 0.06fF
+C19 VPWR S 0.05fF
+C20 VGND X 0.11fF
+C21 X A1 0.02fF
+C22 VGND A1 0.09fF
+C23 a_27_112# a_223_368# 0.09fF
+C24 VPWR a_27_112# 0.99fF
+C25 X a_304_74# 0.29fF
+C26 a_226_74# a_304_74# 0.08fF
+C27 VGND a_304_74# 0.58fF
+C28 A1 a_304_74# 0.69fF
+C29 S A0 0.04fF
+C30 VPWR X 0.28fF
+C31 a_27_112# VPB 0.01fF
+C32 S a_27_112# 0.22fF
+C33 VGND VNB 0.88fF
+C34 X VNB 0.25fF
+C35 VPWR VNB 0.89fF
+C36 A1 VNB 0.37fF
+C37 A0 VNB 0.23fF
+C38 S VNB 0.34fF
+C39 VPB VNB 0.87fF
+C40 a_304_74# VNB 0.36fF
+C41 a_27_112# VNB 0.65fF
+.ends
+
+.subckt prescaler_23 nCLK vss DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_2/latch_diff_0/nD
++ vdd DFlipFlop_2/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ CLK_23 DFlipFlop_2/latch_diff_0/m1_657_280# CLK DFlipFlop_2/latch_diff_1/nD DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_1/D DFlipFlop_2/latch_diff_0/D
++ MC DFlipFlop_0/latch_diff_0/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q2
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1_0/a_304_74# sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__mux2_1_0/a_524_368#
++ sky130_fd_sc_hs__mux2_1_0/a_27_112# sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ nCLK DFlipFlop_0/latch_diff_0/nD
++ Q1 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# nCLK_23 DFlipFlop_0/latch_diff_0/D
++ CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ CLK DFlipFlop_2/latch_diff_0/nD
++ Q2_d DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# Q2 DFlipFlop_2/latch_diff_0/D
++ nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss vdd DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK_23 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q2 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1_0/a_143_136# sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1_1/a_152_368#
++ sky130_fd_sc_hs__or2_1_1/a_63_368# sky130_fd_sc_hs__or2_1
+C0 CLK DFlipFlop_1/latch_diff_1/nD 0.11fF
+C1 nCLK DFlipFlop_2/nQ 0.02fF
+C2 DFlipFlop_2/latch_diff_1/nD CLK 0.19fF
+C3 sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__and2_1_0/a_56_136# 0.07fF
+C4 nCLK_23 DFlipFlop_0/latch_diff_1/nD 0.02fF
+C5 MC Q1 0.29fF
+C6 DFlipFlop_0/nQ Q1 -0.02fF
+C7 sky130_fd_sc_hs__or2_1_0/X vdd 0.03fF
+C8 CLK Q1 -0.07fF
+C9 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C10 nCLK DFlipFlop_1/latch_diff_1/nD 0.18fF
+C11 nCLK DFlipFlop_2/latch_diff_1/nD 0.12fF
+C12 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1 0.01fF
+C13 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.31fF
+C14 DFlipFlop_2/latch_diff_1/m1_657_280# Q2_d 0.03fF
+C15 nCLK Q1 -0.02fF
+C16 nCLK sky130_fd_sc_hs__or2_1_0/a_63_368# 0.05fF
+C17 DFlipFlop_1/latch_diff_1/D CLK 0.18fF
+C18 DFlipFlop_2/latch_diff_1/D Q2 0.13fF
+C19 sky130_fd_sc_hs__or2_1_0/X nCLK_23 0.07fF
+C20 DFlipFlop_1/D sky130_fd_sc_hs__or2_1_0/X 0.35fF
+C21 DFlipFlop_2/latch_diff_1/D Q2_d 0.03fF
+C22 sky130_fd_sc_hs__or2_1_1/X MC 0.02fF
+C23 nCLK DFlipFlop_1/latch_diff_1/D 0.09fF
+C24 vdd Q1 0.07fF
+C25 Q2 DFlipFlop_2/nQ 0.13fF
+C26 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_443_74# 0.09fF
+C27 sky130_fd_sc_hs__or2_1_1/a_63_368# Q2 0.09fF
+C28 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in CLK -0.10fF
+C29 nCLK_23 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.49fF
+C30 MC CLK 0.08fF
+C31 nCLK_23 Q1 0.02fF
+C32 DFlipFlop_0/nQ CLK 0.15fF
+C33 DFlipFlop_2/latch_diff_1/nD Q2 0.17fF
+C34 nCLK DFlipFlop_2/latch_diff_0/nD 0.09fF
+C35 sky130_fd_sc_hs__or2_1_1/X vdd 0.03fF
+C36 nCLK MC 0.01fF
+C37 DFlipFlop_0/nQ nCLK 0.11fF
+C38 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C39 sky130_fd_sc_hs__and2_1_0/a_56_136# CLK 0.08fF
+C40 nCLK sky130_fd_sc_hs__or2_1_0/a_152_368# 0.01fF
+C41 nCLK_23 sky130_fd_sc_hs__or2_1_1/X 0.26fF
+C42 MC vdd 0.88fF
+C43 vdd CLK 0.34fF
+C44 CLK DFlipFlop_2/latch_diff_0/D 0.13fF
+C45 sky130_fd_sc_hs__or2_1_1/X Q2 0.24fF
+C46 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.08fF
+C47 sky130_fd_sc_hs__or2_1_1/X Q2_d 0.03fF
+C48 nCLK_23 MC 4.46fF
+C49 nCLK vdd -0.55fF
+C50 nCLK_23 DFlipFlop_0/nQ 0.05fF
+C51 Q2 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.38fF
+C52 nCLK_23 CLK 0.22fF
+C53 DFlipFlop_1/D CLK 0.40fF
+C54 MC sky130_fd_sc_hs__mux2_1_0/a_27_112# 0.24fF
+C55 MC Q2 0.18fF
+C56 sky130_fd_sc_hs__mux2_1_0/a_524_368# nCLK_23 0.04fF
+C57 DFlipFlop_0/latch_diff_1/nD Q1 0.03fF
+C58 Q2 CLK 0.29fF
+C59 CLK DFlipFlop_0/latch_diff_1/D 0.04fF
+C60 nCLK_23 nCLK 0.11fF
+C61 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.16fF
+C62 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.29fF
+C63 DFlipFlop_0/latch_diff_0/nD nCLK_23 0.12fF
+C64 DFlipFlop_1/D nCLK 0.16fF
+C65 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.31fF
+C66 nCLK_23 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C67 nCLK Q2 0.29fF
+C68 sky130_fd_sc_hs__or2_1_0/X Q1 0.06fF
+C69 nCLK_23 vdd 3.35fF
+C70 vdd CLK_23 0.16fF
+C71 DFlipFlop_1/latch_diff_0/nD CLK 0.09fF
+C72 DFlipFlop_2/latch_diff_0/m1_657_280# nCLK 0.31fF
+C73 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.02fF
+C74 DFlipFlop_1/D vdd 0.07fF
+C75 vdd Q2 1.63fF
+C76 Q2 DFlipFlop_2/latch_diff_0/D 0.30fF
+C77 DFlipFlop_0/latch_diff_1/m1_657_280# Q1 0.06fF
+C78 vdd Q2_d 0.02fF
+C79 sky130_fd_sc_hs__and2_1_0/a_143_136# nCLK_23 0.02fF
+C80 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.06fF
+C81 DFlipFlop_1/D nCLK_23 0.02fF
+C82 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_27_112# 0.07fF
+C83 nCLK_23 Q2 0.03fF
+C84 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C85 nCLK_23 DFlipFlop_0/latch_diff_1/D 0.05fF
+C86 DFlipFlop_2/latch_diff_1/m1_657_280# CLK 0.33fF
+C87 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.09fF
+C88 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.04fF
+C89 CLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.05fF
+C90 nCLK DFlipFlop_1/latch_diff_0/D 0.02fF
+C91 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C92 DFlipFlop_2/latch_diff_1/D CLK 0.09fF
+C93 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C94 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_443_74# 0.03fF
+C95 Q2 Q2_d 0.66fF
+C96 sky130_fd_sc_hs__or2_1_0/X MC 0.09fF
+C97 sky130_fd_sc_hs__or2_1_0/X CLK 0.01fF
+C98 nCLK DFlipFlop_2/latch_diff_1/D 0.16fF
+C99 DFlipFlop_2/nQ CLK 0.02fF
+C100 sky130_fd_sc_hs__or2_1_0/X nCLK 0.06fF
+C101 sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C102 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C103 sky130_fd_sc_hs__or2_1_0/X vss 0.92fF
+C104 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.39fF
+C105 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.72fF
+C106 DFlipFlop_1/latch_diff_1/D vss -1.72fF
+C107 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C108 DFlipFlop_1/latch_diff_1/nD vss 0.58fF
+C109 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C110 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C111 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C112 DFlipFlop_1/D vss 2.98fF
+C113 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C114 Q2_d vss -0.22fF
+C115 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C116 DFlipFlop_2/nQ vss 0.48fF
+C117 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C118 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C119 DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C120 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C121 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C122 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C123 Q2 vss 1.35fF
+C124 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C125 Q1 vss 0.50fF
+C126 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C127 nCLK vss -1.49fF
+C128 DFlipFlop_0/nQ vss 0.48fF
+C129 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C130 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C131 CLK vss -0.61fF
+C132 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C133 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C134 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C135 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C136 nCLK_23 vss -0.65fF
+C137 vdd vss 115.92fF
+C138 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C139 CLK_23 vss -0.57fF
+C140 sky130_fd_sc_hs__or2_1_1/X vss -0.35fF
+C141 MC vss 2.09fF
+C142 sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.41fF
+C143 sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.69fF
+.ends
+
+.subckt freq_div clk_0 vss in_a n_clk_0 vdd prescaler_23_0/Q2 s_0 s_1_n s_1 prescaler_23_0/nCLK_23
++ prescaler_23_0/MC clk_d prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n
++ clk_pre div_by_5_0/DFlipFlop_2/latch_diff_0/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out div_by_5_0/Q1 div_by_5_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD clk_2 in_b clk_5 prescaler_23_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_1/D prescaler_23_0/DFlipFlop_2/latch_diff_0/D
+Xdiv_by_2_0 vss vdd div_by_2_0/nout_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in
++ clk_2 div_by_2_0/nCLK_2 div_by_2_0/o1 clk_out_mux21 div_by_2_0/out_div div_by_2_0/o2
++ div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out div_by_2
+Xmux2to1_0 vss s_0_n clk_out_mux21 clk_pre clk_5 s_0 vdd mux2to1
+Xinverter_min_x4_0 vdd inverter_min_x4_0/in vss clk_d inverter_min_x4
+Xmux2to1_1 vss s_1_n out clk_d clk_2 s_1 vdd mux2to1
+Xinverter_min_x2_0 clk_out_mux21 inverter_min_x4_0/in vss vdd inverter_min_x2
+Xinverter_min_x2_1 s_1 s_1_n vss vdd inverter_min_x2
+Xinverter_min_x2_2 s_0 s_0_n vss vdd inverter_min_x2
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_clk_1 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5_0/Q0 div_by_5_0/Q1 clk_1 div_by_5_0/DFlipFlop_0/Q div_by_5_0/DFlipFlop_2/latch_diff_1/D
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136#
++ div_by_5_0/nQ0 div_by_5_0/DFlipFlop_3/latch_diff_0/D div_by_5_0/DFlipFlop_3/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# clk_5 div_by_5_0/Q1_shift div_by_5_0/nQ2
++ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
++ div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_2/latch_diff_0/D
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xmux2to4_0 vss n_clk_1 vdd s_0 s_0_n in_a clk_0 clk_1 n_clk_0 in_b mux2to4
+Xprescaler_23_0 n_clk_0 vss prescaler_23_0/DFlipFlop_0/latch_diff_1/nD prescaler_23_0/nCLK_23
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vdd prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_pre prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_0 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD prescaler_23_0/DFlipFlop_0/latch_diff_0/nD
++ prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# prescaler_23_0/DFlipFlop_0/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/MC prescaler_23_0/DFlipFlop_0/latch_diff_0/D
++ prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in prescaler_23_0/Q2
++ prescaler_23
+C0 clk_pre prescaler_23_0/nCLK_23 0.03fF
+C1 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0 0.05fF
+C2 vdd s_0 3.90fF
+C3 in_a clk_1 0.05fF
+C4 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD 0.09fF
+C5 s_0_n div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.05fF
+C6 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C7 vdd clk_5 0.06fF
+C8 s_0 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.05fF
+C9 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out s_0 0.30fF
+C10 s_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.19fF
+C11 in_b s_0_n 0.48fF
+C12 s_0 div_by_5_0/nQ2 0.05fF
+C13 in_a s_0 0.30fF
+C14 clk_pre vdd 0.17fF
+C15 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out s_0_n -0.01fF
+C16 s_0_n clk_1 4.82fF
+C17 div_by_5_0/DFlipFlop_0/D s_0_n 0.05fF
+C18 vdd inverter_min_x4_0/in 0.09fF
+C19 s_0_n s_0 7.76fF
+C20 div_by_5_0/Q1 vdd 0.04fF
+C21 n_clk_0 prescaler_23_0/nCLK_23 0.16fF
+C22 s_0_n clk_5 0.56fF
+C23 div_by_5_0/DFlipFlop_2/latch_diff_0/nD s_0_n 0.20fF
+C24 div_by_5_0/DFlipFlop_2/nQ s_0 0.05fF
+C25 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.11fF
+C26 n_clk_0 vdd 0.25fF
+C27 clk_2 vdd 0.06fF
+C28 s_1 clk_d 0.22fF
+C29 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/D 0.13fF
+C30 div_by_5_0/Q1 s_0_n 0.21fF
+C31 clk_out_mux21 s_0 0.68fF
+C32 s_0 div_by_5_0/DFlipFlop_2/D 0.03fF
+C33 div_by_5_0/DFlipFlop_3/latch_diff_0/D s_0 0.10fF
+C34 vdd div_by_5_0/Q0 0.05fF
+C35 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_clk_1 0.06fF
+C36 clk_out_mux21 clk_5 0.05fF
+C37 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.11fF
+C38 clk_pre clk_out_mux21 1.19fF
+C39 n_clk_0 s_0_n 0.31fF
+C40 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0_n 0.24fF
+C41 div_by_5_0/DFlipFlop_3/latch_diff_1/D s_0_n 0.24fF
+C42 n_clk_1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C43 div_by_5_0/DFlipFlop_0/latch_diff_0/nD s_0_n 0.20fF
+C44 div_by_5_0/Q1_shift s_0_n 0.04fF
+C45 div_by_5_0/Q1_shift div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# -0.02fF
+C46 in_b n_clk_1 0.05fF
+C47 s_0_n div_by_5_0/Q0 0.24fF
+C48 div_by_5_0/nQ0 s_0 0.05fF
+C49 div_by_5_0/DFlipFlop_3/latch_diff_1/nD s_0 0.05fF
+C50 div_by_5_0/DFlipFlop_0/D n_clk_1 0.21fF
+C51 div_by_5_0/DFlipFlop_3/nQ s_0 0.02fF
+C52 s_0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.12fF
+C53 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in s_0 -0.36fF
+C54 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD 0.13fF
+C55 s_0_n div_by_5_0/DFlipFlop_1/D 0.19fF
+C56 s_0 div_by_5_0/DFlipFlop_0/Q 0.02fF
+C57 s_1 out 0.39fF
+C58 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_clk_1 0.03fF
+C59 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.04fF
+C60 clk_d inverter_min_x4_0/in 0.11fF
+C61 div_by_5_0/DFlipFlop_0/latch_diff_1/nD clk_1 0.08fF
+C62 div_by_5_0/DFlipFlop_2/latch_diff_1/D s_0_n 0.04fF
+C63 s_0_n vdd 2.76fF
+C64 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.02fF
+C65 s_1 s_1_n 0.39fF
+C66 n_clk_1 div_by_5_0/Q1 0.15fF
+C67 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.04fF
+C68 s_0_n div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.31fF
+C69 s_0_n div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.29fF
+C70 s_0_n div_by_5_0/nQ2 0.05fF
+C71 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_1 0.05fF
+C72 s_0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.02fF
+C73 div_by_5_0/DFlipFlop_0/D clk_1 0.14fF
+C74 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out s_0 -0.13fF
+C75 s_0 clk_1 1.36fF
+C76 prescaler_23_0/DFlipFlop_0/latch_diff_1/D n_clk_0 0.09fF
+C77 div_by_5_0/DFlipFlop_0/D s_0 0.03fF
+C78 clk_out_mux21 vdd 0.14fF
+C79 out s_1_n 0.33fF
+C80 div_by_5_0/DFlipFlop_2/nQ s_0_n 0.04fF
+C81 n_clk_1 div_by_5_0/Q0 0.01fF
+C82 div_by_5_0/Q1 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in -0.03fF
+C83 div_by_5_0/DFlipFlop_2/latch_diff_0/nD s_0 0.12fF
+C84 clk_pre s_0 0.21fF
+C85 clk_0 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C86 clk_out_mux21 s_0_n 0.45fF
+C87 s_0_n div_by_5_0/DFlipFlop_2/D 0.05fF
+C88 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.17fF
+C89 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.08fF
+C90 div_by_5_0/Q1 s_0 0.04fF
+C91 clk_0 prescaler_23_0/nCLK_23 0.16fF
+C92 vdd clk_d 0.23fF
+C93 n_clk_0 clk_1 -0.03fF
+C94 n_clk_1 vdd 0.15fF
+C95 clk_2 out 0.05fF
+C96 clk_0 vdd 0.63fF
+C97 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0 0.02fF
+C98 div_by_5_0/DFlipFlop_0/latch_diff_0/nD clk_1 0.08fF
+C99 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD 0.09fF
+C100 div_by_5_0/DFlipFlop_3/latch_diff_1/D s_0 0.02fF
+C101 div_by_5_0/nQ0 s_0_n 0.05fF
+C102 div_by_5_0/DFlipFlop_0/latch_diff_0/nD s_0 0.12fF
+C103 div_by_5_0/Q1_shift s_0 0.05fF
+C104 clk_2 s_1_n 0.59fF
+C105 div_by_5_0/DFlipFlop_3/latch_diff_1/nD s_0_n 0.04fF
+C106 s_0_n div_by_5_0/DFlipFlop_3/nQ 0.24fF
+C107 s_0 div_by_5_0/Q0 0.02fF
+C108 div_by_5_0/Q1_shift clk_5 0.04fF
+C109 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.20fF
+C110 s_0_n div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.37fF
+C111 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/D 0.13fF
+C112 s_0_n div_by_5_0/DFlipFlop_0/Q 0.24fF
+C113 clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.11fF
+C114 s_0 div_by_5_0/DFlipFlop_1/D 0.03fF
+C115 n_clk_0 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C116 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.05fF
+C117 vdd clk_1 0.18fF
+C118 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.24fF
+C119 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C120 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C121 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C122 prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C123 prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C124 prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C125 prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C126 prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C127 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C128 prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C129 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C130 prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C131 prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C132 prescaler_23_0/Q2_d vss -0.69fF
+C133 prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C134 prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C135 prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C136 prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C137 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C138 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C139 prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C140 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C141 prescaler_23_0/Q2 vss 0.55fF
+C142 prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C143 prescaler_23_0/Q1 vss 0.07fF
+C144 prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C145 n_clk_0 vss -5.72fF
+C146 prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C147 prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C148 prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C149 clk_0 vss 0.74fF
+C150 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C151 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C152 prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C153 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C154 prescaler_23_0/nCLK_23 vss -1.02fF
+C155 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C156 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C157 prescaler_23_0/MC vss 1.07fF
+C158 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C159 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C160 in_b vss 2.26fF
+C161 s_0_n vss -2.65fF
+C162 in_a vss 2.25fF
+C163 s_0 vss 5.73fF
+C164 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C165 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C166 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C167 div_by_5_0/Q1_shift vss -0.36fF
+C168 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C169 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C170 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C171 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C172 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C173 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C174 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C176 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C177 div_by_5_0/Q1 vss 4.35fF
+C178 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C179 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C180 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C181 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C182 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C183 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C184 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C185 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C186 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C187 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C188 div_by_5_0/Q0 vss 0.29fF
+C189 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C190 div_by_5_0/nQ0 vss 0.99fF
+C191 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C192 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C193 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C194 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C195 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C196 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C197 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C198 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C199 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C200 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C201 n_clk_1 vss -0.44fF
+C202 div_by_5_0/nQ2 vss 1.38fF
+C203 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C204 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C205 clk_1 vss -1.17fF
+C206 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C207 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C208 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C209 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C210 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C211 vdd vss 355.84fF
+C212 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C213 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C214 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C215 s_1_n vss 1.15fF
+C216 out vss 1.17fF
+C217 clk_d vss 0.79fF
+C218 s_1 vss 2.97fF
+C219 inverter_min_x4_0/in vss 2.77fF
+C220 clk_5 vss 0.10fF
+C221 clk_out_mux21 vss 5.62fF
+C222 clk_pre vss 1.31fF
+C223 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C224 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C225 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C226 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C227 clk_2 vss 3.57fF
+C228 div_by_2_0/o1 vss 2.20fF
+C229 div_by_2_0/nCLK_2 vss 1.04fF
+C230 div_by_2_0/o2 vss 2.08fF
+C231 div_by_2_0/out_div vss -0.80fF
+C232 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C233 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C234 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C235 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C236 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C237 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C238 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C239 div_by_2_0/nout_div vss 2.62fF
+C240 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+.ends
+
.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
C0 a_15_n150# a_n33_n238# 0.02fF
C1 a_n73_n150# a_n33_n238# 0.02fF
-C2 a_n73_n150# a_15_n150# 0.51fF
+C2 a_15_n150# a_n73_n150# 0.51fF
C3 a_15_n150# w_n211_n360# 0.23fF
C4 a_n73_n150# w_n211_n360# 0.23fF
C5 a_n33_n238# w_n211_n360# 0.17fF
@@ -5287,12 +6286,12 @@
.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_n73_n150# w_n211_n369# 0.20fF
-C1 a_n73_n150# a_n33_181# 0.01fF
-C2 a_15_n150# w_n211_n369# 0.20fF
-C3 a_15_n150# a_n33_181# 0.01fF
-C4 a_n73_n150# a_15_n150# 0.51fF
-C5 a_n33_181# w_n211_n369# 0.05fF
+C0 a_15_n150# w_n211_n369# 0.20fF
+C1 a_n73_n150# a_15_n150# 0.51fF
+C2 a_n33_181# a_15_n150# 0.01fF
+C3 a_n73_n150# w_n211_n369# 0.20fF
+C4 a_n33_181# w_n211_n369# 0.05fF
+C5 a_n73_n150# a_n33_181# 0.01fF
C6 a_15_n150# VSUBS 0.03fF
C7 a_n73_n150# VSUBS 0.03fF
C8 a_n33_181# VSUBS 0.13fF
@@ -5312,51 +6311,51 @@
X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_n321_n150# a_n417_n150# 0.43fF
-C1 a_n321_n150# a_n33_n150# 0.10fF
-C2 a_159_n150# a_n129_n150# 0.10fF
-C3 a_n465_172# a_63_n150# 0.10fF
-C4 a_n509_n150# a_n465_172# 0.01fF
-C5 a_63_n150# a_447_n150# 0.07fF
-C6 a_n225_n150# a_159_n150# 0.07fF
-C7 a_n465_172# a_447_n150# 0.01fF
-C8 a_n129_n150# a_63_n150# 0.16fF
-C9 a_n129_n150# a_n465_172# 0.10fF
-C10 a_n509_n150# a_n129_n150# 0.07fF
-C11 a_n225_n150# a_63_n150# 0.10fF
-C12 a_n225_n150# a_n465_172# 0.10fF
-C13 a_n509_n150# a_n225_n150# 0.10fF
-C14 a_255_n150# a_n33_n150# 0.10fF
-C15 a_n321_n150# a_63_n150# 0.07fF
-C16 a_n321_n150# a_n465_172# 0.10fF
-C17 a_n509_n150# a_n321_n150# 0.16fF
-C18 a_n225_n150# a_n129_n150# 0.43fF
-C19 a_159_n150# a_255_n150# 0.43fF
-C20 a_351_n150# a_255_n150# 0.43fF
-C21 a_n321_n150# a_n129_n150# 0.16fF
-C22 a_n321_n150# a_n225_n150# 0.43fF
-C23 a_n33_n150# a_n417_n150# 0.07fF
-C24 a_63_n150# a_255_n150# 0.16fF
-C25 a_n465_172# a_255_n150# 0.10fF
-C26 a_255_n150# a_447_n150# 0.16fF
-C27 a_n129_n150# a_255_n150# 0.07fF
-C28 a_159_n150# a_n33_n150# 0.16fF
-C29 a_351_n150# a_n33_n150# 0.07fF
-C30 a_n465_172# a_n417_n150# 0.10fF
-C31 a_159_n150# a_351_n150# 0.16fF
-C32 a_n509_n150# a_n417_n150# 0.43fF
-C33 a_63_n150# a_n33_n150# 0.43fF
-C34 a_n465_172# a_n33_n150# 0.10fF
-C35 a_n129_n150# a_n417_n150# 0.10fF
-C36 a_n129_n150# a_n33_n150# 0.43fF
-C37 a_159_n150# a_63_n150# 0.43fF
-C38 a_63_n150# a_351_n150# 0.10fF
-C39 a_159_n150# a_n465_172# 0.10fF
-C40 a_n465_172# a_351_n150# 0.10fF
-C41 a_n225_n150# a_n417_n150# 0.16fF
-C42 a_159_n150# a_447_n150# 0.10fF
-C43 a_351_n150# a_447_n150# 0.43fF
-C44 a_n225_n150# a_n33_n150# 0.16fF
+C0 a_351_n150# a_255_n150# 0.43fF
+C1 a_n129_n150# a_n465_172# 0.10fF
+C2 a_n321_n150# a_63_n150# 0.07fF
+C3 a_n321_n150# a_n465_172# 0.10fF
+C4 a_n33_n150# a_n417_n150# 0.07fF
+C5 a_447_n150# a_159_n150# 0.10fF
+C6 a_447_n150# a_255_n150# 0.16fF
+C7 a_n129_n150# a_n417_n150# 0.10fF
+C8 a_n129_n150# a_n509_n150# 0.07fF
+C9 a_n33_n150# a_n225_n150# 0.16fF
+C10 a_n465_172# a_63_n150# 0.10fF
+C11 a_n129_n150# a_n225_n150# 0.43fF
+C12 a_n417_n150# a_n321_n150# 0.43fF
+C13 a_n509_n150# a_n321_n150# 0.16fF
+C14 a_447_n150# a_351_n150# 0.43fF
+C15 a_n321_n150# a_n225_n150# 0.43fF
+C16 a_n33_n150# a_159_n150# 0.16fF
+C17 a_n33_n150# a_255_n150# 0.10fF
+C18 a_n129_n150# a_159_n150# 0.10fF
+C19 a_n129_n150# a_255_n150# 0.07fF
+C20 a_n225_n150# a_63_n150# 0.10fF
+C21 a_n417_n150# a_n465_172# 0.10fF
+C22 a_n509_n150# a_n465_172# 0.01fF
+C23 a_n33_n150# a_351_n150# 0.07fF
+C24 a_n465_172# a_n225_n150# 0.10fF
+C25 a_63_n150# a_159_n150# 0.43fF
+C26 a_255_n150# a_63_n150# 0.16fF
+C27 a_n417_n150# a_n509_n150# 0.43fF
+C28 a_n465_172# a_159_n150# 0.10fF
+C29 a_n465_172# a_255_n150# 0.10fF
+C30 a_n417_n150# a_n225_n150# 0.16fF
+C31 a_n509_n150# a_n225_n150# 0.10fF
+C32 a_351_n150# a_63_n150# 0.10fF
+C33 a_351_n150# a_n465_172# 0.10fF
+C34 a_n33_n150# a_n129_n150# 0.43fF
+C35 a_n225_n150# a_159_n150# 0.07fF
+C36 a_447_n150# a_63_n150# 0.07fF
+C37 a_n33_n150# a_n321_n150# 0.10fF
+C38 a_447_n150# a_n465_172# 0.01fF
+C39 a_n129_n150# a_n321_n150# 0.16fF
+C40 a_255_n150# a_159_n150# 0.43fF
+C41 a_n33_n150# a_63_n150# 0.43fF
+C42 a_n129_n150# a_63_n150# 0.16fF
+C43 a_n33_n150# a_n465_172# 0.10fF
+C44 a_351_n150# a_159_n150# 0.16fF
C45 a_447_n150# w_n647_n360# 0.17fF
C46 a_351_n150# w_n647_n360# 0.10fF
C47 a_255_n150# w_n647_n360# 0.08fF
@@ -5384,61 +6383,61 @@
X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 w_n647_n369# a_n129_n150# 0.02fF
-C1 a_n225_n150# w_n647_n369# 0.04fF
-C2 a_n33_n150# a_n465_n247# 0.08fF
-C3 a_n33_n150# a_n417_n150# 0.07fF
-C4 a_255_n150# a_n465_n247# 0.08fF
-C5 a_n321_n150# a_63_n150# 0.07fF
-C6 a_159_n150# a_n465_n247# 0.08fF
-C7 w_n647_n369# a_n465_n247# 0.47fF
-C8 a_n417_n150# w_n647_n369# 0.07fF
-C9 a_n321_n150# a_n129_n150# 0.16fF
-C10 a_n225_n150# a_n321_n150# 0.43fF
-C11 a_n509_n150# a_n129_n150# 0.07fF
-C12 a_n33_n150# a_255_n150# 0.10fF
-C13 a_n509_n150# a_n225_n150# 0.10fF
-C14 a_n33_n150# a_159_n150# 0.16fF
-C15 a_255_n150# a_447_n150# 0.16fF
-C16 a_351_n150# a_63_n150# 0.10fF
-C17 a_159_n150# a_447_n150# 0.10fF
-C18 a_159_n150# a_255_n150# 0.43fF
-C19 a_n33_n150# w_n647_n369# 0.02fF
-C20 a_n321_n150# a_n465_n247# 0.08fF
-C21 a_63_n150# a_n129_n150# 0.16fF
-C22 a_n417_n150# a_n321_n150# 0.43fF
-C23 w_n647_n369# a_447_n150# 0.14fF
-C24 a_255_n150# w_n647_n369# 0.05fF
-C25 a_n225_n150# a_63_n150# 0.10fF
-C26 a_159_n150# w_n647_n369# 0.04fF
-C27 a_n509_n150# a_n417_n150# 0.43fF
-C28 a_n225_n150# a_n129_n150# 0.43fF
-C29 a_n33_n150# a_n321_n150# 0.10fF
-C30 a_63_n150# a_n465_n247# 0.08fF
-C31 a_351_n150# a_n465_n247# 0.08fF
-C32 a_n129_n150# a_n465_n247# 0.08fF
-C33 a_n417_n150# a_n129_n150# 0.10fF
-C34 w_n647_n369# a_n321_n150# 0.05fF
-C35 a_n225_n150# a_n465_n247# 0.08fF
-C36 a_n417_n150# a_n225_n150# 0.16fF
-C37 a_n33_n150# a_63_n150# 0.43fF
-C38 a_n509_n150# w_n647_n369# 0.14fF
-C39 a_n33_n150# a_351_n150# 0.07fF
-C40 a_447_n150# a_63_n150# 0.07fF
-C41 a_255_n150# a_63_n150# 0.16fF
-C42 a_159_n150# a_63_n150# 0.43fF
-C43 a_447_n150# a_351_n150# 0.43fF
-C44 a_255_n150# a_351_n150# 0.43fF
-C45 a_n33_n150# a_n129_n150# 0.43fF
-C46 a_159_n150# a_351_n150# 0.16fF
-C47 a_n417_n150# a_n465_n247# 0.08fF
-C48 w_n647_n369# a_63_n150# 0.02fF
-C49 a_n33_n150# a_n225_n150# 0.16fF
-C50 a_255_n150# a_n129_n150# 0.07fF
-C51 w_n647_n369# a_351_n150# 0.07fF
-C52 a_159_n150# a_n129_n150# 0.10fF
-C53 a_n509_n150# a_n321_n150# 0.16fF
-C54 a_159_n150# a_n225_n150# 0.07fF
+C0 a_63_n150# a_255_n150# 0.16fF
+C1 a_159_n150# w_n647_n369# 0.04fF
+C2 a_n465_n247# a_159_n150# 0.08fF
+C3 a_n129_n150# a_n33_n150# 0.43fF
+C4 a_n129_n150# a_63_n150# 0.16fF
+C5 a_n225_n150# a_n33_n150# 0.16fF
+C6 a_n417_n150# w_n647_n369# 0.07fF
+C7 a_n417_n150# a_n465_n247# 0.08fF
+C8 a_n225_n150# a_63_n150# 0.10fF
+C9 a_255_n150# w_n647_n369# 0.05fF
+C10 a_n465_n247# a_255_n150# 0.08fF
+C11 a_n129_n150# w_n647_n369# 0.02fF
+C12 a_n129_n150# a_n465_n247# 0.08fF
+C13 a_n417_n150# a_n509_n150# 0.43fF
+C14 a_n225_n150# w_n647_n369# 0.04fF
+C15 a_n225_n150# a_n465_n247# 0.08fF
+C16 a_159_n150# a_255_n150# 0.43fF
+C17 a_n321_n150# a_n33_n150# 0.10fF
+C18 a_n509_n150# a_n129_n150# 0.07fF
+C19 a_n321_n150# a_63_n150# 0.07fF
+C20 a_n129_n150# a_159_n150# 0.10fF
+C21 a_351_n150# a_447_n150# 0.43fF
+C22 a_351_n150# a_n33_n150# 0.07fF
+C23 a_n509_n150# a_n225_n150# 0.10fF
+C24 a_351_n150# a_63_n150# 0.10fF
+C25 a_n225_n150# a_159_n150# 0.07fF
+C26 a_n417_n150# a_n129_n150# 0.10fF
+C27 a_63_n150# a_447_n150# 0.07fF
+C28 a_63_n150# a_n33_n150# 0.43fF
+C29 a_n417_n150# a_n225_n150# 0.16fF
+C30 a_n129_n150# a_255_n150# 0.07fF
+C31 a_n321_n150# w_n647_n369# 0.05fF
+C32 a_n321_n150# a_n465_n247# 0.08fF
+C33 a_351_n150# w_n647_n369# 0.07fF
+C34 a_351_n150# a_n465_n247# 0.08fF
+C35 a_447_n150# w_n647_n369# 0.14fF
+C36 a_n33_n150# w_n647_n369# 0.02fF
+C37 a_n225_n150# a_n129_n150# 0.43fF
+C38 a_n465_n247# a_n33_n150# 0.08fF
+C39 a_n509_n150# a_n321_n150# 0.16fF
+C40 a_63_n150# w_n647_n369# 0.02fF
+C41 a_63_n150# a_n465_n247# 0.08fF
+C42 a_351_n150# a_159_n150# 0.16fF
+C43 a_n417_n150# a_n321_n150# 0.43fF
+C44 a_447_n150# a_159_n150# 0.10fF
+C45 a_n33_n150# a_159_n150# 0.16fF
+C46 a_n465_n247# w_n647_n369# 0.47fF
+C47 a_63_n150# a_159_n150# 0.43fF
+C48 a_n417_n150# a_n33_n150# 0.07fF
+C49 a_351_n150# a_255_n150# 0.43fF
+C50 a_n129_n150# a_n321_n150# 0.16fF
+C51 a_447_n150# a_255_n150# 0.16fF
+C52 a_n33_n150# a_255_n150# 0.10fF
+C53 a_n225_n150# a_n321_n150# 0.43fF
+C54 a_n509_n150# w_n647_n369# 0.14fF
C55 a_447_n150# VSUBS 0.03fF
C56 a_351_n150# VSUBS 0.03fF
C57 a_255_n150# VSUBS 0.03fF
@@ -5466,7 +6465,7 @@
.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
-C0 a_20_n106# a_n78_n106# 0.21fF
+C0 a_n78_n106# a_20_n106# 0.21fF
C1 a_20_n106# w_n216_n254# 0.14fF
C2 a_n78_n106# w_n216_n254# 0.14fF
C3 a_n33_66# w_n216_n254# 0.12fF
@@ -5476,8 +6475,8 @@
+ a_20_n114#
X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
C0 w_n216_n334# a_n78_n114# 0.20fF
-C1 w_n216_n334# a_20_n114# 0.20fF
-C2 a_n78_n114# a_20_n114# 0.42fF
+C1 a_20_n114# w_n216_n334# 0.20fF
+C2 a_20_n114# a_n78_n114# 0.42fF
C3 a_20_n114# VSUBS 0.03fF
C4 a_n78_n114# VSUBS 0.03fF
C5 a_n33_n211# VSUBS 0.12fF
@@ -5487,10 +6486,10 @@
.subckt inverter_csvco in vbulkn out vbulkp vdd vss
Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
-C0 out vbulkp 0.08fF
-C1 in vdd 0.01fF
-C2 vdd vbulkp 0.04fF
-C3 in vss 0.01fF
+C0 in vss 0.01fF
+C1 vbulkp vdd 0.04fF
+C2 vbulkp out 0.08fF
+C3 in vdd 0.01fF
C4 in out 0.11fF
C5 vbulkp vbulkn 2.49fF
C6 out vbulkn 0.60fF
@@ -5499,8 +6498,8 @@
C9 vss vbulkn 0.17fF
.ends
-.subckt csvco_branch vctrl inverter_csvco_0/vdd in vbp cap_vco_0/t D0 out inverter_csvco_0/vss
-+ vss vdd
+.subckt csvco_branch vctrl inverter_csvco_0/vdd in vbp cap_vco_0/t D0 vss out vdd
++ inverter_csvco_0/vss
Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
+ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
+ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
@@ -5509,20 +6508,20 @@
+ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
-C0 inverter_csvco_0/vdd vdd 1.89fF
-C1 inverter_csvco_0/vdd out 0.02fF
-C2 inverter_csvco_0/vdd in 0.01fF
-C3 inverter_csvco_0/vss out 0.03fF
-C4 inverter_csvco_0/vss in 0.01fF
-C5 D0 inverter_csvco_0/vss 0.02fF
-C6 out in 0.06fF
-C7 D0 out 0.09fF
-C8 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
-C9 inverter_csvco_0/vdd vbp 0.75fF
-C10 cap_vco_0/t vdd 0.04fF
-C11 vdd vbp 1.21fF
-C12 cap_vco_0/t out 0.70fF
-C13 inverter_csvco_0/vss vctrl 0.87fF
+C0 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C1 D0 out 0.09fF
+C2 vdd cap_vco_0/t 0.04fF
+C3 in out 0.06fF
+C4 out inverter_csvco_0/vdd 0.02fF
+C5 out inverter_csvco_0/vss 0.03fF
+C6 vbp inverter_csvco_0/vdd 0.75fF
+C7 in inverter_csvco_0/vdd 0.01fF
+C8 vbp vdd 1.21fF
+C9 D0 inverter_csvco_0/vss 0.02fF
+C10 vctrl inverter_csvco_0/vss 0.87fF
+C11 inverter_csvco_0/vdd vdd 1.89fF
+C12 in inverter_csvco_0/vss 0.01fF
+C13 out cap_vco_0/t 0.70fF
C14 out vss 0.93fF
C15 inverter_csvco_0/vdd vss 0.26fF
C16 in vss 0.69fF
@@ -5534,36 +6533,36 @@
C22 vctrl vss 3.06fF
.ends
-.subckt ring_osc csvco_branch_0/inverter_csvco_0/vdd vctrl csvco_branch_1/inverter_csvco_0/vdd
-+ csvco_branch_2/inverter_csvco_0/vdd vdd vss csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
+.subckt ring_osc csvco_branch_0/inverter_csvco_0/vdd vctrl vss csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch_2/inverter_csvco_0/vdd vdd csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
+ D0 csvco_branch_2/cap_vco_0/t out_vco
Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
+ sky130_fd_pr__pfet_01v8_4757AC
Xcsvco_branch_0 vctrl csvco_branch_0/inverter_csvco_0/vdd out_vco csvco_branch_2/vbp
-+ csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in csvco_branch_0/inverter_csvco_0/vss
-+ vss vdd csvco_branch
++ csvco_branch_0/cap_vco_0/t D0 vss csvco_branch_1/in vdd csvco_branch_0/inverter_csvco_0/vss
++ csvco_branch
Xcsvco_branch_2 vctrl csvco_branch_2/inverter_csvco_0/vdd csvco_branch_2/in csvco_branch_2/vbp
-+ csvco_branch_2/cap_vco_0/t D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd
++ csvco_branch_2/cap_vco_0/t D0 vss out_vco vdd csvco_branch_2/inverter_csvco_0/vss
+ csvco_branch
Xcsvco_branch_1 vctrl csvco_branch_1/inverter_csvco_0/vdd csvco_branch_1/in csvco_branch_2/vbp
-+ csvco_branch_1/cap_vco_0/t D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss
-+ vss vdd csvco_branch
-C0 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
-C1 D0 vctrl 4.41fF
-C2 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
-C3 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
-C4 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
-C5 vdd csvco_branch_2/vbp 1.49fF
-C6 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
-C7 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
-C8 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
-C9 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
-C10 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
-C11 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
-C12 out_vco csvco_branch_2/in 0.58fF
-C13 csvco_branch_2/vbp vctrl 0.06fF
-C14 out_vco csvco_branch_1/in 0.76fF
++ csvco_branch_1/cap_vco_0/t D0 vss csvco_branch_2/in vdd csvco_branch_1/inverter_csvco_0/vss
++ csvco_branch
+C0 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C1 vctrl csvco_branch_2/vbp 0.06fF
+C2 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C3 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C4 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C5 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
+C6 out_vco csvco_branch_2/in 0.58fF
+C7 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C8 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C9 vdd csvco_branch_2/vbp 1.49fF
+C10 csvco_branch_1/in out_vco 0.76fF
+C11 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C12 D0 vctrl 4.41fF
+C13 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
+C14 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
C15 csvco_branch_2/in vss 1.60fF
C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -5586,371 +6585,16 @@
Xinverter_min_x4_1 vdd out_div vss out_pad inverter_min_x4
Xinverter_min_x4_0 vdd o1 vss out_div inverter_min_x4
Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
-C0 vdd o1 0.09fF
-C1 vdd out_div 0.17fF
-C2 o1 out_div 0.11fF
-C3 out_pad vdd 0.10fF
-C4 out_pad out_div 0.15fF
+C0 out_div o1 0.11fF
+C1 out_div vdd 0.17fF
+C2 vdd o1 0.09fF
+C3 out_div out_pad 0.15fF
+C4 vdd out_pad 0.10fF
C5 in_vco vss 0.83fF
C6 o1 vss 2.72fF
C7 vdd vss 14.54fF
-C8 out_div vss 3.00fF
-C9 out_pad vss 0.70fF
-.ends
-
-.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
-+ a_158_392#
-X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-C0 a_355_368# VPWR 0.37fF
-C1 a_355_368# B 0.08fF
-C2 a_355_368# X 0.17fF
-C3 a_194_125# a_158_392# 0.06fF
-C4 a_194_125# A 0.18fF
-C5 VPWR A 0.15fF
-C6 B A 0.28fF
-C7 a_194_125# VPWR 0.33fF
-C8 B a_194_125# 0.57fF
-C9 a_194_125# X 0.29fF
-C10 VGND A 0.31fF
-C11 a_194_125# VGND 0.25fF
-C12 a_355_368# A 0.02fF
-C13 a_355_368# a_194_125# 0.51fF
-C14 B VPWR 0.09fF
-C15 VPWR X 0.07fF
-C16 B X 0.13fF
-C17 VPB VPWR 0.06fF
-C18 VGND VPWR 0.01fF
-C19 B VGND 0.10fF
-C20 VGND X 0.28fF
-C21 VGND VNB 0.78fF
-C22 X VNB 0.21fF
-C23 VPWR VNB 0.78fF
-C24 B VNB 0.56fF
-C25 A VNB 0.70fF
-C26 VPB VNB 0.77fF
-C27 a_355_368# VNB 0.08fF
-C28 a_194_125# VNB 0.40fF
-.ends
-
-.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
-X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
-X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
-X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-C0 X VGND 0.15fF
-C1 B VGND 0.03fF
-C2 a_56_136# VPWR 0.57fF
-C3 A VPWR 0.07fF
-C4 X VPWR 0.20fF
-C5 B VPWR 0.02fF
-C6 VPB VPWR 0.04fF
-C7 A a_56_136# 0.17fF
-C8 X a_56_136# 0.26fF
-C9 B a_56_136# 0.30fF
-C10 A B 0.08fF
-C11 a_56_136# VGND 0.06fF
-C12 A VGND 0.21fF
-C13 B X 0.02fF
-C14 VGND VNB 0.50fF
-C15 X VNB 0.23fF
-C16 VPWR VNB 0.50fF
-C17 B VNB 0.24fF
-C18 A VNB 0.36fF
-C19 VPB VNB 0.48fF
-C20 a_56_136# VNB 0.38fF
-.ends
-
-.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
-X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-C0 VPB VPWR 0.04fF
-C1 X VPWR 0.18fF
-C2 A B 0.10fF
-C3 VGND B 0.11fF
-C4 A X 0.02fF
-C5 VGND X 0.16fF
-C6 a_63_368# VPWR 0.29fF
-C7 A a_63_368# 0.28fF
-C8 VGND a_63_368# 0.27fF
-C9 A VPWR 0.05fF
-C10 a_63_368# a_152_368# 0.03fF
-C11 B a_63_368# 0.14fF
-C12 X a_63_368# 0.33fF
-C13 B VPWR 0.01fF
-C14 VGND VNB 0.53fF
-C15 X VNB 0.24fF
-C16 A VNB 0.21fF
-C17 B VNB 0.31fF
-C18 VPWR VNB 0.46fF
-C19 VPB VNB 0.48fF
-C20 a_63_368# VNB 0.37fF
-.ends
-
-.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK DFlipFlop_0/latch_diff_1/nD
-+ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vdd vss Q0 CLK DFlipFlop_2/latch_diff_1/D
-+ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
-+ DFlipFlop_3/latch_diff_0/D nQ0 DFlipFlop_1/latch_diff_0/nD DFlipFlop_1/latch_diff_1/nD
-+ DFlipFlop_1/latch_diff_0/D CLK_5 nQ2 Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_1/latch_diff_1/D DFlipFlop_2/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
-+ DFlipFlop_0/latch_diff_0/nD sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_1/D
-+ DFlipFlop_2/nQ DFlipFlop_3/latch_diff_0/nD DFlipFlop_2/latch_diff_0/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_0/latch_diff_0/D sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D
-+ sky130_fd_sc_hs__or2_1_0/a_63_368# DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
-+ sky130_fd_sc_hs__xor2_1_0/a_194_125# sky130_fd_sc_hs__and2_1_0/a_143_136# DFlipFlop_2/latch_diff_0/nD
-Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
-+ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
-+ sky130_fd_sc_hs__xor2_1
-XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
-+ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 DFlipFlop_0/latch_diff_0/nD
-+ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/D
-+ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop
-XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss vdd DFlipFlop_2/latch_diff_1/D
-+ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
-+ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
-+ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop
-XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss vdd DFlipFlop_1/latch_diff_1/D
-+ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 DFlipFlop_1/latch_diff_0/nD
-+ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
-+ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop
-XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss vdd DFlipFlop_3/latch_diff_1/D
-+ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
-+ Q1_shift DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# Q1 DFlipFlop_3/latch_diff_0/D
-+ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out CLK DFlipFlop
-Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
-+ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
-Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
-+ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
-Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
-+ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
-C0 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
-C1 DFlipFlop_1/D nQ0 0.12fF
-C2 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
-C3 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
-C4 nCLK DFlipFlop_0/Q 0.11fF
-C5 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
-C6 vdd CLK_5 0.15fF
-C7 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
-C8 Q1 nCLK -0.01fF
-C9 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
-C10 DFlipFlop_0/Q CLK 0.08fF
-C11 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
-C12 Q1 CLK -0.10fF
-C13 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
-C14 vdd Q1 9.49fF
-C15 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
-C16 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
-C17 vdd Q1_shift 0.10fF
-C18 DFlipFlop_2/nQ Q1 0.31fF
-C19 nQ2 nQ0 0.03fF
-C20 Q0 DFlipFlop_0/D 0.39fF
-C21 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
-C22 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
-C23 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
-C24 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
-C25 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
-C26 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
-C27 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
-C28 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
-C29 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
-C30 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C31 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
-C32 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
-C33 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
-C34 DFlipFlop_0/D Q1 0.13fF
-C35 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
-C36 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
-C37 nCLK nQ0 0.09fF
-C38 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
-C39 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
-C40 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
-C41 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
-C42 DFlipFlop_3/nQ Q1 0.10fF
-C43 nQ0 CLK 0.19fF
-C44 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
-C45 vdd nQ0 0.11fF
-C46 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
-C47 DFlipFlop_2/D Q0 0.25fF
-C48 DFlipFlop_3/nQ Q1_shift 0.04fF
-C49 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
-C50 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
-C51 DFlipFlop_1/D nCLK 0.14fF
-C52 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
-C53 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
-C54 DFlipFlop_1/D CLK 0.21fF
-C55 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
-C56 vdd DFlipFlop_1/D 0.25fF
-C57 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.08fF
-C58 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q0 0.42fF
-C59 sky130_fd_sc_hs__and2_1_1/a_56_136# CLK 0.06fF
-C60 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
-C61 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
-C62 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
-C63 DFlipFlop_2/D Q1 0.10fF
-C64 Q0 sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.26fF
-C65 Q0 DFlipFlop_0/Q 0.21fF
-C66 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
-C67 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
-C68 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
-C69 Q0 Q1 9.65fF
-C70 nQ2 nCLK 0.10fF
-C71 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
-C72 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
-C73 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
-C74 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
-C75 nQ2 CLK 0.17fF
-C76 vdd nQ2 0.04fF
-C77 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
-C78 DFlipFlop_2/latch_diff_0/D nCLK 0.11fF
-C79 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
-C80 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q1 0.21fF
-C81 Q0 DFlipFlop_0/latch_diff_1/D 0.23fF
-C82 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
-C83 Q1 DFlipFlop_0/Q 0.13fF
-C84 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C85 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
-C86 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
-C87 Q1_shift Q1 0.36fF
-C88 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
-C89 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
-C90 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
-C91 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
-C92 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
-C93 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
-C94 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.08fF
-C95 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
-C96 vdd nCLK 0.34fF
-C97 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
-C98 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
-C99 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
-C100 DFlipFlop_2/nQ nCLK 0.09fF
-C101 DFlipFlop_2/latch_diff_1/nD CLK 0.09fF
-C102 vdd CLK 0.41fF
-C103 Q0 nQ0 0.33fF
-C104 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
-C105 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
-C106 DFlipFlop_1/latch_diff_0/nD CLK 0.08fF
-C107 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
-C108 DFlipFlop_2/nQ CLK 0.13fF
-C109 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
-C110 vdd DFlipFlop_2/nQ 0.02fF
-C111 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
-C112 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
-C113 Q0 DFlipFlop_1/D 0.07fF
-C114 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
-C115 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
-C116 sky130_fd_sc_hs__and2_1_0/a_56_136# Q1 0.14fF
-C117 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
-C118 Q1 nQ0 0.06fF
-C119 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
-C120 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
-C121 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
-C122 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
-C123 vdd DFlipFlop_0/D 0.19fF
-C124 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
-C125 DFlipFlop_3/nQ nCLK 0.02fF
-C126 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
-C127 DFlipFlop_1/D Q1 0.03fF
-C128 nQ2 Q0 0.23fF
-C129 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
-C130 DFlipFlop_3/nQ CLK 0.01fF
-C131 vdd DFlipFlop_3/nQ 0.02fF
-C132 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
-C133 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
-C134 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
-C135 sky130_fd_sc_hs__and2_1_1/a_143_136# CLK 0.03fF
-C136 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q1 0.09fF
-C137 DFlipFlop_3/latch_diff_0/D CLK 0.11fF
-C138 nQ2 DFlipFlop_0/Q 0.09fF
-C139 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
-C140 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
-C141 DFlipFlop_2/D nCLK 0.41fF
-C142 nQ2 Q1 0.07fF
-C143 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
-C144 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
-C145 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
-C146 Q0 nCLK 0.20fF
-C147 DFlipFlop_2/D CLK 0.14fF
-C148 vdd DFlipFlop_2/D 0.07fF
-C149 DFlipFlop_1/latch_diff_1/m1_657_280# nQ0 0.21fF
-C150 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
-C151 DFlipFlop_2/latch_diff_0/D Q1 0.42fF
-C152 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
-C153 Q0 CLK 0.08fF
-C154 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
-C155 vdd Q0 5.33fF
-C156 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK 0.14fF
-C157 CLK_5 vss -0.18fF
-C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
-C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
-C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
-C161 DFlipFlop_3/nQ vss 0.52fF
-C162 Q1_shift vss -0.29fF
-C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
-C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
-C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
-C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
-C167 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
-C168 DFlipFlop_3/latch_diff_0/D vss 0.96fF
-C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
-C170 Q1 vss 8.55fF
-C171 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C172 nQ0 vss 3.42fF
-C173 Q0 vss 0.53fF
-C174 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
-C175 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C176 DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C177 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C178 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C179 DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C180 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
-C181 DFlipFlop_1/D vss 3.72fF
-C182 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
-C183 DFlipFlop_2/nQ vss 0.50fF
-C184 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
-C185 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
-C186 DFlipFlop_2/latch_diff_1/D vss -1.72fF
-C187 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C188 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
-C189 DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C190 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C191 DFlipFlop_2/D vss 5.34fF
-C192 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C193 nQ2 vss 2.05fF
-C194 DFlipFlop_0/Q vss -0.94fF
-C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
-C196 nCLK vss 0.96fF
-C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C200 CLK vss 0.20fF
-C201 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
-C202 DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C204 DFlipFlop_0/D vss 4.04fF
-C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
-C206 vdd vss 146.76fF
-C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
-C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+C8 out_pad vss 0.70fF
+C9 out_div vss 3.00fF
.ends
.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
@@ -5962,29 +6606,29 @@
X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n317_n125# a_63_n125# 0.06fF
-C1 a_159_n125# a_63_n125# 0.36fF
-C2 a_255_n125# a_63_n125# 0.13fF
-C3 a_n33_n125# a_n129_n125# 0.36fF
-C4 a_n129_n125# a_n225_n125# 0.36fF
-C5 a_255_n125# a_159_n125# 0.36fF
-C6 a_n159_n151# a_n255_n151# 0.02fF
-C7 a_n33_n125# a_63_n125# 0.36fF
-C8 a_63_n125# a_n225_n125# 0.08fF
-C9 a_n317_n125# a_n33_n125# 0.08fF
+C0 a_33_n151# a_n63_n151# 0.02fF
+C1 a_159_n125# a_n33_n125# 0.13fF
+C2 a_129_n151# a_33_n151# 0.02fF
+C3 a_n33_n125# a_n317_n125# 0.08fF
+C4 a_159_n125# a_n129_n125# 0.08fF
+C5 a_n159_n151# a_n63_n151# 0.02fF
+C6 a_159_n125# a_63_n125# 0.36fF
+C7 a_n317_n125# a_n129_n125# 0.13fF
+C8 a_n317_n125# a_63_n125# 0.06fF
+C9 a_159_n125# a_n225_n125# 0.06fF
C10 a_n317_n125# a_n225_n125# 0.36fF
-C11 a_n33_n125# a_159_n125# 0.13fF
-C12 a_159_n125# a_n225_n125# 0.06fF
-C13 a_n33_n125# a_255_n125# 0.08fF
-C14 a_n129_n125# a_63_n125# 0.13fF
-C15 a_225_n151# a_129_n151# 0.02fF
-C16 a_n317_n125# a_n129_n125# 0.13fF
-C17 a_n33_n125# a_n225_n125# 0.13fF
-C18 a_159_n125# a_n129_n125# 0.08fF
-C19 a_33_n151# a_n63_n151# 0.02fF
+C11 a_159_n125# a_255_n125# 0.36fF
+C12 a_n33_n125# a_n129_n125# 0.36fF
+C13 a_n33_n125# a_63_n125# 0.36fF
+C14 a_n33_n125# a_n225_n125# 0.13fF
+C15 a_n129_n125# a_63_n125# 0.13fF
+C16 a_n129_n125# a_n225_n125# 0.36fF
+C17 a_n225_n125# a_63_n125# 0.08fF
+C18 a_255_n125# a_n33_n125# 0.08fF
+C19 a_129_n151# a_225_n151# 0.02fF
C20 a_255_n125# a_n129_n125# 0.06fF
-C21 a_33_n151# a_129_n151# 0.02fF
-C22 a_n63_n151# a_n159_n151# 0.02fF
+C21 a_255_n125# a_63_n125# 0.13fF
+C22 a_n255_n151# a_n159_n151# 0.02fF
C23 a_255_n125# w_n455_n335# 0.14fF
C24 a_159_n125# w_n455_n335# 0.08fF
C25 a_63_n125# w_n455_n335# 0.07fF
@@ -6009,36 +6653,36 @@
X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n159_n154# a_n255_n154# 0.02fF
-C1 w_n455_n344# a_63_n125# 0.04fF
-C2 a_n129_n125# a_n33_n125# 0.36fF
-C3 a_n317_n125# w_n455_n344# 0.11fF
-C4 a_n317_n125# a_63_n125# 0.06fF
-C5 a_255_n125# w_n455_n344# 0.11fF
-C6 a_255_n125# a_63_n125# 0.13fF
+C0 a_159_n125# w_n455_n344# 0.06fF
+C1 a_n225_n125# a_159_n125# 0.06fF
+C2 w_n455_n344# a_63_n125# 0.04fF
+C3 a_n225_n125# a_63_n125# 0.08fF
+C4 a_n129_n125# w_n455_n344# 0.04fF
+C5 a_n33_n125# w_n455_n344# 0.05fF
+C6 a_n225_n125# a_n129_n125# 0.36fF
C7 a_n225_n125# a_n33_n125# 0.13fF
-C8 a_159_n125# a_n33_n125# 0.13fF
-C9 a_n129_n125# w_n455_n344# 0.04fF
-C10 a_n129_n125# a_63_n125# 0.13fF
-C11 a_33_n154# a_129_n154# 0.02fF
-C12 a_225_n154# a_129_n154# 0.02fF
-C13 a_n317_n125# a_n129_n125# 0.13fF
-C14 a_n129_n125# a_255_n125# 0.06fF
-C15 a_n159_n154# a_n63_n154# 0.02fF
-C16 a_n225_n125# w_n455_n344# 0.06fF
-C17 a_n225_n125# a_63_n125# 0.08fF
-C18 a_159_n125# w_n455_n344# 0.06fF
-C19 a_159_n125# a_63_n125# 0.36fF
-C20 a_n317_n125# a_n225_n125# 0.36fF
-C21 a_159_n125# a_255_n125# 0.36fF
-C22 a_n63_n154# a_33_n154# 0.02fF
-C23 a_n129_n125# a_n225_n125# 0.36fF
-C24 a_159_n125# a_n129_n125# 0.08fF
-C25 w_n455_n344# a_n33_n125# 0.05fF
-C26 a_63_n125# a_n33_n125# 0.36fF
-C27 a_n317_n125# a_n33_n125# 0.08fF
-C28 a_255_n125# a_n33_n125# 0.08fF
-C29 a_159_n125# a_n225_n125# 0.06fF
+C8 a_255_n125# w_n455_n344# 0.11fF
+C9 a_n317_n125# w_n455_n344# 0.11fF
+C10 a_n225_n125# a_n317_n125# 0.36fF
+C11 a_n63_n154# a_n159_n154# 0.02fF
+C12 a_33_n154# a_129_n154# 0.02fF
+C13 a_n63_n154# a_33_n154# 0.02fF
+C14 a_159_n125# a_63_n125# 0.36fF
+C15 a_n255_n154# a_n159_n154# 0.02fF
+C16 a_159_n125# a_n129_n125# 0.08fF
+C17 a_n33_n125# a_159_n125# 0.13fF
+C18 a_255_n125# a_159_n125# 0.36fF
+C19 a_n225_n125# w_n455_n344# 0.06fF
+C20 a_n129_n125# a_63_n125# 0.13fF
+C21 a_n33_n125# a_63_n125# 0.36fF
+C22 a_255_n125# a_63_n125# 0.13fF
+C23 a_n317_n125# a_63_n125# 0.06fF
+C24 a_n33_n125# a_n129_n125# 0.36fF
+C25 a_255_n125# a_n129_n125# 0.06fF
+C26 a_255_n125# a_n33_n125# 0.08fF
+C27 a_n129_n125# a_n317_n125# 0.13fF
+C28 a_n33_n125# a_n317_n125# 0.08fF
+C29 a_225_n154# a_129_n154# 0.02fF
C30 a_255_n125# VSUBS 0.03fF
C31 a_159_n125# VSUBS 0.03fF
C32 a_63_n125# VSUBS 0.03fF
@@ -6060,35 +6704,35 @@
+ sky130_fd_pr__nfet_01v8_AZESM8
Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
+ in sky130_fd_pr__pfet_01v8_XJXT7S
-C0 out vdd 0.29fF
+C0 vdd out 0.29fF
C1 out in 0.85fF
-C2 in vdd 0.04fF
+C2 vdd in 0.04fF
C3 vdd vss 5.90fF
C4 out vss 1.30fF
C5 in vss 1.82fF
.ends
-.subckt pfd_cp_interface vss vdd inverter_cp_x1_0/out inverter_cp_x1_2/in Down QA
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
+ QB nDown Up nUp
Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
-Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xtrans_gate_0 nDown vss inverter_cp_x1_0/out vdd trans_gate
Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
-Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
-C0 inverter_cp_x1_2/in vdd 0.42fF
-C1 Down vdd 0.09fF
-C2 vdd nUp 0.14fF
-C3 Down inverter_cp_x1_0/out 0.12fF
-C4 inverter_cp_x1_2/in Up 0.12fF
-C5 nDown Down 0.23fF
-C6 vdd inverter_cp_x1_0/out 0.25fF
-C7 nDown vdd 0.80fF
-C8 nUp Up 0.20fF
-C9 vdd Up 0.60fF
-C10 vdd QB 0.02fF
-C11 nDown inverter_cp_x1_0/out 0.11fF
-C12 QA vdd 0.02fF
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 vdd QB 0.02fF
+C1 vdd QA 0.02fF
+C2 Up inverter_cp_x1_2/in 0.12fF
+C3 Up nUp 0.20fF
+C4 vdd Up 0.60fF
+C5 Down vdd 0.09fF
+C6 Down nDown 0.23fF
+C7 Down inverter_cp_x1_0/out 0.12fF
+C8 vdd inverter_cp_x1_2/in 0.42fF
+C9 vdd nUp 0.14fF
+C10 vdd nDown 0.80fF
+C11 vdd inverter_cp_x1_0/out 0.25fF
+C12 inverter_cp_x1_0/out nDown 0.11fF
C13 inverter_cp_x1_2/in vss 2.01fF
C14 QA vss 1.09fF
C15 inverter_cp_x1_0/out vss 2.00fF
@@ -6106,22 +6750,22 @@
X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
-C0 a_n33_n90# a_63_n90# 0.26fF
-C1 a_159_n90# a_n129_n90# 0.06fF
-C2 a_n221_n90# w_n359_n309# 0.09fF
-C3 a_n33_n90# a_159_n90# 0.09fF
-C4 a_n221_n90# a_63_n90# 0.06fF
-C5 w_n359_n309# a_63_n90# 0.06fF
-C6 a_n221_n90# a_159_n90# 0.04fF
-C7 a_159_n90# w_n359_n309# 0.09fF
-C8 a_n33_n90# a_n129_n90# 0.26fF
-C9 a_159_n90# a_63_n90# 0.26fF
-C10 a_n221_n90# a_n129_n90# 0.26fF
-C11 a_n159_n207# a_n63_n116# 0.12fF
-C12 a_n129_n90# w_n359_n309# 0.06fF
-C13 a_n221_n90# a_n33_n90# 0.09fF
-C14 a_n33_n90# w_n359_n309# 0.05fF
-C15 a_n129_n90# a_63_n90# 0.09fF
+C0 a_n129_n90# w_n359_n309# 0.06fF
+C1 a_n129_n90# a_159_n90# 0.06fF
+C2 w_n359_n309# a_159_n90# 0.09fF
+C3 a_63_n90# a_n129_n90# 0.09fF
+C4 a_63_n90# w_n359_n309# 0.06fF
+C5 a_63_n90# a_159_n90# 0.26fF
+C6 a_n33_n90# a_n221_n90# 0.09fF
+C7 a_n129_n90# a_n33_n90# 0.26fF
+C8 a_n33_n90# w_n359_n309# 0.05fF
+C9 a_n33_n90# a_159_n90# 0.09fF
+C10 a_n159_n207# a_n63_n116# 0.12fF
+C11 a_n129_n90# a_n221_n90# 0.26fF
+C12 a_63_n90# a_n33_n90# 0.26fF
+C13 a_n221_n90# w_n359_n309# 0.09fF
+C14 a_n221_n90# a_159_n90# 0.04fF
+C15 a_63_n90# a_n221_n90# 0.06fF
C16 a_159_n90# VSUBS 0.03fF
C17 a_63_n90# VSUBS 0.03fF
C18 a_n33_n90# VSUBS 0.03fF
@@ -6136,10 +6780,10 @@
+ a_n125_n45# a_63_n45#
X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
-C0 a_n33_n45# a_n125_n45# 0.13fF
-C1 a_33_n71# a_n129_71# 0.04fF
-C2 a_n33_n45# a_63_n45# 0.13fF
-C3 a_n125_n45# a_63_n45# 0.05fF
+C0 a_n33_n45# a_63_n45# 0.13fF
+C1 a_n33_n45# a_n125_n45# 0.13fF
+C2 a_n125_n45# a_63_n45# 0.05fF
+C3 a_n129_71# a_33_n71# 0.04fF
C4 a_63_n45# w_n263_n255# 0.04fF
C5 a_n33_n45# w_n263_n255# 0.04fF
C6 a_n125_n45# w_n263_n255# 0.04fF
@@ -6147,19 +6791,19 @@
C8 a_n129_71# w_n263_n255# 0.14fF
.ends
-.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
-+ vss vdd A B
+.subckt nor_pfd vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss A B
Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
+ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
-C0 out vdd 0.11fF
-C1 A out 0.06fF
-C2 A vdd 0.09fF
-C3 B out 0.40fF
-C4 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
-C5 A B 0.24fF
-C6 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
-C7 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C0 out A 0.06fF
+C1 B A 0.24fF
+C2 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
+C3 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C4 vdd A 0.09fF
+C5 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C6 B out 0.40fF
+C7 vdd out 0.11fF
C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C9 out vss 0.45fF
C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
@@ -6168,46 +6812,46 @@
C13 vdd vss 3.79fF
.ends
-.subckt dff_pfd vdd vss nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
-Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
-+ vss vdd CLK Q nor_pfd
-Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
-+ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
-Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
-+ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
-Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
-+ vss vdd nor_pfd_3/A Reset nor_pfd
-C0 Reset Q 0.14fF
-C1 Reset nor_pfd_3/A 0.12fF
-C2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
-C3 CLK Q 0.04fF
-C4 nor_pfd_2/B Q 2.22fF
-C5 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
-C6 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
-C7 nor_pfd_2/B vdd 0.02fF
-C8 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
-C9 nor_pfd_2/B nor_pfd_3/A 0.58fF
-C10 vdd Q 0.08fF
-C11 nor_pfd_3/A Q 0.98fF
-C12 nor_pfd_3/A vdd 0.09fF
+.subckt dff_pfd vdd vss nor_pfd_2/A Q CLK nor_pfd_3/A Reset nor_pfd_2/B
+Xnor_pfd_0 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss CLK Q nor_pfd
+Xnor_pfd_1 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_3/A Reset nor_pfd
+C0 Q vdd 0.08fF
+C1 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C2 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C3 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C4 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C5 vdd nor_pfd_2/B 0.02fF
+C6 Q Reset 0.14fF
+C7 Q nor_pfd_2/B 2.22fF
+C8 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C9 Reset nor_pfd_2/B 0.43fF
+C10 Q CLK 0.04fF
+C11 vdd nor_pfd_3/A 0.09fF
+C12 vdd nor_pfd_2/A -0.01fF
C13 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
-C14 nor_pfd_2/B nor_pfd_2/A 0.05fF
-C15 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
-C16 nor_pfd_2/A Q 1.38fF
-C17 nor_pfd_2/A vdd -0.01fF
-C18 nor_pfd_3/A nor_pfd_2/A 0.38fF
-C19 Reset nor_pfd_2/B 0.43fF
+C14 Q nor_pfd_3/A 0.98fF
+C15 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C16 Q nor_pfd_2/A 1.38fF
+C17 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C18 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C19 nor_pfd_3/A Reset 0.12fF
C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C21 nor_pfd_2/B vss 1.42fF
C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C23 Reset vss 1.48fF
-C24 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C26 nor_pfd_2/A vss 2.56fF
-C27 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C28 Q vss 2.77fF
-C29 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C30 nor_pfd_3/A vss 3.16fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C31 vdd vss 16.42fF
C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
@@ -6220,17 +6864,17 @@
X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
-C0 a_n129_n45# a_n221_n45# 0.13fF
-C1 a_n159_n173# a_n63_n71# 0.10fF
-C2 a_n129_n45# a_159_n45# 0.03fF
+C0 a_n221_n45# a_63_n45# 0.03fF
+C1 a_n33_n45# a_63_n45# 0.13fF
+C2 a_63_n45# a_159_n45# 0.13fF
C3 a_n33_n45# a_n221_n45# 0.05fF
-C4 a_n33_n45# a_159_n45# 0.05fF
-C5 a_63_n45# a_n129_n45# 0.05fF
-C6 a_159_n45# a_n221_n45# 0.02fF
-C7 a_63_n45# a_n33_n45# 0.13fF
-C8 a_63_n45# a_n221_n45# 0.03fF
-C9 a_63_n45# a_159_n45# 0.13fF
-C10 a_n129_n45# a_n33_n45# 0.13fF
+C4 a_n129_n45# a_63_n45# 0.05fF
+C5 a_n221_n45# a_159_n45# 0.02fF
+C6 a_n129_n45# a_n221_n45# 0.13fF
+C7 a_n159_n173# a_n63_n71# 0.10fF
+C8 a_n33_n45# a_159_n45# 0.05fF
+C9 a_n129_n45# a_n33_n45# 0.13fF
+C10 a_n129_n45# a_159_n45# 0.03fF
C11 a_159_n45# w_n359_n255# 0.04fF
C12 a_63_n45# w_n359_n255# 0.05fF
C13 a_n33_n45# w_n359_n255# 0.05fF
@@ -6244,10 +6888,10 @@
+ a_n33_n90# w_n263_n309#
X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
-C0 a_n33_n90# a_63_n90# 0.26fF
-C1 a_n33_n90# a_n125_n90# 0.26fF
-C2 a_n99_n187# a_33_n187# 0.04fF
-C3 a_n125_n90# a_63_n90# 0.09fF
+C0 a_n125_n90# a_63_n90# 0.09fF
+C1 a_63_n90# a_n33_n90# 0.26fF
+C2 a_n125_n90# a_n33_n90# 0.26fF
+C3 a_n99_n187# a_33_n187# 0.04fF
C4 a_63_n90# VSUBS 0.03fF
C5 a_n33_n90# VSUBS 0.03fF
C6 a_n125_n90# VSUBS 0.03fF
@@ -6258,7 +6902,7 @@
.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
-C0 a_15_n45# a_n73_n45# 0.16fF
+C0 a_n73_n45# a_15_n45# 0.16fF
C1 a_15_n45# w_n211_n255# 0.08fF
C2 a_n73_n45# w_n211_n255# 0.06fF
C3 a_n33_67# w_n211_n255# 0.10fF
@@ -6266,9 +6910,9 @@
.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
-C0 w_n211_n309# a_n73_n90# 0.04fF
-C1 w_n211_n309# a_15_n90# 0.09fF
-C2 a_n73_n90# a_15_n90# 0.31fF
+C0 a_n73_n90# w_n211_n309# 0.04fF
+C1 a_15_n90# w_n211_n309# 0.09fF
+C2 a_15_n90# a_n73_n90# 0.31fF
C3 a_15_n90# VSUBS 0.03fF
C4 a_n73_n90# VSUBS 0.03fF
C5 a_n51_n187# VSUBS 0.12fF
@@ -6281,16 +6925,16 @@
Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
-C0 vdd A 0.05fF
-C1 a_656_410# A 0.04fF
-C2 B A 0.33fF
-C3 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
-C4 out sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.03fF
-C5 a_656_410# vdd 0.20fF
-C6 a_656_410# B 0.30fF
-C7 out vdd 0.10fF
-C8 out a_656_410# 0.20fF
-C9 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C0 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C1 A vdd 0.05fF
+C2 a_656_410# B 0.30fF
+C3 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C4 a_656_410# out 0.20fF
+C5 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C6 out vdd 0.10fF
+C7 A B 0.33fF
+C8 a_656_410# vdd 0.20fF
+C9 A a_656_410# 0.04fF
C10 vdd vss 4.85fF
C11 out vss 0.47fF
C12 a_656_410# vss 1.00fF
@@ -6300,230 +6944,538 @@
C16 B vss 0.95fF
.ends
-.subckt PFD vss vdd Down Up A B Reset
-Xdff_pfd_0 vdd vss dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
-+ Reset dff_pfd
-Xdff_pfd_1 vdd vss dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
-+ Reset dff_pfd
+.subckt PFD vss vdd Reset Down Up A B
+Xdff_pfd_0 vdd vss dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A Reset dff_pfd_0/nor_pfd_2/B
++ dff_pfd
+Xdff_pfd_1 vdd vss dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A Reset dff_pfd_1/nor_pfd_2/B
++ dff_pfd
Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
-C0 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
-C1 vdd Reset 0.02fF
-C2 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C0 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C1 vdd Down 0.08fF
+C2 Down Up 0.06fF
C3 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
-C4 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
-C5 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
-C6 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
-C7 Up vdd 1.62fF
-C8 Down vdd 0.08fF
-C9 Down Up 0.06fF
+C4 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C5 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
+C6 vdd Reset 0.02fF
+C7 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C8 vdd Up 1.62fF
+C9 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
C10 and_pfd_0/a_656_410# vss 0.99fF
C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C16 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C18 dff_pfd_1/nor_pfd_2/A vss 2.56fF
-C19 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C20 Down vss 3.74fF
-C21 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C22 dff_pfd_1/nor_pfd_3/A vss 3.14fF
-C23 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C25 B vss 1.07fF
-C26 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C27 dff_pfd_0/nor_pfd_2/B vss 1.40fF
-C28 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C29 Reset vss 3.85fF
-C30 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C31 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C32 dff_pfd_0/nor_pfd_2/A vss 2.56fF
-C33 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C34 Up vss 3.18fF
-C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C36 dff_pfd_0/nor_pfd_3/A vss 3.14fF
-C37 vdd vss 44.73fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C40 A vss 1.07fF
.ends
-.subckt top_pll_v1 vco_vctrl vdd pswitch ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
-+ charge_pump_0/w_2544_775# ring_osc_0/csvco_branch_2/vbp biasp in_ref Down vss w_13905_n238#
-+ vco_D0 buffer_salida_0/a_3996_n100# ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
-+ QA charge_pump_0/w_1008_774# iref_cp ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
-+ out_to_div nDown out_to_pad Up nUp
+.subckt top_pll_v3 clk_d vdd s_0 charge_pump_0/w_2544_775# out_by_2 s_0_n in_ref ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ buffer_salida_0/a_3996_n100# vss vco_vctrl s_1 ring_osc_0/csvco_branch_2/vbp lf_vc
++ vco_D0 lf_D0 buffer_salida_0/a_678_n100# ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ loop_filter_v2_0/cap3_loop_filter_0/in charge_pump_0/w_1008_774# iref_cp ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
++ Down out_to_div clk_1 out_div nDown s_1_n out_to_pad MC Up clk_0 freq_div_0/prescaler_23_0/nCLK_23
++ biasp nUp n_clk_0
+Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
++ iref_cp nDown Up charge_pump_0/w_1008_774# vss charge_pump
+Xdiv_by_2_0 vss vdd n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2
++ n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_2
+Xloop_filter_v2_0 lf_vc lf_D0 vco_vctrl vss loop_filter_v2_0/cap3_loop_filter_0/in
++ loop_filter_v2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# buffer_salida_0/a_3996_n100# out_to_pad
++ vdd out_to_buffer vss buffer_salida
+Xfreq_div_0 clk_0 vss out_by_2 n_clk_0 vdd freq_div_0/prescaler_23_0/Q2 s_0 s_1_n
++ s_1 freq_div_0/prescaler_23_0/nCLK_23 MC clk_d freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280#
++ s_0_n clk_pre freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out_div freq_div_0/div_by_5_0/Q1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ clk_2_f n_out_by_2 clk_5 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D freq_div
+Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl vss ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd ring_osc_0/csvco_branch_2/vbp
++ ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t
++ vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div PFD
+C0 pswitch nDown 0.53fF
+C1 nDown nUp -0.09fF
+C2 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D 0.53fF
+C3 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD 1.23fF
+C4 charge_pump_0/w_2544_775# nDown 0.05fF
+C5 s_1_n out_div 0.10fF
+C6 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.65fF
+C7 vdd QA -0.04fF
+C8 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vco_vctrl 0.82fF
+C9 pswitch Up 1.98fF
+C10 Up nUp 2.72fF
+C11 vco_vctrl freq_div_0/prescaler_23_0/nCLK_23 0.06fF
+C12 vdd clk_0 0.13fF
+C13 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C14 vdd nDown 0.22fF
+C15 s_0_n n_out_by_2 0.14fF
+C16 vco_vctrl n_clk_1 0.23fF
+C17 clk_d out_div 0.64fF
+C18 s_0 out_to_div 0.94fF
+C19 pswitch nUp 0.93fF
+C20 vco_D0 vdd 0.03fF
+C21 clk_1 n_out_by_2 -0.10fF
+C22 nswitch nDown 0.76fF
+C23 lf_vc MC 0.20fF
+C24 vco_vctrl clk_0 -0.26fF
+C25 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C26 vdd Up 0.28fF
+C27 out_div s_1 0.37fF
+C28 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C29 s_0 n_out_by_2 0.14fF
+C30 out_to_div out_to_buffer 0.13fF
+C31 iref_cp Down 0.09fF
+C32 biasp Down 1.24fF
+C33 nDown Down 2.55fF
+C34 vdd nUp 0.05fF
+C35 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C36 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C37 vco_vctrl MC 0.33fF
+C38 vco_vctrl freq_div_0/div_by_5_0/Q1 0.10fF
+C39 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D 0.09fF
+C40 buffer_salida_0/a_678_n100# vdd 0.24fF
+C41 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD -0.42fF
+C42 charge_pump_0/w_2544_775# Down -0.23fF
+C43 vco_vctrl s_0_n 0.34fF
+C44 vco_vctrl vdd 0.82fF
+C45 vco_vctrl clk_1 -0.04fF
+C46 biasp nDown 0.26fF
+C47 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C48 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vco_vctrl -0.42fF
+C49 buffer_salida_0/a_678_n100# out_to_buffer 0.21fF
+C50 vdd out_to_buffer 0.07fF
+C51 vco_vctrl s_0 0.45fF
+C52 nswitch Down 0.54fF
+C53 biasp Up 0.26fF
+C54 vco_vctrl freq_div_0/prescaler_23_0/Q2 0.06fF
+C55 vco_vctrl freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.15fF
+C56 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# 0.34fF
+C57 vco_vctrl freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD 0.09fF
+C58 out_by_2 n_out_by_2 0.27fF
+C59 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vco_vctrl 0.17fF
+C60 biasp nUp -0.16fF
+C61 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C62 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C63 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C64 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C65 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C66 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C67 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C68 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C69 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C70 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C71 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C72 QB vss 3.15fF
+C73 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C74 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C75 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C76 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C77 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C78 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C79 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C80 pfd_reset vss 1.87fF
+C81 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C82 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C83 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C84 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C85 QA vss 3.49fF
+C86 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C87 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C88 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C89 in_ref vss 0.84fF
+C90 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C91 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C92 nUp vss 0.12fF
+C93 Up vss -4.26fF
+C94 Down vss 1.89fF
+C95 nDown vss 2.80fF
+C96 out_first_buffer vss 2.15fF
+C97 out_to_buffer vss 1.92fF
+C98 out_to_div vss 8.72fF
+C99 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C100 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C101 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C102 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C103 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C104 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C105 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C106 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C107 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C108 vco_out vss 1.65fF
+C109 vco_D0 vss -4.72fF
+C110 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C111 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C112 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C113 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C114 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C115 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C116 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C117 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C118 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C119 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C120 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C121 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C122 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C123 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C124 freq_div_0/prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C125 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C126 freq_div_0/prescaler_23_0/Q2_d vss -0.69fF
+C127 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C128 freq_div_0/prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C129 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C130 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C131 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C132 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C133 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C134 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C135 freq_div_0/prescaler_23_0/Q2 vss 0.55fF
+C136 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C137 freq_div_0/prescaler_23_0/Q1 vss 0.07fF
+C138 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C139 n_clk_0 vss -7.01fF
+C140 freq_div_0/prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C141 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C142 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C143 clk_0 vss -0.37fF
+C144 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C145 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C146 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C147 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C148 freq_div_0/prescaler_23_0/nCLK_23 vss -1.02fF
+C149 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C150 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C151 MC vss -1.42fF
+C152 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C153 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C154 n_out_by_2 vss 4.87fF
+C155 s_0_n vss -4.09fF
+C156 out_by_2 vss 4.52fF
+C157 s_0 vss 5.50fF
+C158 freq_div_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C159 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C160 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 freq_div_0/div_by_5_0/Q1_shift vss -0.36fF
+C162 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C163 freq_div_0/div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C164 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C165 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C166 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C168 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C169 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C170 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 freq_div_0/div_by_5_0/Q1 vss 4.35fF
+C172 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C173 freq_div_0/div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C174 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C175 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C176 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C177 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C178 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C179 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 freq_div_0/div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C181 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 freq_div_0/div_by_5_0/Q0 vss 0.29fF
+C183 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C184 freq_div_0/div_by_5_0/nQ0 vss 0.99fF
+C185 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C186 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C187 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C188 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C190 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C191 freq_div_0/div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C192 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 freq_div_0/div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C194 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C195 n_clk_1 vss -0.56fF
+C196 freq_div_0/div_by_5_0/nQ2 vss 1.38fF
+C197 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C198 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C199 clk_1 vss -2.21fF
+C200 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C202 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C203 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 freq_div_0/div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C205 vdd vss 587.93fF
+C206 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C207 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C209 s_1_n vss -2.04fF
+C210 out_div vss 3.70fF
+C211 clk_d vss 1.27fF
+C212 s_1 vss 1.72fF
+C213 freq_div_0/inverter_min_x4_0/in vss 2.71fF
+C214 clk_5 vss -0.22fF
+C215 clk_out_mux21 vss 3.89fF
+C216 clk_pre vss 1.69fF
+C217 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C218 freq_div_0/div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C219 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C220 freq_div_0/div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 clk_2_f vss 3.30fF
+C222 freq_div_0/div_by_2_0/o1 vss 2.08fF
+C223 freq_div_0/div_by_2_0/nCLK_2 vss 1.04fF
+C224 freq_div_0/div_by_2_0/o2 vss 2.08fF
+C225 freq_div_0/div_by_2_0/out_div vss -0.82fF
+C226 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C227 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C228 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C229 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C230 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C231 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C232 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C233 freq_div_0/div_by_2_0/nout_div vss 2.62fF
+C234 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C235 out_to_pad vss 7.15fF
+C236 buffer_salida_0/a_3996_n100# vss 48.29fF
+C237 buffer_salida_0/a_678_n100# vss 13.38fF
+C238 lf_vc vss -60.88fF
+C239 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C240 lf_D0 vss 0.01fF
+C241 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C242 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C243 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C244 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C245 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C246 out_buffer_div_2 vss 1.57fF
+C247 n_out_buffer_div_2 vss 1.57fF
+C248 out_div_2 vss -0.70fF
+C249 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C250 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C251 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C252 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C253 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C254 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C255 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C256 n_out_div_2 vss 2.11fF
+C257 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C258 nswitch vss 4.61fF
+C259 biasp vss 5.46fF
+C260 iref_cp vss 2.44fF
+C261 vco_vctrl vss -30.24fF
+C262 pswitch vss 2.72fF
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 vc_pex vss -38.13fF
+C2 res_loop_filter_2/out vss 8.49fF
+C3 in vss -18.79fF
+.ends
+
+.subckt top_pll_v1 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vdd charge_pump_0/w_2544_775#
++ pswitch biasp ring_osc_0/csvco_branch_2/vbp in_ref Down w_13905_n238# vss vco_D0
++ QA ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd iref_cp out_to_div nDown out_to_pad
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd Up nUp
Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
-+ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
-Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
-+ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump_0/w_6648_570# charge_pump
+Xdiv_by_2_0 vss vdd n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2
++ n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
+ div_by_2
-Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
-+ vss vdd buffer_salida
-Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
-+ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd vss ring_osc_0/csvco_branch_2/vbp
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# buffer_salida_0/a_3996_n100# out_to_pad
++ vdd out_to_buffer vss buffer_salida
+Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl vss ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd ring_osc_0/csvco_branch_2/vbp
+ ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t
+ vco_out ring_osc
Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
-+ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
-+ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
-+ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_0/latch_diff_1/nD
++ vss vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_5_Q1 out_by_2 div_by_5_0/DFlipFlop_0/Q
++ div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ out_div_by_5 div_5_Q1_shift div_5_nQ2 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_2/latch_diff_1/nD
+ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
-+ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
+ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
-+ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
-+ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
-+ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
-+ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_2/latch_diff_0/D
+ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
+ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
+ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
-+ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
+ div_by_5
-Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
+ Down QA QB nDown Up nUp pfd_cp_interface
-XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
-C0 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
-C1 div_5_nQ2 out_by_2 0.16fF
-C2 Up biasp 0.26fF
-C3 QA vdd -0.04fF
-C4 Down iref_cp 0.09fF
-C5 div_5_Q1 vco_vctrl 0.14fF
-C6 vco_vctrl div_5_Q0 0.48fF
-C7 div_5_Q1 out_div_by_5 0.01fF
-C8 vco_vctrl nswitch -0.06fF
-C9 nUp vdd 0.05fF
-C10 nDown vdd 0.22fF
-C11 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
-C12 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
-C13 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
-C14 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
-C15 vco_D0 vdd 0.03fF
-C16 pswitch Up 1.98fF
-C17 nDown nUp -0.09fF
-C18 n_out_by_2 vco_vctrl 0.52fF
-C19 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
-C20 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
-C21 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
-C22 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
-C23 div_by_5_0/DFlipFlop_3/latch_diff_0/D out_by_2 0.11fF
-C24 buffer_salida_0/a_678_n100# out_to_buffer 0.22fF
-C25 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
-C26 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
-C27 out_to_div out_to_buffer 0.13fF
-C28 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
-C29 Up vdd 0.28fF
-C30 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
-C31 nDown Down 2.55fF
-C32 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
-C33 out_by_2 vco_vctrl 0.53fF
-C34 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
-C35 Up nUp 2.72fF
-C36 nswitch nDown 0.76fF
-C37 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
-C38 vdd lf_vc 0.02fF
-C39 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
-C40 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
-C41 n_out_by_2 vdd 1.03fF
-C42 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
-C43 out_div_by_5 div_5_Q1_shift 0.05fF
-C44 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
-C45 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
-C46 buffer_salida_0/a_678_n100# vdd 0.24fF
-C47 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
-C48 nswitch Down 0.54fF
-C49 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
-C50 out_to_div vdd 0.21fF
-C51 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
-C52 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
-C53 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
-C54 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
-C55 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
-C56 out_by_2 vdd 0.97fF
-C57 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
-C58 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
-C59 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
-C60 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
-C61 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
-C62 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 0.27fF
-C63 n_out_by_2 div_5_nQ0 0.10fF
-C64 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
-C65 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
-C66 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
-C67 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
-C68 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
-C69 div_5_Q1 n_out_by_2 1.04fF
-C70 n_out_by_2 div_5_Q0 -0.12fF
-C71 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
-C72 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
-C73 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.17fF
-C74 vdd out_to_buffer 0.07fF
-C75 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
-C76 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
-C77 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
-C78 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
-C79 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
-C80 vco_vctrl vdd -1.02fF
-C81 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
-C82 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
-C83 out_div_by_5 vdd 0.28fF
-C84 nUp biasp -0.17fF
-C85 nDown biasp 0.26fF
-C86 vdd iref_cp 0.15fF
-C87 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
-C88 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
-C89 out_by_2 div_5_nQ0 0.32fF
-C90 vco_vctrl nUp 0.02fF
-C91 n_out_by_2 div_5_nQ2 0.10fF
-C92 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
-C93 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
-C94 div_by_5_0/DFlipFlop_0/Q out_by_2 0.09fF
-C95 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
-C96 div_5_Q1 out_by_2 0.42fF
-C97 out_by_2 div_5_Q0 0.09fF
-C98 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
-C99 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
-C100 pswitch nUp 0.85fF
-C101 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
-C102 pswitch nDown 0.53fF
-C103 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
-C104 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
-C105 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
-C106 Down biasp 1.24fF
-C107 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div_by_5 PFD
+C0 div_5_nQ2 n_out_by_2 0.10fF
+C1 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C2 div_5_nQ2 out_by_2 0.16fF
+C3 lf_vc vdd 0.02fF
+C4 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
+C5 nDown biasp 0.26fF
+C6 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C7 vdd out_to_buffer 0.07fF
+C8 vdd nUp 0.05fF
+C9 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C10 Down iref_cp 0.09fF
+C11 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.17fF
+C12 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C13 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_to_div -0.16fF
+C14 out_to_div vdd 0.21fF
+C15 biasp Down 1.24fF
+C16 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
+C17 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.33fF
+C18 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
+C19 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C20 nDown Down 2.55fF
+C21 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C22 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C23 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
+C24 buffer_salida_0/a_678_n100# vdd 0.24fF
+C25 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
+C26 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# n_out_by_2 0.01fF
+C27 n_out_by_2 div_5_Q0 -0.12fF
+C28 vdd Up 0.28fF
+C29 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C30 n_out_by_2 div_5_Q1 1.04fF
+C31 pswitch nUp 0.85fF
+C32 out_by_2 div_5_Q0 0.09fF
+C33 out_by_2 div_5_Q1 0.42fF
+C34 out_div_by_5 div_5_Q1_shift 0.05fF
+C35 out_to_div out_to_buffer 0.13fF
+C36 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C37 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
+C38 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
+C39 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C40 buffer_salida_0/a_678_n100# out_to_buffer 0.22fF
+C41 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
+C42 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
+C43 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C44 vdd iref_cp 0.15fF
+C45 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
+C46 div_5_Q0 vco_vctrl 0.48fF
+C47 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C48 pswitch Up 1.98fF
+C49 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
+C50 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C51 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C52 n_out_by_2 vco_vctrl 0.52fF
+C53 vco_vctrl div_5_Q1 0.14fF
+C54 Up nUp 2.72fF
+C55 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
+C56 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
+C57 nDown vdd 0.22fF
+C58 out_by_2 vco_vctrl 0.53fF
+C59 div_5_nQ0 n_out_by_2 0.10fF
+C60 vco_D0 vdd 0.03fF
+C61 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
+C62 div_5_nQ0 out_by_2 0.32fF
+C63 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C64 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C65 n_out_by_2 vdd 1.03fF
+C66 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C67 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C68 out_by_2 vdd 0.97fF
+C69 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
+C70 nDown nswitch 0.76fF
+C71 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
+C72 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C73 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C74 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
+C75 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C76 out_div_by_5 div_5_Q1 0.01fF
+C77 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C78 biasp nUp -0.17fF
+C79 nDown pswitch 0.53fF
+C80 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
+C81 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C82 Down nswitch 0.54fF
+C83 nDown nUp -0.09fF
+C84 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
+C85 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C86 out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.09fF
+C87 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C88 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C89 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
+C90 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C91 vdd vco_vctrl -1.02fF
+C92 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C93 biasp Up 0.26fF
+C94 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C95 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C96 vco_vctrl nswitch -0.06fF
+C97 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C98 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C99 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C100 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
+C101 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C102 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C103 out_div_by_5 vdd 0.28fF
+C104 nUp vco_vctrl 0.02fF
+C105 QA vdd -0.04fF
+C106 div_by_5_0/DFlipFlop_3/latch_diff_0/D out_by_2 0.11fF
+C107 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
-C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C118 QB vss 4.46fF
-C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.46fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C123 out_div_by_5 vss -0.40fF
C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C127 pfd_reset vss 2.17fF
-C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
-C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C132 QA vss 4.31fF
-C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.31fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C137 in_ref vss 1.19fF
@@ -6536,57 +7488,57 @@
C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
-C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
-C148 div_5_Q1_shift vss -0.14fF
-C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
-C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
-C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
-C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C147 div_5_Q1_shift vss -0.14fF
+C148 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C149 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C156 div_5_Q1 vss 4.28fF
-C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C158 div_5_nQ0 vss 0.59fF
-C159 div_5_Q0 vss 0.01fF
-C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
-C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
-C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
-C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
-C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
-C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
-C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
-C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
-C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C179 div_5_nQ2 vss 1.24fF
-C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
-C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
-C182 n_out_by_2 vss -2.62fF
-C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C186 out_by_2 vss -4.51fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_5_Q1 vss 4.28fF
+C158 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C159 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C164 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_Q0 vss 0.01fF
+C169 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C170 div_5_nQ0 vss 0.59fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C180 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C181 n_out_by_2 vss -2.62fF
+C182 div_5_nQ2 vss 1.24fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C185 out_by_2 vss -4.51fF
+C186 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
-C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
-C192 vdd vss 366.82fF
+C191 vdd vss 366.82fF
+C192 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
C195 out_first_buffer vss 2.88fF
-C196 out_to_div vss 4.46fF
-C197 out_to_buffer vss 1.57fF
+C196 out_to_buffer vss 1.57fF
+C197 out_to_div vss 4.46fF
C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -6601,8 +7553,8 @@
C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
-C212 buffer_salida_0/a_3996_n100# vss 48.29fF
-C213 out_to_pad vss 7.50fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
C214 buffer_salida_0/a_678_n100# vss 13.38fF
C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
@@ -6612,9 +7564,9 @@
C220 n_out_buffer_div_2 vss 1.63fF
C221 out_div_2 vss -1.30fF
C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
-C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
@@ -6631,7 +7583,7 @@
.subckt sky130_fd_pr__cap_mim_m3_2_2Y8F6P VSUBS c2_n3251_n3000# m4_n3351_n3100#
X0 c2_n3251_n3000# m4_n3351_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
-C0 m4_n3351_n3100# c2_n3251_n3000# 72.82fF
+C0 c2_n3251_n3000# m4_n3351_n3100# 72.82fF
C1 m4_n3351_n3100# VSUBS 14.58fF
.ends
@@ -6687,16 +7639,16 @@
X47 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
X48 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
-C0 a_n2017_n61# w_n2018_n202# 1.37fF
-C1 a_n1879_n1219# a_n1731_n1219# 19.29fF
-C2 a_n2017_n1317# a_n1731_n1219# 4.73fF
-C3 a_n2017_n1317# a_n1879_n1219# 2.66fF
-C4 a_n2017_n61# a_n1731_n1219# 5.23fF
-C5 a_n2017_n61# a_n1879_n1219# 0.16fF
-C6 a_n2017_n61# a_n2017_n1317# 2.88fF
-C7 w_n2018_n202# a_n1731_n1219# 19.90fF
-C8 w_n2018_n202# a_n1879_n1219# 0.25fF
-C9 w_n2018_n202# a_n2017_n1317# 0.16fF
+C0 a_n2017_n61# a_n2017_n1317# 2.88fF
+C1 a_n1879_n1219# w_n2018_n202# 0.25fF
+C2 a_n1731_n1219# a_n1879_n1219# 19.29fF
+C3 w_n2018_n202# a_n2017_n1317# 0.16fF
+C4 a_n1731_n1219# a_n2017_n1317# 4.73fF
+C5 a_n2017_n61# w_n2018_n202# 1.37fF
+C6 a_n2017_n61# a_n1731_n1219# 5.23fF
+C7 a_n1879_n1219# a_n2017_n1317# 2.66fF
+C8 a_n1731_n1219# w_n2018_n202# 19.90fF
+C9 a_n2017_n61# a_n1879_n1219# 0.16fF
C10 a_n1879_n1219# VSUBS 1.53fF
C11 a_n2017_n1317# VSUBS 5.03fF
C12 a_n1731_n1219# VSUBS 2.60fF
@@ -6727,57 +7679,57 @@
+ iref_3 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
Xsky130_fd_pr__pfet_01v8_lvt_8P223X_4 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219#
+ iref_4 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
-C0 iref_2 iref_3 0.05fF
-C1 iref_5 iref_6 0.05fF
-C2 iref_9 iref -0.01fF
-C3 iref_7 iref_6 0.05fF
-C4 vdd iref -0.07fF
-C5 iref_5 iref 0.05fF
-C6 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# 0.24fF
-C7 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# m1_20168_984# 0.01fF
-C8 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vdd 0.24fF
-C9 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# iref -0.15fF
-C10 iref_2 iref_1 0.05fF
-C11 iref_9 iref_8 0.05fF
-C12 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vdd 0.24fF
-C13 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# iref_6 0.24fF
-C14 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# 0.67fF
-C15 iref_1 iref_0 0.05fF
-C16 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# iref_5 0.24fF
-C17 iref_4 iref 0.30fF
-C18 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
-C19 iref_8 iref_7 0.05fF
-C20 vdd m1_20168_984# 0.25fF
-C21 iref_3 iref_4 0.05fF
-C22 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# iref_1 0.24fF
-C23 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# iref_8 0.24fF
-C24 sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# m1_20168_984# 0.54fF
-C25 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.01fF
-C26 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# iref_7 0.24fF
-C27 iref_2 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
-C28 iref_8 iref -0.03fF
+C0 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# 0.54fF
+C1 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# iref_2 0.24fF
+C2 m1_20168_984# vdd 0.25fF
+C3 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vdd 0.24fF
+C4 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# 0.67fF
+C5 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# m1_20168_984# -0.39fF
+C6 iref m1_20168_984# 0.07fF
+C7 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# iref_6 0.24fF
+C8 iref_4 iref 0.30fF
+C9 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# m1_20168_984# 0.01fF
+C10 iref_4 iref_3 0.05fF
+C11 iref_2 iref -0.01fF
+C12 iref_9 iref_8 0.05fF
+C13 iref_9 iref -0.01fF
+C14 iref_2 iref_3 0.05fF
+C15 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vdd 0.24fF
+C16 iref_8 iref_7 0.05fF
+C17 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vdd 0.24fF
+C18 iref_6 iref_7 0.05fF
+C19 iref_2 iref_1 0.05fF
+C20 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vdd 0.24fF
+C21 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# iref_1 0.24fF
+C22 iref vdd -0.07fF
+C23 iref_8 iref -0.03fF
+C24 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# iref -0.15fF
+C25 iref_7 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C26 iref_5 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# 0.24fF
+C27 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vdd 0.24fF
+C28 iref_0 iref_1 0.05fF
C29 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref 0.02fF
-C30 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# m1_20168_984# -0.39fF
-C31 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# 0.24fF
-C32 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
-C33 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref_3 0.24fF
-C34 iref_1 iref -0.02fF
-C35 m1_20168_984# iref 0.07fF
-C36 iref_2 iref -0.01fF
-C37 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vdd 0.24fF
-C38 iref VSUBS 32.42fF
-C39 iref_4 VSUBS 1.17fF
-C40 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# VSUBS 2.60fF
-C41 iref_3 VSUBS 0.64fF
-C42 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# VSUBS 2.60fF
-C43 iref_2 VSUBS -1.26fF
-C44 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# VSUBS 2.60fF
-C45 iref_1 VSUBS -0.80fF
-C46 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# VSUBS 2.60fF
-C47 m1_20168_984# VSUBS 56.92fF
-C48 vdd VSUBS 416.01fF
-C49 iref_0 VSUBS 1.88fF
-C50 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# VSUBS 2.60fF
+C30 iref_1 iref -0.02fF
+C31 iref_5 iref_6 0.05fF
+C32 iref_5 iref 0.05fF
+C33 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vdd 0.24fF
+C34 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# iref_8 0.24fF
+C35 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# m1_20168_984# 0.01fF
+C36 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref_3 0.24fF
+C37 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vdd 0.24fF
+C38 iref_4 VSUBS 1.17fF
+C39 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# VSUBS 2.60fF
+C40 iref_3 VSUBS 0.64fF
+C41 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# VSUBS 2.60fF
+C42 iref_2 VSUBS -1.26fF
+C43 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# VSUBS 2.60fF
+C44 iref_1 VSUBS -0.80fF
+C45 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# VSUBS 2.60fF
+C46 iref_0 VSUBS 1.88fF
+C47 iref VSUBS 32.42fF
+C48 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# VSUBS 2.60fF
+C49 m1_20168_984# VSUBS 56.92fF
+C50 vdd VSUBS 416.01fF
C51 iref_9 VSUBS -1.13fF
C52 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# VSUBS 2.60fF
C53 iref_7 VSUBS -1.38fF
@@ -6799,234 +7751,182 @@
C0 b VSUBS 68.24fF
.ends
-.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
-+ c1_110_n4150# m3_10_n4250#
-X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
-C1 m3_n4309_50# m3_10_n4250# 1.75fF
-C2 m3_n4309_50# m3_n4309_n4250# 2.63fF
-C3 m3_n4309_50# c1_n4209_n4150# 38.10fF
-C4 c1_110_n4150# m3_10_n4250# 81.11fF
-C5 c1_110_n4150# c1_n4209_n4150# 1.32fF
-C6 m3_n4309_n4250# m3_10_n4250# 1.75fF
-C7 c1_110_n4150# VSUBS 0.12fF
-C8 c1_n4209_n4150# VSUBS 0.12fF
-C9 m3_n4309_n4250# VSUBS 8.68fF
-C10 m3_10_n4250# VSUBS 17.92fF
-C11 m3_n4309_50# VSUBS 8.68fF
-.ends
-
-.subckt cap3_loop_filter VSUBS in out
-Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
-C0 in out 3.21fF
-C1 in VSUBS -8.91fF
-C2 out VSUBS 3.92fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
-X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
-C0 a_n118_n388# a_n88_n300# 0.11fF
-C1 a_n88_n300# a_30_n300# 0.61fF
-C2 a_30_n300# w_n226_n510# 0.40fF
-C3 a_n88_n300# w_n226_n510# 0.40fF
-C4 a_n118_n388# w_n226_n510# 0.28fF
-.ends
-
-.subckt loop_filter_v2 vc_pex D0_cap in vss
-Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
-Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
-Xcap2_loop_filter_0 vss in vss cap2_loop_filter
-Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
-Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
-Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
-Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
-C0 in vc_pex 0.18fF
-C1 cap3_loop_filter_0/in in 0.79fF
-C2 in D0_cap 0.07fF
-C3 vc_pex vss -38.13fF
-C4 res_loop_filter_2/out vss 8.49fF
-C5 D0_cap vss 0.04fF
-C6 in vss -18.54fF
-C7 cap3_loop_filter_0/in vss -3.74fF
-.ends
-
.subckt top_pll_v2 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd pswitch vdd charge_pump_0/w_2544_775#
+ ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd in_ref
+ vco_vctrl Down w_13905_n238# vss D0_vco iref_cp ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
+ out_to_div DO_cap nDown biasp out_to_pad Up nUp
Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
-+ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
-Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
-Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
-+ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump_0/w_6648_570# charge_pump
+Xdiv_by_2_0 vss vdd n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2
++ n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
+ div_by_2
-Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
-+ vss vdd buffer_salida
-Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
-+ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd vss ring_osc_0/csvco_branch_2/vbp
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2_0/cap3_loop_filter_0/in
++ loop_filter_v2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# buffer_salida_0/a_3996_n100# out_to_pad
++ vdd out_to_buffer vss buffer_salida
+Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl vss ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd ring_osc_0/csvco_branch_2/vbp
+ ring_osc_0/csvco_branch_0/inverter_csvco_0/vss D0_vco ring_osc_0/csvco_branch_2/cap_vco_0/t
+ vco_out ring_osc
Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
-+ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
-+ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
-+ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_0/latch_diff_1/nD
++ vss vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_5_Q1 out_by_2 div_by_5_0/DFlipFlop_0/Q
++ div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ out_div_by_5 div_5_Q1_shift div_5_nQ2 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_2/latch_diff_1/nD
+ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
-+ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
+ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
-+ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
-+ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
-+ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
-+ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_2/latch_diff_0/D
+ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
+ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
+ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
-+ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
+ div_by_5
-Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
+ Down QA QB nDown Up nUp pfd_cp_interface
-XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
-C0 nUp biasp -0.17fF
-C1 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
-C2 Down biasp 1.24fF
-C3 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
-C4 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
-C5 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
-C6 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
-C7 nDown nswitch 0.76fF
-C8 nUp pswitch 0.85fF
-C9 vdd buffer_salida_0/a_678_n100# 0.24fF
-C10 div_5_Q1 out_by_2 0.42fF
-C11 nswitch vco_vctrl -0.06fF
-C12 out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.09fF
-C13 vdd out_to_buffer 0.07fF
-C14 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
-C15 div_5_Q1 out_div_by_5 0.01fF
-C16 nDown nUp -0.09fF
-C17 vdd out_by_2 0.97fF
-C18 nDown Down 2.55fF
-C19 out_by_2 div_5_Q0 0.09fF
-C20 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# n_out_by_2 0.01fF
-C21 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
-C22 vdd out_div_by_5 0.28fF
-C23 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
-C24 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
-C25 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
-C26 vco_vctrl nUp 0.02fF
-C27 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
-C28 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_out_by_2 0.12fF
-C29 vdd nDown 0.22fF
-C30 div_5_Q1 vco_vctrl 0.14fF
-C31 div_5_nQ2 out_by_2 0.16fF
-C32 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
-C33 div_5_Q1_shift out_div_by_5 0.05fF
-C34 Up nUp 2.72fF
-C35 div_5_Q1 n_out_by_2 1.04fF
-C36 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
-C37 vdd vco_vctrl -1.02fF
-C38 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
-C39 nDown biasp 0.26fF
-C40 Down iref_cp 0.09fF
-C41 div_5_Q0 vco_vctrl 0.48fF
-C42 vdd n_out_by_2 1.03fF
-C43 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
-C44 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
-C45 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
-C46 div_5_Q0 n_out_by_2 -0.12fF
-C47 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
-C48 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
-C49 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
-C50 vdd Up 0.28fF
-C51 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
-C52 nDown pswitch 0.53fF
-C53 vdd iref_cp 0.15fF
-C54 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
-C55 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.33fF
-C56 out_by_2 vco_vctrl 0.53fF
-C57 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
-C58 Up biasp 0.26fF
-C59 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
-C60 div_by_5_0/DFlipFlop_2/latch_diff_0/D n_out_by_2 0.12fF
-C61 div_5_nQ2 n_out_by_2 0.10fF
-C62 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
-C63 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
-C64 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
-C65 vdd out_to_div 0.21fF
-C66 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
-C67 Up pswitch 1.98fF
-C68 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
-C69 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
-C70 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
-C71 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
-C72 out_to_div out_to_buffer 0.13fF
-C73 n_out_by_2 vco_vctrl 0.52fF
-C74 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
-C75 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
-C76 div_5_nQ0 out_by_2 0.32fF
-C77 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
-C78 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
-C79 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
-C80 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
-C81 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
-C82 Down nswitch 0.54fF
-C83 vdd QA -0.04fF
-C84 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
-C85 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
-C86 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
-C87 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
-C88 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
-C89 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
-C90 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
-C91 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
-C92 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
-C93 vdd D0_vco 0.03fF
-C94 vdd lf_vc 0.02fF
-C95 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
-C96 div_5_nQ0 n_out_by_2 0.10fF
-C97 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
-C98 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# n_out_by_2 -0.05fF
-C99 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
-C100 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
-C101 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
-C102 vdd nUp 0.05fF
-C103 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
-C104 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
-C105 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
-C106 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
-C107 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div_by_5 PFD
+C0 vco_vctrl div_5_Q0 0.48fF
+C1 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C2 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
+C3 vco_vctrl vdd -1.02fF
+C4 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C5 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C6 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
+C7 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C8 div_5_nQ2 out_by_2 0.16fF
+C9 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
+C10 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
+C11 n_out_by_2 div_5_Q1 1.04fF
+C12 n_out_by_2 vco_vctrl 0.52fF
+C13 out_by_2 div_5_Q0 0.09fF
+C14 out_to_div vdd 0.21fF
+C15 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C16 out_by_2 vdd 0.97fF
+C17 vdd D0_vco 0.03fF
+C18 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C19 lf_vc vdd 0.02fF
+C20 pswitch Up 1.98fF
+C21 buffer_salida_0/a_678_n100# vdd 0.24fF
+C22 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C23 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C24 nUp Up 2.72fF
+C25 nUp vdd 0.05fF
+C26 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C27 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C28 iref_cp vdd 0.15fF
+C29 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C30 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
+C31 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
+C32 nDown vdd 0.22fF
+C33 biasp Up 0.26fF
+C34 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C35 vco_vctrl div_5_Q1 0.14fF
+C36 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
+C37 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C38 out_to_div out_to_buffer 0.13fF
+C39 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C40 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C41 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C42 buffer_salida_0/a_678_n100# out_to_buffer 0.22fF
+C43 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C44 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C45 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C46 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
+C47 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C48 out_div_by_5 vdd 0.28fF
+C49 out_by_2 div_5_Q1 0.42fF
+C50 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C51 div_5_Q1_shift out_div_by_5 0.05fF
+C52 vco_vctrl out_by_2 0.53fF
+C53 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C54 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
+C55 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C56 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C57 vco_vctrl nUp 0.02fF
+C58 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
+C59 n_out_by_2 div_5_nQ0 0.10fF
+C60 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
+C61 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
+C62 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C63 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C64 QA vdd -0.04fF
+C65 out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.09fF
+C66 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C67 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C68 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C69 nswitch vco_vctrl -0.06fF
+C70 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C71 vdd Up 0.28fF
+C72 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C73 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C74 div_5_Q1 out_div_by_5 0.01fF
+C75 pswitch nUp 0.85fF
+C76 n_out_by_2 div_5_nQ2 0.10fF
+C77 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C78 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C79 pswitch nDown 0.53fF
+C80 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C81 nUp nDown -0.09fF
+C82 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
+C83 biasp nUp -0.17fF
+C84 n_out_by_2 div_5_Q0 -0.12fF
+C85 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C86 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C87 iref_cp Down 0.09fF
+C88 n_out_by_2 vdd 1.03fF
+C89 biasp nDown 0.26fF
+C90 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C91 nDown Down 2.55fF
+C92 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
+C93 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C94 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
+C95 div_5_nQ0 out_by_2 0.32fF
+C96 biasp Down 1.24fF
+C97 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
+C98 vdd out_to_buffer 0.07fF
+C99 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
+C100 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C101 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C102 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C103 nswitch nDown 0.76fF
+C104 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
+C105 nswitch Down 0.54fF
+C106 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
+C107 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
-C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C118 QB vss 4.46fF
-C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.46fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C123 out_div_by_5 vss -0.40fF
C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C127 pfd_reset vss 2.17fF
-C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
-C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C132 QA vss 4.31fF
-C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.31fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C137 in_ref vss 1.19fF
@@ -7039,57 +7939,57 @@
C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
-C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
-C148 div_5_Q1_shift vss -0.14fF
-C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
-C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
-C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
-C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C147 div_5_Q1_shift vss -0.14fF
+C148 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C149 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C156 div_5_Q1 vss 4.28fF
-C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C158 div_5_nQ0 vss 0.59fF
-C159 div_5_Q0 vss 0.01fF
-C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
-C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
-C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
-C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
-C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
-C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
-C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
-C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
-C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C179 div_5_nQ2 vss 1.24fF
-C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
-C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
-C182 n_out_by_2 vss -2.62fF
-C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C186 out_by_2 vss -4.51fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_5_Q1 vss 4.28fF
+C158 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C159 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C164 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_Q0 vss 0.01fF
+C169 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C170 div_5_nQ0 vss 0.59fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C180 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C181 n_out_by_2 vss -2.62fF
+C182 div_5_nQ2 vss 1.24fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C185 out_by_2 vss -4.51fF
+C186 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
-C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
-C192 vdd vss 366.82fF
+C191 vdd vss 366.82fF
+C192 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
C195 out_first_buffer vss 2.88fF
-C196 out_to_div vss 4.46fF
-C197 out_to_buffer vss 1.57fF
+C196 out_to_buffer vss 1.57fF
+C197 out_to_div vss 4.46fF
C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -7104,29 +8004,29 @@
C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
-C212 buffer_salida_0/a_3996_n100# vss 48.29fF
-C213 out_to_pad vss 7.50fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
C214 buffer_salida_0/a_678_n100# vss 13.38fF
-C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
-C217 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
-C218 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
-C219 out_buffer_div_2 vss 1.60fF
-C220 n_out_buffer_div_2 vss 1.63fF
-C221 out_div_2 vss -1.30fF
-C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
-C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C229 n_out_div_2 vss 1.95fF
-C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
-C231 lf_vc vss -59.89fF
-C232 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
-C233 DO_cap vss 0.01fF
-C234 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C215 lf_vc vss -59.89fF
+C216 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C217 DO_cap vss 0.01fF
+C218 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C220 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C221 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C222 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C223 out_buffer_div_2 vss 1.60fF
+C224 n_out_buffer_div_2 vss 1.63fF
+C225 out_div_2 vss -1.30fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C227 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C228 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C229 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C230 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C231 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C232 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C233 n_out_div_2 vss 1.95fF
+C234 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
C235 nswitch vss 3.73fF
C236 biasp vss 5.44fF
C237 iref_cp vss 2.81fF
@@ -7142,103 +8042,104 @@
+ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
+ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
+ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7]
-+ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
-+ io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
-+ io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
-+ io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9]
-+ io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14]
-+ io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1]
-+ io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25]
-+ io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7]
-+ io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
-+ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20]
-+ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3]
-+ io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10]
-+ io_out[11] io_out[12] io_out[13] io_out[14] io_out[15] io_out[16] io_out[17] io_out[18]
-+ io_out[19] io_out[1] io_out[20] io_out[21] io_out[22] io_out[23] io_out[24] io_out[25]
-+ io_out[26] io_out[2] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8]
-+ io_out[9] la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103]
-+ la_data_in[104] la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108]
-+ la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113]
-+ la_data_in[114] la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118]
-+ la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123]
-+ la_data_in[124] la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13]
-+ la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19]
-+ la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24]
-+ la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2]
-+ la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35]
-+ la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40]
-+ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46]
-+ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51]
-+ la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57]
-+ la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62]
-+ la_data_in[63] la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68]
-+ la_data_in[69] la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73]
-+ la_data_in[74] la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79]
-+ la_data_in[7] la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84]
-+ la_data_in[85] la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8]
-+ la_data_in[90] la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95]
-+ la_data_in[96] la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0]
-+ la_data_out[100] la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104]
-+ la_data_out[105] la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109]
-+ la_data_out[10] la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113]
-+ la_data_out[114] la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118]
-+ la_data_out[119] la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122]
-+ la_data_out[123] la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127]
-+ la_data_out[12] la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16]
-+ la_data_out[17] la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21]
-+ la_data_out[22] la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26]
-+ la_data_out[27] la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31]
-+ la_data_out[32] la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36]
-+ la_data_out[37] la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41]
-+ la_data_out[42] la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46]
-+ la_data_out[47] la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51]
-+ la_data_out[52] la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56]
-+ la_data_out[57] la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61]
-+ la_data_out[62] la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66]
-+ la_data_out[67] la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71]
-+ la_data_out[72] la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76]
-+ la_data_out[77] la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81]
-+ la_data_out[82] la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86]
-+ la_data_out[87] la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91]
-+ la_data_out[92] la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96]
-+ la_data_out[97] la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100]
-+ la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107]
-+ la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113]
-+ la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11]
-+ la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126]
-+ la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17]
-+ la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23]
-+ la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2]
-+ la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36]
-+ la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42]
-+ la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49]
-+ la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55]
-+ la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61]
-+ la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68]
-+ la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74]
-+ la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80]
-+ la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87]
-+ la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93]
-+ la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9]
-+ user_clock2 user_irq[0] user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2
-+ vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11]
-+ wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17]
-+ wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22]
-+ wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28]
-+ wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4]
-+ wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0]
-+ wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15]
-+ wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20]
-+ wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26]
-+ wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31]
-+ wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9]
-+ wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14]
-+ wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1]
-+ wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25]
-+ wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
-+ wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
-+ wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
++ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
Xres_amp_top_0 vssa1 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
+ vdda1 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# bias_0/iref_8
+ res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out
@@ -7266,18 +8167,23 @@
+ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
+ gpio_noesd[2] io_analog[0] res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
+ io_analog[1] io_analog[4] res_amp_top_0/res_amp_sync_v2_0/rst res_amp_top
-Xtop_pll_v1_0 top_pll_v1_0/vco_vctrl vdda1 top_pll_v1_0/pswitch top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
-+ top_pll_v1_0/charge_pump_0/w_2544_775# top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp
-+ top_pll_v1_0/biasp io_analog[10] top_pll_v1_0/Down vssa1 vssa1 gpio_noesd[7] top_pll_v1_0/buffer_salida_0/a_3996_n100#
-+ top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v1_0/QA top_pll_v1_0/charge_pump_0/w_1008_774#
-+ bias_0/iref_2 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd top_pll_v1_0/out_to_div
-+ top_pll_v1_0/nDown io_analog[9] top_pll_v1_0/Up top_pll_v1_0/nUp top_pll_v1
-Xtop_pll_v1_1 top_pll_v1_1/vco_vctrl vdda1 top_pll_v1_1/pswitch top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
-+ top_pll_v1_1/charge_pump_0/w_2544_775# top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp
-+ top_pll_v1_1/biasp io_analog[10] top_pll_v1_1/Down vssa1 vssa1 gpio_noesd[7] top_pll_v1_1/buffer_salida_0/a_3996_n100#
-+ top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v1_1/QA top_pll_v1_1/charge_pump_0/w_1008_774#
-+ bias_0/iref_0 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd top_pll_v1_1/out_to_div
-+ top_pll_v1_1/nDown io_analog[7] top_pll_v1_1/Up top_pll_v1_1/nUp top_pll_v1
+Xtop_pll_v3_0 top_pll_v3_0/clk_d vdda1 gpio_noesd[10] top_pll_v3_0/charge_pump_0/w_2544_775#
++ top_pll_v3_0/out_by_2 top_pll_v3_0/s_0_n io_analog[10] top_pll_v3_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ top_pll_v3_0/buffer_salida_0/a_3996_n100# vssa1 top_pll_v3_0/vco_vctrl gpio_noesd[9]
++ top_pll_v3_0/ring_osc_0/csvco_branch_2/vbp top_pll_v3_0/lf_vc gpio_noesd[7] gpio_noesd[8]
++ top_pll_v3_0/buffer_salida_0/a_678_n100# top_pll_v3_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ top_pll_v3_0/loop_filter_v2_0/cap3_loop_filter_0/in top_pll_v3_0/charge_pump_0/w_1008_774#
++ bias_0/iref_0 top_pll_v3_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd top_pll_v3_0/Down
++ top_pll_v3_0/out_to_div top_pll_v3_0/clk_1 top_pll_v3_0/out_div top_pll_v3_0/nDown
++ top_pll_v3_0/s_1_n io_analog[7] gpio_noesd[11] top_pll_v3_0/Up top_pll_v3_0/clk_0
++ top_pll_v3_0/freq_div_0/prescaler_23_0/nCLK_23 top_pll_v3_0/biasp top_pll_v3_0/nUp
++ top_pll_v3_0/n_clk_0 top_pll_v3
+Xtop_pll_v1_0 top_pll_v1_0/vco_vctrl top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ vdda1 top_pll_v1_0/charge_pump_0/w_2544_775# top_pll_v1_0/pswitch top_pll_v1_0/biasp
++ top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp io_analog[10] top_pll_v1_0/Down vssa1
++ vssa1 gpio_noesd[7] top_pll_v1_0/QA top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ bias_0/iref_2 top_pll_v1_0/out_to_div top_pll_v1_0/nDown io_analog[9] top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
++ top_pll_v1_0/Up top_pll_v1_0/nUp top_pll_v1
Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
@@ -7331,1339 +8237,1432 @@
+ top_pll_v2_0/Down vssa1 vssa1 gpio_noesd[7] bias_0/iref_1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
+ top_pll_v2_0/out_to_div gpio_noesd[8] top_pll_v2_0/nDown top_pll_v2_0/biasp io_analog[8]
+ top_pll_v2_0/Up top_pll_v2_0/nUp top_pll_v2
-C0 gpio_noesd[4] gpio_noesd[5] 4.67fF
-C1 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[5] 0.44fF
-C2 bias_0/iref_9 gpio_noesd[4] -0.25fF
-C3 bias_0/iref_8 bias_0/iref_5 10.19fF
-C4 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in gpio_noesd[5] 0.05fF
-C5 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outp -0.31fF
-C6 io_analog[7] bias_0/iref_1 13.22fF
-C7 io_analog[6] io_clamp_high[2] 0.53fF
-C8 vdda1 io_analog[2] 25.90fF
-C9 gpio_noesd[6] gpio_noesd[5] 0.05fF
-C10 io_analog[6] vdda1 124.15fF
-C11 bias_0/iref_9 io_analog[4] 15.97fF
-C12 bias_0/iref_8 io_analog[3] 13.88fF
-C13 gpio_noesd[7] top_pll_v2_0/out_to_div 0.23fF
-C14 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outp 0.61fF
-C15 bias_0/iref_2 io_analog[8] 14.44fF
-C16 gpio_noesd[7] io_analog[10] 29.88fF
-C17 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.07fF
-C18 io_analog[2] bias_0/iref_6 13.88fF
-C19 io_analog[5] m3_226242_702300# 0.53fF
-C20 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_1008_774# 0.21fF
-C21 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.22fF
-C22 io_analog[4] io_clamp_high[0] 0.53fF
-C23 vdda1 top_pll_v1_0/nUp 0.01fF
-C24 vdda1 top_pll_v2_0/pswitch 0.34fF
-C25 io_analog[4] bias_0/iref_8 15.97fF
-C26 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# bias_0/iref_7 0.09fF
-C27 bias_0/iref_9 gpio_noesd[5] 1.30fF
-C28 bias_0/iref_8 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.34fF
-C29 bias_0/iref_1 top_pll_v2_0/nUp 0.22fF
-C30 res_amp_top_0/res_amp_lin_prog_0/outp gpio_noesd[5] 0.44fF
-C31 gpio_noesd[7] top_pll_v2_0/vco_vctrl 0.05fF
-C32 bias_0/iref_1 top_pll_v2_0/charge_pump_0/w_2544_775# 0.09fF
-C33 top_pll_v1_0/vco_vctrl gpio_noesd[7] 0.05fF
-C34 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.04fF
-C35 vdda1 bias_0/iref_6 29.75fF
-C36 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.17fF
-C37 io_analog[2] bias_0/iref_7 13.88fF
-C38 gpio_noesd[7] top_pll_v1_1/vco_vctrl 0.04fF
-C39 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.72fF
-C40 gpio_noesd[7] gpio_noesd[8] 1.88fF
-C41 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl gpio_noesd[5] 0.33fF
-C42 vdda1 top_pll_v2_0/biasp 0.03fF
-C43 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.42fF
-C44 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# 0.18fF
-C45 bias_0/iref_1 top_pll_v2_0/nDown 0.54fF
-C46 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_2544_775# 0.21fF
-C47 vdda1 io_analog[9] 30.05fF
-C48 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.94fF
-C49 top_pll_v1_0/QA io_analog[10] 0.03fF
-C50 bias_0/iref_9 bias_0/iref_8 9.89fF
-C51 bias_0/iref_2 top_pll_v1_0/nDown 0.70fF
-C52 bias_0/iref_0 top_pll_v1_1/Down 1.08fF
-C53 io_analog[6] bias_0/iref_1 13.22fF
-C54 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA gpio_noesd[3] 0.01fF
-C55 vdda1 bias_0/iref_7 33.08fF
-C56 gpio_noesd[7] top_pll_v1_0/out_to_div 0.23fF
-C57 io_analog[2] bias_0/iref_5 13.88fF
-C58 io_analog[6] bias_0/iref_0 6.93fF
-C59 bias_0/iref_2 top_pll_v1_0/Down 1.11fF
-C60 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA gpio_noesd[4] 0.42fF
-C61 io_analog[2] io_analog[3] 0.14fF
-C62 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.17fF
-C63 vdda1 bias_0/iref_1 15.26fF
-C64 bias_0/iref_7 bias_0/iref_6 17.40fF
-C65 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_6 0.15fF
-C66 gpio_noesd[1] vdda1 214.54fF
-C67 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in bias_0/iref_5 0.46fF
-C68 io_analog[10] gpio_noesd[8] 20.65fF
-C69 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_7 0.37fF
-C70 bias_0/iref_2 io_analog[7] 13.22fF
-C71 gpio_noesd[2] vdda1 214.16fF
-C72 vdda1 bias_0/iref_0 15.18fF
-C73 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_8 0.11fF
-C74 gpio_noesd[4] io_analog[2] -0.21fF
-C75 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in 0.23fF
-C76 bias_0/iref_0 top_pll_v1_1/nUp 0.74fF
-C77 vdda1 bias_0/iref_5 30.67fF
-C78 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp 1.01fF
-C79 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA 0.29fF
-C80 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out 0.21fF
-C81 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.17fF
-C82 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outn -1.06fF
-C83 bias_0/iref_0 top_pll_v1_1/Up 0.74fF
-C84 vdda1 io_analog[3] 25.90fF
-C85 io_analog[4] io_analog[6] 0.59fF
-C86 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/clk 0.39fF
-C87 vdda1 gpio_noesd[3] 120.88fF
-C88 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_7 0.45fF
-C89 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/clk 0.37fF
-C90 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outn 0.45fF
-C91 bias_0/iref_5 bias_0/iref_6 29.11fF
-C92 bias_0/iref_1 top_pll_v2_0/biasp 2.20fF
-C93 bias_0/iref_0 top_pll_v1_1/nDown 0.74fF
-C94 vdda1 gpio_noesd[4] 117.64fF
-C95 top_pll_v1_0/biasp bias_0/iref_2 3.20fF
-C96 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp 0.17fF
-C97 vdda1 io_analog[8] 29.93fF
-C98 io_analog[6] io_clamp_low[2] 0.53fF
-C99 io_analog[3] bias_0/iref_6 13.88fF
-C100 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[2] 0.21fF
-C101 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.12fF
-C102 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[4] -0.05fF
-C103 vdda1 gpio_noesd[6] 53.94fF
-C104 io_analog[4] vdda1 182.26fF
-C105 vdda1 top_pll_v1_1/pswitch 0.48fF
-C106 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[3] 0.21fF
-C107 vdda1 gpio_noesd[7] 120.83fF
-C108 bias_0/iref_9 res_amp_top_0/res_amp_sync_v2_0/rst 0.39fF
-C109 bias_0/iref_0 top_pll_v1_1/biasp 3.13fF
-C110 io_analog[2] gpio_noesd[5] 0.09fF
-C111 top_pll_v1_0/charge_pump_0/w_2544_775# bias_0/iref_2 0.02fF
-C112 bias_0/iref_9 io_analog[2] 13.88fF
-C113 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB 0.19fF
-C114 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C115 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_5 0.45fF
-C116 bias_0/iref_7 bias_0/iref_5 10.35fF
-C117 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[4] -0.01fF
-C118 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in -0.70fF
-C119 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[3] 0.03fF
-C120 io_analog[4] io_clamp_low[0] 0.53fF
-C121 res_amp_top_0/res_amp_lin_prog_0/outn gpio_noesd[5] 1.42fF
-C122 io_analog[4] bias_0/iref_6 15.97fF
-C123 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in 0.18fF
-C124 bias_0/iref_5 io_analog[5] 0.09fF
-C125 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b 0.31fF
-C126 io_analog[3] bias_0/iref_7 13.88fF
-C127 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in gpio_noesd[4] 0.12fF
-C128 gpio_noesd[2] gpio_noesd[1] 0.30fF
-C129 io_analog[6] bias_0/iref_2 54.67fF
-C130 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# -0.08fF
-C131 io_analog[5] m3_222594_702300# 0.53fF
-C132 vdda1 io_analog[1] 76.56fF
-C133 vdda1 gpio_noesd[5] 124.75fF
-C134 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp gpio_noesd[5] 0.54fF
-C135 bias_0/iref_9 vdda1 30.24fF
-C136 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp 2.10fF
-C137 io_analog[2] bias_0/iref_8 13.88fF
-C138 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out 0.21fF
-C139 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out 0.38fF
-C140 bias_0/iref_1 top_pll_v2_0/Up 0.54fF
-C141 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b gpio_noesd[1] 0.23fF
-C142 vdda1 io_analog[10] 0.01fF
-C143 vdda1 io_analog[0] 76.77fF
-C144 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.12fF
-C145 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in 0.20fF
-C146 vdda1 top_pll_v1_0/buffer_salida_0/a_3996_n100# 0.06fF
-C147 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[5] 0.26fF
-C148 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out gpio_noesd[3] 0.33fF
-C149 io_analog[4] bias_0/iref_7 15.97fF
-C150 vdda1 bias_0/iref_2 3.90fF
-C151 vdda1 top_pll_v1_0/pswitch 0.38fF
-C152 bias_0/iref_2 top_pll_v1_0/nUp 0.70fF
-C153 io_analog[3] bias_0/iref_5 13.88fF
-C154 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out gpio_noesd[4] 0.19fF
-C155 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.46fF
-C156 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[5] 0.68fF
-C157 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out gpio_noesd[1] 0.57fF
-C158 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.12fF
-C159 vdda1 bias_0/iref_8 31.37fF
-C160 bias_0/iref_1 top_pll_v2_0/Down 0.91fF
-C161 bias_0/iref_2 top_pll_v1_0/Up 0.70fF
-C162 vdda1 top_pll_v2_0/vco_vctrl 0.59fF
-C163 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C164 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[5] 0.14fF
-C165 vdda1 top_pll_v1_0/vco_vctrl 0.43fF
-C166 gpio_noesd[5] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.32fF
-C167 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# gpio_noesd[5] 0.16fF
-C168 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.78fF
-C169 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.01fF
-C170 vdda1 io_analog[7] 29.48fF
-C171 io_analog[4] bias_0/iref_5 15.97fF
-C172 gpio_noesd[4] io_analog[3] -0.78fF
-C173 vdda1 top_pll_v1_1/vco_vctrl 0.54fF
-C174 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_8 0.37fF
-C175 bias_0/iref_5 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.46fF
-C176 vdda1 gpio_noesd[8] 76.96fF
-C177 bias_0/iref_2 io_analog[9] 14.44fF
-C178 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.08fF
-C179 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[4] -0.13fF
-C180 gpio_noesd[7] top_pll_v1_1/out_to_div 0.15fF
-C181 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA 0.49fF
-C182 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[6] 2.12fF
-C183 io_analog[7] top_pll_v1_1/buffer_salida_0/a_3996_n100# -0.08fF
-C184 vdda1 top_pll_v1_0/biasp 0.03fF
-C185 bias_0/iref_8 bias_0/iref_7 13.23fF
-C186 vdda1 top_pll_v2_0/buffer_salida_0/a_3996_n100# 0.05fF
-C187 vdda1 top_pll_v2_0/nUp 0.01fF
-C188 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.04fF
-C189 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_7 0.40fF
-C190 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp 1.14fF
-C191 io_analog[3] gpio_noesd[5] 0.12fF
-C192 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in gpio_noesd[5] 0.47fF
-C193 bias_0/iref_9 io_analog[3] 13.88fF
-C194 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.04fF
-C195 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# -0.11fF
-C196 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB gpio_noesd[5] 0.14fF
-C197 io_in_3v3[0] vssa1 0.41fF
-C198 io_oeb[26] vssa1 0.61fF
-C199 io_in[0] vssa1 0.41fF
-C200 io_out[26] vssa1 0.61fF
-C201 io_out[0] vssa1 0.41fF
-C202 io_in[26] vssa1 0.61fF
-C203 io_oeb[0] vssa1 0.41fF
-C204 io_in_3v3[26] vssa1 0.61fF
-C205 io_in_3v3[1] vssa1 0.41fF
-C206 io_oeb[25] vssa1 0.61fF
-C207 io_in[1] vssa1 0.41fF
-C208 io_out[25] vssa1 0.61fF
-C209 io_out[1] vssa1 0.41fF
-C210 io_in[25] vssa1 0.61fF
-C211 io_oeb[1] vssa1 0.41fF
-C212 io_in_3v3[25] vssa1 0.61fF
-C213 io_in_3v3[2] vssa1 0.41fF
-C214 io_oeb[24] vssa1 0.61fF
-C215 io_in[2] vssa1 0.41fF
-C216 io_out[24] vssa1 0.61fF
-C217 io_out[2] vssa1 0.41fF
-C218 io_in[24] vssa1 0.61fF
-C219 io_oeb[2] vssa1 -0.20fF
-C220 io_in_3v3[3] vssa1 0.41fF
-C221 gpio_noesd[17] vssa1 0.61fF
-C222 io_in[3] vssa1 0.41fF
-C223 gpio_analog[17] vssa1 0.61fF
-C224 io_out[3] vssa1 0.41fF
-C225 io_oeb[3] vssa1 0.41fF
-C226 io_in_3v3[4] vssa1 0.41fF
-C227 io_in[4] vssa1 0.41fF
-C228 io_out[4] vssa1 0.41fF
-C229 io_oeb[4] vssa1 0.41fF
-C230 io_oeb[23] vssa1 0.61fF
-C231 io_out[23] vssa1 0.61fF
-C232 io_in[23] vssa1 0.61fF
-C233 io_in_3v3[23] vssa1 0.61fF
-C234 gpio_noesd[16] vssa1 0.61fF
-C235 io_in_3v3[5] vssa1 0.41fF
-C236 io_in[5] vssa1 -0.20fF
-C237 io_out[5] vssa1 0.41fF
-C238 io_oeb[5] vssa1 0.41fF
-C239 io_oeb[22] vssa1 0.61fF
-C240 io_out[22] vssa1 0.61fF
-C241 io_in[22] vssa1 0.61fF
-C242 io_in_3v3[22] vssa1 0.61fF
-C243 gpio_analog[15] vssa1 0.61fF
-C244 io_in_3v3[6] vssa1 -0.20fF
-C245 io_in[6] vssa1 0.41fF
-C246 io_out[6] vssa1 0.41fF
-C247 io_oeb[6] vssa1 0.41fF
-C248 io_oeb[21] vssa1 0.61fF
-C249 io_out[21] vssa1 0.61fF
-C250 io_in[21] vssa1 0.61fF
-C251 io_in_3v3[21] vssa1 0.61fF
-C252 gpio_noesd[14] vssa1 0.61fF
-C253 gpio_analog[14] vssa1 0.61fF
-C254 vssd2 vssa1 -5.19fF
-C255 vssd1 vssa1 1.13fF
-C256 vdda2 vssa1 -5.19fF
-C257 io_oeb[20] vssa1 0.61fF
-C258 io_out[20] vssa1 0.61fF
-C259 io_in[20] vssa1 0.61fF
-C260 io_in_3v3[20] vssa1 0.61fF
-C261 gpio_noesd[13] vssa1 0.61fF
-C262 gpio_analog[13] vssa1 0.61fF
-C263 gpio_analog[0] vssa1 0.41fF
-C264 gpio_noesd[0] vssa1 0.41fF
-C265 io_in_3v3[7] vssa1 0.41fF
-C266 io_in[7] vssa1 0.41fF
-C267 io_out[7] vssa1 0.41fF
-C268 io_oeb[7] vssa1 0.41fF
-C269 io_oeb[19] vssa1 0.61fF
-C270 io_out[19] vssa1 0.61fF
-C271 io_in[19] vssa1 0.61fF
-C272 io_in_3v3[19] vssa1 0.61fF
-C273 gpio_noesd[12] vssa1 0.61fF
-C274 gpio_analog[12] vssa1 0.61fF
-C275 gpio_analog[1] vssa1 0.41fF
-C276 io_in_3v3[8] vssa1 0.41fF
-C277 io_in[8] vssa1 0.41fF
-C278 io_out[8] vssa1 -0.20fF
-C279 io_oeb[8] vssa1 0.41fF
-C280 gpio_analog[2] vssa1 0.41fF
-C281 io_in_3v3[9] vssa1 0.41fF
-C282 io_in[9] vssa1 0.41fF
-C283 io_out[9] vssa1 0.41fF
-C284 io_oeb[9] vssa1 0.41fF
-C285 gpio_analog[3] vssa1 0.41fF
-C286 io_in_3v3[10] vssa1 0.41fF
-C287 io_in[10] vssa1 0.41fF
-C288 io_out[10] vssa1 0.41fF
-C289 io_oeb[10] vssa1 0.41fF
-C290 gpio_analog[4] vssa1 0.41fF
-C291 io_in_3v3[11] vssa1 0.41fF
-C292 io_in[11] vssa1 0.41fF
-C293 io_out[11] vssa1 0.41fF
-C294 io_oeb[11] vssa1 0.41fF
-C295 gpio_analog[5] vssa1 0.41fF
-C296 io_in_3v3[12] vssa1 0.41fF
-C297 io_in[12] vssa1 0.41fF
-C298 io_out[12] vssa1 0.41fF
-C299 io_oeb[12] vssa1 0.41fF
-C300 gpio_analog[6] vssa1 0.60fF
-C301 io_in_3v3[13] vssa1 0.60fF
-C302 io_in[13] vssa1 0.60fF
-C303 io_out[13] vssa1 0.60fF
-C304 io_oeb[13] vssa1 0.60fF
-C305 io_oeb[18] vssa1 0.61fF
-C306 io_out[18] vssa1 0.61fF
-C307 io_in_3v3[18] vssa1 0.61fF
-C308 gpio_noesd[11] vssa1 0.61fF
-C309 gpio_analog[11] vssa1 0.61fF
-C310 io_oeb[17] vssa1 0.61fF
-C311 io_in[17] vssa1 0.61fF
-C312 io_in_3v3[17] vssa1 0.61fF
-C313 gpio_noesd[10] vssa1 0.61fF
-C314 gpio_analog[10] vssa1 0.61fF
-C315 io_out[16] vssa1 0.61fF
-C316 io_in[16] vssa1 0.61fF
-C317 io_in_3v3[16] vssa1 0.61fF
-C318 gpio_noesd[9] vssa1 0.61fF
-C319 gpio_analog[9] vssa1 0.61fF
-C320 io_oeb[15] vssa1 0.61fF
-C321 io_out[15] vssa1 0.61fF
-C322 io_in[15] vssa1 0.61fF
-C323 io_in_3v3[15] vssa1 0.61fF
-C324 vccd1 vssa1 0.85fF
-C325 gpio_analog[8] vssa1 0.61fF
-C326 io_oeb[14] vssa1 0.61fF
-C327 io_out[14] vssa1 0.61fF
-C328 io_in[14] vssa1 0.61fF
-C329 io_in_3v3[14] vssa1 0.61fF
-C330 vssa2 vssa1 1.66fF
-C331 vccd2 vssa1 0.91fF
-C332 io_clamp_high[0] vssa1 -2.60fF
-C333 io_clamp_low[0] vssa1 0.82fF
-C334 io_clamp_high[2] vssa1 0.66fF
-C335 io_clamp_low[2] vssa1 0.50fF
-C336 user_irq[2] vssa1 0.63fF
-C337 user_irq[1] vssa1 0.63fF
-C338 user_irq[0] vssa1 0.63fF
-C339 user_clock2 vssa1 0.63fF
-C340 la_oenb[127] vssa1 0.63fF
-C341 la_data_in[127] vssa1 0.63fF
-C342 la_oenb[126] vssa1 0.63fF
-C343 la_data_out[126] vssa1 0.63fF
-C344 la_data_in[126] vssa1 0.63fF
-C345 la_oenb[125] vssa1 0.63fF
-C346 la_data_out[125] vssa1 0.63fF
-C347 la_data_in[125] vssa1 0.63fF
-C348 la_oenb[124] vssa1 0.63fF
-C349 la_data_out[124] vssa1 0.63fF
-C350 la_data_in[124] vssa1 0.63fF
-C351 la_oenb[123] vssa1 0.63fF
-C352 la_data_out[123] vssa1 0.63fF
-C353 la_oenb[122] vssa1 0.63fF
-C354 la_data_out[122] vssa1 0.63fF
-C355 la_data_in[122] vssa1 0.63fF
-C356 la_oenb[121] vssa1 0.63fF
-C357 la_data_out[121] vssa1 0.63fF
-C358 la_data_in[121] vssa1 0.63fF
-C359 la_oenb[120] vssa1 0.63fF
-C360 la_data_out[120] vssa1 0.63fF
-C361 la_data_in[120] vssa1 0.63fF
-C362 la_oenb[119] vssa1 0.63fF
-C363 la_data_out[119] vssa1 0.63fF
-C364 la_data_in[119] vssa1 0.63fF
-C365 la_oenb[118] vssa1 0.63fF
-C366 la_data_out[118] vssa1 0.63fF
-C367 la_data_in[118] vssa1 0.63fF
-C368 la_oenb[117] vssa1 0.63fF
-C369 la_data_out[117] vssa1 0.63fF
-C370 la_data_in[117] vssa1 0.63fF
-C371 la_data_out[116] vssa1 0.63fF
-C372 la_data_in[116] vssa1 0.63fF
-C373 la_oenb[115] vssa1 0.63fF
-C374 la_data_out[115] vssa1 0.63fF
-C375 la_data_in[115] vssa1 0.63fF
-C376 la_oenb[114] vssa1 0.63fF
-C377 la_data_out[114] vssa1 0.63fF
-C378 la_data_in[114] vssa1 0.63fF
-C379 la_oenb[113] vssa1 0.63fF
-C380 la_data_out[113] vssa1 0.63fF
-C381 la_data_in[113] vssa1 0.63fF
-C382 la_oenb[112] vssa1 0.63fF
-C383 la_data_in[112] vssa1 0.63fF
-C384 la_oenb[111] vssa1 0.63fF
-C385 la_data_out[111] vssa1 0.63fF
-C386 la_data_in[111] vssa1 0.63fF
-C387 la_oenb[110] vssa1 0.63fF
-C388 la_data_out[110] vssa1 0.63fF
-C389 la_data_in[110] vssa1 0.63fF
-C390 la_oenb[109] vssa1 0.63fF
-C391 la_data_out[109] vssa1 0.63fF
-C392 la_data_in[109] vssa1 0.63fF
-C393 la_oenb[108] vssa1 0.63fF
-C394 la_data_out[108] vssa1 0.63fF
-C395 la_oenb[107] vssa1 0.63fF
-C396 la_data_out[107] vssa1 0.63fF
-C397 la_data_in[107] vssa1 0.63fF
-C398 la_oenb[106] vssa1 0.63fF
-C399 la_data_out[106] vssa1 0.63fF
-C400 la_oenb[105] vssa1 0.63fF
-C401 la_data_out[105] vssa1 0.63fF
-C402 la_data_in[105] vssa1 0.63fF
-C403 la_oenb[104] vssa1 0.63fF
-C404 la_data_out[104] vssa1 0.63fF
-C405 la_data_in[104] vssa1 0.63fF
-C406 la_oenb[103] vssa1 0.63fF
-C407 la_data_out[103] vssa1 0.63fF
-C408 la_data_in[103] vssa1 0.63fF
-C409 la_oenb[102] vssa1 0.63fF
-C410 la_data_out[102] vssa1 0.63fF
-C411 la_data_in[102] vssa1 0.63fF
-C412 la_data_out[101] vssa1 0.63fF
-C413 la_data_in[101] vssa1 0.63fF
-C414 la_oenb[100] vssa1 0.63fF
-C415 la_data_out[100] vssa1 0.63fF
-C416 la_data_in[100] vssa1 0.63fF
-C417 la_oenb[99] vssa1 0.63fF
-C418 la_data_out[99] vssa1 0.63fF
-C419 la_data_in[99] vssa1 0.63fF
-C420 la_oenb[98] vssa1 0.63fF
-C421 la_data_out[98] vssa1 0.63fF
-C422 la_data_in[98] vssa1 0.63fF
-C423 la_oenb[97] vssa1 0.63fF
-C424 la_data_in[97] vssa1 0.63fF
-C425 la_oenb[96] vssa1 0.63fF
-C426 la_data_out[96] vssa1 0.63fF
-C427 la_data_in[96] vssa1 0.63fF
-C428 la_oenb[95] vssa1 0.63fF
-C429 la_data_out[95] vssa1 0.63fF
-C430 la_data_in[95] vssa1 0.63fF
-C431 la_oenb[94] vssa1 0.63fF
-C432 la_data_out[94] vssa1 0.63fF
-C433 la_data_in[94] vssa1 0.63fF
-C434 la_oenb[93] vssa1 0.63fF
-C435 la_data_out[93] vssa1 0.63fF
-C436 la_oenb[92] vssa1 0.63fF
-C437 la_data_out[92] vssa1 0.63fF
-C438 la_data_in[92] vssa1 0.63fF
-C439 la_oenb[91] vssa1 0.63fF
-C440 la_data_out[91] vssa1 0.63fF
-C441 la_oenb[90] vssa1 0.63fF
-C442 la_data_out[90] vssa1 0.63fF
-C443 la_data_in[90] vssa1 0.63fF
-C444 la_oenb[89] vssa1 0.63fF
-C445 la_data_out[89] vssa1 0.63fF
-C446 la_data_in[89] vssa1 0.63fF
-C447 la_oenb[88] vssa1 0.63fF
-C448 la_data_out[88] vssa1 0.63fF
-C449 la_data_in[88] vssa1 0.63fF
-C450 la_oenb[87] vssa1 0.63fF
-C451 la_data_out[87] vssa1 0.63fF
-C452 la_data_in[87] vssa1 0.63fF
-C453 la_data_out[86] vssa1 0.63fF
-C454 la_data_in[86] vssa1 0.63fF
-C455 la_oenb[85] vssa1 0.63fF
-C456 la_data_out[85] vssa1 0.63fF
-C457 la_data_in[85] vssa1 0.63fF
-C458 la_oenb[84] vssa1 0.63fF
-C459 la_data_out[84] vssa1 0.63fF
-C460 la_data_in[84] vssa1 0.63fF
-C461 la_oenb[83] vssa1 0.63fF
-C462 la_data_out[83] vssa1 0.63fF
-C463 la_data_in[83] vssa1 0.63fF
-C464 la_oenb[82] vssa1 0.63fF
-C465 la_data_in[82] vssa1 0.63fF
-C466 la_oenb[81] vssa1 0.63fF
-C467 la_data_out[81] vssa1 0.63fF
-C468 la_data_in[81] vssa1 0.63fF
-C469 la_oenb[80] vssa1 0.63fF
-C470 la_data_out[80] vssa1 0.63fF
-C471 la_data_in[80] vssa1 0.63fF
-C472 la_oenb[79] vssa1 0.63fF
-C473 la_data_out[79] vssa1 0.63fF
-C474 la_data_in[79] vssa1 0.63fF
-C475 la_oenb[78] vssa1 0.63fF
-C476 la_data_out[78] vssa1 0.63fF
-C477 la_data_in[78] vssa1 0.63fF
-C478 la_oenb[77] vssa1 0.63fF
-C479 la_data_out[77] vssa1 0.63fF
-C480 la_data_in[77] vssa1 0.63fF
-C481 la_oenb[76] vssa1 0.63fF
-C482 la_data_out[76] vssa1 0.63fF
-C483 la_oenb[75] vssa1 0.63fF
-C484 la_data_out[75] vssa1 0.63fF
-C485 la_data_in[75] vssa1 0.63fF
-C486 la_oenb[74] vssa1 0.63fF
-C487 la_data_out[74] vssa1 0.63fF
-C488 la_data_in[74] vssa1 0.63fF
-C489 la_oenb[73] vssa1 0.63fF
-C490 la_data_out[73] vssa1 0.63fF
-C491 la_data_in[73] vssa1 0.63fF
-C492 la_oenb[72] vssa1 0.63fF
-C493 la_data_out[72] vssa1 0.63fF
-C494 la_data_in[72] vssa1 0.63fF
-C495 la_data_out[71] vssa1 0.63fF
-C496 la_data_in[71] vssa1 0.63fF
-C497 la_oenb[70] vssa1 0.63fF
-C498 la_data_out[70] vssa1 0.63fF
-C499 la_data_in[70] vssa1 0.63fF
-C500 la_oenb[69] vssa1 0.63fF
-C501 la_data_out[69] vssa1 0.63fF
-C502 la_data_in[69] vssa1 0.63fF
-C503 la_oenb[68] vssa1 0.63fF
-C504 la_data_out[68] vssa1 0.63fF
-C505 la_data_in[68] vssa1 0.63fF
-C506 la_oenb[67] vssa1 0.63fF
-C507 la_data_in[67] vssa1 0.63fF
-C508 la_oenb[66] vssa1 0.63fF
-C509 la_data_out[66] vssa1 0.63fF
-C510 la_data_in[66] vssa1 0.63fF
-C511 la_oenb[65] vssa1 0.63fF
-C512 la_data_out[65] vssa1 0.26fF
-C513 la_data_in[65] vssa1 0.63fF
-C514 la_oenb[64] vssa1 0.63fF
-C515 la_data_out[64] vssa1 0.63fF
-C516 la_data_in[64] vssa1 0.63fF
-C517 la_oenb[63] vssa1 0.63fF
-C518 la_data_out[63] vssa1 0.63fF
-C519 la_data_in[63] vssa1 0.63fF
-C520 la_oenb[62] vssa1 0.63fF
-C521 la_data_out[62] vssa1 0.63fF
-C522 la_data_in[62] vssa1 0.63fF
-C523 la_oenb[61] vssa1 0.63fF
-C524 la_data_out[61] vssa1 0.63fF
-C525 la_oenb[60] vssa1 0.63fF
-C526 la_data_out[60] vssa1 0.63fF
-C527 la_data_in[60] vssa1 0.63fF
-C528 la_oenb[59] vssa1 0.63fF
-C529 la_data_out[59] vssa1 0.63fF
-C530 la_data_in[59] vssa1 0.63fF
-C531 la_oenb[58] vssa1 0.63fF
-C532 la_data_out[58] vssa1 0.63fF
-C533 la_data_in[58] vssa1 0.63fF
-C534 la_oenb[57] vssa1 0.63fF
-C535 la_data_out[57] vssa1 0.63fF
-C536 la_data_in[57] vssa1 0.63fF
-C537 la_data_out[56] vssa1 0.63fF
-C538 la_data_in[56] vssa1 0.63fF
-C539 la_oenb[55] vssa1 0.63fF
-C540 la_data_out[55] vssa1 0.63fF
-C541 la_data_in[55] vssa1 0.63fF
-C542 la_oenb[54] vssa1 0.63fF
-C543 la_data_out[54] vssa1 0.63fF
-C544 la_data_in[54] vssa1 0.63fF
-C545 la_oenb[53] vssa1 0.63fF
-C546 la_data_out[53] vssa1 0.63fF
-C547 la_data_in[53] vssa1 0.63fF
-C548 la_oenb[52] vssa1 0.63fF
-C549 la_data_in[52] vssa1 0.63fF
-C550 la_oenb[51] vssa1 0.63fF
-C551 la_data_out[51] vssa1 0.63fF
-C552 la_data_in[51] vssa1 0.63fF
-C553 la_oenb[50] vssa1 0.63fF
-C554 la_data_in[50] vssa1 0.63fF
-C555 la_oenb[49] vssa1 0.63fF
-C556 la_data_out[49] vssa1 0.63fF
-C557 la_data_in[49] vssa1 0.63fF
-C558 la_oenb[48] vssa1 0.63fF
-C559 la_data_out[48] vssa1 0.63fF
-C560 la_data_in[48] vssa1 0.63fF
-C561 la_oenb[47] vssa1 0.63fF
-C562 la_data_out[47] vssa1 0.63fF
-C563 la_data_in[47] vssa1 0.63fF
-C564 la_oenb[46] vssa1 0.63fF
-C565 la_data_out[46] vssa1 0.63fF
-C566 la_oenb[45] vssa1 0.63fF
-C567 la_data_out[45] vssa1 0.63fF
-C568 la_data_in[45] vssa1 0.63fF
-C569 la_oenb[44] vssa1 0.63fF
-C570 la_data_out[44] vssa1 0.63fF
-C571 la_data_in[44] vssa1 0.63fF
-C572 la_oenb[43] vssa1 0.63fF
-C573 la_data_out[43] vssa1 0.63fF
-C574 la_data_in[43] vssa1 0.63fF
-C575 la_oenb[42] vssa1 0.63fF
-C576 la_data_out[42] vssa1 0.63fF
-C577 la_data_in[42] vssa1 0.63fF
-C578 la_data_out[41] vssa1 0.63fF
-C579 la_data_in[41] vssa1 0.63fF
-C580 la_oenb[40] vssa1 0.63fF
-C581 la_data_out[40] vssa1 0.63fF
-C582 la_data_in[40] vssa1 0.63fF
-C583 la_oenb[39] vssa1 0.63fF
-C584 la_data_out[39] vssa1 0.63fF
-C585 la_data_in[39] vssa1 0.63fF
-C586 la_oenb[38] vssa1 0.63fF
-C587 la_data_out[38] vssa1 0.63fF
-C588 la_data_in[38] vssa1 0.63fF
-C589 la_oenb[37] vssa1 0.63fF
-C590 la_data_out[37] vssa1 0.26fF
-C591 la_data_in[37] vssa1 0.63fF
-C592 la_oenb[36] vssa1 0.63fF
-C593 la_data_out[36] vssa1 0.63fF
-C594 la_data_in[36] vssa1 0.63fF
-C595 la_oenb[35] vssa1 0.63fF
-C596 la_data_in[35] vssa1 0.63fF
-C597 la_oenb[34] vssa1 0.63fF
-C598 la_data_out[34] vssa1 0.63fF
-C599 la_data_in[34] vssa1 0.63fF
-C600 la_oenb[33] vssa1 0.63fF
-C601 la_data_out[33] vssa1 0.63fF
-C602 la_data_in[33] vssa1 0.63fF
-C603 la_oenb[32] vssa1 0.63fF
-C604 la_data_out[32] vssa1 0.63fF
-C605 la_data_in[32] vssa1 0.63fF
-C606 la_oenb[31] vssa1 0.63fF
-C607 la_data_out[31] vssa1 0.63fF
-C608 la_oenb[30] vssa1 0.63fF
-C609 la_data_out[30] vssa1 0.63fF
-C610 la_data_in[30] vssa1 0.63fF
-C611 la_oenb[29] vssa1 0.63fF
-C612 la_data_out[29] vssa1 0.63fF
-C613 la_data_in[29] vssa1 0.63fF
-C614 la_oenb[28] vssa1 0.63fF
-C615 la_data_out[28] vssa1 0.63fF
-C616 la_data_in[28] vssa1 0.63fF
-C617 la_oenb[27] vssa1 0.63fF
-C618 la_data_out[27] vssa1 0.63fF
-C619 la_data_in[27] vssa1 0.63fF
-C620 la_data_out[26] vssa1 0.63fF
-C621 la_data_in[26] vssa1 0.63fF
-C622 la_oenb[25] vssa1 0.63fF
-C623 la_data_out[25] vssa1 0.63fF
-C624 la_data_in[25] vssa1 0.63fF
-C625 la_oenb[24] vssa1 0.63fF
-C626 la_data_out[24] vssa1 0.63fF
-C627 la_data_in[24] vssa1 0.63fF
-C628 la_oenb[23] vssa1 0.63fF
-C629 la_data_out[23] vssa1 0.63fF
-C630 la_data_in[23] vssa1 0.63fF
-C631 la_oenb[22] vssa1 0.63fF
-C632 la_data_out[22] vssa1 0.63fF
-C633 la_data_in[22] vssa1 0.63fF
-C634 la_oenb[21] vssa1 0.63fF
-C635 la_data_out[21] vssa1 0.63fF
-C636 la_data_in[21] vssa1 0.63fF
-C637 la_oenb[20] vssa1 0.63fF
-C638 la_data_in[20] vssa1 0.63fF
-C639 la_oenb[19] vssa1 0.63fF
-C640 la_data_out[19] vssa1 0.63fF
-C641 la_data_in[19] vssa1 0.63fF
-C642 la_oenb[18] vssa1 0.63fF
-C643 la_data_out[18] vssa1 0.63fF
-C644 la_data_in[18] vssa1 0.63fF
-C645 la_oenb[17] vssa1 0.63fF
-C646 la_data_out[17] vssa1 0.63fF
-C647 la_data_in[17] vssa1 0.63fF
-C648 la_oenb[16] vssa1 0.63fF
-C649 la_data_out[16] vssa1 0.63fF
-C650 la_oenb[15] vssa1 0.63fF
-C651 la_data_out[15] vssa1 0.63fF
-C652 la_data_in[15] vssa1 0.63fF
-C653 la_oenb[14] vssa1 0.63fF
-C654 la_data_out[14] vssa1 0.63fF
-C655 la_data_in[14] vssa1 0.63fF
-C656 la_oenb[13] vssa1 0.63fF
-C657 la_data_out[13] vssa1 0.63fF
-C658 la_data_in[13] vssa1 0.63fF
-C659 la_oenb[12] vssa1 0.63fF
-C660 la_data_out[12] vssa1 0.63fF
-C661 la_data_in[12] vssa1 0.63fF
-C662 la_data_out[11] vssa1 0.63fF
-C663 la_data_in[11] vssa1 0.63fF
-C664 la_oenb[10] vssa1 0.63fF
-C665 la_data_out[10] vssa1 0.63fF
-C666 la_data_in[10] vssa1 0.63fF
-C667 la_data_out[9] vssa1 0.63fF
-C668 la_data_in[9] vssa1 0.63fF
-C669 la_oenb[8] vssa1 0.63fF
-C670 la_data_out[8] vssa1 0.63fF
-C671 la_data_in[8] vssa1 0.63fF
-C672 la_oenb[7] vssa1 0.63fF
-C673 la_data_out[7] vssa1 0.63fF
-C674 la_data_in[7] vssa1 0.63fF
-C675 la_oenb[6] vssa1 0.63fF
-C676 la_data_out[6] vssa1 0.63fF
-C677 la_data_in[6] vssa1 0.63fF
-C678 la_oenb[5] vssa1 0.63fF
-C679 la_data_in[5] vssa1 0.63fF
-C680 la_oenb[4] vssa1 0.63fF
-C681 la_data_out[4] vssa1 0.63fF
-C682 la_data_in[4] vssa1 0.63fF
-C683 la_oenb[3] vssa1 0.63fF
-C684 la_data_out[3] vssa1 0.63fF
-C685 la_data_in[3] vssa1 0.63fF
-C686 la_oenb[2] vssa1 0.63fF
-C687 la_data_out[2] vssa1 0.63fF
-C688 la_data_in[2] vssa1 0.63fF
-C689 la_oenb[1] vssa1 0.63fF
-C690 la_data_out[1] vssa1 0.63fF
-C691 la_oenb[0] vssa1 0.63fF
-C692 la_data_out[0] vssa1 0.63fF
-C693 la_data_in[0] vssa1 0.63fF
-C694 wbs_dat_o[31] vssa1 0.63fF
-C695 wbs_dat_i[31] vssa1 0.63fF
-C696 wbs_adr_i[31] vssa1 0.63fF
-C697 wbs_dat_o[30] vssa1 0.63fF
-C698 wbs_dat_i[30] vssa1 0.63fF
-C699 wbs_adr_i[30] vssa1 0.63fF
-C700 wbs_dat_o[29] vssa1 0.63fF
-C701 wbs_dat_i[29] vssa1 0.63fF
-C702 wbs_adr_i[29] vssa1 0.63fF
-C703 wbs_dat_i[28] vssa1 0.63fF
-C704 wbs_adr_i[28] vssa1 0.63fF
-C705 wbs_dat_o[27] vssa1 0.63fF
-C706 wbs_dat_i[27] vssa1 0.63fF
-C707 wbs_adr_i[27] vssa1 0.63fF
-C708 wbs_dat_i[26] vssa1 0.63fF
-C709 wbs_adr_i[26] vssa1 0.63fF
-C710 wbs_dat_o[25] vssa1 0.63fF
-C711 wbs_dat_i[25] vssa1 0.63fF
-C712 wbs_adr_i[25] vssa1 0.63fF
-C713 wbs_dat_o[24] vssa1 0.63fF
-C714 wbs_dat_i[24] vssa1 0.63fF
-C715 wbs_adr_i[24] vssa1 0.63fF
-C716 wbs_dat_o[23] vssa1 0.63fF
-C717 wbs_dat_i[23] vssa1 0.63fF
-C718 wbs_adr_i[23] vssa1 0.63fF
-C719 wbs_dat_o[22] vssa1 0.63fF
-C720 wbs_adr_i[22] vssa1 0.63fF
-C721 wbs_dat_o[21] vssa1 0.63fF
-C722 wbs_dat_i[21] vssa1 0.63fF
-C723 wbs_adr_i[21] vssa1 0.63fF
-C724 wbs_dat_o[20] vssa1 0.63fF
-C725 wbs_dat_i[20] vssa1 0.63fF
-C726 wbs_adr_i[20] vssa1 0.63fF
-C727 wbs_dat_o[19] vssa1 0.63fF
-C728 wbs_dat_i[19] vssa1 0.63fF
-C729 wbs_adr_i[19] vssa1 0.63fF
-C730 wbs_dat_o[18] vssa1 0.63fF
-C731 wbs_dat_i[18] vssa1 0.63fF
-C732 wbs_dat_o[17] vssa1 0.63fF
-C733 wbs_dat_i[17] vssa1 0.63fF
-C734 wbs_adr_i[17] vssa1 0.63fF
-C735 wbs_dat_o[16] vssa1 0.63fF
-C736 wbs_dat_i[16] vssa1 0.63fF
-C737 wbs_adr_i[16] vssa1 0.63fF
-C738 wbs_dat_o[15] vssa1 0.63fF
-C739 wbs_dat_i[15] vssa1 0.63fF
-C740 wbs_adr_i[15] vssa1 0.63fF
-C741 wbs_dat_o[14] vssa1 0.63fF
-C742 wbs_dat_i[14] vssa1 0.63fF
-C743 wbs_adr_i[14] vssa1 0.63fF
-C744 wbs_dat_o[13] vssa1 0.63fF
-C745 wbs_dat_i[13] vssa1 0.63fF
-C746 wbs_adr_i[13] vssa1 0.63fF
-C747 wbs_dat_o[12] vssa1 0.63fF
-C748 wbs_dat_i[12] vssa1 0.63fF
-C749 wbs_adr_i[12] vssa1 0.63fF
-C750 wbs_dat_i[11] vssa1 0.63fF
-C751 wbs_adr_i[11] vssa1 0.63fF
-C752 wbs_dat_o[10] vssa1 0.63fF
-C753 wbs_dat_i[10] vssa1 0.63fF
-C754 wbs_adr_i[10] vssa1 0.63fF
-C755 wbs_dat_o[9] vssa1 0.63fF
-C756 wbs_dat_i[9] vssa1 0.63fF
-C757 wbs_adr_i[9] vssa1 0.63fF
-C758 wbs_dat_o[8] vssa1 0.63fF
-C759 wbs_dat_i[8] vssa1 0.63fF
-C760 wbs_adr_i[8] vssa1 0.63fF
-C761 wbs_dat_o[7] vssa1 0.63fF
-C762 wbs_adr_i[7] vssa1 0.63fF
-C763 wbs_dat_o[6] vssa1 0.63fF
-C764 wbs_dat_i[6] vssa1 0.63fF
-C765 wbs_adr_i[6] vssa1 0.63fF
-C766 wbs_dat_o[5] vssa1 0.63fF
-C767 wbs_dat_i[5] vssa1 0.63fF
-C768 wbs_adr_i[5] vssa1 0.63fF
-C769 wbs_dat_o[4] vssa1 0.63fF
-C770 wbs_dat_i[4] vssa1 0.63fF
-C771 wbs_adr_i[4] vssa1 0.63fF
-C772 wbs_sel_i[3] vssa1 0.63fF
-C773 wbs_dat_o[3] vssa1 0.63fF
-C774 wbs_adr_i[3] vssa1 0.63fF
-C775 wbs_sel_i[2] vssa1 0.63fF
-C776 wbs_dat_o[2] vssa1 0.63fF
-C777 wbs_dat_i[2] vssa1 0.63fF
-C778 wbs_adr_i[2] vssa1 0.63fF
-C779 wbs_dat_o[1] vssa1 0.63fF
-C780 wbs_dat_i[1] vssa1 0.63fF
-C781 wbs_adr_i[1] vssa1 0.63fF
-C782 wbs_sel_i[0] vssa1 0.63fF
-C783 wbs_dat_o[0] vssa1 0.63fF
-C784 wbs_dat_i[0] vssa1 0.63fF
-C785 wbs_adr_i[0] vssa1 0.63fF
-C786 wbs_we_i vssa1 0.63fF
-C787 wbs_stb_i vssa1 0.63fF
-C788 wbs_cyc_i vssa1 0.63fF
-C789 wbs_ack_o vssa1 0.63fF
-C790 wb_rst_i vssa1 0.63fF
-C791 m3_226242_702300# vssa1 -1.31fF
-C792 m3_222594_702300# vssa1 0.55fF
-C793 top_pll_v2_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C794 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C795 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C796 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C797 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C798 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C799 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C800 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C801 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C802 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C803 top_pll_v2_0/QB vssa1 4.35fF
-C804 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C805 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C806 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C807 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C808 top_pll_v2_0/out_div_by_5 vssa1 -0.40fF
-C809 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C810 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C811 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C812 top_pll_v2_0/pfd_reset vssa1 2.17fF
-C813 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C814 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C815 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C816 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C817 top_pll_v2_0/QA vssa1 4.22fF
-C818 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C819 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C820 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C821 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C822 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C823 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C824 top_pll_v2_0/nUp vssa1 5.39fF
-C825 top_pll_v2_0/Up vssa1 1.85fF
-C826 top_pll_v2_0/Down vssa1 6.19fF
-C827 top_pll_v2_0/nDown vssa1 -3.53fF
-C828 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C829 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C830 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C831 top_pll_v2_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C832 top_pll_v2_0/div_5_Q1_shift vssa1 -0.14fF
-C833 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C834 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C835 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C836 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C837 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C838 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C839 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C840 top_pll_v2_0/div_5_Q1 vssa1 4.25fF
-C841 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C842 top_pll_v2_0/div_5_nQ0 vssa1 0.59fF
-C843 top_pll_v2_0/div_5_Q0 vssa1 0.01fF
-C844 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C845 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C846 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C847 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C848 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C849 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C850 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C851 top_pll_v2_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C852 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C853 top_pll_v2_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C854 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C855 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C856 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C857 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C858 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C859 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C860 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C861 top_pll_v2_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C862 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C863 top_pll_v2_0/div_5_nQ2 vssa1 1.24fF
-C864 top_pll_v2_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C865 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C866 top_pll_v2_0/n_out_by_2 vssa1 -2.75fF
-C867 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C868 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C869 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C870 top_pll_v2_0/out_by_2 vssa1 -5.01fF
-C871 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C872 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C873 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C874 top_pll_v2_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C875 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C876 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C877 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C878 top_pll_v2_0/out_first_buffer vssa1 2.88fF
-C879 top_pll_v2_0/out_to_div vssa1 4.23fF
-C880 top_pll_v2_0/out_to_buffer vssa1 1.54fF
-C881 top_pll_v2_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C882 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C883 top_pll_v2_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C884 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C885 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C886 top_pll_v2_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C887 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C888 top_pll_v2_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C889 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C890 top_pll_v2_0/vco_out vssa1 1.01fF
-C891 top_pll_v2_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C892 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C893 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C894 top_pll_v2_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
-C895 io_analog[8] vssa1 13.78fF
-C896 top_pll_v2_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C897 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C898 top_pll_v2_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C899 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C900 top_pll_v2_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C901 top_pll_v2_0/out_buffer_div_2 vssa1 1.60fF
-C902 top_pll_v2_0/n_out_buffer_div_2 vssa1 1.63fF
-C903 top_pll_v2_0/out_div_2 vssa1 -1.30fF
-C904 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C905 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C906 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C907 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C908 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C909 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C910 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C911 top_pll_v2_0/n_out_div_2 vssa1 1.95fF
-C912 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C913 top_pll_v2_0/lf_vc vssa1 -59.89fF
-C914 top_pll_v2_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
-C915 gpio_noesd[8] vssa1 210.79fF
-C916 top_pll_v2_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
-C917 top_pll_v2_0/nswitch vssa1 3.73fF
-C918 top_pll_v2_0/biasp vssa1 5.44fF
-C919 bias_0/iref_1 vssa1 -91.53fF
-C920 top_pll_v2_0/vco_vctrl vssa1 -20.08fF
-C921 top_pll_v2_0/pswitch vssa1 3.57fF
-C922 io_analog[5] vssa1 33.29fF
-C923 bias_0/iref_4 vssa1 1.17fF
-C924 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vssa1 2.60fF
-C925 bias_0/iref_3 vssa1 0.64fF
-C926 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vssa1 2.60fF
-C927 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vssa1 2.60fF
-C928 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vssa1 2.60fF
-C929 bias_0/m1_20168_984# vssa1 56.92fF
-C930 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vssa1 2.60fF
-C931 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vssa1 2.60fF
-C932 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vssa1 2.60fF
-C933 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vssa1 2.60fF
-C934 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vssa1 2.60fF
-C935 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vssa1 2.60fF
-C936 top_pll_v1_1/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C937 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C938 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C939 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C940 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C941 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C942 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C943 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C944 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C945 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C946 top_pll_v1_1/QB vssa1 4.35fF
-C947 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C948 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C949 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C950 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C951 top_pll_v1_1/out_div_by_5 vssa1 -0.40fF
-C952 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C953 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C954 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C955 top_pll_v1_1/pfd_reset vssa1 2.17fF
-C956 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C957 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C958 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C959 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C960 top_pll_v1_1/QA vssa1 4.22fF
-C961 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C962 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C963 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C964 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C965 io_analog[10] vssa1 503.33fF
-C966 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C967 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C968 top_pll_v1_1/nUp vssa1 5.39fF
-C969 top_pll_v1_1/Up vssa1 1.85fF
-C970 top_pll_v1_1/Down vssa1 6.19fF
-C971 top_pll_v1_1/nDown vssa1 -3.53fF
-C972 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C973 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C974 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C975 top_pll_v1_1/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C976 top_pll_v1_1/div_5_Q1_shift vssa1 -0.14fF
-C977 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C978 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C979 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C980 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C981 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C982 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C983 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C984 top_pll_v1_1/div_5_Q1 vssa1 4.25fF
-C985 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C986 top_pll_v1_1/div_5_nQ0 vssa1 0.59fF
-C987 top_pll_v1_1/div_5_Q0 vssa1 0.01fF
-C988 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C989 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C990 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C991 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C992 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C993 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C994 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C995 top_pll_v1_1/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C996 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C997 top_pll_v1_1/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C998 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C999 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C1000 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C1001 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1002 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1003 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C1004 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1005 top_pll_v1_1/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C1006 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C1007 top_pll_v1_1/div_5_nQ2 vssa1 1.24fF
-C1008 top_pll_v1_1/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C1009 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1010 top_pll_v1_1/n_out_by_2 vssa1 -2.75fF
-C1011 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1012 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1013 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1014 top_pll_v1_1/out_by_2 vssa1 -5.01fF
-C1015 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1016 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1017 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1018 top_pll_v1_1/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C1019 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1020 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C1021 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C1022 top_pll_v1_1/out_first_buffer vssa1 2.88fF
-C1023 top_pll_v1_1/out_to_div vssa1 4.23fF
-C1024 top_pll_v1_1/out_to_buffer vssa1 1.54fF
-C1025 top_pll_v1_1/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C1026 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C1027 top_pll_v1_1/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C1028 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C1029 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C1030 top_pll_v1_1/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C1031 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C1032 top_pll_v1_1/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C1033 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C1034 top_pll_v1_1/vco_out vssa1 1.01fF
-C1035 top_pll_v1_1/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C1036 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C1037 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C1038 top_pll_v1_1/buffer_salida_0/a_3996_n100# vssa1 48.11fF
-C1039 io_analog[7] vssa1 24.61fF
-C1040 top_pll_v1_1/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C1041 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1042 top_pll_v1_1/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C1043 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1044 top_pll_v1_1/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C1045 top_pll_v1_1/out_buffer_div_2 vssa1 1.60fF
-C1046 top_pll_v1_1/n_out_buffer_div_2 vssa1 1.63fF
-C1047 top_pll_v1_1/out_div_2 vssa1 -1.30fF
-C1048 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1049 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1050 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1051 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1052 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1053 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1054 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1055 top_pll_v1_1/n_out_div_2 vssa1 1.95fF
-C1056 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1057 top_pll_v1_1/nswitch vssa1 3.73fF
-C1058 top_pll_v1_1/biasp vssa1 5.44fF
-C1059 bias_0/iref_0 vssa1 -81.35fF
-C1060 top_pll_v1_1/vco_vctrl vssa1 -18.17fF
-C1061 top_pll_v1_1/pswitch vssa1 3.57fF
-C1062 top_pll_v1_1/lf_vc vssa1 -59.89fF
-C1063 top_pll_v1_1/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
-C1064 top_pll_v1_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C1065 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C1066 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C1067 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1068 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C1069 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1070 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1071 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1072 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C1073 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1074 top_pll_v1_0/QB vssa1 4.35fF
-C1075 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1076 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C1077 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1078 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1079 top_pll_v1_0/out_div_by_5 vssa1 -0.40fF
-C1080 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1081 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C1082 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1083 top_pll_v1_0/pfd_reset vssa1 2.17fF
-C1084 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1085 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1086 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C1087 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1088 top_pll_v1_0/QA vssa1 4.22fF
-C1089 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1090 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C1091 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1092 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1093 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C1094 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C1095 top_pll_v1_0/nUp vssa1 5.39fF
-C1096 top_pll_v1_0/Up vssa1 1.85fF
-C1097 top_pll_v1_0/Down vssa1 6.19fF
-C1098 top_pll_v1_0/nDown vssa1 -3.53fF
-C1099 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C1100 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C1101 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C1102 top_pll_v1_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C1103 top_pll_v1_0/div_5_Q1_shift vssa1 -0.14fF
-C1104 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1105 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C1106 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C1107 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1108 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1109 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C1110 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1111 top_pll_v1_0/div_5_Q1 vssa1 4.25fF
-C1112 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C1113 top_pll_v1_0/div_5_nQ0 vssa1 0.59fF
-C1114 top_pll_v1_0/div_5_Q0 vssa1 0.01fF
-C1115 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1116 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C1117 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C1118 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1119 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1120 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C1121 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1122 top_pll_v1_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C1123 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C1124 top_pll_v1_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C1125 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1126 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C1127 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C1128 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1129 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1130 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C1131 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1132 top_pll_v1_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C1133 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C1134 top_pll_v1_0/div_5_nQ2 vssa1 1.24fF
-C1135 top_pll_v1_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C1136 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1137 top_pll_v1_0/n_out_by_2 vssa1 -2.75fF
-C1138 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1139 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1140 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1141 top_pll_v1_0/out_by_2 vssa1 -5.01fF
-C1142 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1143 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1144 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1145 top_pll_v1_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C1146 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1147 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C1148 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C1149 top_pll_v1_0/out_first_buffer vssa1 2.88fF
-C1150 top_pll_v1_0/out_to_div vssa1 4.23fF
-C1151 top_pll_v1_0/out_to_buffer vssa1 1.54fF
-C1152 top_pll_v1_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C1153 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C1154 top_pll_v1_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C1155 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C1156 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C1157 top_pll_v1_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C1158 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C1159 top_pll_v1_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C1160 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C1161 top_pll_v1_0/vco_out vssa1 1.01fF
-C1162 gpio_noesd[7] vssa1 272.21fF
-C1163 top_pll_v1_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C1164 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C1165 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C1166 top_pll_v1_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
-C1167 io_analog[9] vssa1 7.89fF
-C1168 top_pll_v1_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C1169 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1170 top_pll_v1_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C1171 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1172 top_pll_v1_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C1173 top_pll_v1_0/out_buffer_div_2 vssa1 1.60fF
-C1174 top_pll_v1_0/n_out_buffer_div_2 vssa1 1.63fF
-C1175 top_pll_v1_0/out_div_2 vssa1 -1.30fF
-C1176 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1177 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1178 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1179 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1180 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1181 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1182 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1183 top_pll_v1_0/n_out_div_2 vssa1 1.95fF
-C1184 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1185 top_pll_v1_0/nswitch vssa1 3.73fF
-C1186 top_pll_v1_0/biasp vssa1 5.44fF
-C1187 bias_0/iref_2 vssa1 -178.91fF
-C1188 top_pll_v1_0/vco_vctrl vssa1 -18.17fF
-C1189 top_pll_v1_0/pswitch vssa1 3.57fF
-C1190 top_pll_v1_0/lf_vc vssa1 -59.89fF
-C1191 top_pll_v1_0/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
-C1192 bias_0/iref_6 vssa1 -645.65fF
-C1193 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in vssa1 -32.98fF
-C1194 io_analog[1] vssa1 74.58fF
-C1195 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# vssa1 1.29fF
-C1196 bias_0/iref_5 vssa1 -623.45fF
-C1197 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in vssa1 -32.98fF
-C1198 io_analog[0] vssa1 -154.61fF
-C1199 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# vssa1 1.29fF
-C1200 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# vssa1 -35.44fF
-C1201 bias_0/iref_8 vssa1 -189.06fF
-C1202 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# vssa1 -35.44fF
-C1203 bias_0/iref_7 vssa1 -205.18fF
-C1204 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# vssa1 -1.87fF
-C1205 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# vssa1 0.47fF
-C1206 gpio_noesd[5] vssa1 122.09fF
-C1207 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# vssa1 -1.10fF
-C1208 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl vssa1 -2.03fF
-C1209 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# vssa1 -2.23fF
-C1210 gpio_noesd[6] vssa1 325.91fF
-C1211 gpio_noesd[4] vssa1 116.78fF
-C1212 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# vssa1 -1.03fF
-C1213 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# vssa1 0.51fF
-C1214 bias_0/iref_9 vssa1 -181.57fF
-C1215 res_amp_top_0/res_amp_lin_prog_0/outn vssa1 1.55fF
-C1216 io_analog[3] vssa1 -119.52fF
-C1217 res_amp_top_0/res_amp_lin_prog_0/outp vssa1 -4.89fF
-C1218 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp vssa1 -4.89fF
-C1219 io_analog[2] vssa1 -131.04fF
-C1220 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# vssa1 -0.95fF
-C1221 res_amp_top_0/res_amp_lin_prog_0/outn_cap vssa1 -0.01fF
-C1222 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk vssa1 4.27fF
-C1223 res_amp_top_0/res_amp_lin_prog_0/inverter_min_x4_0/out vssa1 4.60fF
-C1224 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in vssa1 1.07fF
-C1225 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in vssa1 1.03fF
-C1226 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in vssa1 1.03fF
-C1227 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in vssa1 1.07fF
-C1228 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in vssa1 1.03fF
-C1229 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in vssa1 1.03fF
-C1230 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in vssa1 1.07fF
-C1231 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in vssa1 1.03fF
-C1232 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in vssa1 1.07fF
-C1233 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in vssa1 1.03fF
-C1234 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in vssa1 1.03fF
-C1235 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in vssa1 1.03fF
-C1236 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in vssa1 1.07fF
-C1237 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB vssa1 -7.88fF
-C1238 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in vssa1 1.03fF
-C1239 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in vssa1 1.03fF
-C1240 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in vssa1 1.07fF
-C1241 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in vssa1 1.03fF
-C1242 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
-C1243 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in vssa1 1.03fF
-C1244 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b vssa1 2.03fF
-C1245 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 vssa1 1.54fF
-C1246 gpio_noesd[3] vssa1 213.06fF
-C1247 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b vssa1 2.03fF
-C1248 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out vssa1 -1.67fF
-C1249 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA vssa1 -2.58fF
-C1250 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b vssa1 2.03fF
-C1251 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out vssa1 -2.25fF
-C1252 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA vssa1 -0.04fF
-C1253 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b vssa1 2.03fF
-C1254 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out vssa1 -2.69fF
-C1255 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB vssa1 -4.96fF
-C1256 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b vssa1 2.03fF
-C1257 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out vssa1 -4.71fF
-C1258 gpio_noesd[2] vssa1 216.13fF
-C1259 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA vssa1 0.63fF
-C1260 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b vssa1 2.03fF
-C1261 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out vssa1 -2.49fF
-C1262 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB vssa1 -3.92fF
-C1263 gpio_noesd[1] vssa1 230.09fF
-C1264 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b vssa1 2.03fF
-C1265 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out vssa1 -0.27fF
-C1266 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB vssa1 -0.97fF
-C1267 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in vssa1 1.07fF
-C1268 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in vssa1 1.03fF
-C1269 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in vssa1 1.03fF
-C1270 res_amp_top_0/res_amp_lin_prog_0/outp_cap vssa1 -7.66fF
-C1271 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/m1_21_n341# vssa1 0.72fF
-C1272 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
-C1273 res_amp_top_0/res_amp_lin_prog_0/clk vssa1 -8.26fF
-C1274 res_amp_top_0/res_amp_sync_v2_0/inverter_min_x4_4/out vssa1 5.85fF
-C1275 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/out vssa1 1.70fF
-C1276 res_amp_top_0/res_amp_sync_v2_0/rst vssa1 -7.88fF
-C1277 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/nQ vssa1 0.48fF
-C1278 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/Q vssa1 -2.08fF
-C1279 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1280 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD vssa1 0.57fF
-C1281 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D vssa1 -1.73fF
-C1282 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1283 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1284 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D vssa1 0.96fF
-C1285 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1286 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/D vssa1 1.83fF
-C1287 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD vssa1 1.14fF
-C1288 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/out vssa1 1.20fF
-C1289 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/Q vssa1 -4.73fF
-C1290 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/nQ vssa1 0.48fF
-C1291 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/Q vssa1 -2.94fF
-C1292 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1293 io_analog[4] vssa1 -253.69fF
-C1294 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C1295 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C1296 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1297 io_analog[6] vssa1 -26.69fF
-C1298 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1299 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C1300 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1301 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/D vssa1 0.79fF
-C1302 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C1303 vdda1 vssa1 7275.97fF
-C1304 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/nQ vssa1 0.48fF
-C1305 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/Q vssa1 -1.08fF
-C1306 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1307 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C1308 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C1309 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1310 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1311 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C1312 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1313 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/D vssa1 -0.38fF
-C1314 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C1315 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/nQ vssa1 0.48fF
-C1316 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1317 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C1318 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C1319 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1320 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1321 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C1322 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1323 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/D vssa1 -1.04fF
-C1324 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C1325 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/nQ vssa1 0.48fF
-C1326 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1327 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1328 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1329 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1330 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1331 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1332 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1333 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C0 vdda1 gpio_noesd[9] 65.72fF
+C1 top_pll_v3_0/clk_1 gpio_noesd[10] 0.49fF
+C2 vdda1 top_pll_v2_0/pswitch 0.34fF
+C3 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in 0.18fF
+C4 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp 2.10fF
+C5 gpio_noesd[4] io_analog[3] -0.78fF
+C6 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_8 0.11fF
+C7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_6 0.15fF
+C8 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA gpio_noesd[1] 0.29fF
+C9 bias_0/iref_2 io_analog[8] 14.44fF
+C10 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA gpio_noesd[2] 0.72fF
+C11 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in gpio_noesd[5] 0.05fF
+C12 io_analog[2] gpio_noesd[5] 0.09fF
+C13 vdda1 top_pll_v2_0/nUp 0.01fF
+C14 vdda1 io_analog[0] 76.77fF
+C15 bias_0/iref_1 top_pll_v2_0/nDown 0.54fF
+C16 vdda1 io_analog[9] 30.05fF
+C17 bias_0/iref_2 top_pll_v1_0/nDown 0.70fF
+C18 top_pll_v3_0/lf_vc gpio_noesd[10] 0.48fF
+C19 gpio_noesd[4] bias_0/iref_9 -0.25fF
+C20 io_analog[4] bias_0/iref_6 15.97fF
+C21 res_amp_top_0/res_amp_lin_prog_0/outn gpio_noesd[5] 1.42fF
+C22 bias_0/iref_2 top_pll_v1_0/charge_pump_0/w_2544_775# 0.02fF
+C23 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.17fF
+C24 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[2] 0.21fF
+C25 io_analog[10] top_pll_v1_0/QA 0.03fF
+C26 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp 1.01fF
+C27 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out gpio_noesd[3] 0.33fF
+C28 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[6] 2.12fF
+C29 gpio_noesd[9] gpio_noesd[11] 0.96fF
+C30 top_pll_v3_0/out_to_div gpio_noesd[7] 4.28fF
+C31 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outp 0.61fF
+C32 vdda1 top_pll_v3_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.12fF
+C33 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_5 0.45fF
+C34 bias_0/iref_2 io_analog[9] 14.44fF
+C35 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in gpio_noesd[5] 0.47fF
+C36 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA gpio_noesd[3] 0.01fF
+C37 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# -0.11fF
+C38 vdda1 top_pll_v1_0/nUp 0.01fF
+C39 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.78fF
+C40 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out 0.57fF
+C41 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp gpio_noesd[5] 0.54fF
+C42 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.04fF
+C43 bias_0/iref_1 top_pll_v2_0/Up 0.54fF
+C44 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[3] 0.03fF
+C45 io_analog[4] bias_0/iref_5 15.97fF
+C46 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out 0.21fF
+C47 vdda1 io_analog[3] 25.90fF
+C48 bias_0/iref_2 top_pll_v1_0/nUp 0.70fF
+C49 gpio_noesd[10] top_pll_v3_0/out_by_2 0.10fF
+C50 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl gpio_noesd[5] 0.33fF
+C51 gpio_noesd[7] top_pll_v2_0/vco_vctrl 0.05fF
+C52 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.17fF
+C53 vdda1 bias_0/iref_7 33.08fF
+C54 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[5] 0.14fF
+C55 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB gpio_noesd[5] 0.14fF
+C56 vdda1 bias_0/iref_9 30.24fF
+C57 io_analog[10] gpio_noesd[7] 29.88fF
+C58 io_analog[6] io_clamp_high[2] 0.53fF
+C59 top_pll_v1_0/vco_vctrl gpio_noesd[7] 0.05fF
+C60 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out gpio_noesd[2] 0.38fF
+C61 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[4] -0.13fF
+C62 bias_0/iref_1 top_pll_v2_0/biasp 2.20fF
+C63 vdda1 gpio_noesd[6] 53.94fF
+C64 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outp -0.31fF
+C65 bias_0/iref_5 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.46fF
+C66 top_pll_v3_0/vco_vctrl gpio_noesd[10] 0.53fF
+C67 io_analog[4] io_clamp_high[0] 0.53fF
+C68 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.04fF
+C69 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[4] -0.01fF
+C70 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C71 vdda1 bias_0/iref_8 31.37fF
+C72 top_pll_v3_0/lf_vc gpio_noesd[8] 2.98fF
+C73 io_analog[3] bias_0/iref_6 13.88fF
+C74 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in -0.70fF
+C75 bias_0/iref_0 top_pll_v3_0/charge_pump_0/w_2544_775# 0.21fF
+C76 vdda1 top_pll_v2_0/biasp 0.03fF
+C77 bias_0/iref_7 bias_0/iref_6 17.40fF
+C78 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.94fF
+C79 bias_0/iref_0 top_pll_v3_0/Up 0.74fF
+C80 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# gpio_noesd[5] 0.16fF
+C81 gpio_noesd[9] io_analog[10] 1.87fF
+C82 vdda1 gpio_noesd[10] 53.94fF
+C83 vdda1 gpio_noesd[4] 117.64fF
+C84 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.01fF
+C85 io_analog[3] bias_0/iref_5 13.88fF
+C86 bias_0/iref_1 top_pll_v2_0/Down 0.91fF
+C87 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[5] 0.26fF
+C88 io_analog[2] io_analog[3] 0.14fF
+C89 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C90 bias_0/iref_7 bias_0/iref_5 10.35fF
+C91 io_analog[2] bias_0/iref_7 13.88fF
+C92 bias_0/iref_0 top_pll_v3_0/nUp 0.74fF
+C93 io_analog[6] gpio_noesd[10] 25.05fF
+C94 vdda1 bias_0/iref_1 15.26fF
+C95 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out gpio_noesd[2] 0.21fF
+C96 io_analog[2] bias_0/iref_9 13.88fF
+C97 vdda1 top_pll_v1_0/biasp 0.03fF
+C98 io_analog[3] gpio_noesd[5] 0.12fF
+C99 gpio_noesd[10] top_pll_v3_0/freq_div_0/prescaler_23_0/nCLK_23 1.35fF
+C100 vdda1 top_pll_v3_0/buffer_salida_0/a_3996_n100# 1.78fF
+C101 io_analog[5] io_clamp_high[1] 0.53fF
+C102 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/clk 0.39fF
+C103 gpio_noesd[10] gpio_noesd[11] 39.51fF
+C104 bias_0/iref_8 bias_0/iref_5 10.19fF
+C105 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out gpio_noesd[4] 0.19fF
+C106 io_analog[2] bias_0/iref_8 13.88fF
+C107 io_analog[6] bias_0/iref_1 13.22fF
+C108 bias_0/iref_2 top_pll_v1_0/biasp 3.20fF
+C109 bias_0/iref_9 gpio_noesd[5] 1.30fF
+C110 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in 0.12fF
+C111 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outn 0.45fF
+C112 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA gpio_noesd[4] 0.42fF
+C113 io_analog[7] bias_0/iref_1 13.22fF
+C114 gpio_noesd[6] gpio_noesd[5] 0.05fF
+C115 top_pll_v3_0/buffer_salida_0/a_3996_n100# io_analog[7] -0.08fF
+C116 gpio_noesd[10] top_pll_v3_0/s_0_n 0.31fF
+C117 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB gpio_noesd[2] 0.19fF
+C118 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# 0.45fF
+C119 vdda1 top_pll_v2_0/buffer_salida_0/a_3996_n100# 0.05fF
+C120 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# bias_0/iref_7 0.09fF
+C121 vdda1 top_pll_v3_0/buffer_salida_0/a_678_n100# 0.50fF
+C122 vdda1 bias_0/iref_2 3.90fF
+C123 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.42fF
+C124 vdda1 top_pll_v3_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.12fF
+C125 vdda1 io_analog[6] 124.15fF
+C126 vdda1 gpio_noesd[8] 77.43fF
+C127 gpio_noesd[10] top_pll_v3_0/clk_0 0.12fF
+C128 bias_0/iref_2 top_pll_v1_0/Down 1.11fF
+C129 vdda1 gpio_noesd[1] 214.54fF
+C130 io_analog[4] bias_0/iref_7 15.97fF
+C131 vdda1 io_analog[7] 29.48fF
+C132 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.22fF
+C133 gpio_noesd[9] top_pll_v3_0/clk_d 0.15fF
+C134 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C135 gpio_noesd[4] io_analog[2] -0.21fF
+C136 vdda1 gpio_noesd[11] 102.31fF
+C137 vdda1 top_pll_v1_0/pswitch 0.38fF
+C138 vdda1 top_pll_v1_0/buffer_salida_0/a_3996_n100# 0.06fF
+C139 io_analog[4] bias_0/iref_9 15.97fF
+C140 io_analog[6] bias_0/iref_2 54.67fF
+C141 vdda1 top_pll_v3_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.12fF
+C142 bias_0/iref_0 top_pll_v3_0/nDown 0.74fF
+C143 io_analog[7] bias_0/iref_2 13.22fF
+C144 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outn -1.06fF
+C145 vdda1 bias_0/iref_6 29.75fF
+C146 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[5] 0.44fF
+C147 gpio_noesd[4] gpio_noesd[5] 4.67fF
+C148 bias_0/iref_2 top_pll_v1_0/Up 0.70fF
+C149 res_amp_top_0/res_amp_lin_prog_0/outp gpio_noesd[5] 0.44fF
+C150 io_analog[4] bias_0/iref_8 15.97fF
+C151 io_analog[6] gpio_noesd[11] 9.16fF
+C152 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.46fF
+C153 io_analog[6] io_clamp_low[2] 0.53fF
+C154 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[5] 0.68fF
+C155 gpio_noesd[11] top_pll_v3_0/freq_div_0/prescaler_23_0/nCLK_23 0.17fF
+C156 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.17fF
+C157 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA 0.49fF
+C158 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp 0.17fF
+C159 io_analog[4] io_clamp_low[0] 0.53fF
+C160 top_pll_v3_0/vco_vctrl gpio_noesd[7] 0.13fF
+C161 gpio_noesd[5] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.32fF
+C162 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_7 0.37fF
+C163 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in 0.23fF
+C164 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.07fF
+C165 gpio_noesd[10] io_analog[10] 1.87fF
+C166 vdda1 bias_0/iref_5 30.67fF
+C167 bias_0/iref_8 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.34fF
+C168 vdda1 io_analog[2] 25.90fF
+C169 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# -0.08fF
+C170 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.04fF
+C171 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[2] 0.37fF
+C172 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.08fF
+C173 top_pll_v3_0/loop_filter_v2_0/cap3_loop_filter_0/in gpio_noesd[8] 3.13fF
+C174 vdda1 io_analog[1] 76.56fF
+C175 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_8 0.37fF
+C176 bias_0/iref_0 top_pll_v3_0/Down 1.08fF
+C177 vdda1 gpio_noesd[5] 124.75fF
+C178 bias_0/iref_1 top_pll_v2_0/charge_pump_0/w_2544_775# 0.09fF
+C179 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b 0.31fF
+C180 io_analog[3] bias_0/iref_7 13.88fF
+C181 vdda1 top_pll_v3_0/ring_osc_0/csvco_branch_2/vbp 1.07fF
+C182 vdda1 gpio_noesd[7] 120.96fF
+C183 gpio_noesd[10] gpio_noesd[9] 0.96fF
+C184 bias_0/iref_0 top_pll_v3_0/charge_pump_0/w_1008_774# 0.21fF
+C185 vdda1 top_pll_v2_0/vco_vctrl 0.59fF
+C186 io_analog[3] bias_0/iref_9 13.88fF
+C187 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[3] 0.21fF
+C188 bias_0/iref_0 vdda1 15.18fF
+C189 gpio_noesd[10] top_pll_v3_0/n_clk_0 0.10fF
+C190 bias_0/iref_5 bias_0/iref_6 29.11fF
+C191 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in bias_0/iref_5 0.46fF
+C192 gpio_noesd[7] top_pll_v2_0/out_to_div 0.23fF
+C193 vdda1 io_analog[10] 0.01fF
+C194 io_analog[2] bias_0/iref_6 13.88fF
+C195 vdda1 top_pll_v1_0/vco_vctrl 0.43fF
+C196 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# 0.18fF
+C197 io_analog[3] bias_0/iref_8 13.88fF
+C198 gpio_noesd[8] gpio_noesd[7] 5.92fF
+C199 vdda1 gpio_noesd[2] 214.16fF
+C200 bias_0/iref_7 bias_0/iref_8 13.23fF
+C201 bias_0/iref_0 io_analog[6] 6.93fF
+C202 io_analog[5] io_clamp_low[1] 0.53fF
+C203 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in 0.20fF
+C204 vdda1 io_analog[4] 182.26fF
+C205 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_7 0.40fF
+C206 gpio_noesd[9] top_pll_v3_0/out_div 0.16fF
+C207 top_pll_v3_0/s_1_n gpio_noesd[9] 0.08fF
+C208 gpio_noesd[8] io_analog[10] 20.65fF
+C209 bias_0/iref_9 bias_0/iref_8 9.89fF
+C210 bias_0/iref_0 top_pll_v3_0/biasp 3.13fF
+C211 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b 0.23fF
+C212 top_pll_v1_0/out_to_div gpio_noesd[7] 0.23fF
+C213 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[4] -0.05fF
+C214 bias_0/iref_1 top_pll_v2_0/nUp 0.22fF
+C215 res_amp_top_0/res_amp_sync_v2_0/rst bias_0/iref_9 0.39fF
+C216 gpio_noesd[1] gpio_noesd[2] 0.30fF
+C217 bias_0/iref_5 io_analog[5] 0.09fF
+C218 io_analog[2] bias_0/iref_5 13.88fF
+C219 vdda1 gpio_noesd[3] 120.88fF
+C220 gpio_noesd[11] io_analog[10] 1.87fF
+C221 vdda1 io_analog[8] 29.93fF
+C222 io_analog[6] io_analog[4] 0.59fF
+C223 io_in_3v3[0] vssa1 0.41fF
+C224 io_oeb[26] vssa1 0.61fF
+C225 io_in[0] vssa1 0.41fF
+C226 io_out[26] vssa1 0.61fF
+C227 io_out[0] vssa1 0.41fF
+C228 io_in[26] vssa1 0.61fF
+C229 io_oeb[0] vssa1 0.41fF
+C230 io_in_3v3[26] vssa1 0.61fF
+C231 io_in_3v3[1] vssa1 0.41fF
+C232 io_oeb[25] vssa1 0.61fF
+C233 io_in[1] vssa1 0.41fF
+C234 io_out[25] vssa1 0.61fF
+C235 io_out[1] vssa1 0.41fF
+C236 io_in[25] vssa1 0.61fF
+C237 io_oeb[1] vssa1 0.41fF
+C238 io_in_3v3[25] vssa1 0.61fF
+C239 io_in_3v3[2] vssa1 0.41fF
+C240 io_oeb[24] vssa1 0.61fF
+C241 io_in[2] vssa1 0.41fF
+C242 io_out[24] vssa1 0.61fF
+C243 io_out[2] vssa1 0.41fF
+C244 io_in[24] vssa1 0.61fF
+C245 io_oeb[2] vssa1 -0.20fF
+C246 io_in_3v3[3] vssa1 0.41fF
+C247 gpio_noesd[17] vssa1 0.61fF
+C248 io_in[3] vssa1 0.41fF
+C249 gpio_analog[17] vssa1 0.61fF
+C250 io_out[3] vssa1 0.41fF
+C251 io_oeb[3] vssa1 0.41fF
+C252 io_in_3v3[4] vssa1 0.41fF
+C253 io_in[4] vssa1 0.41fF
+C254 io_out[4] vssa1 0.41fF
+C255 io_oeb[4] vssa1 0.41fF
+C256 io_oeb[23] vssa1 0.61fF
+C257 io_out[23] vssa1 0.61fF
+C258 io_in[23] vssa1 0.61fF
+C259 io_in_3v3[23] vssa1 0.61fF
+C260 gpio_noesd[16] vssa1 0.61fF
+C261 io_in_3v3[5] vssa1 0.41fF
+C262 io_in[5] vssa1 -0.20fF
+C263 io_out[5] vssa1 0.41fF
+C264 io_oeb[5] vssa1 0.41fF
+C265 io_oeb[22] vssa1 0.61fF
+C266 io_out[22] vssa1 0.61fF
+C267 io_in[22] vssa1 0.61fF
+C268 io_in_3v3[22] vssa1 0.61fF
+C269 gpio_analog[15] vssa1 0.61fF
+C270 io_in_3v3[6] vssa1 -0.20fF
+C271 io_in[6] vssa1 0.41fF
+C272 io_out[6] vssa1 0.41fF
+C273 io_oeb[6] vssa1 0.41fF
+C274 io_oeb[21] vssa1 0.61fF
+C275 io_out[21] vssa1 0.61fF
+C276 io_in[21] vssa1 0.61fF
+C277 io_in_3v3[21] vssa1 0.61fF
+C278 gpio_noesd[14] vssa1 0.61fF
+C279 gpio_analog[14] vssa1 0.61fF
+C280 vssd2 vssa1 -5.19fF
+C281 vssd1 vssa1 1.13fF
+C282 vdda2 vssa1 -5.19fF
+C283 io_oeb[20] vssa1 0.61fF
+C284 io_out[20] vssa1 0.61fF
+C285 io_in[20] vssa1 0.61fF
+C286 io_in_3v3[20] vssa1 0.61fF
+C287 gpio_noesd[13] vssa1 0.61fF
+C288 gpio_analog[13] vssa1 0.61fF
+C289 gpio_analog[0] vssa1 0.41fF
+C290 gpio_noesd[0] vssa1 0.41fF
+C291 io_in_3v3[7] vssa1 0.41fF
+C292 io_in[7] vssa1 0.41fF
+C293 io_out[7] vssa1 0.41fF
+C294 io_oeb[7] vssa1 0.41fF
+C295 io_oeb[19] vssa1 0.61fF
+C296 io_out[19] vssa1 0.61fF
+C297 io_in[19] vssa1 0.61fF
+C298 io_in_3v3[19] vssa1 0.61fF
+C299 gpio_noesd[12] vssa1 0.61fF
+C300 gpio_analog[12] vssa1 0.61fF
+C301 gpio_analog[1] vssa1 0.41fF
+C302 io_in_3v3[8] vssa1 0.41fF
+C303 io_in[8] vssa1 0.41fF
+C304 io_out[8] vssa1 -0.20fF
+C305 io_oeb[8] vssa1 0.41fF
+C306 gpio_analog[2] vssa1 0.41fF
+C307 io_in_3v3[9] vssa1 0.41fF
+C308 io_in[9] vssa1 0.41fF
+C309 io_out[9] vssa1 0.41fF
+C310 io_oeb[9] vssa1 0.41fF
+C311 gpio_analog[3] vssa1 0.41fF
+C312 io_in_3v3[10] vssa1 0.41fF
+C313 io_in[10] vssa1 0.41fF
+C314 io_out[10] vssa1 0.41fF
+C315 io_oeb[10] vssa1 0.41fF
+C316 gpio_analog[4] vssa1 0.41fF
+C317 io_in_3v3[11] vssa1 0.41fF
+C318 io_in[11] vssa1 0.41fF
+C319 io_out[11] vssa1 0.41fF
+C320 io_oeb[11] vssa1 0.41fF
+C321 gpio_analog[5] vssa1 0.41fF
+C322 io_in_3v3[12] vssa1 0.41fF
+C323 io_in[12] vssa1 0.41fF
+C324 io_out[12] vssa1 0.41fF
+C325 io_oeb[12] vssa1 0.41fF
+C326 gpio_analog[6] vssa1 0.60fF
+C327 io_in_3v3[13] vssa1 0.60fF
+C328 io_in[13] vssa1 0.60fF
+C329 io_out[13] vssa1 0.60fF
+C330 io_oeb[13] vssa1 0.60fF
+C331 io_oeb[18] vssa1 0.61fF
+C332 io_out[18] vssa1 0.61fF
+C333 io_in_3v3[18] vssa1 0.61fF
+C334 vccd1 vssa1 0.85fF
+C335 gpio_analog[11] vssa1 0.61fF
+C336 io_oeb[17] vssa1 0.61fF
+C337 io_in[17] vssa1 0.61fF
+C338 io_in_3v3[17] vssa1 0.61fF
+C339 gpio_analog[10] vssa1 0.61fF
+C340 io_out[16] vssa1 0.61fF
+C341 io_in[16] vssa1 0.61fF
+C342 io_in_3v3[16] vssa1 0.61fF
+C343 gpio_analog[9] vssa1 0.61fF
+C344 io_oeb[15] vssa1 0.61fF
+C345 io_out[15] vssa1 0.61fF
+C346 io_in[15] vssa1 0.61fF
+C347 io_in_3v3[15] vssa1 0.61fF
+C348 gpio_analog[8] vssa1 0.61fF
+C349 io_oeb[14] vssa1 0.61fF
+C350 io_out[14] vssa1 0.61fF
+C351 io_in[14] vssa1 0.61fF
+C352 io_in_3v3[14] vssa1 0.61fF
+C353 vssa2 vssa1 1.66fF
+C354 vccd2 vssa1 0.91fF
+C355 io_clamp_high[0] vssa1 -2.60fF
+C356 io_clamp_low[0] vssa1 0.82fF
+C357 io_clamp_high[1] vssa1 0.71fF
+C358 io_clamp_low[1] vssa1 0.55fF
+C359 io_clamp_high[2] vssa1 0.66fF
+C360 io_clamp_low[2] vssa1 0.50fF
+C361 user_irq[2] vssa1 0.63fF
+C362 user_irq[1] vssa1 0.63fF
+C363 user_irq[0] vssa1 0.63fF
+C364 user_clock2 vssa1 0.63fF
+C365 la_oenb[127] vssa1 0.63fF
+C366 la_data_in[127] vssa1 0.63fF
+C367 la_oenb[126] vssa1 0.63fF
+C368 la_data_out[126] vssa1 0.63fF
+C369 la_data_in[126] vssa1 0.63fF
+C370 la_oenb[125] vssa1 0.63fF
+C371 la_data_out[125] vssa1 0.63fF
+C372 la_data_in[125] vssa1 0.63fF
+C373 la_oenb[124] vssa1 0.63fF
+C374 la_data_out[124] vssa1 0.63fF
+C375 la_data_in[124] vssa1 0.63fF
+C376 la_oenb[123] vssa1 0.63fF
+C377 la_data_out[123] vssa1 0.63fF
+C378 la_oenb[122] vssa1 0.63fF
+C379 la_data_out[122] vssa1 0.63fF
+C380 la_data_in[122] vssa1 0.63fF
+C381 la_oenb[121] vssa1 0.63fF
+C382 la_data_out[121] vssa1 0.63fF
+C383 la_data_in[121] vssa1 0.63fF
+C384 la_oenb[120] vssa1 0.63fF
+C385 la_data_out[120] vssa1 0.63fF
+C386 la_data_in[120] vssa1 0.63fF
+C387 la_oenb[119] vssa1 0.63fF
+C388 la_data_out[119] vssa1 0.63fF
+C389 la_data_in[119] vssa1 0.63fF
+C390 la_oenb[118] vssa1 0.63fF
+C391 la_data_out[118] vssa1 0.63fF
+C392 la_data_in[118] vssa1 0.63fF
+C393 la_oenb[117] vssa1 0.63fF
+C394 la_data_out[117] vssa1 0.63fF
+C395 la_data_in[117] vssa1 0.63fF
+C396 la_data_out[116] vssa1 0.63fF
+C397 la_data_in[116] vssa1 0.63fF
+C398 la_oenb[115] vssa1 0.63fF
+C399 la_data_out[115] vssa1 0.63fF
+C400 la_data_in[115] vssa1 0.63fF
+C401 la_oenb[114] vssa1 0.63fF
+C402 la_data_out[114] vssa1 0.63fF
+C403 la_data_in[114] vssa1 0.63fF
+C404 la_oenb[113] vssa1 0.63fF
+C405 la_data_out[113] vssa1 0.63fF
+C406 la_data_in[113] vssa1 0.63fF
+C407 la_oenb[112] vssa1 0.63fF
+C408 la_data_in[112] vssa1 0.63fF
+C409 la_oenb[111] vssa1 0.63fF
+C410 la_data_out[111] vssa1 0.63fF
+C411 la_data_in[111] vssa1 0.63fF
+C412 la_oenb[110] vssa1 0.63fF
+C413 la_data_out[110] vssa1 0.63fF
+C414 la_data_in[110] vssa1 0.63fF
+C415 la_oenb[109] vssa1 0.63fF
+C416 la_data_out[109] vssa1 0.63fF
+C417 la_data_in[109] vssa1 0.63fF
+C418 la_oenb[108] vssa1 0.63fF
+C419 la_data_out[108] vssa1 0.63fF
+C420 la_oenb[107] vssa1 0.63fF
+C421 la_data_out[107] vssa1 0.63fF
+C422 la_data_in[107] vssa1 0.63fF
+C423 la_oenb[106] vssa1 0.63fF
+C424 la_data_out[106] vssa1 0.63fF
+C425 la_oenb[105] vssa1 0.63fF
+C426 la_data_out[105] vssa1 0.63fF
+C427 la_data_in[105] vssa1 0.63fF
+C428 la_oenb[104] vssa1 0.63fF
+C429 la_data_out[104] vssa1 0.63fF
+C430 la_data_in[104] vssa1 0.63fF
+C431 la_oenb[103] vssa1 0.63fF
+C432 la_data_out[103] vssa1 0.63fF
+C433 la_data_in[103] vssa1 0.63fF
+C434 la_oenb[102] vssa1 0.63fF
+C435 la_data_out[102] vssa1 0.63fF
+C436 la_data_in[102] vssa1 0.63fF
+C437 la_data_out[101] vssa1 0.63fF
+C438 la_data_in[101] vssa1 0.63fF
+C439 la_oenb[100] vssa1 0.63fF
+C440 la_data_out[100] vssa1 0.63fF
+C441 la_data_in[100] vssa1 0.63fF
+C442 la_oenb[99] vssa1 0.63fF
+C443 la_data_out[99] vssa1 0.63fF
+C444 la_data_in[99] vssa1 0.63fF
+C445 la_oenb[98] vssa1 0.63fF
+C446 la_data_out[98] vssa1 0.63fF
+C447 la_data_in[98] vssa1 0.63fF
+C448 la_oenb[97] vssa1 0.63fF
+C449 la_data_in[97] vssa1 0.63fF
+C450 la_oenb[96] vssa1 0.63fF
+C451 la_data_out[96] vssa1 0.63fF
+C452 la_data_in[96] vssa1 0.63fF
+C453 la_oenb[95] vssa1 0.63fF
+C454 la_data_out[95] vssa1 0.63fF
+C455 la_data_in[95] vssa1 0.63fF
+C456 la_oenb[94] vssa1 0.63fF
+C457 la_data_out[94] vssa1 0.63fF
+C458 la_data_in[94] vssa1 0.63fF
+C459 la_oenb[93] vssa1 0.63fF
+C460 la_data_out[93] vssa1 0.63fF
+C461 la_oenb[92] vssa1 0.63fF
+C462 la_data_out[92] vssa1 0.63fF
+C463 la_data_in[92] vssa1 0.63fF
+C464 la_oenb[91] vssa1 0.63fF
+C465 la_data_out[91] vssa1 0.63fF
+C466 la_oenb[90] vssa1 0.63fF
+C467 la_data_out[90] vssa1 0.63fF
+C468 la_data_in[90] vssa1 0.63fF
+C469 la_oenb[89] vssa1 0.63fF
+C470 la_data_out[89] vssa1 0.63fF
+C471 la_data_in[89] vssa1 0.63fF
+C472 la_oenb[88] vssa1 0.63fF
+C473 la_data_out[88] vssa1 0.63fF
+C474 la_data_in[88] vssa1 0.63fF
+C475 la_oenb[87] vssa1 0.63fF
+C476 la_data_out[87] vssa1 0.63fF
+C477 la_data_in[87] vssa1 0.63fF
+C478 la_data_out[86] vssa1 0.63fF
+C479 la_data_in[86] vssa1 0.63fF
+C480 la_oenb[85] vssa1 0.63fF
+C481 la_data_out[85] vssa1 0.63fF
+C482 la_data_in[85] vssa1 0.63fF
+C483 la_oenb[84] vssa1 0.63fF
+C484 la_data_out[84] vssa1 0.63fF
+C485 la_data_in[84] vssa1 0.63fF
+C486 la_oenb[83] vssa1 0.63fF
+C487 la_data_out[83] vssa1 0.63fF
+C488 la_data_in[83] vssa1 0.63fF
+C489 la_oenb[82] vssa1 0.63fF
+C490 la_data_in[82] vssa1 0.63fF
+C491 la_oenb[81] vssa1 0.63fF
+C492 la_data_out[81] vssa1 0.63fF
+C493 la_data_in[81] vssa1 0.63fF
+C494 la_oenb[80] vssa1 0.63fF
+C495 la_data_out[80] vssa1 0.63fF
+C496 la_data_in[80] vssa1 0.63fF
+C497 la_oenb[79] vssa1 0.63fF
+C498 la_data_out[79] vssa1 0.63fF
+C499 la_data_in[79] vssa1 0.63fF
+C500 la_oenb[78] vssa1 0.63fF
+C501 la_data_out[78] vssa1 0.63fF
+C502 la_data_in[78] vssa1 0.63fF
+C503 la_oenb[77] vssa1 0.63fF
+C504 la_data_out[77] vssa1 0.63fF
+C505 la_data_in[77] vssa1 0.63fF
+C506 la_oenb[76] vssa1 0.63fF
+C507 la_data_out[76] vssa1 0.63fF
+C508 la_oenb[75] vssa1 0.63fF
+C509 la_data_out[75] vssa1 0.63fF
+C510 la_data_in[75] vssa1 0.63fF
+C511 la_oenb[74] vssa1 0.63fF
+C512 la_data_out[74] vssa1 0.63fF
+C513 la_data_in[74] vssa1 0.63fF
+C514 la_oenb[73] vssa1 0.63fF
+C515 la_data_out[73] vssa1 0.63fF
+C516 la_data_in[73] vssa1 0.63fF
+C517 la_oenb[72] vssa1 0.63fF
+C518 la_data_out[72] vssa1 0.63fF
+C519 la_data_in[72] vssa1 0.63fF
+C520 la_data_out[71] vssa1 0.63fF
+C521 la_data_in[71] vssa1 0.63fF
+C522 la_oenb[70] vssa1 0.63fF
+C523 la_data_out[70] vssa1 0.63fF
+C524 la_data_in[70] vssa1 0.63fF
+C525 la_oenb[69] vssa1 0.63fF
+C526 la_data_out[69] vssa1 0.63fF
+C527 la_data_in[69] vssa1 0.63fF
+C528 la_oenb[68] vssa1 0.63fF
+C529 la_data_out[68] vssa1 0.63fF
+C530 la_data_in[68] vssa1 0.63fF
+C531 la_oenb[67] vssa1 0.63fF
+C532 la_data_in[67] vssa1 0.63fF
+C533 la_oenb[66] vssa1 0.63fF
+C534 la_data_out[66] vssa1 0.63fF
+C535 la_data_in[66] vssa1 0.63fF
+C536 la_oenb[65] vssa1 0.63fF
+C537 la_data_out[65] vssa1 0.26fF
+C538 la_data_in[65] vssa1 0.63fF
+C539 la_oenb[64] vssa1 0.63fF
+C540 la_data_out[64] vssa1 0.63fF
+C541 la_data_in[64] vssa1 0.63fF
+C542 la_oenb[63] vssa1 0.63fF
+C543 la_data_out[63] vssa1 0.63fF
+C544 la_data_in[63] vssa1 0.63fF
+C545 la_oenb[62] vssa1 0.63fF
+C546 la_data_out[62] vssa1 0.63fF
+C547 la_data_in[62] vssa1 0.63fF
+C548 la_oenb[61] vssa1 0.63fF
+C549 la_data_out[61] vssa1 0.63fF
+C550 la_oenb[60] vssa1 0.63fF
+C551 la_data_out[60] vssa1 0.63fF
+C552 la_data_in[60] vssa1 0.63fF
+C553 la_oenb[59] vssa1 0.63fF
+C554 la_data_out[59] vssa1 0.63fF
+C555 la_data_in[59] vssa1 0.63fF
+C556 la_oenb[58] vssa1 0.63fF
+C557 la_data_out[58] vssa1 0.63fF
+C558 la_data_in[58] vssa1 0.63fF
+C559 la_oenb[57] vssa1 0.63fF
+C560 la_data_out[57] vssa1 0.63fF
+C561 la_data_in[57] vssa1 0.63fF
+C562 la_data_out[56] vssa1 0.63fF
+C563 la_data_in[56] vssa1 0.63fF
+C564 la_oenb[55] vssa1 0.63fF
+C565 la_data_out[55] vssa1 0.63fF
+C566 la_data_in[55] vssa1 0.63fF
+C567 la_oenb[54] vssa1 0.63fF
+C568 la_data_out[54] vssa1 0.63fF
+C569 la_data_in[54] vssa1 0.63fF
+C570 la_oenb[53] vssa1 0.63fF
+C571 la_data_out[53] vssa1 0.63fF
+C572 la_data_in[53] vssa1 0.63fF
+C573 la_oenb[52] vssa1 0.63fF
+C574 la_data_in[52] vssa1 0.63fF
+C575 la_oenb[51] vssa1 0.63fF
+C576 la_data_out[51] vssa1 0.63fF
+C577 la_data_in[51] vssa1 0.63fF
+C578 la_oenb[50] vssa1 0.63fF
+C579 la_data_in[50] vssa1 0.63fF
+C580 la_oenb[49] vssa1 0.63fF
+C581 la_data_out[49] vssa1 0.63fF
+C582 la_data_in[49] vssa1 0.63fF
+C583 la_oenb[48] vssa1 0.63fF
+C584 la_data_out[48] vssa1 0.63fF
+C585 la_data_in[48] vssa1 0.63fF
+C586 la_oenb[47] vssa1 0.63fF
+C587 la_data_out[47] vssa1 0.63fF
+C588 la_data_in[47] vssa1 0.63fF
+C589 la_oenb[46] vssa1 0.63fF
+C590 la_data_out[46] vssa1 0.63fF
+C591 la_oenb[45] vssa1 0.63fF
+C592 la_data_out[45] vssa1 0.63fF
+C593 la_data_in[45] vssa1 0.63fF
+C594 la_oenb[44] vssa1 0.63fF
+C595 la_data_out[44] vssa1 0.63fF
+C596 la_data_in[44] vssa1 0.63fF
+C597 la_oenb[43] vssa1 0.63fF
+C598 la_data_out[43] vssa1 0.63fF
+C599 la_data_in[43] vssa1 0.63fF
+C600 la_oenb[42] vssa1 0.63fF
+C601 la_data_out[42] vssa1 0.63fF
+C602 la_data_in[42] vssa1 0.63fF
+C603 la_data_out[41] vssa1 0.63fF
+C604 la_data_in[41] vssa1 0.63fF
+C605 la_oenb[40] vssa1 0.63fF
+C606 la_data_out[40] vssa1 0.63fF
+C607 la_data_in[40] vssa1 0.63fF
+C608 la_oenb[39] vssa1 0.63fF
+C609 la_data_out[39] vssa1 0.63fF
+C610 la_data_in[39] vssa1 0.63fF
+C611 la_oenb[38] vssa1 0.63fF
+C612 la_data_out[38] vssa1 0.63fF
+C613 la_data_in[38] vssa1 0.63fF
+C614 la_oenb[37] vssa1 0.63fF
+C615 la_data_out[37] vssa1 0.26fF
+C616 la_data_in[37] vssa1 0.63fF
+C617 la_oenb[36] vssa1 0.63fF
+C618 la_data_out[36] vssa1 0.63fF
+C619 la_data_in[36] vssa1 0.63fF
+C620 la_oenb[35] vssa1 0.63fF
+C621 la_data_in[35] vssa1 0.63fF
+C622 la_oenb[34] vssa1 0.63fF
+C623 la_data_out[34] vssa1 0.63fF
+C624 la_data_in[34] vssa1 0.63fF
+C625 la_oenb[33] vssa1 0.63fF
+C626 la_data_out[33] vssa1 0.63fF
+C627 la_data_in[33] vssa1 0.63fF
+C628 la_oenb[32] vssa1 0.63fF
+C629 la_data_out[32] vssa1 0.63fF
+C630 la_data_in[32] vssa1 0.63fF
+C631 la_oenb[31] vssa1 0.63fF
+C632 la_data_out[31] vssa1 0.63fF
+C633 la_oenb[30] vssa1 0.63fF
+C634 la_data_out[30] vssa1 0.63fF
+C635 la_data_in[30] vssa1 0.63fF
+C636 la_oenb[29] vssa1 0.63fF
+C637 la_data_out[29] vssa1 0.63fF
+C638 la_data_in[29] vssa1 0.63fF
+C639 la_oenb[28] vssa1 0.63fF
+C640 la_data_out[28] vssa1 0.63fF
+C641 la_data_in[28] vssa1 0.63fF
+C642 la_oenb[27] vssa1 0.63fF
+C643 la_data_out[27] vssa1 0.63fF
+C644 la_data_in[27] vssa1 0.63fF
+C645 la_data_out[26] vssa1 0.63fF
+C646 la_data_in[26] vssa1 0.63fF
+C647 la_oenb[25] vssa1 0.63fF
+C648 la_data_out[25] vssa1 0.63fF
+C649 la_data_in[25] vssa1 0.63fF
+C650 la_oenb[24] vssa1 0.63fF
+C651 la_data_out[24] vssa1 0.63fF
+C652 la_data_in[24] vssa1 0.63fF
+C653 la_oenb[23] vssa1 0.63fF
+C654 la_data_out[23] vssa1 0.63fF
+C655 la_data_in[23] vssa1 0.63fF
+C656 la_oenb[22] vssa1 0.63fF
+C657 la_data_out[22] vssa1 0.63fF
+C658 la_data_in[22] vssa1 0.63fF
+C659 la_oenb[21] vssa1 0.63fF
+C660 la_data_out[21] vssa1 0.63fF
+C661 la_data_in[21] vssa1 0.63fF
+C662 la_oenb[20] vssa1 0.63fF
+C663 la_data_in[20] vssa1 0.63fF
+C664 la_oenb[19] vssa1 0.63fF
+C665 la_data_out[19] vssa1 0.63fF
+C666 la_data_in[19] vssa1 0.63fF
+C667 la_oenb[18] vssa1 0.63fF
+C668 la_data_out[18] vssa1 0.63fF
+C669 la_data_in[18] vssa1 0.63fF
+C670 la_oenb[17] vssa1 0.63fF
+C671 la_data_out[17] vssa1 0.63fF
+C672 la_data_in[17] vssa1 0.63fF
+C673 la_oenb[16] vssa1 0.63fF
+C674 la_data_out[16] vssa1 0.63fF
+C675 la_oenb[15] vssa1 0.63fF
+C676 la_data_out[15] vssa1 0.63fF
+C677 la_data_in[15] vssa1 0.63fF
+C678 la_oenb[14] vssa1 0.63fF
+C679 la_data_out[14] vssa1 0.63fF
+C680 la_data_in[14] vssa1 0.63fF
+C681 la_oenb[13] vssa1 0.63fF
+C682 la_data_out[13] vssa1 0.63fF
+C683 la_data_in[13] vssa1 0.63fF
+C684 la_oenb[12] vssa1 0.63fF
+C685 la_data_out[12] vssa1 0.63fF
+C686 la_data_in[12] vssa1 0.63fF
+C687 la_data_out[11] vssa1 0.63fF
+C688 la_data_in[11] vssa1 0.63fF
+C689 la_oenb[10] vssa1 0.63fF
+C690 la_data_out[10] vssa1 0.63fF
+C691 la_data_in[10] vssa1 0.63fF
+C692 la_data_out[9] vssa1 0.63fF
+C693 la_data_in[9] vssa1 0.63fF
+C694 la_oenb[8] vssa1 0.63fF
+C695 la_data_out[8] vssa1 0.63fF
+C696 la_data_in[8] vssa1 0.63fF
+C697 la_oenb[7] vssa1 0.63fF
+C698 la_data_out[7] vssa1 0.63fF
+C699 la_data_in[7] vssa1 0.63fF
+C700 la_oenb[6] vssa1 0.63fF
+C701 la_data_out[6] vssa1 0.63fF
+C702 la_data_in[6] vssa1 0.63fF
+C703 la_oenb[5] vssa1 0.63fF
+C704 la_data_in[5] vssa1 0.63fF
+C705 la_oenb[4] vssa1 0.63fF
+C706 la_data_out[4] vssa1 0.63fF
+C707 la_data_in[4] vssa1 0.63fF
+C708 la_oenb[3] vssa1 0.63fF
+C709 la_data_out[3] vssa1 0.63fF
+C710 la_data_in[3] vssa1 0.63fF
+C711 la_oenb[2] vssa1 0.63fF
+C712 la_data_out[2] vssa1 0.63fF
+C713 la_data_in[2] vssa1 0.63fF
+C714 la_oenb[1] vssa1 0.63fF
+C715 la_data_out[1] vssa1 0.63fF
+C716 la_oenb[0] vssa1 0.63fF
+C717 la_data_out[0] vssa1 0.63fF
+C718 la_data_in[0] vssa1 0.63fF
+C719 wbs_dat_o[31] vssa1 0.63fF
+C720 wbs_dat_i[31] vssa1 0.63fF
+C721 wbs_adr_i[31] vssa1 0.63fF
+C722 wbs_dat_o[30] vssa1 0.63fF
+C723 wbs_dat_i[30] vssa1 0.63fF
+C724 wbs_adr_i[30] vssa1 0.63fF
+C725 wbs_dat_o[29] vssa1 0.63fF
+C726 wbs_dat_i[29] vssa1 0.63fF
+C727 wbs_adr_i[29] vssa1 0.63fF
+C728 wbs_dat_i[28] vssa1 0.63fF
+C729 wbs_adr_i[28] vssa1 0.63fF
+C730 wbs_dat_o[27] vssa1 0.63fF
+C731 wbs_dat_i[27] vssa1 0.63fF
+C732 wbs_adr_i[27] vssa1 0.63fF
+C733 wbs_dat_i[26] vssa1 0.63fF
+C734 wbs_adr_i[26] vssa1 0.63fF
+C735 wbs_dat_o[25] vssa1 0.63fF
+C736 wbs_dat_i[25] vssa1 0.63fF
+C737 wbs_adr_i[25] vssa1 0.63fF
+C738 wbs_dat_o[24] vssa1 0.63fF
+C739 wbs_dat_i[24] vssa1 0.63fF
+C740 wbs_adr_i[24] vssa1 0.63fF
+C741 wbs_dat_o[23] vssa1 0.63fF
+C742 wbs_dat_i[23] vssa1 0.63fF
+C743 wbs_adr_i[23] vssa1 0.63fF
+C744 wbs_dat_o[22] vssa1 0.63fF
+C745 wbs_adr_i[22] vssa1 0.63fF
+C746 wbs_dat_o[21] vssa1 0.63fF
+C747 wbs_dat_i[21] vssa1 0.63fF
+C748 wbs_adr_i[21] vssa1 0.63fF
+C749 wbs_dat_o[20] vssa1 0.63fF
+C750 wbs_dat_i[20] vssa1 0.63fF
+C751 wbs_adr_i[20] vssa1 0.63fF
+C752 wbs_dat_o[19] vssa1 0.63fF
+C753 wbs_dat_i[19] vssa1 0.63fF
+C754 wbs_adr_i[19] vssa1 0.63fF
+C755 wbs_dat_o[18] vssa1 0.63fF
+C756 wbs_dat_i[18] vssa1 0.63fF
+C757 wbs_dat_o[17] vssa1 0.63fF
+C758 wbs_dat_i[17] vssa1 0.63fF
+C759 wbs_adr_i[17] vssa1 0.63fF
+C760 wbs_dat_o[16] vssa1 0.63fF
+C761 wbs_dat_i[16] vssa1 0.63fF
+C762 wbs_adr_i[16] vssa1 0.63fF
+C763 wbs_dat_o[15] vssa1 0.63fF
+C764 wbs_dat_i[15] vssa1 0.63fF
+C765 wbs_adr_i[15] vssa1 0.63fF
+C766 wbs_dat_o[14] vssa1 0.63fF
+C767 wbs_dat_i[14] vssa1 0.63fF
+C768 wbs_adr_i[14] vssa1 0.63fF
+C769 wbs_dat_o[13] vssa1 0.63fF
+C770 wbs_dat_i[13] vssa1 0.63fF
+C771 wbs_adr_i[13] vssa1 0.63fF
+C772 wbs_dat_o[12] vssa1 0.63fF
+C773 wbs_dat_i[12] vssa1 0.63fF
+C774 wbs_adr_i[12] vssa1 0.63fF
+C775 wbs_dat_i[11] vssa1 0.63fF
+C776 wbs_adr_i[11] vssa1 0.63fF
+C777 wbs_dat_o[10] vssa1 0.63fF
+C778 wbs_dat_i[10] vssa1 0.63fF
+C779 wbs_adr_i[10] vssa1 0.63fF
+C780 wbs_dat_o[9] vssa1 0.63fF
+C781 wbs_dat_i[9] vssa1 0.63fF
+C782 wbs_adr_i[9] vssa1 0.63fF
+C783 wbs_dat_o[8] vssa1 0.63fF
+C784 wbs_dat_i[8] vssa1 0.63fF
+C785 wbs_adr_i[8] vssa1 0.63fF
+C786 wbs_dat_o[7] vssa1 0.63fF
+C787 wbs_adr_i[7] vssa1 0.63fF
+C788 wbs_dat_o[6] vssa1 0.63fF
+C789 wbs_dat_i[6] vssa1 0.63fF
+C790 wbs_adr_i[6] vssa1 0.63fF
+C791 wbs_dat_o[5] vssa1 0.63fF
+C792 wbs_dat_i[5] vssa1 0.63fF
+C793 wbs_adr_i[5] vssa1 0.63fF
+C794 wbs_dat_o[4] vssa1 0.63fF
+C795 wbs_dat_i[4] vssa1 0.63fF
+C796 wbs_adr_i[4] vssa1 0.63fF
+C797 wbs_sel_i[3] vssa1 0.63fF
+C798 wbs_dat_o[3] vssa1 0.63fF
+C799 wbs_adr_i[3] vssa1 0.63fF
+C800 wbs_sel_i[2] vssa1 0.63fF
+C801 wbs_dat_o[2] vssa1 0.63fF
+C802 wbs_dat_i[2] vssa1 0.63fF
+C803 wbs_adr_i[2] vssa1 0.63fF
+C804 wbs_dat_o[1] vssa1 0.63fF
+C805 wbs_dat_i[1] vssa1 0.63fF
+C806 wbs_adr_i[1] vssa1 0.63fF
+C807 wbs_sel_i[0] vssa1 0.63fF
+C808 wbs_dat_o[0] vssa1 0.63fF
+C809 wbs_dat_i[0] vssa1 0.63fF
+C810 wbs_adr_i[0] vssa1 0.63fF
+C811 wbs_we_i vssa1 0.63fF
+C812 wbs_stb_i vssa1 0.63fF
+C813 wbs_cyc_i vssa1 0.63fF
+C814 wbs_ack_o vssa1 0.63fF
+C815 wb_rst_i vssa1 0.63fF
+C816 top_pll_v2_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C817 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C818 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C819 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C820 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C821 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C822 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C823 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C824 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C825 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C826 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C827 top_pll_v2_0/QB vssa1 4.35fF
+C828 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C829 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C830 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C831 top_pll_v2_0/out_div_by_5 vssa1 -0.40fF
+C832 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C833 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C834 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C835 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C836 top_pll_v2_0/pfd_reset vssa1 2.17fF
+C837 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C838 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C839 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C840 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C841 top_pll_v2_0/QA vssa1 4.22fF
+C842 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C843 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C844 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C845 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C846 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C847 top_pll_v2_0/nUp vssa1 5.39fF
+C848 top_pll_v2_0/Up vssa1 1.85fF
+C849 top_pll_v2_0/Down vssa1 6.19fF
+C850 top_pll_v2_0/nDown vssa1 -3.53fF
+C851 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C852 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C853 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C854 top_pll_v2_0/div_5_Q1_shift vssa1 -0.14fF
+C855 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C856 top_pll_v2_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C857 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C858 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C859 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C860 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C861 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C862 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C863 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C864 top_pll_v2_0/div_5_Q1 vssa1 4.25fF
+C865 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C866 top_pll_v2_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C867 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C868 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C869 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C870 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C871 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C872 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C873 top_pll_v2_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C874 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C875 top_pll_v2_0/div_5_Q0 vssa1 0.01fF
+C876 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C877 top_pll_v2_0/div_5_nQ0 vssa1 0.59fF
+C878 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C879 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C880 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C881 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C882 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C883 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C884 top_pll_v2_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C885 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C886 top_pll_v2_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C887 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C888 top_pll_v2_0/n_out_by_2 vssa1 -2.75fF
+C889 top_pll_v2_0/div_5_nQ2 vssa1 1.24fF
+C890 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C891 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C892 top_pll_v2_0/out_by_2 vssa1 -5.01fF
+C893 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C894 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C895 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C896 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C897 top_pll_v2_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C898 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C899 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C900 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C901 top_pll_v2_0/out_first_buffer vssa1 2.88fF
+C902 top_pll_v2_0/out_to_buffer vssa1 1.54fF
+C903 top_pll_v2_0/out_to_div vssa1 4.23fF
+C904 top_pll_v2_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C905 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C906 top_pll_v2_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C907 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C908 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C909 top_pll_v2_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C910 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C911 top_pll_v2_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C912 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C913 top_pll_v2_0/vco_out vssa1 1.01fF
+C914 top_pll_v2_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C915 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C916 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C917 io_analog[8] vssa1 13.78fF
+C918 top_pll_v2_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C919 top_pll_v2_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C920 top_pll_v2_0/lf_vc vssa1 -59.89fF
+C921 top_pll_v2_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
+C922 top_pll_v2_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
+C923 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C924 top_pll_v2_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C925 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C926 top_pll_v2_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C927 top_pll_v2_0/out_buffer_div_2 vssa1 1.60fF
+C928 top_pll_v2_0/n_out_buffer_div_2 vssa1 1.63fF
+C929 top_pll_v2_0/out_div_2 vssa1 -1.30fF
+C930 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C931 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C932 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C933 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C934 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C935 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C936 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C937 top_pll_v2_0/n_out_div_2 vssa1 1.95fF
+C938 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C939 top_pll_v2_0/nswitch vssa1 3.73fF
+C940 top_pll_v2_0/biasp vssa1 5.44fF
+C941 bias_0/iref_1 vssa1 -91.53fF
+C942 top_pll_v2_0/vco_vctrl vssa1 -20.08fF
+C943 top_pll_v2_0/pswitch vssa1 3.57fF
+C944 bias_0/iref_4 vssa1 1.17fF
+C945 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vssa1 2.60fF
+C946 bias_0/iref_3 vssa1 0.64fF
+C947 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vssa1 2.60fF
+C948 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vssa1 2.60fF
+C949 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vssa1 2.60fF
+C950 io_analog[5] vssa1 33.29fF
+C951 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vssa1 2.60fF
+C952 bias_0/m1_20168_984# vssa1 56.92fF
+C953 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vssa1 2.60fF
+C954 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vssa1 2.60fF
+C955 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vssa1 2.60fF
+C956 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vssa1 2.60fF
+C957 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vssa1 2.60fF
+C958 top_pll_v1_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C959 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C960 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C961 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C962 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C963 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C964 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C965 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C966 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C967 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C968 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C969 top_pll_v1_0/QB vssa1 4.35fF
+C970 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C971 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C972 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C973 top_pll_v1_0/out_div_by_5 vssa1 -0.40fF
+C974 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C975 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C976 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C977 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C978 top_pll_v1_0/pfd_reset vssa1 2.17fF
+C979 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C980 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C981 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C982 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C983 top_pll_v1_0/QA vssa1 4.22fF
+C984 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C985 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C986 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C987 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C988 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C989 top_pll_v1_0/nUp vssa1 5.39fF
+C990 top_pll_v1_0/Up vssa1 1.85fF
+C991 top_pll_v1_0/Down vssa1 6.19fF
+C992 top_pll_v1_0/nDown vssa1 -3.53fF
+C993 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C994 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C995 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C996 top_pll_v1_0/div_5_Q1_shift vssa1 -0.14fF
+C997 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C998 top_pll_v1_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C999 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1000 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1001 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1002 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1003 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1004 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1005 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1006 top_pll_v1_0/div_5_Q1 vssa1 4.25fF
+C1007 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1008 top_pll_v1_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1009 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1010 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1011 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1012 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1013 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1014 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1015 top_pll_v1_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1016 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1017 top_pll_v1_0/div_5_Q0 vssa1 0.01fF
+C1018 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1019 top_pll_v1_0/div_5_nQ0 vssa1 0.59fF
+C1020 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1021 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1022 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1023 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1024 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1025 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1026 top_pll_v1_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C1027 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1028 top_pll_v1_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1029 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1030 top_pll_v1_0/n_out_by_2 vssa1 -2.75fF
+C1031 top_pll_v1_0/div_5_nQ2 vssa1 1.24fF
+C1032 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1033 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1034 top_pll_v1_0/out_by_2 vssa1 -5.01fF
+C1035 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1036 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1037 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1038 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1039 top_pll_v1_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1040 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1041 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1042 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1043 top_pll_v1_0/out_first_buffer vssa1 2.88fF
+C1044 top_pll_v1_0/out_to_buffer vssa1 1.54fF
+C1045 top_pll_v1_0/out_to_div vssa1 4.23fF
+C1046 top_pll_v1_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1047 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1048 top_pll_v1_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1049 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1050 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1051 top_pll_v1_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1052 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1053 top_pll_v1_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1054 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1055 top_pll_v1_0/vco_out vssa1 1.01fF
+C1056 gpio_noesd[7] vssa1 271.92fF
+C1057 top_pll_v1_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1058 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1059 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1060 io_analog[9] vssa1 7.89fF
+C1061 top_pll_v1_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C1062 top_pll_v1_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1063 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1064 top_pll_v1_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1065 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1066 top_pll_v1_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1067 top_pll_v1_0/out_buffer_div_2 vssa1 1.60fF
+C1068 top_pll_v1_0/n_out_buffer_div_2 vssa1 1.63fF
+C1069 top_pll_v1_0/out_div_2 vssa1 -1.30fF
+C1070 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1071 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1072 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1073 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1074 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1075 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1076 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1077 top_pll_v1_0/n_out_div_2 vssa1 1.95fF
+C1078 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1079 top_pll_v1_0/nswitch vssa1 3.73fF
+C1080 top_pll_v1_0/biasp vssa1 5.44fF
+C1081 bias_0/iref_2 vssa1 -178.91fF
+C1082 top_pll_v1_0/vco_vctrl vssa1 -18.17fF
+C1083 top_pll_v1_0/pswitch vssa1 3.57fF
+C1084 top_pll_v1_0/lf_vc vssa1 -59.89fF
+C1085 top_pll_v1_0/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C1086 top_pll_v3_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C1087 top_pll_v3_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C1088 top_pll_v3_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C1089 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1090 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C1091 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1092 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C1093 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1094 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1095 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C1096 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1097 top_pll_v3_0/QB vssa1 3.01fF
+C1098 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1099 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1100 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1101 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1102 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C1103 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1104 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C1105 top_pll_v3_0/pfd_reset vssa1 1.87fF
+C1106 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1107 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1108 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C1109 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1110 top_pll_v3_0/QA vssa1 3.41fF
+C1111 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1112 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1113 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1114 io_analog[10] vssa1 502.98fF
+C1115 top_pll_v3_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C1116 top_pll_v3_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C1117 top_pll_v3_0/Up vssa1 -4.79fF
+C1118 top_pll_v3_0/Down vssa1 -0.05fF
+C1119 top_pll_v3_0/nDown vssa1 1.54fF
+C1120 top_pll_v3_0/out_first_buffer vssa1 2.14fF
+C1121 top_pll_v3_0/out_to_buffer vssa1 1.89fF
+C1122 top_pll_v3_0/out_to_div vssa1 8.23fF
+C1123 top_pll_v3_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1124 top_pll_v3_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1125 top_pll_v3_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1126 top_pll_v3_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1127 top_pll_v3_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1128 top_pll_v3_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1129 top_pll_v3_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1130 top_pll_v3_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1131 top_pll_v3_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1132 top_pll_v3_0/vco_out vssa1 1.65fF
+C1133 top_pll_v3_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1134 top_pll_v3_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1135 top_pll_v3_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1136 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vssa1 0.37fF
+C1137 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C1138 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vssa1 0.49fF
+C1139 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C1140 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1141 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1142 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1143 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1144 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1145 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1146 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1147 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/D vssa1 1.90fF
+C1148 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1149 top_pll_v3_0/freq_div_0/prescaler_23_0/Q2_d vssa1 -0.69fF
+C1150 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1151 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1152 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1153 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1154 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1155 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1156 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1157 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1158 top_pll_v3_0/freq_div_0/prescaler_23_0/Q2 vssa1 0.55fF
+C1159 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1160 top_pll_v3_0/freq_div_0/prescaler_23_0/Q1 vssa1 0.07fF
+C1161 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1162 top_pll_v3_0/n_clk_0 vssa1 -7.01fF
+C1163 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/nQ vssa1 0.48fF
+C1164 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1165 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1166 top_pll_v3_0/clk_0 vssa1 -0.37fF
+C1167 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1168 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1169 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1170 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1171 top_pll_v3_0/freq_div_0/prescaler_23_0/nCLK_23 vssa1 -1.02fF
+C1172 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1173 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vssa1 -1.01fF
+C1174 gpio_noesd[11] vssa1 104.40fF
+C1175 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vssa1 0.36fF
+C1176 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vssa1 0.65fF
+C1177 top_pll_v3_0/n_out_by_2 vssa1 4.38fF
+C1178 top_pll_v3_0/s_0_n vssa1 -4.09fF
+C1179 top_pll_v3_0/out_by_2 vssa1 4.28fF
+C1180 gpio_noesd[10] vssa1 110.89fF
+C1181 top_pll_v3_0/freq_div_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C1182 top_pll_v3_0/freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C1183 top_pll_v3_0/freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C1184 top_pll_v3_0/freq_div_0/div_by_5_0/Q1_shift vssa1 -0.36fF
+C1185 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1186 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1187 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1188 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1189 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1190 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1191 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1192 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1193 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1194 top_pll_v3_0/freq_div_0/div_by_5_0/Q1 vssa1 4.35fF
+C1195 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1196 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1197 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1198 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1199 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1200 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1201 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1202 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1203 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1204 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1205 top_pll_v3_0/freq_div_0/div_by_5_0/Q0 vssa1 0.29fF
+C1206 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1207 top_pll_v3_0/freq_div_0/div_by_5_0/nQ0 vssa1 0.99fF
+C1208 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1209 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1210 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1211 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1212 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1213 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1214 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C1215 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1216 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1217 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1218 top_pll_v3_0/n_clk_1 vssa1 -0.56fF
+C1219 top_pll_v3_0/freq_div_0/div_by_5_0/nQ2 vssa1 1.38fF
+C1220 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1221 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1222 top_pll_v3_0/clk_1 vssa1 -2.08fF
+C1223 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1224 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1225 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1226 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1227 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1228 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1229 top_pll_v3_0/freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1230 top_pll_v3_0/freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1231 top_pll_v3_0/s_1_n vssa1 -2.04fF
+C1232 top_pll_v3_0/out_div vssa1 3.58fF
+C1233 top_pll_v3_0/clk_d vssa1 1.27fF
+C1234 gpio_noesd[9] vssa1 196.62fF
+C1235 top_pll_v3_0/freq_div_0/inverter_min_x4_0/in vssa1 2.71fF
+C1236 top_pll_v3_0/clk_5 vssa1 -0.22fF
+C1237 top_pll_v3_0/clk_out_mux21 vssa1 3.89fF
+C1238 top_pll_v3_0/clk_pre vssa1 1.69fF
+C1239 top_pll_v3_0/freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1240 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1241 top_pll_v3_0/freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1242 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1243 top_pll_v3_0/clk_2_f vssa1 3.30fF
+C1244 top_pll_v3_0/freq_div_0/div_by_2_0/o1 vssa1 2.08fF
+C1245 top_pll_v3_0/freq_div_0/div_by_2_0/nCLK_2 vssa1 1.04fF
+C1246 top_pll_v3_0/freq_div_0/div_by_2_0/o2 vssa1 2.08fF
+C1247 top_pll_v3_0/freq_div_0/div_by_2_0/out_div vssa1 -0.82fF
+C1248 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1249 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1250 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1251 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1252 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1253 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1254 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1255 top_pll_v3_0/freq_div_0/div_by_2_0/nout_div vssa1 2.62fF
+C1256 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1257 io_analog[7] vssa1 24.25fF
+C1258 top_pll_v3_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C1259 top_pll_v3_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1260 top_pll_v3_0/lf_vc vssa1 -60.88fF
+C1261 top_pll_v3_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
+C1262 gpio_noesd[8] vssa1 303.23fF
+C1263 top_pll_v3_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
+C1264 top_pll_v3_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1265 top_pll_v3_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1266 top_pll_v3_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1267 top_pll_v3_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1268 top_pll_v3_0/out_buffer_div_2 vssa1 1.57fF
+C1269 top_pll_v3_0/n_out_buffer_div_2 vssa1 1.57fF
+C1270 top_pll_v3_0/out_div_2 vssa1 -0.70fF
+C1271 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1272 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1273 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1274 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1275 top_pll_v3_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1276 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1277 top_pll_v3_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1278 top_pll_v3_0/n_out_div_2 vssa1 2.11fF
+C1279 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1280 top_pll_v3_0/nswitch vssa1 4.61fF
+C1281 top_pll_v3_0/biasp vssa1 5.45fF
+C1282 bias_0/iref_0 vssa1 -81.72fF
+C1283 top_pll_v3_0/vco_vctrl vssa1 -30.71fF
+C1284 top_pll_v3_0/pswitch vssa1 2.72fF
+C1285 bias_0/iref_6 vssa1 -645.65fF
+C1286 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in vssa1 -32.98fF
+C1287 io_analog[1] vssa1 73.96fF
+C1288 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# vssa1 1.29fF
+C1289 bias_0/iref_5 vssa1 -623.45fF
+C1290 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in vssa1 -32.98fF
+C1291 io_analog[0] vssa1 -155.24fF
+C1292 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# vssa1 1.29fF
+C1293 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# vssa1 -35.44fF
+C1294 bias_0/iref_8 vssa1 -189.06fF
+C1295 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# vssa1 -35.44fF
+C1296 bias_0/iref_7 vssa1 -205.18fF
+C1297 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# vssa1 -1.87fF
+C1298 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# vssa1 0.47fF
+C1299 gpio_noesd[5] vssa1 122.09fF
+C1300 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# vssa1 -1.10fF
+C1301 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl vssa1 -2.03fF
+C1302 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# vssa1 -2.23fF
+C1303 gpio_noesd[6] vssa1 325.91fF
+C1304 gpio_noesd[4] vssa1 116.78fF
+C1305 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# vssa1 -1.03fF
+C1306 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# vssa1 0.51fF
+C1307 bias_0/iref_9 vssa1 -181.57fF
+C1308 res_amp_top_0/res_amp_lin_prog_0/outn vssa1 1.55fF
+C1309 io_analog[3] vssa1 -119.52fF
+C1310 res_amp_top_0/res_amp_lin_prog_0/outp vssa1 -4.89fF
+C1311 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp vssa1 -4.89fF
+C1312 io_analog[2] vssa1 -131.04fF
+C1313 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# vssa1 -0.95fF
+C1314 res_amp_top_0/res_amp_lin_prog_0/outn_cap vssa1 -0.01fF
+C1315 res_amp_top_0/res_amp_lin_prog_0/inverter_min_x4_0/out vssa1 4.60fF
+C1316 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk vssa1 4.27fF
+C1317 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in vssa1 1.07fF
+C1318 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA vssa1 -0.04fF
+C1319 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in vssa1 1.03fF
+C1320 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in vssa1 1.03fF
+C1321 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in vssa1 1.07fF
+C1322 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in vssa1 1.03fF
+C1323 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in vssa1 1.03fF
+C1324 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in vssa1 1.07fF
+C1325 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in vssa1 1.03fF
+C1326 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in vssa1 1.07fF
+C1327 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in vssa1 1.03fF
+C1328 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in vssa1 1.03fF
+C1329 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in vssa1 1.03fF
+C1330 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in vssa1 1.07fF
+C1331 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB vssa1 -7.88fF
+C1332 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in vssa1 1.03fF
+C1333 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in vssa1 1.03fF
+C1334 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in vssa1 1.07fF
+C1335 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in vssa1 1.03fF
+C1336 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1337 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in vssa1 1.03fF
+C1338 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 vssa1 1.54fF
+C1339 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b vssa1 2.03fF
+C1340 gpio_noesd[3] vssa1 213.06fF
+C1341 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out vssa1 -1.67fF
+C1342 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b vssa1 2.03fF
+C1343 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA vssa1 -2.58fF
+C1344 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out vssa1 -2.25fF
+C1345 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b vssa1 2.03fF
+C1346 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out vssa1 -2.69fF
+C1347 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB vssa1 -4.96fF
+C1348 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b vssa1 2.03fF
+C1349 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out vssa1 -4.71fF
+C1350 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b vssa1 2.03fF
+C1351 gpio_noesd[2] vssa1 216.13fF
+C1352 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA vssa1 0.63fF
+C1353 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out vssa1 -2.49fF
+C1354 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB vssa1 -3.92fF
+C1355 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b vssa1 2.03fF
+C1356 gpio_noesd[1] vssa1 230.09fF
+C1357 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out vssa1 -0.27fF
+C1358 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB vssa1 -0.97fF
+C1359 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b vssa1 2.03fF
+C1360 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in vssa1 1.07fF
+C1361 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in vssa1 1.03fF
+C1362 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in vssa1 1.03fF
+C1363 res_amp_top_0/res_amp_lin_prog_0/outp_cap vssa1 -7.66fF
+C1364 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/m1_21_n341# vssa1 0.72fF
+C1365 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1366 res_amp_top_0/res_amp_lin_prog_0/clk vssa1 -8.26fF
+C1367 res_amp_top_0/res_amp_sync_v2_0/inverter_min_x4_4/out vssa1 5.85fF
+C1368 res_amp_top_0/res_amp_sync_v2_0/rst vssa1 -7.88fF
+C1369 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/out vssa1 1.70fF
+C1370 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/Q vssa1 -2.08fF
+C1371 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1372 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/nQ vssa1 0.48fF
+C1373 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D vssa1 -1.73fF
+C1374 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1375 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD vssa1 0.57fF
+C1376 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1377 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D vssa1 0.96fF
+C1378 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1379 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/D vssa1 1.83fF
+C1380 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD vssa1 1.14fF
+C1381 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/out vssa1 1.20fF
+C1382 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/Q vssa1 -2.94fF
+C1383 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1384 io_analog[4] vssa1 -253.69fF
+C1385 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1386 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1387 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1388 io_analog[6] vssa1 -26.69fF
+C1389 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1390 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1391 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1392 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1393 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/D vssa1 0.79fF
+C1394 vdda1 vssa1 7499.69fF
+C1395 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1396 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/Q vssa1 -1.08fF
+C1397 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1398 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1399 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1400 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1401 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1402 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1403 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1404 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1405 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/D vssa1 -0.38fF
+C1406 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1407 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1408 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/nQ vssa1 0.48fF
+C1409 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1410 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1411 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1412 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1413 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1414 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1415 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/D vssa1 -1.04fF
+C1416 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1417 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/Q vssa1 -4.73fF
+C1418 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1419 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/nQ vssa1 0.48fF
+C1420 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1421 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1422 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1423 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1424 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1425 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1426 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
.ends
diff --git a/mag/extractions/user_analog_project_wrapper_pex_rc.spice b/mag/extractions/user_analog_project_wrapper_pex_rc.spice
index 73f3f79..4372aa1 100644
--- a/mag/extractions/user_analog_project_wrapper_pex_rc.spice
+++ b/mag/extractions/user_analog_project_wrapper_pex_rc.spice
@@ -5,18 +5,18 @@
X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n81_n125# a_111_n125# 0.13fF
-C1 a_81_n156# a_n15_n156# 0.02fF
-C2 w_n311_n344# a_15_n125# 0.09fF
-C3 a_15_n125# a_n173_n125# 0.13fF
-C4 a_n81_n125# a_15_n125# 0.36fF
-C5 w_n311_n344# a_n173_n125# 0.14fF
-C6 a_111_n125# a_15_n125# 0.36fF
-C7 a_n81_n125# w_n311_n344# 0.09fF
-C8 a_111_n125# w_n311_n344# 0.14fF
-C9 a_n15_n156# a_n111_n156# 0.02fF
-C10 a_n81_n125# a_n173_n125# 0.36fF
-C11 a_111_n125# a_n173_n125# 0.08fF
+C0 a_81_n156# a_n15_n156# 0.02fF
+C1 a_111_n125# w_n311_n344# 0.14fF
+C2 a_15_n125# w_n311_n344# 0.09fF
+C3 w_n311_n344# a_n81_n125# 0.09fF
+C4 a_111_n125# a_n173_n125# 0.08fF
+C5 a_15_n125# a_n173_n125# 0.13fF
+C6 a_n173_n125# a_n81_n125# 0.36fF
+C7 a_n15_n156# a_n111_n156# 0.02fF
+C8 a_n173_n125# w_n311_n344# 0.14fF
+C9 a_15_n125# a_111_n125# 0.36fF
+C10 a_111_n125# a_n81_n125# 0.13fF
+C11 a_15_n125# a_n81_n125# 0.36fF
C12 a_111_n125# VSUBS 0.03fF
C13 a_15_n125# VSUBS 0.03fF
C14 a_n81_n125# VSUBS 0.03fF
@@ -32,14 +32,14 @@
X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n173_n125# a_111_n125# 0.08fF
-C1 a_n111_n151# a_n15_n151# 0.02fF
-C2 a_n81_n125# a_n173_n125# 0.36fF
-C3 a_111_n125# a_15_n125# 0.36fF
-C4 a_n15_n151# a_81_n151# 0.02fF
+C0 a_n15_n151# a_n111_n151# 0.02fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 a_81_n151# a_n15_n151# 0.02fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_111_n125# a_n173_n125# 0.08fF
C5 a_n81_n125# a_15_n125# 0.36fF
-C6 a_n81_n125# a_111_n125# 0.13fF
-C7 a_n173_n125# a_15_n125# 0.13fF
+C6 a_15_n125# a_n173_n125# 0.13fF
+C7 a_n81_n125# a_n173_n125# 0.36fF
C8 a_111_n125# w_n311_n335# 0.17fF
C9 a_15_n125# w_n311_n335# 0.12fF
C10 a_n81_n125# w_n311_n335# 0.12fF
@@ -49,14 +49,14 @@
C14 a_n111_n151# w_n311_n335# 0.05fF
.ends
-.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+.subckt trans_gate m1_187_n605# vss m1_45_n513# vdd
Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
+ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
+ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
-C0 m1_45_n513# vdd 0.69fF
-C1 m1_187_n605# vdd 0.55fF
-C2 m1_187_n605# m1_45_n513# 0.36fF
+C0 m1_45_n513# m1_187_n605# 0.36fF
+C1 m1_45_n513# vdd 0.69fF
+C2 vdd m1_187_n605# 0.55fF
C3 m1_187_n605# vss 0.93fF
C4 m1_45_n513# vss 1.31fF
C5 vdd vss 3.36fF
@@ -67,16 +67,16 @@
X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n81_n125# a_15_n125# 0.36fF
-C1 a_n173_n125# a_n81_n125# 0.36fF
-C2 a_n81_n125# w_n311_n344# 0.09fF
-C3 a_15_n125# a_111_n125# 0.36fF
-C4 a_n173_n125# a_111_n125# 0.08fF
-C5 w_n311_n344# a_111_n125# 0.14fF
-C6 a_n81_n125# a_111_n125# 0.13fF
-C7 a_n173_n125# a_15_n125# 0.13fF
-C8 w_n311_n344# a_15_n125# 0.09fF
-C9 a_n173_n125# w_n311_n344# 0.14fF
+C0 w_n311_n344# a_111_n125# 0.14fF
+C1 w_n311_n344# a_n81_n125# 0.09fF
+C2 a_111_n125# a_n173_n125# 0.08fF
+C3 w_n311_n344# a_15_n125# 0.09fF
+C4 a_n81_n125# a_n173_n125# 0.36fF
+C5 a_15_n125# a_n173_n125# 0.13fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_111_n125# a_15_n125# 0.36fF
+C8 w_n311_n344# a_n173_n125# 0.14fF
+C9 a_15_n125# a_n81_n125# 0.36fF
C10 a_111_n125# VSUBS 0.03fF
C11 a_15_n125# VSUBS 0.03fF
C12 a_n81_n125# VSUBS 0.03fF
@@ -90,12 +90,12 @@
X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n81_n125# a_n173_n125# 0.36fF
-C1 a_n173_n125# a_111_n125# 0.08fF
-C2 a_n81_n125# a_15_n125# 0.36fF
-C3 a_15_n125# a_111_n125# 0.36fF
-C4 a_15_n125# a_n173_n125# 0.13fF
-C5 a_n81_n125# a_111_n125# 0.13fF
+C0 a_15_n125# a_n81_n125# 0.36fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_111_n125# a_n81_n125# 0.13fF
+C3 a_111_n125# a_n173_n125# 0.08fF
+C4 a_111_n125# a_15_n125# 0.36fF
+C5 a_n173_n125# a_n81_n125# 0.36fF
C6 a_111_n125# w_n311_n335# 0.17fF
C7 a_15_n125# w_n311_n335# 0.12fF
C8 a_n81_n125# w_n311_n335# 0.12fF
@@ -106,8 +106,8 @@
.subckt inverter_cp_x1 out in vss vdd
Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
-C0 out vdd 0.10fF
-C1 out in 0.32fF
+C0 out in 0.32fF
+C1 out vdd 0.10fF
C2 out vss 0.77fF
C3 in vss 0.95fF
C4 vdd vss 3.13fF
@@ -115,37 +115,37 @@
.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
+ nCLK_d
-Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xtrans_gate_0 nCLK_d vss inverter_cp_x1_0/out vdd trans_gate
Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
-C0 nCLK_d vdd 0.03fF
-C1 inverter_cp_x1_2/in vdd 0.21fF
-C2 CLK_d vdd 0.03fF
-C3 inverter_cp_x1_0/out CLK 0.31fF
-C4 CLK_d inverter_cp_x1_2/in 0.12fF
-C5 inverter_cp_x1_0/out nCLK_d 0.11fF
-C6 inverter_cp_x1_0/out vdd 0.28fF
-C7 CLK vdd 0.36fF
-C8 inverter_cp_x1_2/in CLK 0.31fF
+C0 CLK inverter_cp_x1_0/out 0.31fF
+C1 CLK_d vdd 0.03fF
+C2 nCLK_d vdd 0.03fF
+C3 CLK vdd 0.36fF
+C4 inverter_cp_x1_2/in vdd 0.21fF
+C5 CLK_d inverter_cp_x1_2/in 0.12fF
+C6 vdd inverter_cp_x1_0/out 0.28fF
+C7 nCLK_d inverter_cp_x1_0/out 0.11fF
+C8 CLK inverter_cp_x1_2/in 0.31fF
C9 inverter_cp_x1_2/in vss 2.01fF
C10 CLK_d vss 0.96fF
C11 inverter_cp_x1_0/out vss 1.97fF
C12 CLK vss 3.03fF
-C13 nCLK_d vss 1.44fF
-C14 vdd vss 16.51fF
+C13 vdd vss 16.51fF
+C14 nCLK_d vss 1.44fF
.ends
.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
+ a_n63_n192#
X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-C0 w_n263_n314# a_n33_n95# 0.08fF
-C1 a_63_n95# a_n33_n95# 0.28fF
-C2 w_n263_n314# a_63_n95# 0.11fF
-C3 a_n125_n95# a_n33_n95# 0.28fF
-C4 a_n125_n95# w_n263_n314# 0.11fF
-C5 a_n125_n95# a_63_n95# 0.10fF
+C0 a_63_n95# a_n125_n95# 0.10fF
+C1 a_n33_n95# a_63_n95# 0.28fF
+C2 w_n263_n314# a_n125_n95# 0.11fF
+C3 a_n33_n95# w_n263_n314# 0.08fF
+C4 a_63_n95# w_n263_n314# 0.11fF
+C5 a_n33_n95# a_n125_n95# 0.28fF
C6 a_63_n95# VSUBS 0.03fF
C7 a_n33_n95# VSUBS 0.03fF
C8 a_n125_n95# VSUBS 0.03fF
@@ -158,16 +158,16 @@
X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_15_n125# a_n81_n125# 0.36fF
+C0 a_111_n125# a_n81_n125# 0.13fF
C1 a_15_n125# a_111_n125# 0.36fF
-C2 a_15_n125# a_n129_n213# 0.10fF
-C3 a_n81_n125# a_n173_n125# 0.36fF
-C4 a_111_n125# a_n173_n125# 0.08fF
-C5 a_n129_n213# a_n173_n125# 0.02fF
-C6 a_111_n125# a_n81_n125# 0.13fF
-C7 a_n129_n213# a_n81_n125# 0.10fF
-C8 a_111_n125# a_n129_n213# 0.01fF
-C9 a_15_n125# a_n173_n125# 0.13fF
+C2 a_n129_n213# a_n81_n125# 0.10fF
+C3 a_15_n125# a_n129_n213# 0.10fF
+C4 a_111_n125# a_n129_n213# 0.01fF
+C5 a_n173_n125# a_n81_n125# 0.36fF
+C6 a_n173_n125# a_15_n125# 0.13fF
+C7 a_n173_n125# a_111_n125# 0.08fF
+C8 a_n173_n125# a_n129_n213# 0.02fF
+C9 a_15_n125# a_n81_n125# 0.36fF
C10 a_111_n125# w_n311_n335# 0.05fF
C11 a_15_n125# w_n311_n335# 0.05fF
C12 a_n81_n125# w_n311_n335# 0.05fF
@@ -178,9 +178,9 @@
.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-C0 a_n125_n95# a_n33_n95# 0.88fF
-C1 a_n125_n95# a_n81_n183# 0.16fF
-C2 a_n33_n95# a_n81_n183# 0.10fF
+C0 a_n81_n183# a_n33_n95# 0.10fF
+C1 a_n125_n95# a_n33_n95# 0.88fF
+C2 a_n125_n95# a_n81_n183# 0.16fF
C3 a_n33_n95# w_n263_n305# 0.07fF
C4 a_n125_n95# w_n263_n305# 0.13fF
C5 a_n81_n183# w_n263_n305# 0.31fF
@@ -192,67 +192,67 @@
Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
-C0 m1_657_280# Q 0.94fF
-C1 m1_657_280# nQ 1.41fF
-C2 Q nD 0.05fF
-C3 nD nQ 0.05fF
-C4 Q nQ 0.93fF
-C5 m1_657_280# CLK 0.24fF
-C6 Q D 0.05fF
-C7 nQ D 0.05fF
-C8 Q vdd 0.16fF
-C9 vdd nQ 0.16fF
-C10 nQ vss 1.16fF
-C11 D vss 0.53fF
-C12 Q vss -0.55fF
-C13 m1_657_280# vss 1.88fF
-C14 nD vss 0.16fF
-C15 CLK vss 0.87fF
+C0 Q vdd 0.16fF
+C1 nD Q 0.05fF
+C2 m1_657_280# Q 0.94fF
+C3 Q D 0.05fF
+C4 CLK m1_657_280# 0.24fF
+C5 vdd nQ 0.16fF
+C6 nD nQ 0.05fF
+C7 m1_657_280# nQ 1.41fF
+C8 D nQ 0.05fF
+C9 Q nQ 0.93fF
+C10 D vss 0.53fF
+C11 Q vss -0.55fF
+C12 m1_657_280# vss 1.88fF
+C13 nD vss 0.16fF
+C14 CLK vss 0.87fF
+C15 nQ vss 1.16fF
C16 vdd vss 5.98fF
.ends
.subckt DFlipFlop latch_diff_0/m1_657_280# vss vdd latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
-+ nQ latch_diff_0/nD Q latch_diff_1/nD latch_diff_1/m1_657_280# D latch_diff_0/D CLK
-+ clock_inverter_0/inverter_cp_x1_0/out nCLK
++ nQ nCLK latch_diff_0/nD Q latch_diff_1/nD latch_diff_1/m1_657_280# D latch_diff_0/D
++ CLK clock_inverter_0/inverter_cp_x1_0/out
Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
+ latch_diff_0/D latch_diff_0/nD clock_inverter
Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
+ latch_diff_0/nD latch_diff_0/D latch_diff
Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
+ latch_diff
-C0 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
-C1 latch_diff_1/D latch_diff_1/nD 0.33fF
-C2 vdd latch_diff_0/D 0.09fF
-C3 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
-C4 vdd latch_diff_1/D 0.03fF
+C0 vdd latch_diff_0/D 0.09fF
+C1 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C2 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
+C3 latch_diff_1/D nQ 0.11fF
+C4 vdd latch_diff_1/nD 0.02fF
C5 latch_diff_0/nD vdd 0.14fF
-C6 latch_diff_0/D latch_diff_1/D 0.11fF
-C7 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
-C8 nQ latch_diff_1/nD 0.08fF
-C9 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
-C10 latch_diff_0/nD latch_diff_1/D 0.41fF
-C11 Q latch_diff_1/nD 0.01fF
-C12 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
-C13 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
-C14 nQ latch_diff_1/D 0.11fF
-C15 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
-C16 vdd latch_diff_1/nD 0.02fF
-C17 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
-C18 latch_diff_0/D latch_diff_1/nD 0.04fF
-C19 nQ vss 0.57fF
-C20 Q vss -0.92fF
-C21 latch_diff_1/m1_657_280# vss 0.64fF
-C22 nCLK vss 0.83fF
-C23 latch_diff_1/nD vss 1.83fF
-C24 latch_diff_1/D vss -0.30fF
-C25 latch_diff_0/m1_657_280# vss 0.72fF
-C26 CLK vss 0.83fF
+C6 Q latch_diff_1/nD 0.01fF
+C7 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C8 latch_diff_1/D latch_diff_0/D 0.11fF
+C9 latch_diff_1/D latch_diff_1/nD 0.33fF
+C10 latch_diff_1/D latch_diff_1/m1_657_280# 0.32fF
+C11 latch_diff_0/nD latch_diff_1/D 0.41fF
+C12 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C13 vdd latch_diff_1/D 0.03fF
+C14 nQ latch_diff_1/nD 0.08fF
+C15 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C16 latch_diff_1/nD latch_diff_0/D 0.04fF
+C17 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C18 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C19 Q vss -0.92fF
+C20 latch_diff_1/m1_657_280# vss 0.64fF
+C21 nCLK vss 0.83fF
+C22 nQ vss 0.57fF
+C23 latch_diff_1/D vss -0.30fF
+C24 latch_diff_0/m1_657_280# vss 0.72fF
+C25 CLK vss 0.83fF
+C26 latch_diff_1/nD vss 1.83fF
C27 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C28 latch_diff_0/D vss 1.29fF
C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
C30 D vss 3.27fF
-C31 latch_diff_0/nD vss 1.74fF
-C32 vdd vss 32.62fF
+C31 vdd vss 32.62fF
+C32 latch_diff_0/nD vss 1.74fF
.ends
.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
@@ -261,24 +261,24 @@
X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_n221_n84# w_n359_n303# 0.08fF
-C1 a_63_n84# w_n359_n303# 0.06fF
-C2 w_n359_n303# a_n33_n84# 0.05fF
-C3 a_n129_n84# w_n359_n303# 0.06fF
-C4 a_n221_n84# a_63_n84# 0.05fF
-C5 a_n221_n84# a_n33_n84# 0.09fF
-C6 a_n129_n84# a_n221_n84# 0.24fF
-C7 a_63_n84# a_n33_n84# 0.24fF
-C8 a_159_n84# w_n359_n303# 0.08fF
-C9 a_n129_n84# a_63_n84# 0.09fF
+C0 a_n129_n84# a_159_n84# 0.05fF
+C1 w_n359_n303# a_159_n84# 0.08fF
+C2 a_n221_n84# a_159_n84# 0.04fF
+C3 a_n33_n84# a_159_n84# 0.09fF
+C4 w_n359_n303# a_n129_n84# 0.06fF
+C5 a_n221_n84# a_n129_n84# 0.24fF
+C6 a_n33_n84# a_n129_n84# 0.24fF
+C7 w_n359_n303# a_n221_n84# 0.08fF
+C8 w_n359_n303# a_n33_n84# 0.05fF
+C9 a_129_n110# a_33_n110# 0.02fF
C10 a_n159_n110# a_n63_n110# 0.02fF
-C11 a_n129_n84# a_n33_n84# 0.24fF
-C12 a_159_n84# a_n221_n84# 0.04fF
-C13 a_159_n84# a_63_n84# 0.24fF
-C14 a_159_n84# a_n33_n84# 0.09fF
-C15 a_n129_n84# a_159_n84# 0.05fF
-C16 a_33_n110# a_n63_n110# 0.02fF
-C17 a_33_n110# a_129_n110# 0.02fF
+C11 a_n221_n84# a_n33_n84# 0.09fF
+C12 a_63_n84# a_159_n84# 0.24fF
+C13 a_63_n84# a_n129_n84# 0.09fF
+C14 w_n359_n303# a_63_n84# 0.06fF
+C15 a_33_n110# a_n63_n110# 0.02fF
+C16 a_63_n84# a_n221_n84# 0.05fF
+C17 a_63_n84# a_n33_n84# 0.24fF
C18 a_159_n84# VSUBS 0.03fF
C19 a_63_n84# VSUBS 0.03fF
C20 a_n33_n84# VSUBS 0.03fF
@@ -297,19 +297,19 @@
X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-C0 a_n33_n42# a_n129_n42# 0.12fF
-C1 a_n159_n68# a_n63_n68# 0.02fF
-C2 a_n33_n42# a_n221_n42# 0.05fF
-C3 a_63_n42# a_n33_n42# 0.12fF
-C4 a_159_n42# a_n33_n42# 0.05fF
-C5 a_n129_n42# a_n221_n42# 0.12fF
-C6 a_63_n42# a_n129_n42# 0.05fF
-C7 a_159_n42# a_n129_n42# 0.03fF
-C8 a_63_n42# a_n221_n42# 0.03fF
-C9 a_159_n42# a_n221_n42# 0.02fF
-C10 a_63_n42# a_159_n42# 0.12fF
-C11 a_129_n68# a_33_n68# 0.02fF
-C12 a_33_n68# a_n63_n68# 0.02fF
+C0 a_63_n42# a_159_n42# 0.12fF
+C1 a_n221_n42# a_n129_n42# 0.12fF
+C2 a_63_n42# a_n33_n42# 0.12fF
+C3 a_n33_n42# a_159_n42# 0.05fF
+C4 a_63_n42# a_n129_n42# 0.05fF
+C5 a_129_n68# a_33_n68# 0.02fF
+C6 a_n129_n42# a_159_n42# 0.03fF
+C7 a_n221_n42# a_63_n42# 0.03fF
+C8 a_n159_n68# a_n63_n68# 0.02fF
+C9 a_n129_n42# a_n33_n42# 0.12fF
+C10 a_n221_n42# a_159_n42# 0.02fF
+C11 a_33_n68# a_n63_n68# 0.02fF
+C12 a_n221_n42# a_n33_n42# 0.05fF
C13 a_159_n42# w_n359_n252# 0.07fF
C14 a_63_n42# w_n359_n252# 0.06fF
C15 a_n33_n42# w_n359_n252# 0.06fF
@@ -324,11 +324,11 @@
.subckt inverter_min_x4 vdd in vss out
Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
-C0 in out 0.67fF
+C0 out in 0.67fF
C1 out vdd 0.62fF
C2 in vdd 0.33fF
-C3 in vss 1.89fF
-C4 out vss 0.66fF
+C3 out vss 0.66fF
+C4 in vss 1.89fF
C5 vdd vss 3.87fF
.ends
@@ -352,72 +352,72 @@
X13 a_447_n84# a_n753_n181# a_351_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X14 a_639_n84# a_n753_n181# a_543_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X15 a_735_n84# a_n753_n181# a_639_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_543_n84# a_639_n84# 0.24fF
-C1 a_n417_n84# a_n321_n84# 0.24fF
-C2 a_447_n84# a_639_n84# 0.09fF
-C3 a_n129_n84# a_n417_n84# 0.05fF
-C4 a_n129_n84# a_159_n84# 0.05fF
-C5 a_n33_n84# a_n225_n84# 0.09fF
-C6 a_159_n84# a_63_n84# 0.24fF
-C7 w_n935_n303# a_n797_n84# 0.08fF
-C8 a_255_n84# a_159_n84# 0.24fF
-C9 a_735_n84# w_n935_n303# 0.08fF
-C10 a_351_n84# a_735_n84# 0.04fF
-C11 a_n513_n84# a_n705_n84# 0.09fF
+C0 w_n935_n303# a_n797_n84# 0.08fF
+C1 a_447_n84# a_543_n84# 0.24fF
+C2 a_63_n84# a_447_n84# 0.04fF
+C3 a_159_n84# a_543_n84# 0.04fF
+C4 w_n935_n303# a_639_n84# 0.04fF
+C5 a_n513_n84# a_n129_n84# 0.04fF
+C6 a_n33_n84# a_159_n84# 0.09fF
+C7 w_n935_n303# a_n513_n84# 0.02fF
+C8 a_63_n84# a_159_n84# 0.24fF
+C9 a_447_n84# a_735_n84# 0.05fF
+C10 a_n417_n84# a_n129_n84# 0.05fF
+C11 a_n513_n84# a_n225_n84# 0.05fF
C12 a_n417_n84# a_n225_n84# 0.09fF
-C13 a_159_n84# a_n225_n84# 0.04fF
-C14 a_351_n84# a_63_n84# 0.05fF
-C15 a_n609_n84# a_n705_n84# 0.24fF
-C16 a_n513_n84# a_n417_n84# 0.24fF
-C17 a_255_n84# a_351_n84# 0.24fF
-C18 a_n129_n84# a_n321_n84# 0.09fF
-C19 a_n609_n84# a_n417_n84# 0.09fF
-C20 a_n321_n84# a_63_n84# 0.04fF
-C21 a_543_n84# a_159_n84# 0.04fF
-C22 a_n129_n84# a_63_n84# 0.09fF
-C23 a_447_n84# a_159_n84# 0.05fF
-C24 a_n129_n84# a_255_n84# 0.04fF
-C25 a_n513_n84# w_n935_n303# 0.02fF
-C26 a_255_n84# a_63_n84# 0.09fF
-C27 a_n513_n84# a_n797_n84# 0.05fF
-C28 a_n609_n84# w_n935_n303# 0.03fF
-C29 a_n609_n84# a_n797_n84# 0.09fF
-C30 a_n321_n84# a_n225_n84# 0.24fF
-C31 a_543_n84# w_n935_n303# 0.03fF
-C32 a_351_n84# a_543_n84# 0.09fF
-C33 a_n129_n84# a_n225_n84# 0.24fF
-C34 a_n513_n84# a_n321_n84# 0.09fF
-C35 a_447_n84# w_n935_n303# 0.02fF
-C36 a_447_n84# a_351_n84# 0.24fF
-C37 a_n129_n84# a_n513_n84# 0.04fF
-C38 a_735_n84# a_543_n84# 0.09fF
-C39 a_n225_n84# a_63_n84# 0.05fF
-C40 a_n609_n84# a_n321_n84# 0.05fF
-C41 a_447_n84# a_735_n84# 0.05fF
-C42 a_639_n84# w_n935_n303# 0.04fF
-C43 a_351_n84# a_639_n84# 0.05fF
-C44 a_735_n84# a_639_n84# 0.24fF
-C45 a_n33_n84# a_n417_n84# 0.04fF
-C46 a_n33_n84# a_159_n84# 0.09fF
-C47 a_255_n84# a_543_n84# 0.05fF
-C48 a_447_n84# a_63_n84# 0.04fF
-C49 a_447_n84# a_255_n84# 0.09fF
-C50 a_n513_n84# a_n225_n84# 0.05fF
-C51 a_n417_n84# a_n705_n84# 0.05fF
-C52 a_n609_n84# a_n225_n84# 0.04fF
-C53 a_255_n84# a_639_n84# 0.04fF
-C54 a_n513_n84# a_n609_n84# 0.24fF
-C55 a_n33_n84# a_351_n84# 0.04fF
-C56 w_n935_n303# a_n705_n84# 0.04fF
-C57 a_n33_n84# a_n321_n84# 0.05fF
-C58 a_n797_n84# a_n705_n84# 0.24fF
-C59 a_n129_n84# a_n33_n84# 0.24fF
-C60 a_447_n84# a_543_n84# 0.24fF
-C61 a_351_n84# a_159_n84# 0.09fF
-C62 a_n417_n84# a_n797_n84# 0.04fF
-C63 a_n33_n84# a_63_n84# 0.24fF
-C64 a_n33_n84# a_255_n84# 0.05fF
-C65 a_n321_n84# a_n705_n84# 0.04fF
+C13 a_255_n84# a_n129_n84# 0.04fF
+C14 a_n513_n84# a_n797_n84# 0.05fF
+C15 a_63_n84# a_n33_n84# 0.24fF
+C16 a_n417_n84# a_n797_n84# 0.04fF
+C17 a_447_n84# w_n935_n303# 0.02fF
+C18 a_n321_n84# a_n33_n84# 0.05fF
+C19 a_735_n84# a_543_n84# 0.09fF
+C20 a_159_n84# a_n129_n84# 0.05fF
+C21 a_n609_n84# a_n705_n84# 0.24fF
+C22 a_63_n84# a_n321_n84# 0.04fF
+C23 a_639_n84# a_351_n84# 0.05fF
+C24 a_n321_n84# a_n705_n84# 0.04fF
+C25 a_n321_n84# a_n609_n84# 0.05fF
+C26 a_159_n84# a_n225_n84# 0.04fF
+C27 a_n417_n84# a_n513_n84# 0.24fF
+C28 a_639_n84# a_255_n84# 0.04fF
+C29 a_255_n84# a_351_n84# 0.24fF
+C30 w_n935_n303# a_543_n84# 0.03fF
+C31 a_n33_n84# a_n129_n84# 0.24fF
+C32 a_447_n84# a_639_n84# 0.09fF
+C33 a_63_n84# a_n129_n84# 0.09fF
+C34 a_n33_n84# a_n225_n84# 0.09fF
+C35 a_447_n84# a_351_n84# 0.24fF
+C36 w_n935_n303# a_n705_n84# 0.04fF
+C37 w_n935_n303# a_n609_n84# 0.03fF
+C38 a_63_n84# a_n225_n84# 0.05fF
+C39 a_n321_n84# a_n129_n84# 0.09fF
+C40 a_n609_n84# a_n225_n84# 0.04fF
+C41 w_n935_n303# a_735_n84# 0.08fF
+C42 a_n321_n84# a_n225_n84# 0.24fF
+C43 a_159_n84# a_351_n84# 0.09fF
+C44 a_447_n84# a_255_n84# 0.09fF
+C45 a_159_n84# a_255_n84# 0.24fF
+C46 a_n797_n84# a_n705_n84# 0.24fF
+C47 a_n609_n84# a_n797_n84# 0.09fF
+C48 a_639_n84# a_543_n84# 0.24fF
+C49 a_351_n84# a_543_n84# 0.09fF
+C50 a_n33_n84# a_351_n84# 0.04fF
+C51 a_447_n84# a_159_n84# 0.05fF
+C52 a_n129_n84# a_n225_n84# 0.24fF
+C53 a_63_n84# a_351_n84# 0.05fF
+C54 a_n33_n84# a_n417_n84# 0.04fF
+C55 a_n513_n84# a_n705_n84# 0.09fF
+C56 a_n609_n84# a_n513_n84# 0.24fF
+C57 a_255_n84# a_543_n84# 0.05fF
+C58 a_n321_n84# a_n513_n84# 0.09fF
+C59 a_735_n84# a_639_n84# 0.24fF
+C60 a_n417_n84# a_n705_n84# 0.05fF
+C61 a_n609_n84# a_n417_n84# 0.09fF
+C62 a_n33_n84# a_255_n84# 0.05fF
+C63 a_735_n84# a_351_n84# 0.04fF
+C64 a_n321_n84# a_n417_n84# 0.24fF
+C65 a_63_n84# a_255_n84# 0.09fF
C66 a_735_n84# VSUBS 0.03fF
C67 a_639_n84# VSUBS 0.03fF
C68 a_543_n84# VSUBS 0.03fF
@@ -459,64 +459,64 @@
X13 a_n225_n42# a_n757_64# a_n321_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
X14 a_n129_n42# a_n757_64# a_n225_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
X15 a_n609_n42# a_n757_64# a_n705_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-C0 a_159_n42# a_543_n42# 0.02fF
-C1 a_n705_n42# a_n417_n42# 0.03fF
-C2 a_n129_n42# a_n321_n42# 0.05fF
-C3 a_n797_n42# a_n513_n42# 0.03fF
-C4 a_n321_n42# a_63_n42# 0.02fF
-C5 a_639_n42# a_543_n42# 0.12fF
-C6 a_n321_n42# a_n225_n42# 0.12fF
-C7 a_735_n42# a_351_n42# 0.02fF
-C8 a_n321_n42# a_n417_n42# 0.12fF
-C9 a_n705_n42# a_n513_n42# 0.05fF
-C10 a_n797_n42# a_n705_n42# 0.12fF
-C11 a_447_n42# a_159_n42# 0.03fF
-C12 a_255_n42# a_543_n42# 0.03fF
-C13 a_447_n42# a_639_n42# 0.05fF
-C14 a_n321_n42# a_n513_n42# 0.05fF
-C15 a_159_n42# a_n33_n42# 0.05fF
-C16 a_351_n42# a_543_n42# 0.05fF
-C17 a_447_n42# a_63_n42# 0.02fF
-C18 a_n225_n42# a_n609_n42# 0.02fF
-C19 a_n129_n42# a_n33_n42# 0.12fF
-C20 a_n129_n42# a_159_n42# 0.03fF
-C21 a_n417_n42# a_n609_n42# 0.05fF
-C22 a_n33_n42# a_63_n42# 0.12fF
-C23 a_159_n42# a_63_n42# 0.12fF
-C24 a_n321_n42# a_n705_n42# 0.02fF
-C25 a_n225_n42# a_n33_n42# 0.05fF
-C26 a_159_n42# a_n225_n42# 0.02fF
-C27 a_735_n42# a_543_n42# 0.05fF
-C28 a_255_n42# a_447_n42# 0.05fF
-C29 a_n417_n42# a_n33_n42# 0.02fF
-C30 a_n129_n42# a_63_n42# 0.05fF
-C31 a_n129_n42# a_n225_n42# 0.12fF
-C32 a_447_n42# a_351_n42# 0.12fF
-C33 a_n225_n42# a_63_n42# 0.03fF
-C34 a_n513_n42# a_n609_n42# 0.12fF
-C35 a_n797_n42# a_n609_n42# 0.05fF
-C36 a_n129_n42# a_n417_n42# 0.03fF
-C37 a_255_n42# a_n33_n42# 0.03fF
-C38 a_255_n42# a_159_n42# 0.12fF
-C39 a_351_n42# a_n33_n42# 0.02fF
-C40 a_351_n42# a_159_n42# 0.05fF
-C41 a_n417_n42# a_n225_n42# 0.05fF
-C42 a_255_n42# a_639_n42# 0.02fF
-C43 a_735_n42# a_447_n42# 0.03fF
-C44 a_255_n42# a_n129_n42# 0.02fF
-C45 a_n705_n42# a_n609_n42# 0.12fF
-C46 a_255_n42# a_63_n42# 0.05fF
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-C48 a_n129_n42# a_n513_n42# 0.02fF
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-C54 a_n797_n42# a_n417_n42# 0.02fF
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-C56 a_255_n42# a_351_n42# 0.12fF
-C57 a_n321_n42# a_n33_n42# 0.03fF
+C0 a_63_n42# a_255_n42# 0.05fF
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+C10 a_n513_n42# a_n417_n42# 0.12fF
+C11 a_n705_n42# a_n321_n42# 0.02fF
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+C13 a_n129_n42# a_n33_n42# 0.12fF
+C14 a_n33_n42# a_n417_n42# 0.02fF
+C15 a_n225_n42# a_n513_n42# 0.03fF
+C16 a_639_n42# a_351_n42# 0.03fF
+C17 a_n225_n42# a_n33_n42# 0.05fF
+C18 a_639_n42# a_543_n42# 0.12fF
+C19 a_n129_n42# a_255_n42# 0.02fF
+C20 a_n129_n42# a_n321_n42# 0.05fF
+C21 a_543_n42# a_351_n42# 0.05fF
+C22 a_n417_n42# a_n321_n42# 0.12fF
+C23 a_63_n42# a_351_n42# 0.03fF
+C24 a_n225_n42# a_n321_n42# 0.12fF
+C25 a_n129_n42# a_159_n42# 0.03fF
+C26 a_n225_n42# a_159_n42# 0.02fF
+C27 a_n513_n42# a_n797_n42# 0.03fF
+C28 a_n609_n42# a_n705_n42# 0.12fF
+C29 a_n129_n42# a_63_n42# 0.05fF
+C30 a_n609_n42# a_n417_n42# 0.05fF
+C31 a_n513_n42# a_n321_n42# 0.05fF
+C32 a_n33_n42# a_255_n42# 0.03fF
+C33 a_n33_n42# a_n321_n42# 0.03fF
+C34 a_63_n42# a_n225_n42# 0.03fF
+C35 a_n225_n42# a_n609_n42# 0.02fF
+C36 a_n705_n42# a_n417_n42# 0.03fF
+C37 a_n33_n42# a_159_n42# 0.05fF
+C38 a_447_n42# a_255_n42# 0.05fF
+C39 a_n129_n42# a_n417_n42# 0.03fF
+C40 a_735_n42# a_447_n42# 0.03fF
+C41 a_255_n42# a_159_n42# 0.12fF
+C42 a_n129_n42# a_n225_n42# 0.12fF
+C43 a_n225_n42# a_n417_n42# 0.05fF
+C44 a_n33_n42# a_351_n42# 0.02fF
+C45 a_447_n42# a_159_n42# 0.03fF
+C46 a_n609_n42# a_n797_n42# 0.05fF
+C47 a_n609_n42# a_n513_n42# 0.12fF
+C48 a_63_n42# a_n33_n42# 0.12fF
+C49 a_639_n42# a_255_n42# 0.02fF
+C50 a_n705_n42# a_n797_n42# 0.12fF
+C51 a_255_n42# a_351_n42# 0.12fF
+C52 a_639_n42# a_447_n42# 0.05fF
+C53 a_n513_n42# a_n705_n42# 0.05fF
+C54 a_639_n42# a_735_n42# 0.12fF
+C55 a_447_n42# a_351_n42# 0.12fF
+C56 a_543_n42# a_255_n42# 0.03fF
+C57 a_735_n42# a_351_n42# 0.02fF
C58 a_735_n42# w_n935_n252# 0.07fF
C59 a_639_n42# w_n935_n252# 0.05fF
C60 a_543_n42# w_n935_n252# 0.05fF
@@ -542,9 +542,9 @@
+ out vdd out vdd out out out sky130_fd_pr__pfet_01v8_BDRUME
Xsky130_fd_pr__nfet_01v8_QQE8KM_0 out vss out out out out vss vss out vss in vss vss
+ out vss out vss out vss sky130_fd_pr__nfet_01v8_QQE8KM
-C0 vdd in 1.15fF
-C1 in out 1.40fF
-C2 vdd out 1.63fF
+C0 in out 1.40fF
+C1 vdd out 1.63fF
+C2 vdd in 1.15fF
C3 out vss 0.98fF
C4 in vss 7.30fF
C5 vdd vss 10.49fF
@@ -556,22 +556,22 @@
X1 a_63_n102# a_25_n199# a_n33_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
X2 a_n129_n102# a_n177_n199# a_n221_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
X3 a_n33_n102# a_n177_n199# a_n129_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
-C0 a_159_n102# a_n33_n102# 0.11fF
-C1 w_n359_n321# a_n33_n102# 0.06fF
-C2 a_n129_n102# a_63_n102# 0.11fF
-C3 a_159_n102# a_n221_n102# 0.05fF
-C4 w_n359_n321# a_n221_n102# 0.10fF
-C5 a_63_n102# a_n33_n102# 0.30fF
-C6 w_n359_n321# a_159_n102# 0.10fF
-C7 a_n129_n102# a_n33_n102# 0.30fF
-C8 a_63_n102# a_n221_n102# 0.07fF
-C9 a_25_n199# a_n177_n199# 0.07fF
-C10 a_63_n102# a_159_n102# 0.30fF
-C11 a_n129_n102# a_n221_n102# 0.30fF
-C12 a_63_n102# w_n359_n321# 0.07fF
-C13 a_n129_n102# a_159_n102# 0.07fF
-C14 a_n33_n102# a_n221_n102# 0.11fF
-C15 a_n129_n102# w_n359_n321# 0.07fF
+C0 a_159_n102# a_n129_n102# 0.07fF
+C1 a_63_n102# a_n129_n102# 0.11fF
+C2 a_n33_n102# a_n129_n102# 0.30fF
+C3 a_n221_n102# a_159_n102# 0.05fF
+C4 a_n221_n102# a_63_n102# 0.07fF
+C5 a_159_n102# w_n359_n321# 0.10fF
+C6 a_63_n102# w_n359_n321# 0.07fF
+C7 a_n177_n199# a_25_n199# 0.07fF
+C8 a_n33_n102# a_n221_n102# 0.11fF
+C9 a_n33_n102# w_n359_n321# 0.06fF
+C10 a_n221_n102# a_n129_n102# 0.30fF
+C11 a_n129_n102# w_n359_n321# 0.07fF
+C12 a_n221_n102# w_n359_n321# 0.10fF
+C13 a_63_n102# a_159_n102# 0.30fF
+C14 a_n33_n102# a_159_n102# 0.11fF
+C15 a_n33_n102# a_63_n102# 0.30fF
C16 a_159_n102# VSUBS 0.03fF
C17 a_63_n102# VSUBS 0.03fF
C18 a_n33_n102# VSUBS 0.03fF
@@ -600,13 +600,13 @@
+ avdd1p8 sky130_fd_pr__pfet_01v8_75PKJG
Xsky130_fd_pr__nfet_01v8_XRJ78J_0 m1_21_n341# avss1p8 avss1p8 avss1p8 in1 sky130_fd_pr__nfet_01v8_XRJ78J
Xsky130_fd_pr__nfet_01v8_XRJ78J_1 out avss1p8 m1_21_n341# m1_21_n341# in2 sky130_fd_pr__nfet_01v8_XRJ78J
-C0 m1_21_n341# avdd1p8 0.01fF
-C1 in2 out 0.37fF
-C2 in1 in2 0.07fF
-C3 in2 avdd1p8 0.02fF
-C4 m1_21_n341# out 0.13fF
-C5 in1 out 0.10fF
-C6 out avdd1p8 0.20fF
+C0 in2 avdd1p8 0.02fF
+C1 in2 in1 0.07fF
+C2 m1_21_n341# out 0.13fF
+C3 avdd1p8 out 0.20fF
+C4 in1 out 0.10fF
+C5 avdd1p8 m1_21_n341# 0.01fF
+C6 in2 out 0.37fF
C7 in1 m1_21_n341# 0.25fF
C8 m1_21_n341# avss1p8 0.92fF
C9 out avss1p8 0.47fF
@@ -622,32 +622,32 @@
+ DFlipFlop_4/latch_diff_0/D DFlipFlop_3/latch_diff_1/D clk_amp DFlipFlop_3/nQ clkp
+ rst
XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_0/latch_diff_1/D
-+ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ clkn DFlipFlop_0/latch_diff_0/nD
+ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_3/D
+ DFlipFlop_0/latch_diff_0/D clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ clkn DFlipFlop
++ DFlipFlop
XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_1/latch_diff_1/D
-+ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/nQ DFlipFlop_1/latch_diff_0/nD
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/nQ DFlipFlop_0/Q DFlipFlop_1/latch_diff_0/nD
+ DFlipFlop_2/D DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
+ DFlipFlop_1/latch_diff_0/D DFlipFlop_3/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_0/Q DFlipFlop
++ DFlipFlop
XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_2/latch_diff_1/D
-+ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ clkn DFlipFlop_2/latch_diff_0/nD
+ DFlipFlop_2/Q DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
+ DFlipFlop_2/latch_diff_0/D clkp DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
-+ clkn DFlipFlop
++ DFlipFlop
XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_3/latch_diff_1/D
-+ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ clkn DFlipFlop_3/latch_diff_0/nD
+ DFlipFlop_3/Q DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/D
+ DFlipFlop_3/latch_diff_0/D clkp DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
-+ clkn DFlipFlop
++ DFlipFlop
Xinverter_min_x4_0 avdd1p8 DFlipFlop_0/Q vss DFlipFlop_3/D inverter_min_x4
Xinverter_min_x4_1 avdd1p8 nand_logic_0/out vss DFlipFlop_4/D inverter_min_x4
XDFlipFlop_4 DFlipFlop_4/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_4/latch_diff_1/D
-+ DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_4/nQ DFlipFlop_4/latch_diff_0/nD
++ DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_4/nQ clkn DFlipFlop_4/latch_diff_0/nD
+ DFlipFlop_4/Q DFlipFlop_4/latch_diff_1/nD DFlipFlop_4/latch_diff_1/m1_657_280# DFlipFlop_4/D
+ DFlipFlop_4/latch_diff_0/D clkp DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out
-+ clkn DFlipFlop
++ DFlipFlop
Xinverter_min_x4_2 avdd1p8 DFlipFlop_2/D vss DFlipFlop_1/D inverter_min_x4
Xinverter_min_x4_3 avdd1p8 nand_logic_1/out vss rst inverter_min_x4
Xinverter_min_x4_4 avdd1p8 DFlipFlop_4/Q vss inverter_min_x4_4/out inverter_min_x4
@@ -656,200 +656,200 @@
+ nand_logic
Xnand_logic_1 vss DFlipFlop_4/D avdd1p8 clkp nand_logic_1/out nand_logic_1/m1_21_n341#
+ nand_logic
-C0 DFlipFlop_2/latch_diff_1/nD clkn 0.17fF
-C1 clkp DFlipFlop_2/latch_diff_1/D 0.15fF
-C2 DFlipFlop_3/latch_diff_1/D clkp 0.15fF
-C3 clkp DFlipFlop_4/Q 0.20fF
-C4 nand_logic_0/m1_21_n341# DFlipFlop_3/Q 0.07fF
-C5 DFlipFlop_0/latch_diff_0/D clkn 0.12fF
-C6 DFlipFlop_2/latch_diff_1/D clkn 0.08fF
-C7 DFlipFlop_3/latch_diff_1/D clkn 0.08fF
-C8 DFlipFlop_2/latch_diff_1/D DFlipFlop_3/Q 0.03fF
-C9 avdd1p8 DFlipFlop_2/D 4.16fF
-C10 DFlipFlop_3/Q DFlipFlop_4/Q 0.11fF
-C11 inverter_min_x4_4/out clk_amp 0.12fF
-C12 DFlipFlop_3/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.54fF
-C13 DFlipFlop_3/D avdd1p8 4.16fF
-C14 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out clkp -0.31fF
-C15 avdd1p8 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.01fF
-C16 nand_logic_1/out nand_logic_1/m1_21_n341# 0.01fF
-C17 DFlipFlop_3/nQ avdd1p8 0.03fF
-C18 avdd1p8 DFlipFlop_4/D 0.52fF
-C19 DFlipFlop_0/Q DFlipFlop_1/latch_diff_0/D 0.74fF
-C20 DFlipFlop_1/D DFlipFlop_1/latch_diff_1/D 0.02fF
-C21 DFlipFlop_2/D DFlipFlop_2/latch_diff_1/D 0.03fF
-C22 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/Q 0.55fF
-C23 DFlipFlop_3/D DFlipFlop_0/latch_diff_0/D 0.31fF
-C24 nand_logic_0/out avdd1p8 0.03fF
-C25 nand_logic_0/m1_21_n341# DFlipFlop_4/D 0.02fF
-C26 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in clkn -0.33fF
-C27 DFlipFlop_4/D DFlipFlop_4/Q 0.27fF
-C28 DFlipFlop_4/latch_diff_0/m1_657_280# clkp 0.30fF
-C29 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
-C30 clkp clkn 0.22fF
-C31 clkp DFlipFlop_3/Q 0.17fF
-C32 nand_logic_0/out nand_logic_0/m1_21_n341# 0.01fF
-C33 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out clkp 0.16fF
-C34 DFlipFlop_2/Q clkp 0.11fF
-C35 avdd1p8 inverter_min_x4_4/out 0.09fF
-C36 clkp DFlipFlop_0/latch_diff_0/nD 0.08fF
-C37 DFlipFlop_3/Q clkn 0.12fF
-C38 nand_logic_1/out avdd1p8 0.04fF
-C39 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_4/D 0.42fF
-C40 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/D 0.03fF
-C41 clkp DFlipFlop_0/latch_diff_0/m1_657_280# 0.32fF
-C42 DFlipFlop_0/Q avdd1p8 0.66fF
-C43 DFlipFlop_2/Q DFlipFlop_3/Q 0.09fF
-C44 clkp DFlipFlop_3/latch_diff_0/m1_657_280# 0.30fF
-C45 clkn DFlipFlop_2/latch_diff_0/D 0.12fF
-C46 DFlipFlop_1/D DFlipFlop_2/D 0.02fF
-C47 DFlipFlop_3/D DFlipFlop_1/D 0.28fF
-C48 DFlipFlop_2/D clkp 0.15fF
-C49 DFlipFlop_3/D clkp 0.35fF
-C50 inverter_min_x4_4/out DFlipFlop_4/Q 0.01fF
-C51 DFlipFlop_2/D clkn 0.15fF
-C52 clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
-C53 DFlipFlop_3/D clkn 0.35fF
-C54 avdd1p8 clk_amp 0.10fF
-C55 DFlipFlop_3/nQ clkp 0.13fF
-C56 DFlipFlop_4/D clkp 0.24fF
-C57 clkn DFlipFlop_3/latch_diff_0/D 0.12fF
-C58 DFlipFlop_4/latch_diff_0/D clkn 0.12fF
-C59 clkp DFlipFlop_4/latch_diff_0/nD 0.08fF
-C60 DFlipFlop_3/nQ clkn 0.10fF
-C61 clkp DFlipFlop_0/latch_diff_1/nD 0.10fF
-C62 DFlipFlop_4/D clkn 0.15fF
-C63 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.02fF
-C64 DFlipFlop_2/D DFlipFlop_2/latch_diff_0/D -0.07fF
-C65 DFlipFlop_1/D DFlipFlop_1/nQ 0.02fF
-C66 DFlipFlop_4/D DFlipFlop_3/Q 0.94fF
-C67 clkn DFlipFlop_0/latch_diff_1/nD 0.17fF
-C68 DFlipFlop_2/latch_diff_0/nD clkp 0.08fF
-C69 DFlipFlop_3/D DFlipFlop_2/D 0.06fF
-C70 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/nD 0.02fF
-C71 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out clkp 0.16fF
-C72 nand_logic_0/out DFlipFlop_3/Q 0.01fF
-C73 nand_logic_0/out DFlipFlop_2/Q 0.02fF
-C74 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/D 0.10fF
-C75 DFlipFlop_3/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.43fF
-C76 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/m1_657_280# 0.25fF
-C77 clkp inverter_min_x4_4/out 0.43fF
-C78 nand_logic_1/out clkp 0.03fF
-C79 DFlipFlop_0/Q DFlipFlop_1/D 0.72fF
-C80 DFlipFlop_2/latch_diff_1/m1_657_280# clkn 0.30fF
-C81 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/nD 0.17fF
-C82 DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_3/Q 0.04fF
-C83 DFlipFlop_4/nQ DFlipFlop_4/Q 0.06fF
-C84 DFlipFlop_3/D DFlipFlop_1/nQ 0.05fF
-C85 DFlipFlop_0/nQ clkp 0.02fF
-C86 DFlipFlop_4/latch_diff_1/D clkp 0.15fF
-C87 DFlipFlop_0/latch_diff_1/m1_657_280# clkn 0.30fF
-C88 DFlipFlop_2/nQ clkp 0.13fF
-C89 DFlipFlop_0/nQ clkn 0.02fF
-C90 DFlipFlop_4/latch_diff_1/D clkn 0.08fF
-C91 nand_logic_1/out rst 0.04fF
-C92 clkp DFlipFlop_4/latch_diff_1/nD 0.10fF
-C93 DFlipFlop_2/nQ clkn 0.02fF
-C94 DFlipFlop_2/nQ DFlipFlop_3/Q 0.02fF
-C95 nand_logic_0/out DFlipFlop_4/D 0.04fF
-C96 clkp clk_amp 0.52fF
-C97 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
-C98 DFlipFlop_4/latch_diff_1/nD clkn 0.17fF
-C99 avdd1p8 DFlipFlop_4/Q 4.03fF
-C100 nand_logic_1/m1_21_n341# clkp 0.09fF
-C101 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/D 0.41fF
-C102 DFlipFlop_3/D DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
-C103 DFlipFlop_2/latch_diff_0/m1_657_280# clkp 0.30fF
-C104 DFlipFlop_3/D DFlipFlop_0/Q 0.38fF
-C105 DFlipFlop_3/latch_diff_1/m1_657_280# clkn 0.30fF
-C106 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/nD 0.19fF
-C107 DFlipFlop_0/latch_diff_1/D clkp 0.15fF
-C108 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.03fF
-C109 DFlipFlop_3/D DFlipFlop_0/nQ 0.08fF
-C110 DFlipFlop_2/nQ DFlipFlop_2/D 0.03fF
-C111 nand_logic_1/m1_21_n341# rst 0.02fF
-C112 nand_logic_1/out DFlipFlop_4/D 0.01fF
-C113 DFlipFlop_0/latch_diff_1/D clkn 0.08fF
-C114 DFlipFlop_4/nQ clkp 0.02fF
-C115 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/D 0.49fF
-C116 DFlipFlop_4/nQ clkn 0.02fF
-C117 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.03fF
-C118 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
-C119 DFlipFlop_0/Q DFlipFlop_1/nQ 0.01fF
-C120 DFlipFlop_3/latch_diff_0/nD clkp 0.08fF
-C121 DFlipFlop_1/D avdd1p8 2.55fF
-C122 avdd1p8 clkp 0.53fF
-C123 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/D 0.08fF
-C124 clkp DFlipFlop_3/latch_diff_1/nD 0.10fF
-C125 nand_logic_1/m1_21_n341# DFlipFlop_4/D 0.09fF
-C126 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
-C127 avdd1p8 clkn -1.00fF
-C128 clkn DFlipFlop_4/latch_diff_1/m1_657_280# 0.30fF
-C129 avdd1p8 DFlipFlop_3/Q 0.76fF
-C130 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
-C131 DFlipFlop_2/latch_diff_1/nD clkp 0.20fF
-C132 clkn DFlipFlop_3/latch_diff_1/nD 0.17fF
-C133 avdd1p8 DFlipFlop_2/Q 0.05fF
-C134 avdd1p8 rst 0.02fF
+C0 clkn DFlipFlop_4/latch_diff_1/nD 0.17fF
+C1 DFlipFlop_1/latch_diff_1/D DFlipFlop_0/Q 0.10fF
+C2 clkn DFlipFlop_0/nQ 0.02fF
+C3 DFlipFlop_3/D clkp 0.35fF
+C4 nand_logic_1/out DFlipFlop_4/D 0.01fF
+C5 clkn DFlipFlop_4/latch_diff_1/D 0.08fF
+C6 clkn DFlipFlop_0/latch_diff_1/nD 0.17fF
+C7 clkn DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C8 DFlipFlop_3/D DFlipFlop_1/nQ 0.05fF
+C9 clkn DFlipFlop_3/latch_diff_1/D 0.08fF
+C10 DFlipFlop_2/Q avdd1p8 0.05fF
+C11 clkn DFlipFlop_2/D 0.15fF
+C12 clkp DFlipFlop_0/latch_diff_0/nD 0.08fF
+C13 avdd1p8 DFlipFlop_2/D 4.16fF
+C14 nand_logic_1/out rst 0.04fF
+C15 clk_amp inverter_min_x4_4/out 0.12fF
+C16 clkn DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C17 avdd1p8 DFlipFlop_1/D 2.55fF
+C18 clkn DFlipFlop_0/latch_diff_1/m1_657_280# 0.30fF
+C19 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/nD 0.19fF
+C20 DFlipFlop_3/Q DFlipFlop_4/D 0.94fF
+C21 clkp DFlipFlop_2/latch_diff_1/D 0.15fF
+C22 avdd1p8 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.01fF
+C23 nand_logic_0/out DFlipFlop_4/D 0.04fF
+C24 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_4/D 0.42fF
+C25 clkp nand_logic_1/out 0.03fF
+C26 clkp DFlipFlop_0/latch_diff_1/D 0.15fF
+C27 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/D 0.03fF
+C28 DFlipFlop_2/D DFlipFlop_2/nQ 0.03fF
+C29 nand_logic_0/m1_21_n341# DFlipFlop_4/D 0.02fF
+C30 DFlipFlop_4/Q DFlipFlop_4/D 0.27fF
+C31 clkn DFlipFlop_2/latch_diff_0/D 0.12fF
+C32 nand_logic_1/m1_21_n341# DFlipFlop_4/D 0.09fF
+C33 clkn DFlipFlop_4/D 0.15fF
+C34 avdd1p8 DFlipFlop_4/D 0.52fF
+C35 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/D 0.08fF
+C36 DFlipFlop_3/D DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C37 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/nD 0.02fF
+C38 clkp DFlipFlop_3/Q 0.17fF
+C39 nand_logic_1/m1_21_n341# rst 0.02fF
+C40 avdd1p8 DFlipFlop_0/Q 0.66fF
+C41 avdd1p8 rst 0.02fF
+C42 clkp DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C43 clkp DFlipFlop_3/nQ 0.13fF
+C44 clkp DFlipFlop_2/latch_diff_0/nD 0.08fF
+C45 clkp DFlipFlop_4/Q 0.20fF
+C46 clkp nand_logic_1/m1_21_n341# 0.09fF
+C47 clkp DFlipFlop_3/latch_diff_0/m1_657_280# 0.30fF
+C48 DFlipFlop_2/D DFlipFlop_1/D 0.02fF
+C49 clkn DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C50 DFlipFlop_0/Q DFlipFlop_1/latch_diff_0/D 0.74fF
+C51 clkn clkp 0.22fF
+C52 avdd1p8 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.01fF
+C53 DFlipFlop_2/latch_diff_1/nD clkp 0.20fF
+C54 clkp avdd1p8 0.53fF
+C55 clkp DFlipFlop_4/latch_diff_0/nD 0.08fF
+C56 clkn DFlipFlop_3/latch_diff_1/m1_657_280# 0.30fF
+C57 DFlipFlop_3/D DFlipFlop_0/latch_diff_0/D 0.31fF
+C58 clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C59 clkn DFlipFlop_3/D 0.35fF
+C60 DFlipFlop_3/D avdd1p8 4.16fF
+C61 clkp DFlipFlop_3/latch_diff_0/nD 0.08fF
+C62 clkp DFlipFlop_4/latch_diff_0/m1_657_280# 0.30fF
+C63 DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_3/Q 0.04fF
+C64 DFlipFlop_2/latch_diff_1/D DFlipFlop_3/Q 0.03fF
+C65 clkp DFlipFlop_2/nQ 0.13fF
+C66 clkp clk_amp 0.52fF
+C67 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.02fF
+C68 DFlipFlop_2/latch_diff_0/D DFlipFlop_2/D -0.07fF
+C69 clkn DFlipFlop_4/latch_diff_0/D 0.12fF
+C70 DFlipFlop_3/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.43fF
+C71 clkp DFlipFlop_4/nQ 0.02fF
+C72 clkp inverter_min_x4_4/out 0.43fF
+C73 clkp DFlipFlop_3/latch_diff_1/nD 0.10fF
+C74 clkn DFlipFlop_2/latch_diff_1/m1_657_280# 0.30fF
+C75 DFlipFlop_0/Q DFlipFlop_1/D 0.72fF
+C76 clkn DFlipFlop_2/latch_diff_1/D 0.08fF
+C77 clkp DFlipFlop_4/latch_diff_1/nD 0.10fF
+C78 nand_logic_1/m1_21_n341# nand_logic_1/out 0.01fF
+C79 clkp DFlipFlop_0/nQ 0.02fF
+C80 clkn DFlipFlop_0/latch_diff_1/D 0.08fF
+C81 avdd1p8 nand_logic_1/out 0.04fF
+C82 DFlipFlop_3/Q nand_logic_0/out 0.01fF
+C83 clkp DFlipFlop_4/latch_diff_1/D 0.15fF
+C84 DFlipFlop_0/latch_diff_1/nD clkp 0.10fF
+C85 clkp DFlipFlop_2/Q 0.11fF
+C86 DFlipFlop_3/Q nand_logic_0/m1_21_n341# 0.07fF
+C87 DFlipFlop_0/latch_diff_0/m1_657_280# clkp 0.32fF
+C88 clkp DFlipFlop_3/latch_diff_1/D 0.15fF
+C89 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/D 0.49fF
+C90 DFlipFlop_3/Q DFlipFlop_4/Q 0.11fF
+C91 clkp DFlipFlop_2/D 0.15fF
+C92 nand_logic_0/m1_21_n341# nand_logic_0/out 0.01fF
+C93 DFlipFlop_3/D DFlipFlop_0/nQ 0.08fF
+C94 clkn DFlipFlop_3/Q 0.12fF
+C95 DFlipFlop_1/nQ DFlipFlop_1/D 0.02fF
+C96 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/nD 0.17fF
+C97 DFlipFlop_3/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.54fF
+C98 avdd1p8 DFlipFlop_3/Q 0.76fF
+C99 clkp DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C100 avdd1p8 nand_logic_0/out 0.03fF
+C101 clkn DFlipFlop_3/nQ 0.10fF
+C102 DFlipFlop_3/D DFlipFlop_2/D 0.06fF
+C103 avdd1p8 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C104 avdd1p8 DFlipFlop_3/nQ 0.03fF
+C105 DFlipFlop_3/D DFlipFlop_1/D 0.28fF
+C106 avdd1p8 DFlipFlop_4/Q 4.03fF
+C107 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/D 0.41fF
+C108 clkn DFlipFlop_0/latch_diff_0/D 0.12fF
+C109 clkn DFlipFlop_2/latch_diff_1/nD 0.17fF
+C110 DFlipFlop_3/Q DFlipFlop_2/nQ 0.02fF
+C111 clkn avdd1p8 -1.00fF
+C112 clkp DFlipFlop_4/D 0.24fF
+C113 DFlipFlop_1/latch_diff_1/D DFlipFlop_1/D 0.02fF
+C114 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_0/Q 0.25fF
+C115 DFlipFlop_2/latch_diff_1/D DFlipFlop_2/D 0.03fF
+C116 clkn DFlipFlop_3/latch_diff_0/D 0.12fF
+C117 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
+C118 DFlipFlop_0/Q DFlipFlop_1/nQ 0.01fF
+C119 clkp DFlipFlop_2/latch_diff_0/m1_657_280# 0.30fF
+C120 clkn DFlipFlop_2/nQ 0.02fF
+C121 clkn DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C122 clk_amp avdd1p8 0.10fF
+C123 avdd1p8 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C124 DFlipFlop_4/Q DFlipFlop_4/nQ 0.06fF
+C125 DFlipFlop_4/Q inverter_min_x4_4/out 0.01fF
+C126 clkp DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C127 clkn DFlipFlop_4/latch_diff_1/m1_657_280# 0.30fF
+C128 DFlipFlop_3/D DFlipFlop_0/Q 0.38fF
+C129 DFlipFlop_2/Q DFlipFlop_3/Q 0.09fF
+C130 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/Q 0.55fF
+C131 clkn DFlipFlop_4/nQ 0.02fF
+C132 DFlipFlop_2/Q nand_logic_0/out 0.02fF
+C133 avdd1p8 inverter_min_x4_4/out 0.09fF
+C134 clkn DFlipFlop_3/latch_diff_1/nD 0.17fF
C135 nand_logic_1/m1_21_n341# vss 0.86fF
C136 nand_logic_0/m1_21_n341# vss 0.90fF
C137 clk_amp vss 0.43fF
C138 inverter_min_x4_4/out vss 5.90fF
-C139 nand_logic_1/out vss 1.76fF
-C140 rst vss 0.71fF
-C141 DFlipFlop_4/nQ vss 0.48fF
-C142 DFlipFlop_4/Q vss -2.08fF
-C143 DFlipFlop_4/latch_diff_1/m1_657_280# vss 0.57fF
-C144 DFlipFlop_4/latch_diff_1/nD vss 0.57fF
-C145 DFlipFlop_4/latch_diff_1/D vss -1.73fF
-C146 DFlipFlop_4/latch_diff_0/m1_657_280# vss 0.57fF
+C139 rst vss 0.71fF
+C140 nand_logic_1/out vss 1.76fF
+C141 DFlipFlop_4/Q vss -2.08fF
+C142 DFlipFlop_4/latch_diff_1/m1_657_280# vss 0.57fF
+C143 DFlipFlop_4/nQ vss 0.48fF
+C144 DFlipFlop_4/latch_diff_1/D vss -1.73fF
+C145 DFlipFlop_4/latch_diff_0/m1_657_280# vss 0.57fF
+C146 DFlipFlop_4/latch_diff_1/nD vss 0.57fF
C147 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
C148 DFlipFlop_4/latch_diff_0/D vss 0.96fF
C149 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
C150 DFlipFlop_4/D vss 4.59fF
C151 DFlipFlop_4/latch_diff_0/nD vss 1.14fF
C152 nand_logic_0/out vss 1.26fF
-C153 DFlipFlop_0/Q vss -3.86fF
-C154 DFlipFlop_3/nQ vss 0.50fF
-C155 DFlipFlop_3/Q vss -2.01fF
-C156 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.72fF
-C157 clkn vss -2.25fF
-C158 DFlipFlop_3/latch_diff_1/nD vss 0.58fF
-C159 DFlipFlop_3/latch_diff_1/D vss -1.72fF
-C160 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
-C161 clkp vss -22.80fF
-C162 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C163 DFlipFlop_3/latch_diff_0/D vss 0.96fF
-C164 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C165 DFlipFlop_3/D vss 1.64fF
+C153 DFlipFlop_3/Q vss -2.01fF
+C154 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.72fF
+C155 clkn vss -2.25fF
+C156 DFlipFlop_3/nQ vss 0.50fF
+C157 DFlipFlop_3/latch_diff_1/D vss -1.72fF
+C158 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C159 clkp vss -22.80fF
+C160 DFlipFlop_3/latch_diff_1/nD vss 0.58fF
+C161 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C162 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C163 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C164 DFlipFlop_3/D vss 1.64fF
+C165 avdd1p8 vss 196.01fF
C166 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C167 avdd1p8 vss 196.01fF
-C168 DFlipFlop_2/nQ vss 0.48fF
-C169 DFlipFlop_2/Q vss -1.05fF
-C170 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.65fF
-C171 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
-C172 DFlipFlop_2/latch_diff_1/D vss -1.73fF
-C173 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C174 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C175 DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C176 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C177 DFlipFlop_2/D vss -0.35fF
-C178 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C167 DFlipFlop_2/Q vss -1.05fF
+C168 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.65fF
+C169 DFlipFlop_2/nQ vss 0.48fF
+C170 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C171 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C172 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C173 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C174 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C175 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C176 DFlipFlop_2/D vss -0.35fF
+C177 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C178 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.59fF
C179 DFlipFlop_1/nQ vss 0.48fF
-C180 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.59fF
-C181 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C182 DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C183 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C184 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
-C185 DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C186 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C187 DFlipFlop_1/D vss -1.00fF
-C188 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
-C189 DFlipFlop_0/nQ vss 0.48fF
-C190 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.59fF
-C191 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C192 DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C193 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C180 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C181 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C182 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C183 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C184 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C185 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C186 DFlipFlop_1/D vss -1.00fF
+C187 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C188 DFlipFlop_0/Q vss -3.86fF
+C189 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.59fF
+C190 DFlipFlop_0/nQ vss 0.48fF
+C191 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C192 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C193 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
C194 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C195 DFlipFlop_0/latch_diff_0/D vss 0.96fF
C196 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
@@ -863,29 +863,29 @@
X2 a_35_n200# a_n291_n238# a_n93_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
X3 a_163_n200# a_n291_n238# a_35_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
X4 a_n93_n200# a_n291_n238# a_n221_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
-C0 a_163_n200# a_n221_n200# 0.09fF
-C1 a_n349_n200# a_n221_n200# 0.36fF
-C2 a_n221_n200# a_n291_n238# 0.08fF
-C3 w_n487_n419# a_n221_n200# 0.08fF
-C4 a_35_n200# a_n221_n200# 0.15fF
-C5 a_n93_n200# a_n221_n200# 0.36fF
-C6 a_163_n200# a_n291_n238# 0.08fF
-C7 a_163_n200# w_n487_n419# 0.08fF
-C8 a_163_n200# a_291_n200# 0.36fF
-C9 a_n349_n200# w_n487_n419# 0.18fF
-C10 w_n487_n419# a_n291_n238# 0.30fF
-C11 a_163_n200# a_35_n200# 0.36fF
-C12 a_291_n200# w_n487_n419# 0.18fF
-C13 a_n349_n200# a_35_n200# 0.09fF
-C14 a_35_n200# a_n291_n238# 0.08fF
-C15 a_163_n200# a_n93_n200# 0.15fF
-C16 a_35_n200# w_n487_n419# 0.06fF
-C17 a_35_n200# a_291_n200# 0.15fF
-C18 a_n349_n200# a_n93_n200# 0.15fF
-C19 a_n93_n200# a_n291_n238# 0.08fF
-C20 a_n93_n200# w_n487_n419# 0.06fF
-C21 a_n93_n200# a_291_n200# 0.09fF
-C22 a_n93_n200# a_35_n200# 0.36fF
+C0 a_291_n200# w_n487_n419# 0.18fF
+C1 a_n291_n238# w_n487_n419# 0.30fF
+C2 a_163_n200# a_n93_n200# 0.15fF
+C3 a_163_n200# w_n487_n419# 0.08fF
+C4 a_n93_n200# w_n487_n419# 0.06fF
+C5 a_n349_n200# a_n93_n200# 0.15fF
+C6 a_n349_n200# w_n487_n419# 0.18fF
+C7 a_n221_n200# a_35_n200# 0.15fF
+C8 a_n291_n238# a_n221_n200# 0.08fF
+C9 a_n221_n200# a_163_n200# 0.09fF
+C10 a_n221_n200# a_n93_n200# 0.36fF
+C11 a_291_n200# a_35_n200# 0.15fF
+C12 a_n291_n238# a_35_n200# 0.08fF
+C13 a_n221_n200# w_n487_n419# 0.08fF
+C14 a_n349_n200# a_n221_n200# 0.36fF
+C15 a_163_n200# a_35_n200# 0.36fF
+C16 a_n93_n200# a_35_n200# 0.36fF
+C17 a_291_n200# a_163_n200# 0.36fF
+C18 a_291_n200# a_n93_n200# 0.09fF
+C19 a_35_n200# w_n487_n419# 0.06fF
+C20 a_n291_n238# a_163_n200# 0.08fF
+C21 a_n291_n238# a_n93_n200# 0.08fF
+C22 a_n349_n200# a_35_n200# 0.09fF
C23 a_291_n200# VSUBS 0.03fF
C24 a_163_n200# VSUBS 0.03fF
C25 a_35_n200# VSUBS 0.03fF
@@ -898,9 +898,9 @@
.subckt sky130_fd_pr__nfet_01v8_L78GGD a_n73_n73# w_n211_n221# a_15_n73# a_n33_33#
X0 a_15_n73# a_n33_33# a_n73_n73# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-C0 a_n73_n73# a_n33_33# 0.02fF
-C1 a_15_n73# a_n73_n73# 0.15fF
-C2 a_15_n73# a_n33_33# 0.02fF
+C0 a_n73_n73# a_15_n73# 0.15fF
+C1 a_n33_33# a_n73_n73# 0.02fF
+C2 a_n33_33# a_15_n73# 0.02fF
C3 a_15_n73# w_n211_n221# 0.11fF
C4 a_n73_n73# w_n211_n221# 0.11fF
C5 a_n33_33# w_n211_n221# 0.18fF
@@ -908,12 +908,12 @@
.subckt sky130_fd_pr__pfet_01v8_6RX2PQ VSUBS w_n211_n268# a_15_n48# a_n33_n145# a_n73_n48#
X0 a_15_n48# a_n33_n145# a_n73_n48# w_n211_n268# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_n73_n48# a_15_n48# 0.29fF
-C1 w_n211_n268# a_n33_n145# 0.06fF
-C2 a_n73_n48# a_n33_n145# 0.01fF
-C3 a_n73_n48# w_n211_n268# 0.13fF
-C4 a_n33_n145# a_15_n48# 0.01fF
-C5 w_n211_n268# a_15_n48# 0.13fF
+C0 a_n33_n145# a_15_n48# 0.01fF
+C1 a_n33_n145# a_n73_n48# 0.01fF
+C2 a_15_n48# a_n73_n48# 0.29fF
+C3 w_n211_n268# a_n33_n145# 0.06fF
+C4 w_n211_n268# a_15_n48# 0.13fF
+C5 w_n211_n268# a_n73_n48# 0.13fF
C6 a_15_n48# VSUBS 0.03fF
C7 a_n73_n48# VSUBS 0.03fF
C8 a_n33_n145# VSUBS 0.12fF
@@ -923,9 +923,9 @@
.subckt inverter_min vdd out in vss
XXM1 vss vss out in sky130_fd_pr__nfet_01v8_L78GGD
XXM2 vss vdd out in vdd sky130_fd_pr__pfet_01v8_6RX2PQ
-C0 vdd in 0.13fF
-C1 vdd out 0.20fF
-C2 in out 0.67fF
+C0 out vdd 0.20fF
+C1 in out 0.67fF
+C2 in vdd 0.13fF
C3 out vss 0.52fF
C4 in vss 0.72fF
C5 vdd vss 2.55fF
@@ -934,10 +934,10 @@
.subckt buffer_no_inv_x05 VSUBS in avdd1p8 inverter_min_1/in out
Xinverter_min_1 avdd1p8 out inverter_min_1/in VSUBS inverter_min
Xinverter_min_0 avdd1p8 inverter_min_1/in in VSUBS inverter_min
-C0 inverter_min_1/in out 0.12fF
-C1 avdd1p8 inverter_min_1/in 0.09fF
-C2 inverter_min_1/in in 0.07fF
-C3 avdd1p8 out 0.02fF
+C0 avdd1p8 out 0.02fF
+C1 in inverter_min_1/in 0.07fF
+C2 avdd1p8 inverter_min_1/in 0.09fF
+C3 inverter_min_1/in out 0.12fF
C4 in VSUBS 0.63fF
C5 avdd1p8 VSUBS 4.78fF
C6 out VSUBS 0.45fF
@@ -948,17 +948,17 @@
+ w_n263_n330# a_n33_n111#
X0 a_n33_n111# a_n87_142# a_n125_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
X1 a_63_n111# a_21_142# a_n33_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
-C0 a_n125_n111# a_n87_142# 0.02fF
-C1 a_21_142# a_63_n111# 0.02fF
-C2 a_n125_n111# w_n263_n330# 0.14fF
-C3 a_n87_142# w_n263_n330# 0.05fF
-C4 a_n125_n111# a_n33_n111# 0.32fF
-C5 a_n125_n111# a_63_n111# 0.12fF
-C6 w_n263_n330# a_n33_n111# 0.10fF
-C7 w_n263_n330# a_63_n111# 0.14fF
-C8 a_n87_142# a_21_142# 0.14fF
-C9 a_n33_n111# a_63_n111# 0.32fF
-C10 w_n263_n330# a_21_142# 0.05fF
+C0 w_n263_n330# a_n125_n111# 0.14fF
+C1 w_n263_n330# a_21_142# 0.05fF
+C2 a_n33_n111# a_n125_n111# 0.32fF
+C3 a_63_n111# w_n263_n330# 0.14fF
+C4 a_63_n111# a_n33_n111# 0.32fF
+C5 w_n263_n330# a_n87_142# 0.05fF
+C6 a_63_n111# a_n125_n111# 0.12fF
+C7 a_63_n111# a_21_142# 0.02fF
+C8 a_n87_142# a_n125_n111# 0.02fF
+C9 a_n87_142# a_21_142# 0.14fF
+C10 w_n263_n330# a_n33_n111# 0.10fF
C11 a_63_n111# VSUBS 0.03fF
C12 a_n33_n111# VSUBS 0.03fF
C13 a_n125_n111# VSUBS 0.03fF
@@ -969,9 +969,9 @@
.subckt sky130_fd_pr__nfet_01v8_HAN8QX a_15_n142# a_n33_102# a_n73_n142# w_n211_n290#
X0 a_15_n142# a_n33_102# a_n73_n142# w_n211_n290# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
-C0 a_n33_102# a_n73_n142# 0.03fF
-C1 a_n33_102# a_15_n142# 0.03fF
-C2 a_15_n142# a_n73_n142# 0.38fF
+C0 a_n33_102# a_15_n142# 0.03fF
+C1 a_n33_102# a_n73_n142# 0.03fF
+C2 a_n73_n142# a_15_n142# 0.38fF
C3 a_15_n142# w_n211_n290# 0.19fF
C4 a_n73_n142# w_n211_n290# 0.19fF
C5 a_n33_102# w_n211_n290# 0.21fF
@@ -983,25 +983,25 @@
Xsky130_fd_pr__pfet_01v8_XA7ZMQ_1 avss1p8 sel_b DinB sel_b DinB avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
Xsky130_fd_pr__nfet_01v8_HAN8QX_0 out sel_b DinA avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
Xsky130_fd_pr__nfet_01v8_HAN8QX_1 out sel DinB avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
-C0 out DinB 0.37fF
-C1 avdd1p8 DinA 0.26fF
-C2 out sel 0.53fF
-C3 out sel_b 0.58fF
-C4 out DinA 0.30fF
-C5 DinB sel 0.02fF
-C6 DinB sel_b 0.27fF
-C7 out avdd1p8 0.23fF
-C8 sel sel_b 0.32fF
-C9 DinB DinA 0.07fF
-C10 avdd1p8 DinB 0.16fF
-C11 sel DinA 0.07fF
-C12 DinA sel_b 0.56fF
-C13 avdd1p8 sel 0.72fF
-C14 avdd1p8 sel_b 0.74fF
+C0 sel_b avdd1p8 0.74fF
+C1 sel out 0.53fF
+C2 sel DinA 0.07fF
+C3 sel DinB 0.02fF
+C4 sel avdd1p8 0.72fF
+C5 sel_b sel 0.32fF
+C6 DinA out 0.30fF
+C7 DinB out 0.37fF
+C8 avdd1p8 out 0.23fF
+C9 DinA DinB 0.07fF
+C10 avdd1p8 DinA 0.26fF
+C11 sel_b out 0.58fF
+C12 avdd1p8 DinB 0.16fF
+C13 sel_b DinA 0.56fF
+C14 sel_b DinB 0.27fF
C15 DinA avss1p8 0.63fF
-C16 sel_b avss1p8 2.16fF
-C17 out avss1p8 1.11fF
-C18 DinB avss1p8 -0.09fF
+C16 out avss1p8 1.11fF
+C17 DinB avss1p8 -0.09fF
+C18 sel_b avss1p8 2.16fF
C19 sel avss1p8 2.55fF
C20 avdd1p8 avss1p8 8.26fF
.ends
@@ -1058,246 +1058,246 @@
+ buffer_no_inv_x05_7/in buffer_no_inv_x05
Xbuffer_no_inv_x05_7 avss1p8 buffer_no_inv_x05_7/in avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in
+ mux_2to1_logic_3/DinA buffer_no_inv_x05
-C0 reg0 mux_2to1_logic_2/out 0.44fF
-C1 mux_2to1_logic_4/sel_b buffer_no_inv_x05_8/inverter_min_1/in 0.01fF
-C2 reg0 mux_2to1_logic_5/out 0.23fF
-C3 buffer_no_inv_x05_0/inverter_min_1/in buffer_no_inv_x05_1/in 0.07fF
-C4 buffer_no_inv_x05_12/inverter_min_1/in buffer_no_inv_x05_13/in 0.07fF
-C5 reg1 reg2 2.15fF
-C6 buffer_no_inv_x05_2/inverter_min_1/in mux_2to1_logic_1/DinA 0.10fF
-C7 buffer_no_inv_x05_1/in buffer_no_inv_x05_1/inverter_min_1/in 0.12fF
-C8 avdd1p8 reg2 0.14fF
-C9 mux_2to1_logic_3/DinA reg2 0.33fF
-C10 buffer_no_inv_x05_1/inverter_min_1/in mux_2to1_logic_0/DinB 0.08fF
-C11 clk mux_2to1_logic_0/DinB 0.01fF
-C12 mux_2to1_logic_0/out reg1 0.63fF
-C13 mux_2to1_logic_2/out nand_logic_0/in1 0.06fF
-C14 clk mux_2to1_logic_1/DinB 0.01fF
-C15 mux_2to1_logic_5/out mux_2to1_logic_2/out 1.29fF
-C16 reg2 mux_2to1_logic_2/sel_b 0.07fF
-C17 buffer_no_inv_x05_2/inverter_min_1/in buffer_no_inv_x05_3/in 0.07fF
-C18 mux_2to1_logic_0/out avdd1p8 0.43fF
-C19 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_3/DinB 0.02fF
-C20 mux_2to1_logic_0/out mux_2to1_logic_1/out 1.27fF
-C21 mux_2to1_logic_5/out nand_logic_0/in1 0.38fF
-C22 buffer_no_inv_x05_9/in mux_2to1_logic_3/DinB 0.10fF
-C23 mux_2to1_logic_3/out mux_2to1_logic_5/sel_b 0.37fF
-C24 buffer_no_inv_x05_7/in buffer_no_inv_x05_6/inverter_min_1/in 0.07fF
-C25 mux_2to1_logic_1/DinA mux_2to1_logic_0/DinB 0.11fF
-C26 mux_2to1_logic_4/sel_b mux_2to1_logic_3/DinB 0.04fF
-C27 mux_2to1_logic_4/DinA mux_2to1_logic_6/sel_b 0.01fF
-C28 mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB 0.66fF
-C29 mux_2to1_logic_0/sel_b mux_2to1_logic_0/DinB 0.06fF
-C30 mux_2to1_logic_0/out mux_2to1_logic_2/sel_b 0.15fF
-C31 mux_2to1_logic_3/out mux_2to1_logic_4/DinA 0.12fF
-C32 avdd1p8 buffer_no_inv_x05_6/inverter_min_1/in 0.03fF
-C33 mux_2to1_logic_3/DinA buffer_no_inv_x05_6/inverter_min_1/in 0.04fF
-C34 buffer_no_inv_x05_2/inverter_min_1/in avdd1p8 0.03fF
-C35 avdd1p8 buffer_no_inv_x05_9/in 0.10fF
-C36 avdd1p8 buffer_no_inv_x05_5/inverter_min_1/in 0.03fF
-C37 avdd1p8 mux_2to1_logic_4/sel_b 0.07fF
-C38 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinB 0.03fF
-C39 mux_2to1_logic_2/out reg2 0.85fF
-C40 buffer_no_inv_x05_3/inverter_min_1/in mux_2to1_logic_1/DinB 0.15fF
-C41 mux_2to1_logic_4/DinB mux_2to1_logic_6/sel_b 0.28fF
-C42 mux_2to1_logic_3/out mux_2to1_logic_4/DinB 0.18fF
-C43 mux_2to1_logic_4/DinB mux_2to1_logic_5/sel_b 0.31fF
-C44 avdd1p8 buffer_no_inv_x05_1/in 0.09fF
-C45 mux_2to1_logic_0/out mux_2to1_logic_2/out 0.05fF
-C46 avdd1p8 mux_2to1_logic_0/DinB 1.33fF
-C47 mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB 1.68fF
-C48 buffer_no_inv_x05_4/inverter_min_1/in mux_2to1_logic_1/DinB 0.15fF
-C49 buffer_no_inv_x05_3/in mux_2to1_logic_1/sel_b 0.01fF
-C50 avdd1p8 mux_2to1_logic_1/DinB 1.09fF
-C51 mux_2to1_logic_3/DinA mux_2to1_logic_1/DinB 0.07fF
-C52 mux_2to1_logic_1/out mux_2to1_logic_1/DinB 0.23fF
-C53 clk mux_2to1_logic_4/DinA 0.01fF
-C54 mux_2to1_logic_4/DinB buffer_no_inv_x05_13/inverter_min_1/in 0.11fF
-C55 buffer_no_inv_x05_9/inverter_min_1/in buffer_no_inv_x05_9/in 0.12fF
-C56 mux_2to1_logic_2/sel_b mux_2to1_logic_1/DinB 0.04fF
-C57 buffer_no_inv_x05_7/inverter_min_1/in mux_2to1_logic_3/DinB 0.10fF
-C58 avdd1p8 mux_2to1_logic_1/sel_b 0.09fF
-C59 buffer_no_inv_x05_7/inverter_min_1/in buffer_no_inv_x05_7/in 0.12fF
-C60 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b 0.22fF
-C61 clk mux_2to1_logic_4/DinB 0.12fF
-C62 mux_2to1_logic_3/out mux_2to1_logic_3/DinB 0.13fF
-C63 mux_2to1_logic_3/DinB mux_2to1_logic_5/sel_b 0.01fF
-C64 avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in 0.04fF
-C65 mux_2to1_logic_3/DinA buffer_no_inv_x05_7/inverter_min_1/in 0.21fF
-C66 buffer_no_inv_x05_11/inverter_min_1/in mux_2to1_logic_4/DinA 0.08fF
-C67 mux_2to1_logic_0/out reg2 0.45fF
-C68 mux_2to1_logic_3/DinB mux_2to1_logic_3/sel_b 0.21fF
-C69 mux_2to1_logic_4/DinA mux_2to1_logic_3/DinB 0.90fF
-C70 buffer_no_inv_x05_4/inverter_min_1/in buffer_no_inv_x05_5/in 0.07fF
-C71 reg1 mux_2to1_logic_3/out 0.47fF
-C72 reg1 mux_2to1_logic_5/sel_b 0.06fF
-C73 avdd1p8 mux_2to1_logic_6/sel_b 0.05fF
-C74 avdd1p8 buffer_no_inv_x05_5/in 0.09fF
-C75 mux_2to1_logic_4/out mux_2to1_logic_6/sel_b 0.04fF
-C76 mux_2to1_logic_3/out avdd1p8 0.39fF
-C77 mux_2to1_logic_1/DinA clk 0.01fF
-C78 mux_2to1_logic_3/out mux_2to1_logic_3/DinA 0.05fF
-C79 avdd1p8 mux_2to1_logic_5/sel_b 0.09fF
-C80 mux_2to1_logic_3/out mux_2to1_logic_4/out 1.18fF
-C81 mux_2to1_logic_4/out mux_2to1_logic_5/sel_b 0.20fF
-C82 mux_2to1_logic_0/sel_b buffer_no_inv_x05_1/inverter_min_1/in 0.01fF
-C83 avdd1p8 mux_2to1_logic_3/sel_b 0.09fF
-C84 mux_2to1_logic_1/out mux_2to1_logic_3/sel_b 0.04fF
-C85 avdd1p8 mux_2to1_logic_4/DinA 1.95fF
-C86 mux_2to1_logic_3/DinA mux_2to1_logic_4/DinA 0.07fF
-C87 buffer_no_inv_x05_5/in mux_2to1_logic_2/sel_b 0.01fF
-C88 mux_2to1_logic_4/out mux_2to1_logic_4/DinA 0.27fF
-C89 mux_2to1_logic_4/DinB mux_2to1_logic_3/DinB 0.29fF
-C90 reg2 mux_2to1_logic_4/sel_b 0.06fF
-C91 mux_2to1_logic_3/DinB buffer_no_inv_x05_8/inverter_min_1/in 0.10fF
-C92 clk mux_2to1_logic_3/DinB 0.01fF
-C93 reg0 mux_2to1_logic_6/sel_b 0.06fF
-C94 avdd1p8 buffer_no_inv_x05_13/inverter_min_1/in 0.03fF
-C95 reg1 mux_2to1_logic_4/DinB 0.40fF
-C96 clk clk_out 0.33fF
-C97 reg2 buffer_no_inv_x05_1/in 0.01fF
-C98 buffer_no_inv_x05_0/inverter_min_1/in avdd1p8 0.01fF
-C99 avdd1p8 mux_2to1_logic_4/DinB 2.49fF
-C100 reg2 mux_2to1_logic_0/DinB 0.06fF
-C101 mux_2to1_logic_4/out mux_2to1_logic_4/DinB 0.65fF
-C102 nand_logic_0/m1_21_n341# clk_out 0.02fF
-C103 mux_2to1_logic_1/DinA buffer_no_inv_x05_3/in 0.16fF
-C104 mux_2to1_logic_1/DinA buffer_no_inv_x05_3/inverter_min_1/in 0.23fF
-C105 reg2 mux_2to1_logic_1/DinB 0.07fF
-C106 avdd1p8 buffer_no_inv_x05_8/inverter_min_1/in 0.03fF
-C107 avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in 0.03fF
-C108 mux_2to1_logic_3/DinA buffer_no_inv_x05_8/inverter_min_1/in 0.12fF
-C109 avdd1p8 clk 1.01fF
-C110 clk mux_2to1_logic_3/DinA 0.01fF
-C111 mux_2to1_logic_2/out mux_2to1_logic_6/sel_b 0.31fF
-C112 mux_2to1_logic_3/out mux_2to1_logic_2/out 0.99fF
-C113 mux_2to1_logic_2/out mux_2to1_logic_5/sel_b 0.20fF
-C114 mux_2to1_logic_0/out mux_2to1_logic_0/DinB 0.14fF
-C115 mux_2to1_logic_5/out mux_2to1_logic_6/sel_b 0.20fF
-C116 mux_2to1_logic_3/DinB buffer_no_inv_x05_10/inverter_min_1/in 0.12fF
-C117 mux_2to1_logic_3/out mux_2to1_logic_5/out 0.07fF
-C118 mux_2to1_logic_1/DinA buffer_no_inv_x05_4/inverter_min_1/in 0.12fF
-C119 mux_2to1_logic_0/out mux_2to1_logic_1/DinB 0.12fF
-C120 buffer_no_inv_x05_13/in buffer_no_inv_x05_13/inverter_min_1/in 0.12fF
-C121 mux_2to1_logic_2/out mux_2to1_logic_3/sel_b 0.33fF
-C122 buffer_no_inv_x05_3/in buffer_no_inv_x05_3/inverter_min_1/in 0.12fF
-C123 mux_2to1_logic_1/DinA avdd1p8 0.55fF
-C124 mux_2to1_logic_1/out mux_2to1_logic_1/DinA 0.05fF
-C125 reg2 mux_2to1_logic_1/sel_b 0.13fF
-C126 buffer_no_inv_x05_12/inverter_min_1/in mux_2to1_logic_4/DinA 0.12fF
-C127 reg0 mux_2to1_logic_4/DinB -0.24fF
-C128 mux_2to1_logic_0/sel_b avdd1p8 0.05fF
-C129 mux_2to1_logic_5/out mux_2to1_logic_4/DinA 0.23fF
-C130 buffer_no_inv_x05_13/in mux_2to1_logic_4/DinB 0.11fF
-C131 buffer_no_inv_x05_7/in mux_2to1_logic_3/DinB 0.10fF
-C132 buffer_no_inv_x05_11/in buffer_no_inv_x05_10/inverter_min_1/in 0.07fF
-C133 buffer_no_inv_x05_2/inverter_min_1/in mux_2to1_logic_0/DinB 0.12fF
-C134 avdd1p8 buffer_no_inv_x05_10/inverter_min_1/in 0.03fF
-C135 buffer_no_inv_x05_11/inverter_min_1/in buffer_no_inv_x05_11/in 0.14fF
-C136 clk buffer_no_inv_x05_13/in 0.07fF
-C137 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_1/DinB 0.12fF
-C138 buffer_no_inv_x05_11/inverter_min_1/in avdd1p8 0.03fF
-C139 mux_2to1_logic_0/out mux_2to1_logic_1/sel_b 0.26fF
-C140 avdd1p8 buffer_no_inv_x05_3/in 0.11fF
-C141 avdd1p8 buffer_no_inv_x05_3/inverter_min_1/in 0.03fF
-C142 avdd1p8 mux_2to1_logic_3/DinB 0.82fF
-C143 mux_2to1_logic_3/DinA mux_2to1_logic_3/DinB 1.18fF
-C144 mux_2to1_logic_2/out mux_2to1_logic_4/DinB 0.07fF
-C145 buffer_no_inv_x05_5/inverter_min_1/in mux_2to1_logic_1/DinB 0.23fF
-C146 buffer_no_inv_x05_12/inverter_min_1/in mux_2to1_logic_4/DinB 0.07fF
-C147 avdd1p8 buffer_no_inv_x05_7/in 0.09fF
-C148 mux_2to1_logic_3/DinA buffer_no_inv_x05_7/in 0.13fF
-C149 avdd1p8 clk_out 0.04fF
-C150 mux_2to1_logic_5/out mux_2to1_logic_4/DinB 0.52fF
-C151 reg1 buffer_no_inv_x05_4/inverter_min_1/in 0.01fF
-C152 mux_2to1_logic_3/out reg2 0.36fF
-C153 reg1 avdd1p8 0.08fF
-C154 mux_2to1_logic_1/out reg1 0.36fF
-C155 avdd1p8 buffer_no_inv_x05_4/inverter_min_1/in 0.03fF
-C156 reg1 mux_2to1_logic_4/out 0.37fF
-C157 avdd1p8 buffer_no_inv_x05_11/in 0.10fF
-C158 reg2 mux_2to1_logic_3/sel_b 0.13fF
-C159 avdd1p8 mux_2to1_logic_3/DinA 0.81fF
-C160 mux_2to1_logic_1/out avdd1p8 0.84fF
-C161 reg2 mux_2to1_logic_4/DinA 0.31fF
-C162 avdd1p8 mux_2to1_logic_4/out 0.76fF
-C163 reg0 buffer_no_inv_x05_11/inverter_min_1/in 0.01fF
-C164 reg1 mux_2to1_logic_2/sel_b 0.06fF
-C165 avdd1p8 mux_2to1_logic_2/sel_b 0.07fF
-C166 mux_2to1_logic_1/out mux_2to1_logic_2/sel_b 0.19fF
-C167 reg0 reg1 0.01fF
-C168 mux_2to1_logic_1/sel_b mux_2to1_logic_0/DinB 0.04fF
-C169 reg2 mux_2to1_logic_4/DinB 0.05fF
-C170 buffer_no_inv_x05_9/inverter_min_1/in mux_2to1_logic_3/DinB 0.18fF
-C171 reg0 avdd1p8 0.05fF
-C172 mux_2to1_logic_1/sel_b mux_2to1_logic_1/DinB -0.06fF
-C173 buffer_no_inv_x05_5/in buffer_no_inv_x05_5/inverter_min_1/in 0.12fF
-C174 avdd1p8 buffer_no_inv_x05_13/in 0.10fF
-C175 clk reg2 0.12fF
-C176 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_3/sel_b 0.01fF
-C177 mux_2to1_logic_3/out mux_2to1_logic_4/sel_b 0.23fF
-C178 reg1 mux_2to1_logic_2/out 1.41fF
-C179 avdd1p8 buffer_no_inv_x05_9/inverter_min_1/in 0.03fF
-C180 mux_2to1_logic_0/out clk 0.05fF
-C181 avdd1p8 mux_2to1_logic_2/out 0.41fF
-C182 mux_2to1_logic_1/out mux_2to1_logic_2/out 0.35fF
-C183 mux_2to1_logic_1/DinA reg2 0.18fF
-C184 mux_2to1_logic_2/out mux_2to1_logic_4/out 0.26fF
-C185 buffer_no_inv_x05_12/inverter_min_1/in avdd1p8 0.03fF
-C186 mux_2to1_logic_0/sel_b reg2 0.14fF
-C187 avdd1p8 mux_2to1_logic_5/out 0.64fF
-C188 mux_2to1_logic_5/out mux_2to1_logic_4/out 0.45fF
-C189 buffer_no_inv_x05_5/in mux_2to1_logic_1/DinB 0.15fF
-C190 mux_2to1_logic_0/out mux_2to1_logic_1/DinA 0.12fF
-C191 buffer_no_inv_x05_9/in buffer_no_inv_x05_8/inverter_min_1/in 0.07fF
-C192 mux_2to1_logic_4/sel_b mux_2to1_logic_4/DinB 0.20fF
-C193 reg2 mux_2to1_logic_3/DinB 0.08fF
+C0 buffer_no_inv_x05_0/inverter_min_1/in buffer_no_inv_x05_1/in 0.07fF
+C1 avdd1p8 mux_2to1_logic_2/sel_b 0.07fF
+C2 buffer_no_inv_x05_5/in mux_2to1_logic_2/sel_b 0.01fF
+C3 mux_2to1_logic_0/out avdd1p8 0.43fF
+C4 mux_2to1_logic_3/DinA mux_2to1_logic_4/DinA 0.07fF
+C5 mux_2to1_logic_3/sel_b mux_2to1_logic_1/out 0.04fF
+C6 buffer_no_inv_x05_9/inverter_min_1/in avdd1p8 0.03fF
+C7 buffer_no_inv_x05_7/in buffer_no_inv_x05_7/inverter_min_1/in 0.12fF
+C8 buffer_no_inv_x05_1/in reg2 0.01fF
+C9 reg1 mux_2to1_logic_2/sel_b 0.06fF
+C10 mux_2to1_logic_1/DinA buffer_no_inv_x05_3/in 0.16fF
+C11 mux_2to1_logic_0/out reg1 0.63fF
+C12 mux_2to1_logic_0/DinB buffer_no_inv_x05_2/inverter_min_1/in 0.12fF
+C13 mux_2to1_logic_4/DinA mux_2to1_logic_6/sel_b 0.01fF
+C14 mux_2to1_logic_1/DinA buffer_no_inv_x05_3/inverter_min_1/in 0.23fF
+C15 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b 0.22fF
+C16 mux_2to1_logic_3/DinA mux_2to1_logic_1/DinB 0.07fF
+C17 clk reg2 0.12fF
+C18 clk clk_out 0.33fF
+C19 mux_2to1_logic_3/DinB mux_2to1_logic_4/DinA 0.90fF
+C20 mux_2to1_logic_3/DinB mux_2to1_logic_4/sel_b 0.04fF
+C21 mux_2to1_logic_2/out mux_2to1_logic_4/out 0.26fF
+C22 buffer_no_inv_x05_1/in avdd1p8 0.09fF
+C23 mux_2to1_logic_4/out mux_2to1_logic_6/sel_b 0.04fF
+C24 mux_2to1_logic_3/DinA buffer_no_inv_x05_7/inverter_min_1/in 0.21fF
+C25 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinB 0.03fF
+C26 buffer_no_inv_x05_3/inverter_min_1/in mux_2to1_logic_1/DinB 0.15fF
+C27 clk avdd1p8 1.01fF
+C28 mux_2to1_logic_3/sel_b buffer_no_inv_x05_6/inverter_min_1/in 0.01fF
+C29 mux_2to1_logic_0/DinB mux_2to1_logic_1/sel_b 0.04fF
+C30 mux_2to1_logic_0/out mux_2to1_logic_2/out 0.05fF
+C31 avdd1p8 buffer_no_inv_x05_9/in 0.10fF
+C32 mux_2to1_logic_3/DinB buffer_no_inv_x05_7/inverter_min_1/in 0.10fF
+C33 mux_2to1_logic_4/DinB mux_2to1_logic_5/out 0.52fF
+C34 reg0 mux_2to1_logic_5/out 0.23fF
+C35 mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB 0.66fF
+C36 mux_2to1_logic_4/DinA mux_2to1_logic_4/out 0.27fF
+C37 reg0 mux_2to1_logic_4/DinB -0.24fF
+C38 buffer_no_inv_x05_8/inverter_min_1/in buffer_no_inv_x05_9/in 0.07fF
+C39 avdd1p8 buffer_no_inv_x05_2/inverter_min_1/in 0.03fF
+C40 mux_2to1_logic_3/DinB buffer_no_inv_x05_9/inverter_min_1/in 0.18fF
+C41 buffer_no_inv_x05_12/inverter_min_1/in mux_2to1_logic_4/DinB 0.07fF
+C42 mux_2to1_logic_3/sel_b reg2 0.13fF
+C43 avdd1p8 mux_2to1_logic_1/out 0.84fF
+C44 mux_2to1_logic_1/DinA mux_2to1_logic_0/out 0.12fF
+C45 clk mux_2to1_logic_3/DinA 0.01fF
+C46 reg0 buffer_no_inv_x05_11/inverter_min_1/in 0.01fF
+C47 mux_2to1_logic_0/DinB mux_2to1_logic_0/sel_b 0.06fF
+C48 buffer_no_inv_x05_1/in buffer_no_inv_x05_1/inverter_min_1/in 0.12fF
+C49 mux_2to1_logic_1/sel_b reg2 0.13fF
+C50 mux_2to1_logic_4/DinB buffer_no_inv_x05_13/inverter_min_1/in 0.11fF
+C51 reg1 mux_2to1_logic_1/out 0.36fF
+C52 mux_2to1_logic_0/DinB reg2 0.06fF
+C53 clk buffer_no_inv_x05_13/in 0.07fF
+C54 mux_2to1_logic_4/DinB mux_2to1_logic_5/sel_b 0.31fF
+C55 mux_2to1_logic_3/sel_b avdd1p8 0.09fF
+C56 mux_2to1_logic_4/DinB reg2 0.05fF
+C57 avdd1p8 mux_2to1_logic_1/sel_b 0.09fF
+C58 mux_2to1_logic_2/sel_b mux_2to1_logic_1/DinB 0.04fF
+C59 mux_2to1_logic_0/out mux_2to1_logic_1/DinB 0.12fF
+C60 mux_2to1_logic_3/DinB clk 0.01fF
+C61 buffer_no_inv_x05_11/in buffer_no_inv_x05_11/inverter_min_1/in 0.14fF
+C62 mux_2to1_logic_0/DinB avdd1p8 1.33fF
+C63 avdd1p8 mux_2to1_logic_5/out 0.64fF
+C64 avdd1p8 mux_2to1_logic_4/DinB 2.49fF
+C65 buffer_no_inv_x05_6/inverter_min_1/in avdd1p8 0.03fF
+C66 reg0 avdd1p8 0.05fF
+C67 mux_2to1_logic_3/DinB buffer_no_inv_x05_9/in 0.10fF
+C68 reg2 mux_2to1_logic_0/sel_b 0.14fF
+C69 mux_2to1_logic_1/DinA clk 0.01fF
+C70 mux_2to1_logic_0/out mux_2to1_logic_2/sel_b 0.15fF
+C71 mux_2to1_logic_3/out mux_2to1_logic_5/out 0.07fF
+C72 avdd1p8 buffer_no_inv_x05_12/inverter_min_1/in 0.03fF
+C73 buffer_no_inv_x05_3/in buffer_no_inv_x05_2/inverter_min_1/in 0.07fF
+C74 mux_2to1_logic_2/out mux_2to1_logic_1/out 0.35fF
+C75 reg1 mux_2to1_logic_4/DinB 0.40fF
+C76 clk mux_2to1_logic_4/DinA 0.01fF
+C77 reg0 reg1 0.01fF
+C78 mux_2to1_logic_4/DinB mux_2to1_logic_3/out 0.18fF
+C79 buffer_no_inv_x05_6/inverter_min_1/in buffer_no_inv_x05_7/in 0.07fF
+C80 buffer_no_inv_x05_11/inverter_min_1/in avdd1p8 0.03fF
+C81 buffer_no_inv_x05_0/inverter_min_1/in avdd1p8 0.01fF
+C82 avdd1p8 buffer_no_inv_x05_13/inverter_min_1/in 0.03fF
+C83 avdd1p8 mux_2to1_logic_0/sel_b 0.05fF
+C84 buffer_no_inv_x05_11/in avdd1p8 0.10fF
+C85 avdd1p8 mux_2to1_logic_5/sel_b 0.09fF
+C86 mux_2to1_logic_3/sel_b mux_2to1_logic_2/out 0.33fF
+C87 clk mux_2to1_logic_1/DinB 0.01fF
+C88 avdd1p8 reg2 0.14fF
+C89 clk_out avdd1p8 0.04fF
+C90 mux_2to1_logic_1/DinA buffer_no_inv_x05_2/inverter_min_1/in 0.10fF
+C91 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_3/DinA 0.04fF
+C92 mux_2to1_logic_1/DinA mux_2to1_logic_1/out 0.05fF
+C93 mux_2to1_logic_3/DinB mux_2to1_logic_3/sel_b 0.21fF
+C94 reg1 mux_2to1_logic_5/sel_b 0.06fF
+C95 reg1 reg2 2.15fF
+C96 buffer_no_inv_x05_3/in mux_2to1_logic_1/sel_b 0.01fF
+C97 mux_2to1_logic_3/out mux_2to1_logic_5/sel_b 0.37fF
+C98 mux_2to1_logic_2/out mux_2to1_logic_5/out 1.29fF
+C99 mux_2to1_logic_6/sel_b mux_2to1_logic_5/out 0.20fF
+C100 mux_2to1_logic_3/out reg2 0.36fF
+C101 buffer_no_inv_x05_13/in mux_2to1_logic_4/DinB 0.11fF
+C102 mux_2to1_logic_0/DinB buffer_no_inv_x05_1/inverter_min_1/in 0.08fF
+C103 mux_2to1_logic_2/out mux_2to1_logic_4/DinB 0.07fF
+C104 mux_2to1_logic_0/out clk 0.05fF
+C105 buffer_no_inv_x05_5/in avdd1p8 0.09fF
+C106 mux_2to1_logic_6/sel_b mux_2to1_logic_4/DinB 0.28fF
+C107 reg0 mux_2to1_logic_2/out 0.44fF
+C108 buffer_no_inv_x05_10/inverter_min_1/in buffer_no_inv_x05_11/in 0.07fF
+C109 reg0 mux_2to1_logic_6/sel_b 0.06fF
+C110 nand_logic_0/in1 mux_2to1_logic_5/out 0.38fF
+C111 buffer_no_inv_x05_5/inverter_min_1/in buffer_no_inv_x05_5/in 0.12fF
+C112 buffer_no_inv_x05_5/inverter_min_1/in avdd1p8 0.03fF
+C113 buffer_no_inv_x05_4/inverter_min_1/in buffer_no_inv_x05_5/in 0.07fF
+C114 buffer_no_inv_x05_4/inverter_min_1/in avdd1p8 0.03fF
+C115 buffer_no_inv_x05_13/in buffer_no_inv_x05_12/inverter_min_1/in 0.07fF
+C116 buffer_no_inv_x05_8/inverter_min_1/in avdd1p8 0.03fF
+C117 mux_2to1_logic_3/DinB mux_2to1_logic_4/DinB 0.29fF
+C118 mux_2to1_logic_3/DinB buffer_no_inv_x05_6/inverter_min_1/in 0.02fF
+C119 reg1 avdd1p8 0.08fF
+C120 mux_2to1_logic_1/out mux_2to1_logic_1/DinB 0.23fF
+C121 avdd1p8 mux_2to1_logic_3/out 0.39fF
+C122 buffer_no_inv_x05_7/in avdd1p8 0.09fF
+C123 buffer_no_inv_x05_4/inverter_min_1/in reg1 0.01fF
+C124 mux_2to1_logic_3/DinA reg2 0.33fF
+C125 buffer_no_inv_x05_9/inverter_min_1/in buffer_no_inv_x05_9/in 0.12fF
+C126 buffer_no_inv_x05_13/in buffer_no_inv_x05_13/inverter_min_1/in 0.12fF
+C127 mux_2to1_logic_1/DinA mux_2to1_logic_0/DinB 0.11fF
+C128 buffer_no_inv_x05_10/inverter_min_1/in avdd1p8 0.03fF
+C129 mux_2to1_logic_0/sel_b buffer_no_inv_x05_1/inverter_min_1/in 0.01fF
+C130 reg1 mux_2to1_logic_3/out 0.47fF
+C131 mux_2to1_logic_4/DinA mux_2to1_logic_5/out 0.23fF
+C132 mux_2to1_logic_2/out mux_2to1_logic_5/sel_b 0.20fF
+C133 mux_2to1_logic_1/out mux_2to1_logic_2/sel_b 0.19fF
+C134 mux_2to1_logic_2/out reg2 0.85fF
+C135 mux_2to1_logic_0/out mux_2to1_logic_1/out 1.27fF
+C136 nand_logic_0/m1_21_n341# clk_out 0.02fF
+C137 mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB 1.68fF
+C138 mux_2to1_logic_4/sel_b mux_2to1_logic_4/DinB 0.20fF
+C139 mux_2to1_logic_3/DinA avdd1p8 0.81fF
+C140 mux_2to1_logic_3/DinB mux_2to1_logic_5/sel_b 0.01fF
+C141 mux_2to1_logic_1/sel_b mux_2to1_logic_1/DinB -0.06fF
+C142 mux_2to1_logic_4/out mux_2to1_logic_5/out 0.45fF
+C143 mux_2to1_logic_3/DinB reg2 0.08fF
+C144 mux_2to1_logic_4/DinA buffer_no_inv_x05_12/inverter_min_1/in 0.12fF
+C145 mux_2to1_logic_4/out mux_2to1_logic_4/DinB 0.65fF
+C146 avdd1p8 buffer_no_inv_x05_13/in 0.10fF
+C147 buffer_no_inv_x05_8/inverter_min_1/in mux_2to1_logic_3/DinA 0.12fF
+C148 mux_2to1_logic_2/out avdd1p8 0.41fF
+C149 avdd1p8 mux_2to1_logic_6/sel_b 0.05fF
+C150 mux_2to1_logic_4/DinA buffer_no_inv_x05_11/inverter_min_1/in 0.08fF
+C151 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_1/DinB 0.12fF
+C152 mux_2to1_logic_3/DinA mux_2to1_logic_3/out 0.05fF
+C153 avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in 0.03fF
+C154 buffer_no_inv_x05_7/in mux_2to1_logic_3/DinA 0.13fF
+C155 buffer_no_inv_x05_3/in avdd1p8 0.11fF
+C156 buffer_no_inv_x05_3/inverter_min_1/in avdd1p8 0.03fF
+C157 mux_2to1_logic_1/DinA reg2 0.18fF
+C158 mux_2to1_logic_0/out mux_2to1_logic_1/sel_b 0.26fF
+C159 mux_2to1_logic_3/DinB avdd1p8 0.82fF
+C160 reg1 mux_2to1_logic_2/out 1.41fF
+C161 mux_2to1_logic_2/out mux_2to1_logic_3/out 0.99fF
+C162 mux_2to1_logic_0/out mux_2to1_logic_0/DinB 0.14fF
+C163 mux_2to1_logic_4/DinA reg2 0.31fF
+C164 mux_2to1_logic_4/sel_b reg2 0.06fF
+C165 mux_2to1_logic_3/DinB buffer_no_inv_x05_8/inverter_min_1/in 0.10fF
+C166 mux_2to1_logic_3/DinB mux_2to1_logic_3/out 0.13fF
+C167 mux_2to1_logic_1/DinA avdd1p8 0.55fF
+C168 mux_2to1_logic_4/out mux_2to1_logic_5/sel_b 0.20fF
+C169 mux_2to1_logic_3/DinB buffer_no_inv_x05_7/in 0.10fF
+C170 mux_2to1_logic_1/DinA buffer_no_inv_x05_4/inverter_min_1/in 0.12fF
+C171 mux_2to1_logic_1/DinB reg2 0.07fF
+C172 mux_2to1_logic_4/DinA avdd1p8 1.95fF
+C173 avdd1p8 mux_2to1_logic_4/sel_b 0.07fF
+C174 mux_2to1_logic_3/DinB buffer_no_inv_x05_10/inverter_min_1/in 0.12fF
+C175 buffer_no_inv_x05_8/inverter_min_1/in mux_2to1_logic_4/sel_b 0.01fF
+C176 avdd1p8 mux_2to1_logic_4/out 0.76fF
+C177 mux_2to1_logic_4/DinA mux_2to1_logic_3/out 0.12fF
+C178 mux_2to1_logic_3/DinB mux_2to1_logic_3/DinA 1.18fF
+C179 mux_2to1_logic_4/sel_b mux_2to1_logic_3/out 0.23fF
+C180 mux_2to1_logic_2/out mux_2to1_logic_6/sel_b 0.31fF
+C181 mux_2to1_logic_2/sel_b reg2 0.07fF
+C182 mux_2to1_logic_0/out reg2 0.45fF
+C183 avdd1p8 mux_2to1_logic_1/DinB 1.09fF
+C184 buffer_no_inv_x05_5/in mux_2to1_logic_1/DinB 0.15fF
+C185 buffer_no_inv_x05_5/inverter_min_1/in mux_2to1_logic_1/DinB 0.23fF
+C186 mux_2to1_logic_0/DinB clk 0.01fF
+C187 buffer_no_inv_x05_4/inverter_min_1/in mux_2to1_logic_1/DinB 0.15fF
+C188 nand_logic_0/in1 mux_2to1_logic_2/out 0.06fF
+C189 reg1 mux_2to1_logic_4/out 0.37fF
+C190 clk mux_2to1_logic_4/DinB 0.12fF
+C191 mux_2to1_logic_4/out mux_2to1_logic_3/out 1.18fF
+C192 buffer_no_inv_x05_3/inverter_min_1/in buffer_no_inv_x05_3/in 0.12fF
+C193 avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in 0.04fF
C194 buffer_no_inv_x05_7/in avss1p8 1.12fF
-C195 buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.05fF
-C196 buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.04fF
-C197 buffer_no_inv_x05_5/in avss1p8 1.12fF
-C198 buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.04fF
-C199 buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.04fF
-C200 buffer_no_inv_x05_3/in avss1p8 1.13fF
-C201 buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.04fF
-C202 buffer_no_inv_x05_1/in avss1p8 1.12fF
-C203 buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.04fF
-C204 buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.05fF
-C205 clk avss1p8 2.54fF
-C206 buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
-C207 buffer_no_inv_x05_13/in avss1p8 1.12fF
-C208 mux_2to1_logic_4/DinB avss1p8 -7.83fF
-C209 buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.04fF
-C210 buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.04fF
-C211 buffer_no_inv_x05_11/in avss1p8 1.12fF
-C212 buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.04fF
-C213 nand_logic_0/m1_21_n341# avss1p8 0.72fF
-C214 clk_out avss1p8 0.27fF
-C215 buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.04fF
-C216 mux_2to1_logic_6/sel_b avss1p8 2.08fF
+C195 mux_2to1_logic_3/DinA avss1p8 0.02fF
+C196 buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.05fF
+C197 buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.04fF
+C198 buffer_no_inv_x05_5/in avss1p8 1.12fF
+C199 buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.04fF
+C200 buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.04fF
+C201 buffer_no_inv_x05_3/in avss1p8 1.13fF
+C202 buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.04fF
+C203 buffer_no_inv_x05_1/in avss1p8 1.12fF
+C204 buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.04fF
+C205 buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.05fF
+C206 clk avss1p8 2.54fF
+C207 buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C208 buffer_no_inv_x05_13/in avss1p8 1.12fF
+C209 mux_2to1_logic_4/DinB avss1p8 -7.83fF
+C210 buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.04fF
+C211 buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.04fF
+C212 buffer_no_inv_x05_11/in avss1p8 1.12fF
+C213 buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.04fF
+C214 nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C215 clk_out avss1p8 0.27fF
+C216 buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.04fF
C217 nand_logic_0/in1 avss1p8 1.63fF
-C218 reg0 avss1p8 3.16fF
-C219 mux_2to1_logic_5/sel_b avss1p8 2.05fF
+C218 mux_2to1_logic_6/sel_b avss1p8 2.08fF
+C219 reg0 avss1p8 3.16fF
C220 mux_2to1_logic_5/out avss1p8 -1.59fF
-C221 mux_2to1_logic_4/DinA avss1p8 -2.53fF
-C222 mux_2to1_logic_4/sel_b avss1p8 2.05fF
+C221 mux_2to1_logic_5/sel_b avss1p8 2.05fF
+C222 mux_2to1_logic_4/DinA avss1p8 -2.53fF
C223 mux_2to1_logic_4/out avss1p8 -2.14fF
-C224 mux_2to1_logic_3/DinA avss1p8 0.02fF
-C225 mux_2to1_logic_3/sel_b avss1p8 2.05fF
-C226 mux_2to1_logic_3/out avss1p8 -2.13fF
-C227 mux_2to1_logic_3/DinB avss1p8 -4.89fF
-C228 mux_2to1_logic_2/sel_b avss1p8 2.05fF
-C229 mux_2to1_logic_2/out avss1p8 -1.34fF
+C224 mux_2to1_logic_4/sel_b avss1p8 2.05fF
+C225 mux_2to1_logic_3/out avss1p8 -2.13fF
+C226 mux_2to1_logic_3/DinB avss1p8 -4.89fF
+C227 mux_2to1_logic_3/sel_b avss1p8 2.05fF
+C228 mux_2to1_logic_2/out avss1p8 -1.34fF
+C229 mux_2to1_logic_2/sel_b avss1p8 2.05fF
C230 reg1 avss1p8 4.95fF
C231 mux_2to1_logic_1/DinA avss1p8 0.68fF
-C232 mux_2to1_logic_1/sel_b avss1p8 2.05fF
-C233 mux_2to1_logic_1/out avss1p8 -2.38fF
-C234 mux_2to1_logic_1/DinB avss1p8 -3.84fF
+C232 mux_2to1_logic_1/out avss1p8 -2.38fF
+C233 mux_2to1_logic_1/DinB avss1p8 -3.84fF
+C234 mux_2to1_logic_1/sel_b avss1p8 2.05fF
C235 reg2 avss1p8 13.29fF
C236 avdd1p8 avss1p8 125.49fF
-C237 mux_2to1_logic_0/sel_b avss1p8 2.04fF
-C238 mux_2to1_logic_0/out avss1p8 0.32fF
-C239 mux_2to1_logic_0/DinB avss1p8 -0.89fF
+C237 mux_2to1_logic_0/out avss1p8 0.32fF
+C238 mux_2to1_logic_0/DinB avss1p8 -0.89fF
+C239 mux_2to1_logic_0/sel_b avss1p8 2.04fF
C240 buffer_no_inv_x05_9/in avss1p8 1.12fF
C241 buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.04fF
C242 buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.04fF
@@ -1308,14 +1308,14 @@
X0 a_15_n100# a_n128_122# a_n81_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X1 a_n81_n100# a_n128_122# a_n173_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X2 a_111_n100# a_n128_122# a_15_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n81_n100# a_n128_122# 0.10fF
-C1 a_n128_122# a_15_n100# 0.10fF
-C2 a_n81_n100# a_n173_n100# 0.29fF
-C3 a_n81_n100# a_15_n100# 0.29fF
-C4 a_n81_n100# a_111_n100# 0.11fF
-C5 a_n173_n100# a_15_n100# 0.11fF
-C6 a_111_n100# a_n173_n100# 0.06fF
-C7 a_111_n100# a_15_n100# 0.29fF
+C0 a_15_n100# a_111_n100# 0.29fF
+C1 a_15_n100# a_n81_n100# 0.29fF
+C2 a_n81_n100# a_111_n100# 0.11fF
+C3 a_15_n100# a_n128_122# 0.10fF
+C4 a_15_n100# a_n173_n100# 0.11fF
+C5 a_111_n100# a_n173_n100# 0.06fF
+C6 a_n128_122# a_n81_n100# 0.10fF
+C7 a_n81_n100# a_n173_n100# 0.29fF
C8 a_111_n100# w_n311_n310# 0.15fF
C9 a_15_n100# w_n311_n310# 0.11fF
C10 a_n81_n100# w_n311_n310# 0.11fF
@@ -1328,19 +1328,19 @@
X0 a_15_n100# a_n129_131# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X1 a_111_n100# a_n129_131# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X2 a_n81_n100# a_n129_131# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_15_n100# a_n81_n100# 0.29fF
-C1 a_111_n100# a_n173_n100# 0.06fF
-C2 a_15_n100# w_n311_n319# 0.08fF
-C3 a_n173_n100# a_n81_n100# 0.29fF
-C4 a_n173_n100# w_n311_n319# 0.12fF
-C5 a_n173_n100# a_15_n100# 0.11fF
-C6 a_111_n100# a_n81_n100# 0.11fF
-C7 a_n81_n100# a_n129_131# 0.08fF
-C8 a_111_n100# w_n311_n319# 0.12fF
-C9 w_n311_n319# a_n129_131# 0.16fF
-C10 a_n81_n100# w_n311_n319# 0.08fF
-C11 a_111_n100# a_15_n100# 0.29fF
-C12 a_15_n100# a_n129_131# 0.08fF
+C0 a_n81_n100# a_111_n100# 0.11fF
+C1 a_111_n100# a_15_n100# 0.29fF
+C2 a_111_n100# a_n173_n100# 0.06fF
+C3 w_n311_n319# a_n129_131# 0.16fF
+C4 a_n81_n100# a_15_n100# 0.29fF
+C5 a_n81_n100# a_n173_n100# 0.29fF
+C6 a_n173_n100# a_15_n100# 0.11fF
+C7 a_111_n100# w_n311_n319# 0.12fF
+C8 a_n81_n100# w_n311_n319# 0.08fF
+C9 a_n81_n100# a_n129_131# 0.08fF
+C10 w_n311_n319# a_15_n100# 0.08fF
+C11 a_15_n100# a_n129_131# 0.08fF
+C12 w_n311_n319# a_n173_n100# 0.12fF
C13 a_111_n100# VSUBS 0.03fF
C14 a_15_n100# VSUBS 0.03fF
C15 a_n81_n100# VSUBS 0.03fF
@@ -1356,31 +1356,31 @@
X2 a_111_n100# a_n225_131# a_15_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X3 a_n81_n100# a_n225_131# a_n177_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X4 a_n177_n100# a_n225_131# a_n269_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n269_n100# a_111_n100# 0.05fF
-C1 w_n407_n319# a_n81_n100# 0.06fF
-C2 a_15_n100# a_n177_n100# 0.11fF
-C3 w_n407_n319# a_n269_n100# 0.10fF
-C4 a_n177_n100# a_111_n100# 0.06fF
-C5 a_15_n100# a_n225_131# 0.08fF
-C6 a_n225_131# a_111_n100# 0.08fF
-C7 a_15_n100# a_207_n100# 0.11fF
-C8 a_207_n100# a_111_n100# 0.29fF
-C9 w_n407_n319# a_n177_n100# 0.05fF
-C10 w_n407_n319# a_n225_131# 0.25fF
-C11 a_n81_n100# a_n269_n100# 0.11fF
+C0 a_111_n100# a_n225_131# 0.08fF
+C1 a_n177_n100# a_207_n100# 0.05fF
+C2 a_n177_n100# a_15_n100# 0.11fF
+C3 a_n81_n100# a_207_n100# 0.06fF
+C4 a_15_n100# a_n81_n100# 0.29fF
+C5 a_15_n100# a_n269_n100# 0.06fF
+C6 a_111_n100# a_207_n100# 0.29fF
+C7 a_15_n100# a_111_n100# 0.29fF
+C8 w_n407_n319# a_n225_131# 0.25fF
+C9 a_n177_n100# a_n81_n100# 0.29fF
+C10 a_n177_n100# a_n269_n100# 0.29fF
+C11 a_n269_n100# a_n81_n100# 0.11fF
C12 w_n407_n319# a_207_n100# 0.10fF
-C13 a_15_n100# a_111_n100# 0.29fF
-C14 a_n81_n100# a_n177_n100# 0.29fF
-C15 a_n81_n100# a_n225_131# 0.08fF
-C16 w_n407_n319# a_15_n100# 0.06fF
-C17 a_n81_n100# a_207_n100# 0.06fF
-C18 w_n407_n319# a_111_n100# 0.05fF
-C19 a_n269_n100# a_n177_n100# 0.29fF
-C20 a_n81_n100# a_15_n100# 0.29fF
-C21 a_n225_131# a_n177_n100# 0.08fF
-C22 a_n81_n100# a_111_n100# 0.11fF
-C23 a_207_n100# a_n177_n100# 0.05fF
-C24 a_15_n100# a_n269_n100# 0.06fF
+C13 a_15_n100# w_n407_n319# 0.06fF
+C14 a_n177_n100# a_111_n100# 0.06fF
+C15 a_15_n100# a_n225_131# 0.08fF
+C16 a_n81_n100# a_111_n100# 0.11fF
+C17 a_n269_n100# a_111_n100# 0.05fF
+C18 a_15_n100# a_207_n100# 0.11fF
+C19 a_n177_n100# w_n407_n319# 0.05fF
+C20 a_n177_n100# a_n225_131# 0.08fF
+C21 w_n407_n319# a_n81_n100# 0.06fF
+C22 a_n81_n100# a_n225_131# 0.08fF
+C23 w_n407_n319# a_n269_n100# 0.10fF
+C24 w_n407_n319# a_111_n100# 0.05fF
C25 a_207_n100# VSUBS 0.03fF
C26 a_111_n100# VSUBS 0.03fF
C27 a_15_n100# VSUBS 0.03fF
@@ -1393,9 +1393,9 @@
.subckt sky130_fd_pr__nfet_01v8_lvt_2AP43D a_15_n81# a_n33_41# w_n211_n229# a_n73_n81#
X0 a_15_n81# a_n33_41# a_n73_n81# w_n211_n229# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=500000u l=150000u
-C0 a_n73_n81# a_n33_41# 0.02fF
-C1 a_n33_41# a_15_n81# 0.02fF
-C2 a_n73_n81# a_15_n81# 0.17fF
+C0 a_n73_n81# a_15_n81# 0.17fF
+C1 a_n33_41# a_n73_n81# 0.02fF
+C2 a_n33_41# a_15_n81# 0.02fF
C3 a_15_n81# w_n211_n229# 0.12fF
C4 a_n73_n81# w_n211_n229# 0.12fF
C5 a_n33_41# w_n211_n229# 0.18fF
@@ -1416,32 +1416,32 @@
Xsky130_fd_pr__pfet_01v8_2XUYGK_6 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
Xsky130_fd_pr__pfet_01v8_2XUYGK_7 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
Xsky130_fd_pr__pfet_01v8_2XUYGK_8 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
-C0 avdd1p8 outn 1.33fF
-C1 vp avdd1p8 6.92fF
-C2 inn inp 2.67fF
-C3 clk inp 0.06fF
-C4 vp outn 4.23fF
-C5 outp inp 1.28fF
-C6 avdd1p8 inp 1.02fF
-C7 vctrl a_3747_261# 0.76fF
-C8 inp outn 5.59fF
-C9 vp inp 0.78fF
+C0 a_3747_261# clk 0.44fF
+C1 outp clk 0.56fF
+C2 outp inn 5.76fF
+C3 avdd1p8 clk 2.36fF
+C4 inp clk 0.06fF
+C5 inn avdd1p8 1.05fF
+C6 inp inn 2.67fF
+C7 outp outn 4.18fF
+C8 outn avdd1p8 1.33fF
+C9 outn inp 5.59fF
C10 vctrl clk 0.02fF
-C11 clk a_3747_261# 0.44fF
-C12 vctrl avdd1p8 1.19fF
-C13 inn outp 5.76fF
-C14 clk outp 0.56fF
-C15 avdd1p8 a_3747_261# 1.24fF
-C16 avdd1p8 inn 1.05fF
-C17 clk avdd1p8 2.36fF
-C18 vp a_3747_261# 1.08fF
-C19 avdd1p8 outp 1.56fF
-C20 inn outn 1.15fF
-C21 vp inn 0.84fF
-C22 clk outn 0.71fF
-C23 clk vp 0.79fF
-C24 outp outn 4.18fF
-C25 vp outp 4.81fF
+C11 vp clk 0.79fF
+C12 inn vp 0.84fF
+C13 outn vp 4.23fF
+C14 a_3747_261# avdd1p8 1.24fF
+C15 outp avdd1p8 1.56fF
+C16 outp inp 1.28fF
+C17 inp avdd1p8 1.02fF
+C18 vctrl a_3747_261# 0.76fF
+C19 a_3747_261# vp 1.08fF
+C20 outp vp 4.81fF
+C21 vctrl avdd1p8 1.19fF
+C22 avdd1p8 vp 6.92fF
+C23 inp vp 0.78fF
+C24 outn clk 0.71fF
+C25 outn inn 1.15fF
C26 outn avss1p8 0.69fF
C27 inp avss1p8 -0.11fF
C28 outp avss1p8 -0.62fF
@@ -1460,24 +1460,24 @@
X2 a_n81_n100# a_n225_n188# a_n177_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X3 a_111_n100# a_n225_n188# a_15_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X4 a_n177_n100# a_n225_n188# a_n269_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n269_n100# a_15_n100# 0.06fF
+C0 a_207_n100# a_n81_n100# 0.06fF
C1 a_15_n100# a_207_n100# 0.11fF
-C2 a_111_n100# a_15_n100# 0.29fF
-C3 a_n225_n188# a_n81_n100# 0.10fF
-C4 a_n81_n100# a_n177_n100# 0.29fF
-C5 a_n81_n100# a_n269_n100# 0.11fF
-C6 a_n81_n100# a_207_n100# 0.06fF
-C7 a_n225_n188# a_n177_n100# 0.10fF
-C8 a_111_n100# a_n81_n100# 0.11fF
-C9 a_n177_n100# a_n269_n100# 0.29fF
-C10 a_n225_n188# a_111_n100# 0.10fF
-C11 a_n81_n100# a_15_n100# 0.29fF
-C12 a_n177_n100# a_207_n100# 0.05fF
-C13 a_111_n100# a_n177_n100# 0.06fF
-C14 a_111_n100# a_n269_n100# 0.05fF
-C15 a_n225_n188# a_15_n100# 0.10fF
-C16 a_111_n100# a_207_n100# 0.29fF
-C17 a_n177_n100# a_15_n100# 0.11fF
+C2 a_n177_n100# a_111_n100# 0.06fF
+C3 a_n177_n100# a_n225_n188# 0.10fF
+C4 a_n225_n188# a_111_n100# 0.10fF
+C5 a_n177_n100# a_n269_n100# 0.29fF
+C6 a_n177_n100# a_n81_n100# 0.29fF
+C7 a_n177_n100# a_15_n100# 0.11fF
+C8 a_111_n100# a_n269_n100# 0.05fF
+C9 a_111_n100# a_n81_n100# 0.11fF
+C10 a_15_n100# a_111_n100# 0.29fF
+C11 a_n177_n100# a_207_n100# 0.05fF
+C12 a_207_n100# a_111_n100# 0.29fF
+C13 a_n225_n188# a_n81_n100# 0.10fF
+C14 a_n225_n188# a_15_n100# 0.10fF
+C15 a_n81_n100# a_n269_n100# 0.11fF
+C16 a_15_n100# a_n269_n100# 0.06fF
+C17 a_15_n100# a_n81_n100# 0.29fF
C18 a_207_n100# w_n407_n310# 0.13fF
C19 a_111_n100# w_n407_n310# 0.08fF
C20 a_15_n100# w_n407_n310# 0.09fF
@@ -1495,29 +1495,29 @@
X3 a_255_n100# a_n271_122# a_159_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X4 a_n225_n100# a_n271_122# a_n317_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X5 a_n129_n100# a_n271_122# a_n225_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n33_n100# a_n317_n100# 0.06fF
-C1 a_n33_n100# a_63_n100# 0.29fF
-C2 a_n129_n100# a_159_n100# 0.06fF
-C3 a_159_n100# a_255_n100# 0.29fF
-C4 a_n129_n100# a_n271_122# 0.10fF
-C5 a_159_n100# a_63_n100# 0.29fF
-C6 a_n129_n100# a_n225_n100# 0.29fF
-C7 a_n317_n100# a_n225_n100# 0.29fF
-C8 a_n271_122# a_63_n100# 0.10fF
-C9 a_63_n100# a_n225_n100# 0.06fF
-C10 a_159_n100# a_n33_n100# 0.11fF
-C11 a_n129_n100# a_255_n100# 0.05fF
-C12 a_n271_122# a_n33_n100# 0.10fF
-C13 a_n129_n100# a_n317_n100# 0.11fF
-C14 a_n33_n100# a_n225_n100# 0.11fF
-C15 a_n129_n100# a_63_n100# 0.11fF
-C16 a_63_n100# a_255_n100# 0.11fF
-C17 a_159_n100# a_n271_122# 0.10fF
-C18 a_63_n100# a_n317_n100# 0.05fF
-C19 a_159_n100# a_n225_n100# 0.05fF
-C20 a_n271_122# a_n225_n100# 0.10fF
-C21 a_n129_n100# a_n33_n100# 0.29fF
-C22 a_n33_n100# a_255_n100# 0.06fF
+C0 a_159_n100# a_n225_n100# 0.05fF
+C1 a_n271_122# a_63_n100# 0.10fF
+C2 a_n271_122# a_n129_n100# 0.10fF
+C3 a_n271_122# a_n33_n100# 0.10fF
+C4 a_63_n100# a_n129_n100# 0.11fF
+C5 a_63_n100# a_n33_n100# 0.29fF
+C6 a_n33_n100# a_n129_n100# 0.29fF
+C7 a_63_n100# a_255_n100# 0.11fF
+C8 a_n129_n100# a_255_n100# 0.05fF
+C9 a_n33_n100# a_255_n100# 0.06fF
+C10 a_159_n100# a_n271_122# 0.10fF
+C11 a_159_n100# a_63_n100# 0.29fF
+C12 a_159_n100# a_n129_n100# 0.06fF
+C13 a_159_n100# a_n33_n100# 0.11fF
+C14 a_n225_n100# a_n317_n100# 0.29fF
+C15 a_159_n100# a_255_n100# 0.29fF
+C16 a_n271_122# a_n225_n100# 0.10fF
+C17 a_n225_n100# a_63_n100# 0.06fF
+C18 a_n225_n100# a_n129_n100# 0.29fF
+C19 a_n225_n100# a_n33_n100# 0.11fF
+C20 a_63_n100# a_n317_n100# 0.05fF
+C21 a_n129_n100# a_n317_n100# 0.11fF
+C22 a_n33_n100# a_n317_n100# 0.06fF
C23 a_255_n100# w_n455_n310# 0.13fF
C24 a_159_n100# w_n455_n310# 0.08fF
C25 a_63_n100# w_n455_n310# 0.07fF
@@ -1532,12 +1532,12 @@
+ a_n125_n100#
X0 a_63_n100# a_n79_122# a_n33_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X1 a_n33_n100# a_n79_122# a_n125_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_63_n100# a_n125_n100# 0.11fF
-C1 a_n125_n100# a_n33_n100# 0.29fF
-C2 a_n125_n100# a_n79_122# 0.02fF
-C3 a_63_n100# a_n33_n100# 0.29fF
-C4 a_63_n100# a_n79_122# 0.02fF
-C5 a_n33_n100# a_n79_122# 0.11fF
+C0 a_63_n100# a_n33_n100# 0.29fF
+C1 a_63_n100# a_n79_122# 0.02fF
+C2 a_n125_n100# a_n33_n100# 0.29fF
+C3 a_n125_n100# a_n79_122# 0.02fF
+C4 a_n79_122# a_n33_n100# 0.11fF
+C5 a_n125_n100# a_63_n100# 0.11fF
C6 a_63_n100# w_n263_n310# 0.16fF
C7 a_n33_n100# w_n263_n310# 0.12fF
C8 a_n125_n100# w_n263_n310# 0.16fF
@@ -1554,39 +1554,39 @@
X5 a_n321_n100# a_n368_122# a_n413_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X6 a_n225_n100# a_n368_122# a_n321_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X7 a_n129_n100# a_n368_122# a_n225_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n33_n100# a_n368_122# 0.10fF
-C1 a_n129_n100# a_n33_n100# 0.29fF
-C2 a_159_n100# a_351_n100# 0.11fF
-C3 a_n321_n100# a_n33_n100# 0.06fF
-C4 a_63_n100# a_159_n100# 0.29fF
-C5 a_n225_n100# a_n413_n100# 0.11fF
-C6 a_159_n100# a_n368_122# 0.10fF
-C7 a_n129_n100# a_159_n100# 0.06fF
-C8 a_n225_n100# a_63_n100# 0.06fF
-C9 a_255_n100# a_351_n100# 0.29fF
+C0 a_351_n100# a_159_n100# 0.11fF
+C1 a_n413_n100# a_n33_n100# 0.05fF
+C2 a_n225_n100# a_n129_n100# 0.29fF
+C3 a_n368_122# a_63_n100# 0.10fF
+C4 a_159_n100# a_255_n100# 0.29fF
+C5 a_351_n100# a_63_n100# 0.06fF
+C6 a_n368_122# a_255_n100# 0.10fF
+C7 a_n33_n100# a_n129_n100# 0.29fF
+C8 a_n225_n100# a_n321_n100# 0.29fF
+C9 a_n225_n100# a_159_n100# 0.05fF
C10 a_63_n100# a_255_n100# 0.11fF
-C11 a_n225_n100# a_n368_122# 0.10fF
-C12 a_n225_n100# a_n129_n100# 0.29fF
-C13 a_255_n100# a_n368_122# 0.10fF
-C14 a_n225_n100# a_n321_n100# 0.29fF
-C15 a_255_n100# a_n129_n100# 0.05fF
-C16 a_159_n100# a_n33_n100# 0.11fF
-C17 a_n225_n100# a_n33_n100# 0.11fF
-C18 a_255_n100# a_n33_n100# 0.06fF
-C19 a_63_n100# a_351_n100# 0.06fF
-C20 a_n225_n100# a_159_n100# 0.05fF
-C21 a_255_n100# a_159_n100# 0.29fF
-C22 a_n129_n100# a_n413_n100# 0.06fF
-C23 a_n321_n100# a_n413_n100# 0.29fF
-C24 a_63_n100# a_n368_122# 0.10fF
-C25 a_63_n100# a_n129_n100# 0.11fF
-C26 a_63_n100# a_n321_n100# 0.05fF
-C27 a_n129_n100# a_n368_122# 0.10fF
-C28 a_n33_n100# a_n413_n100# 0.05fF
-C29 a_n321_n100# a_n368_122# 0.10fF
-C30 a_n321_n100# a_n129_n100# 0.11fF
-C31 a_n33_n100# a_351_n100# 0.05fF
-C32 a_63_n100# a_n33_n100# 0.29fF
+C11 a_n413_n100# a_n129_n100# 0.06fF
+C12 a_351_n100# a_255_n100# 0.29fF
+C13 a_n225_n100# a_n368_122# 0.10fF
+C14 a_n33_n100# a_n321_n100# 0.06fF
+C15 a_n33_n100# a_159_n100# 0.11fF
+C16 a_n225_n100# a_63_n100# 0.06fF
+C17 a_n33_n100# a_n368_122# 0.10fF
+C18 a_n413_n100# a_n321_n100# 0.29fF
+C19 a_n33_n100# a_63_n100# 0.29fF
+C20 a_351_n100# a_n33_n100# 0.05fF
+C21 a_n129_n100# a_n321_n100# 0.11fF
+C22 a_n129_n100# a_159_n100# 0.06fF
+C23 a_n33_n100# a_255_n100# 0.06fF
+C24 a_n368_122# a_n129_n100# 0.10fF
+C25 a_n129_n100# a_63_n100# 0.11fF
+C26 a_n225_n100# a_n33_n100# 0.11fF
+C27 a_n368_122# a_n321_n100# 0.10fF
+C28 a_n368_122# a_159_n100# 0.10fF
+C29 a_n413_n100# a_n225_n100# 0.11fF
+C30 a_n129_n100# a_255_n100# 0.05fF
+C31 a_63_n100# a_n321_n100# 0.05fF
+C32 a_159_n100# a_63_n100# 0.29fF
C33 a_351_n100# w_n551_n310# 0.13fF
C34 a_255_n100# w_n551_n310# 0.08fF
C35 a_159_n100# w_n551_n310# 0.07fF
@@ -1604,19 +1604,19 @@
X0 a_15_n100# a_n129_n197# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X1 a_111_n100# a_n129_n197# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X2 a_n81_n100# a_n129_n197# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n129_n197# w_n311_n319# 0.17fF
-C1 a_15_n100# a_111_n100# 0.29fF
-C2 a_15_n100# w_n311_n319# 0.08fF
-C3 a_n173_n100# a_15_n100# 0.11fF
-C4 a_111_n100# a_n81_n100# 0.11fF
-C5 w_n311_n319# a_n81_n100# 0.08fF
-C6 a_15_n100# a_n129_n197# 0.08fF
-C7 a_n173_n100# a_n81_n100# 0.29fF
-C8 a_n129_n197# a_n81_n100# 0.08fF
-C9 a_111_n100# w_n311_n319# 0.12fF
-C10 a_n173_n100# a_111_n100# 0.06fF
+C0 a_n173_n100# a_15_n100# 0.11fF
+C1 a_n81_n100# a_n173_n100# 0.29fF
+C2 a_n129_n197# w_n311_n319# 0.17fF
+C3 a_n129_n197# a_15_n100# 0.08fF
+C4 a_111_n100# w_n311_n319# 0.12fF
+C5 a_15_n100# w_n311_n319# 0.08fF
+C6 a_n81_n100# a_n129_n197# 0.08fF
+C7 a_15_n100# a_111_n100# 0.29fF
+C8 a_n81_n100# w_n311_n319# 0.08fF
+C9 a_n81_n100# a_111_n100# 0.11fF
+C10 a_n81_n100# a_15_n100# 0.29fF
C11 a_n173_n100# w_n311_n319# 0.12fF
-C12 a_15_n100# a_n81_n100# 0.29fF
+C12 a_n173_n100# a_111_n100# 0.06fF
C13 a_111_n100# VSUBS 0.03fF
C14 a_15_n100# VSUBS 0.03fF
C15 a_n81_n100# VSUBS 0.03fF
@@ -1631,19 +1631,19 @@
X1 a_n33_n100# a_n176_122# a_n129_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X2 a_159_n100# a_n176_122# a_63_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X3 a_n129_n100# a_n176_122# a_n221_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 a_n129_n100# a_n176_122# 0.10fF
-C1 a_n221_n100# a_n33_n100# 0.11fF
-C2 a_63_n100# a_159_n100# 0.29fF
-C3 a_n33_n100# a_n176_122# 0.10fF
-C4 a_n129_n100# a_63_n100# 0.11fF
-C5 a_n129_n100# a_159_n100# 0.06fF
-C6 a_63_n100# a_n33_n100# 0.29fF
-C7 a_n33_n100# a_159_n100# 0.11fF
-C8 a_n129_n100# a_n33_n100# 0.29fF
-C9 a_63_n100# a_n221_n100# 0.06fF
-C10 a_n221_n100# a_159_n100# 0.05fF
-C11 a_63_n100# a_n176_122# 0.10fF
-C12 a_n129_n100# a_n221_n100# 0.29fF
+C0 a_n129_n100# a_63_n100# 0.11fF
+C1 a_n33_n100# a_n129_n100# 0.29fF
+C2 a_n221_n100# a_159_n100# 0.05fF
+C3 a_n221_n100# a_63_n100# 0.06fF
+C4 a_63_n100# a_n176_122# 0.10fF
+C5 a_n33_n100# a_n221_n100# 0.11fF
+C6 a_63_n100# a_159_n100# 0.29fF
+C7 a_n33_n100# a_n176_122# 0.10fF
+C8 a_n33_n100# a_159_n100# 0.11fF
+C9 a_n33_n100# a_63_n100# 0.29fF
+C10 a_n129_n100# a_n221_n100# 0.29fF
+C11 a_n129_n100# a_n176_122# 0.10fF
+C12 a_n129_n100# a_159_n100# 0.06fF
C13 a_159_n100# w_n359_n310# 0.13fF
C14 a_63_n100# w_n359_n310# 0.10fF
C15 a_n33_n100# w_n359_n310# 0.10fF
@@ -1656,14 +1656,14 @@
+ a_63_n100# a_n125_n100#
X0 a_63_n100# a_n81_n197# a_n33_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X1 a_n33_n100# a_n81_n197# a_n125_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-C0 w_n263_n319# a_63_n100# 0.13fF
-C1 a_n33_n100# a_n81_n197# 0.08fF
-C2 a_n33_n100# a_n125_n100# 0.29fF
-C3 a_n81_n197# w_n263_n319# 0.11fF
-C4 a_63_n100# a_n125_n100# 0.11fF
-C5 w_n263_n319# a_n125_n100# 0.13fF
+C0 a_n125_n100# a_63_n100# 0.11fF
+C1 a_n33_n100# a_n125_n100# 0.29fF
+C2 a_n81_n197# w_n263_n319# 0.11fF
+C3 a_63_n100# w_n263_n319# 0.13fF
+C4 a_n33_n100# a_n81_n197# 0.08fF
+C5 a_n33_n100# w_n263_n319# 0.09fF
C6 a_n33_n100# a_63_n100# 0.29fF
-C7 a_n33_n100# w_n263_n319# 0.09fF
+C7 a_n125_n100# w_n263_n319# 0.13fF
C8 a_63_n100# VSUBS 0.03fF
C9 a_n33_n100# VSUBS 0.03fF
C10 a_n125_n100# VSUBS 0.03fF
@@ -1672,7 +1672,7 @@
.ends
.subckt iref_ctrl_res_amp m1_n356_n363# avss1p8 vctrl reg2 avdd1p8 reg0 m1_1996_n363#
-+ reg1 iref m1_964_n363# m1_511_801# m1_1384_n363#
++ reg1 iref m1_511_801# m1_964_n363# m1_1384_n363#
Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 iref m1_n356_n363# m1_n356_n363# iref iref iref
+ avss1p8 iref m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_n356_n363# m1_n356_n363# avdd1p8
@@ -1694,42 +1694,42 @@
Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_1 avss1p8 m1_1384_n363# avss1p8 m1_1384_n363#
+ avss1p8 reg1 avss1p8 sky130_fd_pr__nfet_01v8_lvt_B2JNY3
Xsky130_fd_pr__pfet_01v8_XACJHL_0 avss1p8 vctrl avdd1p8 m1_511_801# vctrl vctrl sky130_fd_pr__pfet_01v8_XACJHL
-C0 reg1 vctrl 0.06fF
-C1 iref avdd1p8 0.32fF
-C2 iref m1_n356_n363# 1.89fF
-C3 iref vctrl 2.27fF
-C4 reg0 m1_964_n363# 0.47fF
-C5 m1_1384_n363# vctrl 0.95fF
-C6 reg2 reg1 0.04fF
-C7 m1_1996_n363# vctrl 1.72fF
-C8 reg2 iref 0.03fF
-C9 reg0 avdd1p8 0.03fF
-C10 reg0 vctrl 0.04fF
-C11 iref m1_448_n363# 0.29fF
-C12 iref reg1 0.03fF
-C13 m1_511_801# avdd1p8 1.05fF
-C14 m1_511_801# vctrl 1.08fF
-C15 m1_1996_n363# reg2 1.30fF
-C16 m1_1384_n363# reg1 0.85fF
-C17 iref m1_1384_n363# 0.22fF
-C18 m1_964_n363# vctrl 0.52fF
-C19 m1_1996_n363# reg1 0.06fF
-C20 m1_1996_n363# iref 0.41fF
-C21 reg0 reg1 0.04fF
-C22 reg0 iref 0.02fF
-C23 avdd1p8 m1_n356_n363# 1.41fF
-C24 avdd1p8 vctrl 0.52fF
-C25 m1_n356_n363# vctrl 0.08fF
-C26 m1_1996_n363# m1_1384_n363# 0.18fF
-C27 reg0 m1_1384_n363# 0.06fF
-C28 m1_511_801# iref 0.05fF
-C29 m1_448_n363# m1_964_n363# 0.24fF
-C30 iref m1_964_n363# 0.11fF
-C31 reg2 vctrl 0.07fF
-C32 avdd1p8 m1_448_n363# 0.77fF
-C33 m1_448_n363# m1_n356_n363# 0.17fF
-C34 m1_448_n363# vctrl 1.16fF
-C35 m1_1384_n363# m1_964_n363# 0.18fF
+C0 m1_n356_n363# vctrl 0.08fF
+C1 vctrl m1_964_n363# 0.52fF
+C2 reg1 reg2 0.04fF
+C3 m1_1996_n363# m1_1384_n363# 0.18fF
+C4 reg2 iref 0.03fF
+C5 m1_1384_n363# m1_964_n363# 0.18fF
+C6 avdd1p8 reg0 0.03fF
+C7 reg2 vctrl 0.07fF
+C8 reg0 m1_964_n363# 0.47fF
+C9 m1_511_801# iref 0.05fF
+C10 m1_448_n363# iref 0.29fF
+C11 reg1 iref 0.03fF
+C12 avdd1p8 m1_n356_n363# 1.41fF
+C13 vctrl m1_511_801# 1.08fF
+C14 vctrl m1_448_n363# 1.16fF
+C15 reg1 vctrl 0.06fF
+C16 vctrl iref 2.27fF
+C17 reg1 m1_1384_n363# 0.85fF
+C18 m1_1996_n363# reg2 1.30fF
+C19 m1_1384_n363# iref 0.22fF
+C20 reg1 reg0 0.04fF
+C21 reg0 iref 0.02fF
+C22 vctrl m1_1384_n363# 0.95fF
+C23 avdd1p8 m1_511_801# 1.05fF
+C24 vctrl reg0 0.04fF
+C25 avdd1p8 m1_448_n363# 0.77fF
+C26 m1_1996_n363# reg1 0.06fF
+C27 m1_n356_n363# m1_448_n363# 0.17fF
+C28 m1_448_n363# m1_964_n363# 0.24fF
+C29 m1_1996_n363# iref 0.41fF
+C30 avdd1p8 iref 0.32fF
+C31 reg0 m1_1384_n363# 0.06fF
+C32 m1_n356_n363# iref 1.89fF
+C33 m1_964_n363# iref 0.11fF
+C34 m1_1996_n363# vctrl 1.72fF
+C35 avdd1p8 vctrl 0.52fF
C36 m1_511_801# avss1p8 -1.62fF
C37 m1_1384_n363# avss1p8 1.30fF
C38 reg1 avss1p8 1.36fF
@@ -1745,10 +1745,10 @@
.ends
.subckt res_amp_lin_prog delay_cell_buff_0/mux_2to1_logic_0/out iref_ctrl_res_amp_0/m1_964_n363#
-+ delay_reg2 avdd1p8 inp delay_cell_buff_0/mux_2to1_logic_3/DinA delay_cell_buff_0/mux_2to1_logic_3/out
-+ res_amp_lin_0/vctrl iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_0/clk delay_cell_buff_0/nand_logic_0/in1
-+ outp_cap avss1p8 outn_cap clk delay_cell_buff_0/mux_2to1_logic_1/sel_b delay_reg0
-+ delay_cell_buff_0/mux_2to1_logic_4/DinA delay_cell_buff_0/mux_2to1_logic_4/DinB
++ delay_reg2 avdd1p8 inp delay_cell_buff_0/mux_2to1_logic_3/DinA res_amp_lin_0/vctrl
++ delay_cell_buff_0/mux_2to1_logic_3/out iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_0/clk
++ delay_cell_buff_0/nand_logic_0/in1 outp_cap avss1p8 outn_cap clk delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ delay_reg0 delay_cell_buff_0/mux_2to1_logic_4/DinA delay_cell_buff_0/mux_2to1_logic_4/DinB
+ outn delay_cell_buff_0/mux_2to1_logic_1/DinA outp delay_cell_buff_0/mux_2to1_logic_5/out
+ delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in delay_cell_buff_0/mux_2to1_logic_3/DinB
+ iref_reg0 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in iref_reg1 iref_reg2
@@ -1786,29 +1786,29 @@
Xsky130_fd_pr__nfet_01v8_lvt_595QY5_1 outp outp outp outp_cap outp_cap avss1p8 outp_cap
+ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
Xiref_ctrl_res_amp_0 iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 res_amp_lin_0/vctrl
-+ iref_reg2 avdd1p8 iref_reg0 iref_ctrl_res_amp_0/m1_1996_n363# iref_reg1 iref iref_ctrl_res_amp_0/m1_964_n363#
-+ iref_ctrl_res_amp_0/m1_511_801# iref_ctrl_res_amp_0/m1_1384_n363# iref_ctrl_res_amp
-C0 rst outn_cap 0.34fF
-C1 inverter_min_x4_0/out res_amp_lin_0/clk 0.14fF
-C2 outp_cap avdd1p8 0.25fF
-C3 iref res_amp_lin_0/vctrl 0.10fF
-C4 outn res_amp_lin_0/clk 0.09fF
-C5 outp_cap outp 1.90fF
-C6 inverter_min_x4_0/out outn_cap 0.57fF
-C7 outp_cap rst 0.34fF
-C8 outn avdd1p8 0.36fF
++ iref_reg2 avdd1p8 iref_reg0 iref_ctrl_res_amp_0/m1_1996_n363# iref_reg1 iref iref_ctrl_res_amp_0/m1_511_801#
++ iref_ctrl_res_amp_0/m1_964_n363# iref_ctrl_res_amp_0/m1_1384_n363# iref_ctrl_res_amp
+C0 avdd1p8 outn_cap 0.26fF
+C1 outp_cap inverter_min_x4_0/out 0.57fF
+C2 avdd1p8 outn 0.36fF
+C3 inverter_min_x4_0/out rst 0.01fF
+C4 outp_cap rst 0.34fF
+C5 avdd1p8 res_amp_lin_0/clk 1.99fF
+C6 res_amp_lin_0/clk outp 0.09fF
+C7 avdd1p8 outp_cap 0.25fF
+C8 outn outn_cap 1.90fF
C9 outp inverter_min_x4_0/out 0.32fF
-C10 rst inverter_min_x4_0/out 0.01fF
-C11 outn outn_cap 1.90fF
-C12 outp_cap inverter_min_x4_0/out 0.57fF
-C13 res_amp_lin_0/clk avdd1p8 1.99fF
-C14 outn_cap res_amp_lin_0/clk 1.04fF
-C15 outp res_amp_lin_0/clk 0.09fF
-C16 outn_cap avdd1p8 0.26fF
-C17 outn inverter_min_x4_0/out 0.32fF
-C18 outp avdd1p8 0.34fF
-C19 outp_cap res_amp_lin_0/clk 1.04fF
-C20 res_amp_lin_0/vctrl avdd1p8 1.42fF
+C10 outp_cap outp 1.90fF
+C11 res_amp_lin_0/clk outn_cap 1.04fF
+C12 outn_cap inverter_min_x4_0/out 0.57fF
+C13 res_amp_lin_0/vctrl iref 0.10fF
+C14 outn res_amp_lin_0/clk 0.09fF
+C15 outn inverter_min_x4_0/out 0.32fF
+C16 avdd1p8 outp 0.34fF
+C17 outn_cap rst 0.34fF
+C18 res_amp_lin_0/clk inverter_min_x4_0/out 0.14fF
+C19 avdd1p8 res_amp_lin_0/vctrl 1.42fF
+C20 res_amp_lin_0/clk outp_cap 1.04fF
C21 iref_ctrl_res_amp_0/m1_511_801# avss1p8 -1.87fF
C22 iref_ctrl_res_amp_0/m1_1384_n363# avss1p8 0.47fF
C23 iref_reg1 avss1p8 0.47fF
@@ -1828,53 +1828,53 @@
C37 res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
C38 outn_cap avss1p8 -1.33fF
C39 rst avss1p8 0.58fF
-C40 res_amp_lin_0/clk avss1p8 5.34fF
-C41 inverter_min_x4_0/out avss1p8 7.53fF
+C40 inverter_min_x4_0/out avss1p8 7.53fF
+C41 res_amp_lin_0/clk avss1p8 5.34fF
C42 delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
-C43 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
-C44 delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
-C45 delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
-C46 delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
-C47 delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
-C48 delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
-C49 delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
-C50 delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
-C51 delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
-C52 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
-C53 clk avss1p8 -4.09fF
-C54 delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
-C55 delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
-C56 delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
-C57 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
-C58 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
-C59 delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
-C60 delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
-C61 delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
-C62 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
-C63 delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C43 delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C44 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C45 delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C46 delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C47 delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C48 delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C49 delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C50 delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C51 delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C52 delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C53 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C54 clk avss1p8 -4.09fF
+C55 delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C56 delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C57 delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C58 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C59 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C60 delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C61 delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C62 delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C63 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
C64 delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
-C65 delay_reg0 avss1p8 2.77fF
-C66 delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C65 delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C66 delay_reg0 avss1p8 2.77fF
C67 delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
-C68 delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
-C69 delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C68 delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C69 delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
C70 delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
-C71 delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
-C72 delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
-C73 delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
-C74 delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
-C75 delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
-C76 delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C71 delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C72 delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C73 delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C74 delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C75 delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C76 delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
C77 delay_reg1 avss1p8 3.80fF
C78 delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
-C79 delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
-C80 delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
-C81 delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C79 delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C80 delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C81 delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
C82 delay_reg2 avss1p8 11.07fF
C83 avdd1p8 avss1p8 177.60fF
-C84 delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.03fF
-C85 delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
-C86 delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C84 delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C85 delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C86 delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.03fF
C87 delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
C88 delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
C89 delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
@@ -1900,53 +1900,53 @@
X7 a_n29_n236# a_n611_n262# a_n157_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
X8 a_n413_n236# a_n611_n262# a_n541_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
X9 a_n541_n236# a_n611_n262# a_n669_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
-C0 a_n611_n262# w_n807_n384# 0.60fF
-C1 a_483_n236# a_355_n236# 0.36fF
-C2 a_227_n236# a_483_n236# 0.15fF
-C3 a_n157_n236# a_n29_n236# 0.36fF
-C4 a_99_n236# a_n29_n236# 0.36fF
-C5 a_n157_n236# a_n541_n236# 0.09fF
-C6 a_n413_n236# a_n29_n236# 0.09fF
-C7 a_n413_n236# a_n541_n236# 0.36fF
-C8 a_355_n236# a_n29_n236# 0.09fF
-C9 a_611_n236# w_n807_n384# 0.19fF
-C10 a_227_n236# a_n29_n236# 0.15fF
-C11 a_n285_n236# a_n29_n236# 0.15fF
-C12 a_n285_n236# a_n541_n236# 0.15fF
-C13 a_n157_n236# w_n807_n384# 0.02fF
-C14 a_99_n236# w_n807_n384# 0.02fF
-C15 a_n413_n236# w_n807_n384# 0.06fF
-C16 a_355_n236# w_n807_n384# 0.06fF
-C17 a_227_n236# w_n807_n384# 0.02fF
-C18 a_n285_n236# w_n807_n384# 0.02fF
-C19 a_n413_n236# a_n669_n236# 0.15fF
-C20 a_483_n236# w_n807_n384# 0.09fF
-C21 a_n669_n236# a_n285_n236# 0.09fF
-C22 a_n157_n236# a_n611_n262# 0.08fF
-C23 a_n611_n262# a_99_n236# 0.08fF
-C24 a_n413_n236# a_n611_n262# 0.08fF
-C25 a_n611_n262# a_355_n236# 0.08fF
-C26 a_227_n236# a_n611_n262# 0.08fF
-C27 a_n285_n236# a_n611_n262# 0.08fF
-C28 a_n29_n236# w_n807_n384# 0.02fF
-C29 a_483_n236# a_n611_n262# 0.08fF
-C30 a_n541_n236# w_n807_n384# 0.09fF
-C31 a_n669_n236# a_n541_n236# 0.36fF
-C32 a_355_n236# a_611_n236# 0.15fF
-C33 a_227_n236# a_611_n236# 0.09fF
-C34 a_n157_n236# a_99_n236# 0.15fF
-C35 a_n413_n236# a_n157_n236# 0.15fF
-C36 a_n611_n262# a_n29_n236# 0.08fF
-C37 a_n611_n262# a_n541_n236# 0.08fF
-C38 a_355_n236# a_99_n236# 0.15fF
-C39 a_483_n236# a_611_n236# 0.36fF
-C40 a_n669_n236# w_n807_n384# 0.19fF
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C47 a_483_n236# a_99_n236# 0.09fF
C48 a_611_n236# VSUBS 0.03fF
C49 a_483_n236# VSUBS 0.03fF
@@ -1981,91 +1981,91 @@
X12 a_n273_n100# a_n705_n197# a_n369_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X13 a_n81_n100# a_n705_n197# a_n177_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X14 a_n177_n100# a_n705_n197# a_n273_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
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+C75 a_n177_n100# a_n81_n100# 0.29fF
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+C84 a_207_n100# a_495_n100# 0.06fF
C85 a_687_n100# VSUBS 0.03fF
C86 a_591_n100# VSUBS 0.03fF
C87 a_495_n100# VSUBS 0.03fF
@@ -2098,17 +2098,17 @@
+ m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
Xsky130_fd_pr__pfet_01v8_VCU74W_1 avss1p8 out out avdd1p8 out avdd1p8 out out avdd1p8
+ avdd1p8 avdd1p8 out m1_957_828# out avdd1p8 avdd1p8 avdd1p8 out avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
-C0 out avdd1p8 3.96fF
-C1 out m1_957_828# 1.52fF
-C2 iref avdd1p8 0.29fF
-C3 in avdd1p8 0.32fF
-C4 m1_957_828# iref 0.88fF
-C5 m1_957_828# in 0.52fF
-C6 out in 1.16fF
-C7 m1_957_828# avdd1p8 1.12fF
-C8 out avss1p8 -1.64fF
-C9 in avss1p8 1.94fF
-C10 avdd1p8 avss1p8 15.90fF
+C0 out m1_957_828# 1.52fF
+C1 in avdd1p8 0.32fF
+C2 in out 1.16fF
+C3 avdd1p8 iref 0.29fF
+C4 out avdd1p8 3.96fF
+C5 in m1_957_828# 0.52fF
+C6 m1_957_828# avdd1p8 1.12fF
+C7 m1_957_828# iref 0.88fF
+C8 avdd1p8 avss1p8 15.90fF
+C9 out avss1p8 -1.64fF
+C10 in avss1p8 1.94fF
C11 m1_957_828# avss1p8 -34.25fF
C12 iref avss1p8 4.22fF
.ends
@@ -2206,355 +2206,355 @@
X77 a_1311_n309# a_n1905_n87# a_1215_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X78 a_n1281_n309# a_n1905_n87# a_n1377_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
X79 a_n609_n309# a_n1905_n87# a_n705_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
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@@ -2825,745 +2825,745 @@
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+C548 a_351_527# a_159_527# 0.11fF
+C549 a_1215_n309# a_927_n309# 0.06fF
+C550 a_n225_109# a_63_109# 0.06fF
+C551 a_1311_n309# a_1599_n309# 0.06fF
+C552 a_n897_n309# a_n1185_n309# 0.06fF
+C553 a_1791_n309# a_1791_n727# 0.01fF
+C554 a_n705_109# a_n513_109# 0.11fF
+C555 a_n609_n727# a_n705_n727# 0.29fF
+C556 a_351_n309# a_639_n309# 0.06fF
+C557 a_n705_527# a_n897_527# 0.11fF
+C558 a_n1857_n727# a_n1857_n309# 0.01fF
+C559 a_831_109# a_831_n309# 0.01fF
+C560 a_n1281_n727# a_n1185_n727# 0.29fF
+C561 a_n1569_527# a_n1857_527# 0.06fF
+C562 a_831_n309# a_1023_n309# 0.11fF
+C563 a_1695_n309# a_1695_109# 0.01fF
+C564 a_n1473_n309# a_n1089_n309# 0.05fF
+C565 a_n1857_n309# a_n1949_n309# 0.29fF
+C566 a_n609_n309# a_n993_n309# 0.05fF
+C567 a_255_n727# a_63_n727# 0.11fF
+C568 a_255_527# a_543_527# 0.06fF
+C569 a_63_n727# a_447_n727# 0.05fF
+C570 a_1695_n309# a_1503_n309# 0.11fF
+C571 a_n129_n309# a_255_n309# 0.05fF
+C572 a_255_109# a_639_109# 0.05fF
+C573 a_735_n309# a_543_n309# 0.11fF
+C574 a_639_n309# a_639_109# 0.01fF
+C575 a_1023_527# a_735_527# 0.06fF
+C576 a_543_109# a_639_109# 0.29fF
+C577 a_n321_n727# a_n321_n309# 0.01fF
+C578 a_n1857_n309# a_n1857_109# 0.01fF
+C579 a_n417_527# a_n225_527# 0.11fF
+C580 a_n705_n309# a_n897_n309# 0.11fF
+C581 a_447_527# a_159_527# 0.06fF
+C582 a_255_n727# a_n33_n727# 0.06fF
+C583 a_1695_n727# a_1311_n727# 0.05fF
+C584 a_63_527# a_159_527# 0.29fF
+C585 a_n1569_527# a_n1185_527# 0.05fF
+C586 a_1119_n309# a_1503_n309# 0.05fF
+C587 a_n225_n309# a_n513_n309# 0.06fF
+C588 a_n897_527# a_n513_527# 0.05fF
+C589 a_n1089_109# a_n801_109# 0.06fF
+C590 a_n513_n727# a_n801_n727# 0.06fF
+C591 a_351_n309# a_63_n309# 0.06fF
+C592 a_n1569_109# a_n1761_109# 0.11fF
+C593 a_n417_527# a_n417_109# 0.01fF
+C594 a_1791_109# a_1599_109# 0.11fF
+C595 a_n1089_n727# a_n1089_n309# 0.01fF
+C596 a_1215_109# a_1215_527# 0.01fF
+C597 a_n609_109# a_n801_109# 0.11fF
+C598 a_n225_n309# a_n417_n309# 0.11fF
+C599 a_351_527# a_735_527# 0.05fF
+C600 a_n129_n309# a_n321_n309# 0.11fF
+C601 a_n321_n727# a_n705_n727# 0.05fF
+C602 a_n993_527# a_n993_109# 0.01fF
+C603 a_n129_109# a_n513_109# 0.05fF
+C604 a_n609_109# a_n609_527# 0.01fF
+C605 a_n1761_527# a_n1569_527# 0.11fF
+C606 a_n1473_n309# a_n1857_n309# 0.05fF
+C607 a_n321_109# a_n33_109# 0.06fF
+C608 a_351_527# a_543_527# 0.11fF
+C609 a_1599_527# a_1599_109# 0.01fF
+C610 a_n1569_527# a_n1377_527# 0.11fF
+C611 a_1599_n727# a_1887_n727# 0.06fF
+C612 a_1599_109# a_1599_n309# 0.01fF
+C613 a_n1569_n309# a_n1185_n309# 0.05fF
+C614 a_n1377_n309# a_n993_n309# 0.05fF
+C615 a_543_n727# a_351_n727# 0.11fF
+C616 a_n1281_n309# a_n1089_n309# 0.11fF
+C617 a_543_n727# a_831_n727# 0.06fF
+C618 a_63_109# a_n321_109# 0.05fF
+C619 a_1311_527# a_1215_527# 0.29fF
+C620 a_159_n309# a_255_n309# 0.29fF
+C621 a_n1569_n727# a_n1377_n727# 0.11fF
+C622 a_n609_n309# a_n321_n309# 0.06fF
+C623 a_n705_527# a_n1089_527# 0.05fF
+C624 a_1023_109# a_1311_109# 0.06fF
+C625 a_n897_n309# a_n801_n309# 0.29fF
+C626 a_n417_n727# a_n705_n727# 0.06fF
+C627 a_831_n727# a_1215_n727# 0.05fF
+C628 a_n1665_n727# a_n1473_n727# 0.11fF
+C629 a_447_527# a_735_527# 0.06fF
+C630 a_831_527# a_927_527# 0.29fF
+C631 a_n1377_109# a_n1089_109# 0.06fF
+C632 a_n705_109# a_n801_109# 0.29fF
+C633 a_1215_n309# a_1215_n727# 0.01fF
+C634 a_831_109# a_639_109# 0.11fF
+C635 a_1599_109# a_1407_109# 0.11fF
+C636 a_n993_n727# a_n897_n727# 0.29fF
+C637 a_n1281_n727# a_n1377_n727# 0.29fF
+C638 a_n225_n727# a_n609_n727# 0.05fF
+C639 a_n1377_109# a_n1377_527# 0.01fF
+C640 a_n33_527# a_n33_109# 0.01fF
+C641 a_447_527# a_543_527# 0.29fF
+C642 a_1407_n309# a_1407_n727# 0.01fF
+C643 a_n1949_527# a_n1949_109# 0.01fF
+C644 a_n1473_109# a_n1473_527# 0.01fF
+C645 a_n321_n727# a_n609_n727# 0.06fF
+C646 a_n1761_527# a_n1857_527# 0.29fF
+C647 a_n129_n309# a_n33_n309# 0.29fF
+C648 a_159_n309# a_543_n309# 0.05fF
+C649 a_n897_n309# a_n993_n309# 0.29fF
+C650 a_n1377_109# a_n1665_109# 0.06fF
+C651 a_1791_n727# a_1695_n727# 0.29fF
+C652 a_n1089_n727# a_n897_n727# 0.11fF
+C653 a_543_109# a_735_109# 0.11fF
+C654 a_1695_527# a_1407_527# 0.06fF
+C655 a_n993_109# a_n1281_109# 0.06fF
+C656 a_n1569_109# a_n1857_109# 0.06fF
+C657 a_n1665_n309# a_n1857_n309# 0.11fF
+C658 a_735_n727# a_735_n309# 0.01fF
+C659 a_1119_527# a_1119_109# 0.01fF
+C660 a_n1665_n309# a_n1949_n309# 0.06fF
+C661 a_543_n727# a_159_n727# 0.05fF
+C662 a_n897_109# a_n1281_109# 0.05fF
+C663 a_543_n727# a_639_n727# 0.29fF
+C664 a_831_n309# a_543_n309# 0.06fF
+C665 a_n609_109# a_n417_109# 0.11fF
+C666 a_351_527# a_351_109# 0.01fF
+C667 a_351_n727# a_159_n727# 0.11fF
+C668 a_351_n727# a_639_n727# 0.06fF
+C669 a_1599_527# a_1311_527# 0.06fF
+C670 a_n1281_527# a_n1569_527# 0.06fF
+C671 a_831_n727# a_639_n727# 0.11fF
+C672 a_1887_n309# a_1887_109# 0.01fF
+C673 a_927_n309# a_639_n309# 0.06fF
+C674 a_n321_527# a_63_527# 0.05fF
+C675 a_n417_n309# a_n513_n309# 0.29fF
+C676 a_n897_527# a_n609_527# 0.06fF
+C677 a_1119_527# a_735_527# 0.05fF
+C678 a_1215_109# a_1407_109# 0.11fF
+C679 a_n1281_n727# a_n1569_n727# 0.06fF
+C680 a_n609_n727# a_n417_n727# 0.11fF
+C681 a_1023_109# a_1119_109# 0.29fF
+C682 a_831_109# a_1023_109# 0.11fF
+C683 a_927_109# a_543_109# 0.05fF
+C684 a_1023_109# a_1023_n309# 0.01fF
+C685 a_1311_527# a_1503_527# 0.11fF
+C686 a_n513_n727# a_n705_n727# 0.11fF
+C687 a_255_n727# a_255_n309# 0.01fF
+C688 a_1407_n309# a_1599_n309# 0.11fF
+C689 a_159_n309# a_159_109# 0.01fF
+C690 a_447_527# a_447_109# 0.01fF
+C691 a_1407_n727# a_1599_n727# 0.11fF
+C692 a_n1377_527# a_n1185_527# 0.11fF
+C693 a_n225_109# a_n513_109# 0.06fF
+C694 a_n1089_n727# a_n993_n727# 0.29fF
+C695 a_1599_527# a_1215_527# 0.05fF
+C696 a_927_109# a_1311_109# 0.05fF
+C697 a_n225_n727# a_n321_n727# 0.29fF
+C698 a_1695_527# a_1791_527# 0.29fF
+C699 a_n1473_n309# a_n1281_n309# 0.11fF
+C700 a_n609_n309# a_n609_n727# 0.01fF
+C701 a_n1665_n309# a_n1473_n309# 0.11fF
+C702 a_351_n309# a_255_n309# 0.29fF
+C703 a_351_n309# a_351_109# 0.01fF
+C704 a_n129_527# a_159_527# 0.06fF
+C705 a_1119_n309# a_1119_109# 0.01fF
+C706 a_1695_n727# a_1503_n727# 0.11fF
+C707 a_159_n309# a_n33_n309# 0.11fF
+C708 a_1119_n309# a_1023_n309# 0.29fF
+C709 a_n1185_n309# a_n1089_n309# 0.29fF
+C710 a_n1761_527# a_n1377_527# 0.05fF
+C711 a_447_109# a_639_109# 0.11fF
+C712 a_1503_527# a_1215_527# 0.06fF
+C713 a_n705_109# a_n417_109# 0.06fF
+C714 a_1407_n309# a_1407_109# 0.01fF
+C715 a_n1569_n727# a_n1949_n727# 0.05fF
+C716 a_n225_n727# a_n129_n727# 0.29fF
+C717 a_735_109# a_1119_109# 0.05fF
+C718 a_831_109# a_735_109# 0.29fF
+C719 a_n321_n727# a_n129_n727# 0.11fF
+C720 a_n129_109# a_159_109# 0.06fF
+C721 a_1887_n309# a_1503_n309# 0.05fF
+C722 a_1215_n309# a_1503_n309# 0.06fF
+C723 a_351_109# a_639_109# 0.06fF
+C724 a_n993_109# a_n1185_109# 0.11fF
+C725 a_n225_n727# a_n417_n727# 0.11fF
+C726 a_351_n309# a_543_n309# 0.11fF
+C727 a_1599_n727# a_1599_n309# 0.01fF
+C728 a_n321_n727# a_n417_n727# 0.29fF
+C729 a_735_109# a_735_527# 0.01fF
+C730 a_n609_n727# a_n513_n727# 0.29fF
+C731 a_n897_109# a_n1185_109# 0.06fF
+C732 a_n1377_109# a_n1377_n309# 0.01fF
+C733 a_n705_n309# a_n1089_n309# 0.05fF
+C734 a_1311_n309# a_1695_n309# 0.05fF
+C735 a_n33_527# a_159_527# 0.11fF
+C736 a_927_n309# a_1023_n309# 0.29fF
+C737 a_n129_n309# a_n129_n727# 0.01fF
+C738 a_927_n309# a_927_n727# 0.01fF
C739 a_1887_n727# w_n2087_n937# 0.12fF
C740 a_1791_n727# w_n2087_n937# 0.08fF
C741 a_1695_n727# w_n2087_n937# 0.06fF
@@ -3757,12 +3757,12 @@
+ out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8 out out out out avss1p8 out avss1p8
+ avss1p8 out out out out out avss1p8 avss1p8 out avss1p8 out avss1p8 out out avss1p8
+ avss1p8 avss1p8 avss1p8 avss1p8 out out out avss1p8 avss1p8 out sky130_fd_pr__nfet_01v8_lvt_CAF2P9
-C0 in out 10.03fF
-C1 iref in 0.11fF
-C2 in avdd1p8 2.17fF
+C0 out iref 22.08fF
+C1 out in 10.03fF
+C2 out avdd1p8 9.98fF
C3 iref m1_460_n1129# 2.64fF
-C4 iref out 22.08fF
-C5 avdd1p8 out 9.98fF
+C4 in iref 0.11fF
+C5 in avdd1p8 2.17fF
C6 iref avss1p8 18.70fF
C7 in avss1p8 -31.17fF
C8 out avss1p8 -28.37fF
@@ -3786,22 +3786,22 @@
+ VSUBS source_follower_buff_nmos_1/in source_follower_buff_nmos_1/m1_460_n1129# iref2
+ source_follower_buff_nmos_1/w_2049_850# source_follower_buff_nmos_1/w_2250_1287#
+ source_follower_buff_nmos_1/w_2250_355# source_follower_buff_nmos
-C0 avdd1p8 outn 0.18fF
-C1 inn avdd1p8 0.07fF
+C0 inn source_follower_buff_pmos_0/m1_957_828# 0.08fF
+C1 source_follower_buff_nmos_1/in avdd1p8 0.63fF
C2 source_follower_buff_nmos_1/in outp 0.11fF
-C3 source_follower_buff_nmos_1/w_2250_n1147# outp 0.09fF
-C4 avdd1p8 source_follower_buff_nmos_0/w_2049_850# 0.16fF
-C5 inp source_follower_buff_pmos_1/m1_957_828# 0.08fF
-C6 avdd1p8 inp 0.07fF
-C7 source_follower_buff_nmos_0/w_2250_1287# avdd1p8 0.18fF
-C8 avdd1p8 source_follower_buff_nmos_1/in 0.63fF
-C9 inp iref1 0.01fF
-C10 inp source_follower_buff_nmos_1/in -0.25fF
-C11 source_follower_buff_nmos_0/in outn 0.11fF
-C12 source_follower_buff_nmos_0/in inn -0.25fF
-C13 source_follower_buff_nmos_0/in avdd1p8 0.63fF
-C14 inn source_follower_buff_pmos_0/m1_957_828# 0.08fF
-C15 inn iref3 0.01fF
+C3 inp iref1 0.01fF
+C4 source_follower_buff_nmos_1/in inp -0.25fF
+C5 avdd1p8 source_follower_buff_nmos_0/w_2250_1287# 0.18fF
+C6 inn iref3 0.01fF
+C7 inp source_follower_buff_pmos_1/m1_957_828# 0.08fF
+C8 inn source_follower_buff_nmos_0/in -0.25fF
+C9 outn avdd1p8 0.18fF
+C10 avdd1p8 inp 0.07fF
+C11 avdd1p8 source_follower_buff_nmos_0/w_2049_850# 0.16fF
+C12 avdd1p8 inn 0.07fF
+C13 source_follower_buff_nmos_1/w_2250_n1147# outp 0.09fF
+C14 outn source_follower_buff_nmos_0/in 0.11fF
+C15 avdd1p8 source_follower_buff_nmos_0/in 0.63fF
C16 iref2 VSUBS 11.84fF
C17 source_follower_buff_nmos_1/in VSUBS -32.98fF
C18 outp VSUBS 0.56fF
@@ -3850,7 +3850,7 @@
+ res_amp_sync_v2_0/clkp res_amp_sync_v2_0/rst res_amp_sync_v2
Xres_amp_lin_prog_0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363#
+ delay_reg2 avdd1p8 inp res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA
-+ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_lin_prog_0/res_amp_lin_0/vctrl res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out
+ res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_prog_0/res_amp_lin_0/clk
+ res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 res_amp_lin_prog_0/outp_cap
+ avss1p8 res_amp_lin_prog_0/outn_cap res_amp_lin_prog_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b
@@ -3877,59 +3877,59 @@
+ source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# source_follower_buff_diff_0/source_follower_buff_nmos_1/in
+ source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# res_amp_lin_prog_0/outn_cap
+ source_follower_buff_diff
-C0 res_amp_lin_prog_0/outn_cap res_amp_sync_v2_0/rst 0.06fF
-C1 clkn res_amp_lin_prog_0/clk 0.07fF
-C2 res_amp_sync_v2_0/DFlipFlop_3/D avdd1p8 0.89fF
-C3 avdd1p8 iref0 -0.63fF
-C4 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in res_amp_lin_prog_0/clk 0.48fF
-C5 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# res_amp_lin_prog_0/clk 0.06fF
-C6 avdd1p8 delay_reg2 0.08fF
-C7 res_amp_sync_v2_0/DFlipFlop_3/Q res_amp_lin_prog_0/clk 0.25fF
-C8 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in res_amp_lin_prog_0/clk 0.48fF
-C9 res_amp_sync_v2_0/clkp avdd1p8 1.19fF
-C10 avdd1p8 clkn 0.74fF
-C11 avdd1p8 outp 0.31fF
-C12 delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.04fF
-C13 iref1 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# 0.10fF
-C14 res_amp_sync_v2_0/rst res_amp_lin_prog_0/outp_cap 0.13fF
-C15 avdd1p8 source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.39fF
-C16 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/nQ 0.20fF
-C17 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D res_amp_lin_prog_0/clk 0.47fF
-C18 res_amp_sync_v2_0/rst inp 0.09fF
-C19 avdd1p8 iref_reg1 0.05fF
-C20 iref4 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# 0.13fF
-C21 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D res_amp_lin_prog_0/clk 0.23fF
-C22 avdd1p8 res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.03fF
-C23 avdd1p8 res_amp_lin_prog_0/clk 9.77fF
-C24 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D res_amp_lin_prog_0/clk 0.20fF
-C25 avdd1p8 inp 0.46fF
-C26 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD 0.25fF
-C27 delay_reg1 avdd1p8 0.04fF
-C28 avdd1p8 iref_reg2 -0.57fF
-C29 avdd1p8 res_amp_sync_v2_0/rst 0.80fF
-C30 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# avdd1p8 0.02fF
-C31 res_amp_sync_v2_0/DFlipFlop_4/Q res_amp_lin_prog_0/clk 0.44fF
-C32 res_amp_sync_v2_0/DFlipFlop_4/D res_amp_lin_prog_0/clk 0.08fF
-C33 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out delay_reg2 0.03fF
-C34 outn source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# 0.15fF
-C35 inn inp 1.68fF
-C36 avdd1p8 res_amp_sync_v2_0/DFlipFlop_1/D 0.29fF
-C37 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# iref3 0.10fF
-C38 outn avdd1p8 0.30fF
-C39 res_amp_sync_v2_0/clkp clkn 0.06fF
-C40 res_amp_sync_v2_0/DFlipFlop_3/D res_amp_lin_prog_0/clk 0.07fF
-C41 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D res_amp_lin_prog_0/clk 0.47fF
-C42 res_amp_lin_prog_0/res_amp_lin_0/vctrl iref0 -0.03fF
-C43 res_amp_sync_v2_0/rst inn 0.09fF
-C44 iref0 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.02fF
-C45 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD res_amp_lin_prog_0/clk 0.28fF
-C46 avdd1p8 source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.40fF
-C47 avdd1p8 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# 1.10fF
-C48 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/nQ 0.22fF
-C49 avdd1p8 inn 0.46fF
-C50 avdd1p8 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# 0.02fF
-C51 iref2 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# 0.12fF
-C52 delay_reg1 delay_reg2 0.23fF
+C0 avdd1p8 outn 0.30fF
+C1 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D res_amp_lin_prog_0/clk 0.23fF
+C2 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in res_amp_lin_prog_0/clk 0.48fF
+C3 inp res_amp_sync_v2_0/rst 0.09fF
+C4 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# iref4 0.13fF
+C5 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/D 0.07fF
+C6 avdd1p8 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# 1.10fF
+C7 avdd1p8 iref0 -0.63fF
+C8 avdd1p8 res_amp_sync_v2_0/DFlipFlop_3/D 0.89fF
+C9 avdd1p8 res_amp_sync_v2_0/clkp 1.19fF
+C10 avdd1p8 source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.40fF
+C11 avdd1p8 inn 0.46fF
+C12 avdd1p8 delay_reg1 0.04fF
+C13 delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.04fF
+C14 avdd1p8 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# 0.02fF
+C15 avdd1p8 outp 0.31fF
+C16 avdd1p8 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# 0.02fF
+C17 avdd1p8 res_amp_lin_prog_0/clk 9.77fF
+C18 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D res_amp_lin_prog_0/clk 0.47fF
+C19 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out delay_reg2 0.03fF
+C20 iref3 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# 0.10fF
+C21 res_amp_sync_v2_0/clkp clkn 0.06fF
+C22 iref2 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# 0.12fF
+C23 avdd1p8 iref_reg1 0.05fF
+C24 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# res_amp_lin_prog_0/clk 0.06fF
+C25 iref0 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.02fF
+C26 res_amp_sync_v2_0/DFlipFlop_3/nQ res_amp_lin_prog_0/clk 0.20fF
+C27 res_amp_sync_v2_0/rst inn 0.09fF
+C28 res_amp_sync_v2_0/DFlipFlop_3/Q res_amp_lin_prog_0/clk 0.25fF
+C29 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D 0.47fF
+C30 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D 0.20fF
+C31 res_amp_lin_prog_0/clk clkn 0.07fF
+C32 avdd1p8 source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.39fF
+C33 avdd1p8 res_amp_sync_v2_0/DFlipFlop_1/D 0.29fF
+C34 iref0 res_amp_lin_prog_0/res_amp_lin_0/vctrl -0.03fF
+C35 avdd1p8 clkn 0.74fF
+C36 res_amp_sync_v2_0/rst res_amp_lin_prog_0/outn_cap 0.06fF
+C37 res_amp_sync_v2_0/rst res_amp_lin_prog_0/outp_cap 0.13fF
+C38 avdd1p8 res_amp_sync_v2_0/rst 0.80fF
+C39 inp inn 1.68fF
+C40 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/nQ 0.22fF
+C41 iref1 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# 0.10fF
+C42 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in 0.48fF
+C43 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD res_amp_lin_prog_0/clk 0.25fF
+C44 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD res_amp_lin_prog_0/clk 0.28fF
+C45 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/D 0.08fF
+C46 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/Q 0.44fF
+C47 delay_reg1 delay_reg2 0.23fF
+C48 inp avdd1p8 0.46fF
+C49 iref_reg2 avdd1p8 -0.57fF
+C50 avdd1p8 res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.03fF
+C51 outn source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# 0.15fF
+C52 avdd1p8 delay_reg2 0.08fF
C53 iref2 avss1p8 12.17fF
C54 source_follower_buff_diff_0/source_follower_buff_nmos_1/in avss1p8 -32.88fF
C55 outp avss1p8 -1.74fF
@@ -3961,51 +3961,51 @@
C81 inn avss1p8 -6.68fF
C82 res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
C83 res_amp_lin_prog_0/outn_cap avss1p8 1.00fF
-C84 res_amp_lin_prog_0/res_amp_lin_0/clk avss1p8 4.30fF
-C85 res_amp_lin_prog_0/inverter_min_x4_0/out avss1p8 4.87fF
+C84 res_amp_lin_prog_0/inverter_min_x4_0/out avss1p8 4.87fF
+C85 res_amp_lin_prog_0/res_amp_lin_0/clk avss1p8 4.30fF
C86 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
-C87 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
-C88 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
-C89 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
-C90 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
-C91 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
-C92 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
-C93 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
-C94 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
-C95 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
-C96 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
-C97 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.04fF
-C98 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
-C99 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
-C100 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
-C101 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
-C102 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
-C103 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
-C104 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
-C105 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
-C106 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C87 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C88 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C89 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C90 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C91 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C92 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C93 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C94 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C95 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C96 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C97 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C98 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.04fF
+C99 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C100 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C101 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C102 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C103 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C104 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C105 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C106 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
C107 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
-C108 delay_reg0 avss1p8 2.90fF
-C109 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C108 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C109 delay_reg0 avss1p8 2.90fF
C110 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
-C111 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
-C112 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C111 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C112 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
C113 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
-C114 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
-C115 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
-C116 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
-C117 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
-C118 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
-C119 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C114 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C115 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C116 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C117 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C118 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C119 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
C120 delay_reg1 avss1p8 3.97fF
C121 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
-C122 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
-C123 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
-C124 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C122 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C123 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C124 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
C125 delay_reg2 avss1p8 11.33fF
-C126 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.04fF
-C127 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
-C128 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C126 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C127 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C128 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.04fF
C129 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
C130 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
C131 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
@@ -4014,272 +4014,67 @@
C134 res_amp_sync_v2_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
C135 res_amp_lin_prog_0/clk avss1p8 -6.90fF
C136 res_amp_sync_v2_0/inverter_min_x4_4/out avss1p8 5.85fF
-C137 res_amp_sync_v2_0/nand_logic_1/out avss1p8 1.70fF
-C138 res_amp_sync_v2_0/rst avss1p8 -3.03fF
-C139 res_amp_sync_v2_0/DFlipFlop_4/nQ avss1p8 0.48fF
-C140 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 -2.08fF
-C141 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# avss1p8 0.57fF
-C142 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD avss1p8 0.57fF
-C143 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D avss1p8 -1.73fF
-C144 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C137 res_amp_sync_v2_0/rst avss1p8 -3.03fF
+C138 res_amp_sync_v2_0/nand_logic_1/out avss1p8 1.70fF
+C139 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 -2.08fF
+C140 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C141 res_amp_sync_v2_0/DFlipFlop_4/nQ avss1p8 0.48fF
+C142 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D avss1p8 -1.73fF
+C143 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C144 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD avss1p8 0.57fF
C145 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
C146 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D avss1p8 0.96fF
C147 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
C148 res_amp_sync_v2_0/DFlipFlop_4/D avss1p8 1.83fF
C149 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD avss1p8 1.14fF
C150 res_amp_sync_v2_0/nand_logic_0/out avss1p8 1.20fF
-C151 res_amp_sync_v2_0/DFlipFlop_0/Q avss1p8 -4.73fF
-C152 res_amp_sync_v2_0/DFlipFlop_3/nQ avss1p8 0.48fF
-C153 res_amp_sync_v2_0/DFlipFlop_3/Q avss1p8 -2.94fF
-C154 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# avss1p8 0.57fF
-C155 clkn avss1p8 -7.50fF
-C156 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD avss1p8 0.57fF
-C157 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D avss1p8 -1.73fF
-C158 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# avss1p8 0.57fF
-C159 res_amp_sync_v2_0/clkp avss1p8 -28.00fF
-C160 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
-C161 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D avss1p8 0.96fF
-C162 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
-C163 res_amp_sync_v2_0/DFlipFlop_3/D avss1p8 1.33fF
+C151 res_amp_sync_v2_0/DFlipFlop_3/Q avss1p8 -2.94fF
+C152 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C153 clkn avss1p8 -7.50fF
+C154 res_amp_sync_v2_0/DFlipFlop_3/nQ avss1p8 0.48fF
+C155 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D avss1p8 -1.73fF
+C156 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C157 res_amp_sync_v2_0/clkp avss1p8 -28.00fF
+C158 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD avss1p8 0.57fF
+C159 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C160 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D avss1p8 0.96fF
+C161 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C162 res_amp_sync_v2_0/DFlipFlop_3/D avss1p8 1.33fF
+C163 avdd1p8 avss1p8 415.30fF
C164 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD avss1p8 1.14fF
-C165 avdd1p8 avss1p8 415.30fF
-C166 res_amp_sync_v2_0/DFlipFlop_2/nQ avss1p8 0.48fF
-C167 res_amp_sync_v2_0/DFlipFlop_2/Q avss1p8 -1.08fF
-C168 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# avss1p8 0.57fF
-C169 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD avss1p8 0.57fF
-C170 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D avss1p8 -1.73fF
-C171 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# avss1p8 0.57fF
-C172 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
-C173 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D avss1p8 0.96fF
-C174 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
-C175 res_amp_sync_v2_0/DFlipFlop_2/D avss1p8 -0.38fF
-C176 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD avss1p8 1.14fF
+C165 res_amp_sync_v2_0/DFlipFlop_2/Q avss1p8 -1.08fF
+C166 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C167 res_amp_sync_v2_0/DFlipFlop_2/nQ avss1p8 0.48fF
+C168 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D avss1p8 -1.73fF
+C169 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C170 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD avss1p8 0.57fF
+C171 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C172 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D avss1p8 0.96fF
+C173 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C174 res_amp_sync_v2_0/DFlipFlop_2/D avss1p8 -0.38fF
+C175 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD avss1p8 1.14fF
+C176 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# avss1p8 0.57fF
C177 res_amp_sync_v2_0/DFlipFlop_1/nQ avss1p8 0.48fF
-C178 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# avss1p8 0.57fF
-C179 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD avss1p8 0.57fF
-C180 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D avss1p8 -1.73fF
-C181 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# avss1p8 0.57fF
-C182 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
-C183 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D avss1p8 0.96fF
-C184 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
-C185 res_amp_sync_v2_0/DFlipFlop_1/D avss1p8 -1.02fF
-C186 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD avss1p8 1.14fF
-C187 res_amp_sync_v2_0/DFlipFlop_0/nQ avss1p8 0.48fF
-C188 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# avss1p8 0.57fF
-C189 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD avss1p8 0.57fF
-C190 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D avss1p8 -1.73fF
-C191 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C178 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D avss1p8 -1.73fF
+C179 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C180 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD avss1p8 0.57fF
+C181 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C182 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D avss1p8 0.96fF
+C183 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C184 res_amp_sync_v2_0/DFlipFlop_1/D avss1p8 -1.02fF
+C185 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD avss1p8 1.14fF
+C186 res_amp_sync_v2_0/DFlipFlop_0/Q avss1p8 -4.73fF
+C187 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C188 res_amp_sync_v2_0/DFlipFlop_0/nQ avss1p8 0.48fF
+C189 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D avss1p8 -1.73fF
+C190 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C191 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD avss1p8 0.57fF
C192 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
C193 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D avss1p8 0.96fF
C194 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
C195 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD avss1p8 1.14fF
.ends
-.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
-+ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
-+ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
-+ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
-+ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
-X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-C0 m3_7988_n13200# m3_2669_n13200# 2.73fF
-C1 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
-C2 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
-C3 m3_2669_n7900# m3_2669_n13200# 3.28fF
-C4 c1_n13188_n13100# m3_7988_n13200# 60.75fF
-C5 m3_n13288_2700# m3_n13288_n2600# 3.28fF
-C6 c1_n13188_n13100# m3_2669_n7900# 58.86fF
-C7 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
-C8 c1_n13188_n13100# m3_n13288_2700# 58.61fF
-C9 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
-C10 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
-C11 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
-C12 m3_7988_n7900# m3_7988_n2600# 3.39fF
-C13 m3_2669_n7900# m3_n2650_n7900# 2.73fF
-C14 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
-C15 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
-C16 m3_n2650_2700# m3_n7969_2700# 2.73fF
-C17 m3_7988_n7900# c1_n13188_n13100# 61.01fF
-C18 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
-C19 c1_n13188_n13100# m3_7988_8000# 60.75fF
-C20 m3_n13288_8000# m3_n7969_8000# 2.73fF
-C21 c1_n13188_n13100# m3_2669_8000# 58.61fF
-C22 m3_n7969_2700# m3_n7969_8000# 3.28fF
-C23 m3_n2650_8000# m3_2669_8000# 2.73fF
-C24 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
-C25 m3_7988_n7900# m3_7988_n13200# 3.39fF
-C26 m3_2669_8000# m3_2669_2700# 3.28fF
-C27 m3_7988_n7900# m3_2669_n7900# 2.73fF
-C28 m3_2669_n2600# m3_7988_n2600# 2.73fF
-C29 m3_n2650_n13200# m3_2669_n13200# 2.73fF
-C30 m3_7988_2700# m3_7988_n2600# 3.39fF
-C31 m3_n2650_n2600# m3_n2650_n7900# 3.28fF
-C32 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
-C33 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
-C34 c1_n13188_n13100# m3_n13288_8000# 58.36fF
-C35 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
-C36 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
-C37 c1_n13188_n13100# m3_2669_n2600# 58.86fF
-C38 c1_n13188_n13100# m3_n7969_2700# 58.86fF
-C39 c1_n13188_n13100# m3_7988_2700# 61.01fF
-C40 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
-C41 m3_2669_n2600# m3_2669_2700# 3.28fF
-C42 c1_n13188_n13100# m3_n2650_2700# 58.86fF
-C43 m3_7988_2700# m3_2669_2700# 2.73fF
-C44 m3_n2650_8000# m3_n2650_2700# 3.28fF
-C45 m3_n13288_2700# m3_n13288_8000# 3.28fF
-C46 m3_n2650_2700# m3_2669_2700# 2.73fF
-C47 m3_2669_n2600# m3_2669_n7900# 3.28fF
-C48 m3_2669_8000# m3_7988_8000# 2.73fF
-C49 m3_n13288_2700# m3_n7969_2700# 2.73fF
-C50 m3_n7969_n2600# m3_n7969_2700# 3.28fF
-C51 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
-C52 c1_n13188_n13100# m3_n7969_8000# 58.61fF
-C53 m3_n2650_8000# m3_n7969_8000# 2.73fF
-C54 c1_n13188_n13100# m3_7988_n2600# 61.01fF
-C55 c1_n13188_n13100# m3_2669_n13200# 58.61fF
-C56 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
-C57 m3_7988_2700# m3_7988_8000# 3.39fF
-C58 m3_n2650_n2600# m3_2669_n2600# 2.73fF
-C59 c1_n13188_n13100# m3_n2650_8000# 58.61fF
-C60 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
-C61 c1_n13188_n13100# m3_2669_2700# 58.86fF
-C62 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
-C63 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
-C64 m3_n2650_n2600# m3_n2650_2700# 3.28fF
-C65 c1_n13188_n13100# VSUBS 2.51fF
-C66 m3_7988_n13200# VSUBS 12.57fF
-C67 m3_2669_n13200# VSUBS 12.37fF
-C68 m3_n2650_n13200# VSUBS 12.37fF
-C69 m3_n7969_n13200# VSUBS 12.37fF
-C70 m3_n13288_n13200# VSUBS 12.37fF
-C71 m3_7988_n7900# VSUBS 12.57fF
-C72 m3_2669_n7900# VSUBS 12.37fF
-C73 m3_n2650_n7900# VSUBS 12.37fF
-C74 m3_n7969_n7900# VSUBS 12.37fF
-C75 m3_n13288_n7900# VSUBS 12.37fF
-C76 m3_7988_n2600# VSUBS 12.57fF
-C77 m3_2669_n2600# VSUBS 12.37fF
-C78 m3_n2650_n2600# VSUBS 12.37fF
-C79 m3_n7969_n2600# VSUBS 12.37fF
-C80 m3_n13288_n2600# VSUBS 12.37fF
-C81 m3_7988_2700# VSUBS 12.57fF
-C82 m3_2669_2700# VSUBS 12.37fF
-C83 m3_n2650_2700# VSUBS 12.37fF
-C84 m3_n7969_2700# VSUBS 12.37fF
-C85 m3_n13288_2700# VSUBS 12.37fF
-C86 m3_7988_8000# VSUBS 12.57fF
-C87 m3_2669_8000# VSUBS 12.37fF
-C88 m3_n2650_8000# VSUBS 12.37fF
-C89 m3_n7969_8000# VSUBS 12.37fF
-C90 m3_n13288_8000# VSUBS 12.37fF
-.ends
-
-.subckt cap1_loop_filter VSUBS in out
-Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
-+ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
-C0 in out 2.17fF
-C1 in VSUBS -10.03fF
-C2 out VSUBS 62.40fF
-.ends
-
-.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
-+ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
-+ m3_n6469_n6400#
-X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
-C1 m3_2169_n6400# m3_n2150_2200# 1.75fF
-C2 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
-C3 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
-C4 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
-C5 m3_n6469_2200# c1_n6369_n6300# 38.10fF
-C6 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
-C7 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
-C8 m3_2169_n6400# c1_2269_n6300# 121.67fF
-C9 m3_n2150_n2100# m3_2169_n6400# 1.75fF
-C10 m3_n2150_n2100# m3_n2150_2200# 2.63fF
-C11 c1_n2050_n6300# m3_n2150_2200# 38.10fF
-C12 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
-C13 m3_n2150_n6400# m3_2169_n6400# 1.75fF
-C14 m3_n6469_2200# m3_n2150_2200# 1.75fF
-C15 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
-C16 m3_n6469_2200# m3_n6469_n2100# 2.63fF
-C17 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
-C18 c1_n2050_n6300# c1_2269_n6300# 1.99fF
-C19 c1_2269_n6300# VSUBS 0.16fF
-C20 c1_n2050_n6300# VSUBS 0.16fF
-C21 c1_n6369_n6300# VSUBS 0.16fF
-C22 m3_n2150_n6400# VSUBS 8.68fF
-C23 m3_n6469_n6400# VSUBS 8.68fF
-C24 m3_n2150_n2100# VSUBS 8.68fF
-C25 m3_n6469_n2100# VSUBS 8.68fF
-C26 m3_2169_n6400# VSUBS 26.86fF
-C27 m3_n2150_2200# VSUBS 8.68fF
-C28 m3_n6469_2200# VSUBS 8.68fF
-.ends
-
-.subckt cap2_loop_filter VSUBS in out
-Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
-C0 out in 8.08fF
-C1 in VSUBS -16.59fF
-C2 out VSUBS 13.00fF
-.ends
-
-.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
-X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
-C0 a_n573_n2724# w_n739_n2890# 1.98fF
-C1 a_n573_2292# w_n739_n2890# 1.98fF
-.ends
-
-.subckt res_loop_filter vss out in
-Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
-C0 out vss 3.87fF
-C1 in vss 3.02fF
-.ends
-
-.subckt loop_filter vc_pex in vss
-Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
-Xcap2_loop_filter_0 vss in vss cap2_loop_filter
-Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
-Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
-Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
-C0 in vc_pex 0.18fF
-C1 vc_pex vss -38.13fF
-C2 res_loop_filter_2/out vss 8.49fF
-C3 in vss -18.79fF
-.ends
-
.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
+ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
+ a_n1403_n486# a_2261_n486# a_n1861_n486#
@@ -4293,17 +4088,17 @@
X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
-C0 w_n2457_n634# a_887_n486# 0.02fF
-C1 w_n2457_n634# a_n29_n486# 0.02fF
-C2 w_n2457_n634# a_2261_n486# 0.02fF
-C3 a_1803_n486# w_n2457_n634# 0.02fF
-C4 w_n2457_n634# a_n1861_n486# 0.02fF
-C5 w_n2457_n634# a_n945_n486# 0.02fF
-C6 w_n2457_n634# a_429_n486# 0.02fF
-C7 w_n2457_n634# a_n487_n486# 0.02fF
+C0 w_n2457_n634# a_1803_n486# 0.02fF
+C1 w_n2457_n634# a_n487_n486# 0.02fF
+C2 w_n2457_n634# a_n29_n486# 0.02fF
+C3 w_n2457_n634# a_n945_n486# 0.02fF
+C4 w_n2457_n634# a_1345_n486# 0.02fF
+C5 w_n2457_n634# a_n1403_n486# 0.02fF
+C6 w_n2457_n634# a_2261_n486# 0.02fF
+C7 w_n2457_n634# a_429_n486# 0.02fF
C8 w_n2457_n634# a_n2319_n486# 0.02fF
-C9 w_n2457_n634# a_n1403_n486# 0.02fF
-C10 w_n2457_n634# a_1345_n486# 0.02fF
+C9 w_n2457_n634# a_887_n486# 0.02fF
+C10 w_n2457_n634# a_n1861_n486# 0.02fF
C11 a_2261_n486# VSUBS 0.03fF
C12 a_1803_n486# VSUBS 0.03fF
C13 a_1345_n486# VSUBS 0.03fF
@@ -4349,100 +4144,100 @@
X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
-C0 a_n1229_n75# a_n1041_n75# 0.08fF
-C1 a_n273_n75# a_n561_n75# 0.05fF
-C2 a_591_n75# a_303_n75# 0.05fF
-C3 a_399_n75# a_495_n75# 0.22fF
-C4 a_n945_n75# a_n657_n75# 0.05fF
-C5 a_n273_n75# a_n369_n75# 0.22fF
-C6 a_n849_n75# a_n753_n75# 0.22fF
-C7 a_111_n75# a_303_n75# 0.08fF
-C8 a_879_n75# a_783_n75# 0.22fF
-C9 a_n177_n75# a_n81_n75# 0.22fF
-C10 a_n657_n75# a_n849_n75# 0.08fF
-C11 a_495_n75# a_591_n75# 0.22fF
-C12 a_n561_n75# a_n369_n75# 0.08fF
-C13 a_783_n75# a_687_n75# 0.22fF
-C14 a_n1137_n75# a_n1041_n75# 0.22fF
-C15 a_n945_n75# a_n1229_n75# 0.05fF
-C16 a_111_n75# a_495_n75# 0.03fF
-C17 a_783_n75# a_399_n75# 0.03fF
-C18 a_975_n75# a_1167_n75# 0.08fF
-C19 a_15_n75# a_207_n75# 0.08fF
-C20 a_n177_n75# a_111_n75# 0.05fF
-C21 a_n849_n75# a_n1229_n75# 0.03fF
-C22 a_n273_n75# a_n177_n75# 0.22fF
-C23 a_783_n75# a_591_n75# 0.08fF
-C24 a_n945_n75# a_n561_n75# 0.03fF
-C25 a_1167_n75# a_1071_n75# 0.22fF
+C0 a_n465_n75# a_n273_n75# 0.08fF
+C1 a_783_n75# a_399_n75# 0.03fF
+C2 a_879_n75# a_687_n75# 0.08fF
+C3 a_303_n75# a_111_n75# 0.08fF
+C4 a_591_n75# a_399_n75# 0.08fF
+C5 a_n1229_n75# a_n1041_n75# 0.08fF
+C6 a_15_n75# a_399_n75# 0.03fF
+C7 a_879_n75# a_495_n75# 0.03fF
+C8 a_303_n75# a_n81_n75# 0.03fF
+C9 a_15_n75# a_n369_n75# 0.03fF
+C10 a_n561_n75# a_n465_n75# 0.22fF
+C11 a_975_n75# a_687_n75# 0.05fF
+C12 a_n657_n75# a_n273_n75# 0.03fF
+C13 a_207_n75# a_591_n75# 0.03fF
+C14 a_15_n75# a_207_n75# 0.08fF
+C15 a_1071_n75# a_687_n75# 0.03fF
+C16 a_783_n75# a_1167_n75# 0.03fF
+C17 a_303_n75# a_687_n75# 0.03fF
+C18 a_n657_n75# a_n561_n75# 0.22fF
+C19 a_n849_n75# a_n1229_n75# 0.03fF
+C20 a_303_n75# a_495_n75# 0.08fF
+C21 a_n849_n75# a_n561_n75# 0.05fF
+C22 a_783_n75# a_879_n75# 0.22fF
+C23 a_111_n75# a_n81_n75# 0.08fF
+C24 a_n1137_n75# a_n753_n75# 0.03fF
+C25 a_879_n75# a_591_n75# 0.05fF
C26 a_n945_n75# a_n1137_n75# 0.08fF
-C27 a_n945_n75# a_n1041_n75# 0.22fF
-C28 a_15_n75# a_399_n75# 0.03fF
-C29 a_15_n75# a_n81_n75# 0.22fF
-C30 a_975_n75# a_1071_n75# 0.22fF
-C31 a_n177_n75# a_n561_n75# 0.03fF
-C32 a_n753_n75# a_n465_n75# 0.05fF
-C33 a_n177_n75# a_n369_n75# 0.08fF
-C34 a_n849_n75# a_n561_n75# 0.05fF
-C35 a_n1137_n75# a_n849_n75# 0.05fF
-C36 a_n849_n75# a_n1041_n75# 0.08fF
-C37 a_495_n75# a_303_n75# 0.08fF
-C38 a_879_n75# a_687_n75# 0.08fF
-C39 a_n81_n75# a_n465_n75# 0.03fF
-C40 a_n657_n75# a_n465_n75# 0.08fF
-C41 a_399_n75# a_207_n75# 0.08fF
-C42 a_n81_n75# a_207_n75# 0.05fF
-C43 a_15_n75# a_111_n75# 0.22fF
-C44 a_1167_n75# a_783_n75# 0.03fF
-C45 a_n657_n75# a_n753_n75# 0.22fF
-C46 a_n273_n75# a_15_n75# 0.05fF
-C47 a_207_n75# a_591_n75# 0.03fF
-C48 a_399_n75# a_687_n75# 0.05fF
-C49 a_879_n75# a_591_n75# 0.05fF
-C50 a_975_n75# a_783_n75# 0.08fF
-C51 a_n945_n75# a_n849_n75# 0.22fF
-C52 a_111_n75# a_207_n75# 0.22fF
-C53 a_687_n75# a_591_n75# 0.22fF
-C54 a_n273_n75# a_n465_n75# 0.08fF
-C55 a_15_n75# a_n369_n75# 0.03fF
-C56 a_1071_n75# a_783_n75# 0.05fF
-C57 a_399_n75# a_591_n75# 0.08fF
-C58 a_783_n75# a_495_n75# 0.05fF
-C59 a_n561_n75# a_n465_n75# 0.22fF
-C60 a_n465_n75# a_n369_n75# 0.22fF
-C61 a_111_n75# a_399_n75# 0.05fF
-C62 a_111_n75# a_n81_n75# 0.08fF
-C63 a_15_n75# a_303_n75# 0.05fF
-C64 a_n273_n75# a_n81_n75# 0.08fF
-C65 a_879_n75# a_1167_n75# 0.05fF
-C66 a_n657_n75# a_n273_n75# 0.03fF
-C67 a_n561_n75# a_n753_n75# 0.08fF
-C68 a_975_n75# a_879_n75# 0.22fF
-C69 a_n1137_n75# a_n753_n75# 0.03fF
-C70 a_n753_n75# a_n369_n75# 0.03fF
-C71 a_n753_n75# a_n1041_n75# 0.05fF
-C72 a_207_n75# a_303_n75# 0.22fF
-C73 a_n657_n75# a_n561_n75# 0.22fF
-C74 a_n177_n75# a_15_n75# 0.08fF
-C75 a_975_n75# a_687_n75# 0.05fF
-C76 a_n657_n75# a_n369_n75# 0.05fF
-C77 a_n81_n75# a_n369_n75# 0.05fF
-C78 a_n657_n75# a_n1041_n75# 0.03fF
-C79 a_n273_n75# a_111_n75# 0.03fF
-C80 a_687_n75# a_303_n75# 0.03fF
-C81 a_879_n75# a_1071_n75# 0.08fF
-C82 a_207_n75# a_495_n75# 0.05fF
-C83 a_879_n75# a_495_n75# 0.03fF
-C84 a_n177_n75# a_n465_n75# 0.05fF
-C85 a_399_n75# a_303_n75# 0.22fF
-C86 a_n81_n75# a_303_n75# 0.03fF
-C87 a_n849_n75# a_n465_n75# 0.03fF
-C88 a_n177_n75# a_207_n75# 0.03fF
-C89 a_1071_n75# a_687_n75# 0.03fF
-C90 a_n945_n75# a_n753_n75# 0.08fF
-C91 a_687_n75# a_495_n75# 0.08fF
-C92 a_n1137_n75# a_n1229_n75# 0.22fF
-C93 a_975_n75# a_591_n75# 0.03fF
+C27 a_783_n75# a_975_n75# 0.08fF
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+C29 a_975_n75# a_591_n75# 0.03fF
+C30 a_n945_n75# a_n753_n75# 0.08fF
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+C33 a_n369_n75# a_n465_n75# 0.22fF
+C34 a_n177_n75# a_n81_n75# 0.22fF
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+C36 a_303_n75# a_591_n75# 0.05fF
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C94 a_1167_n75# w_n1367_n285# 0.10fF
C95 a_1071_n75# w_n1367_n285# 0.07fF
C96 a_975_n75# w_n1367_n285# 0.06fF
@@ -4496,81 +4291,81 @@
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X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
-C0 a_255_n75# a_n33_n75# 0.05fF
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-C1 a_329_n44# a_n29_n44# 0.04fF
-C2 a_n745_n44# a_n387_n44# 0.04fF
-C3 a_n1461_n44# a_n1819_n44# 0.04fF
-C4 a_n745_n44# a_n1103_n44# 0.04fF
-C5 a_n387_n44# a_n29_n44# 0.04fF
-C6 a_1403_n44# a_1761_n44# 0.04fF
-C7 a_n1461_n44# a_n1103_n44# 0.04fF
-C8 a_1045_n44# a_1403_n44# 0.04fF
-C9 a_329_n44# a_687_n44# 0.04fF
+C0 a_687_n44# a_329_n44# 0.04fF
+C1 a_n387_n44# a_n29_n44# 0.04fF
+C2 a_n387_n44# a_n745_n44# 0.04fF
+C3 a_n1103_n44# a_n745_n44# 0.04fF
+C4 a_1045_n44# a_1403_n44# 0.04fF
+C5 a_329_n44# a_n29_n44# 0.04fF
+C6 a_n1461_n44# a_n1103_n44# 0.04fF
+C7 a_n1461_n44# a_n1819_n44# 0.04fF
+C8 a_1045_n44# a_687_n44# 0.04fF
+C9 a_1761_n44# a_1403_n44# 0.04fF
C10 a_1761_n44# w_n1957_n254# 0.04fF
C11 a_1403_n44# w_n1957_n254# 0.04fF
C12 a_1045_n44# w_n1957_n254# 0.04fF
@@ -4788,104 +4583,104 @@
X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_n81_n150# a_n177_n150# 0.43fF
-C1 a_n561_n150# a_n945_n150# 0.07fF
-C2 a_n1229_n150# a_n945_n150# 0.10fF
-C3 a_1071_n150# w_n1367_n369# 0.07fF
-C4 a_n657_n150# a_n465_n150# 0.16fF
-C5 a_111_n150# a_n177_n150# 0.10fF
-C6 a_15_n150# a_207_n150# 0.16fF
-C7 a_495_n150# a_591_n150# 0.43fF
-C8 a_15_n150# a_n369_n150# 0.07fF
-C9 a_n465_n150# a_n369_n150# 0.43fF
-C10 a_399_n150# a_687_n150# 0.10fF
-C11 a_n81_n150# a_n273_n150# 0.16fF
-C12 a_495_n150# a_303_n150# 0.16fF
-C13 a_n753_n150# a_n1137_n150# 0.07fF
-C14 a_111_n150# a_399_n150# 0.10fF
-C15 a_1071_n150# a_975_n150# 0.43fF
-C16 a_111_n150# a_n273_n150# 0.07fF
-C17 a_207_n150# a_n177_n150# 0.07fF
-C18 a_n657_n150# a_n753_n150# 0.43fF
-C19 a_n369_n150# a_n177_n150# 0.16fF
-C20 a_879_n150# w_n1367_n369# 0.04fF
-C21 a_n1137_n150# a_n849_n150# 0.10fF
-C22 a_591_n150# a_687_n150# 0.43fF
-C23 a_n753_n150# a_n369_n150# 0.07fF
-C24 a_n1041_n150# a_n753_n150# 0.10fF
-C25 a_n657_n150# a_n273_n150# 0.07fF
-C26 a_399_n150# a_207_n150# 0.16fF
-C27 a_1167_n150# w_n1367_n369# 0.14fF
-C28 a_n81_n150# a_303_n150# 0.07fF
-C29 a_15_n150# a_n177_n150# 0.16fF
-C30 a_n657_n150# a_n849_n150# 0.16fF
-C31 a_n465_n150# a_n177_n150# 0.10fF
-C32 a_879_n150# a_591_n150# 0.10fF
-C33 a_303_n150# a_687_n150# 0.07fF
-C34 a_687_n150# a_975_n150# 0.10fF
-C35 a_n273_n150# a_n369_n150# 0.43fF
-C36 a_783_n150# a_399_n150# 0.07fF
-C37 a_111_n150# a_303_n150# 0.16fF
-C38 a_n465_n150# a_n753_n150# 0.10fF
-C39 a_n1041_n150# a_n849_n150# 0.16fF
-C40 a_879_n150# a_975_n150# 0.43fF
-C41 a_n1229_n150# a_n1137_n150# 0.43fF
-C42 a_399_n150# a_15_n150# 0.07fF
-C43 a_n1137_n150# a_n945_n150# 0.16fF
-C44 a_n273_n150# a_15_n150# 0.10fF
-C45 a_n465_n150# a_n273_n150# 0.16fF
-C46 a_207_n150# a_591_n150# 0.07fF
-C47 a_1167_n150# a_975_n150# 0.16fF
-C48 a_n657_n150# a_n561_n150# 0.43fF
-C49 a_n465_n150# a_n849_n150# 0.07fF
-C50 a_495_n150# a_687_n150# 0.16fF
-C51 a_n657_n150# a_n945_n150# 0.10fF
-C52 a_1071_n150# a_687_n150# 0.07fF
-C53 a_303_n150# a_207_n150# 0.43fF
-C54 a_783_n150# a_591_n150# 0.16fF
-C55 a_495_n150# a_111_n150# 0.07fF
-C56 a_n561_n150# a_n369_n150# 0.16fF
-C57 a_n1229_n150# a_n1041_n150# 0.16fF
-C58 a_879_n150# a_495_n150# 0.07fF
-C59 a_n1041_n150# a_n945_n150# 0.43fF
-C60 a_879_n150# a_1071_n150# 0.16fF
-C61 a_n273_n150# a_n177_n150# 0.43fF
-C62 a_783_n150# a_975_n150# 0.16fF
-C63 a_n561_n150# a_n465_n150# 0.43fF
-C64 a_303_n150# a_15_n150# 0.10fF
-C65 a_1167_n150# a_1071_n150# 0.43fF
-C66 a_n753_n150# a_n849_n150# 0.43fF
-C67 a_495_n150# a_207_n150# 0.10fF
-C68 a_n81_n150# a_111_n150# 0.16fF
-C69 a_879_n150# a_687_n150# 0.16fF
-C70 a_783_n150# a_495_n150# 0.10fF
-C71 a_n561_n150# a_n177_n150# 0.07fF
-C72 a_783_n150# a_1071_n150# 0.10fF
-C73 a_399_n150# a_591_n150# 0.16fF
-C74 a_n561_n150# a_n753_n150# 0.16fF
-C75 a_n753_n150# a_n945_n150# 0.16fF
-C76 a_n81_n150# a_207_n150# 0.10fF
-C77 a_399_n150# a_303_n150# 0.43fF
-C78 a_n81_n150# a_n369_n150# 0.10fF
-C79 a_879_n150# a_1167_n150# 0.10fF
-C80 a_n561_n150# a_n273_n150# 0.10fF
-C81 a_111_n150# a_207_n150# 0.43fF
-C82 a_n561_n150# a_n849_n150# 0.10fF
-C83 a_n1229_n150# a_n849_n150# 0.07fF
-C84 w_n1367_n369# a_975_n150# 0.05fF
-C85 a_783_n150# a_687_n150# 0.43fF
-C86 a_n849_n150# a_n945_n150# 0.43fF
-C87 a_n81_n150# a_15_n150# 0.43fF
-C88 a_n1041_n150# a_n1137_n150# 0.43fF
-C89 a_n81_n150# a_n465_n150# 0.07fF
-C90 a_879_n150# a_783_n150# 0.43fF
-C91 a_495_n150# a_399_n150# 0.43fF
-C92 a_303_n150# a_591_n150# 0.10fF
-C93 a_111_n150# a_15_n150# 0.43fF
-C94 a_591_n150# a_975_n150# 0.07fF
-C95 a_n657_n150# a_n369_n150# 0.10fF
-C96 a_n657_n150# a_n1041_n150# 0.07fF
-C97 a_783_n150# a_1167_n150# 0.07fF
+C0 a_n657_n150# a_n369_n150# 0.10fF
+C1 a_495_n150# a_687_n150# 0.16fF
+C2 a_687_n150# a_303_n150# 0.07fF
+C3 a_1167_n150# a_783_n150# 0.07fF
+C4 a_n945_n150# a_n753_n150# 0.16fF
+C5 a_111_n150# a_399_n150# 0.10fF
+C6 a_495_n150# a_399_n150# 0.43fF
+C7 a_879_n150# a_783_n150# 0.43fF
+C8 a_n177_n150# a_n273_n150# 0.43fF
+C9 a_n561_n150# a_n369_n150# 0.16fF
+C10 a_495_n150# a_591_n150# 0.43fF
+C11 a_n945_n150# a_n657_n150# 0.10fF
+C12 a_399_n150# a_303_n150# 0.43fF
+C13 a_n945_n150# a_n1229_n150# 0.10fF
+C14 a_591_n150# a_303_n150# 0.10fF
+C15 a_1167_n150# a_1071_n150# 0.43fF
+C16 a_879_n150# a_1071_n150# 0.16fF
+C17 a_n273_n150# a_n657_n150# 0.07fF
+C18 a_n1041_n150# a_n753_n150# 0.10fF
+C19 a_n945_n150# a_n561_n150# 0.07fF
+C20 a_n945_n150# a_n849_n150# 0.43fF
+C21 a_n177_n150# a_15_n150# 0.16fF
+C22 a_n177_n150# a_207_n150# 0.07fF
+C23 a_687_n150# a_879_n150# 0.16fF
+C24 a_n1041_n150# a_n657_n150# 0.07fF
+C25 a_n1041_n150# a_n1229_n150# 0.16fF
+C26 a_n273_n150# a_n561_n150# 0.10fF
+C27 a_n945_n150# a_n1137_n150# 0.16fF
+C28 a_n177_n150# a_n465_n150# 0.10fF
+C29 a_15_n150# a_399_n150# 0.07fF
+C30 a_591_n150# a_879_n150# 0.10fF
+C31 a_n1041_n150# a_n849_n150# 0.16fF
+C32 a_207_n150# a_399_n150# 0.16fF
+C33 a_1167_n150# a_975_n150# 0.16fF
+C34 a_879_n150# a_975_n150# 0.43fF
+C35 a_n753_n150# a_n465_n150# 0.10fF
+C36 a_207_n150# a_591_n150# 0.07fF
+C37 a_783_n150# a_1071_n150# 0.10fF
+C38 a_n1041_n150# a_n1137_n150# 0.43fF
+C39 a_n657_n150# a_n465_n150# 0.16fF
+C40 a_n81_n150# a_n369_n150# 0.10fF
+C41 a_687_n150# a_783_n150# 0.43fF
+C42 a_n561_n150# a_n465_n150# 0.43fF
+C43 a_n81_n150# a_111_n150# 0.16fF
+C44 a_n849_n150# a_n465_n150# 0.07fF
+C45 a_783_n150# a_399_n150# 0.07fF
+C46 a_n81_n150# a_303_n150# 0.07fF
+C47 a_687_n150# a_1071_n150# 0.07fF
+C48 a_591_n150# a_783_n150# 0.16fF
+C49 a_783_n150# a_975_n150# 0.16fF
+C50 a_n273_n150# a_n81_n150# 0.16fF
+C51 a_495_n150# a_111_n150# 0.07fF
+C52 a_1071_n150# a_975_n150# 0.43fF
+C53 w_n1367_n369# a_1167_n150# 0.14fF
+C54 w_n1367_n369# a_879_n150# 0.04fF
+C55 a_687_n150# a_399_n150# 0.10fF
+C56 a_111_n150# a_303_n150# 0.16fF
+C57 a_495_n150# a_303_n150# 0.16fF
+C58 a_n273_n150# a_n369_n150# 0.43fF
+C59 a_n657_n150# a_n753_n150# 0.43fF
+C60 a_591_n150# a_687_n150# 0.43fF
+C61 a_n177_n150# a_n561_n150# 0.07fF
+C62 a_687_n150# a_975_n150# 0.10fF
+C63 a_15_n150# a_n81_n150# 0.43fF
+C64 a_n273_n150# a_111_n150# 0.07fF
+C65 a_n81_n150# a_207_n150# 0.10fF
+C66 a_591_n150# a_399_n150# 0.16fF
+C67 a_n561_n150# a_n753_n150# 0.16fF
+C68 a_n849_n150# a_n753_n150# 0.43fF
+C69 a_n657_n150# a_n561_n150# 0.43fF
+C70 a_n81_n150# a_n465_n150# 0.07fF
+C71 a_591_n150# a_975_n150# 0.07fF
+C72 a_n657_n150# a_n849_n150# 0.16fF
+C73 a_15_n150# a_n369_n150# 0.07fF
+C74 a_n945_n150# a_n1041_n150# 0.43fF
+C75 a_n1137_n150# a_n753_n150# 0.07fF
+C76 a_n849_n150# a_n1229_n150# 0.07fF
+C77 a_495_n150# a_879_n150# 0.07fF
+C78 a_15_n150# a_111_n150# 0.43fF
+C79 a_207_n150# a_111_n150# 0.43fF
+C80 a_n465_n150# a_n369_n150# 0.43fF
+C81 a_207_n150# a_495_n150# 0.10fF
+C82 a_n1137_n150# a_n1229_n150# 0.43fF
+C83 a_n849_n150# a_n561_n150# 0.10fF
+C84 a_15_n150# a_303_n150# 0.10fF
+C85 a_207_n150# a_303_n150# 0.43fF
+C86 w_n1367_n369# a_1071_n150# 0.07fF
+C87 a_n1137_n150# a_n849_n150# 0.10fF
+C88 a_15_n150# a_n273_n150# 0.10fF
+C89 a_n177_n150# a_n81_n150# 0.43fF
+C90 a_n273_n150# a_n465_n150# 0.16fF
+C91 a_495_n150# a_783_n150# 0.10fF
+C92 a_1167_n150# a_879_n150# 0.10fF
+C93 a_n177_n150# a_n369_n150# 0.16fF
+C94 w_n1367_n369# a_975_n150# 0.05fF
+C95 a_15_n150# a_207_n150# 0.16fF
+C96 a_n753_n150# a_n369_n150# 0.07fF
+C97 a_n177_n150# a_111_n150# 0.10fF
C98 a_1167_n150# VSUBS 0.03fF
C99 a_1071_n150# VSUBS 0.03fF
C100 a_975_n150# VSUBS 0.03fF
@@ -4917,7 +4712,7 @@
.ends
.subckt charge_pump vss pswitch nswitch out vdd biasp nUp Down w_2544_775# iref nDown
-+ Up w_1008_774#
++ Up w_1008_774# w_6648_570#
Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
+ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
@@ -4940,25 +4735,25 @@
Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
+ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
+ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
-C0 nswitch biasp 0.03fF
-C1 nswitch iref 1.91fF
-C2 nswitch vdd 0.07fF
-C3 Down nUp 0.25fF
-C4 nUp pswitch 5.66fF
-C5 Up pswitch 0.70fF
-C6 out pswitch 4.91fF
+C0 biasp vdd 2.64fF
+C1 biasp pswitch 3.11fF
+C2 nDown nswitch 0.31fF
+C3 biasp nswitch 0.03fF
+C4 vdd out 6.66fF
+C5 out pswitch 4.91fF
+C6 biasp iref 0.80fF
C7 nDown Down 0.13fF
-C8 Up nUp 0.15fF
-C9 out nUp 0.31fF
-C10 biasp pswitch 3.11fF
-C11 nswitch Down 2.27fF
-C12 vdd pswitch 3.98fF
-C13 nswitch pswitch 0.06fF
-C14 out vdd 6.66fF
-C15 out nswitch 1.28fF
-C16 iref biasp 0.80fF
-C17 vdd biasp 2.64fF
-C18 nDown nswitch 0.31fF
+C8 Up pswitch 0.70fF
+C9 vdd pswitch 3.98fF
+C10 out nUp 0.31fF
+C11 out nswitch 1.28fF
+C12 Up nUp 0.15fF
+C13 vdd nswitch 0.07fF
+C14 pswitch nUp 5.66fF
+C15 pswitch nswitch 0.06fF
+C16 iref nswitch 1.91fF
+C17 nUp Down 0.25fF
+C18 Down nswitch 2.27fF
C19 vdd vss 35.71fF
C20 Down vss 4.77fF
C21 Up vss 1.17fF
@@ -4975,10 +4770,10 @@
+ a_n125_n42# a_63_n42#
X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-C0 a_n33_n42# a_n125_n42# 0.12fF
-C1 a_63_n42# a_n125_n42# 0.05fF
+C0 a_n33_n42# a_63_n42# 0.12fF
+C1 a_n33_n42# a_n125_n42# 0.12fF
C2 a_33_n68# a_n63_n68# 0.02fF
-C3 a_n33_n42# a_63_n42# 0.12fF
+C3 a_63_n42# a_n125_n42# 0.05fF
C4 a_63_n42# w_n263_n252# 0.09fF
C5 a_n33_n42# w_n263_n252# 0.07fF
C6 a_n125_n42# w_n263_n252# 0.09fF
@@ -4990,13 +4785,13 @@
+ w_n263_n303# a_n33_n84#
X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_63_n84# a_n33_n84# 0.24fF
-C1 a_33_n110# a_n63_n110# 0.02fF
-C2 w_n263_n303# a_n125_n84# 0.10fF
-C3 w_n263_n303# a_n33_n84# 0.07fF
-C4 a_n33_n84# a_n125_n84# 0.24fF
-C5 a_63_n84# w_n263_n303# 0.10fF
-C6 a_63_n84# a_n125_n84# 0.09fF
+C0 w_n263_n303# a_n125_n84# 0.10fF
+C1 w_n263_n303# a_n33_n84# 0.07fF
+C2 a_n125_n84# a_n33_n84# 0.24fF
+C3 a_63_n84# w_n263_n303# 0.10fF
+C4 a_63_n84# a_n125_n84# 0.09fF
+C5 a_n63_n110# a_33_n110# 0.02fF
+C6 a_63_n84# a_n33_n84# 0.24fF
C7 a_63_n84# VSUBS 0.03fF
C8 a_n33_n84# VSUBS 0.03fF
C9 a_n125_n84# VSUBS 0.03fF
@@ -5008,82 +4803,329 @@
.subckt inverter_min_x2 in out vss vdd
Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
-C0 vdd out 0.15fF
+C0 in out 0.30fF
C1 vdd in 0.01fF
-C2 in out 0.30fF
+C2 vdd out 0.15fF
C3 vdd vss 2.93fF
C4 out vss 0.66fF
C5 in vss 0.72fF
.ends
-.subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
-+ out_div o2 nout_div clock_inverter_0/inverter_cp_x1_0/out
+.subckt div_by_2 vss vdd nout_div clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2
++ o1 CLK out_div o2 clock_inverter_0/inverter_cp_x1_0/out
XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
-+ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD
+ out_div DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# nout_div
+ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_0/nCLK DFlipFlop
++ DFlipFlop
Xinverter_min_x4_1 vdd o2 vss nCLK_2 inverter_min_x4
Xinverter_min_x4_0 vdd o1 vss CLK_2 inverter_min_x4
Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
+ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
-C0 nout_div out_div 0.22fF
-C1 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
-C2 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
-C3 nout_div DFlipFlop_0/nCLK 0.43fF
-C4 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
-C5 nout_div DFlipFlop_0/CLK 0.42fF
-C6 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
-C7 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
-C8 vdd out_div 0.03fF
-C9 DFlipFlop_0/nCLK vdd 0.30fF
-C10 o2 nCLK_2 0.11fF
-C11 o1 out_div 0.01fF
-C12 vdd DFlipFlop_0/CLK 0.40fF
-C13 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
-C14 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
-C15 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
-C16 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
-C17 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
-C18 nCLK_2 vdd 0.08fF
-C19 nout_div vdd 0.16fF
-C20 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
-C21 o2 vdd 0.14fF
-C22 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
-C23 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
-C24 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
-C25 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
-C26 vdd CLK_2 0.08fF
-C27 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
-C28 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
-C29 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
-C30 o1 CLK_2 0.11fF
-C31 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
-C32 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
-C33 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
-C34 vdd o1 0.14fF
+C0 vdd nout_div 0.16fF
+C1 DFlipFlop_0/latch_diff_0/nD nout_div 0.07fF
+C2 vdd o1 0.14fF
+C3 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
+C4 o2 vdd 0.14fF
+C5 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C6 vdd nCLK_2 0.08fF
+C7 DFlipFlop_0/latch_diff_0/D nout_div 0.09fF
+C8 vdd DFlipFlop_0/nCLK 0.30fF
+C9 o2 nCLK_2 0.11fF
+C10 DFlipFlop_0/nCLK nout_div 0.43fF
+C11 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C12 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
+C13 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C14 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C15 DFlipFlop_0/latch_diff_0/D DFlipFlop_0/nCLK 0.13fF
+C16 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/CLK -0.48fF
+C17 vdd CLK_2 0.08fF
+C18 DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.29fF
+C19 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C20 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C21 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
+C22 o1 CLK_2 0.11fF
+C23 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C24 vdd DFlipFlop_0/CLK 0.40fF
+C25 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C26 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C27 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
+C28 vdd out_div 0.03fF
+C29 DFlipFlop_0/CLK nout_div 0.42fF
+C30 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C31 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C32 out_div nout_div 0.22fF
+C33 out_div o1 0.01fF
+C34 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
C35 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C36 DFlipFlop_0/CLK vss 1.03fF
C37 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
C38 CLK vss 3.27fF
C39 DFlipFlop_0/nCLK vss 1.76fF
-C40 o1 vss 2.21fF
-C41 CLK_2 vss 1.08fF
-C42 o2 vss 2.21fF
-C43 nCLK_2 vss 1.08fF
+C40 CLK_2 vss 1.08fF
+C41 o1 vss 2.21fF
+C42 nCLK_2 vss 1.08fF
+C43 o2 vss 2.21fF
C44 out_div vss -0.77fF
C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
-C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
-C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C46 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C47 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C48 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
C50 DFlipFlop_0/latch_diff_0/D vss 0.96fF
C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
C52 nout_div vss 4.41fF
-C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
-C54 vdd vss 64.43fF
+C53 vdd vss 64.43fF
+C54 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n7969_2700# m3_n2650_2700# 2.73fF
+C1 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C2 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C3 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C4 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C5 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C6 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C7 m3_7988_2700# m3_2669_2700# 2.73fF
+C8 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C9 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C10 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
+C11 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
+C12 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C13 c1_n13188_n13100# m3_7988_n7900# 61.01fF
+C14 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C15 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C16 m3_2669_8000# m3_7988_8000# 2.73fF
+C17 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C18 m3_n7969_2700# m3_n13288_2700# 2.73fF
+C19 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C20 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C21 m3_2669_n7900# m3_7988_n7900# 2.73fF
+C22 m3_n2650_n7900# m3_n7969_n7900# 2.73fF
+C23 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C24 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C25 m3_2669_n13200# m3_7988_n13200# 2.73fF
+C26 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C27 m3_n7969_8000# m3_n2650_8000# 2.73fF
+C28 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C29 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C30 m3_7988_2700# m3_7988_n2600# 3.39fF
+C31 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C32 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
+C33 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C34 m3_2669_8000# m3_2669_2700# 3.28fF
+C35 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C36 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C37 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C38 m3_n2650_n2600# m3_n2650_2700# 3.28fF
+C39 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C40 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C41 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C42 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C43 m3_n2650_n7900# m3_n2650_n13200# 3.28fF
+C44 m3_n2650_n7900# c1_n13188_n13100# 58.86fF
+C45 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C46 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C47 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C48 m3_7988_2700# m3_7988_8000# 3.39fF
+C49 m3_n13288_n2600# m3_n13288_2700# 3.28fF
+C50 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C51 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C52 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C53 m3_2669_8000# m3_n2650_8000# 2.73fF
+C54 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C55 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C56 m3_n2650_n7900# m3_2669_n7900# 2.73fF
+C57 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C58 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C59 m3_2669_n2600# m3_2669_2700# 3.28fF
+C60 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C61 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C62 m3_n13288_n7900# c1_n13188_n13100# 58.61fF
+C63 m3_n2650_2700# m3_2669_2700# 2.73fF
+C64 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C65 c1_n13188_n13100# VSUBS 2.51fF
+C66 m3_7988_n13200# VSUBS 12.57fF
+C67 m3_2669_n13200# VSUBS 12.37fF
+C68 m3_n2650_n13200# VSUBS 12.37fF
+C69 m3_n7969_n13200# VSUBS 12.37fF
+C70 m3_n13288_n13200# VSUBS 12.37fF
+C71 m3_7988_n7900# VSUBS 12.57fF
+C72 m3_2669_n7900# VSUBS 12.37fF
+C73 m3_n2650_n7900# VSUBS 12.37fF
+C74 m3_n7969_n7900# VSUBS 12.37fF
+C75 m3_n13288_n7900# VSUBS 12.37fF
+C76 m3_7988_n2600# VSUBS 12.57fF
+C77 m3_2669_n2600# VSUBS 12.37fF
+C78 m3_n2650_n2600# VSUBS 12.37fF
+C79 m3_n7969_n2600# VSUBS 12.37fF
+C80 m3_n13288_n2600# VSUBS 12.37fF
+C81 m3_7988_2700# VSUBS 12.57fF
+C82 m3_2669_2700# VSUBS 12.37fF
+C83 m3_n2650_2700# VSUBS 12.37fF
+C84 m3_n7969_2700# VSUBS 12.37fF
+C85 m3_n13288_2700# VSUBS 12.37fF
+C86 m3_7988_8000# VSUBS 12.57fF
+C87 m3_2669_8000# VSUBS 12.37fF
+C88 m3_n2650_8000# VSUBS 12.37fF
+C89 m3_n7969_8000# VSUBS 12.37fF
+C90 m3_n13288_8000# VSUBS 12.37fF
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+C0 out in 2.17fF
+C1 in VSUBS -10.03fF
+C2 out VSUBS 62.40fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
+C1 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C2 m3_10_n4250# m3_n4309_n4250# 1.75fF
+C3 m3_10_n4250# m3_n4309_50# 1.75fF
+C4 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C5 m3_10_n4250# c1_110_n4150# 81.11fF
+C6 m3_n4309_n4250# m3_n4309_50# 2.63fF
+C7 c1_110_n4150# VSUBS 0.12fF
+C8 c1_n4209_n4150# VSUBS 0.12fF
+C9 m3_n4309_n4250# VSUBS 8.68fF
+C10 m3_10_n4250# VSUBS 17.92fF
+C11 m3_n4309_50# VSUBS 8.68fF
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+C0 out in 3.21fF
+C1 in VSUBS -8.91fF
+C2 out VSUBS 3.92fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C1 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C2 m3_n2150_2200# m3_n6469_2200# 1.75fF
+C3 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C4 c1_n6369_n6300# m3_n6469_2200# 38.10fF
+C5 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C6 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C7 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C8 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C9 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C10 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C11 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C12 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
+C13 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C14 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C15 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C16 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
+C17 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C18 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
+C19 c1_2269_n6300# VSUBS 0.16fF
+C20 c1_n2050_n6300# VSUBS 0.16fF
+C21 c1_n6369_n6300# VSUBS 0.16fF
+C22 m3_n2150_n6400# VSUBS 8.68fF
+C23 m3_n6469_n6400# VSUBS 8.68fF
+C24 m3_n2150_n2100# VSUBS 8.68fF
+C25 m3_n6469_n2100# VSUBS 8.68fF
+C26 m3_2169_n6400# VSUBS 26.86fF
+C27 m3_n2150_2200# VSUBS 8.68fF
+C28 m3_n6469_2200# VSUBS 8.68fF
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+C0 out in 8.08fF
+C1 in VSUBS -16.59fF
+C2 out VSUBS 13.00fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+C0 a_30_n300# a_n88_n300# 0.61fF
+C1 a_n88_n300# a_n118_n388# 0.11fF
+C2 a_30_n300# w_n226_n510# 0.40fF
+C3 a_n88_n300# w_n226_n510# 0.40fF
+C4 a_n118_n388# w_n226_n510# 0.28fF
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# w_n739_n2890# 1.98fF
+C1 a_n573_2292# w_n739_n2890# 1.98fF
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+C0 out vss 3.87fF
+C1 in vss 3.02fF
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss cap3_loop_filter_0/in
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 vc_pex in 0.18fF
+C1 D0_cap in 0.07fF
+C2 cap3_loop_filter_0/in in 0.79fF
+C3 vc_pex vss -38.13fF
+C4 res_loop_filter_2/out vss 8.49fF
+C5 D0_cap vss 0.04fF
+C6 in vss -18.54fF
+C7 cap3_loop_filter_0/in vss -3.74fF
.ends
.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
@@ -5092,9 +5134,9 @@
X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
-C0 a_n129_n600# a_n257_n777# 0.29fF
-C1 a_n129_n600# a_n221_n600# 7.87fF
-C2 a_n221_n600# a_n257_n777# 0.25fF
+C0 a_n221_n600# a_n257_n777# 0.25fF
+C1 a_n257_n777# a_n129_n600# 0.29fF
+C2 a_n221_n600# a_n129_n600# 7.87fF
C3 a_n129_n600# VSUBS 0.10fF
C4 a_n221_n600# VSUBS 0.25fF
C5 a_n257_n777# VSUBS 1.05fF
@@ -5106,15 +5148,15 @@
X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
-C0 a_n129_n300# a_n257_n404# 0.30fF
+C0 a_n257_n404# a_n221_n300# 0.21fF
C1 a_n129_n300# a_n221_n300# 4.05fF
-C2 a_n257_n404# a_n221_n300# 0.21fF
+C2 a_n257_n404# a_n129_n300# 0.30fF
C3 a_n129_n300# w_n257_n327# 0.11fF
C4 a_n221_n300# w_n257_n327# 0.25fF
C5 a_n257_n404# w_n257_n327# 1.11fF
.ends
-.subckt buffer_salida a_678_n100# out in a_3996_n100# vss vdd
+.subckt buffer_salida a_678_n100# a_3996_n100# out vdd in vss
Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
@@ -5261,24 +5303,981 @@
Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
-C0 a_678_n100# vdd 0.08fF
-C1 out vdd 47.17fF
-C2 a_3996_n100# a_678_n100# 6.52fF
-C3 a_3996_n100# out 55.19fF
-C4 a_678_n100# in 0.81fF
-C5 a_3996_n100# vdd 3.68fF
-C6 vdd in 0.02fF
-C7 a_3996_n100# vss 49.53fF
-C8 vdd vss 20.93fF
-C9 out vss 35.17fF
+C0 a_3996_n100# a_678_n100# 6.52fF
+C1 vdd out 47.17fF
+C2 vdd a_3996_n100# 3.68fF
+C3 in a_678_n100# 0.81fF
+C4 a_3996_n100# out 55.19fF
+C5 in vdd 0.02fF
+C6 vdd a_678_n100# 0.08fF
+C7 vdd vss 20.93fF
+C8 out vss 35.17fF
+C9 a_3996_n100# vss 49.53fF
C10 a_678_n100# vss 13.08fF
C11 in vss 0.87fF
.ends
+.subckt trans_gate_mux2to8 in vss out en_pos en_neg vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss en_neg in out out vdd en_neg en_neg in sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 en_pos vss en_pos in out out en_pos in sky130_fd_pr__nfet_01v8_BHR94T
+C0 in en_neg 0.28fF
+C1 in out 0.36fF
+C2 en_pos en_neg 0.04fF
+C3 en_pos out 0.27fF
+C4 en_neg vdd 0.01fF
+C5 vdd out 0.68fF
+C6 en_neg out 0.07fF
+C7 en_pos in 0.07fF
+C8 in vdd 0.05fF
+C9 vdd vss 2.75fF
+C10 en_pos vss 0.30fF
+C11 in vss 1.53fF
+C12 out vss 0.88fF
+C13 en_neg vss 0.31fF
+.ends
+
+.subckt mux2to1 vss select_0_neg in_a out_a_0 out_a_1 select_0 vdd
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 out_a_1 select_0 0.14fF
+C1 out_a_1 in_a 0.08fF
+C2 select_0_neg select_0 0.17fF
+C3 select_0_neg in_a 0.11fF
+C4 select_0 in_a 0.31fF
+C5 out_a_1 vdd 0.09fF
+C6 out_a_0 select_0_neg 0.05fF
+C7 out_a_0 in_a 0.08fF
+C8 select_0 vdd 0.04fF
+C9 vdd in_a 0.14fF
+C10 out_a_0 vdd 0.09fF
+C11 out_a_1 vss 1.03fF
+C12 vdd vss 6.09fF
+C13 select_0_neg vss 1.12fF
+C14 in_a vss 2.43fF
+C15 out_a_0 vss 1.03fF
+C16 select_0 vss 1.03fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 a_194_125# X 0.29fF
+C1 a_194_125# VPWR 0.33fF
+C2 a_355_368# X 0.17fF
+C3 A VPWR 0.15fF
+C4 a_194_125# B 0.57fF
+C5 a_194_125# VGND 0.25fF
+C6 A B 0.28fF
+C7 A VGND 0.31fF
+C8 VPWR a_355_368# 0.37fF
+C9 a_355_368# B 0.08fF
+C10 a_194_125# a_158_392# 0.06fF
+C11 A a_194_125# 0.18fF
+C12 VPWR VPB 0.06fF
+C13 a_194_125# a_355_368# 0.51fF
+C14 VPWR X 0.07fF
+C15 A a_355_368# 0.02fF
+C16 B X 0.13fF
+C17 VGND X 0.28fF
+C18 VPWR B 0.09fF
+C19 VPWR VGND 0.01fF
+C20 VGND B 0.10fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 B VPWR 0.02fF
+C1 a_56_136# VGND 0.06fF
+C2 a_56_136# B 0.30fF
+C3 X VGND 0.15fF
+C4 VPB VPWR 0.04fF
+C5 X B 0.02fF
+C6 A VGND 0.21fF
+C7 A B 0.08fF
+C8 B VGND 0.03fF
+C9 a_56_136# VPWR 0.57fF
+C10 X VPWR 0.20fF
+C11 X a_56_136# 0.26fF
+C12 A VPWR 0.07fF
+C13 a_56_136# A 0.17fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 X A 0.02fF
+C1 B A 0.10fF
+C2 VGND X 0.16fF
+C3 VGND B 0.11fF
+C4 a_63_368# A 0.28fF
+C5 VPWR A 0.05fF
+C6 VGND a_63_368# 0.27fF
+C7 X a_63_368# 0.33fF
+C8 B a_63_368# 0.14fF
+C9 X VPWR 0.18fF
+C10 B VPWR 0.01fF
+C11 a_152_368# a_63_368# 0.03fF
+C12 VPWR a_63_368# 0.29fF
+C13 VPWR VPB 0.04fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/latch_diff_1/nD vss vdd DFlipFlop_2/latch_diff_0/nD Q0 Q1 CLK DFlipFlop_0/Q
++ DFlipFlop_2/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ nQ0 DFlipFlop_3/latch_diff_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/nD DFlipFlop_1/latch_diff_0/D DFlipFlop_2/latch_diff_0/m1_657_280#
++ CLK_5 Q1_shift nQ2 DFlipFlop_2/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D DFlipFlop_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/latch_diff_0/nD sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_0/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_1/D DFlipFlop_2/nQ DFlipFlop_3/latch_diff_0/nD DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_2/latch_diff_0/D DFlipFlop_0/latch_diff_0/D sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368# DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_1/a_143_136# sky130_fd_sc_hs__or2_1_0/a_152_368# sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_3/nQ sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 nCLK DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/D
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss vdd DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ nCLK DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss vdd DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ CLK DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# Q1 DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 Q1 DFlipFlop_2/D 0.10fF
+C1 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C2 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
+C3 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C4 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C5 Q1 nQ0 0.06fF
+C6 CLK vdd 0.41fF
+C7 DFlipFlop_1/D vdd 0.25fF
+C8 DFlipFlop_0/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C9 vdd nQ2 0.04fF
+C10 Q1_shift DFlipFlop_3/nQ 0.04fF
+C11 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
+C12 DFlipFlop_1/D nCLK 0.14fF
+C13 nQ2 nCLK 0.10fF
+C14 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C15 DFlipFlop_3/latch_diff_0/m1_657_280# Q1 0.28fF
+C16 Q0 DFlipFlop_0/D 0.39fF
+C17 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C18 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C19 nCLK DFlipFlop_0/Q 0.11fF
+C20 vdd Q1_shift 0.10fF
+C21 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C22 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C23 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C24 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C25 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C26 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C27 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C28 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C29 Q0 DFlipFlop_0/latch_diff_1/D 0.23fF
+C30 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C31 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C32 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C33 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C34 vdd Q0 5.33fF
+C35 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C36 nCLK DFlipFlop_3/latch_diff_1/D 0.14fF
+C37 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C38 Q0 nCLK 0.20fF
+C39 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C40 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C41 CLK DFlipFlop_1/D 0.21fF
+C42 CLK nQ2 0.17fF
+C43 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C44 Q1 DFlipFlop_0/D 0.13fF
+C45 DFlipFlop_2/nQ Q1 0.31fF
+C46 DFlipFlop_2/latch_diff_0/D nCLK 0.11fF
+C47 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C48 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C49 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C50 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C51 CLK DFlipFlop_0/Q 0.08fF
+C52 DFlipFlop_3/latch_diff_1/nD nCLK 0.09fF
+C53 nQ2 DFlipFlop_0/Q 0.09fF
+C54 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C55 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C56 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C57 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
+C58 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C59 Q1 DFlipFlop_3/nQ 0.10fF
+C60 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C61 Q1 DFlipFlop_0/latch_diff_0/D 0.15fF
+C62 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C63 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C64 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C65 vdd Q1 9.49fF
+C66 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C67 Q1 nCLK -0.01fF
+C68 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C69 CLK Q0 0.08fF
+C70 DFlipFlop_1/D Q0 0.07fF
+C71 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C72 nQ2 Q0 0.23fF
+C73 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
+C74 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C75 vdd DFlipFlop_2/D 0.07fF
+C76 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C77 Q0 DFlipFlop_0/Q 0.21fF
+C78 DFlipFlop_2/D nCLK 0.41fF
+C79 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C80 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C81 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C82 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
+C83 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C84 vdd nQ0 0.11fF
+C85 nQ0 nCLK 0.09fF
+C86 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
+C87 nQ0 DFlipFlop_1/latch_diff_0/nD 0.08fF
+C88 sky130_fd_sc_hs__and2_1_0/a_56_136# DFlipFlop_0/D 0.04fF
+C89 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C90 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C91 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C92 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C93 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C94 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C95 CLK Q1 -0.10fF
+C96 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C97 DFlipFlop_1/D Q1 0.03fF
+C98 Q1 nQ2 0.07fF
+C99 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C100 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C101 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C102 Q1 DFlipFlop_0/Q 0.13fF
+C103 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C104 CLK DFlipFlop_2/D 0.14fF
+C105 Q1 Q1_shift 0.36fF
+C106 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C107 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
+C108 CLK nQ0 0.19fF
+C109 DFlipFlop_1/D nQ0 0.12fF
+C110 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C111 nQ2 nQ0 0.03fF
+C112 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C113 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C114 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C115 vdd DFlipFlop_0/D 0.19fF
+C116 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C117 DFlipFlop_2/nQ vdd 0.02fF
+C118 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C119 DFlipFlop_2/nQ nCLK 0.09fF
+C120 Q1 DFlipFlop_3/latch_diff_1/D 0.79fF
+C121 Q1 DFlipFlop_3/latch_diff_1/m1_657_280# 0.28fF
+C122 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q1 0.20fF
+C123 Q1 Q0 9.65fF
+C124 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C125 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C126 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C127 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C128 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C129 vdd DFlipFlop_3/nQ 0.02fF
+C130 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C131 nCLK DFlipFlop_3/nQ 0.02fF
+C132 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C133 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C134 vdd CLK_5 0.15fF
+C135 DFlipFlop_2/D Q0 0.25fF
+C136 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C137 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C138 vdd nCLK 0.34fF
+C139 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C140 Q0 nQ0 0.33fF
+C141 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.08fF
+C142 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
+C143 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C144 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C145 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C146 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C147 CLK DFlipFlop_2/nQ 0.13fF
+C148 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C149 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C150 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C151 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C152 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C153 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C154 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C155 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C156 CLK DFlipFlop_3/nQ 0.01fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 Q1_shift vss -0.29fF
+C162 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C163 DFlipFlop_3/nQ vss 0.52fF
+C164 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C165 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C166 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C168 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 Q1 vss 8.55fF
+C172 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C173 DFlipFlop_2/nQ vss 0.50fF
+C174 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C175 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C176 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C177 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C178 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 DFlipFlop_2/D vss 5.34fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 Q0 vss 0.53fF
+C183 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C184 nQ0 vss 3.42fF
+C185 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C186 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C187 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C188 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C191 DFlipFlop_1/D vss 3.72fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 DFlipFlop_0/Q vss -0.94fF
+C194 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C195 nCLK vss 0.96fF
+C196 nQ2 vss 2.05fF
+C197 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C198 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C199 CLK vss 0.20fF
+C200 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C202 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 DFlipFlop_0/D vss 4.04fF
+C205 vdd vss 146.76fF
+C206 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt mux2to4 vss out_b_1 vdd select_0 select_0_neg in_a out_a_0 out_a_1 out_b_0
++ in_b
+Xtrans_gate_mux2to8_0 in_a vss out_a_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_1 in_a vss out_a_1 select_0 select_0_neg vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_2 in_b vss out_b_0 select_0_neg select_0 vdd trans_gate_mux2to8
+Xtrans_gate_mux2to8_3 in_b vss out_b_1 select_0 select_0_neg vdd trans_gate_mux2to8
+C0 vdd select_0_neg 0.08fF
+C1 in_b out_b_0 0.08fF
+C2 out_a_0 in_a 0.08fF
+C3 out_b_0 in_a 0.11fF
+C4 vdd out_b_1 0.09fF
+C5 out_a_1 select_0 0.18fF
+C6 select_0 select_0_neg 0.49fF
+C7 out_a_1 in_b 0.08fF
+C8 select_0 out_b_1 0.14fF
+C9 out_a_1 out_b_0 0.88fF
+C10 out_a_0 select_0_neg 0.05fF
+C11 out_a_1 in_a 0.08fF
+C12 in_b select_0_neg 0.10fF
+C13 out_b_0 select_0_neg -0.13fF
+C14 select_0_neg in_a 0.22fF
+C15 in_b out_b_1 0.08fF
+C16 select_0 vdd 0.08fF
+C17 out_a_1 select_0_neg 0.12fF
+C18 out_a_0 vdd 0.09fF
+C19 vdd in_b 0.17fF
+C20 vdd out_b_0 0.15fF
+C21 vdd in_a 0.17fF
+C22 select_0 in_b 0.24fF
+C23 select_0 out_b_0 0.03fF
+C24 select_0 in_a 0.31fF
+C25 out_a_1 vdd 0.16fF
+C26 out_b_1 vss 1.03fF
+C27 in_b vss 2.46fF
+C28 out_b_0 vss 0.84fF
+C29 out_a_1 vss 0.32fF
+C30 vdd vss 12.14fF
+C31 select_0_neg vss 2.57fF
+C32 in_a vss 2.46fF
+C33 out_a_0 vss 1.03fF
+C34 select_0 vss 2.24fF
+.ends
+
+.subckt sky130_fd_sc_hs__mux2_1 A0 A1 S VGND VNB VPB VPWR X a_304_74# a_443_74# a_524_368#
++ a_27_112#
+X0 VPWR S a_27_112# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 VGND a_27_112# a_443_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 X a_304_74# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X3 VPWR a_27_112# a_524_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_304_74# A1 a_226_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X5 X a_304_74# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X6 a_223_368# S VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_304_74# A0 a_223_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_443_74# A0 a_304_74# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X9 a_524_368# A1 a_304_74# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_226_74# S VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X11 VGND S a_27_112# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VGND a_304_74# 0.58fF
+C1 VGND VPWR 0.02fF
+C2 VGND X 0.11fF
+C3 VGND S 0.07fF
+C4 VPB VPWR 0.06fF
+C5 A1 A0 0.31fF
+C6 a_27_112# A1 0.18fF
+C7 a_524_368# a_27_112# 0.06fF
+C8 a_304_74# a_443_74# 0.12fF
+C9 VGND A1 0.09fF
+C10 A1 a_443_74# 0.07fF
+C11 a_27_112# A0 0.07fF
+C12 a_223_368# a_304_74# 0.05fF
+C13 VGND A0 0.02fF
+C14 VGND a_27_112# 0.18fF
+C15 a_27_112# VPB 0.01fF
+C16 a_304_74# VPWR 0.13fF
+C17 X a_304_74# 0.29fF
+C18 S a_304_74# 0.18fF
+C19 X VPWR 0.28fF
+C20 S VPWR 0.05fF
+C21 A1 a_304_74# 0.69fF
+C22 A1 VPWR 0.01fF
+C23 A1 X 0.02fF
+C24 A1 S 0.10fF
+C25 a_223_368# a_27_112# 0.09fF
+C26 a_226_74# a_304_74# 0.08fF
+C27 a_304_74# A0 0.23fF
+C28 a_27_112# a_304_74# 0.58fF
+C29 a_27_112# VPWR 0.99fF
+C30 a_27_112# X 0.08fF
+C31 S A0 0.04fF
+C32 a_27_112# S 0.22fF
+C33 VGND VNB 0.88fF
+C34 X VNB 0.25fF
+C35 VPWR VNB 0.89fF
+C36 A1 VNB 0.37fF
+C37 A0 VNB 0.23fF
+C38 S VNB 0.34fF
+C39 VPB VNB 0.87fF
+C40 a_304_74# VNB 0.36fF
+C41 a_27_112# VNB 0.65fF
+.ends
+
+.subckt prescaler_23 nCLK vss DFlipFlop_0/latch_diff_1/nD nCLK_23 DFlipFlop_2/latch_diff_0/nD
++ vdd DFlipFlop_2/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ CLK_23 DFlipFlop_2/latch_diff_0/m1_657_280# CLK DFlipFlop_2/latch_diff_1/nD DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_1/D DFlipFlop_2/latch_diff_0/D
++ MC DFlipFlop_0/latch_diff_0/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q2
+Xsky130_fd_sc_hs__mux2_1_0 sky130_fd_sc_hs__or2_1_1/X nCLK_23 MC vss vss vdd vdd CLK_23
++ sky130_fd_sc_hs__mux2_1_0/a_304_74# sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__mux2_1_0/a_524_368#
++ sky130_fd_sc_hs__mux2_1_0/a_27_112# sky130_fd_sc_hs__mux2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ nCLK DFlipFlop_0/latch_diff_0/nD
++ Q1 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# nCLK_23 DFlipFlop_0/latch_diff_0/D
++ CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ CLK DFlipFlop_2/latch_diff_0/nD
++ Q2_d DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# Q2 DFlipFlop_2/latch_diff_0/D
++ nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss vdd DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK_23 nCLK DFlipFlop_1/latch_diff_0/nD
++ Q2 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 nCLK_23 sky130_fd_sc_hs__or2_1_0/X vss vss vdd vdd DFlipFlop_1/D
++ sky130_fd_sc_hs__and2_1_0/a_143_136# sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 MC vss vss vdd vdd sky130_fd_sc_hs__or2_1_0/X sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+Xsky130_fd_sc_hs__or2_1_1 Q2 Q2_d vss vss vdd vdd sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__or2_1_1/a_152_368#
++ sky130_fd_sc_hs__or2_1_1/a_63_368# sky130_fd_sc_hs__or2_1
+C0 Q1 MC 0.29fF
+C1 CLK Q2 0.29fF
+C2 CLK DFlipFlop_2/latch_diff_1/nD 0.19fF
+C3 nCLK_23 DFlipFlop_0/nQ 0.05fF
+C4 MC Q2 0.18fF
+C5 DFlipFlop_2/nQ nCLK 0.02fF
+C6 CLK DFlipFlop_1/D 0.40fF
+C7 sky130_fd_sc_hs__or2_1_1/X vdd 0.03fF
+C8 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C9 sky130_fd_sc_hs__or2_1_1/X sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.08fF
+C10 DFlipFlop_2/latch_diff_0/m1_657_280# nCLK 0.31fF
+C11 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.02fF
+C12 nCLK_23 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C13 DFlipFlop_2/nQ Q2 0.13fF
+C14 nCLK_23 vdd 3.35fF
+C15 nCLK sky130_fd_sc_hs__or2_1_0/a_152_368# 0.01fF
+C16 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_304_74# 0.04fF
+C17 sky130_fd_sc_hs__or2_1_1/a_63_368# Q2 0.09fF
+C18 sky130_fd_sc_hs__or2_1_1/X Q2_d 0.03fF
+C19 MC CLK 0.08fF
+C20 nCLK DFlipFlop_1/latch_diff_1/D 0.09fF
+C21 sky130_fd_sc_hs__mux2_1_0/a_443_74# sky130_fd_sc_hs__or2_1_1/X 0.03fF
+C22 Q1 sky130_fd_sc_hs__or2_1_0/a_152_368# 0.01fF
+C23 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C24 sky130_fd_sc_hs__mux2_1_0/a_443_74# nCLK_23 0.09fF
+C25 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in Q2 0.38fF
+C26 nCLK_23 sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C27 DFlipFlop_2/nQ CLK 0.02fF
+C28 DFlipFlop_0/latch_diff_1/D nCLK_23 0.05fF
+C29 DFlipFlop_0/latch_diff_1/nD Q1 0.03fF
+C30 sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__or2_1_0/X 0.07fF
+C31 nCLK nCLK_23 0.11fF
+C32 DFlipFlop_2/latch_diff_1/m1_657_280# Q2_d 0.03fF
+C33 nCLK DFlipFlop_1/latch_diff_0/D 0.02fF
+C34 sky130_fd_sc_hs__or2_1_1/X Q2 0.24fF
+C35 nCLK DFlipFlop_0/nQ 0.11fF
+C36 Q1 nCLK_23 0.02fF
+C37 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out nCLK_23 0.49fF
+C38 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C39 nCLK_23 Q2 0.03fF
+C40 Q2_d vdd 0.02fF
+C41 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.10fF
+C42 MC sky130_fd_sc_hs__mux2_1_0/a_27_112# 0.24fF
+C43 DFlipFlop_1/latch_diff_1/nD nCLK 0.18fF
+C44 Q1 DFlipFlop_0/nQ -0.02fF
+C45 CLK DFlipFlop_1/latch_diff_1/D 0.18fF
+C46 sky130_fd_sc_hs__or2_1_0/X vdd 0.03fF
+C47 Q1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.06fF
+C48 DFlipFlop_1/D nCLK_23 0.02fF
+C49 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C50 nCLK vdd -0.55fF
+C51 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C52 MC sky130_fd_sc_hs__or2_1_1/X 0.02fF
+C53 DFlipFlop_2/latch_diff_0/D Q2 0.30fF
+C54 DFlipFlop_1/latch_diff_0/nD CLK 0.09fF
+C55 CLK nCLK_23 0.22fF
+C56 Q1 vdd 0.07fF
+C57 MC nCLK_23 4.46fF
+C58 nCLK_23 DFlipFlop_0/latch_diff_0/nD 0.12fF
+C59 Q2 vdd 1.63fF
+C60 sky130_fd_sc_hs__and2_1_0/a_56_136# CLK 0.08fF
+C61 sky130_fd_sc_hs__or2_1_0/a_63_368# nCLK 0.05fF
+C62 CLK DFlipFlop_0/nQ 0.15fF
+C63 nCLK sky130_fd_sc_hs__or2_1_0/X 0.06fF
+C64 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.31fF
+C65 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.29fF
+C66 Q2_d DFlipFlop_2/latch_diff_1/D 0.03fF
+C67 DFlipFlop_1/D vdd 0.07fF
+C68 Q2_d Q2 0.66fF
+C69 CLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.33fF
+C70 nCLK DFlipFlop_2/latch_diff_0/nD 0.09fF
+C71 DFlipFlop_1/latch_diff_1/nD CLK 0.11fF
+C72 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.09fF
+C73 Q1 sky130_fd_sc_hs__or2_1_0/X 0.06fF
+C74 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.06fF
+C75 CLK DFlipFlop_2/latch_diff_0/D 0.13fF
+C76 Q1 nCLK -0.02fF
+C77 CLK vdd 0.34fF
+C78 nCLK DFlipFlop_2/latch_diff_1/D 0.16fF
+C79 nCLK Q2 0.29fF
+C80 nCLK DFlipFlop_2/latch_diff_1/nD 0.12fF
+C81 MC vdd 0.88fF
+C82 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_524_368# 0.04fF
+C83 nCLK_23 sky130_fd_sc_hs__mux2_1_0/a_27_112# 0.07fF
+C84 DFlipFlop_1/D sky130_fd_sc_hs__or2_1_0/X 0.35fF
+C85 CLK_23 vdd 0.16fF
+C86 sky130_fd_sc_hs__mux2_1_0/a_304_74# CLK_23 0.05fF
+C87 Q2 DFlipFlop_2/latch_diff_1/D 0.13fF
+C88 nCLK DFlipFlop_1/D 0.16fF
+C89 Q2 DFlipFlop_2/latch_diff_1/nD 0.17fF
+C90 CLK sky130_fd_sc_hs__or2_1_0/X 0.01fF
+C91 DFlipFlop_0/latch_diff_1/nD nCLK_23 0.02fF
+C92 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.31fF
+C93 MC sky130_fd_sc_hs__or2_1_0/X 0.09fF
+C94 DFlipFlop_0/latch_diff_1/D CLK 0.04fF
+C95 sky130_fd_sc_hs__or2_1_1/X nCLK_23 0.26fF
+C96 MC nCLK 0.01fF
+C97 Q1 CLK -0.07fF
+C98 sky130_fd_sc_hs__and2_1_0/a_56_136# nCLK_23 0.14fF
+C99 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C100 CLK DFlipFlop_2/latch_diff_1/D 0.09fF
+C101 sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C102 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C103 sky130_fd_sc_hs__or2_1_0/X vss 0.92fF
+C104 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.39fF
+C105 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.72fF
+C106 DFlipFlop_1/latch_diff_1/D vss -1.72fF
+C107 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C108 DFlipFlop_1/latch_diff_1/nD vss 0.58fF
+C109 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C110 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C111 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C112 DFlipFlop_1/D vss 2.98fF
+C113 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C114 Q2_d vss -0.22fF
+C115 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C116 DFlipFlop_2/nQ vss 0.48fF
+C117 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C118 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C119 DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C120 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C121 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C122 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C123 Q2 vss 1.35fF
+C124 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C125 Q1 vss 0.50fF
+C126 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C127 nCLK vss -1.49fF
+C128 DFlipFlop_0/nQ vss 0.48fF
+C129 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C130 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C131 CLK vss -0.61fF
+C132 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C133 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C134 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C135 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C136 nCLK_23 vss -0.65fF
+C137 vdd vss 115.92fF
+C138 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C139 CLK_23 vss -0.57fF
+C140 sky130_fd_sc_hs__or2_1_1/X vss -0.35fF
+C141 MC vss 2.09fF
+C142 sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.41fF
+C143 sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.69fF
+.ends
+
+.subckt freq_div clk_0 vss in_a n_clk_0 vdd prescaler_23_0/Q2 s_0 s_1_n s_1 prescaler_23_0/nCLK_23
++ prescaler_23_0/MC clk_d prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# s_0_n
++ clk_pre div_by_5_0/DFlipFlop_2/latch_diff_0/nD prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out div_by_5_0/Q1 div_by_5_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ div_by_5_0/DFlipFlop_2/latch_diff_1/nD clk_2 in_b clk_5 prescaler_23_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_1/D prescaler_23_0/DFlipFlop_2/latch_diff_0/D
+Xdiv_by_2_0 vss vdd div_by_2_0/nout_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in
++ clk_2 div_by_2_0/nCLK_2 div_by_2_0/o1 clk_out_mux21 div_by_2_0/out_div div_by_2_0/o2
++ div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out div_by_2
+Xmux2to1_0 vss s_0_n clk_out_mux21 clk_pre clk_5 s_0 vdd mux2to1
+Xinverter_min_x4_0 vdd inverter_min_x4_0/in vss clk_d inverter_min_x4
+Xmux2to1_1 vss s_1_n out clk_d clk_2 s_1 vdd mux2to1
+Xinverter_min_x2_0 clk_out_mux21 inverter_min_x4_0/in vss vdd inverter_min_x2
+Xinverter_min_x2_1 s_1 s_1_n vss vdd inverter_min_x2
+Xinverter_min_x2_2 s_0 s_0_n vss vdd inverter_min_x2
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_clk_1 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5_0/Q0 div_by_5_0/Q1 clk_1 div_by_5_0/DFlipFlop_0/Q div_by_5_0/DFlipFlop_2/latch_diff_1/D
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136#
++ div_by_5_0/nQ0 div_by_5_0/DFlipFlop_3/latch_diff_0/D div_by_5_0/DFlipFlop_3/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# clk_5 div_by_5_0/Q1_shift div_by_5_0/nQ2
++ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
++ div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_2/latch_diff_0/D
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xmux2to4_0 vss n_clk_1 vdd s_0 s_0_n in_a clk_0 clk_1 n_clk_0 in_b mux2to4
+Xprescaler_23_0 n_clk_0 vss prescaler_23_0/DFlipFlop_0/latch_diff_1/nD prescaler_23_0/nCLK_23
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vdd prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_pre prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_0 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD prescaler_23_0/DFlipFlop_0/latch_diff_0/nD
++ prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# prescaler_23_0/DFlipFlop_0/latch_diff_1/D
++ prescaler_23_0/DFlipFlop_2/latch_diff_0/D prescaler_23_0/MC prescaler_23_0/DFlipFlop_0/latch_diff_0/D
++ prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in prescaler_23_0/Q2
++ prescaler_23
+C0 s_0_n div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.37fF
+C1 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.05fF
+C2 n_clk_0 prescaler_23_0/nCLK_23 0.16fF
+C3 s_1 out 0.39fF
+C4 s_0_n div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C5 vdd clk_out_mux21 0.14fF
+C6 inverter_min_x4_0/in clk_d 0.11fF
+C7 s_0 clk_1 1.36fF
+C8 s_0_n div_by_5_0/DFlipFlop_0/Q 0.24fF
+C9 s_1 clk_d 0.22fF
+C10 vdd clk_0 0.63fF
+C11 vdd div_by_5_0/Q1 0.04fF
+C12 div_by_5_0/DFlipFlop_0/D clk_1 0.14fF
+C13 div_by_5_0/DFlipFlop_1/D s_0 0.03fF
+C14 div_by_5_0/nQ2 s_0 0.05fF
+C15 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_clk_1 0.11fF
+C16 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.20fF
+C17 div_by_5_0/DFlipFlop_2/latch_diff_0/nD s_0 0.12fF
+C18 n_clk_1 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.11fF
+C19 s_0 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.05fF
+C20 s_0_n clk_out_mux21 0.45fF
+C21 clk_pre s_0 0.21fF
+C22 div_by_5_0/DFlipFlop_1/latch_diff_1/D s_0_n 0.04fF
+C23 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/D 0.13fF
+C24 s_0_n in_b 0.48fF
+C25 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out s_0 -0.13fF
+C26 s_0_n div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.31fF
+C27 vdd n_clk_1 0.15fF
+C28 div_by_5_0/DFlipFlop_0/latch_diff_1/D clk_1 0.11fF
+C29 s_0_n div_by_5_0/Q1 0.21fF
+C30 vdd clk_d 0.23fF
+C31 s_0_n div_by_5_0/Q1_shift 0.04fF
+C32 s_0 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.02fF
+C33 out s_1_n 0.33fF
+C34 s_0 div_by_5_0/nQ0 0.05fF
+C35 vdd clk_2 0.06fF
+C36 clk_5 clk_out_mux21 0.05fF
+C37 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.04fF
+C38 s_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.19fF
+C39 s_0_n div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C40 vdd s_0 3.90fF
+C41 s_0 div_by_5_0/DFlipFlop_2/nQ 0.05fF
+C42 div_by_5_0/Q0 n_clk_1 0.01fF
+C43 clk_5 div_by_5_0/Q1_shift 0.04fF
+C44 s_0 div_by_5_0/DFlipFlop_3/nQ 0.02fF
+C45 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_1 0.05fF
+C46 s_1_n clk_2 0.59fF
+C47 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out clk_0 0.16fF
+C48 s_0_n s_0 7.76fF
+C49 div_by_5_0/Q0 s_0 0.02fF
+C50 s_0_n div_by_5_0/DFlipFlop_0/D 0.05fF
+C51 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD n_clk_0 0.13fF
+C52 div_by_5_0/DFlipFlop_0/latch_diff_1/nD clk_1 0.08fF
+C53 n_clk_0 clk_1 -0.03fF
+C54 div_by_5_0/DFlipFlop_0/latch_diff_0/nD s_0 0.12fF
+C55 vdd clk_1 0.18fF
+C56 clk_0 prescaler_23_0/nCLK_23 0.16fF
+C57 s_0 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.02fF
+C58 s_0_n div_by_5_0/DFlipFlop_2/D 0.05fF
+C59 s_0 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.10fF
+C60 n_clk_1 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C61 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.04fF
+C62 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD 0.09fF
+C63 div_by_5_0/Q1_shift div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# -0.02fF
+C64 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/Q1 -0.03fF
+C65 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in s_0 -0.36fF
+C66 vdd inverter_min_x4_0/in 0.09fF
+C67 clk_pre vdd 0.17fF
+C68 s_0_n clk_1 4.82fF
+C69 s_0 in_a 0.30fF
+C70 prescaler_23_0/DFlipFlop_0/latch_diff_0/D n_clk_0 0.13fF
+C71 div_by_5_0/DFlipFlop_2/latch_diff_1/nD s_0 0.02fF
+C72 div_by_5_0/DFlipFlop_1/D s_0_n 0.19fF
+C73 s_0_n div_by_5_0/nQ2 0.05fF
+C74 in_b n_clk_1 0.05fF
+C75 div_by_5_0/DFlipFlop_0/Q s_0 0.02fF
+C76 n_clk_1 div_by_5_0/Q1 0.15fF
+C77 s_0_n div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.20fF
+C78 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_clk_1 0.14fF
+C79 s_0_n div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.04fF
+C80 div_by_5_0/DFlipFlop_0/latch_diff_0/nD clk_1 0.08fF
+C81 s_0_n div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out -0.01fF
+C82 s_0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.12fF
+C83 vdd n_clk_0 0.25fF
+C84 s_0 clk_out_mux21 0.68fF
+C85 s_1 s_1_n 0.39fF
+C86 div_by_5_0/DFlipFlop_1/latch_diff_1/D s_0 0.05fF
+C87 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out s_0 0.30fF
+C88 out clk_2 0.05fF
+C89 s_0 div_by_5_0/Q1 0.04fF
+C90 s_0 div_by_5_0/Q1_shift 0.05fF
+C91 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.24fF
+C92 s_0_n div_by_5_0/nQ0 0.05fF
+C93 in_a clk_1 0.05fF
+C94 n_clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/D 0.09fF
+C95 s_0_n div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.29fF
+C96 s_0_n n_clk_0 0.31fF
+C97 s_0_n vdd 2.76fF
+C98 s_0_n div_by_5_0/DFlipFlop_2/nQ 0.04fF
+C99 s_0 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.05fF
+C100 div_by_5_0/Q0 vdd 0.05fF
+C101 div_by_5_0/DFlipFlop_1/latch_diff_1/nD s_0 0.02fF
+C102 s_0_n div_by_5_0/DFlipFlop_3/nQ 0.24fF
+C103 div_by_5_0/DFlipFlop_0/D n_clk_1 0.21fF
+C104 clk_0 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD 0.09fF
+C105 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_clk_0 0.14fF
+C106 s_0_n div_by_5_0/Q0 0.24fF
+C107 vdd clk_5 0.06fF
+C108 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_clk_1 0.06fF
+C109 clk_pre prescaler_23_0/nCLK_23 0.03fF
+C110 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_clk_1 0.08fF
+C111 s_0_n div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.05fF
+C112 clk_pre clk_out_mux21 1.19fF
+C113 div_by_5_0/DFlipFlop_0/D s_0 0.03fF
+C114 s_0_n div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.20fF
+C115 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C116 s_0_n div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.17fF
+C117 s_0_n clk_5 0.56fF
+C118 s_0 div_by_5_0/DFlipFlop_2/D 0.03fF
+C119 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C120 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C121 prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C122 prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C123 prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C124 prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C125 prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C126 prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C127 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C128 prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C129 prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C130 prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C131 prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C132 prescaler_23_0/Q2_d vss -0.69fF
+C133 prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C134 prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C135 prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C136 prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C137 prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C138 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C139 prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C140 prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C141 prescaler_23_0/Q2 vss 0.55fF
+C142 prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C143 prescaler_23_0/Q1 vss 0.07fF
+C144 prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C145 n_clk_0 vss -5.72fF
+C146 prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C147 prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C148 prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C149 clk_0 vss 0.74fF
+C150 prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C151 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C152 prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C153 prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C154 prescaler_23_0/nCLK_23 vss -1.02fF
+C155 prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C156 prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C157 prescaler_23_0/MC vss 1.07fF
+C158 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C159 prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C160 in_b vss 2.26fF
+C161 s_0_n vss -2.65fF
+C162 in_a vss 2.25fF
+C163 s_0 vss 5.73fF
+C164 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C165 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C166 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C167 div_by_5_0/Q1_shift vss -0.36fF
+C168 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C169 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C170 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C171 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C172 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C173 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C174 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C175 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C176 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C177 div_by_5_0/Q1 vss 4.35fF
+C178 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C179 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C180 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C181 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C182 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C183 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C184 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C185 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C186 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C187 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C188 div_by_5_0/Q0 vss 0.29fF
+C189 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C190 div_by_5_0/nQ0 vss 0.99fF
+C191 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C192 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C193 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C194 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C195 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C196 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C197 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C198 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C199 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C200 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C201 n_clk_1 vss -0.44fF
+C202 div_by_5_0/nQ2 vss 1.38fF
+C203 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C204 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C205 clk_1 vss -1.17fF
+C206 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C207 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C208 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C209 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C210 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C211 vdd vss 355.84fF
+C212 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C213 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C214 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C215 s_1_n vss 1.15fF
+C216 out vss 1.17fF
+C217 clk_d vss 0.79fF
+C218 s_1 vss 2.97fF
+C219 inverter_min_x4_0/in vss 2.77fF
+C220 clk_5 vss 0.10fF
+C221 clk_out_mux21 vss 5.62fF
+C222 clk_pre vss 1.31fF
+C223 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C224 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C225 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C226 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C227 clk_2 vss 3.57fF
+C228 div_by_2_0/o1 vss 2.20fF
+C229 div_by_2_0/nCLK_2 vss 1.04fF
+C230 div_by_2_0/o2 vss 2.08fF
+C231 div_by_2_0/out_div vss -0.80fF
+C232 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C233 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C234 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C235 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C236 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C237 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C238 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C239 div_by_2_0/nout_div vss 2.62fF
+C240 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+.ends
+
.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_15_n150# a_n33_n238# 0.02fF
-C1 a_n73_n150# a_n33_n238# 0.02fF
+C0 a_n33_n238# a_n73_n150# 0.02fF
+C1 a_15_n150# a_n33_n238# 0.02fF
C2 a_15_n150# a_n73_n150# 0.51fF
C3 a_15_n150# w_n211_n360# 0.23fF
C4 a_n73_n150# w_n211_n360# 0.23fF
@@ -5287,12 +6286,12 @@
.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 w_n211_n369# a_n73_n150# 0.20fF
-C1 a_15_n150# a_n73_n150# 0.51fF
+C0 a_15_n150# w_n211_n369# 0.20fF
+C1 a_15_n150# a_n33_181# 0.01fF
C2 w_n211_n369# a_n33_181# 0.05fF
-C3 a_n33_181# a_15_n150# 0.01fF
-C4 a_n33_181# a_n73_n150# 0.01fF
-C5 w_n211_n369# a_15_n150# 0.20fF
+C3 a_n73_n150# a_15_n150# 0.51fF
+C4 a_n73_n150# w_n211_n369# 0.20fF
+C5 a_n73_n150# a_n33_181# 0.01fF
C6 a_15_n150# VSUBS 0.03fF
C7 a_n73_n150# VSUBS 0.03fF
C8 a_n33_181# VSUBS 0.13fF
@@ -5312,51 +6311,51 @@
X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_63_n150# a_255_n150# 0.16fF
-C1 a_63_n150# a_n129_n150# 0.16fF
-C2 a_n417_n150# a_n509_n150# 0.43fF
-C3 a_n509_n150# a_n225_n150# 0.10fF
-C4 a_255_n150# a_351_n150# 0.43fF
-C5 a_n417_n150# a_n129_n150# 0.10fF
-C6 a_n129_n150# a_n225_n150# 0.43fF
-C7 a_n33_n150# a_n321_n150# 0.10fF
-C8 a_63_n150# a_n225_n150# 0.10fF
-C9 a_63_n150# a_351_n150# 0.10fF
-C10 a_n417_n150# a_n225_n150# 0.16fF
-C11 a_159_n150# a_n465_172# 0.10fF
-C12 a_n33_n150# a_n465_172# 0.10fF
-C13 a_447_n150# a_n465_172# 0.01fF
-C14 a_159_n150# a_255_n150# 0.43fF
-C15 a_n33_n150# a_255_n150# 0.10fF
-C16 a_159_n150# a_n129_n150# 0.10fF
-C17 a_447_n150# a_255_n150# 0.16fF
-C18 a_n33_n150# a_n129_n150# 0.43fF
-C19 a_n465_172# a_n321_n150# 0.10fF
-C20 a_63_n150# a_159_n150# 0.43fF
-C21 a_159_n150# a_n225_n150# 0.07fF
-C22 a_63_n150# a_n33_n150# 0.43fF
-C23 a_159_n150# a_351_n150# 0.16fF
-C24 a_n33_n150# a_n417_n150# 0.07fF
-C25 a_63_n150# a_447_n150# 0.07fF
-C26 a_n33_n150# a_n225_n150# 0.16fF
-C27 a_n509_n150# a_n321_n150# 0.16fF
-C28 a_n33_n150# a_351_n150# 0.07fF
-C29 a_n129_n150# a_n321_n150# 0.16fF
-C30 a_447_n150# a_351_n150# 0.43fF
-C31 a_63_n150# a_n321_n150# 0.07fF
-C32 a_n417_n150# a_n321_n150# 0.43fF
-C33 a_n321_n150# a_n225_n150# 0.43fF
-C34 a_n465_172# a_255_n150# 0.10fF
-C35 a_n465_172# a_n509_n150# 0.01fF
-C36 a_n465_172# a_n129_n150# 0.10fF
-C37 a_255_n150# a_n129_n150# 0.07fF
-C38 a_63_n150# a_n465_172# 0.10fF
-C39 a_n509_n150# a_n129_n150# 0.07fF
-C40 a_159_n150# a_n33_n150# 0.16fF
-C41 a_n417_n150# a_n465_172# 0.10fF
-C42 a_n465_172# a_n225_n150# 0.10fF
-C43 a_159_n150# a_447_n150# 0.10fF
-C44 a_n465_172# a_351_n150# 0.10fF
+C0 a_n225_n150# a_n33_n150# 0.16fF
+C1 a_n129_n150# a_255_n150# 0.07fF
+C2 a_n321_n150# a_n465_172# 0.10fF
+C3 a_n321_n150# a_n129_n150# 0.16fF
+C4 a_n465_172# a_n129_n150# 0.10fF
+C5 a_n321_n150# a_n509_n150# 0.16fF
+C6 a_255_n150# a_63_n150# 0.16fF
+C7 a_n417_n150# a_n33_n150# 0.07fF
+C8 a_n465_172# a_n509_n150# 0.01fF
+C9 a_n129_n150# a_n509_n150# 0.07fF
+C10 a_n321_n150# a_63_n150# 0.07fF
+C11 a_159_n150# a_351_n150# 0.16fF
+C12 a_n465_172# a_63_n150# 0.10fF
+C13 a_n129_n150# a_63_n150# 0.16fF
+C14 a_159_n150# a_447_n150# 0.10fF
+C15 a_n225_n150# a_n321_n150# 0.43fF
+C16 a_159_n150# a_n33_n150# 0.16fF
+C17 a_n225_n150# a_n465_172# 0.10fF
+C18 a_n225_n150# a_n129_n150# 0.43fF
+C19 a_351_n150# a_447_n150# 0.43fF
+C20 a_n225_n150# a_n509_n150# 0.10fF
+C21 a_n33_n150# a_351_n150# 0.07fF
+C22 a_n417_n150# a_n321_n150# 0.43fF
+C23 a_n225_n150# a_63_n150# 0.10fF
+C24 a_n417_n150# a_n465_172# 0.10fF
+C25 a_n417_n150# a_n129_n150# 0.10fF
+C26 a_159_n150# a_255_n150# 0.43fF
+C27 a_n417_n150# a_n509_n150# 0.43fF
+C28 a_159_n150# a_n465_172# 0.10fF
+C29 a_159_n150# a_n129_n150# 0.10fF
+C30 a_351_n150# a_255_n150# 0.43fF
+C31 a_447_n150# a_255_n150# 0.16fF
+C32 a_n33_n150# a_255_n150# 0.10fF
+C33 a_n417_n150# a_n225_n150# 0.16fF
+C34 a_n465_172# a_351_n150# 0.10fF
+C35 a_n465_172# a_447_n150# 0.01fF
+C36 a_n321_n150# a_n33_n150# 0.10fF
+C37 a_159_n150# a_63_n150# 0.43fF
+C38 a_n465_172# a_n33_n150# 0.10fF
+C39 a_n129_n150# a_n33_n150# 0.43fF
+C40 a_159_n150# a_n225_n150# 0.07fF
+C41 a_351_n150# a_63_n150# 0.10fF
+C42 a_447_n150# a_63_n150# 0.07fF
+C43 a_n33_n150# a_63_n150# 0.43fF
+C44 a_n465_172# a_255_n150# 0.10fF
C45 a_447_n150# w_n647_n360# 0.17fF
C46 a_351_n150# w_n647_n360# 0.10fF
C47 a_255_n150# w_n647_n360# 0.08fF
@@ -5384,61 +6383,61 @@
X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_n33_n150# a_63_n150# 0.43fF
-C1 a_n225_n150# a_n465_n247# 0.08fF
-C2 a_n225_n150# a_159_n150# 0.07fF
-C3 w_n647_n369# a_n509_n150# 0.14fF
-C4 w_n647_n369# a_447_n150# 0.14fF
-C5 a_n225_n150# a_63_n150# 0.10fF
-C6 a_n33_n150# a_n129_n150# 0.43fF
-C7 a_n225_n150# a_n129_n150# 0.43fF
-C8 w_n647_n369# a_n465_n247# 0.47fF
-C9 w_n647_n369# a_159_n150# 0.04fF
-C10 a_447_n150# a_255_n150# 0.16fF
-C11 a_n225_n150# a_n33_n150# 0.16fF
-C12 a_n417_n150# a_n321_n150# 0.43fF
-C13 w_n647_n369# a_63_n150# 0.02fF
-C14 a_n465_n247# a_255_n150# 0.08fF
-C15 a_255_n150# a_159_n150# 0.43fF
-C16 a_n509_n150# a_n321_n150# 0.16fF
-C17 w_n647_n369# a_n129_n150# 0.02fF
-C18 w_n647_n369# a_n33_n150# 0.02fF
-C19 a_255_n150# a_63_n150# 0.16fF
-C20 w_n647_n369# a_n225_n150# 0.04fF
-C21 a_255_n150# a_n129_n150# 0.07fF
-C22 a_n465_n247# a_n321_n150# 0.08fF
-C23 a_n33_n150# a_255_n150# 0.10fF
-C24 a_63_n150# a_n321_n150# 0.07fF
-C25 a_447_n150# a_351_n150# 0.43fF
-C26 a_n129_n150# a_n321_n150# 0.16fF
-C27 a_n509_n150# a_n417_n150# 0.43fF
-C28 a_n33_n150# a_n321_n150# 0.10fF
-C29 a_n465_n247# a_351_n150# 0.08fF
-C30 a_351_n150# a_159_n150# 0.16fF
-C31 a_351_n150# a_63_n150# 0.10fF
-C32 a_n225_n150# a_n321_n150# 0.43fF
-C33 w_n647_n369# a_255_n150# 0.05fF
-C34 a_n465_n247# a_n417_n150# 0.08fF
-C35 a_n33_n150# a_351_n150# 0.07fF
-C36 w_n647_n369# a_n321_n150# 0.05fF
-C37 a_447_n150# a_159_n150# 0.10fF
-C38 a_n417_n150# a_n129_n150# 0.10fF
-C39 a_n33_n150# a_n417_n150# 0.07fF
-C40 a_447_n150# a_63_n150# 0.07fF
-C41 a_n465_n247# a_159_n150# 0.08fF
-C42 a_n225_n150# a_n417_n150# 0.16fF
-C43 a_n509_n150# a_n129_n150# 0.07fF
-C44 a_n465_n247# a_63_n150# 0.08fF
-C45 a_63_n150# a_159_n150# 0.43fF
-C46 w_n647_n369# a_351_n150# 0.07fF
-C47 a_n225_n150# a_n509_n150# 0.10fF
-C48 a_n465_n247# a_n129_n150# 0.08fF
-C49 a_159_n150# a_n129_n150# 0.10fF
-C50 a_n33_n150# a_n465_n247# 0.08fF
-C51 a_n33_n150# a_159_n150# 0.16fF
-C52 w_n647_n369# a_n417_n150# 0.07fF
-C53 a_255_n150# a_351_n150# 0.43fF
-C54 a_63_n150# a_n129_n150# 0.16fF
+C0 a_255_n150# a_n33_n150# 0.10fF
+C1 a_63_n150# a_351_n150# 0.10fF
+C2 a_159_n150# a_n129_n150# 0.10fF
+C3 a_n129_n150# a_n225_n150# 0.43fF
+C4 a_63_n150# a_159_n150# 0.43fF
+C5 w_n647_n369# a_n321_n150# 0.05fF
+C6 a_n129_n150# a_n465_n247# 0.08fF
+C7 a_n129_n150# a_255_n150# 0.07fF
+C8 w_n647_n369# a_n509_n150# 0.14fF
+C9 w_n647_n369# a_447_n150# 0.14fF
+C10 a_63_n150# a_n225_n150# 0.10fF
+C11 a_n129_n150# a_n33_n150# 0.43fF
+C12 a_63_n150# a_n465_n247# 0.08fF
+C13 w_n647_n369# a_n417_n150# 0.07fF
+C14 a_n321_n150# a_n509_n150# 0.16fF
+C15 a_63_n150# a_255_n150# 0.16fF
+C16 w_n647_n369# a_351_n150# 0.07fF
+C17 a_n321_n150# a_n417_n150# 0.43fF
+C18 a_63_n150# a_n33_n150# 0.43fF
+C19 a_n509_n150# a_n417_n150# 0.43fF
+C20 a_447_n150# a_351_n150# 0.43fF
+C21 w_n647_n369# a_159_n150# 0.04fF
+C22 w_n647_n369# a_n225_n150# 0.04fF
+C23 a_159_n150# a_447_n150# 0.10fF
+C24 a_63_n150# a_n129_n150# 0.16fF
+C25 w_n647_n369# a_n465_n247# 0.47fF
+C26 a_n321_n150# a_n225_n150# 0.43fF
+C27 w_n647_n369# a_255_n150# 0.05fF
+C28 a_n321_n150# a_n465_n247# 0.08fF
+C29 a_159_n150# a_351_n150# 0.16fF
+C30 a_n225_n150# a_n509_n150# 0.10fF
+C31 w_n647_n369# a_n33_n150# 0.02fF
+C32 a_n225_n150# a_n417_n150# 0.16fF
+C33 a_n33_n150# a_n321_n150# 0.10fF
+C34 a_255_n150# a_447_n150# 0.16fF
+C35 a_n417_n150# a_n465_n247# 0.08fF
+C36 a_n465_n247# a_351_n150# 0.08fF
+C37 a_255_n150# a_351_n150# 0.43fF
+C38 a_n33_n150# a_n417_n150# 0.07fF
+C39 a_159_n150# a_n225_n150# 0.07fF
+C40 a_n33_n150# a_351_n150# 0.07fF
+C41 w_n647_n369# a_n129_n150# 0.02fF
+C42 a_159_n150# a_n465_n247# 0.08fF
+C43 a_n129_n150# a_n321_n150# 0.16fF
+C44 a_159_n150# a_255_n150# 0.43fF
+C45 a_63_n150# w_n647_n369# 0.02fF
+C46 a_n129_n150# a_n509_n150# 0.07fF
+C47 a_159_n150# a_n33_n150# 0.16fF
+C48 a_n225_n150# a_n465_n247# 0.08fF
+C49 a_63_n150# a_n321_n150# 0.07fF
+C50 a_n129_n150# a_n417_n150# 0.10fF
+C51 a_255_n150# a_n465_n247# 0.08fF
+C52 a_n33_n150# a_n225_n150# 0.16fF
+C53 a_63_n150# a_447_n150# 0.07fF
+C54 a_n33_n150# a_n465_n247# 0.08fF
C55 a_447_n150# VSUBS 0.03fF
C56 a_351_n150# VSUBS 0.03fF
C57 a_255_n150# VSUBS 0.03fF
@@ -5457,8 +6456,8 @@
.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
C0 a_n33_n99# a_n73_n11# 0.02fF
-C1 a_n73_n11# a_15_n11# 0.15fF
-C2 a_n33_n99# a_15_n11# 0.02fF
+C1 a_n33_n99# a_15_n11# 0.02fF
+C2 a_n73_n11# a_15_n11# 0.15fF
C3 a_15_n11# w_n211_n221# 0.09fF
C4 a_n73_n11# w_n211_n221# 0.09fF
C5 a_n33_n99# w_n211_n221# 0.17fF
@@ -5466,7 +6465,7 @@
.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
-C0 a_20_n106# a_n78_n106# 0.21fF
+C0 a_n78_n106# a_20_n106# 0.21fF
C1 a_20_n106# w_n216_n254# 0.14fF
C2 a_n78_n106# w_n216_n254# 0.14fF
C3 a_n33_66# w_n216_n254# 0.12fF
@@ -5475,9 +6474,9 @@
.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
+ a_20_n114#
X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
-C0 w_n216_n334# a_n78_n114# 0.20fF
-C1 w_n216_n334# a_20_n114# 0.20fF
-C2 a_20_n114# a_n78_n114# 0.42fF
+C0 w_n216_n334# a_20_n114# 0.20fF
+C1 w_n216_n334# a_n78_n114# 0.20fF
+C2 a_n78_n114# a_20_n114# 0.42fF
C3 a_20_n114# VSUBS 0.03fF
C4 a_n78_n114# VSUBS 0.03fF
C5 a_n33_n211# VSUBS 0.12fF
@@ -5487,11 +6486,11 @@
.subckt inverter_csvco in vbulkn out vbulkp vdd vss
Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
-C0 in vdd 0.01fF
-C1 vss in 0.01fF
-C2 out vbulkp 0.08fF
-C3 out in 0.11fF
-C4 vbulkp vdd 0.04fF
+C0 vss in 0.01fF
+C1 vbulkp out 0.08fF
+C2 out in 0.11fF
+C3 vbulkp vdd 0.04fF
+C4 vdd in 0.01fF
C5 vbulkp vbulkn 2.49fF
C6 out vbulkn 0.60fF
C7 vdd vbulkn 0.06fF
@@ -5499,8 +6498,8 @@
C9 vss vbulkn 0.17fF
.ends
-.subckt csvco_branch vctrl inverter_csvco_0/vdd in vbp cap_vco_0/t D0 out inverter_csvco_0/vss
-+ vss vdd
+.subckt csvco_branch vctrl inverter_csvco_0/vdd in vbp cap_vco_0/t D0 vss out vdd
++ inverter_csvco_0/vss
Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
+ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
+ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
@@ -5509,20 +6508,20 @@
+ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
-C0 vbp inverter_csvco_0/vdd 0.75fF
+C0 out D0 0.09fF
C1 in inverter_csvco_0/vdd 0.01fF
-C2 in inverter_csvco_0/vss 0.01fF
-C3 vdd cap_vco_0/t 0.04fF
-C4 vctrl inverter_csvco_0/vss 0.87fF
-C5 D0 out 0.09fF
-C6 cap_vco_0/t out 0.70fF
-C7 vdd vbp 1.21fF
-C8 vdd inverter_csvco_0/vdd 1.89fF
-C9 D0 inverter_csvco_0/vss 0.02fF
-C10 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
-C11 inverter_csvco_0/vdd out 0.02fF
-C12 inverter_csvco_0/vss out 0.03fF
-C13 in out 0.06fF
+C2 out inverter_csvco_0/vss 0.03fF
+C3 vdd inverter_csvco_0/vdd 1.89fF
+C4 inverter_csvco_0/vss vctrl 0.87fF
+C5 out inverter_csvco_0/vdd 0.02fF
+C6 cap_vco_0/t vdd 0.04fF
+C7 out cap_vco_0/t 0.70fF
+C8 vdd vbp 1.21fF
+C9 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C10 in inverter_csvco_0/vss 0.01fF
+C11 D0 inverter_csvco_0/vss 0.02fF
+C12 out in 0.06fF
+C13 vbp inverter_csvco_0/vdd 0.75fF
C14 out vss 0.93fF
C15 inverter_csvco_0/vdd vss 0.26fF
C16 in vss 0.69fF
@@ -5534,36 +6533,36 @@
C22 vctrl vss 3.06fF
.ends
-.subckt ring_osc csvco_branch_0/inverter_csvco_0/vdd vctrl csvco_branch_1/inverter_csvco_0/vdd
-+ csvco_branch_2/inverter_csvco_0/vdd vdd vss csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
+.subckt ring_osc csvco_branch_0/inverter_csvco_0/vdd vctrl vss csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch_2/inverter_csvco_0/vdd vdd csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
+ D0 csvco_branch_2/cap_vco_0/t out_vco
Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
+ sky130_fd_pr__pfet_01v8_4757AC
Xcsvco_branch_0 vctrl csvco_branch_0/inverter_csvco_0/vdd out_vco csvco_branch_2/vbp
-+ csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in csvco_branch_0/inverter_csvco_0/vss
-+ vss vdd csvco_branch
++ csvco_branch_0/cap_vco_0/t D0 vss csvco_branch_1/in vdd csvco_branch_0/inverter_csvco_0/vss
++ csvco_branch
Xcsvco_branch_2 vctrl csvco_branch_2/inverter_csvco_0/vdd csvco_branch_2/in csvco_branch_2/vbp
-+ csvco_branch_2/cap_vco_0/t D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd
++ csvco_branch_2/cap_vco_0/t D0 vss out_vco vdd csvco_branch_2/inverter_csvco_0/vss
+ csvco_branch
Xcsvco_branch_1 vctrl csvco_branch_1/inverter_csvco_0/vdd csvco_branch_1/in csvco_branch_2/vbp
-+ csvco_branch_1/cap_vco_0/t D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss
-+ vss vdd csvco_branch
-C0 vctrl csvco_branch_2/vbp 0.06fF
-C1 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
-C2 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
-C3 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
-C4 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
-C5 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
-C6 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
-C7 out_vco csvco_branch_2/in 0.58fF
-C8 D0 csvco_branch_1/inverter_csvco_0/vss 0.68fF
-C9 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
-C10 out_vco csvco_branch_1/in 0.76fF
-C11 vdd csvco_branch_2/vbp 1.49fF
-C12 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
-C13 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
-C14 D0 vctrl 4.41fF
++ csvco_branch_1/cap_vco_0/t D0 vss csvco_branch_2/in vdd csvco_branch_1/inverter_csvco_0/vss
++ csvco_branch
+C0 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C1 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
+C2 csvco_branch_1/in out_vco 0.76fF
+C3 csvco_branch_2/in out_vco 0.58fF
+C4 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C5 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss 0.06fF
+C6 csvco_branch_2/vbp vdd 1.49fF
+C7 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C8 csvco_branch_1/cap_vco_0/t out_vco 0.03fF
+C9 vctrl D0 4.41fF
+C10 csvco_branch_2/vbp vctrl 0.06fF
+C11 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C12 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
+C13 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C14 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
C15 csvco_branch_2/in vss 1.60fF
C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -5586,371 +6585,16 @@
Xinverter_min_x4_1 vdd out_div vss out_pad inverter_min_x4
Xinverter_min_x4_0 vdd o1 vss out_div inverter_min_x4
Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
-C0 vdd o1 0.09fF
-C1 out_div vdd 0.17fF
-C2 vdd out_pad 0.10fF
+C0 out_pad vdd 0.10fF
+C1 o1 vdd 0.09fF
+C2 out_div out_pad 0.15fF
C3 out_div o1 0.11fF
-C4 out_div out_pad 0.15fF
+C4 out_div vdd 0.17fF
C5 in_vco vss 0.83fF
C6 o1 vss 2.72fF
C7 vdd vss 14.54fF
-C8 out_div vss 3.00fF
-C9 out_pad vss 0.70fF
-.ends
-
-.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
-+ a_158_392#
-X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
-X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-C0 X B 0.13fF
-C1 B a_355_368# 0.08fF
-C2 B VGND 0.10fF
-C3 VPWR B 0.09fF
-C4 B A 0.28fF
-C5 B a_194_125# 0.57fF
-C6 a_194_125# a_158_392# 0.06fF
-C7 X a_355_368# 0.17fF
-C8 X VGND 0.28fF
-C9 VPWR X 0.07fF
-C10 VPWR a_355_368# 0.37fF
-C11 VPWR VGND 0.01fF
-C12 a_355_368# A 0.02fF
-C13 X a_194_125# 0.29fF
-C14 a_355_368# a_194_125# 0.51fF
-C15 VPWR VPB 0.06fF
-C16 VGND A 0.31fF
-C17 VPWR A 0.15fF
-C18 VGND a_194_125# 0.25fF
-C19 VPWR a_194_125# 0.33fF
-C20 a_194_125# A 0.18fF
-C21 VGND VNB 0.78fF
-C22 X VNB 0.21fF
-C23 VPWR VNB 0.78fF
-C24 B VNB 0.56fF
-C25 A VNB 0.70fF
-C26 VPB VNB 0.77fF
-C27 a_355_368# VNB 0.08fF
-C28 a_194_125# VNB 0.40fF
-.ends
-
-.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
-X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
-X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
-X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-C0 a_56_136# VPWR 0.57fF
-C1 A VPWR 0.07fF
-C2 B VGND 0.03fF
-C3 VPB VPWR 0.04fF
-C4 a_56_136# B 0.30fF
-C5 a_56_136# VGND 0.06fF
-C6 B A 0.08fF
-C7 VGND A 0.21fF
-C8 VPWR X 0.20fF
-C9 a_56_136# A 0.17fF
-C10 B X 0.02fF
-C11 B VPWR 0.02fF
-C12 VGND X 0.15fF
-C13 a_56_136# X 0.26fF
-C14 VGND VNB 0.50fF
-C15 X VNB 0.23fF
-C16 VPWR VNB 0.50fF
-C17 B VNB 0.24fF
-C18 A VNB 0.36fF
-C19 VPB VNB 0.48fF
-C20 a_56_136# VNB 0.38fF
-.ends
-
-.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
-X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-C0 A a_63_368# 0.28fF
-C1 VGND a_63_368# 0.27fF
-C2 X VPWR 0.18fF
-C3 X a_63_368# 0.33fF
-C4 X A 0.02fF
-C5 VGND X 0.16fF
-C6 VPWR VPB 0.04fF
-C7 B VPWR 0.01fF
-C8 B a_63_368# 0.14fF
-C9 B A 0.10fF
-C10 VGND B 0.11fF
-C11 a_152_368# a_63_368# 0.03fF
-C12 VPWR a_63_368# 0.29fF
-C13 VPWR A 0.05fF
-C14 VGND VNB 0.53fF
-C15 X VNB 0.24fF
-C16 A VNB 0.21fF
-C17 B VNB 0.31fF
-C18 VPWR VNB 0.46fF
-C19 VPB VNB 0.48fF
-C20 a_63_368# VNB 0.37fF
-.ends
-
-.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK DFlipFlop_0/latch_diff_1/nD
-+ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vdd vss Q0 CLK DFlipFlop_2/latch_diff_1/D
-+ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
-+ DFlipFlop_3/latch_diff_0/D nQ0 DFlipFlop_1/latch_diff_0/nD DFlipFlop_1/latch_diff_1/nD
-+ DFlipFlop_1/latch_diff_0/D CLK_5 nQ2 Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_1/latch_diff_1/D DFlipFlop_2/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
-+ DFlipFlop_0/latch_diff_0/nD sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_1/D
-+ DFlipFlop_2/nQ DFlipFlop_3/latch_diff_0/nD DFlipFlop_2/latch_diff_0/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_0/latch_diff_0/D sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D
-+ sky130_fd_sc_hs__or2_1_0/a_63_368# DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
-+ sky130_fd_sc_hs__xor2_1_0/a_194_125# sky130_fd_sc_hs__and2_1_0/a_143_136# DFlipFlop_2/latch_diff_0/nD
-Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
-+ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
-+ sky130_fd_sc_hs__xor2_1
-XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
-+ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 DFlipFlop_0/latch_diff_0/nD
-+ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/D
-+ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop
-XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss vdd DFlipFlop_2/latch_diff_1/D
-+ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
-+ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
-+ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop
-XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss vdd DFlipFlop_1/latch_diff_1/D
-+ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 DFlipFlop_1/latch_diff_0/nD
-+ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
-+ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop
-XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss vdd DFlipFlop_3/latch_diff_1/D
-+ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
-+ Q1_shift DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# Q1 DFlipFlop_3/latch_diff_0/D
-+ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out CLK DFlipFlop
-Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
-+ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
-Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
-+ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
-Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
-+ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
-C0 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
-C1 DFlipFlop_0/Q Q1 0.13fF
-C2 nQ0 Q0 0.33fF
-C3 nQ0 DFlipFlop_1/latch_diff_0/D 0.09fF
-C4 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
-C5 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
-C6 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
-C7 Q0 DFlipFlop_0/latch_diff_1/D 0.23fF
-C8 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
-C9 Q0 nQ2 0.23fF
-C10 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C11 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
-C12 Q0 nCLK 0.20fF
-C13 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
-C14 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
-C15 nQ0 DFlipFlop_1/latch_diff_0/m1_657_280# 0.25fF
-C16 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
-C17 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
-C18 Q0 vdd 5.33fF
-C19 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
-C20 Q0 Q1 9.65fF
-C21 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
-C22 nQ0 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.04fF
-C23 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
-C24 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
-C25 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
-C26 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
-C27 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
-C28 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
-C29 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
-C30 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
-C31 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
-C32 CLK DFlipFlop_1/D 0.21fF
-C33 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
-C34 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
-C35 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
-C36 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
-C37 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
-C38 vdd DFlipFlop_0/D 0.19fF
-C39 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
-C40 nQ0 CLK 0.19fF
-C41 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
-C42 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
-C43 Q0 DFlipFlop_2/D 0.25fF
-C44 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
-C45 Q1 DFlipFlop_0/D 0.13fF
-C46 nQ0 DFlipFlop_1/D 0.12fF
-C47 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
-C48 Q0 DFlipFlop_0/Q 0.21fF
-C49 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
-C50 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
-C51 CLK nQ2 0.17fF
-C52 CLK_5 vdd 0.15fF
-C53 DFlipFlop_3/nQ CLK 0.01fF
-C54 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
-C55 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
-C56 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
-C57 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
-C58 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
-C59 DFlipFlop_1/D nCLK 0.14fF
-C60 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
-C61 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
-C62 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
-C63 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
-C64 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
-C65 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
-C66 CLK vdd 0.41fF
-C67 DFlipFlop_2/nQ CLK 0.13fF
-C68 nQ0 nQ2 0.03fF
-C69 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C70 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
-C71 nQ0 nCLK 0.09fF
-C72 vdd DFlipFlop_1/D 0.25fF
-C73 CLK Q1 -0.10fF
-C74 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
-C75 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
-C76 DFlipFlop_3/nQ Q1_shift 0.04fF
-C77 nCLK nQ2 0.10fF
-C78 DFlipFlop_1/D Q1 0.03fF
-C79 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
-C80 DFlipFlop_3/nQ nCLK 0.02fF
-C81 Q1_shift sky130_fd_sc_hs__or2_1_0/a_63_368# -0.27fF
-C82 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
-C83 nQ0 vdd 0.11fF
-C84 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
-C85 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
-C86 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
-C87 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
-C88 DFlipFlop_2/latch_diff_1/m1_657_280# Q1 0.03fF
-C89 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
-C90 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
-C91 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
-C92 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
-C93 nQ0 Q1 0.06fF
-C94 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
-C95 vdd Q1_shift 0.10fF
-C96 vdd nQ2 0.04fF
-C97 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
-C98 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
-C99 DFlipFlop_3/nQ vdd 0.02fF
-C100 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
-C101 DFlipFlop_2/nQ nCLK 0.09fF
-C102 vdd nCLK 0.34fF
-C103 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
-C104 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
-C105 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
-C106 Q1 Q1_shift 0.36fF
-C107 Q1 nQ2 0.07fF
-C108 CLK DFlipFlop_2/D 0.14fF
-C109 DFlipFlop_3/nQ Q1 0.10fF
-C110 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
-C111 nCLK Q1 -0.01fF
-C112 nQ0 DFlipFlop_1/latch_diff_0/nD 0.08fF
-C113 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
-C114 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
-C115 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
-C116 CLK DFlipFlop_0/Q 0.08fF
-C117 DFlipFlop_2/nQ vdd 0.02fF
-C118 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
-C119 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
-C120 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
-C121 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
-C122 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
-C123 Q0 DFlipFlop_0/D 0.39fF
-C124 vdd Q1 9.49fF
-C125 DFlipFlop_2/nQ Q1 0.31fF
-C126 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
-C127 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
-C128 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
-C129 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
-C130 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
-C131 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
-C132 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
-C133 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
-C134 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
-C135 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
-C136 Q0 sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.26fF
-C137 nCLK DFlipFlop_2/D 0.41fF
-C138 DFlipFlop_0/latch_diff_1/nD Q1 0.10fF
-C139 DFlipFlop_0/Q nQ2 0.09fF
-C140 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
-C141 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
-C142 DFlipFlop_0/Q nCLK 0.11fF
-C143 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
-C144 Q0 CLK 0.08fF
-C145 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
-C146 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
-C147 vdd DFlipFlop_2/D 0.07fF
-C148 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
-C149 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
-C150 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
-C151 Q0 DFlipFlop_1/D 0.07fF
-C152 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
-C153 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
-C154 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
-C155 Q1 DFlipFlop_2/D 0.10fF
-C156 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
-C157 CLK_5 vss -0.18fF
-C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
-C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
-C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
-C161 DFlipFlop_3/nQ vss 0.52fF
-C162 Q1_shift vss -0.29fF
-C163 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
-C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
-C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
-C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
-C167 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
-C168 DFlipFlop_3/latch_diff_0/D vss 0.96fF
-C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
-C170 Q1 vss 8.55fF
-C171 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C172 nQ0 vss 3.42fF
-C173 Q0 vss 0.53fF
-C174 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
-C175 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C176 DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C177 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C178 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C179 DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C180 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
-C181 DFlipFlop_1/D vss 3.72fF
-C182 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
-C183 DFlipFlop_2/nQ vss 0.50fF
-C184 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
-C185 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
-C186 DFlipFlop_2/latch_diff_1/D vss -1.72fF
-C187 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C188 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
-C189 DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C190 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C191 DFlipFlop_2/D vss 5.34fF
-C192 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C193 nQ2 vss 2.05fF
-C194 DFlipFlop_0/Q vss -0.94fF
-C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
-C196 nCLK vss 0.96fF
-C197 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C200 CLK vss 0.20fF
-C201 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
-C202 DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C204 DFlipFlop_0/D vss 4.04fF
-C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
-C206 vdd vss 146.76fF
-C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
-C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+C8 out_pad vss 0.70fF
+C9 out_div vss 3.00fF
.ends
.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
@@ -5962,29 +6606,29 @@
X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_63_n125# a_n33_n125# 0.36fF
-C1 a_n255_n151# a_n159_n151# 0.02fF
-C2 a_n225_n125# a_n129_n125# 0.36fF
-C3 a_129_n151# a_225_n151# 0.02fF
-C4 a_255_n125# a_63_n125# 0.13fF
-C5 a_n129_n125# a_n33_n125# 0.36fF
-C6 a_33_n151# a_n63_n151# 0.02fF
-C7 a_63_n125# a_n317_n125# 0.06fF
-C8 a_129_n151# a_33_n151# 0.02fF
-C9 a_255_n125# a_n129_n125# 0.06fF
-C10 a_n225_n125# a_159_n125# 0.06fF
-C11 a_n33_n125# a_159_n125# 0.13fF
-C12 a_n129_n125# a_n317_n125# 0.13fF
-C13 a_n129_n125# a_63_n125# 0.13fF
-C14 a_n225_n125# a_n33_n125# 0.13fF
-C15 a_255_n125# a_159_n125# 0.36fF
-C16 a_63_n125# a_159_n125# 0.36fF
-C17 a_255_n125# a_n33_n125# 0.08fF
-C18 a_n225_n125# a_n317_n125# 0.36fF
-C19 a_n159_n151# a_n63_n151# 0.02fF
-C20 a_n33_n125# a_n317_n125# 0.08fF
-C21 a_n225_n125# a_63_n125# 0.08fF
-C22 a_n129_n125# a_159_n125# 0.08fF
+C0 a_n129_n125# a_159_n125# 0.08fF
+C1 a_n33_n125# a_255_n125# 0.08fF
+C2 a_159_n125# a_n225_n125# 0.06fF
+C3 a_n129_n125# a_n33_n125# 0.36fF
+C4 a_n129_n125# a_n317_n125# 0.13fF
+C5 a_n225_n125# a_n33_n125# 0.13fF
+C6 a_n317_n125# a_n225_n125# 0.36fF
+C7 a_n63_n151# a_n159_n151# 0.02fF
+C8 a_63_n125# a_255_n125# 0.13fF
+C9 a_159_n125# a_n33_n125# 0.13fF
+C10 a_n129_n125# a_63_n125# 0.13fF
+C11 a_n225_n125# a_63_n125# 0.08fF
+C12 a_n159_n151# a_n255_n151# 0.02fF
+C13 a_n129_n125# a_255_n125# 0.06fF
+C14 a_129_n151# a_225_n151# 0.02fF
+C15 a_n317_n125# a_n33_n125# 0.08fF
+C16 a_n63_n151# a_33_n151# 0.02fF
+C17 a_n129_n125# a_n225_n125# 0.36fF
+C18 a_159_n125# a_63_n125# 0.36fF
+C19 a_159_n125# a_255_n125# 0.36fF
+C20 a_n33_n125# a_63_n125# 0.36fF
+C21 a_129_n151# a_33_n151# 0.02fF
+C22 a_n317_n125# a_63_n125# 0.06fF
C23 a_255_n125# w_n455_n335# 0.14fF
C24 a_159_n125# w_n455_n335# 0.08fF
C25 a_63_n125# w_n455_n335# 0.07fF
@@ -6009,36 +6653,36 @@
X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 w_n455_n344# a_n33_n125# 0.05fF
-C1 a_159_n125# a_63_n125# 0.36fF
-C2 a_n225_n125# a_159_n125# 0.06fF
-C3 a_255_n125# a_159_n125# 0.36fF
-C4 a_n225_n125# a_63_n125# 0.08fF
-C5 a_255_n125# a_63_n125# 0.13fF
-C6 w_n455_n344# a_n317_n125# 0.11fF
-C7 a_n129_n125# a_n33_n125# 0.36fF
-C8 a_n33_n125# a_159_n125# 0.13fF
-C9 a_n129_n125# a_n317_n125# 0.13fF
-C10 a_n33_n125# a_63_n125# 0.36fF
-C11 a_n225_n125# a_n33_n125# 0.13fF
-C12 w_n455_n344# a_n129_n125# 0.04fF
-C13 a_255_n125# a_n33_n125# 0.08fF
+C0 a_n129_n125# a_159_n125# 0.08fF
+C1 a_n225_n125# a_n317_n125# 0.36fF
+C2 w_n455_n344# a_159_n125# 0.06fF
+C3 a_n225_n125# a_159_n125# 0.06fF
+C4 a_255_n125# a_63_n125# 0.13fF
+C5 a_63_n125# a_n33_n125# 0.36fF
+C6 a_63_n125# a_n129_n125# 0.13fF
+C7 w_n455_n344# a_63_n125# 0.04fF
+C8 a_255_n125# a_n33_n125# 0.08fF
+C9 a_n225_n125# a_63_n125# 0.08fF
+C10 a_255_n125# a_n129_n125# 0.06fF
+C11 a_n129_n125# a_n33_n125# 0.36fF
+C12 w_n455_n344# a_255_n125# 0.11fF
+C13 w_n455_n344# a_n33_n125# 0.05fF
C14 a_n317_n125# a_63_n125# 0.06fF
-C15 w_n455_n344# a_159_n125# 0.06fF
-C16 a_n225_n125# a_n317_n125# 0.36fF
-C17 a_n159_n154# a_n63_n154# 0.02fF
-C18 w_n455_n344# a_63_n125# 0.04fF
-C19 a_n225_n125# w_n455_n344# 0.06fF
-C20 w_n455_n344# a_255_n125# 0.11fF
-C21 a_129_n154# a_33_n154# 0.02fF
-C22 a_n159_n154# a_n255_n154# 0.02fF
-C23 a_n129_n125# a_159_n125# 0.08fF
-C24 a_n129_n125# a_63_n125# 0.13fF
-C25 a_33_n154# a_n63_n154# 0.02fF
-C26 a_n225_n125# a_n129_n125# 0.36fF
-C27 a_n317_n125# a_n33_n125# 0.08fF
-C28 a_225_n154# a_129_n154# 0.02fF
-C29 a_255_n125# a_n129_n125# 0.06fF
+C15 w_n455_n344# a_n129_n125# 0.04fF
+C16 a_n225_n125# a_n33_n125# 0.13fF
+C17 a_225_n154# a_129_n154# 0.02fF
+C18 a_63_n125# a_159_n125# 0.36fF
+C19 a_n63_n154# a_n159_n154# 0.02fF
+C20 a_n317_n125# a_n33_n125# 0.08fF
+C21 a_n225_n125# a_n129_n125# 0.36fF
+C22 a_n225_n125# w_n455_n344# 0.06fF
+C23 a_n63_n154# a_33_n154# 0.02fF
+C24 a_129_n154# a_33_n154# 0.02fF
+C25 a_n317_n125# a_n129_n125# 0.13fF
+C26 a_255_n125# a_159_n125# 0.36fF
+C27 w_n455_n344# a_n317_n125# 0.11fF
+C28 a_159_n125# a_n33_n125# 0.13fF
+C29 a_n255_n154# a_n159_n154# 0.02fF
C30 a_255_n125# VSUBS 0.03fF
C31 a_159_n125# VSUBS 0.03fF
C32 a_63_n125# VSUBS 0.03fF
@@ -6061,34 +6705,34 @@
Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
+ in sky130_fd_pr__pfet_01v8_XJXT7S
C0 in vdd 0.04fF
-C1 out vdd 0.29fF
-C2 out in 0.85fF
+C1 out in 0.85fF
+C2 out vdd 0.29fF
C3 vdd vss 5.90fF
C4 out vss 1.30fF
C5 in vss 1.82fF
.ends
-.subckt pfd_cp_interface vss vdd inverter_cp_x1_0/out inverter_cp_x1_2/in Down QA
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
+ QB nDown Up nUp
Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
-Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xtrans_gate_0 nDown vss inverter_cp_x1_0/out vdd trans_gate
Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
-Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
-C0 vdd Down 0.09fF
-C1 nDown inverter_cp_x1_0/out 0.11fF
-C2 nDown vdd 0.80fF
-C3 vdd inverter_cp_x1_0/out 0.25fF
-C4 vdd QB 0.02fF
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 nDown inverter_cp_x1_0/out 0.11fF
+C1 inverter_cp_x1_0/out Down 0.12fF
+C2 inverter_cp_x1_0/out vdd 0.25fF
+C3 vdd nUp 0.14fF
+C4 Up nUp 0.20fF
C5 vdd inverter_cp_x1_2/in 0.42fF
-C6 vdd Up 0.60fF
-C7 inverter_cp_x1_2/in Up 0.12fF
-C8 nUp vdd 0.14fF
-C9 nUp Up 0.20fF
-C10 vdd QA 0.02fF
-C11 nDown Down 0.23fF
-C12 Down inverter_cp_x1_0/out 0.12fF
+C6 nDown Down 0.23fF
+C7 nDown vdd 0.80fF
+C8 vdd Down 0.09fF
+C9 Up inverter_cp_x1_2/in 0.12fF
+C10 Up vdd 0.60fF
+C11 vdd QB 0.02fF
+C12 vdd QA 0.02fF
C13 inverter_cp_x1_2/in vss 2.01fF
C14 QA vss 1.09fF
C15 inverter_cp_x1_0/out vss 2.00fF
@@ -6106,22 +6750,22 @@
X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
-C0 a_n129_n90# a_63_n90# 0.09fF
-C1 a_n221_n90# a_159_n90# 0.04fF
-C2 w_n359_n309# a_n221_n90# 0.09fF
-C3 a_n221_n90# a_n33_n90# 0.09fF
-C4 a_n221_n90# a_n129_n90# 0.26fF
-C5 a_n221_n90# a_63_n90# 0.06fF
+C0 a_63_n90# a_159_n90# 0.26fF
+C1 a_n33_n90# a_n129_n90# 0.26fF
+C2 a_159_n90# w_n359_n309# 0.09fF
+C3 a_159_n90# a_n129_n90# 0.06fF
+C4 a_63_n90# a_n221_n90# 0.06fF
+C5 a_n63_n116# a_n159_n207# 0.12fF
C6 a_n33_n90# a_159_n90# 0.09fF
-C7 w_n359_n309# a_159_n90# 0.09fF
-C8 a_n129_n90# a_159_n90# 0.06fF
-C9 a_63_n90# a_159_n90# 0.26fF
-C10 a_n63_n116# a_n159_n207# 0.12fF
-C11 w_n359_n309# a_n33_n90# 0.05fF
-C12 a_n129_n90# a_n33_n90# 0.26fF
+C7 a_n221_n90# w_n359_n309# 0.09fF
+C8 a_63_n90# w_n359_n309# 0.06fF
+C9 a_n221_n90# a_n129_n90# 0.26fF
+C10 a_63_n90# a_n129_n90# 0.09fF
+C11 a_n33_n90# a_n221_n90# 0.09fF
+C12 a_63_n90# a_n33_n90# 0.26fF
C13 w_n359_n309# a_n129_n90# 0.06fF
-C14 a_n33_n90# a_63_n90# 0.26fF
-C15 w_n359_n309# a_63_n90# 0.06fF
+C14 a_n33_n90# w_n359_n309# 0.05fF
+C15 a_n221_n90# a_159_n90# 0.04fF
C16 a_159_n90# VSUBS 0.03fF
C17 a_63_n90# VSUBS 0.03fF
C18 a_n33_n90# VSUBS 0.03fF
@@ -6136,10 +6780,10 @@
+ a_n125_n45# a_63_n45#
X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
-C0 a_63_n45# a_n33_n45# 0.13fF
-C1 a_n129_71# a_33_n71# 0.04fF
-C2 a_n125_n45# a_n33_n45# 0.13fF
-C3 a_63_n45# a_n125_n45# 0.05fF
+C0 a_n129_71# a_33_n71# 0.04fF
+C1 a_n125_n45# a_63_n45# 0.05fF
+C2 a_n33_n45# a_n125_n45# 0.13fF
+C3 a_n33_n45# a_63_n45# 0.13fF
C4 a_63_n45# w_n263_n255# 0.04fF
C5 a_n33_n45# w_n263_n255# 0.04fF
C6 a_n125_n45# w_n263_n255# 0.04fF
@@ -6147,19 +6791,19 @@
C8 a_n129_71# w_n263_n255# 0.14fF
.ends
-.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
-+ vss vdd A B
+.subckt nor_pfd vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss A B
Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
+ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
-C0 out vdd 0.11fF
-C1 out A 0.06fF
-C2 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C0 A B 0.24fF
+C1 out vdd 0.11fF
+C2 A out 0.06fF
C3 A vdd 0.09fF
-C4 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
-C5 B out 0.40fF
-C6 B A 0.24fF
-C7 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C4 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
+C5 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out 0.08fF
+C6 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
+C7 out B 0.40fF
C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C9 out vss 0.45fF
C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
@@ -6168,46 +6812,46 @@
C13 vdd vss 3.79fF
.ends
-.subckt dff_pfd vdd vss nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
-Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
-+ vss vdd CLK Q nor_pfd
-Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
-+ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
-Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
-+ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
-Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
-+ vss vdd nor_pfd_3/A Reset nor_pfd
-C0 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
-C1 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
-C2 nor_pfd_3/A vdd 0.09fF
-C3 Reset nor_pfd_2/B 0.43fF
-C4 nor_pfd_3/A nor_pfd_2/B 0.58fF
-C5 nor_pfd_2/A nor_pfd_3/A 0.38fF
-C6 vdd Q 0.08fF
-C7 nor_pfd_2/B Q 2.22fF
-C8 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
-C9 nor_pfd_2/A Q 1.38fF
-C10 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
-C11 CLK Q 0.04fF
-C12 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
-C13 nor_pfd_3/A Reset 0.12fF
-C14 nor_pfd_2/B vdd 0.02fF
-C15 nor_pfd_2/A vdd -0.01fF
-C16 nor_pfd_2/A nor_pfd_2/B 0.05fF
-C17 Reset Q 0.14fF
-C18 nor_pfd_3/A Q 0.98fF
-C19 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+.subckt dff_pfd vdd vss nor_pfd_2/A Q CLK nor_pfd_3/A Reset nor_pfd_2/B
+Xnor_pfd_0 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss CLK Q nor_pfd
+Xnor_pfd_1 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_3/A Reset nor_pfd
+C0 nor_pfd_3/A Reset 0.12fF
+C1 nor_pfd_2/B Reset 0.43fF
+C2 nor_pfd_3/A Q 0.98fF
+C3 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C4 nor_pfd_2/B Q 2.22fF
+C5 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C6 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C7 vdd Q 0.08fF
+C8 nor_pfd_2/A vdd -0.01fF
+C9 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C10 Reset Q 0.14fF
+C11 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C12 CLK Q 0.04fF
+C13 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C14 nor_pfd_2/A Q 1.38fF
+C15 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C16 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C17 vdd nor_pfd_3/A 0.09fF
+C18 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C19 vdd nor_pfd_2/B 0.02fF
C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C21 nor_pfd_2/B vss 1.42fF
C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C23 Reset vss 1.48fF
-C24 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C26 nor_pfd_2/A vss 2.56fF
-C27 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C28 Q vss 2.77fF
-C29 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C30 nor_pfd_3/A vss 3.16fF
+C23 nor_pfd_3/A vss 3.16fF
+C24 Reset vss 1.48fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C27 nor_pfd_2/A vss 2.56fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C31 vdd vss 16.42fF
C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
@@ -6220,16 +6864,16 @@
X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
-C0 a_159_n45# a_n221_n45# 0.02fF
-C1 a_63_n45# a_n33_n45# 0.13fF
-C2 a_n129_n45# a_63_n45# 0.05fF
-C3 a_n129_n45# a_n33_n45# 0.13fF
-C4 a_n221_n45# a_63_n45# 0.03fF
-C5 a_n221_n45# a_n33_n45# 0.05fF
-C6 a_n129_n45# a_n221_n45# 0.13fF
-C7 a_159_n45# a_63_n45# 0.13fF
+C0 a_n129_n45# a_n221_n45# 0.13fF
+C1 a_n129_n45# a_159_n45# 0.03fF
+C2 a_159_n45# a_n221_n45# 0.02fF
+C3 a_n129_n45# a_63_n45# 0.05fF
+C4 a_63_n45# a_n221_n45# 0.03fF
+C5 a_n129_n45# a_n33_n45# 0.13fF
+C6 a_63_n45# a_159_n45# 0.13fF
+C7 a_n221_n45# a_n33_n45# 0.05fF
C8 a_159_n45# a_n33_n45# 0.05fF
-C9 a_159_n45# a_n129_n45# 0.03fF
+C9 a_63_n45# a_n33_n45# 0.13fF
C10 a_n63_n71# a_n159_n173# 0.10fF
C11 a_159_n45# w_n359_n255# 0.04fF
C12 a_63_n45# w_n359_n255# 0.05fF
@@ -6244,10 +6888,10 @@
+ a_n33_n90# w_n263_n309#
X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
-C0 a_n99_n187# a_33_n187# 0.04fF
-C1 a_n125_n90# a_63_n90# 0.09fF
-C2 a_n33_n90# a_63_n90# 0.26fF
-C3 a_n33_n90# a_n125_n90# 0.26fF
+C0 a_n125_n90# a_63_n90# 0.09fF
+C1 a_33_n187# a_n99_n187# 0.04fF
+C2 a_n33_n90# a_n125_n90# 0.26fF
+C3 a_n33_n90# a_63_n90# 0.26fF
C4 a_63_n90# VSUBS 0.03fF
C5 a_n33_n90# VSUBS 0.03fF
C6 a_n125_n90# VSUBS 0.03fF
@@ -6266,9 +6910,9 @@
.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
-C0 a_n73_n90# a_15_n90# 0.31fF
-C1 a_15_n90# w_n211_n309# 0.09fF
-C2 a_n73_n90# w_n211_n309# 0.04fF
+C0 w_n211_n309# a_15_n90# 0.09fF
+C1 a_15_n90# a_n73_n90# 0.31fF
+C2 w_n211_n309# a_n73_n90# 0.04fF
C3 a_15_n90# VSUBS 0.03fF
C4 a_n73_n90# VSUBS 0.03fF
C5 a_n51_n187# VSUBS 0.12fF
@@ -6281,16 +6925,16 @@
Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
-C0 A vdd 0.05fF
-C1 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
-C2 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
-C3 out vdd 0.10fF
-C4 B A 0.33fF
-C5 A a_656_410# 0.04fF
-C6 vdd a_656_410# 0.20fF
-C7 out a_656_410# 0.20fF
-C8 B a_656_410# 0.30fF
-C9 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
+C0 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
+C1 A vdd 0.05fF
+C2 out vdd 0.10fF
+C3 a_656_410# A 0.04fF
+C4 a_656_410# out 0.20fF
+C5 a_656_410# B 0.30fF
+C6 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C7 a_656_410# vdd 0.20fF
+C8 B A 0.33fF
+C9 out sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.03fF
C10 vdd vss 4.85fF
C11 out vss 0.47fF
C12 a_656_410# vss 1.00fF
@@ -6300,230 +6944,538 @@
C16 B vss 0.95fF
.ends
-.subckt PFD vss vdd Down Up A B Reset
-Xdff_pfd_0 vdd vss dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
-+ Reset dff_pfd
-Xdff_pfd_1 vdd vss dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
-+ Reset dff_pfd
+.subckt PFD vss vdd Reset Down Up A B
+Xdff_pfd_0 vdd vss dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A Reset dff_pfd_0/nor_pfd_2/B
++ dff_pfd
+Xdff_pfd_1 vdd vss dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A Reset dff_pfd_1/nor_pfd_2/B
++ dff_pfd
Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
-C0 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
-C1 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
-C2 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
-C3 vdd Up 1.62fF
-C4 Down vdd 0.08fF
-C5 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
-C6 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
-C7 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
-C8 Down Up 0.06fF
-C9 vdd Reset 0.02fF
+C0 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C1 Up vdd 1.62fF
+C2 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
+C3 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C4 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C5 Reset vdd 0.02fF
+C6 Down vdd 0.08fF
+C7 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
+C8 dff_pfd_1/nor_pfd_2/B vdd 0.04fF
+C9 Up Down 0.06fF
C10 and_pfd_0/a_656_410# vss 0.99fF
C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C16 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C18 dff_pfd_1/nor_pfd_2/A vss 2.56fF
-C19 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C20 Down vss 3.74fF
-C21 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C22 dff_pfd_1/nor_pfd_3/A vss 3.14fF
-C23 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C25 B vss 1.07fF
-C26 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C27 dff_pfd_0/nor_pfd_2/B vss 1.40fF
-C28 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C29 Reset vss 3.85fF
-C30 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C31 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C32 dff_pfd_0/nor_pfd_2/A vss 2.56fF
-C33 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C34 Up vss 3.18fF
-C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C36 dff_pfd_0/nor_pfd_3/A vss 3.14fF
-C37 vdd vss 44.73fF
+C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 3.74fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C31 Reset vss 3.85fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C36 Up vss 3.18fF
+C37 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C40 A vss 1.07fF
.ends
-.subckt top_pll_v1 vco_vctrl vdd pswitch ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
-+ charge_pump_0/w_2544_775# ring_osc_0/csvco_branch_2/vbp biasp in_ref Down vss w_13905_n238#
-+ vco_D0 buffer_salida_0/a_3996_n100# ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
-+ QA charge_pump_0/w_1008_774# iref_cp ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
-+ out_to_div nDown out_to_pad Up nUp
+.subckt top_pll_v3 clk_d vdd s_0 charge_pump_0/w_2544_775# out_by_2 s_0_n in_ref ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ buffer_salida_0/a_3996_n100# vss vco_vctrl s_1 ring_osc_0/csvco_branch_2/vbp lf_vc
++ vco_D0 lf_D0 buffer_salida_0/a_678_n100# ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ loop_filter_v2_0/cap3_loop_filter_0/in charge_pump_0/w_1008_774# iref_cp ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
++ Down out_to_div clk_1 out_div nDown s_1_n out_to_pad MC Up clk_0 freq_div_0/prescaler_23_0/nCLK_23
++ biasp nUp n_clk_0
+Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
++ iref_cp nDown Up charge_pump_0/w_1008_774# vss charge_pump
+Xdiv_by_2_0 vss vdd n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2
++ n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_2
+Xloop_filter_v2_0 lf_vc lf_D0 vco_vctrl vss loop_filter_v2_0/cap3_loop_filter_0/in
++ loop_filter_v2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# buffer_salida_0/a_3996_n100# out_to_pad
++ vdd out_to_buffer vss buffer_salida
+Xfreq_div_0 clk_0 vss out_by_2 n_clk_0 vdd freq_div_0/prescaler_23_0/Q2 s_0 s_1_n
++ s_1 freq_div_0/prescaler_23_0/nCLK_23 MC clk_d freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280#
++ s_0_n clk_pre freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD clk_1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ clk_out_mux21 n_clk_1 out_div freq_div_0/div_by_5_0/Q1 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ clk_2_f n_out_by_2 clk_5 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D
++ freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D freq_div
+Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl vss ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd ring_osc_0/csvco_branch_2/vbp
++ ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t
++ vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div PFD
+C0 nDown vdd 0.22fF
+C1 s_0_n vco_vctrl 0.34fF
+C2 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C3 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vco_vctrl 0.34fF
+C4 nDown pswitch 0.53fF
+C5 vdd QA -0.04fF
+C6 n_clk_1 vco_vctrl 0.23fF
+C7 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vco_vctrl 1.23fF
+C8 out_to_div out_to_buffer 0.13fF
+C9 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C10 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C11 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C12 clk_d out_div 0.64fF
+C13 freq_div_0/prescaler_23_0/nCLK_23 vco_vctrl 0.06fF
+C14 charge_pump_0/w_2544_775# nDown 0.05fF
+C15 Up biasp 0.26fF
+C16 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D vco_vctrl 0.09fF
+C17 nUp vdd 0.05fF
+C18 Up nUp 2.72fF
+C19 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vco_vctrl -0.42fF
+C20 out_to_buffer buffer_salida_0/a_678_n100# 0.21fF
+C21 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vco_vctrl -0.42fF
+C22 vdd vco_D0 0.03fF
+C23 nDown nswitch 0.76fF
+C24 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
+C25 nUp pswitch 0.93fF
+C26 freq_div_0/prescaler_23_0/Q2 vco_vctrl 0.06fF
+C27 s_0_n n_out_by_2 0.14fF
+C28 s_0 vco_vctrl 0.45fF
+C29 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vco_vctrl 0.82fF
+C30 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C31 charge_pump_0/w_2544_775# Down -0.23fF
+C32 out_to_div s_0 0.94fF
+C33 clk_1 vco_vctrl -0.04fF
+C34 s_1_n out_div 0.10fF
+C35 vdd clk_0 0.13fF
+C36 Up vdd 0.28fF
+C37 Down nswitch 0.54fF
+C38 MC vco_vctrl 0.33fF
+C39 nDown biasp 0.26fF
+C40 freq_div_0/div_by_5_0/Q1 vco_vctrl 0.10fF
+C41 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vco_vctrl 0.65fF
+C42 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vco_vctrl 0.17fF
+C43 nDown Down 2.55fF
+C44 Up pswitch 1.98fF
+C45 clk_0 vco_vctrl -0.26fF
+C46 vdd vco_vctrl 0.82fF
+C47 nUp nDown -0.09fF
+C48 s_1 out_div 0.37fF
+C49 out_by_2 n_out_by_2 0.27fF
+C50 iref_cp Down 0.09fF
+C51 s_0 n_out_by_2 0.14fF
+C52 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vco_vctrl 0.09fF
+C53 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D vco_vctrl 0.53fF
+C54 n_out_by_2 clk_1 -0.10fF
+C55 Down biasp 1.24fF
+C56 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vco_vctrl 0.15fF
+C57 nUp biasp -0.16fF
+C58 vdd buffer_salida_0/a_678_n100# 0.24fF
+C59 vdd out_to_buffer 0.07fF
+C60 MC lf_vc 0.20fF
+C61 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C62 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C63 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C64 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C65 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C66 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C67 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C68 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C69 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C70 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C71 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C72 QB vss 3.15fF
+C73 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C74 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C75 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C76 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C77 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C78 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C79 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C80 pfd_reset vss 1.87fF
+C81 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C82 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C83 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C84 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C85 QA vss 3.49fF
+C86 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C87 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C88 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C89 in_ref vss 0.84fF
+C90 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C91 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C92 nUp vss 0.12fF
+C93 Up vss -4.26fF
+C94 Down vss 1.89fF
+C95 nDown vss 2.80fF
+C96 out_first_buffer vss 2.15fF
+C97 out_to_buffer vss 1.92fF
+C98 out_to_div vss 8.72fF
+C99 ring_osc_0/csvco_branch_2/in vss 1.60fF
+C100 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C101 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C102 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C103 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C104 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.10fF
+C105 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.52fF
+C106 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C107 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C108 vco_out vss 1.65fF
+C109 vco_D0 vss -4.72fF
+C110 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C111 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C112 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C113 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vss 0.37fF
+C114 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C115 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vss 0.49fF
+C116 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C117 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C118 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C119 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C120 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C121 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C122 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C123 freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C124 freq_div_0/prescaler_23_0/DFlipFlop_1/D vss 1.90fF
+C125 freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C126 freq_div_0/prescaler_23_0/Q2_d vss -0.69fF
+C127 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C128 freq_div_0/prescaler_23_0/DFlipFlop_2/nQ vss 0.48fF
+C129 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C130 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C131 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C132 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C133 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C134 freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C135 freq_div_0/prescaler_23_0/Q2 vss 0.55fF
+C136 freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C137 freq_div_0/prescaler_23_0/Q1 vss 0.07fF
+C138 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C139 n_clk_0 vss -7.01fF
+C140 freq_div_0/prescaler_23_0/DFlipFlop_0/nQ vss 0.48fF
+C141 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C142 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C143 clk_0 vss -0.37fF
+C144 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C145 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C146 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C147 freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C148 freq_div_0/prescaler_23_0/nCLK_23 vss -1.02fF
+C149 freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C150 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vss -1.01fF
+C151 MC vss -1.42fF
+C152 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vss 0.36fF
+C153 freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vss 0.65fF
+C154 n_out_by_2 vss 4.87fF
+C155 s_0_n vss -4.09fF
+C156 out_by_2 vss 4.52fF
+C157 s_0 vss 5.50fF
+C158 freq_div_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C159 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C160 freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 freq_div_0/div_by_5_0/Q1_shift vss -0.36fF
+C162 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C163 freq_div_0/div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C164 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C165 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C166 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C168 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C169 freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C170 freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 freq_div_0/div_by_5_0/Q1 vss 4.35fF
+C172 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C173 freq_div_0/div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C174 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C175 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C176 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C177 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C178 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C179 freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C180 freq_div_0/div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C181 freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 freq_div_0/div_by_5_0/Q0 vss 0.29fF
+C183 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C184 freq_div_0/div_by_5_0/nQ0 vss 0.99fF
+C185 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C186 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C187 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C188 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C189 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C190 freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C191 freq_div_0/div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C192 freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 freq_div_0/div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C194 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C195 n_clk_1 vss -0.56fF
+C196 freq_div_0/div_by_5_0/nQ2 vss 1.38fF
+C197 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C198 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C199 clk_1 vss -2.21fF
+C200 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C202 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C203 freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C204 freq_div_0/div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C205 vdd vss 587.93fF
+C206 freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C207 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C209 s_1_n vss -2.04fF
+C210 out_div vss 3.70fF
+C211 clk_d vss 1.27fF
+C212 s_1 vss 1.72fF
+C213 freq_div_0/inverter_min_x4_0/in vss 2.71fF
+C214 clk_5 vss -0.22fF
+C215 clk_out_mux21 vss 3.89fF
+C216 clk_pre vss 1.69fF
+C217 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C218 freq_div_0/div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C219 freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C220 freq_div_0/div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C221 clk_2_f vss 3.30fF
+C222 freq_div_0/div_by_2_0/o1 vss 2.08fF
+C223 freq_div_0/div_by_2_0/nCLK_2 vss 1.04fF
+C224 freq_div_0/div_by_2_0/o2 vss 2.08fF
+C225 freq_div_0/div_by_2_0/out_div vss -0.82fF
+C226 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C227 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C228 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C229 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C230 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C231 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C232 freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C233 freq_div_0/div_by_2_0/nout_div vss 2.62fF
+C234 freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C235 out_to_pad vss 7.15fF
+C236 buffer_salida_0/a_3996_n100# vss 48.29fF
+C237 buffer_salida_0/a_678_n100# vss 13.38fF
+C238 lf_vc vss -60.88fF
+C239 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C240 lf_D0 vss 0.01fF
+C241 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C242 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C243 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C244 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C245 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C246 out_buffer_div_2 vss 1.57fF
+C247 n_out_buffer_div_2 vss 1.57fF
+C248 out_div_2 vss -0.70fF
+C249 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C250 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C251 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C252 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C253 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C254 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C255 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C256 n_out_div_2 vss 2.11fF
+C257 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C258 nswitch vss 4.61fF
+C259 biasp vss 5.46fF
+C260 iref_cp vss 2.44fF
+C261 vco_vctrl vss -30.24fF
+C262 pswitch vss 2.72fF
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+C0 in vc_pex 0.18fF
+C1 vc_pex vss -38.13fF
+C2 res_loop_filter_2/out vss 8.49fF
+C3 in vss -18.79fF
+.ends
+
+.subckt top_pll_v1 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vdd charge_pump_0/w_2544_775#
++ pswitch biasp ring_osc_0/csvco_branch_2/vbp in_ref Down w_13905_n238# vss vco_D0
++ QA ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd iref_cp out_to_div nDown out_to_pad
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd Up nUp
Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
-+ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
-Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
-+ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump_0/w_6648_570# charge_pump
+Xdiv_by_2_0 vss vdd n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2
++ n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
+ div_by_2
-Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
-+ vss vdd buffer_salida
-Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
-+ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd vss ring_osc_0/csvco_branch_2/vbp
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# buffer_salida_0/a_3996_n100# out_to_pad
++ vdd out_to_buffer vss buffer_salida
+Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl vss ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd ring_osc_0/csvco_branch_2/vbp
+ ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t
+ vco_out ring_osc
Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
-+ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
-+ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
-+ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_0/latch_diff_1/nD
++ vss vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_5_Q1 out_by_2 div_by_5_0/DFlipFlop_0/Q
++ div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ out_div_by_5 div_5_Q1_shift div_5_nQ2 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_2/latch_diff_1/nD
+ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
-+ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
+ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
-+ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
-+ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
-+ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
-+ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_2/latch_diff_0/D
+ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
+ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
+ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
-+ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
+ div_by_5
-Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
+ Down QA QB nDown Up nUp pfd_cp_interface
-XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
-C0 vco_vctrl nswitch -0.06fF
-C1 vco_D0 vdd 0.03fF
-C2 Up vdd 0.28fF
-C3 iref_cp vdd 0.15fF
-C4 Down iref_cp 0.09fF
-C5 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
-C6 out_to_buffer vdd 0.07fF
-C7 out_div_by_5 div_5_Q1_shift 0.05fF
-C8 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
-C9 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
-C10 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
-C11 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
-C12 Up pswitch 1.98fF
-C13 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
-C14 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
-C15 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
-C16 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
-C17 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
-C18 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
-C19 vdd out_to_div 0.21fF
-C20 Up nUp 2.72fF
-C21 div_by_5_0/DFlipFlop_2/latch_diff_1/D n_out_by_2 0.10fF
-C22 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
-C23 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
-C24 n_out_by_2 div_5_nQ0 0.10fF
-C25 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
-C26 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
-C27 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
-C28 out_by_2 div_5_nQ0 0.32fF
-C29 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
-C30 Down biasp 1.24fF
-C31 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C32 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
-C33 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
-C34 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
-C35 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
-C36 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.17fF
-C37 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
-C38 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
-C39 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
-C40 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
-C41 biasp nUp -0.17fF
-C42 nDown biasp 0.26fF
-C43 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
-C44 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
-C45 vdd lf_vc 0.02fF
-C46 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
-C47 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
-C48 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
-C49 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
-C50 n_out_by_2 div_5_nQ2 0.10fF
-C51 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
-C52 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
-C53 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
-C54 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
-C55 buffer_salida_0/a_678_n100# vdd 0.24fF
-C56 out_by_2 div_5_nQ2 0.16fF
-C57 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
-C58 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
-C59 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
-C60 n_out_by_2 div_5_Q1 1.04fF
-C61 vco_vctrl div_5_Q1 0.14fF
-C62 n_out_by_2 vdd 1.03fF
-C63 nUp vdd 0.05fF
-C64 nDown vdd 0.22fF
-C65 vco_vctrl vdd -1.02fF
-C66 div_5_Q1 out_by_2 0.42fF
-C67 Down nDown 2.55fF
-C68 out_by_2 vdd 0.97fF
-C69 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
-C70 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
-C71 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
-C72 pswitch nUp 0.85fF
-C73 nDown pswitch 0.53fF
-C74 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
-C75 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
-C76 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
-C77 out_to_buffer out_to_div 0.13fF
-C78 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
-C79 n_out_by_2 vco_vctrl 0.52fF
-C80 nDown nUp -0.09fF
-C81 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
-C82 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
-C83 vco_vctrl nUp 0.02fF
-C84 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
-C85 n_out_by_2 div_5_Q0 -0.12fF
-C86 vco_vctrl div_5_Q0 0.48fF
-C87 vco_vctrl out_by_2 0.53fF
-C88 QA vdd -0.04fF
-C89 Up biasp 0.26fF
-C90 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
-C91 div_5_Q1 out_div_by_5 0.01fF
-C92 out_by_2 div_5_Q0 0.09fF
-C93 out_div_by_5 vdd 0.28fF
-C94 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
-C95 Down nswitch 0.54fF
-C96 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
-C97 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
-C98 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
-C99 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
-C100 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
-C101 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
-C102 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_to_div -0.16fF
-C103 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
-C104 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
-C105 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
-C106 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
-C107 nDown nswitch 0.76fF
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div_by_5 PFD
+C0 nDown vdd 0.22fF
+C1 out_to_buffer out_to_div 0.13fF
+C2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 0.27fF
+C3 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C4 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C5 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C6 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C7 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
+C8 nUp Up 2.72fF
+C9 biasp nUp -0.17fF
+C10 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C11 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C12 biasp nDown 0.26fF
+C13 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
+C14 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
+C15 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
+C16 out_by_2 div_5_Q1 0.42fF
+C17 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C18 div_5_Q1_shift out_div_by_5 0.05fF
+C19 out_by_2 div_5_nQ0 0.32fF
+C20 n_out_by_2 vdd 1.03fF
+C21 vdd Up 0.28fF
+C22 out_div_by_5 vdd 0.28fF
+C23 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C24 vdd out_to_div 0.21fF
+C25 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C26 vco_vctrl div_5_Q1 0.14fF
+C27 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
+C28 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
+C29 biasp Up 0.26fF
+C30 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
+C31 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C32 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
+C33 iref_cp vdd 0.15fF
+C34 nDown Down 2.55fF
+C35 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C36 nswitch Down 0.54fF
+C37 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
+C38 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C39 vco_vctrl nUp 0.02fF
+C40 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
+C41 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
+C42 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C43 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C44 out_by_2 vdd 0.97fF
+C45 nswitch vco_vctrl -0.06fF
+C46 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C47 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
+C48 vdd vco_D0 0.03fF
+C49 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.33fF
+C50 vco_vctrl vdd -1.02fF
+C51 biasp Down 1.24fF
+C52 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C53 n_out_by_2 div_5_nQ2 0.10fF
+C54 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C55 n_out_by_2 vco_vctrl 0.52fF
+C56 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
+C57 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C58 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C59 pswitch nUp 0.85fF
+C60 iref_cp Down 0.09fF
+C61 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C62 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C63 pswitch nDown 0.53fF
+C64 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
+C65 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C66 buffer_salida_0/a_678_n100# out_to_buffer 0.22fF
+C67 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C68 div_5_Q0 n_out_by_2 -0.12fF
+C69 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C70 out_by_2 div_5_nQ2 0.16fF
+C71 out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.09fF
+C72 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C73 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
+C74 out_by_2 vco_vctrl 0.53fF
+C75 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C76 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C77 pswitch Up 1.98fF
+C78 buffer_salida_0/a_678_n100# vdd 0.24fF
+C79 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C80 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C81 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_to_div -0.16fF
+C82 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C83 div_by_5_0/DFlipFlop_2/latch_diff_0/D n_out_by_2 0.12fF
+C84 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C85 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C86 nUp nDown -0.09fF
+C87 n_out_by_2 div_5_Q1 1.04fF
+C88 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_out_by_2 0.12fF
+C89 div_5_Q0 out_by_2 0.09fF
+C90 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C91 out_div_by_5 div_5_Q1 0.01fF
+C92 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C93 n_out_by_2 div_5_nQ0 0.10fF
+C94 div_by_5_0/DFlipFlop_1/D out_by_2 0.38fF
+C95 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C96 lf_vc vdd 0.02fF
+C97 out_to_buffer vdd 0.07fF
+C98 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C99 nswitch nDown 0.76fF
+C100 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C101 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C102 QA vdd -0.04fF
+C103 nUp vdd 0.05fF
+C104 div_5_Q0 vco_vctrl 0.48fF
+C105 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C106 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C107 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
-C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C118 QB vss 4.46fF
-C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.46fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C123 out_div_by_5 vss -0.40fF
C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C127 pfd_reset vss 2.17fF
-C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
-C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C132 QA vss 4.31fF
-C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.31fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C137 in_ref vss 1.19fF
@@ -6536,57 +7488,57 @@
C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
-C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
-C148 div_5_Q1_shift vss -0.14fF
-C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
-C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
-C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
-C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C147 div_5_Q1_shift vss -0.14fF
+C148 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C149 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C156 div_5_Q1 vss 4.28fF
-C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C158 div_5_nQ0 vss 0.59fF
-C159 div_5_Q0 vss 0.01fF
-C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
-C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
-C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
-C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
-C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
-C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
-C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
-C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
-C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C179 div_5_nQ2 vss 1.24fF
-C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
-C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
-C182 n_out_by_2 vss -2.62fF
-C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C186 out_by_2 vss -4.51fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_5_Q1 vss 4.28fF
+C158 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C159 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C164 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_Q0 vss 0.01fF
+C169 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C170 div_5_nQ0 vss 0.59fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C180 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C181 n_out_by_2 vss -2.62fF
+C182 div_5_nQ2 vss 1.24fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C185 out_by_2 vss -4.51fF
+C186 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
-C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
-C192 vdd vss 366.82fF
+C191 vdd vss 366.82fF
+C192 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
C195 out_first_buffer vss 2.88fF
-C196 out_to_div vss 4.46fF
-C197 out_to_buffer vss 1.57fF
+C196 out_to_buffer vss 1.57fF
+C197 out_to_div vss 4.46fF
C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -6601,8 +7553,8 @@
C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
-C212 buffer_salida_0/a_3996_n100# vss 48.29fF
-C213 out_to_pad vss 7.50fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
C214 buffer_salida_0/a_678_n100# vss 13.38fF
C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
@@ -6612,9 +7564,9 @@
C220 n_out_buffer_div_2 vss 1.63fF
C221 out_div_2 vss -1.30fF
C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
-C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C223 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C224 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C225 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
@@ -6631,7 +7583,7 @@
.subckt sky130_fd_pr__cap_mim_m3_2_2Y8F6P VSUBS c2_n3251_n3000# m4_n3351_n3100#
X0 c2_n3251_n3000# m4_n3351_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
-C0 m4_n3351_n3100# c2_n3251_n3000# 72.82fF
+C0 c2_n3251_n3000# m4_n3351_n3100# 72.82fF
C1 m4_n3351_n3100# VSUBS 14.58fF
.ends
@@ -6687,16 +7639,16 @@
X47 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
X48 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
-C0 w_n2018_n202# a_n2017_n61# 1.37fF
-C1 w_n2018_n202# a_n1879_n1219# 0.25fF
-C2 a_n2017_n61# a_n1879_n1219# 0.16fF
-C3 a_n2017_n1317# a_n1731_n1219# 4.73fF
-C4 w_n2018_n202# a_n1731_n1219# 19.90fF
+C0 a_n2017_n61# a_n1879_n1219# 0.16fF
+C1 a_n1731_n1219# w_n2018_n202# 19.90fF
+C2 w_n2018_n202# a_n2017_n1317# 0.16fF
+C3 a_n1731_n1219# a_n2017_n1317# 4.73fF
+C4 a_n2017_n61# w_n2018_n202# 1.37fF
C5 a_n2017_n61# a_n1731_n1219# 5.23fF
-C6 a_n1879_n1219# a_n1731_n1219# 19.29fF
-C7 w_n2018_n202# a_n2017_n1317# 0.16fF
+C6 a_n1879_n1219# w_n2018_n202# 0.25fF
+C7 a_n1731_n1219# a_n1879_n1219# 19.29fF
C8 a_n2017_n61# a_n2017_n1317# 2.88fF
-C9 a_n2017_n1317# a_n1879_n1219# 2.66fF
+C9 a_n1879_n1219# a_n2017_n1317# 2.66fF
C10 a_n1879_n1219# VSUBS 1.53fF
C11 a_n2017_n1317# VSUBS 5.03fF
C12 a_n1731_n1219# VSUBS 2.60fF
@@ -6727,57 +7679,57 @@
+ iref_3 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
Xsky130_fd_pr__pfet_01v8_lvt_8P223X_4 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219#
+ iref_4 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
-C0 iref_4 iref_3 0.05fF
-C1 iref_5 iref_6 0.05fF
-C2 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# 0.24fF
-C3 iref_3 iref_2 0.05fF
-C4 iref_9 iref_8 0.05fF
-C5 iref_5 iref 0.05fF
-C6 iref_7 iref_6 0.05fF
-C7 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vdd 0.24fF
-C8 iref_7 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
-C9 iref_2 iref_1 0.05fF
-C10 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# iref -0.15fF
-C11 iref_8 iref -0.03fF
-C12 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# iref_6 0.24fF
-C13 iref_3 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.24fF
-C14 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.01fF
-C15 iref_4 iref 0.30fF
-C16 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vdd 0.24fF
-C17 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# 0.24fF
-C18 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.01fF
-C19 m1_20168_984# iref 0.07fF
-C20 iref_2 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
-C21 m1_20168_984# vdd 0.25fF
-C22 iref iref_2 -0.01fF
-C23 iref_8 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# 0.24fF
-C24 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# 0.67fF
-C25 iref iref_1 -0.02fF
-C26 iref_8 iref_7 0.05fF
-C27 iref_0 iref_1 0.05fF
-C28 iref_5 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# 0.24fF
-C29 iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.02fF
-C30 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# iref_1 0.24fF
-C31 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vdd 0.24fF
-C32 iref_9 iref -0.01fF
-C33 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# m1_20168_984# -0.39fF
-C34 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
-C35 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# 0.54fF
-C36 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
-C37 iref vdd -0.07fF
-C38 iref VSUBS 32.42fF
-C39 iref_4 VSUBS 1.17fF
-C40 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# VSUBS 2.60fF
-C41 iref_3 VSUBS 0.64fF
-C42 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# VSUBS 2.60fF
-C43 iref_2 VSUBS -1.26fF
-C44 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# VSUBS 2.60fF
-C45 iref_1 VSUBS -0.80fF
-C46 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# VSUBS 2.60fF
-C47 m1_20168_984# VSUBS 56.92fF
-C48 vdd VSUBS 416.01fF
-C49 iref_0 VSUBS 1.88fF
-C50 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# VSUBS 2.60fF
+C0 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# 0.24fF
+C1 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# 0.24fF
+C2 iref m1_20168_984# 0.07fF
+C3 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# iref_5 0.24fF
+C4 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C5 iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.02fF
+C6 iref_6 iref_5 0.05fF
+C7 iref_6 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# 0.24fF
+C8 iref_6 iref_7 0.05fF
+C9 iref_2 iref_3 0.05fF
+C10 iref_7 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C11 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# 0.67fF
+C12 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# 0.24fF
+C13 iref_2 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
+C14 iref_7 iref_8 0.05fF
+C15 iref_1 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# 0.24fF
+C16 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# m1_20168_984# -0.39fF
+C17 iref iref_9 -0.01fF
+C18 iref_4 iref_3 0.05fF
+C19 iref_1 iref -0.02fF
+C20 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
+C21 sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# m1_20168_984# 0.54fF
+C22 vdd m1_20168_984# 0.25fF
+C23 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.24fF
+C24 iref sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# -0.15fF
+C25 iref_2 iref -0.01fF
+C26 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# 0.24fF
+C27 iref iref_8 -0.03fF
+C28 iref_1 iref_2 0.05fF
+C29 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# m1_20168_984# 0.01fF
+C30 iref_4 iref 0.30fF
+C31 vdd iref -0.07fF
+C32 iref_8 iref_9 0.05fF
+C33 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref_3 0.24fF
+C34 iref_0 iref_1 0.05fF
+C35 iref iref_5 0.05fF
+C36 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# m1_20168_984# 0.01fF
+C37 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# iref_8 0.24fF
+C38 iref_4 VSUBS 1.17fF
+C39 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# VSUBS 2.60fF
+C40 iref_3 VSUBS 0.64fF
+C41 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# VSUBS 2.60fF
+C42 iref_2 VSUBS -1.26fF
+C43 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# VSUBS 2.60fF
+C44 iref_1 VSUBS -0.80fF
+C45 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# VSUBS 2.60fF
+C46 iref_0 VSUBS 1.88fF
+C47 iref VSUBS 32.42fF
+C48 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# VSUBS 2.60fF
+C49 m1_20168_984# VSUBS 56.92fF
+C50 vdd VSUBS 416.01fF
C51 iref_9 VSUBS -1.13fF
C52 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# VSUBS 2.60fF
C53 iref_7 VSUBS -1.38fF
@@ -6799,234 +7751,182 @@
C0 b VSUBS 68.24fF
.ends
-.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
-+ c1_110_n4150# m3_10_n4250#
-X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
-C1 m3_n4309_50# m3_n4309_n4250# 2.63fF
-C2 c1_110_n4150# m3_10_n4250# 81.11fF
-C3 m3_n4309_50# m3_10_n4250# 1.75fF
-C4 m3_n4309_n4250# m3_10_n4250# 1.75fF
-C5 c1_n4209_n4150# c1_110_n4150# 1.32fF
-C6 c1_n4209_n4150# m3_n4309_50# 38.10fF
-C7 c1_110_n4150# VSUBS 0.12fF
-C8 c1_n4209_n4150# VSUBS 0.12fF
-C9 m3_n4309_n4250# VSUBS 8.68fF
-C10 m3_10_n4250# VSUBS 17.92fF
-C11 m3_n4309_50# VSUBS 8.68fF
-.ends
-
-.subckt cap3_loop_filter VSUBS in out
-Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
-C0 in out 3.21fF
-C1 in VSUBS -8.91fF
-C2 out VSUBS 3.92fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
-X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
-C0 a_30_n300# a_n88_n300# 0.61fF
-C1 a_n88_n300# a_n118_n388# 0.11fF
-C2 a_30_n300# w_n226_n510# 0.40fF
-C3 a_n88_n300# w_n226_n510# 0.40fF
-C4 a_n118_n388# w_n226_n510# 0.28fF
-.ends
-
-.subckt loop_filter_v2 vc_pex D0_cap in vss
-Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
-Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
-Xcap2_loop_filter_0 vss in vss cap2_loop_filter
-Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
-Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
-Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
-Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
-C0 in cap3_loop_filter_0/in 0.79fF
-C1 in vc_pex 0.18fF
-C2 in D0_cap 0.07fF
-C3 vc_pex vss -38.13fF
-C4 res_loop_filter_2/out vss 8.49fF
-C5 D0_cap vss 0.04fF
-C6 in vss -18.54fF
-C7 cap3_loop_filter_0/in vss -3.74fF
-.ends
-
.subckt top_pll_v2 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd pswitch vdd charge_pump_0/w_2544_775#
+ ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd in_ref
+ vco_vctrl Down w_13905_n238# vss D0_vco iref_cp ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
+ out_to_div DO_cap nDown biasp out_to_pad Up nUp
Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
-+ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
-Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
-Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
-+ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump_0/w_6648_570# charge_pump
+Xdiv_by_2_0 vss vdd n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2
++ n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
+ div_by_2
-Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
-+ vss vdd buffer_salida
-Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
-+ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd vss ring_osc_0/csvco_branch_2/vbp
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2_0/cap3_loop_filter_0/in
++ loop_filter_v2
+Xbuffer_salida_0 buffer_salida_0/a_678_n100# buffer_salida_0/a_3996_n100# out_to_pad
++ vdd out_to_buffer vss buffer_salida
+Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl vss ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdd ring_osc_0/csvco_branch_2/vbp
+ ring_osc_0/csvco_branch_0/inverter_csvco_0/vss D0_vco ring_osc_0/csvco_branch_2/cap_vco_0/t
+ vco_out ring_osc
Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
-+ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
-+ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
-+ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_0/latch_diff_1/nD
++ vss vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_5_Q1 out_by_2 div_by_5_0/DFlipFlop_0/Q
++ div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD div_by_5_0/DFlipFlop_1/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280#
++ out_div_by_5 div_5_Q1_shift div_5_nQ2 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_2/latch_diff_1/nD
+ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
-+ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
+ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
-+ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
-+ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
-+ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
-+ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_2/latch_diff_0/D
+ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
+ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
+ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
-+ div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
++ div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_152_368# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/DFlipFlop_3/nQ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
+ div_by_5
-Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
+ Down QA QB nDown Up nUp pfd_cp_interface
-XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
-C0 pswitch nDown 0.53fF
-C1 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
-C2 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
-C3 div_5_nQ0 out_by_2 0.32fF
-C4 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
-C5 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
-C6 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
-C7 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
-C8 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
-C9 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
-C10 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
-C11 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.33fF
-C12 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
-C13 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
-C14 nDown nUp -0.09fF
-C15 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# n_out_by_2 0.01fF
-C16 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
-C17 vdd nUp 0.05fF
-C18 Down nDown 2.55fF
-C19 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
-C20 vdd Up 0.28fF
-C21 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
-C22 pswitch nUp 0.85fF
-C23 nDown biasp 0.26fF
-C24 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
-C25 vdd iref_cp 0.15fF
-C26 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
-C27 pswitch Up 1.98fF
-C28 div_5_Q1_shift out_div_by_5 0.05fF
-C29 nswitch nDown 0.76fF
-C30 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
-C31 out_by_2 vdd 0.97fF
-C32 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
-C33 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
-C34 div_5_Q1 n_out_by_2 1.04fF
-C35 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
-C36 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
-C37 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
-C38 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
-C39 Up nUp 2.72fF
-C40 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
-C41 vco_vctrl n_out_by_2 0.52fF
-C42 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
-C43 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
-C44 div_5_Q0 n_out_by_2 -0.12fF
-C45 vdd out_div_by_5 0.28fF
-C46 div_5_nQ2 n_out_by_2 0.10fF
-C47 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
-C48 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
-C49 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
-C50 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
-C51 vdd vco_vctrl -1.02fF
-C52 biasp nUp -0.17fF
-C53 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
-C54 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
-C55 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
-C56 Down iref_cp 0.09fF
-C57 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
-C58 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
-C59 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
-C60 out_to_buffer out_to_div 0.13fF
-C61 Up biasp 0.26fF
-C62 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
-C63 Down biasp 1.24fF
-C64 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
-C65 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div_by_5 PFD
+C0 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C1 vdd Up 0.28fF
+C2 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
+C3 div_5_Q0 out_by_2 0.09fF
+C4 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
+C5 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C6 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C7 vdd iref_cp 0.15fF
+C8 nUp nDown -0.09fF
+C9 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C10 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C11 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
+C12 vdd out_div_by_5 0.28fF
+C13 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
+C14 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
+C15 vco_vctrl out_by_2 0.53fF
+C16 Down iref_cp 0.09fF
+C17 vdd vco_vctrl -1.02fF
+C18 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C19 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C20 Up nUp 2.72fF
+C21 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C22 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C23 div_5_nQ2 out_by_2 0.16fF
+C24 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
+C25 n_out_by_2 div_5_Q1 1.04fF
+C26 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C27 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C28 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C29 vco_vctrl nUp 0.02fF
+C30 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C31 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C32 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
+C33 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C34 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
+C35 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C36 div_5_Q0 vco_vctrl 0.48fF
+C37 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_to_div -0.16fF
+C38 n_out_by_2 vdd 1.03fF
+C39 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C40 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C41 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C42 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C43 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
+C44 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
+C45 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
+C46 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C47 buffer_salida_0/a_678_n100# vdd 0.24fF
+C48 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C49 buffer_salida_0/a_678_n100# out_to_buffer 0.22fF
+C50 div_5_Q1_shift out_div_by_5 0.05fF
+C51 vdd D0_vco 0.03fF
+C52 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C53 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C54 n_out_by_2 div_5_nQ0 0.10fF
+C55 lf_vc vdd 0.02fF
+C56 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C57 vdd QA -0.04fF
+C58 div_5_Q1 out_by_2 0.42fF
+C59 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C60 div_by_5_0/DFlipFlop_0/Q out_by_2 0.09fF
+C61 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C62 out_to_div vdd 0.21fF
+C63 n_out_by_2 div_5_Q0 -0.12fF
+C64 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C65 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
C66 Down nswitch 0.54fF
-C67 div_5_nQ0 n_out_by_2 0.10fF
-C68 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
-C69 out_to_div vdd 0.21fF
-C70 div_by_5_0/DFlipFlop_2/latch_diff_1/nD n_out_by_2 0.24fF
-C71 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
-C72 vco_vctrl nUp 0.02fF
-C73 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
-C74 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
-C75 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
-C76 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
-C77 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
-C78 vdd buffer_salida_0/a_678_n100# 0.24fF
-C79 vdd lf_vc 0.02fF
-C80 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
-C81 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
-C82 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
-C83 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
-C84 out_by_2 div_5_Q1 0.42fF
-C85 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
-C86 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
-C87 out_by_2 vco_vctrl 0.53fF
-C88 out_by_2 div_5_Q0 0.09fF
+C67 out_to_div out_to_buffer 0.13fF
+C68 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C69 biasp Down 1.24fF
+C70 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
+C71 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C72 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C73 n_out_by_2 vco_vctrl 0.52fF
+C74 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
+C75 vdd out_by_2 0.97fF
+C76 biasp nUp -0.17fF
+C77 nswitch nDown 0.76fF
+C78 out_to_buffer vdd 0.07fF
+C79 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C80 pswitch nUp 0.85fF
+C81 div_5_nQ2 n_out_by_2 0.10fF
+C82 biasp nDown 0.26fF
+C83 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C84 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C85 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C86 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C87 pswitch nDown 0.53fF
+C88 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
C89 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
-C90 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
-C91 div_5_nQ2 out_by_2 0.16fF
-C92 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
-C93 nswitch vco_vctrl -0.06fF
-C94 div_5_Q1 out_div_by_5 0.01fF
-C95 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
-C96 out_to_buffer vdd 0.07fF
-C97 vdd n_out_by_2 1.03fF
-C98 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
-C99 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
-C100 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
-C101 vco_vctrl div_5_Q1 0.14fF
-C102 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
-C103 vdd nDown 0.22fF
-C104 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
-C105 vdd QA -0.04fF
-C106 div_5_Q0 vco_vctrl 0.48fF
-C107 D0_vco vdd 0.03fF
+C90 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
+C91 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
+C92 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C93 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C94 vdd nUp 0.05fF
+C95 biasp Up 0.26fF
+C96 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C97 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C98 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C99 Up pswitch 1.98fF
+C100 div_5_nQ0 out_by_2 0.32fF
+C101 vdd nDown 0.22fF
+C102 out_div_by_5 div_5_Q1 0.01fF
+C103 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C104 vco_vctrl div_5_Q1 0.14fF
+C105 nswitch vco_vctrl -0.06fF
+C106 Down nDown 2.55fF
+C107 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
-C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C118 QB vss 4.46fF
-C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C119 QB vss 4.46fF
+C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C123 out_div_by_5 vss -0.40fF
C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C127 pfd_reset vss 2.17fF
-C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
-C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C132 QA vss 4.31fF
-C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C128 pfd_reset vss 2.17fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C133 QA vss 4.31fF
+C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
C137 in_ref vss 1.19fF
@@ -7039,57 +7939,57 @@
C144 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
C145 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
C146 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
-C147 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
-C148 div_5_Q1_shift vss -0.14fF
-C149 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
-C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
-C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
-C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C147 div_5_Q1_shift vss -0.14fF
+C148 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C149 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C150 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C151 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C152 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C156 div_5_Q1 vss 4.28fF
-C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C158 div_5_nQ0 vss 0.59fF
-C159 div_5_Q0 vss 0.01fF
-C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
-C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
-C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
-C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
-C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
-C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
-C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
-C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
-C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C179 div_5_nQ2 vss 1.24fF
-C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
-C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
-C182 n_out_by_2 vss -2.62fF
-C183 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C186 out_by_2 vss -4.51fF
+C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C157 div_5_Q1 vss 4.28fF
+C158 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C159 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C160 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C161 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C162 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C163 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C164 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C168 div_5_Q0 vss 0.01fF
+C169 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C170 div_5_nQ0 vss 0.59fF
+C171 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C172 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C173 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C174 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C179 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C180 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C181 n_out_by_2 vss -2.62fF
+C182 div_5_nQ2 vss 1.24fF
+C183 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C184 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C185 out_by_2 vss -4.51fF
+C186 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
-C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
-C192 vdd vss 366.82fF
+C191 vdd vss 366.82fF
+C192 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
C195 out_first_buffer vss 2.88fF
-C196 out_to_div vss 4.46fF
-C197 out_to_buffer vss 1.57fF
+C196 out_to_buffer vss 1.57fF
+C197 out_to_div vss 4.46fF
C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -7104,29 +8004,29 @@
C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
-C212 buffer_salida_0/a_3996_n100# vss 48.29fF
-C213 out_to_pad vss 7.50fF
+C212 out_to_pad vss 7.50fF
+C213 buffer_salida_0/a_3996_n100# vss 48.29fF
C214 buffer_salida_0/a_678_n100# vss 13.38fF
-C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
-C217 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
-C218 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
-C219 out_buffer_div_2 vss 1.60fF
-C220 n_out_buffer_div_2 vss 1.63fF
-C221 out_div_2 vss -1.30fF
-C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
-C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
-C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
-C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C229 n_out_div_2 vss 1.95fF
-C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
-C231 lf_vc vss -59.89fF
-C232 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
-C233 DO_cap vss 0.01fF
-C234 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C215 lf_vc vss -59.89fF
+C216 loop_filter_v2_0/res_loop_filter_2/out vss 7.90fF
+C217 DO_cap vss 0.01fF
+C218 loop_filter_v2_0/cap3_loop_filter_0/in vss -12.03fF
+C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C220 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C221 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C222 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C223 out_buffer_div_2 vss 1.60fF
+C224 n_out_buffer_div_2 vss 1.63fF
+C225 out_div_2 vss -1.30fF
+C226 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C227 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C228 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C229 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C230 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C231 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C232 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C233 n_out_div_2 vss 1.95fF
+C234 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
C235 nswitch vss 3.73fF
C236 biasp vss 5.44fF
C237 iref_cp vss 2.81fF
@@ -7142,103 +8042,104 @@
+ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
+ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
+ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7]
-+ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
-+ io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
-+ io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
-+ io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9]
-+ io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14]
-+ io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1]
-+ io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25]
-+ io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7]
-+ io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
-+ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20]
-+ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3]
-+ io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10]
-+ io_out[11] io_out[12] io_out[13] io_out[14] io_out[15] io_out[16] io_out[17] io_out[18]
-+ io_out[19] io_out[1] io_out[20] io_out[21] io_out[22] io_out[23] io_out[24] io_out[25]
-+ io_out[26] io_out[2] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8]
-+ io_out[9] la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103]
-+ la_data_in[104] la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108]
-+ la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113]
-+ la_data_in[114] la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118]
-+ la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123]
-+ la_data_in[124] la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13]
-+ la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19]
-+ la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24]
-+ la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2]
-+ la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35]
-+ la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40]
-+ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46]
-+ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51]
-+ la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57]
-+ la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62]
-+ la_data_in[63] la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68]
-+ la_data_in[69] la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73]
-+ la_data_in[74] la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79]
-+ la_data_in[7] la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84]
-+ la_data_in[85] la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8]
-+ la_data_in[90] la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95]
-+ la_data_in[96] la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0]
-+ la_data_out[100] la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104]
-+ la_data_out[105] la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109]
-+ la_data_out[10] la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113]
-+ la_data_out[114] la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118]
-+ la_data_out[119] la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122]
-+ la_data_out[123] la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127]
-+ la_data_out[12] la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16]
-+ la_data_out[17] la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21]
-+ la_data_out[22] la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26]
-+ la_data_out[27] la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31]
-+ la_data_out[32] la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36]
-+ la_data_out[37] la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41]
-+ la_data_out[42] la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46]
-+ la_data_out[47] la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51]
-+ la_data_out[52] la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56]
-+ la_data_out[57] la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61]
-+ la_data_out[62] la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66]
-+ la_data_out[67] la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71]
-+ la_data_out[72] la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76]
-+ la_data_out[77] la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81]
-+ la_data_out[82] la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86]
-+ la_data_out[87] la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91]
-+ la_data_out[92] la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96]
-+ la_data_out[97] la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100]
-+ la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107]
-+ la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113]
-+ la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11]
-+ la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126]
-+ la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17]
-+ la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23]
-+ la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2]
-+ la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36]
-+ la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42]
-+ la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49]
-+ la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55]
-+ la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61]
-+ la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68]
-+ la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74]
-+ la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80]
-+ la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87]
-+ la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93]
-+ la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9]
-+ user_clock2 user_irq[0] user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2
-+ vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11]
-+ wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17]
-+ wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22]
-+ wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28]
-+ wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4]
-+ wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0]
-+ wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15]
-+ wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20]
-+ wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26]
-+ wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31]
-+ wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9]
-+ wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14]
-+ wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1]
-+ wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25]
-+ wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
-+ wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
-+ wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
++ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
Xres_amp_top_0 vssa1 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
+ vdda1 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# bias_0/iref_8
+ res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out
@@ -7266,18 +8167,23 @@
+ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
+ gpio_noesd[2] io_analog[0] res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
+ io_analog[1] io_analog[4] res_amp_top_0/res_amp_sync_v2_0/rst res_amp_top
-Xtop_pll_v1_0 top_pll_v1_0/vco_vctrl vdda1 top_pll_v1_0/pswitch top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
-+ top_pll_v1_0/charge_pump_0/w_2544_775# top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp
-+ top_pll_v1_0/biasp io_analog[10] top_pll_v1_0/Down vssa1 vssa1 gpio_noesd[7] top_pll_v1_0/buffer_salida_0/a_3996_n100#
-+ top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v1_0/QA top_pll_v1_0/charge_pump_0/w_1008_774#
-+ bias_0/iref_2 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd top_pll_v1_0/out_to_div
-+ top_pll_v1_0/nDown io_analog[9] top_pll_v1_0/Up top_pll_v1_0/nUp top_pll_v1
-Xtop_pll_v1_1 top_pll_v1_1/vco_vctrl vdda1 top_pll_v1_1/pswitch top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
-+ top_pll_v1_1/charge_pump_0/w_2544_775# top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp
-+ top_pll_v1_1/biasp io_analog[10] top_pll_v1_1/Down vssa1 vssa1 gpio_noesd[7] top_pll_v1_1/buffer_salida_0/a_3996_n100#
-+ top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v1_1/QA top_pll_v1_1/charge_pump_0/w_1008_774#
-+ bias_0/iref_0 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd top_pll_v1_1/out_to_div
-+ top_pll_v1_1/nDown io_analog[7] top_pll_v1_1/Up top_pll_v1_1/nUp top_pll_v1
+Xtop_pll_v3_0 top_pll_v3_0/clk_d vdda1 gpio_noesd[10] top_pll_v3_0/charge_pump_0/w_2544_775#
++ top_pll_v3_0/out_by_2 top_pll_v3_0/s_0_n io_analog[10] top_pll_v3_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ top_pll_v3_0/buffer_salida_0/a_3996_n100# vssa1 top_pll_v3_0/vco_vctrl gpio_noesd[9]
++ top_pll_v3_0/ring_osc_0/csvco_branch_2/vbp top_pll_v3_0/lf_vc gpio_noesd[7] gpio_noesd[8]
++ top_pll_v3_0/buffer_salida_0/a_678_n100# top_pll_v3_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ top_pll_v3_0/loop_filter_v2_0/cap3_loop_filter_0/in top_pll_v3_0/charge_pump_0/w_1008_774#
++ bias_0/iref_0 top_pll_v3_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd top_pll_v3_0/Down
++ top_pll_v3_0/out_to_div top_pll_v3_0/clk_1 top_pll_v3_0/out_div top_pll_v3_0/nDown
++ top_pll_v3_0/s_1_n io_analog[7] gpio_noesd[11] top_pll_v3_0/Up top_pll_v3_0/clk_0
++ top_pll_v3_0/freq_div_0/prescaler_23_0/nCLK_23 top_pll_v3_0/biasp top_pll_v3_0/nUp
++ top_pll_v3_0/n_clk_0 top_pll_v3
+Xtop_pll_v1_0 top_pll_v1_0/vco_vctrl top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
++ vdda1 top_pll_v1_0/charge_pump_0/w_2544_775# top_pll_v1_0/pswitch top_pll_v1_0/biasp
++ top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp io_analog[10] top_pll_v1_0/Down vssa1
++ vssa1 gpio_noesd[7] top_pll_v1_0/QA top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
++ bias_0/iref_2 top_pll_v1_0/out_to_div top_pll_v1_0/nDown io_analog[9] top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
++ top_pll_v1_0/Up top_pll_v1_0/nUp top_pll_v1
Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
@@ -7331,1339 +8237,1432 @@
+ top_pll_v2_0/Down vssa1 vssa1 gpio_noesd[7] bias_0/iref_1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
+ top_pll_v2_0/out_to_div gpio_noesd[8] top_pll_v2_0/nDown top_pll_v2_0/biasp io_analog[8]
+ top_pll_v2_0/Up top_pll_v2_0/nUp top_pll_v2
-C0 bias_0/iref_7 bias_0/iref_5 10.35fF
-C1 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.21fF
-C2 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/clk 0.39fF
-C3 io_analog[4] bias_0/iref_9 15.97fF
-C4 bias_0/iref_8 bias_0/iref_7 13.23fF
-C5 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp 1.14fF
-C6 bias_0/iref_7 bias_0/iref_6 17.40fF
-C7 io_analog[10] gpio_noesd[8] 20.65fF
-C8 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_7 0.40fF
-C9 bias_0/iref_1 top_pll_v2_0/nUp 0.22fF
-C10 vdda1 io_analog[1] 76.56fF
-C11 vdda1 gpio_noesd[5] 124.75fF
-C12 io_analog[5] m3_222594_702300# 0.53fF
-C13 io_analog[3] gpio_noesd[5] 0.12fF
-C14 vdda1 top_pll_v1_0/nUp 0.01fF
-C15 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.72fF
-C16 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in 0.18fF
-C17 vdda1 bias_0/iref_2 3.90fF
-C18 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# gpio_noesd[5] 0.16fF
-C19 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_8 0.37fF
-C20 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[5] 0.26fF
-C21 bias_0/iref_1 top_pll_v2_0/Up 0.54fF
-C22 vdda1 top_pll_v1_0/pswitch 0.38fF
-C23 vdda1 bias_0/iref_5 30.67fF
-C24 vdda1 gpio_noesd[3] 120.88fF
-C25 vdda1 bias_0/iref_8 31.37fF
-C26 gpio_noesd[6] gpio_noesd[5] 0.05fF
-C27 bias_0/iref_2 io_analog[7] 13.22fF
-C28 vdda1 bias_0/iref_6 29.75fF
-C29 io_analog[3] bias_0/iref_5 13.88fF
-C30 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b gpio_noesd[1] 0.23fF
-C31 bias_0/iref_8 io_analog[3] 13.88fF
-C32 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outp 0.61fF
-C33 io_analog[3] bias_0/iref_6 13.88fF
-C34 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.78fF
-C35 top_pll_v1_0/charge_pump_0/w_2544_775# bias_0/iref_2 0.02fF
-C36 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_7 0.45fF
-C37 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in -0.70fF
-C38 vdda1 top_pll_v1_0/vco_vctrl 0.43fF
-C39 gpio_noesd[4] vdda1 117.64fF
-C40 vdda1 top_pll_v2_0/pswitch 0.34fF
-C41 gpio_noesd[4] io_analog[3] -0.78fF
-C42 vdda1 io_analog[9] 30.05fF
-C43 gpio_noesd[2] gpio_noesd[1] 0.30fF
-C44 bias_0/iref_0 top_pll_v1_1/nDown 0.74fF
-C45 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.22fF
-C46 top_pll_v1_0/QA io_analog[10] 0.03fF
-C47 io_analog[6] bias_0/iref_1 13.22fF
-C48 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out gpio_noesd[1] 0.21fF
-C49 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 -0.05fF
-C50 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA 0.49fF
-C51 io_analog[4] io_clamp_low[0] 0.53fF
-C52 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.17fF
-C53 io_analog[6] bias_0/iref_0 6.93fF
-C54 res_amp_top_0/res_amp_lin_prog_0/outp gpio_noesd[5] 0.44fF
-C55 vdda1 top_pll_v2_0/biasp 0.03fF
-C56 vdda1 top_pll_v1_0/biasp 0.03fF
-C57 io_analog[2] bias_0/iref_7 13.88fF
-C58 io_analog[6] io_clamp_high[2] 0.53fF
-C59 vdda1 bias_0/iref_9 30.24fF
-C60 io_analog[7] top_pll_v1_1/buffer_salida_0/a_3996_n100# -0.08fF
-C61 io_analog[6] io_analog[4] 0.59fF
-C62 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB 0.19fF
-C63 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl gpio_noesd[5] 0.33fF
-C64 bias_0/iref_9 io_analog[3] 13.88fF
-C65 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in 0.20fF
-C66 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.94fF
-C67 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp 1.01fF
-C68 bias_0/iref_2 top_pll_v1_0/nUp 0.70fF
-C69 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# -0.11fF
-C70 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.46fF
-C71 io_analog[4] bias_0/iref_7 15.97fF
-C72 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.12fF
-C73 gpio_noesd[4] gpio_noesd[5] 4.67fF
-C74 bias_0/iref_0 top_pll_v1_1/Up 0.74fF
-C75 vdda1 bias_0/iref_1 15.26fF
-C76 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outp -0.31fF
-C77 vdda1 top_pll_v2_0/nUp 0.01fF
-C78 vdda1 io_analog[2] 25.90fF
-C79 bias_0/iref_8 bias_0/iref_5 10.19fF
-C80 vdda1 bias_0/iref_0 15.18fF
-C81 bias_0/iref_5 bias_0/iref_6 29.11fF
-C82 io_analog[2] io_analog[3] 0.14fF
-C83 io_analog[7] bias_0/iref_1 13.22fF
-C84 gpio_noesd[2] vdda1 214.16fF
-C85 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_8 0.11fF
-C86 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.07fF
-C87 bias_0/iref_1 top_pll_v2_0/nDown 0.54fF
-C88 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[5] 0.68fF
-C89 vdda1 gpio_noesd[7] 120.83fF
-C90 bias_0/iref_2 io_analog[9] 14.44fF
-C91 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.17fF
-C92 gpio_noesd[7] top_pll_v2_0/vco_vctrl 0.05fF
-C93 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out 0.33fF
-C94 io_analog[4] vdda1 182.26fF
-C95 gpio_noesd[7] top_pll_v1_0/out_to_div 0.23fF
-C96 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA gpio_noesd[1] 0.29fF
-C97 io_analog[5] m3_226242_702300# 0.53fF
-C98 gpio_noesd[7] top_pll_v1_1/vco_vctrl 0.04fF
-C99 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_1008_774# 0.21fF
-C100 bias_0/iref_9 gpio_noesd[5] 1.30fF
-C101 vdda1 io_analog[8] 29.93fF
-C102 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out 0.19fF
-C103 gpio_noesd[7] gpio_noesd[8] 1.88fF
-C104 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.12fF
-C105 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.17fF
-C106 gpio_noesd[1] vdda1 214.54fF
-C107 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[6] 2.12fF
-C108 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outn 0.45fF
-C109 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.12fF
-C110 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/clk 0.21fF
-C111 top_pll_v1_0/biasp bias_0/iref_2 3.20fF
-C112 top_pll_v1_1/pswitch vdda1 0.48fF
-C113 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_5 0.45fF
-C114 bias_0/iref_1 top_pll_v2_0/charge_pump_0/w_2544_775# 0.09fF
-C115 gpio_noesd[7] top_pll_v1_1/out_to_div 0.15fF
-C116 gpio_noesd[7] top_pll_v2_0/out_to_div 0.23fF
-C117 gpio_noesd[7] io_analog[10] 29.88fF
-C118 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.42fF
-C119 res_amp_top_0/res_amp_sync_v2_0/rst bias_0/iref_9 0.39fF
-C120 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_6 0.15fF
-C121 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/clk -0.01fF
-C122 vdda1 top_pll_v1_0/buffer_salida_0/a_3996_n100# 0.06fF
-C123 io_analog[6] vdda1 124.15fF
-C124 bias_0/iref_9 bias_0/iref_8 9.89fF
-C125 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# 0.18fF
-C126 io_analog[2] gpio_noesd[5] 0.09fF
-C127 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C128 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_7 0.37fF
-C129 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in gpio_noesd[5] 0.47fF
-C130 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[3] 0.03fF
-C131 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_2544_775# 0.21fF
-C132 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[5] 0.44fF
-C133 res_amp_top_0/res_amp_lin_prog_0/outn gpio_noesd[5] 1.42fF
-C134 gpio_noesd[4] bias_0/iref_9 -0.25fF
-C135 vdda1 bias_0/iref_7 33.08fF
-C136 bias_0/iref_5 io_analog[5] 0.09fF
-C137 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB gpio_noesd[5] 0.14fF
-C138 bias_0/iref_0 top_pll_v1_1/nUp 0.74fF
-C139 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp 2.10fF
-C140 io_analog[3] bias_0/iref_7 13.88fF
-C141 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in gpio_noesd[5] 0.05fF
-C142 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.04fF
-C143 io_analog[2] bias_0/iref_5 13.88fF
-C144 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp gpio_noesd[5] 0.54fF
-C145 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out 0.57fF
-C146 io_analog[2] bias_0/iref_8 13.88fF
-C147 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[5] 0.14fF
-C148 io_analog[2] bias_0/iref_6 13.88fF
-C149 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.01fF
-C150 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out 0.21fF
-C151 io_analog[6] io_clamp_low[2] 0.53fF
-C152 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.01fF
-C153 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in bias_0/iref_5 0.46fF
-C154 io_analog[4] io_clamp_high[0] 0.53fF
-C155 gpio_noesd[4] io_analog[2] -0.21fF
-C156 bias_0/iref_5 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.46fF
-C157 io_analog[4] bias_0/iref_5 15.97fF
-C158 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.42fF
-C159 bias_0/iref_8 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.34fF
-C160 io_analog[4] bias_0/iref_8 15.97fF
-C161 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk -0.13fF
-C162 bias_0/iref_2 io_analog[8] 14.44fF
-C163 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outn -1.06fF
-C164 vdda1 top_pll_v2_0/vco_vctrl 0.59fF
-C165 io_analog[4] bias_0/iref_6 15.97fF
-C166 vdda1 io_analog[0] 76.77fF
-C167 vdda1 io_analog[3] 25.90fF
-C168 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.08fF
-C169 top_pll_v1_0/vco_vctrl gpio_noesd[7] 0.05fF
-C170 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# bias_0/iref_7 0.09fF
-C171 vdda1 io_analog[7] 29.48fF
-C172 bias_0/iref_2 top_pll_v1_0/Up 0.70fF
-C173 vdda1 top_pll_v1_1/vco_vctrl 0.54fF
-C174 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C175 bias_0/iref_0 top_pll_v1_1/Down 1.08fF
-C176 gpio_noesd[5] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.32fF
-C177 vdda1 gpio_noesd[8] 76.96fF
-C178 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp 0.17fF
-C179 bias_0/iref_1 top_pll_v2_0/biasp 2.20fF
-C180 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b 0.31fF
-C181 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[4] -0.08fF
-C182 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.04fF
-C183 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in 0.23fF
-C184 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/clk 0.37fF
-C185 bias_0/iref_2 top_pll_v1_0/nDown 0.70fF
-C186 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.04fF
-C187 io_analog[6] bias_0/iref_2 54.67fF
-C188 vdda1 gpio_noesd[6] 53.94fF
-C189 bias_0/iref_1 top_pll_v2_0/Down 0.91fF
-C190 bias_0/iref_9 io_analog[2] 13.88fF
-C191 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in 0.12fF
-C192 vdda1 io_analog[10] 0.01fF
-C193 bias_0/iref_0 top_pll_v1_1/biasp 3.13fF
-C194 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out 0.38fF
-C195 vdda1 top_pll_v2_0/buffer_salida_0/a_3996_n100# 0.05fF
-C196 bias_0/iref_2 top_pll_v1_0/Down 1.11fF
-C197 io_in_3v3[0] vssa1 0.41fF
-C198 io_oeb[26] vssa1 0.61fF
-C199 io_in[0] vssa1 0.41fF
-C200 io_out[26] vssa1 0.61fF
-C201 io_out[0] vssa1 0.41fF
-C202 io_in[26] vssa1 0.61fF
-C203 io_oeb[0] vssa1 0.41fF
-C204 io_in_3v3[26] vssa1 0.61fF
-C205 io_in_3v3[1] vssa1 0.41fF
-C206 io_oeb[25] vssa1 0.61fF
-C207 io_in[1] vssa1 0.41fF
-C208 io_out[25] vssa1 0.61fF
-C209 io_out[1] vssa1 0.41fF
-C210 io_in[25] vssa1 0.61fF
-C211 io_oeb[1] vssa1 0.41fF
-C212 io_in_3v3[25] vssa1 0.61fF
-C213 io_in_3v3[2] vssa1 0.41fF
-C214 io_oeb[24] vssa1 0.61fF
-C215 io_in[2] vssa1 0.41fF
-C216 io_out[24] vssa1 0.61fF
-C217 io_out[2] vssa1 0.41fF
-C218 io_in[24] vssa1 0.61fF
-C219 io_oeb[2] vssa1 -0.20fF
-C220 io_in_3v3[3] vssa1 0.41fF
-C221 gpio_noesd[17] vssa1 0.61fF
-C222 io_in[3] vssa1 0.41fF
-C223 gpio_analog[17] vssa1 0.61fF
-C224 io_out[3] vssa1 0.41fF
-C225 io_oeb[3] vssa1 0.41fF
-C226 io_in_3v3[4] vssa1 0.41fF
-C227 io_in[4] vssa1 0.41fF
-C228 io_out[4] vssa1 0.41fF
-C229 io_oeb[4] vssa1 0.41fF
-C230 io_oeb[23] vssa1 0.61fF
-C231 io_out[23] vssa1 0.61fF
-C232 io_in[23] vssa1 0.61fF
-C233 io_in_3v3[23] vssa1 0.61fF
-C234 gpio_noesd[16] vssa1 0.61fF
-C235 io_in_3v3[5] vssa1 0.41fF
-C236 io_in[5] vssa1 -0.20fF
-C237 io_out[5] vssa1 0.41fF
-C238 io_oeb[5] vssa1 0.41fF
-C239 io_oeb[22] vssa1 0.61fF
-C240 io_out[22] vssa1 0.61fF
-C241 io_in[22] vssa1 0.61fF
-C242 io_in_3v3[22] vssa1 0.61fF
-C243 gpio_analog[15] vssa1 0.61fF
-C244 io_in_3v3[6] vssa1 -0.20fF
-C245 io_in[6] vssa1 0.41fF
-C246 io_out[6] vssa1 0.41fF
-C247 io_oeb[6] vssa1 0.41fF
-C248 io_oeb[21] vssa1 0.61fF
-C249 io_out[21] vssa1 0.61fF
-C250 io_in[21] vssa1 0.61fF
-C251 io_in_3v3[21] vssa1 0.61fF
-C252 gpio_noesd[14] vssa1 0.61fF
-C253 gpio_analog[14] vssa1 0.61fF
-C254 vssd2 vssa1 -5.19fF
-C255 vssd1 vssa1 1.13fF
-C256 vdda2 vssa1 -5.19fF
-C257 io_oeb[20] vssa1 0.61fF
-C258 io_out[20] vssa1 0.61fF
-C259 io_in[20] vssa1 0.61fF
-C260 io_in_3v3[20] vssa1 0.61fF
-C261 gpio_noesd[13] vssa1 0.61fF
-C262 gpio_analog[13] vssa1 0.61fF
-C263 gpio_analog[0] vssa1 0.41fF
-C264 gpio_noesd[0] vssa1 0.41fF
-C265 io_in_3v3[7] vssa1 0.41fF
-C266 io_in[7] vssa1 0.41fF
-C267 io_out[7] vssa1 0.41fF
-C268 io_oeb[7] vssa1 0.41fF
-C269 io_oeb[19] vssa1 0.61fF
-C270 io_out[19] vssa1 0.61fF
-C271 io_in[19] vssa1 0.61fF
-C272 io_in_3v3[19] vssa1 0.61fF
-C273 gpio_noesd[12] vssa1 0.61fF
-C274 gpio_analog[12] vssa1 0.61fF
-C275 gpio_analog[1] vssa1 0.41fF
-C276 io_in_3v3[8] vssa1 0.41fF
-C277 io_in[8] vssa1 0.41fF
-C278 io_out[8] vssa1 -0.20fF
-C279 io_oeb[8] vssa1 0.41fF
-C280 gpio_analog[2] vssa1 0.41fF
-C281 io_in_3v3[9] vssa1 0.41fF
-C282 io_in[9] vssa1 0.41fF
-C283 io_out[9] vssa1 0.41fF
-C284 io_oeb[9] vssa1 0.41fF
-C285 gpio_analog[3] vssa1 0.41fF
-C286 io_in_3v3[10] vssa1 0.41fF
-C287 io_in[10] vssa1 0.41fF
-C288 io_out[10] vssa1 0.41fF
-C289 io_oeb[10] vssa1 0.41fF
-C290 gpio_analog[4] vssa1 0.41fF
-C291 io_in_3v3[11] vssa1 0.41fF
-C292 io_in[11] vssa1 0.41fF
-C293 io_out[11] vssa1 0.41fF
-C294 io_oeb[11] vssa1 0.41fF
-C295 gpio_analog[5] vssa1 0.41fF
-C296 io_in_3v3[12] vssa1 0.41fF
-C297 io_in[12] vssa1 0.41fF
-C298 io_out[12] vssa1 0.41fF
-C299 io_oeb[12] vssa1 0.41fF
-C300 gpio_analog[6] vssa1 0.60fF
-C301 io_in_3v3[13] vssa1 0.60fF
-C302 io_in[13] vssa1 0.60fF
-C303 io_out[13] vssa1 0.60fF
-C304 io_oeb[13] vssa1 0.60fF
-C305 io_oeb[18] vssa1 0.61fF
-C306 io_out[18] vssa1 0.61fF
-C307 io_in_3v3[18] vssa1 0.61fF
-C308 gpio_noesd[11] vssa1 0.61fF
-C309 gpio_analog[11] vssa1 0.61fF
-C310 io_oeb[17] vssa1 0.61fF
-C311 io_in[17] vssa1 0.61fF
-C312 io_in_3v3[17] vssa1 0.61fF
-C313 gpio_noesd[10] vssa1 0.61fF
-C314 gpio_analog[10] vssa1 0.61fF
-C315 io_out[16] vssa1 0.61fF
-C316 io_in[16] vssa1 0.61fF
-C317 io_in_3v3[16] vssa1 0.61fF
-C318 gpio_noesd[9] vssa1 0.61fF
-C319 gpio_analog[9] vssa1 0.61fF
-C320 io_oeb[15] vssa1 0.61fF
-C321 io_out[15] vssa1 0.61fF
-C322 io_in[15] vssa1 0.61fF
-C323 io_in_3v3[15] vssa1 0.61fF
-C324 vccd1 vssa1 0.85fF
-C325 gpio_analog[8] vssa1 0.61fF
-C326 io_oeb[14] vssa1 0.61fF
-C327 io_out[14] vssa1 0.61fF
-C328 io_in[14] vssa1 0.61fF
-C329 io_in_3v3[14] vssa1 0.61fF
-C330 vssa2 vssa1 1.66fF
-C331 vccd2 vssa1 0.91fF
-C332 io_clamp_high[0] vssa1 -2.60fF
-C333 io_clamp_low[0] vssa1 0.82fF
-C334 io_clamp_high[2] vssa1 0.66fF
-C335 io_clamp_low[2] vssa1 0.50fF
-C336 user_irq[2] vssa1 0.63fF
-C337 user_irq[1] vssa1 0.63fF
-C338 user_irq[0] vssa1 0.63fF
-C339 user_clock2 vssa1 0.63fF
-C340 la_oenb[127] vssa1 0.63fF
-C341 la_data_in[127] vssa1 0.63fF
-C342 la_oenb[126] vssa1 0.63fF
-C343 la_data_out[126] vssa1 0.63fF
-C344 la_data_in[126] vssa1 0.63fF
-C345 la_oenb[125] vssa1 0.63fF
-C346 la_data_out[125] vssa1 0.63fF
-C347 la_data_in[125] vssa1 0.63fF
-C348 la_oenb[124] vssa1 0.63fF
-C349 la_data_out[124] vssa1 0.63fF
-C350 la_data_in[124] vssa1 0.63fF
-C351 la_oenb[123] vssa1 0.63fF
-C352 la_data_out[123] vssa1 0.63fF
-C353 la_oenb[122] vssa1 0.63fF
-C354 la_data_out[122] vssa1 0.63fF
-C355 la_data_in[122] vssa1 0.63fF
-C356 la_oenb[121] vssa1 0.63fF
-C357 la_data_out[121] vssa1 0.63fF
-C358 la_data_in[121] vssa1 0.63fF
-C359 la_oenb[120] vssa1 0.63fF
-C360 la_data_out[120] vssa1 0.63fF
-C361 la_data_in[120] vssa1 0.63fF
-C362 la_oenb[119] vssa1 0.63fF
-C363 la_data_out[119] vssa1 0.63fF
-C364 la_data_in[119] vssa1 0.63fF
-C365 la_oenb[118] vssa1 0.63fF
-C366 la_data_out[118] vssa1 0.63fF
-C367 la_data_in[118] vssa1 0.63fF
-C368 la_oenb[117] vssa1 0.63fF
-C369 la_data_out[117] vssa1 0.63fF
-C370 la_data_in[117] vssa1 0.63fF
-C371 la_data_out[116] vssa1 0.63fF
-C372 la_data_in[116] vssa1 0.63fF
-C373 la_oenb[115] vssa1 0.63fF
-C374 la_data_out[115] vssa1 0.63fF
-C375 la_data_in[115] vssa1 0.63fF
-C376 la_oenb[114] vssa1 0.63fF
-C377 la_data_out[114] vssa1 0.63fF
-C378 la_data_in[114] vssa1 0.63fF
-C379 la_oenb[113] vssa1 0.63fF
-C380 la_data_out[113] vssa1 0.63fF
-C381 la_data_in[113] vssa1 0.63fF
-C382 la_oenb[112] vssa1 0.63fF
-C383 la_data_in[112] vssa1 0.63fF
-C384 la_oenb[111] vssa1 0.63fF
-C385 la_data_out[111] vssa1 0.63fF
-C386 la_data_in[111] vssa1 0.63fF
-C387 la_oenb[110] vssa1 0.63fF
-C388 la_data_out[110] vssa1 0.63fF
-C389 la_data_in[110] vssa1 0.63fF
-C390 la_oenb[109] vssa1 0.63fF
-C391 la_data_out[109] vssa1 0.63fF
-C392 la_data_in[109] vssa1 0.63fF
-C393 la_oenb[108] vssa1 0.63fF
-C394 la_data_out[108] vssa1 0.63fF
-C395 la_oenb[107] vssa1 0.63fF
-C396 la_data_out[107] vssa1 0.63fF
-C397 la_data_in[107] vssa1 0.63fF
-C398 la_oenb[106] vssa1 0.63fF
-C399 la_data_out[106] vssa1 0.63fF
-C400 la_oenb[105] vssa1 0.63fF
-C401 la_data_out[105] vssa1 0.63fF
-C402 la_data_in[105] vssa1 0.63fF
-C403 la_oenb[104] vssa1 0.63fF
-C404 la_data_out[104] vssa1 0.63fF
-C405 la_data_in[104] vssa1 0.63fF
-C406 la_oenb[103] vssa1 0.63fF
-C407 la_data_out[103] vssa1 0.63fF
-C408 la_data_in[103] vssa1 0.63fF
-C409 la_oenb[102] vssa1 0.63fF
-C410 la_data_out[102] vssa1 0.63fF
-C411 la_data_in[102] vssa1 0.63fF
-C412 la_data_out[101] vssa1 0.63fF
-C413 la_data_in[101] vssa1 0.63fF
-C414 la_oenb[100] vssa1 0.63fF
-C415 la_data_out[100] vssa1 0.63fF
-C416 la_data_in[100] vssa1 0.63fF
-C417 la_oenb[99] vssa1 0.63fF
-C418 la_data_out[99] vssa1 0.63fF
-C419 la_data_in[99] vssa1 0.63fF
-C420 la_oenb[98] vssa1 0.63fF
-C421 la_data_out[98] vssa1 0.63fF
-C422 la_data_in[98] vssa1 0.63fF
-C423 la_oenb[97] vssa1 0.63fF
-C424 la_data_in[97] vssa1 0.63fF
-C425 la_oenb[96] vssa1 0.63fF
-C426 la_data_out[96] vssa1 0.63fF
-C427 la_data_in[96] vssa1 0.63fF
-C428 la_oenb[95] vssa1 0.63fF
-C429 la_data_out[95] vssa1 0.63fF
-C430 la_data_in[95] vssa1 0.63fF
-C431 la_oenb[94] vssa1 0.63fF
-C432 la_data_out[94] vssa1 0.63fF
-C433 la_data_in[94] vssa1 0.63fF
-C434 la_oenb[93] vssa1 0.63fF
-C435 la_data_out[93] vssa1 0.63fF
-C436 la_oenb[92] vssa1 0.63fF
-C437 la_data_out[92] vssa1 0.63fF
-C438 la_data_in[92] vssa1 0.63fF
-C439 la_oenb[91] vssa1 0.63fF
-C440 la_data_out[91] vssa1 0.63fF
-C441 la_oenb[90] vssa1 0.63fF
-C442 la_data_out[90] vssa1 0.63fF
-C443 la_data_in[90] vssa1 0.63fF
-C444 la_oenb[89] vssa1 0.63fF
-C445 la_data_out[89] vssa1 0.63fF
-C446 la_data_in[89] vssa1 0.63fF
-C447 la_oenb[88] vssa1 0.63fF
-C448 la_data_out[88] vssa1 0.63fF
-C449 la_data_in[88] vssa1 0.63fF
-C450 la_oenb[87] vssa1 0.63fF
-C451 la_data_out[87] vssa1 0.63fF
-C452 la_data_in[87] vssa1 0.63fF
-C453 la_data_out[86] vssa1 0.63fF
-C454 la_data_in[86] vssa1 0.63fF
-C455 la_oenb[85] vssa1 0.63fF
-C456 la_data_out[85] vssa1 0.63fF
-C457 la_data_in[85] vssa1 0.63fF
-C458 la_oenb[84] vssa1 0.63fF
-C459 la_data_out[84] vssa1 0.63fF
-C460 la_data_in[84] vssa1 0.63fF
-C461 la_oenb[83] vssa1 0.63fF
-C462 la_data_out[83] vssa1 0.63fF
-C463 la_data_in[83] vssa1 0.63fF
-C464 la_oenb[82] vssa1 0.63fF
-C465 la_data_in[82] vssa1 0.63fF
-C466 la_oenb[81] vssa1 0.63fF
-C467 la_data_out[81] vssa1 0.63fF
-C468 la_data_in[81] vssa1 0.63fF
-C469 la_oenb[80] vssa1 0.63fF
-C470 la_data_out[80] vssa1 0.63fF
-C471 la_data_in[80] vssa1 0.63fF
-C472 la_oenb[79] vssa1 0.63fF
-C473 la_data_out[79] vssa1 0.63fF
-C474 la_data_in[79] vssa1 0.63fF
-C475 la_oenb[78] vssa1 0.63fF
-C476 la_data_out[78] vssa1 0.63fF
-C477 la_data_in[78] vssa1 0.63fF
-C478 la_oenb[77] vssa1 0.63fF
-C479 la_data_out[77] vssa1 0.63fF
-C480 la_data_in[77] vssa1 0.63fF
-C481 la_oenb[76] vssa1 0.63fF
-C482 la_data_out[76] vssa1 0.63fF
-C483 la_oenb[75] vssa1 0.63fF
-C484 la_data_out[75] vssa1 0.63fF
-C485 la_data_in[75] vssa1 0.63fF
-C486 la_oenb[74] vssa1 0.63fF
-C487 la_data_out[74] vssa1 0.63fF
-C488 la_data_in[74] vssa1 0.63fF
-C489 la_oenb[73] vssa1 0.63fF
-C490 la_data_out[73] vssa1 0.63fF
-C491 la_data_in[73] vssa1 0.63fF
-C492 la_oenb[72] vssa1 0.63fF
-C493 la_data_out[72] vssa1 0.63fF
-C494 la_data_in[72] vssa1 0.63fF
-C495 la_data_out[71] vssa1 0.63fF
-C496 la_data_in[71] vssa1 0.63fF
-C497 la_oenb[70] vssa1 0.63fF
-C498 la_data_out[70] vssa1 0.63fF
-C499 la_data_in[70] vssa1 0.63fF
-C500 la_oenb[69] vssa1 0.63fF
-C501 la_data_out[69] vssa1 0.63fF
-C502 la_data_in[69] vssa1 0.63fF
-C503 la_oenb[68] vssa1 0.63fF
-C504 la_data_out[68] vssa1 0.63fF
-C505 la_data_in[68] vssa1 0.63fF
-C506 la_oenb[67] vssa1 0.63fF
-C507 la_data_in[67] vssa1 0.63fF
-C508 la_oenb[66] vssa1 0.63fF
-C509 la_data_out[66] vssa1 0.63fF
-C510 la_data_in[66] vssa1 0.63fF
-C511 la_oenb[65] vssa1 0.63fF
-C512 la_data_out[65] vssa1 0.26fF
-C513 la_data_in[65] vssa1 0.63fF
-C514 la_oenb[64] vssa1 0.63fF
-C515 la_data_out[64] vssa1 0.63fF
-C516 la_data_in[64] vssa1 0.63fF
-C517 la_oenb[63] vssa1 0.63fF
-C518 la_data_out[63] vssa1 0.63fF
-C519 la_data_in[63] vssa1 0.63fF
-C520 la_oenb[62] vssa1 0.63fF
-C521 la_data_out[62] vssa1 0.63fF
-C522 la_data_in[62] vssa1 0.63fF
-C523 la_oenb[61] vssa1 0.63fF
-C524 la_data_out[61] vssa1 0.63fF
-C525 la_oenb[60] vssa1 0.63fF
-C526 la_data_out[60] vssa1 0.63fF
-C527 la_data_in[60] vssa1 0.63fF
-C528 la_oenb[59] vssa1 0.63fF
-C529 la_data_out[59] vssa1 0.63fF
-C530 la_data_in[59] vssa1 0.63fF
-C531 la_oenb[58] vssa1 0.63fF
-C532 la_data_out[58] vssa1 0.63fF
-C533 la_data_in[58] vssa1 0.63fF
-C534 la_oenb[57] vssa1 0.63fF
-C535 la_data_out[57] vssa1 0.63fF
-C536 la_data_in[57] vssa1 0.63fF
-C537 la_data_out[56] vssa1 0.63fF
-C538 la_data_in[56] vssa1 0.63fF
-C539 la_oenb[55] vssa1 0.63fF
-C540 la_data_out[55] vssa1 0.63fF
-C541 la_data_in[55] vssa1 0.63fF
-C542 la_oenb[54] vssa1 0.63fF
-C543 la_data_out[54] vssa1 0.63fF
-C544 la_data_in[54] vssa1 0.63fF
-C545 la_oenb[53] vssa1 0.63fF
-C546 la_data_out[53] vssa1 0.63fF
-C547 la_data_in[53] vssa1 0.63fF
-C548 la_oenb[52] vssa1 0.63fF
-C549 la_data_in[52] vssa1 0.63fF
-C550 la_oenb[51] vssa1 0.63fF
-C551 la_data_out[51] vssa1 0.63fF
-C552 la_data_in[51] vssa1 0.63fF
-C553 la_oenb[50] vssa1 0.63fF
-C554 la_data_in[50] vssa1 0.63fF
-C555 la_oenb[49] vssa1 0.63fF
-C556 la_data_out[49] vssa1 0.63fF
-C557 la_data_in[49] vssa1 0.63fF
-C558 la_oenb[48] vssa1 0.63fF
-C559 la_data_out[48] vssa1 0.63fF
-C560 la_data_in[48] vssa1 0.63fF
-C561 la_oenb[47] vssa1 0.63fF
-C562 la_data_out[47] vssa1 0.63fF
-C563 la_data_in[47] vssa1 0.63fF
-C564 la_oenb[46] vssa1 0.63fF
-C565 la_data_out[46] vssa1 0.63fF
-C566 la_oenb[45] vssa1 0.63fF
-C567 la_data_out[45] vssa1 0.63fF
-C568 la_data_in[45] vssa1 0.63fF
-C569 la_oenb[44] vssa1 0.63fF
-C570 la_data_out[44] vssa1 0.63fF
-C571 la_data_in[44] vssa1 0.63fF
-C572 la_oenb[43] vssa1 0.63fF
-C573 la_data_out[43] vssa1 0.63fF
-C574 la_data_in[43] vssa1 0.63fF
-C575 la_oenb[42] vssa1 0.63fF
-C576 la_data_out[42] vssa1 0.63fF
-C577 la_data_in[42] vssa1 0.63fF
-C578 la_data_out[41] vssa1 0.63fF
-C579 la_data_in[41] vssa1 0.63fF
-C580 la_oenb[40] vssa1 0.63fF
-C581 la_data_out[40] vssa1 0.63fF
-C582 la_data_in[40] vssa1 0.63fF
-C583 la_oenb[39] vssa1 0.63fF
-C584 la_data_out[39] vssa1 0.63fF
-C585 la_data_in[39] vssa1 0.63fF
-C586 la_oenb[38] vssa1 0.63fF
-C587 la_data_out[38] vssa1 0.63fF
-C588 la_data_in[38] vssa1 0.63fF
-C589 la_oenb[37] vssa1 0.63fF
-C590 la_data_out[37] vssa1 0.26fF
-C591 la_data_in[37] vssa1 0.63fF
-C592 la_oenb[36] vssa1 0.63fF
-C593 la_data_out[36] vssa1 0.63fF
-C594 la_data_in[36] vssa1 0.63fF
-C595 la_oenb[35] vssa1 0.63fF
-C596 la_data_in[35] vssa1 0.63fF
-C597 la_oenb[34] vssa1 0.63fF
-C598 la_data_out[34] vssa1 0.63fF
-C599 la_data_in[34] vssa1 0.63fF
-C600 la_oenb[33] vssa1 0.63fF
-C601 la_data_out[33] vssa1 0.63fF
-C602 la_data_in[33] vssa1 0.63fF
-C603 la_oenb[32] vssa1 0.63fF
-C604 la_data_out[32] vssa1 0.63fF
-C605 la_data_in[32] vssa1 0.63fF
-C606 la_oenb[31] vssa1 0.63fF
-C607 la_data_out[31] vssa1 0.63fF
-C608 la_oenb[30] vssa1 0.63fF
-C609 la_data_out[30] vssa1 0.63fF
-C610 la_data_in[30] vssa1 0.63fF
-C611 la_oenb[29] vssa1 0.63fF
-C612 la_data_out[29] vssa1 0.63fF
-C613 la_data_in[29] vssa1 0.63fF
-C614 la_oenb[28] vssa1 0.63fF
-C615 la_data_out[28] vssa1 0.63fF
-C616 la_data_in[28] vssa1 0.63fF
-C617 la_oenb[27] vssa1 0.63fF
-C618 la_data_out[27] vssa1 0.63fF
-C619 la_data_in[27] vssa1 0.63fF
-C620 la_data_out[26] vssa1 0.63fF
-C621 la_data_in[26] vssa1 0.63fF
-C622 la_oenb[25] vssa1 0.63fF
-C623 la_data_out[25] vssa1 0.63fF
-C624 la_data_in[25] vssa1 0.63fF
-C625 la_oenb[24] vssa1 0.63fF
-C626 la_data_out[24] vssa1 0.63fF
-C627 la_data_in[24] vssa1 0.63fF
-C628 la_oenb[23] vssa1 0.63fF
-C629 la_data_out[23] vssa1 0.63fF
-C630 la_data_in[23] vssa1 0.63fF
-C631 la_oenb[22] vssa1 0.63fF
-C632 la_data_out[22] vssa1 0.63fF
-C633 la_data_in[22] vssa1 0.63fF
-C634 la_oenb[21] vssa1 0.63fF
-C635 la_data_out[21] vssa1 0.63fF
-C636 la_data_in[21] vssa1 0.63fF
-C637 la_oenb[20] vssa1 0.63fF
-C638 la_data_in[20] vssa1 0.63fF
-C639 la_oenb[19] vssa1 0.63fF
-C640 la_data_out[19] vssa1 0.63fF
-C641 la_data_in[19] vssa1 0.63fF
-C642 la_oenb[18] vssa1 0.63fF
-C643 la_data_out[18] vssa1 0.63fF
-C644 la_data_in[18] vssa1 0.63fF
-C645 la_oenb[17] vssa1 0.63fF
-C646 la_data_out[17] vssa1 0.63fF
-C647 la_data_in[17] vssa1 0.63fF
-C648 la_oenb[16] vssa1 0.63fF
-C649 la_data_out[16] vssa1 0.63fF
-C650 la_oenb[15] vssa1 0.63fF
-C651 la_data_out[15] vssa1 0.63fF
-C652 la_data_in[15] vssa1 0.63fF
-C653 la_oenb[14] vssa1 0.63fF
-C654 la_data_out[14] vssa1 0.63fF
-C655 la_data_in[14] vssa1 0.63fF
-C656 la_oenb[13] vssa1 0.63fF
-C657 la_data_out[13] vssa1 0.63fF
-C658 la_data_in[13] vssa1 0.63fF
-C659 la_oenb[12] vssa1 0.63fF
-C660 la_data_out[12] vssa1 0.63fF
-C661 la_data_in[12] vssa1 0.63fF
-C662 la_data_out[11] vssa1 0.63fF
-C663 la_data_in[11] vssa1 0.63fF
-C664 la_oenb[10] vssa1 0.63fF
-C665 la_data_out[10] vssa1 0.63fF
-C666 la_data_in[10] vssa1 0.63fF
-C667 la_data_out[9] vssa1 0.63fF
-C668 la_data_in[9] vssa1 0.63fF
-C669 la_oenb[8] vssa1 0.63fF
-C670 la_data_out[8] vssa1 0.63fF
-C671 la_data_in[8] vssa1 0.63fF
-C672 la_oenb[7] vssa1 0.63fF
-C673 la_data_out[7] vssa1 0.63fF
-C674 la_data_in[7] vssa1 0.63fF
-C675 la_oenb[6] vssa1 0.63fF
-C676 la_data_out[6] vssa1 0.63fF
-C677 la_data_in[6] vssa1 0.63fF
-C678 la_oenb[5] vssa1 0.63fF
-C679 la_data_in[5] vssa1 0.63fF
-C680 la_oenb[4] vssa1 0.63fF
-C681 la_data_out[4] vssa1 0.63fF
-C682 la_data_in[4] vssa1 0.63fF
-C683 la_oenb[3] vssa1 0.63fF
-C684 la_data_out[3] vssa1 0.63fF
-C685 la_data_in[3] vssa1 0.63fF
-C686 la_oenb[2] vssa1 0.63fF
-C687 la_data_out[2] vssa1 0.63fF
-C688 la_data_in[2] vssa1 0.63fF
-C689 la_oenb[1] vssa1 0.63fF
-C690 la_data_out[1] vssa1 0.63fF
-C691 la_oenb[0] vssa1 0.63fF
-C692 la_data_out[0] vssa1 0.63fF
-C693 la_data_in[0] vssa1 0.63fF
-C694 wbs_dat_o[31] vssa1 0.63fF
-C695 wbs_dat_i[31] vssa1 0.63fF
-C696 wbs_adr_i[31] vssa1 0.63fF
-C697 wbs_dat_o[30] vssa1 0.63fF
-C698 wbs_dat_i[30] vssa1 0.63fF
-C699 wbs_adr_i[30] vssa1 0.63fF
-C700 wbs_dat_o[29] vssa1 0.63fF
-C701 wbs_dat_i[29] vssa1 0.63fF
-C702 wbs_adr_i[29] vssa1 0.63fF
-C703 wbs_dat_i[28] vssa1 0.63fF
-C704 wbs_adr_i[28] vssa1 0.63fF
-C705 wbs_dat_o[27] vssa1 0.63fF
-C706 wbs_dat_i[27] vssa1 0.63fF
-C707 wbs_adr_i[27] vssa1 0.63fF
-C708 wbs_dat_i[26] vssa1 0.63fF
-C709 wbs_adr_i[26] vssa1 0.63fF
-C710 wbs_dat_o[25] vssa1 0.63fF
-C711 wbs_dat_i[25] vssa1 0.63fF
-C712 wbs_adr_i[25] vssa1 0.63fF
-C713 wbs_dat_o[24] vssa1 0.63fF
-C714 wbs_dat_i[24] vssa1 0.63fF
-C715 wbs_adr_i[24] vssa1 0.63fF
-C716 wbs_dat_o[23] vssa1 0.63fF
-C717 wbs_dat_i[23] vssa1 0.63fF
-C718 wbs_adr_i[23] vssa1 0.63fF
-C719 wbs_dat_o[22] vssa1 0.63fF
-C720 wbs_adr_i[22] vssa1 0.63fF
-C721 wbs_dat_o[21] vssa1 0.63fF
-C722 wbs_dat_i[21] vssa1 0.63fF
-C723 wbs_adr_i[21] vssa1 0.63fF
-C724 wbs_dat_o[20] vssa1 0.63fF
-C725 wbs_dat_i[20] vssa1 0.63fF
-C726 wbs_adr_i[20] vssa1 0.63fF
-C727 wbs_dat_o[19] vssa1 0.63fF
-C728 wbs_dat_i[19] vssa1 0.63fF
-C729 wbs_adr_i[19] vssa1 0.63fF
-C730 wbs_dat_o[18] vssa1 0.63fF
-C731 wbs_dat_i[18] vssa1 0.63fF
-C732 wbs_dat_o[17] vssa1 0.63fF
-C733 wbs_dat_i[17] vssa1 0.63fF
-C734 wbs_adr_i[17] vssa1 0.63fF
-C735 wbs_dat_o[16] vssa1 0.63fF
-C736 wbs_dat_i[16] vssa1 0.63fF
-C737 wbs_adr_i[16] vssa1 0.63fF
-C738 wbs_dat_o[15] vssa1 0.63fF
-C739 wbs_dat_i[15] vssa1 0.63fF
-C740 wbs_adr_i[15] vssa1 0.63fF
-C741 wbs_dat_o[14] vssa1 0.63fF
-C742 wbs_dat_i[14] vssa1 0.63fF
-C743 wbs_adr_i[14] vssa1 0.63fF
-C744 wbs_dat_o[13] vssa1 0.63fF
-C745 wbs_dat_i[13] vssa1 0.63fF
-C746 wbs_adr_i[13] vssa1 0.63fF
-C747 wbs_dat_o[12] vssa1 0.63fF
-C748 wbs_dat_i[12] vssa1 0.63fF
-C749 wbs_adr_i[12] vssa1 0.63fF
-C750 wbs_dat_i[11] vssa1 0.63fF
-C751 wbs_adr_i[11] vssa1 0.63fF
-C752 wbs_dat_o[10] vssa1 0.63fF
-C753 wbs_dat_i[10] vssa1 0.63fF
-C754 wbs_adr_i[10] vssa1 0.63fF
-C755 wbs_dat_o[9] vssa1 0.63fF
-C756 wbs_dat_i[9] vssa1 0.63fF
-C757 wbs_adr_i[9] vssa1 0.63fF
-C758 wbs_dat_o[8] vssa1 0.63fF
-C759 wbs_dat_i[8] vssa1 0.63fF
-C760 wbs_adr_i[8] vssa1 0.63fF
-C761 wbs_dat_o[7] vssa1 0.63fF
-C762 wbs_adr_i[7] vssa1 0.63fF
-C763 wbs_dat_o[6] vssa1 0.63fF
-C764 wbs_dat_i[6] vssa1 0.63fF
-C765 wbs_adr_i[6] vssa1 0.63fF
-C766 wbs_dat_o[5] vssa1 0.63fF
-C767 wbs_dat_i[5] vssa1 0.63fF
-C768 wbs_adr_i[5] vssa1 0.63fF
-C769 wbs_dat_o[4] vssa1 0.63fF
-C770 wbs_dat_i[4] vssa1 0.63fF
-C771 wbs_adr_i[4] vssa1 0.63fF
-C772 wbs_sel_i[3] vssa1 0.63fF
-C773 wbs_dat_o[3] vssa1 0.63fF
-C774 wbs_adr_i[3] vssa1 0.63fF
-C775 wbs_sel_i[2] vssa1 0.63fF
-C776 wbs_dat_o[2] vssa1 0.63fF
-C777 wbs_dat_i[2] vssa1 0.63fF
-C778 wbs_adr_i[2] vssa1 0.63fF
-C779 wbs_dat_o[1] vssa1 0.63fF
-C780 wbs_dat_i[1] vssa1 0.63fF
-C781 wbs_adr_i[1] vssa1 0.63fF
-C782 wbs_sel_i[0] vssa1 0.63fF
-C783 wbs_dat_o[0] vssa1 0.63fF
-C784 wbs_dat_i[0] vssa1 0.63fF
-C785 wbs_adr_i[0] vssa1 0.63fF
-C786 wbs_we_i vssa1 0.63fF
-C787 wbs_stb_i vssa1 0.63fF
-C788 wbs_cyc_i vssa1 0.63fF
-C789 wbs_ack_o vssa1 0.63fF
-C790 wb_rst_i vssa1 0.63fF
-C791 m3_226242_702300# vssa1 -1.31fF
-C792 m3_222594_702300# vssa1 0.55fF
-C793 top_pll_v2_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C794 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C795 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C796 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C797 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C798 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C799 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C800 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C801 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C802 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C803 top_pll_v2_0/QB vssa1 4.35fF
-C804 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C805 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C806 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C807 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C808 top_pll_v2_0/out_div_by_5 vssa1 -0.40fF
-C809 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C810 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C811 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C812 top_pll_v2_0/pfd_reset vssa1 2.17fF
-C813 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C814 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C815 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C816 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C817 top_pll_v2_0/QA vssa1 4.22fF
-C818 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C819 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C820 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C821 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C822 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C823 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C824 top_pll_v2_0/nUp vssa1 5.39fF
-C825 top_pll_v2_0/Up vssa1 1.85fF
-C826 top_pll_v2_0/Down vssa1 6.19fF
-C827 top_pll_v2_0/nDown vssa1 -3.53fF
-C828 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C829 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C830 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C831 top_pll_v2_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C832 top_pll_v2_0/div_5_Q1_shift vssa1 -0.14fF
-C833 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C834 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C835 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C836 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C837 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C838 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C839 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C840 top_pll_v2_0/div_5_Q1 vssa1 4.25fF
-C841 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C842 top_pll_v2_0/div_5_nQ0 vssa1 0.59fF
-C843 top_pll_v2_0/div_5_Q0 vssa1 0.01fF
-C844 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C845 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C846 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C847 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C848 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C849 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C850 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C851 top_pll_v2_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C852 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C853 top_pll_v2_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C854 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C855 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C856 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C857 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C858 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C859 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C860 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C861 top_pll_v2_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C862 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C863 top_pll_v2_0/div_5_nQ2 vssa1 1.24fF
-C864 top_pll_v2_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C865 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C866 top_pll_v2_0/n_out_by_2 vssa1 -2.75fF
-C867 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C868 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C869 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C870 top_pll_v2_0/out_by_2 vssa1 -5.01fF
-C871 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C872 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C873 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C874 top_pll_v2_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C875 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C876 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C877 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C878 top_pll_v2_0/out_first_buffer vssa1 2.88fF
-C879 top_pll_v2_0/out_to_div vssa1 4.23fF
-C880 top_pll_v2_0/out_to_buffer vssa1 1.54fF
-C881 top_pll_v2_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C882 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C883 top_pll_v2_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C884 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C885 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C886 top_pll_v2_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C887 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C888 top_pll_v2_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C889 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C890 top_pll_v2_0/vco_out vssa1 1.01fF
-C891 top_pll_v2_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C892 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C893 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C894 top_pll_v2_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
-C895 io_analog[8] vssa1 13.78fF
-C896 top_pll_v2_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C897 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C898 top_pll_v2_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C899 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C900 top_pll_v2_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C901 top_pll_v2_0/out_buffer_div_2 vssa1 1.60fF
-C902 top_pll_v2_0/n_out_buffer_div_2 vssa1 1.63fF
-C903 top_pll_v2_0/out_div_2 vssa1 -1.30fF
-C904 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C905 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C906 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C907 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C908 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C909 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C910 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C911 top_pll_v2_0/n_out_div_2 vssa1 1.95fF
-C912 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C913 top_pll_v2_0/lf_vc vssa1 -59.89fF
-C914 top_pll_v2_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
-C915 gpio_noesd[8] vssa1 210.79fF
-C916 top_pll_v2_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
-C917 top_pll_v2_0/nswitch vssa1 3.73fF
-C918 top_pll_v2_0/biasp vssa1 5.44fF
-C919 bias_0/iref_1 vssa1 -91.53fF
-C920 top_pll_v2_0/vco_vctrl vssa1 -20.08fF
-C921 top_pll_v2_0/pswitch vssa1 3.57fF
-C922 io_analog[5] vssa1 33.29fF
-C923 bias_0/iref_4 vssa1 1.17fF
-C924 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vssa1 2.60fF
-C925 bias_0/iref_3 vssa1 0.64fF
-C926 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vssa1 2.60fF
-C927 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vssa1 2.60fF
-C928 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vssa1 2.60fF
-C929 bias_0/m1_20168_984# vssa1 56.92fF
-C930 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vssa1 2.60fF
-C931 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vssa1 2.60fF
-C932 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vssa1 2.60fF
-C933 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vssa1 2.60fF
-C934 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vssa1 2.60fF
-C935 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vssa1 2.60fF
-C936 top_pll_v1_1/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C937 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C938 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C939 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C940 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C941 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C942 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C943 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C944 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C945 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C946 top_pll_v1_1/QB vssa1 4.35fF
-C947 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C948 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C949 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C950 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C951 top_pll_v1_1/out_div_by_5 vssa1 -0.40fF
-C952 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C953 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C954 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C955 top_pll_v1_1/pfd_reset vssa1 2.17fF
-C956 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C957 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C958 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C959 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C960 top_pll_v1_1/QA vssa1 4.22fF
-C961 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C962 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C963 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C964 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C965 io_analog[10] vssa1 503.33fF
-C966 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C967 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C968 top_pll_v1_1/nUp vssa1 5.39fF
-C969 top_pll_v1_1/Up vssa1 1.85fF
-C970 top_pll_v1_1/Down vssa1 6.19fF
-C971 top_pll_v1_1/nDown vssa1 -3.53fF
-C972 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C973 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C974 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C975 top_pll_v1_1/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C976 top_pll_v1_1/div_5_Q1_shift vssa1 -0.14fF
-C977 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C978 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C979 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C980 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C981 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C982 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C983 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C984 top_pll_v1_1/div_5_Q1 vssa1 4.25fF
-C985 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C986 top_pll_v1_1/div_5_nQ0 vssa1 0.59fF
-C987 top_pll_v1_1/div_5_Q0 vssa1 0.01fF
-C988 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C989 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C990 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C991 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C992 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C993 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C994 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C995 top_pll_v1_1/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C996 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C997 top_pll_v1_1/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C998 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C999 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C1000 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C1001 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1002 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1003 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C1004 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1005 top_pll_v1_1/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C1006 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C1007 top_pll_v1_1/div_5_nQ2 vssa1 1.24fF
-C1008 top_pll_v1_1/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C1009 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1010 top_pll_v1_1/n_out_by_2 vssa1 -2.75fF
-C1011 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1012 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1013 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1014 top_pll_v1_1/out_by_2 vssa1 -5.01fF
-C1015 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1016 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1017 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1018 top_pll_v1_1/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C1019 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1020 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C1021 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C1022 top_pll_v1_1/out_first_buffer vssa1 2.88fF
-C1023 top_pll_v1_1/out_to_div vssa1 4.23fF
-C1024 top_pll_v1_1/out_to_buffer vssa1 1.54fF
-C1025 top_pll_v1_1/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C1026 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C1027 top_pll_v1_1/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C1028 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C1029 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C1030 top_pll_v1_1/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C1031 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C1032 top_pll_v1_1/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C1033 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C1034 top_pll_v1_1/vco_out vssa1 1.01fF
-C1035 top_pll_v1_1/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C1036 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C1037 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C1038 top_pll_v1_1/buffer_salida_0/a_3996_n100# vssa1 48.11fF
-C1039 io_analog[7] vssa1 24.61fF
-C1040 top_pll_v1_1/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C1041 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1042 top_pll_v1_1/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C1043 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1044 top_pll_v1_1/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C1045 top_pll_v1_1/out_buffer_div_2 vssa1 1.60fF
-C1046 top_pll_v1_1/n_out_buffer_div_2 vssa1 1.63fF
-C1047 top_pll_v1_1/out_div_2 vssa1 -1.30fF
-C1048 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1049 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1050 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1051 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1052 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1053 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1054 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1055 top_pll_v1_1/n_out_div_2 vssa1 1.95fF
-C1056 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1057 top_pll_v1_1/nswitch vssa1 3.73fF
-C1058 top_pll_v1_1/biasp vssa1 5.44fF
-C1059 bias_0/iref_0 vssa1 -81.35fF
-C1060 top_pll_v1_1/vco_vctrl vssa1 -18.17fF
-C1061 top_pll_v1_1/pswitch vssa1 3.57fF
-C1062 top_pll_v1_1/lf_vc vssa1 -59.89fF
-C1063 top_pll_v1_1/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
-C1064 top_pll_v1_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C1065 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C1066 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C1067 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1068 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C1069 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1070 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1071 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1072 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C1073 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1074 top_pll_v1_0/QB vssa1 4.35fF
-C1075 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1076 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C1077 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1078 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1079 top_pll_v1_0/out_div_by_5 vssa1 -0.40fF
-C1080 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1081 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C1082 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1083 top_pll_v1_0/pfd_reset vssa1 2.17fF
-C1084 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1085 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1086 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C1087 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1088 top_pll_v1_0/QA vssa1 4.22fF
-C1089 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1090 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C1091 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C1092 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C1093 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C1094 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C1095 top_pll_v1_0/nUp vssa1 5.39fF
-C1096 top_pll_v1_0/Up vssa1 1.85fF
-C1097 top_pll_v1_0/Down vssa1 6.19fF
-C1098 top_pll_v1_0/nDown vssa1 -3.53fF
-C1099 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C1100 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C1101 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C1102 top_pll_v1_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C1103 top_pll_v1_0/div_5_Q1_shift vssa1 -0.14fF
-C1104 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1105 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C1106 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C1107 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1108 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1109 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C1110 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1111 top_pll_v1_0/div_5_Q1 vssa1 4.25fF
-C1112 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C1113 top_pll_v1_0/div_5_nQ0 vssa1 0.59fF
-C1114 top_pll_v1_0/div_5_Q0 vssa1 0.01fF
-C1115 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1116 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C1117 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C1118 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1119 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1120 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C1121 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1122 top_pll_v1_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C1123 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C1124 top_pll_v1_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C1125 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1126 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C1127 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C1128 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1129 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1130 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C1131 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1132 top_pll_v1_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C1133 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C1134 top_pll_v1_0/div_5_nQ2 vssa1 1.24fF
-C1135 top_pll_v1_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C1136 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1137 top_pll_v1_0/n_out_by_2 vssa1 -2.75fF
-C1138 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1139 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1140 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1141 top_pll_v1_0/out_by_2 vssa1 -5.01fF
-C1142 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1143 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1144 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1145 top_pll_v1_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C1146 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1147 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C1148 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C1149 top_pll_v1_0/out_first_buffer vssa1 2.88fF
-C1150 top_pll_v1_0/out_to_div vssa1 4.23fF
-C1151 top_pll_v1_0/out_to_buffer vssa1 1.54fF
-C1152 top_pll_v1_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C1153 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C1154 top_pll_v1_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C1155 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C1156 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C1157 top_pll_v1_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C1158 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C1159 top_pll_v1_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C1160 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C1161 top_pll_v1_0/vco_out vssa1 1.01fF
-C1162 gpio_noesd[7] vssa1 272.21fF
-C1163 top_pll_v1_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C1164 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C1165 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C1166 top_pll_v1_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
-C1167 io_analog[9] vssa1 7.89fF
-C1168 top_pll_v1_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C1169 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1170 top_pll_v1_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C1171 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1172 top_pll_v1_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C1173 top_pll_v1_0/out_buffer_div_2 vssa1 1.60fF
-C1174 top_pll_v1_0/n_out_buffer_div_2 vssa1 1.63fF
-C1175 top_pll_v1_0/out_div_2 vssa1 -1.30fF
-C1176 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1177 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1178 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1179 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1180 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1181 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1182 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1183 top_pll_v1_0/n_out_div_2 vssa1 1.95fF
-C1184 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1185 top_pll_v1_0/nswitch vssa1 3.73fF
-C1186 top_pll_v1_0/biasp vssa1 5.44fF
-C1187 bias_0/iref_2 vssa1 -178.91fF
-C1188 top_pll_v1_0/vco_vctrl vssa1 -18.17fF
-C1189 top_pll_v1_0/pswitch vssa1 3.57fF
-C1190 top_pll_v1_0/lf_vc vssa1 -59.89fF
-C1191 top_pll_v1_0/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
-C1192 bias_0/iref_6 vssa1 -645.65fF
-C1193 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in vssa1 -32.98fF
-C1194 io_analog[1] vssa1 74.58fF
-C1195 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# vssa1 1.29fF
-C1196 bias_0/iref_5 vssa1 -623.45fF
-C1197 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in vssa1 -32.98fF
-C1198 io_analog[0] vssa1 -154.61fF
-C1199 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# vssa1 1.29fF
-C1200 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# vssa1 -35.44fF
-C1201 bias_0/iref_8 vssa1 -189.06fF
-C1202 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# vssa1 -35.44fF
-C1203 bias_0/iref_7 vssa1 -205.18fF
-C1204 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# vssa1 -1.87fF
-C1205 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# vssa1 0.47fF
-C1206 gpio_noesd[5] vssa1 122.09fF
-C1207 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# vssa1 -1.10fF
-C1208 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl vssa1 -2.03fF
-C1209 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# vssa1 -2.23fF
-C1210 gpio_noesd[6] vssa1 325.91fF
-C1211 gpio_noesd[4] vssa1 116.78fF
-C1212 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# vssa1 -1.03fF
-C1213 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# vssa1 0.51fF
-C1214 bias_0/iref_9 vssa1 -181.57fF
-C1215 res_amp_top_0/res_amp_lin_prog_0/outn vssa1 1.55fF
-C1216 io_analog[3] vssa1 -119.52fF
-C1217 res_amp_top_0/res_amp_lin_prog_0/outp vssa1 -4.89fF
-C1218 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp vssa1 -4.89fF
-C1219 io_analog[2] vssa1 -131.04fF
-C1220 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# vssa1 -0.95fF
-C1221 res_amp_top_0/res_amp_lin_prog_0/outn_cap vssa1 -0.01fF
-C1222 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk vssa1 4.27fF
-C1223 res_amp_top_0/res_amp_lin_prog_0/inverter_min_x4_0/out vssa1 4.60fF
-C1224 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in vssa1 1.07fF
-C1225 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in vssa1 1.03fF
-C1226 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in vssa1 1.03fF
-C1227 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in vssa1 1.07fF
-C1228 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in vssa1 1.03fF
-C1229 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in vssa1 1.03fF
-C1230 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in vssa1 1.07fF
-C1231 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in vssa1 1.03fF
-C1232 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in vssa1 1.07fF
-C1233 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in vssa1 1.03fF
-C1234 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in vssa1 1.03fF
-C1235 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in vssa1 1.03fF
-C1236 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in vssa1 1.07fF
-C1237 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB vssa1 -7.88fF
-C1238 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in vssa1 1.03fF
-C1239 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in vssa1 1.03fF
-C1240 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in vssa1 1.07fF
-C1241 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in vssa1 1.03fF
-C1242 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
-C1243 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in vssa1 1.03fF
-C1244 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b vssa1 2.03fF
-C1245 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 vssa1 1.54fF
-C1246 gpio_noesd[3] vssa1 213.06fF
-C1247 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b vssa1 2.03fF
-C1248 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out vssa1 -1.67fF
-C1249 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA vssa1 -2.58fF
-C1250 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b vssa1 2.03fF
-C1251 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out vssa1 -2.25fF
-C1252 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA vssa1 -0.04fF
-C1253 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b vssa1 2.03fF
-C1254 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out vssa1 -2.69fF
-C1255 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB vssa1 -4.96fF
-C1256 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b vssa1 2.03fF
-C1257 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out vssa1 -4.71fF
-C1258 gpio_noesd[2] vssa1 216.13fF
-C1259 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA vssa1 0.63fF
-C1260 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b vssa1 2.03fF
-C1261 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out vssa1 -2.49fF
-C1262 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB vssa1 -3.92fF
-C1263 gpio_noesd[1] vssa1 230.09fF
-C1264 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b vssa1 2.03fF
-C1265 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out vssa1 -0.27fF
-C1266 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB vssa1 -0.97fF
-C1267 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in vssa1 1.07fF
-C1268 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in vssa1 1.03fF
-C1269 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in vssa1 1.03fF
-C1270 res_amp_top_0/res_amp_lin_prog_0/outp_cap vssa1 -7.66fF
-C1271 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/m1_21_n341# vssa1 0.72fF
-C1272 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
-C1273 res_amp_top_0/res_amp_lin_prog_0/clk vssa1 -8.26fF
-C1274 res_amp_top_0/res_amp_sync_v2_0/inverter_min_x4_4/out vssa1 5.85fF
-C1275 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/out vssa1 1.70fF
-C1276 res_amp_top_0/res_amp_sync_v2_0/rst vssa1 -7.88fF
-C1277 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/nQ vssa1 0.48fF
-C1278 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/Q vssa1 -2.08fF
-C1279 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1280 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD vssa1 0.57fF
-C1281 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D vssa1 -1.73fF
-C1282 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1283 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1284 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D vssa1 0.96fF
-C1285 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1286 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/D vssa1 1.83fF
-C1287 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD vssa1 1.14fF
-C1288 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/out vssa1 1.20fF
-C1289 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/Q vssa1 -4.73fF
-C1290 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/nQ vssa1 0.48fF
-C1291 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/Q vssa1 -2.94fF
-C1292 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1293 io_analog[4] vssa1 -253.69fF
-C1294 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C1295 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C1296 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1297 io_analog[6] vssa1 -26.69fF
-C1298 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1299 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C1300 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1301 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/D vssa1 0.79fF
-C1302 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C1303 vdda1 vssa1 7275.97fF
-C1304 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/nQ vssa1 0.48fF
-C1305 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/Q vssa1 -1.08fF
-C1306 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1307 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C1308 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C1309 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1310 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1311 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C1312 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1313 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/D vssa1 -0.38fF
-C1314 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C1315 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/nQ vssa1 0.48fF
-C1316 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1317 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C1318 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C1319 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1320 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1321 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C1322 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1323 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/D vssa1 -1.04fF
-C1324 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C1325 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/nQ vssa1 0.48fF
-C1326 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1327 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1328 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1329 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1330 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1331 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1332 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1333 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C0 vdda1 bias_0/iref_1 15.26fF
+C1 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out 0.38fF
+C2 vdda1 gpio_noesd[9] 65.72fF
+C3 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# 0.45fF
+C4 bias_0/iref_2 top_pll_v1_0/nDown 0.70fF
+C5 vdda1 top_pll_v1_0/biasp 0.03fF
+C6 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C7 io_analog[3] bias_0/iref_7 13.88fF
+C8 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outp 0.61fF
+C9 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.72fF
+C10 top_pll_v3_0/out_to_div gpio_noesd[7] 4.28fF
+C11 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.01fF
+C12 io_analog[3] bias_0/iref_9 13.88fF
+C13 vdda1 gpio_noesd[3] 120.88fF
+C14 io_analog[2] bias_0/iref_5 13.88fF
+C15 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.46fF
+C16 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outp -0.31fF
+C17 io_analog[3] bias_0/iref_8 13.88fF
+C18 gpio_noesd[7] top_pll_v2_0/vco_vctrl 0.05fF
+C19 vdda1 top_pll_v2_0/buffer_salida_0/a_3996_n100# 0.05fF
+C20 bias_0/iref_7 bias_0/iref_8 13.23fF
+C21 vdda1 io_analog[3] 25.90fF
+C22 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/clk 0.37fF
+C23 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA gpio_noesd[1] 0.29fF
+C24 vdda1 top_pll_v1_0/pswitch 0.38fF
+C25 vdda1 bias_0/iref_2 3.90fF
+C26 gpio_noesd[8] gpio_noesd[7] 5.92fF
+C27 vdda1 top_pll_v3_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.12fF
+C28 gpio_noesd[10] gpio_noesd[9] 0.96fF
+C29 vdda1 bias_0/iref_7 33.08fF
+C30 bias_0/iref_9 bias_0/iref_8 9.89fF
+C31 io_analog[10] gpio_noesd[7] 29.88fF
+C32 top_pll_v1_0/vco_vctrl gpio_noesd[7] 0.05fF
+C33 bias_0/iref_8 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.34fF
+C34 top_pll_v3_0/lf_vc gpio_noesd[10] 0.48fF
+C35 vdda1 top_pll_v3_0/buffer_salida_0/a_678_n100# 0.50fF
+C36 io_analog[4] bias_0/iref_7 15.97fF
+C37 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[5] 0.68fF
+C38 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out 0.21fF
+C39 vdda1 bias_0/iref_9 30.24fF
+C40 top_pll_v3_0/buffer_salida_0/a_3996_n100# io_analog[7] -0.08fF
+C41 vdda1 top_pll_v1_0/buffer_salida_0/a_3996_n100# 0.06fF
+C42 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.04fF
+C43 gpio_noesd[9] gpio_noesd[11] 0.96fF
+C44 io_analog[4] bias_0/iref_9 15.97fF
+C45 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA 0.49fF
+C46 vdda1 top_pll_v3_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.12fF
+C47 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in -0.70fF
+C48 gpio_noesd[9] io_analog[10] 1.87fF
+C49 top_pll_v3_0/lf_vc gpio_noesd[8] 2.98fF
+C50 bias_0/iref_1 top_pll_v2_0/charge_pump_0/w_2544_775# 0.09fF
+C51 vdda1 bias_0/iref_8 31.37fF
+C52 gpio_noesd[9] top_pll_v3_0/out_div 0.16fF
+C53 top_pll_v3_0/s_1_n gpio_noesd[9] 0.08fF
+C54 io_analog[2] gpio_noesd[5] 0.09fF
+C55 io_analog[4] bias_0/iref_8 15.97fF
+C56 io_analog[6] bias_0/iref_1 13.22fF
+C57 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_7 0.37fF
+C58 bias_0/iref_2 top_pll_v1_0/Down 1.11fF
+C59 bias_0/iref_0 top_pll_v3_0/charge_pump_0/w_1008_774# 0.21fF
+C60 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.17fF
+C61 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.04fF
+C62 vdda1 io_analog[4] 182.26fF
+C63 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out gpio_noesd[2] 0.21fF
+C64 res_amp_top_0/res_amp_lin_prog_0/outn gpio_noesd[5] 1.42fF
+C65 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in gpio_noesd[4] 0.12fF
+C66 top_pll_v3_0/clk_1 gpio_noesd[10] 0.49fF
+C67 gpio_noesd[10] top_pll_v3_0/freq_div_0/prescaler_23_0/nCLK_23 1.35fF
+C68 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.04fF
+C69 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA gpio_noesd[4] 0.42fF
+C70 bias_0/iref_0 top_pll_v3_0/Down 1.08fF
+C71 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_6 0.15fF
+C72 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.78fF
+C73 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.21fF
+C74 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_8 0.37fF
+C75 io_analog[3] bias_0/iref_6 13.88fF
+C76 io_analog[5] io_clamp_low[1] 0.53fF
+C77 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp gpio_noesd[5] 0.54fF
+C78 gpio_noesd[11] top_pll_v3_0/freq_div_0/prescaler_23_0/nCLK_23 0.17fF
+C79 bias_0/iref_7 bias_0/iref_6 17.40fF
+C80 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in 0.23fF
+C81 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA gpio_noesd[3] 0.01fF
+C82 io_analog[7] bias_0/iref_1 13.22fF
+C83 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl gpio_noesd[5] 0.33fF
+C84 bias_0/iref_1 top_pll_v2_0/nUp 0.22fF
+C85 top_pll_v3_0/vco_vctrl gpio_noesd[10] 0.53fF
+C86 io_analog[6] bias_0/iref_2 54.67fF
+C87 vdda1 gpio_noesd[10] 53.94fF
+C88 vdda1 top_pll_v3_0/ring_osc_0/csvco_branch_2/vbp 1.07fF
+C89 io_analog[10] top_pll_v1_0/QA 0.03fF
+C90 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[4] -0.01fF
+C91 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# gpio_noesd[5] 0.16fF
+C92 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.94fF
+C93 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[5] 0.26fF
+C94 vdda1 top_pll_v2_0/vco_vctrl 0.59fF
+C95 io_analog[4] io_clamp_high[0] 0.53fF
+C96 io_analog[6] io_clamp_low[2] 0.53fF
+C97 vdda1 gpio_noesd[11] 102.31fF
+C98 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in 0.20fF
+C99 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outn 0.45fF
+C100 gpio_noesd[10] top_pll_v3_0/clk_0 0.12fF
+C101 bias_0/iref_2 io_analog[8] 14.44fF
+C102 vdda1 gpio_noesd[8] 77.43fF
+C103 vdda1 bias_0/iref_6 29.75fF
+C104 gpio_noesd[6] gpio_noesd[5] 0.05fF
+C105 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_5 0.45fF
+C106 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[3] 0.21fF
+C107 vdda1 io_analog[10] 0.01fF
+C108 gpio_noesd[10] top_pll_v3_0/out_by_2 0.10fF
+C109 vdda1 top_pll_v1_0/vco_vctrl 0.43fF
+C110 bias_0/iref_1 top_pll_v2_0/nDown 0.54fF
+C111 io_analog[3] bias_0/iref_5 13.88fF
+C112 gpio_noesd[4] io_analog[2] -0.21fF
+C113 io_analog[4] bias_0/iref_6 15.97fF
+C114 bias_0/iref_2 top_pll_v1_0/charge_pump_0/w_2544_775# 0.02fF
+C115 bias_0/iref_7 bias_0/iref_5 10.35fF
+C116 res_amp_top_0/res_amp_sync_v2_0/rst bias_0/iref_9 0.39fF
+C117 vdda1 io_analog[6] 124.15fF
+C118 io_analog[7] bias_0/iref_2 13.22fF
+C119 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outn -1.06fF
+C120 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[5] 0.14fF
+C121 io_analog[4] io_analog[6] 0.59fF
+C122 bias_0/iref_2 io_analog[9] 14.44fF
+C123 gpio_noesd[4] gpio_noesd[5] 4.67fF
+C124 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in bias_0/iref_5 0.46fF
+C125 vdda1 gpio_noesd[1] 214.54fF
+C126 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.22fF
+C127 vdda1 bias_0/iref_0 15.18fF
+C128 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out gpio_noesd[4] 0.19fF
+C129 vdda1 io_analog[8] 29.93fF
+C130 bias_0/iref_1 top_pll_v2_0/Up 0.54fF
+C131 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp 0.17fF
+C132 bias_0/iref_8 bias_0/iref_5 10.19fF
+C133 gpio_noesd[10] gpio_noesd[11] 39.51fF
+C134 vdda1 top_pll_v2_0/pswitch 0.34fF
+C135 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out gpio_noesd[1] 0.57fF
+C136 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp 2.10fF
+C137 bias_0/iref_0 top_pll_v3_0/nDown 0.74fF
+C138 vdda1 bias_0/iref_5 30.67fF
+C139 gpio_noesd[8] top_pll_v3_0/loop_filter_v2_0/cap3_loop_filter_0/in 3.13fF
+C140 gpio_noesd[10] io_analog[10] 1.87fF
+C141 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.07fF
+C142 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out gpio_noesd[3] 0.33fF
+C143 io_analog[2] io_analog[3] 0.14fF
+C144 vdda1 io_analog[7] 29.48fF
+C145 io_analog[4] bias_0/iref_5 15.97fF
+C146 vdda1 top_pll_v2_0/nUp 0.01fF
+C147 io_analog[2] bias_0/iref_7 13.88fF
+C148 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in 0.18fF
+C149 io_analog[6] gpio_noesd[10] 25.05fF
+C150 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b 0.31fF
+C151 vdda1 io_analog[9] 30.05fF
+C152 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[4] -0.05fF
+C153 bias_0/iref_1 top_pll_v2_0/biasp 2.20fF
+C154 gpio_noesd[11] io_analog[10] 1.87fF
+C155 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.17fF
+C156 io_analog[2] bias_0/iref_9 13.88fF
+C157 io_analog[3] gpio_noesd[5] 0.12fF
+C158 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp 1.01fF
+C159 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[3] 0.03fF
+C160 gpio_noesd[8] io_analog[10] 20.65fF
+C161 bias_0/iref_5 io_analog[5] 0.09fF
+C162 vdda1 top_pll_v3_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.12fF
+C163 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C164 io_analog[6] gpio_noesd[11] 9.16fF
+C165 top_pll_v1_0/out_to_div gpio_noesd[7] 0.23fF
+C166 vdda1 io_analog[1] 76.56fF
+C167 io_analog[2] bias_0/iref_8 13.88fF
+C168 bias_0/iref_9 gpio_noesd[5] 1.30fF
+C169 gpio_noesd[10] top_pll_v3_0/n_clk_0 0.10fF
+C170 vdda1 io_analog[2] 25.90fF
+C171 bias_0/iref_0 top_pll_v3_0/charge_pump_0/w_2544_775# 0.21fF
+C172 vdda1 gpio_noesd[2] 214.16fF
+C173 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[4] -0.08fF
+C174 top_pll_v3_0/biasp bias_0/iref_0 3.13fF
+C175 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.17fF
+C176 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# 0.18fF
+C177 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b 0.23fF
+C178 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# bias_0/iref_7 0.09fF
+C179 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB gpio_noesd[5] 0.14fF
+C180 bias_0/iref_2 top_pll_v1_0/Up 0.70fF
+C181 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[5] 0.44fF
+C182 vdda1 gpio_noesd[5] 124.75fF
+C183 io_analog[6] bias_0/iref_0 6.93fF
+C184 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.42fF
+C185 bias_0/iref_5 bias_0/iref_6 29.11fF
+C186 bias_0/iref_1 top_pll_v2_0/Down 0.91fF
+C187 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_7 0.40fF
+C188 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C189 vdda1 top_pll_v3_0/buffer_salida_0/a_3996_n100# 1.78fF
+C190 gpio_noesd[10] top_pll_v3_0/s_0_n 0.31fF
+C191 gpio_noesd[7] top_pll_v2_0/out_to_div 0.23fF
+C192 bias_0/iref_0 top_pll_v3_0/Up 0.74fF
+C193 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in bias_0/iref_5 0.46fF
+C194 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in gpio_noesd[5] 0.47fF
+C195 io_analog[5] io_clamp_high[1] 0.53fF
+C196 res_amp_top_0/res_amp_lin_prog_0/outp gpio_noesd[5] 0.44fF
+C197 bias_0/iref_2 top_pll_v1_0/nUp 0.70fF
+C198 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_8 0.11fF
+C199 gpio_noesd[4] io_analog[3] -0.78fF
+C200 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB 0.19fF
+C201 vdda1 top_pll_v2_0/biasp 0.03fF
+C202 io_analog[4] io_clamp_low[0] 0.53fF
+C203 vdda1 io_analog[0] 76.77fF
+C204 gpio_noesd[9] top_pll_v3_0/clk_d 0.15fF
+C205 bias_0/iref_2 top_pll_v1_0/biasp 3.20fF
+C206 gpio_noesd[5] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.32fF
+C207 gpio_noesd[4] bias_0/iref_9 -0.25fF
+C208 io_analog[2] bias_0/iref_6 13.88fF
+C209 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/clk 0.39fF
+C210 bias_0/iref_0 top_pll_v3_0/nUp 0.74fF
+C211 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk 2.12fF
+C212 vdda1 gpio_noesd[6] 53.94fF
+C213 top_pll_v3_0/vco_vctrl gpio_noesd[7] 0.13fF
+C214 vdda1 gpio_noesd[7] 120.96fF
+C215 io_analog[6] io_clamp_high[2] 0.53fF
+C216 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# -0.11fF
+C217 vdda1 top_pll_v1_0/nUp 0.01fF
+C218 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB gpio_noesd[4] 0.08fF
+C219 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[4] -0.13fF
+C220 vdda1 gpio_noesd[4] 117.64fF
+C221 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in gpio_noesd[5] 0.05fF
+C222 gpio_noesd[1] gpio_noesd[2] 0.30fF
+C223 io_in_3v3[0] vssa1 0.41fF
+C224 io_oeb[26] vssa1 0.61fF
+C225 io_in[0] vssa1 0.41fF
+C226 io_out[26] vssa1 0.61fF
+C227 io_out[0] vssa1 0.41fF
+C228 io_in[26] vssa1 0.61fF
+C229 io_oeb[0] vssa1 0.41fF
+C230 io_in_3v3[26] vssa1 0.61fF
+C231 io_in_3v3[1] vssa1 0.41fF
+C232 io_oeb[25] vssa1 0.61fF
+C233 io_in[1] vssa1 0.41fF
+C234 io_out[25] vssa1 0.61fF
+C235 io_out[1] vssa1 0.41fF
+C236 io_in[25] vssa1 0.61fF
+C237 io_oeb[1] vssa1 0.41fF
+C238 io_in_3v3[25] vssa1 0.61fF
+C239 io_in_3v3[2] vssa1 0.41fF
+C240 io_oeb[24] vssa1 0.61fF
+C241 io_in[2] vssa1 0.41fF
+C242 io_out[24] vssa1 0.61fF
+C243 io_out[2] vssa1 0.41fF
+C244 io_in[24] vssa1 0.61fF
+C245 io_oeb[2] vssa1 -0.20fF
+C246 io_in_3v3[3] vssa1 0.41fF
+C247 gpio_noesd[17] vssa1 0.61fF
+C248 io_in[3] vssa1 0.41fF
+C249 gpio_analog[17] vssa1 0.61fF
+C250 io_out[3] vssa1 0.41fF
+C251 io_oeb[3] vssa1 0.41fF
+C252 io_in_3v3[4] vssa1 0.41fF
+C253 io_in[4] vssa1 0.41fF
+C254 io_out[4] vssa1 0.41fF
+C255 io_oeb[4] vssa1 0.41fF
+C256 io_oeb[23] vssa1 0.61fF
+C257 io_out[23] vssa1 0.61fF
+C258 io_in[23] vssa1 0.61fF
+C259 io_in_3v3[23] vssa1 0.61fF
+C260 gpio_noesd[16] vssa1 0.61fF
+C261 io_in_3v3[5] vssa1 0.41fF
+C262 io_in[5] vssa1 -0.20fF
+C263 io_out[5] vssa1 0.41fF
+C264 io_oeb[5] vssa1 0.41fF
+C265 io_oeb[22] vssa1 0.61fF
+C266 io_out[22] vssa1 0.61fF
+C267 io_in[22] vssa1 0.61fF
+C268 io_in_3v3[22] vssa1 0.61fF
+C269 gpio_analog[15] vssa1 0.61fF
+C270 io_in_3v3[6] vssa1 -0.20fF
+C271 io_in[6] vssa1 0.41fF
+C272 io_out[6] vssa1 0.41fF
+C273 io_oeb[6] vssa1 0.41fF
+C274 io_oeb[21] vssa1 0.61fF
+C275 io_out[21] vssa1 0.61fF
+C276 io_in[21] vssa1 0.61fF
+C277 io_in_3v3[21] vssa1 0.61fF
+C278 gpio_noesd[14] vssa1 0.61fF
+C279 gpio_analog[14] vssa1 0.61fF
+C280 vssd2 vssa1 -5.19fF
+C281 vssd1 vssa1 1.13fF
+C282 vdda2 vssa1 -5.19fF
+C283 io_oeb[20] vssa1 0.61fF
+C284 io_out[20] vssa1 0.61fF
+C285 io_in[20] vssa1 0.61fF
+C286 io_in_3v3[20] vssa1 0.61fF
+C287 gpio_noesd[13] vssa1 0.61fF
+C288 gpio_analog[13] vssa1 0.61fF
+C289 gpio_analog[0] vssa1 0.41fF
+C290 gpio_noesd[0] vssa1 0.41fF
+C291 io_in_3v3[7] vssa1 0.41fF
+C292 io_in[7] vssa1 0.41fF
+C293 io_out[7] vssa1 0.41fF
+C294 io_oeb[7] vssa1 0.41fF
+C295 io_oeb[19] vssa1 0.61fF
+C296 io_out[19] vssa1 0.61fF
+C297 io_in[19] vssa1 0.61fF
+C298 io_in_3v3[19] vssa1 0.61fF
+C299 gpio_noesd[12] vssa1 0.61fF
+C300 gpio_analog[12] vssa1 0.61fF
+C301 gpio_analog[1] vssa1 0.41fF
+C302 io_in_3v3[8] vssa1 0.41fF
+C303 io_in[8] vssa1 0.41fF
+C304 io_out[8] vssa1 -0.20fF
+C305 io_oeb[8] vssa1 0.41fF
+C306 gpio_analog[2] vssa1 0.41fF
+C307 io_in_3v3[9] vssa1 0.41fF
+C308 io_in[9] vssa1 0.41fF
+C309 io_out[9] vssa1 0.41fF
+C310 io_oeb[9] vssa1 0.41fF
+C311 gpio_analog[3] vssa1 0.41fF
+C312 io_in_3v3[10] vssa1 0.41fF
+C313 io_in[10] vssa1 0.41fF
+C314 io_out[10] vssa1 0.41fF
+C315 io_oeb[10] vssa1 0.41fF
+C316 gpio_analog[4] vssa1 0.41fF
+C317 io_in_3v3[11] vssa1 0.41fF
+C318 io_in[11] vssa1 0.41fF
+C319 io_out[11] vssa1 0.41fF
+C320 io_oeb[11] vssa1 0.41fF
+C321 gpio_analog[5] vssa1 0.41fF
+C322 io_in_3v3[12] vssa1 0.41fF
+C323 io_in[12] vssa1 0.41fF
+C324 io_out[12] vssa1 0.41fF
+C325 io_oeb[12] vssa1 0.41fF
+C326 gpio_analog[6] vssa1 0.60fF
+C327 io_in_3v3[13] vssa1 0.60fF
+C328 io_in[13] vssa1 0.60fF
+C329 io_out[13] vssa1 0.60fF
+C330 io_oeb[13] vssa1 0.60fF
+C331 io_oeb[18] vssa1 0.61fF
+C332 io_out[18] vssa1 0.61fF
+C333 io_in_3v3[18] vssa1 0.61fF
+C334 vccd1 vssa1 0.85fF
+C335 gpio_analog[11] vssa1 0.61fF
+C336 io_oeb[17] vssa1 0.61fF
+C337 io_in[17] vssa1 0.61fF
+C338 io_in_3v3[17] vssa1 0.61fF
+C339 gpio_analog[10] vssa1 0.61fF
+C340 io_out[16] vssa1 0.61fF
+C341 io_in[16] vssa1 0.61fF
+C342 io_in_3v3[16] vssa1 0.61fF
+C343 gpio_analog[9] vssa1 0.61fF
+C344 io_oeb[15] vssa1 0.61fF
+C345 io_out[15] vssa1 0.61fF
+C346 io_in[15] vssa1 0.61fF
+C347 io_in_3v3[15] vssa1 0.61fF
+C348 gpio_analog[8] vssa1 0.61fF
+C349 io_oeb[14] vssa1 0.61fF
+C350 io_out[14] vssa1 0.61fF
+C351 io_in[14] vssa1 0.61fF
+C352 io_in_3v3[14] vssa1 0.61fF
+C353 vssa2 vssa1 1.66fF
+C354 vccd2 vssa1 0.91fF
+C355 io_clamp_high[0] vssa1 -2.60fF
+C356 io_clamp_low[0] vssa1 0.82fF
+C357 io_clamp_high[1] vssa1 0.71fF
+C358 io_clamp_low[1] vssa1 0.55fF
+C359 io_clamp_high[2] vssa1 0.66fF
+C360 io_clamp_low[2] vssa1 0.50fF
+C361 user_irq[2] vssa1 0.63fF
+C362 user_irq[1] vssa1 0.63fF
+C363 user_irq[0] vssa1 0.63fF
+C364 user_clock2 vssa1 0.63fF
+C365 la_oenb[127] vssa1 0.63fF
+C366 la_data_in[127] vssa1 0.63fF
+C367 la_oenb[126] vssa1 0.63fF
+C368 la_data_out[126] vssa1 0.63fF
+C369 la_data_in[126] vssa1 0.63fF
+C370 la_oenb[125] vssa1 0.63fF
+C371 la_data_out[125] vssa1 0.63fF
+C372 la_data_in[125] vssa1 0.63fF
+C373 la_oenb[124] vssa1 0.63fF
+C374 la_data_out[124] vssa1 0.63fF
+C375 la_data_in[124] vssa1 0.63fF
+C376 la_oenb[123] vssa1 0.63fF
+C377 la_data_out[123] vssa1 0.63fF
+C378 la_oenb[122] vssa1 0.63fF
+C379 la_data_out[122] vssa1 0.63fF
+C380 la_data_in[122] vssa1 0.63fF
+C381 la_oenb[121] vssa1 0.63fF
+C382 la_data_out[121] vssa1 0.63fF
+C383 la_data_in[121] vssa1 0.63fF
+C384 la_oenb[120] vssa1 0.63fF
+C385 la_data_out[120] vssa1 0.63fF
+C386 la_data_in[120] vssa1 0.63fF
+C387 la_oenb[119] vssa1 0.63fF
+C388 la_data_out[119] vssa1 0.63fF
+C389 la_data_in[119] vssa1 0.63fF
+C390 la_oenb[118] vssa1 0.63fF
+C391 la_data_out[118] vssa1 0.63fF
+C392 la_data_in[118] vssa1 0.63fF
+C393 la_oenb[117] vssa1 0.63fF
+C394 la_data_out[117] vssa1 0.63fF
+C395 la_data_in[117] vssa1 0.63fF
+C396 la_data_out[116] vssa1 0.63fF
+C397 la_data_in[116] vssa1 0.63fF
+C398 la_oenb[115] vssa1 0.63fF
+C399 la_data_out[115] vssa1 0.63fF
+C400 la_data_in[115] vssa1 0.63fF
+C401 la_oenb[114] vssa1 0.63fF
+C402 la_data_out[114] vssa1 0.63fF
+C403 la_data_in[114] vssa1 0.63fF
+C404 la_oenb[113] vssa1 0.63fF
+C405 la_data_out[113] vssa1 0.63fF
+C406 la_data_in[113] vssa1 0.63fF
+C407 la_oenb[112] vssa1 0.63fF
+C408 la_data_in[112] vssa1 0.63fF
+C409 la_oenb[111] vssa1 0.63fF
+C410 la_data_out[111] vssa1 0.63fF
+C411 la_data_in[111] vssa1 0.63fF
+C412 la_oenb[110] vssa1 0.63fF
+C413 la_data_out[110] vssa1 0.63fF
+C414 la_data_in[110] vssa1 0.63fF
+C415 la_oenb[109] vssa1 0.63fF
+C416 la_data_out[109] vssa1 0.63fF
+C417 la_data_in[109] vssa1 0.63fF
+C418 la_oenb[108] vssa1 0.63fF
+C419 la_data_out[108] vssa1 0.63fF
+C420 la_oenb[107] vssa1 0.63fF
+C421 la_data_out[107] vssa1 0.63fF
+C422 la_data_in[107] vssa1 0.63fF
+C423 la_oenb[106] vssa1 0.63fF
+C424 la_data_out[106] vssa1 0.63fF
+C425 la_oenb[105] vssa1 0.63fF
+C426 la_data_out[105] vssa1 0.63fF
+C427 la_data_in[105] vssa1 0.63fF
+C428 la_oenb[104] vssa1 0.63fF
+C429 la_data_out[104] vssa1 0.63fF
+C430 la_data_in[104] vssa1 0.63fF
+C431 la_oenb[103] vssa1 0.63fF
+C432 la_data_out[103] vssa1 0.63fF
+C433 la_data_in[103] vssa1 0.63fF
+C434 la_oenb[102] vssa1 0.63fF
+C435 la_data_out[102] vssa1 0.63fF
+C436 la_data_in[102] vssa1 0.63fF
+C437 la_data_out[101] vssa1 0.63fF
+C438 la_data_in[101] vssa1 0.63fF
+C439 la_oenb[100] vssa1 0.63fF
+C440 la_data_out[100] vssa1 0.63fF
+C441 la_data_in[100] vssa1 0.63fF
+C442 la_oenb[99] vssa1 0.63fF
+C443 la_data_out[99] vssa1 0.63fF
+C444 la_data_in[99] vssa1 0.63fF
+C445 la_oenb[98] vssa1 0.63fF
+C446 la_data_out[98] vssa1 0.63fF
+C447 la_data_in[98] vssa1 0.63fF
+C448 la_oenb[97] vssa1 0.63fF
+C449 la_data_in[97] vssa1 0.63fF
+C450 la_oenb[96] vssa1 0.63fF
+C451 la_data_out[96] vssa1 0.63fF
+C452 la_data_in[96] vssa1 0.63fF
+C453 la_oenb[95] vssa1 0.63fF
+C454 la_data_out[95] vssa1 0.63fF
+C455 la_data_in[95] vssa1 0.63fF
+C456 la_oenb[94] vssa1 0.63fF
+C457 la_data_out[94] vssa1 0.63fF
+C458 la_data_in[94] vssa1 0.63fF
+C459 la_oenb[93] vssa1 0.63fF
+C460 la_data_out[93] vssa1 0.63fF
+C461 la_oenb[92] vssa1 0.63fF
+C462 la_data_out[92] vssa1 0.63fF
+C463 la_data_in[92] vssa1 0.63fF
+C464 la_oenb[91] vssa1 0.63fF
+C465 la_data_out[91] vssa1 0.63fF
+C466 la_oenb[90] vssa1 0.63fF
+C467 la_data_out[90] vssa1 0.63fF
+C468 la_data_in[90] vssa1 0.63fF
+C469 la_oenb[89] vssa1 0.63fF
+C470 la_data_out[89] vssa1 0.63fF
+C471 la_data_in[89] vssa1 0.63fF
+C472 la_oenb[88] vssa1 0.63fF
+C473 la_data_out[88] vssa1 0.63fF
+C474 la_data_in[88] vssa1 0.63fF
+C475 la_oenb[87] vssa1 0.63fF
+C476 la_data_out[87] vssa1 0.63fF
+C477 la_data_in[87] vssa1 0.63fF
+C478 la_data_out[86] vssa1 0.63fF
+C479 la_data_in[86] vssa1 0.63fF
+C480 la_oenb[85] vssa1 0.63fF
+C481 la_data_out[85] vssa1 0.63fF
+C482 la_data_in[85] vssa1 0.63fF
+C483 la_oenb[84] vssa1 0.63fF
+C484 la_data_out[84] vssa1 0.63fF
+C485 la_data_in[84] vssa1 0.63fF
+C486 la_oenb[83] vssa1 0.63fF
+C487 la_data_out[83] vssa1 0.63fF
+C488 la_data_in[83] vssa1 0.63fF
+C489 la_oenb[82] vssa1 0.63fF
+C490 la_data_in[82] vssa1 0.63fF
+C491 la_oenb[81] vssa1 0.63fF
+C492 la_data_out[81] vssa1 0.63fF
+C493 la_data_in[81] vssa1 0.63fF
+C494 la_oenb[80] vssa1 0.63fF
+C495 la_data_out[80] vssa1 0.63fF
+C496 la_data_in[80] vssa1 0.63fF
+C497 la_oenb[79] vssa1 0.63fF
+C498 la_data_out[79] vssa1 0.63fF
+C499 la_data_in[79] vssa1 0.63fF
+C500 la_oenb[78] vssa1 0.63fF
+C501 la_data_out[78] vssa1 0.63fF
+C502 la_data_in[78] vssa1 0.63fF
+C503 la_oenb[77] vssa1 0.63fF
+C504 la_data_out[77] vssa1 0.63fF
+C505 la_data_in[77] vssa1 0.63fF
+C506 la_oenb[76] vssa1 0.63fF
+C507 la_data_out[76] vssa1 0.63fF
+C508 la_oenb[75] vssa1 0.63fF
+C509 la_data_out[75] vssa1 0.63fF
+C510 la_data_in[75] vssa1 0.63fF
+C511 la_oenb[74] vssa1 0.63fF
+C512 la_data_out[74] vssa1 0.63fF
+C513 la_data_in[74] vssa1 0.63fF
+C514 la_oenb[73] vssa1 0.63fF
+C515 la_data_out[73] vssa1 0.63fF
+C516 la_data_in[73] vssa1 0.63fF
+C517 la_oenb[72] vssa1 0.63fF
+C518 la_data_out[72] vssa1 0.63fF
+C519 la_data_in[72] vssa1 0.63fF
+C520 la_data_out[71] vssa1 0.63fF
+C521 la_data_in[71] vssa1 0.63fF
+C522 la_oenb[70] vssa1 0.63fF
+C523 la_data_out[70] vssa1 0.63fF
+C524 la_data_in[70] vssa1 0.63fF
+C525 la_oenb[69] vssa1 0.63fF
+C526 la_data_out[69] vssa1 0.63fF
+C527 la_data_in[69] vssa1 0.63fF
+C528 la_oenb[68] vssa1 0.63fF
+C529 la_data_out[68] vssa1 0.63fF
+C530 la_data_in[68] vssa1 0.63fF
+C531 la_oenb[67] vssa1 0.63fF
+C532 la_data_in[67] vssa1 0.63fF
+C533 la_oenb[66] vssa1 0.63fF
+C534 la_data_out[66] vssa1 0.63fF
+C535 la_data_in[66] vssa1 0.63fF
+C536 la_oenb[65] vssa1 0.63fF
+C537 la_data_out[65] vssa1 0.26fF
+C538 la_data_in[65] vssa1 0.63fF
+C539 la_oenb[64] vssa1 0.63fF
+C540 la_data_out[64] vssa1 0.63fF
+C541 la_data_in[64] vssa1 0.63fF
+C542 la_oenb[63] vssa1 0.63fF
+C543 la_data_out[63] vssa1 0.63fF
+C544 la_data_in[63] vssa1 0.63fF
+C545 la_oenb[62] vssa1 0.63fF
+C546 la_data_out[62] vssa1 0.63fF
+C547 la_data_in[62] vssa1 0.63fF
+C548 la_oenb[61] vssa1 0.63fF
+C549 la_data_out[61] vssa1 0.63fF
+C550 la_oenb[60] vssa1 0.63fF
+C551 la_data_out[60] vssa1 0.63fF
+C552 la_data_in[60] vssa1 0.63fF
+C553 la_oenb[59] vssa1 0.63fF
+C554 la_data_out[59] vssa1 0.63fF
+C555 la_data_in[59] vssa1 0.63fF
+C556 la_oenb[58] vssa1 0.63fF
+C557 la_data_out[58] vssa1 0.63fF
+C558 la_data_in[58] vssa1 0.63fF
+C559 la_oenb[57] vssa1 0.63fF
+C560 la_data_out[57] vssa1 0.63fF
+C561 la_data_in[57] vssa1 0.63fF
+C562 la_data_out[56] vssa1 0.63fF
+C563 la_data_in[56] vssa1 0.63fF
+C564 la_oenb[55] vssa1 0.63fF
+C565 la_data_out[55] vssa1 0.63fF
+C566 la_data_in[55] vssa1 0.63fF
+C567 la_oenb[54] vssa1 0.63fF
+C568 la_data_out[54] vssa1 0.63fF
+C569 la_data_in[54] vssa1 0.63fF
+C570 la_oenb[53] vssa1 0.63fF
+C571 la_data_out[53] vssa1 0.63fF
+C572 la_data_in[53] vssa1 0.63fF
+C573 la_oenb[52] vssa1 0.63fF
+C574 la_data_in[52] vssa1 0.63fF
+C575 la_oenb[51] vssa1 0.63fF
+C576 la_data_out[51] vssa1 0.63fF
+C577 la_data_in[51] vssa1 0.63fF
+C578 la_oenb[50] vssa1 0.63fF
+C579 la_data_in[50] vssa1 0.63fF
+C580 la_oenb[49] vssa1 0.63fF
+C581 la_data_out[49] vssa1 0.63fF
+C582 la_data_in[49] vssa1 0.63fF
+C583 la_oenb[48] vssa1 0.63fF
+C584 la_data_out[48] vssa1 0.63fF
+C585 la_data_in[48] vssa1 0.63fF
+C586 la_oenb[47] vssa1 0.63fF
+C587 la_data_out[47] vssa1 0.63fF
+C588 la_data_in[47] vssa1 0.63fF
+C589 la_oenb[46] vssa1 0.63fF
+C590 la_data_out[46] vssa1 0.63fF
+C591 la_oenb[45] vssa1 0.63fF
+C592 la_data_out[45] vssa1 0.63fF
+C593 la_data_in[45] vssa1 0.63fF
+C594 la_oenb[44] vssa1 0.63fF
+C595 la_data_out[44] vssa1 0.63fF
+C596 la_data_in[44] vssa1 0.63fF
+C597 la_oenb[43] vssa1 0.63fF
+C598 la_data_out[43] vssa1 0.63fF
+C599 la_data_in[43] vssa1 0.63fF
+C600 la_oenb[42] vssa1 0.63fF
+C601 la_data_out[42] vssa1 0.63fF
+C602 la_data_in[42] vssa1 0.63fF
+C603 la_data_out[41] vssa1 0.63fF
+C604 la_data_in[41] vssa1 0.63fF
+C605 la_oenb[40] vssa1 0.63fF
+C606 la_data_out[40] vssa1 0.63fF
+C607 la_data_in[40] vssa1 0.63fF
+C608 la_oenb[39] vssa1 0.63fF
+C609 la_data_out[39] vssa1 0.63fF
+C610 la_data_in[39] vssa1 0.63fF
+C611 la_oenb[38] vssa1 0.63fF
+C612 la_data_out[38] vssa1 0.63fF
+C613 la_data_in[38] vssa1 0.63fF
+C614 la_oenb[37] vssa1 0.63fF
+C615 la_data_out[37] vssa1 0.26fF
+C616 la_data_in[37] vssa1 0.63fF
+C617 la_oenb[36] vssa1 0.63fF
+C618 la_data_out[36] vssa1 0.63fF
+C619 la_data_in[36] vssa1 0.63fF
+C620 la_oenb[35] vssa1 0.63fF
+C621 la_data_in[35] vssa1 0.63fF
+C622 la_oenb[34] vssa1 0.63fF
+C623 la_data_out[34] vssa1 0.63fF
+C624 la_data_in[34] vssa1 0.63fF
+C625 la_oenb[33] vssa1 0.63fF
+C626 la_data_out[33] vssa1 0.63fF
+C627 la_data_in[33] vssa1 0.63fF
+C628 la_oenb[32] vssa1 0.63fF
+C629 la_data_out[32] vssa1 0.63fF
+C630 la_data_in[32] vssa1 0.63fF
+C631 la_oenb[31] vssa1 0.63fF
+C632 la_data_out[31] vssa1 0.63fF
+C633 la_oenb[30] vssa1 0.63fF
+C634 la_data_out[30] vssa1 0.63fF
+C635 la_data_in[30] vssa1 0.63fF
+C636 la_oenb[29] vssa1 0.63fF
+C637 la_data_out[29] vssa1 0.63fF
+C638 la_data_in[29] vssa1 0.63fF
+C639 la_oenb[28] vssa1 0.63fF
+C640 la_data_out[28] vssa1 0.63fF
+C641 la_data_in[28] vssa1 0.63fF
+C642 la_oenb[27] vssa1 0.63fF
+C643 la_data_out[27] vssa1 0.63fF
+C644 la_data_in[27] vssa1 0.63fF
+C645 la_data_out[26] vssa1 0.63fF
+C646 la_data_in[26] vssa1 0.63fF
+C647 la_oenb[25] vssa1 0.63fF
+C648 la_data_out[25] vssa1 0.63fF
+C649 la_data_in[25] vssa1 0.63fF
+C650 la_oenb[24] vssa1 0.63fF
+C651 la_data_out[24] vssa1 0.63fF
+C652 la_data_in[24] vssa1 0.63fF
+C653 la_oenb[23] vssa1 0.63fF
+C654 la_data_out[23] vssa1 0.63fF
+C655 la_data_in[23] vssa1 0.63fF
+C656 la_oenb[22] vssa1 0.63fF
+C657 la_data_out[22] vssa1 0.63fF
+C658 la_data_in[22] vssa1 0.63fF
+C659 la_oenb[21] vssa1 0.63fF
+C660 la_data_out[21] vssa1 0.63fF
+C661 la_data_in[21] vssa1 0.63fF
+C662 la_oenb[20] vssa1 0.63fF
+C663 la_data_in[20] vssa1 0.63fF
+C664 la_oenb[19] vssa1 0.63fF
+C665 la_data_out[19] vssa1 0.63fF
+C666 la_data_in[19] vssa1 0.63fF
+C667 la_oenb[18] vssa1 0.63fF
+C668 la_data_out[18] vssa1 0.63fF
+C669 la_data_in[18] vssa1 0.63fF
+C670 la_oenb[17] vssa1 0.63fF
+C671 la_data_out[17] vssa1 0.63fF
+C672 la_data_in[17] vssa1 0.63fF
+C673 la_oenb[16] vssa1 0.63fF
+C674 la_data_out[16] vssa1 0.63fF
+C675 la_oenb[15] vssa1 0.63fF
+C676 la_data_out[15] vssa1 0.63fF
+C677 la_data_in[15] vssa1 0.63fF
+C678 la_oenb[14] vssa1 0.63fF
+C679 la_data_out[14] vssa1 0.63fF
+C680 la_data_in[14] vssa1 0.63fF
+C681 la_oenb[13] vssa1 0.63fF
+C682 la_data_out[13] vssa1 0.63fF
+C683 la_data_in[13] vssa1 0.63fF
+C684 la_oenb[12] vssa1 0.63fF
+C685 la_data_out[12] vssa1 0.63fF
+C686 la_data_in[12] vssa1 0.63fF
+C687 la_data_out[11] vssa1 0.63fF
+C688 la_data_in[11] vssa1 0.63fF
+C689 la_oenb[10] vssa1 0.63fF
+C690 la_data_out[10] vssa1 0.63fF
+C691 la_data_in[10] vssa1 0.63fF
+C692 la_data_out[9] vssa1 0.63fF
+C693 la_data_in[9] vssa1 0.63fF
+C694 la_oenb[8] vssa1 0.63fF
+C695 la_data_out[8] vssa1 0.63fF
+C696 la_data_in[8] vssa1 0.63fF
+C697 la_oenb[7] vssa1 0.63fF
+C698 la_data_out[7] vssa1 0.63fF
+C699 la_data_in[7] vssa1 0.63fF
+C700 la_oenb[6] vssa1 0.63fF
+C701 la_data_out[6] vssa1 0.63fF
+C702 la_data_in[6] vssa1 0.63fF
+C703 la_oenb[5] vssa1 0.63fF
+C704 la_data_in[5] vssa1 0.63fF
+C705 la_oenb[4] vssa1 0.63fF
+C706 la_data_out[4] vssa1 0.63fF
+C707 la_data_in[4] vssa1 0.63fF
+C708 la_oenb[3] vssa1 0.63fF
+C709 la_data_out[3] vssa1 0.63fF
+C710 la_data_in[3] vssa1 0.63fF
+C711 la_oenb[2] vssa1 0.63fF
+C712 la_data_out[2] vssa1 0.63fF
+C713 la_data_in[2] vssa1 0.63fF
+C714 la_oenb[1] vssa1 0.63fF
+C715 la_data_out[1] vssa1 0.63fF
+C716 la_oenb[0] vssa1 0.63fF
+C717 la_data_out[0] vssa1 0.63fF
+C718 la_data_in[0] vssa1 0.63fF
+C719 wbs_dat_o[31] vssa1 0.63fF
+C720 wbs_dat_i[31] vssa1 0.63fF
+C721 wbs_adr_i[31] vssa1 0.63fF
+C722 wbs_dat_o[30] vssa1 0.63fF
+C723 wbs_dat_i[30] vssa1 0.63fF
+C724 wbs_adr_i[30] vssa1 0.63fF
+C725 wbs_dat_o[29] vssa1 0.63fF
+C726 wbs_dat_i[29] vssa1 0.63fF
+C727 wbs_adr_i[29] vssa1 0.63fF
+C728 wbs_dat_i[28] vssa1 0.63fF
+C729 wbs_adr_i[28] vssa1 0.63fF
+C730 wbs_dat_o[27] vssa1 0.63fF
+C731 wbs_dat_i[27] vssa1 0.63fF
+C732 wbs_adr_i[27] vssa1 0.63fF
+C733 wbs_dat_i[26] vssa1 0.63fF
+C734 wbs_adr_i[26] vssa1 0.63fF
+C735 wbs_dat_o[25] vssa1 0.63fF
+C736 wbs_dat_i[25] vssa1 0.63fF
+C737 wbs_adr_i[25] vssa1 0.63fF
+C738 wbs_dat_o[24] vssa1 0.63fF
+C739 wbs_dat_i[24] vssa1 0.63fF
+C740 wbs_adr_i[24] vssa1 0.63fF
+C741 wbs_dat_o[23] vssa1 0.63fF
+C742 wbs_dat_i[23] vssa1 0.63fF
+C743 wbs_adr_i[23] vssa1 0.63fF
+C744 wbs_dat_o[22] vssa1 0.63fF
+C745 wbs_adr_i[22] vssa1 0.63fF
+C746 wbs_dat_o[21] vssa1 0.63fF
+C747 wbs_dat_i[21] vssa1 0.63fF
+C748 wbs_adr_i[21] vssa1 0.63fF
+C749 wbs_dat_o[20] vssa1 0.63fF
+C750 wbs_dat_i[20] vssa1 0.63fF
+C751 wbs_adr_i[20] vssa1 0.63fF
+C752 wbs_dat_o[19] vssa1 0.63fF
+C753 wbs_dat_i[19] vssa1 0.63fF
+C754 wbs_adr_i[19] vssa1 0.63fF
+C755 wbs_dat_o[18] vssa1 0.63fF
+C756 wbs_dat_i[18] vssa1 0.63fF
+C757 wbs_dat_o[17] vssa1 0.63fF
+C758 wbs_dat_i[17] vssa1 0.63fF
+C759 wbs_adr_i[17] vssa1 0.63fF
+C760 wbs_dat_o[16] vssa1 0.63fF
+C761 wbs_dat_i[16] vssa1 0.63fF
+C762 wbs_adr_i[16] vssa1 0.63fF
+C763 wbs_dat_o[15] vssa1 0.63fF
+C764 wbs_dat_i[15] vssa1 0.63fF
+C765 wbs_adr_i[15] vssa1 0.63fF
+C766 wbs_dat_o[14] vssa1 0.63fF
+C767 wbs_dat_i[14] vssa1 0.63fF
+C768 wbs_adr_i[14] vssa1 0.63fF
+C769 wbs_dat_o[13] vssa1 0.63fF
+C770 wbs_dat_i[13] vssa1 0.63fF
+C771 wbs_adr_i[13] vssa1 0.63fF
+C772 wbs_dat_o[12] vssa1 0.63fF
+C773 wbs_dat_i[12] vssa1 0.63fF
+C774 wbs_adr_i[12] vssa1 0.63fF
+C775 wbs_dat_i[11] vssa1 0.63fF
+C776 wbs_adr_i[11] vssa1 0.63fF
+C777 wbs_dat_o[10] vssa1 0.63fF
+C778 wbs_dat_i[10] vssa1 0.63fF
+C779 wbs_adr_i[10] vssa1 0.63fF
+C780 wbs_dat_o[9] vssa1 0.63fF
+C781 wbs_dat_i[9] vssa1 0.63fF
+C782 wbs_adr_i[9] vssa1 0.63fF
+C783 wbs_dat_o[8] vssa1 0.63fF
+C784 wbs_dat_i[8] vssa1 0.63fF
+C785 wbs_adr_i[8] vssa1 0.63fF
+C786 wbs_dat_o[7] vssa1 0.63fF
+C787 wbs_adr_i[7] vssa1 0.63fF
+C788 wbs_dat_o[6] vssa1 0.63fF
+C789 wbs_dat_i[6] vssa1 0.63fF
+C790 wbs_adr_i[6] vssa1 0.63fF
+C791 wbs_dat_o[5] vssa1 0.63fF
+C792 wbs_dat_i[5] vssa1 0.63fF
+C793 wbs_adr_i[5] vssa1 0.63fF
+C794 wbs_dat_o[4] vssa1 0.63fF
+C795 wbs_dat_i[4] vssa1 0.63fF
+C796 wbs_adr_i[4] vssa1 0.63fF
+C797 wbs_sel_i[3] vssa1 0.63fF
+C798 wbs_dat_o[3] vssa1 0.63fF
+C799 wbs_adr_i[3] vssa1 0.63fF
+C800 wbs_sel_i[2] vssa1 0.63fF
+C801 wbs_dat_o[2] vssa1 0.63fF
+C802 wbs_dat_i[2] vssa1 0.63fF
+C803 wbs_adr_i[2] vssa1 0.63fF
+C804 wbs_dat_o[1] vssa1 0.63fF
+C805 wbs_dat_i[1] vssa1 0.63fF
+C806 wbs_adr_i[1] vssa1 0.63fF
+C807 wbs_sel_i[0] vssa1 0.63fF
+C808 wbs_dat_o[0] vssa1 0.63fF
+C809 wbs_dat_i[0] vssa1 0.63fF
+C810 wbs_adr_i[0] vssa1 0.63fF
+C811 wbs_we_i vssa1 0.63fF
+C812 wbs_stb_i vssa1 0.63fF
+C813 wbs_cyc_i vssa1 0.63fF
+C814 wbs_ack_o vssa1 0.63fF
+C815 wb_rst_i vssa1 0.63fF
+C816 top_pll_v2_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C817 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C818 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C819 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C820 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C821 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C822 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C823 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C824 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C825 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C826 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C827 top_pll_v2_0/QB vssa1 4.35fF
+C828 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C829 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C830 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C831 top_pll_v2_0/out_div_by_5 vssa1 -0.40fF
+C832 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C833 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C834 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C835 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C836 top_pll_v2_0/pfd_reset vssa1 2.17fF
+C837 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C838 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C839 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C840 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C841 top_pll_v2_0/QA vssa1 4.22fF
+C842 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C843 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C844 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C845 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C846 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C847 top_pll_v2_0/nUp vssa1 5.39fF
+C848 top_pll_v2_0/Up vssa1 1.85fF
+C849 top_pll_v2_0/Down vssa1 6.19fF
+C850 top_pll_v2_0/nDown vssa1 -3.53fF
+C851 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C852 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C853 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C854 top_pll_v2_0/div_5_Q1_shift vssa1 -0.14fF
+C855 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C856 top_pll_v2_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C857 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C858 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C859 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C860 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C861 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C862 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C863 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C864 top_pll_v2_0/div_5_Q1 vssa1 4.25fF
+C865 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C866 top_pll_v2_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C867 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C868 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C869 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C870 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C871 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C872 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C873 top_pll_v2_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C874 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C875 top_pll_v2_0/div_5_Q0 vssa1 0.01fF
+C876 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C877 top_pll_v2_0/div_5_nQ0 vssa1 0.59fF
+C878 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C879 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C880 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C881 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C882 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C883 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C884 top_pll_v2_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C885 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C886 top_pll_v2_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C887 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C888 top_pll_v2_0/n_out_by_2 vssa1 -2.75fF
+C889 top_pll_v2_0/div_5_nQ2 vssa1 1.24fF
+C890 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C891 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C892 top_pll_v2_0/out_by_2 vssa1 -5.01fF
+C893 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C894 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C895 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C896 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C897 top_pll_v2_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C898 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C899 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C900 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C901 top_pll_v2_0/out_first_buffer vssa1 2.88fF
+C902 top_pll_v2_0/out_to_buffer vssa1 1.54fF
+C903 top_pll_v2_0/out_to_div vssa1 4.23fF
+C904 top_pll_v2_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C905 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C906 top_pll_v2_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C907 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C908 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C909 top_pll_v2_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C910 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C911 top_pll_v2_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C912 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C913 top_pll_v2_0/vco_out vssa1 1.01fF
+C914 top_pll_v2_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C915 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C916 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C917 io_analog[8] vssa1 13.78fF
+C918 top_pll_v2_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C919 top_pll_v2_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C920 top_pll_v2_0/lf_vc vssa1 -59.89fF
+C921 top_pll_v2_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
+C922 top_pll_v2_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
+C923 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C924 top_pll_v2_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C925 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C926 top_pll_v2_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C927 top_pll_v2_0/out_buffer_div_2 vssa1 1.60fF
+C928 top_pll_v2_0/n_out_buffer_div_2 vssa1 1.63fF
+C929 top_pll_v2_0/out_div_2 vssa1 -1.30fF
+C930 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C931 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C932 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C933 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C934 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C935 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C936 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C937 top_pll_v2_0/n_out_div_2 vssa1 1.95fF
+C938 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C939 top_pll_v2_0/nswitch vssa1 3.73fF
+C940 top_pll_v2_0/biasp vssa1 5.44fF
+C941 bias_0/iref_1 vssa1 -91.53fF
+C942 top_pll_v2_0/vco_vctrl vssa1 -20.08fF
+C943 top_pll_v2_0/pswitch vssa1 3.57fF
+C944 bias_0/iref_4 vssa1 1.17fF
+C945 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vssa1 2.60fF
+C946 bias_0/iref_3 vssa1 0.64fF
+C947 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vssa1 2.60fF
+C948 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vssa1 2.60fF
+C949 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vssa1 2.60fF
+C950 io_analog[5] vssa1 33.29fF
+C951 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vssa1 2.60fF
+C952 bias_0/m1_20168_984# vssa1 56.92fF
+C953 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vssa1 2.60fF
+C954 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vssa1 2.60fF
+C955 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vssa1 2.60fF
+C956 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vssa1 2.60fF
+C957 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vssa1 2.60fF
+C958 top_pll_v1_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C959 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C960 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C961 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C962 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C963 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C964 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C965 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C966 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C967 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C968 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C969 top_pll_v1_0/QB vssa1 4.35fF
+C970 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C971 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C972 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C973 top_pll_v1_0/out_div_by_5 vssa1 -0.40fF
+C974 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C975 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C976 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C977 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C978 top_pll_v1_0/pfd_reset vssa1 2.17fF
+C979 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C980 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C981 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C982 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C983 top_pll_v1_0/QA vssa1 4.22fF
+C984 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C985 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C986 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C987 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C988 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C989 top_pll_v1_0/nUp vssa1 5.39fF
+C990 top_pll_v1_0/Up vssa1 1.85fF
+C991 top_pll_v1_0/Down vssa1 6.19fF
+C992 top_pll_v1_0/nDown vssa1 -3.53fF
+C993 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C994 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C995 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C996 top_pll_v1_0/div_5_Q1_shift vssa1 -0.14fF
+C997 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C998 top_pll_v1_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C999 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1000 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1001 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1002 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1003 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1004 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1005 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1006 top_pll_v1_0/div_5_Q1 vssa1 4.25fF
+C1007 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1008 top_pll_v1_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1009 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1010 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1011 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1012 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1013 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1014 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1015 top_pll_v1_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1016 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1017 top_pll_v1_0/div_5_Q0 vssa1 0.01fF
+C1018 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1019 top_pll_v1_0/div_5_nQ0 vssa1 0.59fF
+C1020 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1021 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1022 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1023 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1024 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1025 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1026 top_pll_v1_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C1027 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1028 top_pll_v1_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1029 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1030 top_pll_v1_0/n_out_by_2 vssa1 -2.75fF
+C1031 top_pll_v1_0/div_5_nQ2 vssa1 1.24fF
+C1032 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1033 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1034 top_pll_v1_0/out_by_2 vssa1 -5.01fF
+C1035 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1036 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1037 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1038 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1039 top_pll_v1_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1040 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1041 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1042 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1043 top_pll_v1_0/out_first_buffer vssa1 2.88fF
+C1044 top_pll_v1_0/out_to_buffer vssa1 1.54fF
+C1045 top_pll_v1_0/out_to_div vssa1 4.23fF
+C1046 top_pll_v1_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1047 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1048 top_pll_v1_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1049 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1050 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1051 top_pll_v1_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1052 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1053 top_pll_v1_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1054 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1055 top_pll_v1_0/vco_out vssa1 1.01fF
+C1056 gpio_noesd[7] vssa1 271.92fF
+C1057 top_pll_v1_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1058 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1059 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1060 io_analog[9] vssa1 7.89fF
+C1061 top_pll_v1_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C1062 top_pll_v1_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1063 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1064 top_pll_v1_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1065 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1066 top_pll_v1_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1067 top_pll_v1_0/out_buffer_div_2 vssa1 1.60fF
+C1068 top_pll_v1_0/n_out_buffer_div_2 vssa1 1.63fF
+C1069 top_pll_v1_0/out_div_2 vssa1 -1.30fF
+C1070 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1071 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1072 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1073 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1074 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1075 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1076 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1077 top_pll_v1_0/n_out_div_2 vssa1 1.95fF
+C1078 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1079 top_pll_v1_0/nswitch vssa1 3.73fF
+C1080 top_pll_v1_0/biasp vssa1 5.44fF
+C1081 bias_0/iref_2 vssa1 -178.91fF
+C1082 top_pll_v1_0/vco_vctrl vssa1 -18.17fF
+C1083 top_pll_v1_0/pswitch vssa1 3.57fF
+C1084 top_pll_v1_0/lf_vc vssa1 -59.89fF
+C1085 top_pll_v1_0/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C1086 top_pll_v3_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C1087 top_pll_v3_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C1088 top_pll_v3_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C1089 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1090 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C1091 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1092 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C1093 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1094 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1095 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C1096 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1097 top_pll_v3_0/QB vssa1 3.01fF
+C1098 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1099 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1100 top_pll_v3_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1101 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1102 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C1103 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1104 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C1105 top_pll_v3_0/pfd_reset vssa1 1.87fF
+C1106 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1107 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1108 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C1109 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1110 top_pll_v3_0/QA vssa1 3.41fF
+C1111 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1112 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1113 top_pll_v3_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1114 io_analog[10] vssa1 502.98fF
+C1115 top_pll_v3_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C1116 top_pll_v3_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C1117 top_pll_v3_0/Up vssa1 -4.79fF
+C1118 top_pll_v3_0/Down vssa1 -0.05fF
+C1119 top_pll_v3_0/nDown vssa1 1.54fF
+C1120 top_pll_v3_0/out_first_buffer vssa1 2.14fF
+C1121 top_pll_v3_0/out_to_buffer vssa1 1.89fF
+C1122 top_pll_v3_0/out_to_div vssa1 8.23fF
+C1123 top_pll_v3_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1124 top_pll_v3_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1125 top_pll_v3_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1126 top_pll_v3_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1127 top_pll_v3_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1128 top_pll_v3_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1129 top_pll_v3_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1130 top_pll_v3_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1131 top_pll_v3_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1132 top_pll_v3_0/vco_out vssa1 1.65fF
+C1133 top_pll_v3_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1134 top_pll_v3_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1135 top_pll_v3_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1136 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/a_63_368# vssa1 0.37fF
+C1137 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C1138 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_0/X vssa1 0.49fF
+C1139 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C1140 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1141 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1142 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1143 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1144 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1145 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1146 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1147 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/D vssa1 1.90fF
+C1148 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1149 top_pll_v3_0/freq_div_0/prescaler_23_0/Q2_d vssa1 -0.69fF
+C1150 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1151 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1152 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1153 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1154 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1155 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1156 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1157 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1158 top_pll_v3_0/freq_div_0/prescaler_23_0/Q2 vssa1 0.55fF
+C1159 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1160 top_pll_v3_0/freq_div_0/prescaler_23_0/Q1 vssa1 0.07fF
+C1161 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1162 top_pll_v3_0/n_clk_0 vssa1 -7.01fF
+C1163 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/nQ vssa1 0.48fF
+C1164 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1165 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1166 top_pll_v3_0/clk_0 vssa1 -0.37fF
+C1167 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1168 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1169 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1170 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1171 top_pll_v3_0/freq_div_0/prescaler_23_0/nCLK_23 vssa1 -1.02fF
+C1172 top_pll_v3_0/freq_div_0/prescaler_23_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1173 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__or2_1_1/X vssa1 -1.01fF
+C1174 gpio_noesd[11] vssa1 104.40fF
+C1175 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_304_74# vssa1 0.36fF
+C1176 top_pll_v3_0/freq_div_0/prescaler_23_0/sky130_fd_sc_hs__mux2_1_0/a_27_112# vssa1 0.65fF
+C1177 top_pll_v3_0/n_out_by_2 vssa1 4.38fF
+C1178 top_pll_v3_0/s_0_n vssa1 -4.09fF
+C1179 top_pll_v3_0/out_by_2 vssa1 4.28fF
+C1180 gpio_noesd[10] vssa1 110.89fF
+C1181 top_pll_v3_0/freq_div_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C1182 top_pll_v3_0/freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C1183 top_pll_v3_0/freq_div_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C1184 top_pll_v3_0/freq_div_0/div_by_5_0/Q1_shift vssa1 -0.36fF
+C1185 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1186 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1187 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1188 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1189 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1190 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1191 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1192 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1193 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1194 top_pll_v3_0/freq_div_0/div_by_5_0/Q1 vssa1 4.35fF
+C1195 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1196 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1197 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1198 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1199 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1200 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1201 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1202 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1203 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1204 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1205 top_pll_v3_0/freq_div_0/div_by_5_0/Q0 vssa1 0.29fF
+C1206 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1207 top_pll_v3_0/freq_div_0/div_by_5_0/nQ0 vssa1 0.99fF
+C1208 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1209 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1210 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1211 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1212 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1213 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1214 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C1215 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1216 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1217 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1218 top_pll_v3_0/n_clk_1 vssa1 -0.56fF
+C1219 top_pll_v3_0/freq_div_0/div_by_5_0/nQ2 vssa1 1.38fF
+C1220 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1221 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1222 top_pll_v3_0/clk_1 vssa1 -2.08fF
+C1223 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1224 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1225 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1226 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1227 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1228 top_pll_v3_0/freq_div_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1229 top_pll_v3_0/freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1230 top_pll_v3_0/freq_div_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1231 top_pll_v3_0/s_1_n vssa1 -2.04fF
+C1232 top_pll_v3_0/out_div vssa1 3.58fF
+C1233 top_pll_v3_0/clk_d vssa1 1.27fF
+C1234 gpio_noesd[9] vssa1 196.62fF
+C1235 top_pll_v3_0/freq_div_0/inverter_min_x4_0/in vssa1 2.71fF
+C1236 top_pll_v3_0/clk_5 vssa1 -0.22fF
+C1237 top_pll_v3_0/clk_out_mux21 vssa1 3.89fF
+C1238 top_pll_v3_0/clk_pre vssa1 1.69fF
+C1239 top_pll_v3_0/freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1240 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1241 top_pll_v3_0/freq_div_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1242 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1243 top_pll_v3_0/clk_2_f vssa1 3.30fF
+C1244 top_pll_v3_0/freq_div_0/div_by_2_0/o1 vssa1 2.08fF
+C1245 top_pll_v3_0/freq_div_0/div_by_2_0/nCLK_2 vssa1 1.04fF
+C1246 top_pll_v3_0/freq_div_0/div_by_2_0/o2 vssa1 2.08fF
+C1247 top_pll_v3_0/freq_div_0/div_by_2_0/out_div vssa1 -0.82fF
+C1248 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1249 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1250 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1251 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1252 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1253 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1254 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1255 top_pll_v3_0/freq_div_0/div_by_2_0/nout_div vssa1 2.62fF
+C1256 top_pll_v3_0/freq_div_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1257 io_analog[7] vssa1 24.25fF
+C1258 top_pll_v3_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C1259 top_pll_v3_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1260 top_pll_v3_0/lf_vc vssa1 -60.88fF
+C1261 top_pll_v3_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
+C1262 gpio_noesd[8] vssa1 303.23fF
+C1263 top_pll_v3_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
+C1264 top_pll_v3_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1265 top_pll_v3_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1266 top_pll_v3_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1267 top_pll_v3_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1268 top_pll_v3_0/out_buffer_div_2 vssa1 1.57fF
+C1269 top_pll_v3_0/n_out_buffer_div_2 vssa1 1.57fF
+C1270 top_pll_v3_0/out_div_2 vssa1 -0.70fF
+C1271 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1272 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1273 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1274 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1275 top_pll_v3_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1276 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1277 top_pll_v3_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1278 top_pll_v3_0/n_out_div_2 vssa1 2.11fF
+C1279 top_pll_v3_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1280 top_pll_v3_0/nswitch vssa1 4.61fF
+C1281 top_pll_v3_0/biasp vssa1 5.45fF
+C1282 bias_0/iref_0 vssa1 -81.72fF
+C1283 top_pll_v3_0/vco_vctrl vssa1 -30.71fF
+C1284 top_pll_v3_0/pswitch vssa1 2.72fF
+C1285 bias_0/iref_6 vssa1 -645.65fF
+C1286 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in vssa1 -32.98fF
+C1287 io_analog[1] vssa1 73.96fF
+C1288 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# vssa1 1.29fF
+C1289 bias_0/iref_5 vssa1 -623.45fF
+C1290 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in vssa1 -32.98fF
+C1291 io_analog[0] vssa1 -155.24fF
+C1292 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# vssa1 1.29fF
+C1293 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# vssa1 -35.44fF
+C1294 bias_0/iref_8 vssa1 -189.06fF
+C1295 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# vssa1 -35.44fF
+C1296 bias_0/iref_7 vssa1 -205.18fF
+C1297 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# vssa1 -1.87fF
+C1298 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# vssa1 0.47fF
+C1299 gpio_noesd[5] vssa1 122.09fF
+C1300 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# vssa1 -1.10fF
+C1301 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl vssa1 -2.03fF
+C1302 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# vssa1 -2.23fF
+C1303 gpio_noesd[6] vssa1 325.91fF
+C1304 gpio_noesd[4] vssa1 116.78fF
+C1305 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# vssa1 -1.03fF
+C1306 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# vssa1 0.51fF
+C1307 bias_0/iref_9 vssa1 -181.57fF
+C1308 res_amp_top_0/res_amp_lin_prog_0/outn vssa1 1.55fF
+C1309 io_analog[3] vssa1 -119.52fF
+C1310 res_amp_top_0/res_amp_lin_prog_0/outp vssa1 -4.89fF
+C1311 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp vssa1 -4.89fF
+C1312 io_analog[2] vssa1 -131.04fF
+C1313 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# vssa1 -0.95fF
+C1314 res_amp_top_0/res_amp_lin_prog_0/outn_cap vssa1 -0.01fF
+C1315 res_amp_top_0/res_amp_lin_prog_0/inverter_min_x4_0/out vssa1 4.60fF
+C1316 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk vssa1 4.27fF
+C1317 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in vssa1 1.07fF
+C1318 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA vssa1 -0.04fF
+C1319 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in vssa1 1.03fF
+C1320 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in vssa1 1.03fF
+C1321 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in vssa1 1.07fF
+C1322 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in vssa1 1.03fF
+C1323 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in vssa1 1.03fF
+C1324 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in vssa1 1.07fF
+C1325 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in vssa1 1.03fF
+C1326 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in vssa1 1.07fF
+C1327 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in vssa1 1.03fF
+C1328 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in vssa1 1.03fF
+C1329 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in vssa1 1.03fF
+C1330 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in vssa1 1.07fF
+C1331 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB vssa1 -7.88fF
+C1332 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in vssa1 1.03fF
+C1333 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in vssa1 1.03fF
+C1334 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in vssa1 1.07fF
+C1335 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in vssa1 1.03fF
+C1336 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1337 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in vssa1 1.03fF
+C1338 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 vssa1 1.54fF
+C1339 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b vssa1 2.03fF
+C1340 gpio_noesd[3] vssa1 213.06fF
+C1341 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out vssa1 -1.67fF
+C1342 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b vssa1 2.03fF
+C1343 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA vssa1 -2.58fF
+C1344 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out vssa1 -2.25fF
+C1345 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b vssa1 2.03fF
+C1346 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out vssa1 -2.69fF
+C1347 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB vssa1 -4.96fF
+C1348 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b vssa1 2.03fF
+C1349 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out vssa1 -4.71fF
+C1350 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b vssa1 2.03fF
+C1351 gpio_noesd[2] vssa1 216.13fF
+C1352 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA vssa1 0.63fF
+C1353 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out vssa1 -2.49fF
+C1354 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB vssa1 -3.92fF
+C1355 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b vssa1 2.03fF
+C1356 gpio_noesd[1] vssa1 230.09fF
+C1357 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out vssa1 -0.27fF
+C1358 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB vssa1 -0.97fF
+C1359 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b vssa1 2.03fF
+C1360 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in vssa1 1.07fF
+C1361 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in vssa1 1.03fF
+C1362 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in vssa1 1.03fF
+C1363 res_amp_top_0/res_amp_lin_prog_0/outp_cap vssa1 -7.66fF
+C1364 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/m1_21_n341# vssa1 0.72fF
+C1365 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1366 res_amp_top_0/res_amp_lin_prog_0/clk vssa1 -8.26fF
+C1367 res_amp_top_0/res_amp_sync_v2_0/inverter_min_x4_4/out vssa1 5.85fF
+C1368 res_amp_top_0/res_amp_sync_v2_0/rst vssa1 -7.88fF
+C1369 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/out vssa1 1.70fF
+C1370 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/Q vssa1 -2.08fF
+C1371 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1372 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/nQ vssa1 0.48fF
+C1373 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D vssa1 -1.73fF
+C1374 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1375 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD vssa1 0.57fF
+C1376 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1377 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D vssa1 0.96fF
+C1378 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1379 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/D vssa1 1.83fF
+C1380 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD vssa1 1.14fF
+C1381 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/out vssa1 1.20fF
+C1382 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/Q vssa1 -2.94fF
+C1383 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1384 io_analog[4] vssa1 -253.69fF
+C1385 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1386 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1387 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1388 io_analog[6] vssa1 -26.69fF
+C1389 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1390 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1391 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1392 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1393 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/D vssa1 0.79fF
+C1394 vdda1 vssa1 7499.69fF
+C1395 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1396 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/Q vssa1 -1.08fF
+C1397 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1398 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1399 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1400 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1401 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1402 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1403 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1404 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1405 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/D vssa1 -0.38fF
+C1406 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1407 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1408 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/nQ vssa1 0.48fF
+C1409 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1410 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1411 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1412 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1413 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1414 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1415 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/D vssa1 -1.04fF
+C1416 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1417 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/Q vssa1 -4.73fF
+C1418 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1419 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/nQ vssa1 0.48fF
+C1420 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1421 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1422 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1423 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1424 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1425 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1426 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
.ends
diff --git a/mag/freq_div.mag b/mag/freq_div.mag
index 3d6b5e9..14416b0 100644
--- a/mag/freq_div.mag
+++ b/mag/freq_div.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624885207
+timestamp 1624896651
<< nwell >>
rect 2984 3068 4571 3079
rect 10778 3059 11706 3083
@@ -358,6 +358,14 @@
rect -1845 237 -1844 240
rect 15571 239 15661 240
rect -1953 236 -1844 237
+use div_by_5 div_by_5_0
+timestamp 1624896651
+transform 1 0 556 0 1 0
+box -556 0 13892 3068
+use div_by_2 div_by_2_0
+timestamp 1624896651
+transform 1 0 17530 0 1 0
+box -1244 0 4228 3068
use mux2to1 mux2to1_1
timestamp 1624653480
transform -1 0 23305 0 -1 2710
@@ -370,10 +378,6 @@
timestamp 1624653480
transform 1 0 -2821 0 -1 2556
box -11 -1360 2541 2
-use div_by_5 div_by_5_0
-timestamp 1624885207
-transform 1 0 556 0 1 0
-box -556 0 13892 3068
use inverter_min_x2 inverter_min_x2_2
timestamp 1624049879
transform 1 0 -1766 0 -1 655
@@ -382,10 +386,6 @@
timestamp 1624049879
transform -1 0 22879 0 -1 655
box -53 -615 473 655
-use div_by_2 div_by_2_0
-timestamp 1624885207
-transform 1 0 17530 0 1 0
-box -1244 0 4228 3068
use inverter_min_x4 inverter_min_x4_0
timestamp 1624049879
transform 1 0 18971 0 -1 4889
@@ -395,7 +395,7 @@
transform 1 0 18445 0 -1 4890
box -53 -615 473 655
use prescaler_23 prescaler_23_0
-timestamp 1624885207
+timestamp 1624896651
transform 1 0 0 0 -1 6136
box 0 -316 11752 3068
<< labels >>
diff --git a/mag/prescaler_23.mag b/mag/prescaler_23.mag
index 7c01995..11b362d 100644
--- a/mag/prescaler_23.mag
+++ b/mag/prescaler_23.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624885207
+timestamp 1624896651
<< nwell >>
rect 2984 1980 4570 3060
rect 10382 2725 10536 3068
@@ -359,22 +359,6 @@
rect 3558 234 3559 267
rect 3664 234 3665 393
rect 3558 233 3665 234
-use sky130_fd_sc_hs__mux2_1 sky130_fd_sc_hs__mux2_1_0
-timestamp 1623986409
-transform 1 0 10830 0 -1 1419
-box -38 -49 902 715
-use sky130_fd_sc_hs__or2_1 sky130_fd_sc_hs__or2_1_0
-timestamp 1624049879
-transform 1 0 3537 0 1 1649
-box -38 -49 518 715
-use sky130_fd_sc_hs__or2_1 sky130_fd_sc_hs__or2_1_1
-timestamp 1624049879
-transform 1 0 11026 0 1 1649
-box -38 -49 518 715
-use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_0
-timestamp 1624049879
-transform 1 0 3537 0 -1 1419
-box -38 -49 518 715
use DFlipFlop DFlipFlop_0
timestamp 1624885207
transform 1 0 1244 0 1 0
@@ -387,6 +371,22 @@
timestamp 1624885207
transform 1 0 8798 0 -1 3068
box -1244 0 1740 3068
+use sky130_fd_sc_hs__and2_1 sky130_fd_sc_hs__and2_1_0
+timestamp 1624049879
+transform 1 0 3537 0 -1 1419
+box -38 -49 518 715
+use sky130_fd_sc_hs__or2_1 sky130_fd_sc_hs__or2_1_1
+timestamp 1624049879
+transform 1 0 11026 0 1 1649
+box -38 -49 518 715
+use sky130_fd_sc_hs__or2_1 sky130_fd_sc_hs__or2_1_0
+timestamp 1624049879
+transform 1 0 3537 0 1 1649
+box -38 -49 518 715
+use sky130_fd_sc_hs__mux2_1 sky130_fd_sc_hs__mux2_1_0
+timestamp 1623986409
+transform 1 0 10830 0 -1 1419
+box -38 -49 902 715
<< labels >>
rlabel metal4 2267 860 6523 952 1 CLK
rlabel metal4 2270 2112 6548 2204 1 nCLK
diff --git a/mag/top_pll_v1.mag b/mag/top_pll_v1.mag
index e732e11..bdb5c72 100644
--- a/mag/top_pll_v1.mag
+++ b/mag/top_pll_v1.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624402156
+timestamp 1624896651
<< nwell >>
rect 0 2846 20536 2860
rect 0 2838 6183 2846
@@ -518,42 +518,42 @@
rect 13764 -4358 13765 -3781
rect 13076 -4359 13765 -4358
rect 19686 -4493 43939 -3693
-use div_by_2 div_by_2_0
-timestamp 1624402156
-transform -1 0 18034 0 -1 -350
-box -1244 0 4228 3068
-use div_by_5 div_by_5_0
-timestamp 1624402156
-transform -1 0 13250 0 1 -3418
-box -556 0 13892 3068
-use ring_osc_buffer ring_osc_buffer_0
-timestamp 1624402156
-transform 1 0 18509 0 1 653
-box 0 0 1963 1270
-use ring_osc ring_osc_0
-timestamp 1624049879
-transform 1 0 14447 0 1 -174
-box -422 0 3882 2956
-use PFD PFD_0
-timestamp 1624049879
-transform 1 0 0 0 1 1304
-box 0 -1304 3790 1304
use pfd_cp_interface pfd_cp_interface_0
-timestamp 1624049879
+timestamp 1624885207
transform 1 0 3909 0 1 -230
box 0 0 2154 3068
-use buffer_salida buffer_salida_0
-timestamp 1624049879
-transform 1 0 20599 0 1 1292
-box -63 -1119 28718 1568
-use charge_pump charge_pump_0
-timestamp 1624049879
-transform 1 0 6183 0 1 -142
-box 0 -96 7722 2988
+use div_by_5 div_by_5_0
+timestamp 1624896651
+transform -1 0 13250 0 1 -3418
+box -556 0 13892 3068
+use div_by_2 div_by_2_0
+timestamp 1624896651
+transform -1 0 18034 0 -1 -350
+box -1244 0 4228 3068
use loop_filter loop_filter_0
timestamp 1624049879
transform 1 0 15820 0 1 -9473
box -16462 -24206 34360 5780
+use charge_pump charge_pump_0
+timestamp 1624049879
+transform 1 0 6183 0 1 -142
+box 0 -96 7722 2988
+use buffer_salida buffer_salida_0
+timestamp 1624049879
+transform 1 0 20599 0 1 1292
+box -63 -1119 28718 1568
+use PFD PFD_0
+timestamp 1624049879
+transform 1 0 0 0 1 1304
+box 0 -1304 3790 1304
+use ring_osc ring_osc_0
+timestamp 1624049879
+transform 1 0 14447 0 1 -174
+box -422 0 3882 2956
+use ring_osc_buffer ring_osc_buffer_0
+timestamp 1624402156
+transform 1 0 18509 0 1 653
+box 0 0 1963 1270
<< labels >>
rlabel metal2 2159 858 2211 1750 1 pfd_reset
rlabel metal1 0 1956 210 2022 1 in_ref
diff --git a/mag/top_pll_v2.mag b/mag/top_pll_v2.mag
index ef4fb6a..b1ecf32 100644
--- a/mag/top_pll_v2.mag
+++ b/mag/top_pll_v2.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624402156
+timestamp 1624896651
<< nwell >>
rect 0 2846 20536 2860
rect 0 2838 6183 2846
@@ -519,42 +519,42 @@
rect 13764 -4358 13765 -3781
rect 13076 -4359 13765 -4358
rect 19686 -4493 43939 -3693
-use charge_pump charge_pump_0
-timestamp 1624049879
-transform 1 0 6183 0 1 -142
-box 0 -96 7722 2988
-use buffer_salida buffer_salida_0
-timestamp 1624049879
-transform 1 0 20599 0 1 1292
-box -63 -1119 28718 1568
use pfd_cp_interface pfd_cp_interface_0
-timestamp 1624049879
+timestamp 1624885207
transform 1 0 3909 0 1 -230
box 0 0 2154 3068
-use PFD PFD_0
-timestamp 1624049879
-transform 1 0 0 0 1 1304
-box 0 -1304 3790 1304
-use ring_osc ring_osc_0
-timestamp 1624049879
-transform 1 0 14447 0 1 -174
-box -422 0 3882 2956
-use ring_osc_buffer ring_osc_buffer_0
-timestamp 1624402156
-transform 1 0 18509 0 1 653
-box 0 0 1963 1270
use div_by_5 div_by_5_0
-timestamp 1624402156
+timestamp 1624896651
transform -1 0 13250 0 1 -3418
box -556 0 13892 3068
use div_by_2 div_by_2_0
-timestamp 1624402156
+timestamp 1624896651
transform -1 0 18034 0 -1 -350
box -1244 0 4228 3068
use loop_filter_v2 loop_filter_v2_0
timestamp 1624053471
transform 1 0 15820 0 1 -9473
box -16462 -24206 34360 5780
+use ring_osc_buffer ring_osc_buffer_0
+timestamp 1624402156
+transform 1 0 18509 0 1 653
+box 0 0 1963 1270
+use ring_osc ring_osc_0
+timestamp 1624049879
+transform 1 0 14447 0 1 -174
+box -422 0 3882 2956
+use PFD PFD_0
+timestamp 1624049879
+transform 1 0 0 0 1 1304
+box 0 -1304 3790 1304
+use buffer_salida buffer_salida_0
+timestamp 1624049879
+transform 1 0 20599 0 1 1292
+box -63 -1119 28718 1568
+use charge_pump charge_pump_0
+timestamp 1624049879
+transform 1 0 6183 0 1 -142
+box 0 -96 7722 2988
<< labels >>
rlabel metal2 2159 858 2211 1750 1 pfd_reset
rlabel metal1 0 1956 210 2022 1 in_ref
diff --git a/mag/top_pll_v3.mag b/mag/top_pll_v3.mag
index 8270648..ca5cb27 100644
--- a/mag/top_pll_v3.mag
+++ b/mag/top_pll_v3.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624886397
+timestamp 1624896651
<< nwell >>
rect 0 2846 20536 2860
rect 0 2838 6183 2846
@@ -546,42 +546,42 @@
rect 13136 -7854 13169 -7126
rect 13729 -7854 13764 -7126
rect 13136 -7886 13764 -7854
-use loop_filter_v2 loop_filter_v2_0
-timestamp 1624053471
-transform 1 0 15820 0 1 -12873
-box -16462 -24206 34360 5780
-use div_by_2 div_by_2_0
-timestamp 1624885207
-transform -1 0 30791 0 -1 -468
-box -1244 0 4228 3068
-use freq_div *freq_div_0
-timestamp 1624885207
-transform -1 0 22875 0 -1 -400
-box -2832 0 23316 6452
-use ring_osc_buffer ring_osc_buffer_0
-timestamp 1624402156
-transform 1 0 18509 0 1 653
-box 0 0 1963 1270
-use ring_osc ring_osc_0
-timestamp 1624049879
-transform 1 0 14447 0 1 -174
-box -422 0 3882 2956
-use PFD PFD_0
-timestamp 1624049879
-transform 1 0 0 0 1 1304
-box 0 -1304 3790 1304
use pfd_cp_interface pfd_cp_interface_0
timestamp 1624885207
transform 1 0 3909 0 1 -230
box 0 0 2154 3068
-use buffer_salida buffer_salida_0
-timestamp 1624049879
-transform 1 0 20599 0 1 1292
-box -63 -1119 28718 1568
+use div_by_2 div_by_2_0
+timestamp 1624896651
+transform -1 0 30791 0 -1 -468
+box -1244 0 4228 3068
use charge_pump *charge_pump_0
timestamp 1624049879
transform 1 0 6183 0 1 -142
box 0 -96 7722 2988
+use buffer_salida buffer_salida_0
+timestamp 1624049879
+transform 1 0 20599 0 1 1292
+box -63 -1119 28718 1568
+use PFD PFD_0
+timestamp 1624049879
+transform 1 0 0 0 1 1304
+box 0 -1304 3790 1304
+use ring_osc ring_osc_0
+timestamp 1624049879
+transform 1 0 14447 0 1 -174
+box -422 0 3882 2956
+use ring_osc_buffer ring_osc_buffer_0
+timestamp 1624402156
+transform 1 0 18509 0 1 653
+box 0 0 1963 1270
+use freq_div *freq_div_0
+timestamp 1624896651
+transform -1 0 22875 0 -1 -400
+box -2832 0 23316 6452
+use loop_filter_v2 loop_filter_v2_0
+timestamp 1624053471
+transform 1 0 15820 0 1 -12873
+box -16462 -24206 34360 5780
<< labels >>
rlabel metal2 2159 858 2211 1750 1 pfd_reset
rlabel metal1 0 1956 210 2022 1 in_ref
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index 6b6fd30..9c674aa 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1624402156
+timestamp 1624896780
<< nwell >>
rect 14730 660108 64962 661110
rect 14730 660034 64841 660108
@@ -125,8 +125,8 @@
rect 119074 659953 119177 660062
rect 125643 660015 133067 660062
rect 112601 659944 119177 659953
-rect 157073 659472 157083 659901
-rect 198006 659472 198016 659901
+rect 157078 659483 157088 659803
+rect 192325 659483 192335 659803
rect 12990 659376 14703 659415
rect 12990 659103 13065 659376
rect 14624 659270 14703 659376
@@ -173,40 +173,33 @@
rect 149987 657395 149997 658524
rect 152333 658062 156268 658524
rect 152333 657778 157347 658062
+rect 206380 657846 208306 658174
rect 152333 657395 156268 657778
rect 149997 657379 156268 657395
rect 82894 656573 83702 657275
rect 112660 657160 112670 657243
rect 112802 657160 112812 657243
rect 112685 656533 112741 657160
-rect 156207 656708 157418 657036
rect 197704 657001 197714 657125
rect 199942 657001 199952 657125
rect 112626 656348 112636 656533
rect 112797 656348 112807 656533
-rect 156207 656248 156786 656708
-rect 186130 656623 186140 656702
-rect 186225 656623 186235 656702
-rect 186152 656414 186208 656623
-rect 186119 656316 186129 656414
-rect 186241 656316 186251 656414
rect 12125 655528 13406 655533
rect 12125 655200 14468 655528
rect 133382 655200 135242 655528
rect 12125 652870 13406 655200
rect 134093 653281 135239 655200
-rect 207475 654986 208245 655013
-rect 206694 654658 208245 654986
rect 12125 651670 15784 652870
rect 132088 652146 135239 653281
-rect 207475 652403 208245 654658
rect 132558 652135 135239 652146
rect 12125 651669 15583 651670
rect 12125 651650 13406 651669
-rect 205405 651403 208245 652403
-rect 205405 651383 207885 651403
+rect 207978 650936 208306 657846
+rect 204923 650607 208306 650936
rect 124847 637057 124857 637281
rect 125442 637057 125452 637281
+rect 198050 633158 198060 633275
+rect 198739 633158 198749 633275
<< via1 >>
rect 202966 687835 206549 688225
rect 207123 687795 210595 688222
@@ -253,7 +246,7 @@
rect 132556 660180 133038 660424
rect 120252 660106 133038 660180
rect 112657 659953 119074 660076
-rect 157083 659472 198006 659901
+rect 157088 659483 192325 659803
rect 13065 659103 14624 659376
rect 133081 659175 133354 659303
rect 66170 657870 68582 659137
@@ -267,9 +260,8 @@
rect 112670 657160 112802 657243
rect 197714 657001 199942 657125
rect 112636 656348 112797 656533
-rect 186140 656623 186225 656702
-rect 186129 656316 186241 656414
rect 124857 637057 125442 637281
+rect 198060 633158 198739 633275
<< metal2 >>
rect 211169 688703 214642 688713
rect 207123 688623 210596 688633
@@ -307,7 +299,6 @@
rect 14834 660111 23042 660121
rect 23042 660091 64025 660101
rect 83756 660472 83765 660482
-rect 157083 660502 197708 660512
rect 124085 660445 133038 660455
rect 112324 659999 112657 660179
rect 83756 659989 112324 659999
@@ -315,7 +306,7 @@
rect 119074 660096 133038 660106
rect 119074 659999 120418 660096
rect 112657 659943 119074 659953
-rect 197708 659901 198006 659911
+rect 157088 659960 192325 659970
rect 2509 659760 14155 659826
rect 2509 658727 2671 659760
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@@ -333,7 +324,7 @@
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rect 133210 658850 140004 658887
rect 206714 659015 212383 659085
rect 206714 658768 209986 659015
@@ -366,21 +357,30 @@
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rect 35452 656678 73065 656710
rect 197714 656991 199942 657001
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rect 144160 637403 145498 637413
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rect 124857 637281 144160 637291
@@ -393,6 +393,13 @@
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rect 368680 633573 368815 633583
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rect 152624 510676 153820 510686
rect 1323 510540 152624 510561
rect 1323 510538 73012 510540
@@ -410,6 +417,27 @@
rect 1326 467013 144170 467014
rect 145472 467013 145524 467320
rect 1326 466990 145524 467013
+rect 227798 424159 229007 424169
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+rect 1890 337352 242303 337654
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+rect 243532 337328 243556 337677
+rect 242303 337310 243532 337320
rect 524 -800 636 480
rect 1706 -800 1818 480
rect 2888 -800 3000 480
@@ -941,12 +969,12 @@
rect 112657 660179 119074 660332
rect 119074 660179 120252 660332
rect 120252 660179 124085 660445
-rect 157083 659901 197708 660502
rect 2671 658727 5073 659760
+rect 157088 659803 192325 659960
rect 66170 657870 68582 659137
rect 79848 657985 82308 658972
rect 137580 658887 139946 659558
-rect 157083 659472 197708 659901
+rect 157088 659483 192325 659803
rect 21160 657665 23631 657690
rect 21160 657532 23631 657665
rect 124336 657529 126700 657669
@@ -954,15 +982,26 @@
rect 209986 658377 212293 659015
rect 73065 656222 74069 657028
rect 197714 657001 199942 657125
-rect 152633 656134 153791 656403
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+rect 227813 652745 229004 652913
+rect 242313 649835 243530 650014
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rect 144160 636937 145498 637403
rect 368681 635421 368816 635516
rect 368680 633583 368815 633678
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rect 1358 510236 2171 510538
rect 73012 510260 74070 510540
rect 152624 510205 153820 510676
rect 1361 467014 2174 467316
rect 144170 467013 145472 467320
+rect 974 423801 1787 424103
+rect 227798 423762 229007 424159
+rect 1164 380579 1977 380881
+rect 235266 380530 236476 380923
+rect 1077 337352 1890 337654
+rect 242303 337320 243532 337690
<< metal3 >>
rect 16194 702300 21194 704800
rect 68194 702300 73194 704800
@@ -1102,10 +1141,9 @@
rect 190382 667305 192882 681570
rect 190367 664796 190377 667305
rect 192874 664796 192884 667305
-rect 157073 660502 197718 660507
-rect 157073 659472 157083 660502
-rect 197708 659472 197718 660502
-rect 157073 659467 197718 659472
+rect 157078 659483 157088 660235
+rect 192327 659483 192337 660235
+rect 157078 659478 192335 659483
rect 149955 657395 149997 658524
rect 152333 657395 152455 658524
rect 149955 657301 152455 657395
@@ -1170,15 +1208,19 @@
rect 197704 657001 197714 657125
rect 199942 657001 199952 657125
rect 197704 656996 199952 657001
-rect 152609 656403 153837 656431
-rect 152609 656134 152633 656403
-rect 153791 656134 153837 656403
+rect 152600 656658 153843 656663
+rect 152600 656472 152610 656658
+rect 153833 656472 153843 656658
+rect 152600 656467 153843 656472
rect 137480 607168 137755 611839
rect 139770 607168 139980 611839
rect 137480 607076 139980 607168
rect 144145 637403 145521 637418
rect 144145 636937 144160 637403
rect 145498 636937 145521 637403
+rect 144145 632647 145521 636937
+rect 144145 631480 144162 632647
+rect 145484 631480 145521 632647
rect 72999 510260 73012 510540
rect 74070 510260 74122 510540
rect 72999 510192 74122 510260
@@ -1195,10 +1237,15 @@
rect 1351 467014 1361 467118
rect 2174 467014 2184 467316
rect 1351 467009 2184 467014
-rect 144145 467320 145521 636937
-rect 152609 510676 153837 656134
-rect 156490 620709 156500 624128
-rect 206836 620709 206846 624128
+rect 144145 467320 145521 631480
+rect 152609 510676 153837 656467
+rect 181564 649797 181652 653612
+rect 181555 649792 181660 649797
+rect 181555 649671 181565 649792
+rect 181650 649671 181660 649792
+rect 181555 649666 181660 649671
+rect 155874 618137 155884 620718
+rect 207402 618137 207412 620718
rect 209899 611733 212399 658377
rect 296890 658340 299390 688285
rect 301225 661655 303725 691142
@@ -1230,6 +1277,26 @@
rect 303725 659155 303735 661655
rect 296880 655840 296890 658340
rect 299390 655840 299400 658340
+rect 209899 607161 210137 611733
+rect 212245 607161 212399 611733
+rect 209899 606979 212399 607161
+rect 227791 652913 229019 652943
+rect 227791 652745 227813 652913
+rect 229004 652745 229019 652913
+rect 152609 510205 152624 510676
+rect 153820 510205 153837 510676
+rect 152609 510169 153837 510205
+rect 144145 467013 144170 467320
+rect 145472 467013 145521 467320
+rect 144145 466948 145521 467013
+rect -800 465944 480 466056
+rect -800 464872 1188 464874
+rect -800 464762 1508 464872
+rect 253 464760 1508 464762
+rect -800 463580 480 463692
+rect -800 462398 480 462510
+rect -800 425086 480 425198
+rect 227791 424164 229019 652745
rect 325555 650863 328055 692621
rect 582300 681668 584800 682984
rect 576277 679168 576287 681668
@@ -1246,6 +1313,54 @@
rect 369549 659155 369559 661655
rect 366150 655840 366160 658340
rect 367510 655840 367520 658340
+rect 242308 650019 243536 650034
+rect 242303 650014 243540 650019
+rect 242303 649835 242313 650014
+rect 243530 649835 243540 650014
+rect 235257 649816 236485 649832
+rect 242303 649830 243540 649835
+rect 235251 649811 236492 649816
+rect 235251 649653 235261 649811
+rect 236482 649653 236492 649811
+rect 235251 649648 236492 649653
+rect 227788 424159 229019 424164
+rect 964 424103 1797 424108
+rect 964 424017 974 424103
+rect 255 424016 974 424017
+rect -800 423905 974 424016
+rect -800 423904 480 423905
+rect 964 423801 974 423905
+rect 1787 423801 1797 424103
+rect 964 423796 1797 423801
+rect 227788 423762 227798 424159
+rect 229007 423762 229019 424159
+rect 227788 423757 229019 423762
+rect 227791 423745 229019 423757
+rect -800 422722 480 422834
+rect -800 421540 480 421652
+rect -800 420358 480 420470
+rect -800 419176 480 419288
+rect -800 381864 480 381976
+rect 235257 380928 236485 649648
+rect 235256 380923 236486 380928
+rect 1154 380881 1987 380886
+rect 1154 380795 1164 380881
+rect 143 380794 1164 380795
+rect -800 380683 1164 380794
+rect -800 380682 480 380683
+rect 1154 380579 1164 380683
+rect 1977 380579 1987 380881
+rect 1154 380574 1987 380579
+rect 235256 380530 235266 380923
+rect 236476 380530 236486 380923
+rect 235256 380525 236486 380530
+rect 235257 380513 236485 380525
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+rect -800 375954 480 376066
+rect -800 338642 480 338754
+rect 242308 337695 243536 649830
rect 325545 648363 325555 650863
rect 328055 648363 328065 650863
rect 325555 648358 328055 648363
@@ -1320,35 +1435,18 @@
rect 352226 613265 360609 613751
rect 360123 612028 360609 613265
rect 365504 613072 365990 614551
-rect 209899 607161 210137 611733
-rect 212245 607161 212399 611733
-rect 209899 606979 212399 607161
-rect 152609 510205 152624 510676
-rect 153820 510205 153837 510676
-rect 152609 510169 153837 510205
-rect 144145 467013 144170 467320
-rect 145472 467013 145521 467320
-rect 144145 466948 145521 467013
-rect -800 465944 480 466056
-rect -800 464872 1188 464874
-rect -800 464762 1508 464872
-rect 253 464760 1508 464762
-rect -800 463580 480 463692
-rect -800 462398 480 462510
-rect -800 425086 480 425198
-rect -800 423904 480 424016
-rect -800 422722 480 422834
-rect -800 421540 480 421652
-rect -800 420358 480 420470
-rect -800 419176 480 419288
-rect -800 381864 480 381976
-rect -800 380682 480 380794
-rect -800 379500 480 379612
-rect -800 378318 480 378430
-rect -800 377136 480 377248
-rect -800 375954 480 376066
-rect -800 338642 480 338754
-rect -800 337460 480 337572
+rect 242293 337690 243542 337695
+rect 1067 337654 1900 337659
+rect -800 337568 480 337572
+rect 1067 337568 1077 337654
+rect -800 337460 1077 337568
+rect 163 337456 1077 337460
+rect 1067 337352 1077 337456
+rect 1890 337352 1900 337654
+rect 1067 337347 1900 337352
+rect 242293 337320 242303 337690
+rect 243532 337320 243542 337690
+rect 242293 337315 243542 337320
rect -800 336278 480 336390
rect -800 335096 480 335208
rect -800 333914 480 334026
@@ -1531,14 +1629,16 @@
rect 223921 694931 226270 697338
rect 207591 690328 209950 692355
rect 190377 664796 192874 667305
-rect 157083 659472 197708 660502
+rect 157088 659960 192327 660235
+rect 157088 659483 192325 659960
+rect 192325 659483 192327 659960
rect 242732 699634 245232 702134
rect 228965 694945 231314 697352
rect 227277 688115 230750 688664
rect 202780 684711 247142 685291
rect 202805 684082 247109 684711
rect 137755 607168 139770 611839
-rect 156500 620709 206836 624128
+rect 155884 618137 207402 620718
rect 510511 696878 525661 703099
rect 567875 696717 570375 698736
rect 414564 693921 417064 696421
@@ -1548,6 +1648,7 @@
rect 305178 662170 307678 664670
rect 301225 659155 303725 661655
rect 296890 655840 299390 658340
+rect 210137 607161 212245 611733
rect 576287 679168 578306 681668
rect 373475 669228 374825 671728
rect 371788 665658 373138 668158
@@ -1562,7 +1663,6 @@
rect 360264 628346 360662 628648
rect 361132 628469 361530 628771
rect 362048 628436 362446 628738
-rect 210137 607161 212245 611733
rect 578768 540186 583178 555678
rect 578419 225380 583286 240347
rect 578907 136610 583774 151577
@@ -1686,10 +1786,8 @@
rect 83764 660179 83765 661488
rect 83764 660178 124072 660179
rect 23041 660100 64018 660101
-rect 157082 659472 157083 660503
-rect 197702 660502 197709 660503
-rect 197708 659472 197709 660502
-rect 157082 659471 197709 659472
+rect 157087 659483 157088 660236
+rect 157087 659482 192328 659483
rect 233017 635570 235517 664799
rect 305177 664670 307679 664671
rect 369972 664670 371324 664671
@@ -1773,9 +1871,7 @@
rect 14426 624437 14427 624619
rect 64644 621627 64645 624619
rect 64282 621626 64645 621627
-rect 156499 624128 206837 624129
-rect 156499 624087 156500 624128
-rect 206836 620708 206837 624128
+rect 155883 618136 155884 620719
rect 275302 624644 345528 625028
rect 275302 617580 311280 624644
rect 345358 623908 345528 624644
@@ -1931,8 +2027,9 @@
rect 83765 661487 124085 662834
rect 83765 660179 124071 661487
rect 124071 660179 124085 661487
-rect 157083 660502 197702 661420
-rect 157083 659472 197702 660502
+rect 157088 660235 192336 660547
+rect 157088 659483 192327 660235
+rect 192327 659483 192336 660235
rect 356670 643622 356990 643930
rect 359056 643622 359376 643930
rect 360315 637262 360607 637553
@@ -1950,9 +2047,10 @@
rect 83152 622007 133410 624630
rect 133410 622007 133488 624630
rect 82973 617893 133488 622007
-rect 156376 620709 156500 624087
-rect 156500 620709 206836 624087
-rect 156376 619144 206836 620709
+rect 155884 620718 207581 620969
+rect 155884 618137 207402 620718
+rect 207402 618137 207581 620718
+rect 155884 617025 207581 618137
rect 259670 617074 275302 625270
rect 311280 617580 345358 624644
rect 380146 621915 380589 623908
@@ -2132,21 +2230,21 @@
rect 100463 432558 116619 583221
rect 124759 599200 126962 599322
rect 147647 599210 151189 672301
-rect 171295 661444 184887 673086
+rect 171295 660571 184887 673086
rect 216554 672994 216578 677841
rect 232215 673051 232247 677841
rect 259666 678175 275332 678276
rect 232215 672994 232239 673051
rect 216554 672970 232239 672994
-rect 157059 661420 197726 661444
-rect 157059 659472 157083 661420
-rect 197702 659472 197726 661420
-rect 157059 659448 197726 659472
-rect 156352 624096 206860 624111
-rect 156352 624087 207124 624096
-rect 156352 619144 156376 624087
-rect 206836 619144 207124 624087
-rect 156352 619120 207124 619144
+rect 157064 660547 192360 660571
+rect 157064 659483 157088 660547
+rect 192336 659483 192360 660547
+rect 157064 659459 192360 659483
+rect 171295 659368 184887 659459
+rect 155860 620969 207605 620993
+rect 155860 617025 155884 620969
+rect 207581 617025 207605 620969
+rect 155860 617001 207605 617025
rect 147647 599200 147711 599210
rect 124759 599176 147711 599200
rect 151098 599200 151189 599210
@@ -2154,7 +2252,7 @@
rect 151098 599176 154813 599200
rect 124759 583547 124862 599176
rect 154759 583547 154813 599176
-rect 172171 598949 188327 619120
+rect 172171 598949 188327 617001
rect 218723 615607 222084 672970
rect 259666 671893 260437 678175
rect 274962 671893 275332 678175
@@ -2895,7 +2993,7 @@
transform 1 0 38481 0 1 560871
box 0 -159 34500 6363
use top_pll_v1 top_pll_v1_0
-timestamp 1624402156
+timestamp 1624896651
transform 1 0 14782 0 1 657248
box -642 -33679 50180 2860
use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_0
@@ -2904,9 +3002,13 @@
transform 1 0 74005 0 1 616157
box -3351 -3261 3373 3261
use top_pll_v2 *top_pll_v2_0
-timestamp 1624402156
+timestamp 1624896651
transform -1 0 133068 0 1 657248
box -642 -33679 50180 2860
+use top_pll_v3 top_pll_v3_0
+timestamp 1624896651
+transform -1 0 206380 0 1 656706
+box -642 -37079 50180 2860
use mimcap_decoup_1x5 mimcap_decoup_1x5_1
array 0 0 34500 0 2 6522
timestamp 1624376995
@@ -2917,10 +3019,6 @@
timestamp 1624129585
transform 1 0 144463 0 1 616442
box -3351 -3261 3373 3261
-use top_pll_v1 *top_pll_v1_1
-timestamp 1624402156
-transform -1 0 206380 0 1 656706
-box -642 -33679 50180 2860
use sky130_fd_pr__cap_mim_m3_2_2Y8F6P sky130_fd_pr__cap_mim_m3_2_2Y8F6P_2
array 0 0 6724 0 6 6522
timestamp 1624129585
@@ -2946,7 +3044,7 @@
transform 1 0 291410 0 1 559700
box 0 -159 34500 6363
use res_amp_top res_amp_top_0 ~/caravel_analog_fulgor/mag/afernandez_residue_amplifier
-timestamp 1624402156
+timestamp 1624896651
transform 1 0 349695 0 1 630386
box -5005 -972 31038 12726
use mimcap_decoup_1x5 mimcap_decoup_1x5_4
diff --git a/xschem/simulations/tb_top_pll_v3_pex_c.spice b/xschem/simulations/tb_top_pll_v3_pex_c.spice
index 9175dd1..55ba19f 100644
--- a/xschem/simulations/tb_top_pll_v3_pex_c.spice
+++ b/xschem/simulations/tb_top_pll_v3_pex_c.spice
@@ -29,12 +29,12 @@
.param vd0 = 0.0
.param vd1 = 0.0
-.options TEMP = 0.0
+.options TEMP = 100.0
.options RSHUNT = 1e20
-.options GMIN = 1e-10
+*.options GMIN = 1e-10
* Models
-.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
.include ~/caravel_analog_fulgor/xschem/simulations/top_pll_v3_pex_c.spice
diff --git a/xschem/simulations/user_analog_project_wrapper.spice b/xschem/simulations/user_analog_project_wrapper.spice
index 464abdb..114e702 100644
--- a/xschem/simulations/user_analog_project_wrapper.spice
+++ b/xschem/simulations/user_analog_project_wrapper.spice
@@ -66,9 +66,6 @@
x3 iref_cp1 vssa1 vdda1 net43 net42 net36 net31 net35 io_analog[10] io_analog[8] net34 net37 net32
+ gpio_noesd[7] net41 net44 net38 net39 net33 net40 net50 net45 net57 net51 net53 net55 net54 net48 net49 net52
+ net47 net56 net46 net58 gpio_noesd[8] top_pll_v2
-x4 iref_cp0 vssa1 vdda1 net71 net70 net64 net59 net63 io_analog[10] io_analog[7] net62 net65 net60
-+ gpio_noesd[7] net69 net72 net66 net67 net61 net68 net78 net73 net85 net79 net81 net83 net82 net76 net77 net80
-+ net75 net84 net74 net86 top_pll_v1
XC1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=9 m=9
XC2 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=9 m=9
XC3 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=7 m=7
@@ -82,11 +79,15 @@
+ gpio_noesd[5] gpio_noesd[6] gpio_noesd[3] gpio_noesd[1] gpio_noesd[2] iref0 io_analog[4] iref1 iref2 iref3 iref4
+ res_amp_top
XC10 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=10 m=10
+x4 iref_cp0 vssa1 vdda1 net71 net70 net64 net60 net92 io_analog[10] net63 io_analog[7] net62 net65
++ net59 gpio_noesd[7] net69 net72 net66 net67 net68 net61 gpio_noesd[10] gpio_noesd[11] gpio_noesd[9] net78
++ net73 net91 net79 net75 net74 net76 net77 net81 net90 net89 net88 net87 net86 net85 net84 net83 net82
++ net80 gpio_noesd[8] top_pll_v3
**.ends
* expanding symbol: top_pll_v1.sym # of pins=34
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v1.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v1.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1.sch
.subckt top_pll_v1 iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
+ pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
+ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
@@ -140,8 +141,8 @@
* expanding symbol: bias.sym # of pins=12
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/bias.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/bias.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sch
.subckt bias vdd iref iref_0 iref_1 iref_2 iref_3 iref_4 iref_5 iref_6 iref_7 iref_8 iref_9
*.iopin iref
*.iopin vdd
@@ -225,8 +226,8 @@
* expanding symbol: top_pll_v2.sym # of pins=35
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v2.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v2.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v2.sch
.subckt top_pll_v2 iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
+ pfd_QB D0_vco lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
+ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
@@ -281,8 +282,8 @@
* expanding symbol: res_amp_top.sym # of pins=19
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_top.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_top.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_amp_top.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_amp_top.sch
.subckt res_amp_top avdd1p8 inp inn outp outn avss1p8 clkp iref_reg0 iref_reg1 iref_reg2 delay_reg0
+ delay_reg2 delay_reg1 iref0 clkn iref1 iref2 iref3 iref4
*.ipin inp
@@ -313,9 +314,74 @@
.ends
+* expanding symbol: top_pll_v3.sym # of pins=44
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v3.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v3.sch
+.subckt top_pll_v3 iref_cp vss vdd vco_out vco_vctrl Up pfd_QA out_to_buffer in_ref nUp out_to_pad
++ Down nDown pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch cp_nswitch pfd_reset s_0 MC s_1
++ out_by_2 out_to_div out_div n_out_by_2 n_out_div_2 out_div_2 n_out_buffer_div_2 out_buffer_div_2 n_clk_0 s1n
++ s0n clk_2_f clk_d clk_out_mux21 clk_5 clk_pre n_clk_1 clk_1 clk_0 lf_D0
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.ipin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.iopin out_to_buffer
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin out_div
+*.opin out_to_pad
+*.iopin clk_0
+*.iopin n_clk_0
+*.iopin clk_1
+*.iopin n_clk_1
+*.iopin clk_pre
+*.iopin clk_5
+*.iopin clk_out_mux21
+*.iopin clk_d
+*.iopin clk_2_f
+*.iopin s0n
+*.iopin s1n
+*.ipin MC
+*.ipin s_0
+*.ipin s_1
+*.ipin lf_D0
+x1 vss vdd pfd_QA in_ref out_div pfd_QB pfd_reset PFD
+x2 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface
+x3 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump
+x5 vdd vco_out vco_D0 vco_vctrl vss csvco
+x6 vdd vco_out out_to_buffer out_to_div vss out_first_buffer ring_osc_buffer
+x7 vdd out_to_pad out_to_buffer vss buffer_salida
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2
+x9 s1n s0n s_0 s_1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 out_div out_by_2 clk_5
++ clk_2_f n_out_by_2 clk_1 n_clk_1 freq_div
+x4 vss vco_vctrl lf_vc lf_D0 loop_filter_v2
+.ends
+
+
* expanding symbol: PFD.sym # of pins=7
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/PFD.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/PFD.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
.subckt PFD vss vdd Up A B Down Reset
*.iopin vdd
*.iopin vss
@@ -331,8 +397,8 @@
* expanding symbol: charge_pump.sym # of pins=11
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/charge_pump.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/charge_pump.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sch
.subckt charge_pump vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
*.iopin vss
*.iopin vdd
@@ -382,8 +448,8 @@
* expanding symbol: pfd_cp_interface.sym # of pins=8
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
.subckt pfd_cp_interface Up vdd QA nUp Down QB vss nDown
*.iopin vdd
*.iopin vss
@@ -403,8 +469,8 @@
* expanding symbol: loop_filter.sym # of pins=3
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sch
.subckt loop_filter vss in vc_pex
*.iopin in
*.iopin vss
@@ -418,8 +484,8 @@
* expanding symbol: csvco.sym # of pins=5
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sch
.subckt csvco vdd out D0 vctrl vss
*.ipin vctrl
*.iopin vss
@@ -439,8 +505,8 @@
* expanding symbol: ring_osc_buffer.sym # of pins=6
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
.subckt ring_osc_buffer vdd in_vco out_pad out_div vss o1
*.iopin vdd
*.iopin vss
@@ -455,8 +521,8 @@
* expanding symbol: div_by_5.sym # of pins=10
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_5.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_5.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
.subckt div_by_5 vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
*.iopin vdd
*.iopin vss
@@ -480,8 +546,8 @@
* expanding symbol: div_by_2.sym # of pins=9
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_2.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_2.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
.subckt div_by_2 nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
*.ipin CLK
*.opin CLK_2
@@ -502,8 +568,8 @@
* expanding symbol: buffer_salida.sym # of pins=4
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_salida.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_salida.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sch
.subckt buffer_salida vdd out in vss
*.iopin vss
*.ipin in
@@ -531,8 +597,8 @@
* expanding symbol: loop_filter_v2.sym # of pins=4
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter_v2.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter_v2.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter_v2.sch
.subckt loop_filter_v2 vss in vc_pex D0_cap
*.iopin in
*.iopin vss
@@ -551,8 +617,8 @@
* expanding symbol: res_amp_lin_prog.sym # of pins=17
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin_prog.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin_prog.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_amp_lin_prog.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_amp_lin_prog.sch
.subckt res_amp_lin_prog avdd1p8 rst inp inn outp outn avss1p8 outp_cap outn_cap clk iref_reg0
+ iref_reg1 iref_reg2 delay_reg0 delay_reg2 delay_reg1 iref
*.ipin clk
@@ -598,8 +664,8 @@
* expanding symbol: res_amp_sync_v2.sym # of pins=6
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_sync_v2.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_sync_v2.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_amp_sync_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_amp_sync_v2.sch
.subckt res_amp_sync_v2 avdd1p8 clkp clkn avss1p8 clk_amp rst
*.ipin clkn
*.ipin clkp
@@ -624,8 +690,8 @@
* expanding symbol: source_follower_buff_diff.sym # of pins=10
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_diff.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_diff.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/source_follower_buff_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/source_follower_buff_diff.sch
.subckt source_follower_buff_diff avdd1p8 iref1 inp outp avss1p8 inn outn iref2 iref3 iref4
*.iopin avdd1p8
*.iopin avss1p8
@@ -644,9 +710,46 @@
.ends
+* expanding symbol: freq_div.sym # of pins=19
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/freq_div.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/freq_div.sch
+.subckt freq_div s_1_n s_0_n s_0 s_1 MC clk_0 clk_pre vss vdd clk_out_mux21 clk_d n_clk_0 out in_a
++ clk_5 clk_2 in_b clk_1 n_clk_1
+*.ipin s_0
+*.iopin vdd
+*.iopin vss
+*.ipin in_a
+*.ipin in_b
+*.opin out
+*.ipin MC
+*.ipin s_1
+*.iopin clk_0
+*.iopin n_clk_0
+*.iopin clk_1
+*.iopin n_clk_1
+*.iopin clk_pre
+*.iopin clk_5
+*.iopin clk_out_mux21
+*.iopin clk_d
+*.iopin clk_2
+*.iopin s_0_n
+*.iopin s_1_n
+x2 vdd clk_pre clk_0 n_clk_0 vss MC net2 net1 net3 net4 prescaler_23
+x3 net14 vss clk_out_mux21 vdd clk_2 net5 net6 net7 net8 div_by_2
+x4 vdd clk_5 clk_1 vss n_clk_1 net9 net10 net12 net13 net11 div_by_5
+x9 vdd s_0_n s_0 vss inverter_min_x2
+x1 vdd vss in_a in_b n_clk_0 clk_0 s_0 n_clk_1 clk_1 s_0_n mux2to4
+x6 vdd vss clk_out_mux21 clk_pre s_0 clk_5 s_0_n mux2to1
+x5 vdd vss out clk_d s_1 clk_2 s_1_n mux2to1
+x7 vdd s_1_n s_1 vss inverter_min_x2
+x8 vdd net15 clk_out_mux21 vss inverter_min_x2
+x10 vdd clk_d net15 vss inverter_min_x4
+.ends
+
+
* expanding symbol: DFF.sym # of pins=5
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/DFF.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/DFF.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
.subckt DFF D CLK Q Reset vss
*.ipin D
*.ipin CLK
@@ -661,8 +764,8 @@
* expanding symbol: and_pfd.sym # of pins=5
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/and_pfd.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/and_pfd.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
.subckt and_pfd vdd out A B vss
*.iopin vdd
*.iopin vss
@@ -697,8 +800,8 @@
* expanding symbol: trans_gate.sym # of pins=4
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/trans_gate.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/trans_gate.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
.subckt trans_gate vdd out in vss
*.iopin vss
*.ipin in
@@ -714,8 +817,8 @@
* expanding symbol: inverter_cp_x1.sym # of pins=4
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
.subckt inverter_cp_x1 vdd out in vss
*.iopin vss
*.ipin in
@@ -731,8 +834,8 @@
* expanding symbol: inverter_cp_x2.sym # of pins=4
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
.subckt inverter_cp_x2 vdd out in vss
*.iopin vss
*.ipin in
@@ -748,19 +851,19 @@
* expanding symbol: res_loop_filter.sym # of pins=3
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_loop_filter.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_loop_filter.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sch
.subckt res_loop_filter in out vss
*.iopin in
*.iopin vss
*.iopin out
-XR3 out in vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 L=22.92 mult=1 m=1
.ends
* expanding symbol: cap1_loop_filter.sym # of pins=2
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
.subckt cap1_loop_filter in out
*.iopin in
*.iopin out
@@ -769,8 +872,8 @@
* expanding symbol: cap2_loop_filter.sym # of pins=2
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
.subckt cap2_loop_filter in out
*.iopin in
*.iopin out
@@ -779,8 +882,8 @@
* expanding symbol: csvco_branch.sym # of pins=7
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco_branch.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco_branch.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sch
.subckt csvco_branch vdd vbp in out vctrl vss D0
*.ipin vctrl
*.ipin vbp
@@ -804,8 +907,8 @@
* expanding symbol: inverter_min_x2.sym # of pins=4
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x2.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
.subckt inverter_min_x2 vdd out in vss
*.iopin vss
*.ipin in
@@ -821,8 +924,8 @@
* expanding symbol: inverter_min_x4.sym # of pins=4
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x4.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
.subckt inverter_min_x4 vdd out in vss
*.iopin vss
*.ipin in
@@ -838,8 +941,8 @@
* expanding symbol: DFlipFlop.sym # of pins=7
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/DFlipFlop.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/DFlipFlop.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
.subckt DFlipFlop vdd Q nQ vss D CLK nCLK
*.iopin vdd
*.iopin vss
@@ -855,8 +958,8 @@
* expanding symbol: clock_inverter.sym # of pins=5
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/clock_inverter.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/clock_inverter.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
.subckt clock_inverter vdd CLK_d CLK nCLK_d vss
*.ipin CLK
*.iopin vdd
@@ -871,8 +974,8 @@
* expanding symbol: cap3_loop_filter.sym # of pins=2
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/cap3_loop_filter.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/cap3_loop_filter.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sch
.subckt cap3_loop_filter in out
*.iopin in
*.iopin out
@@ -881,8 +984,8 @@
* expanding symbol: delay_cell_buff.sym # of pins=7
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/delay_cell_buff.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/delay_cell_buff.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/delay_cell_buff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/delay_cell_buff.sch
.subckt delay_cell_buff avdd1p8 clk avss1p8 clk_out reg0 reg1 reg2
*.ipin clk
*.iopin avdd1p8
@@ -917,8 +1020,8 @@
* expanding symbol: res_amp_lin.sym # of pins=8
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_amp_lin.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_amp_lin.sch
.subckt res_amp_lin avdd1p8 clk inp inn outp outn avss1p8 vctrl
*.iopin avdd1p8
*.iopin avss1p8
@@ -950,8 +1053,8 @@
* expanding symbol: iref_ctrl_res_amp.sym # of pins=7
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sch
.subckt iref_ctrl_res_amp avdd1p8 iref avss1p8 vctrl reg0 reg1 reg2
*.iopin avdd1p8
*.iopin avss1p8
@@ -1000,8 +1103,8 @@
* expanding symbol: nand_logic.sym # of pins=5
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/nand_logic.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/nand_logic.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nand_logic.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nand_logic.sch
.subckt nand_logic avdd1p8 in1 out in2 avss1p8
*.ipin in1
*.ipin in2
@@ -1024,8 +1127,8 @@
* expanding symbol: inverter_min_x16.sym # of pins=4
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x16.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x16.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x16.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x16.sch
.subckt inverter_min_x16 vdd out in vss
*.iopin vss
*.ipin in
@@ -1041,8 +1144,8 @@
* expanding symbol: source_follower_buff_pmos.sym # of pins=5
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_pmos.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_pmos.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/source_follower_buff_pmos.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/source_follower_buff_pmos.sch
.subckt source_follower_buff_pmos avdd1p8 iref in out avss1p8
*.iopin avdd1p8
*.iopin avss1p8
@@ -1068,8 +1171,8 @@
* expanding symbol: source_follower_buff_nmos.sym # of pins=5
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_nmos.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_nmos.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/source_follower_buff_nmos.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/source_follower_buff_nmos.sch
.subckt source_follower_buff_nmos avdd1p8 iref in out avss1p8
*.iopin avdd1p8
*.iopin avss1p8
@@ -1091,9 +1194,70 @@
.ends
+* expanding symbol: prescaler_23.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/prescaler_23.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/prescaler_23.sch
+.subckt prescaler_23 vdd CLK_23 CLK nCLK vss MC Q1 nCLK_23 Q2 Q2_d
+*.iopin vdd
+*.ipin CLK
+*.ipin nCLK
+*.ipin MC
+*.iopin vss
+*.opin CLK_23
+*.iopin nCLK_23
+*.iopin Q1
+*.iopin Q2
+*.iopin Q2_d
+x3 nCLK_23 1 vss vss vdd vdd 2 sky130_fd_sc_hs__and2_1
+x4 Q1 MC vss vss vdd vdd 1 sky130_fd_sc_hs__or2_1
+x6 3 nCLK_23 MC vss vss vdd vdd CLK_23 sky130_fd_sc_hs__mux2_1
+x7 Q2 Q2_d vss vss vdd vdd 3 sky130_fd_sc_hs__or2_1
+x1 vdd Q1 net1 vss nCLK_23 CLK nCLK DFlipFlop
+x2 vdd Q2 nCLK_23 vss 2 CLK nCLK DFlipFlop
+x5 vdd Q2_d net2 vss Q2 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding symbol: mux2to4.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to4.sch
+.subckt mux2to4 vdd vss in_a in_b out_b_0 out_a_0 selec_0 out_b_1 out_a_1 selec_0_neg
+*.iopin in_a
+*.iopin in_b
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_b_0
+*.iopin out_b_1
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+x8 selec_0 out_b_1 in_b selec_0_neg vss vdd trans_gate_mux2to8
+x9 selec_0_neg out_b_0 in_b selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
+* expanding symbol: mux2to1.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/mux2to1.sch
+.subckt mux2to1 vdd vss in_a out_a_0 selec_0 out_a_1 selec_0_neg
+*.iopin in_a
+*.ipin selec_0_neg
+*.ipin selec_0
+*.iopin out_a_0
+*.iopin out_a_1
+*.iopin vdd
+*.iopin vss
+x4 selec_0 out_a_1 in_a selec_0_neg vss vdd trans_gate_mux2to8
+x5 selec_0_neg out_a_0 in_a selec_0 vss vdd trans_gate_mux2to8
+.ends
+
+
* expanding symbol: nor.sym # of pins=5
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/nor.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/nor.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
.subckt nor vdd A B out vss
*.ipin A
*.ipin B
@@ -1122,8 +1286,8 @@
* expanding symbol: inverter_csvco.sym # of pins=6
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_csvco.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_csvco.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
.subckt inverter_csvco vdd out in vss vbulkp vbulkn
*.iopin vss
*.ipin in
@@ -1141,8 +1305,8 @@
* expanding symbol: latch_diff.sym # of pins=7
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/latch_diff.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/latch_diff.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
.subckt latch_diff vdd nQ Q D nD CLK vss
*.iopin vdd
*.iopin vss
@@ -1170,8 +1334,8 @@
* expanding symbol: mux_2to1_logic.sym # of pins=6
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/mux_2to1_logic.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/mux_2to1_logic.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/mux_2to1_logic.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/mux_2to1_logic.sch
.subckt mux_2to1_logic avdd1p8 sel avss1p8 DinB out DinA
*.ipin DinB
*.ipin DinA
@@ -1196,8 +1360,8 @@
* expanding symbol: buffer_no_inv_x05.sym # of pins=4
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sch
.subckt buffer_no_inv_x05 avdd1p8 in avss1p8 out
*.ipin in
*.iopin avdd1p8
@@ -1208,9 +1372,28 @@
.ends
+* expanding symbol: trans_gate_mux2to8.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate_mux2to8.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate_mux2to8.sch
+.subckt trans_gate_mux2to8 en_pos out in en_neg vss vdd
+*.iopin en_neg
+*.ipin in
+*.opin out
+*.iopin en_pos
+*.iopin vdd
+*.iopin vss
+XM2 out en_neg in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+XM1 out en_pos in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3
+.ends
+
+
* expanding symbol: inverter_min.sym # of pins=4
-* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min.sym
-* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min.sch
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min.sch
.subckt inverter_min vdd out in vss
*.iopin vss
*.ipin in
diff --git a/xschem/tb_top_pll_v3_pex_c.sch b/xschem/tb_top_pll_v3_pex_c.sch
index 6b3f76e..3f6424c 100644
--- a/xschem/tb_top_pll_v3_pex_c.sch
+++ b/xschem/tb_top_pll_v3_pex_c.sch
@@ -122,12 +122,12 @@
.param vd0 = 0.0
.param vd1 = 0.0
-.options TEMP = 0.0
+.options TEMP = 100.0
.options RSHUNT = 1e20
-.options GMIN = 1e-10
+*.options GMIN = 1e-10
* Models
-.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
.include ~/caravel_analog_fulgor/xschem/simulations/top_pll_v3_pex_c.spice
diff --git a/xschem/top_pll_v3.sym b/xschem/top_pll_v3.sym
index 7c53df5..1954db1 100644
--- a/xschem/top_pll_v3.sym
+++ b/xschem/top_pll_v3.sym
@@ -117,7 +117,7 @@
B 5 -242.5 127.5 -237.5 132.5 {name=Down dir=inout }
B 5 -222.5 127.5 -217.5 132.5 {name=nDown dir=inout }
B 5 -322.5 127.5 -317.5 132.5 {name=pfd_QB dir=inout }
-B 5 -282.5 -132.5 -277.5 -127.5 {name=lf_D0 dir=in }
+B 5 -282.5 -132.5 -277.5 -127.5 {name=vco_D0 dir=in }
B 5 -102.5 127.5 -97.5 132.5 {name=lf_vc dir=inout }
B 5 -22.5 127.5 -17.5 132.5 {name=out_first_buffer dir=inout }
B 5 -142.5 127.5 -137.5 132.5 {name=cp_biasp dir=inout }
diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch
index 62d50fa..05843ce 100644
--- a/xschem/user_analog_project_wrapper.sch
+++ b/xschem/user_analog_project_wrapper.sch
@@ -151,69 +151,69 @@
N 5030 350 5070 350 { lab=io_analog[10]}
N 3950 -310 3990 -310 { lab=iref_cp1}
N 5340 150 5340 220 { lab=gpio_noesd[8]}
-N 6880 160 6880 220 { lab=vdda1}
-N 6940 160 6940 220 { lab=vssa1}
-N 6460 530 6460 580 { lab=#net59}
-N 6460 480 6460 530 { lab=#net59}
-N 6440 530 6440 580 { lab=#net60}
-N 6440 480 6440 530 { lab=#net60}
-N 6420 530 6420 580 { lab=#net61}
-N 6420 480 6420 530 { lab=#net61}
-N 6530 530 6530 580 { lab=#net62}
-N 6530 480 6530 530 { lab=#net62}
-N 6510 530 6510 580 { lab=#net63}
-N 6510 480 6510 530 { lab=#net63}
-N 6490 530 6490 580 { lab=#net64}
-N 6490 480 6490 530 { lab=#net64}
-N 6550 530 6550 580 { lab=#net65}
-N 6550 480 6550 530 { lab=#net65}
+N 7080 160 7080 220 { lab=vdda1}
+N 7120 160 7120 220 { lab=vssa1}
+N 6440 530 6440 580 { lab=#net59}
+N 6440 480 6440 530 { lab=#net59}
+N 6420 530 6420 580 { lab=#net60}
+N 6420 480 6420 530 { lab=#net60}
+N 6400 530 6400 580 { lab=#net61}
+N 6400 480 6400 530 { lab=#net61}
+N 6520 530 6520 580 { lab=#net62}
+N 6520 480 6520 530 { lab=#net62}
+N 6500 530 6500 580 { lab=#net63}
+N 6500 480 6500 530 { lab=#net63}
+N 6480 530 6480 580 { lab=#net64}
+N 6480 480 6480 530 { lab=#net64}
+N 6540 530 6540 580 { lab=#net65}
+N 6540 480 6540 530 { lab=#net65}
N 6620 530 6620 580 { lab=#net66}
N 6620 480 6620 530 { lab=#net66}
N 6600 530 6600 580 { lab=#net67}
N 6600 480 6600 530 { lab=#net67}
N 6580 530 6580 580 { lab=#net68}
N 6580 480 6580 530 { lab=#net68}
-N 6650 530 6650 580 { lab=#net69}
-N 6650 480 6650 530 { lab=#net69}
-N 6680 530 6680 580 { lab=#net70}
-N 6680 480 6680 530 { lab=#net70}
-N 6700 530 6700 580 { lab=#net71}
-N 6700 480 6700 530 { lab=#net71}
-N 6720 530 6720 580 { lab=#net72}
-N 6720 480 6720 530 { lab=#net72}
-N 6740 530 6740 580 { lab=#net73}
-N 6740 480 6740 530 { lab=#net73}
-N 6770 530 6770 580 { lab=#net74}
-N 6770 480 6770 530 { lab=#net74}
-N 6790 530 6790 580 { lab=#net75}
-N 6790 480 6790 530 { lab=#net75}
-N 6810 530 6810 580 { lab=#net76}
-N 6810 480 6810 530 { lab=#net76}
-N 6830 530 6830 580 { lab=#net77}
-N 6830 480 6830 530 { lab=#net77}
-N 6850 530 6850 580 { lab=#net78}
-N 6850 480 6850 530 { lab=#net78}
-N 6870 530 6870 580 { lab=#net79}
-N 6870 480 6870 530 { lab=#net79}
-N 6900 530 6900 580 { lab=#net80}
-N 6900 480 6900 530 { lab=#net80}
-N 6920 530 6920 580 { lab=#net81}
-N 6920 480 6920 530 { lab=#net81}
-N 6940 530 6940 580 { lab=#net82}
-N 6940 480 6940 530 { lab=#net82}
-N 6960 530 6960 580 { lab=#net83}
-N 6960 480 6960 530 { lab=#net83}
-N 6980 530 6980 580 { lab=#net84}
-N 6980 480 6980 530 { lab=#net84}
-N 7000 530 7000 580 { lab=#net85}
-N 7000 480 7000 530 { lab=#net85}
-N 7050 530 7050 580 { lab=#net86}
-N 7050 480 7050 530 { lab=#net86}
-N 7170 350 7220 350 { lab=io_analog[7]}
-N 7120 350 7170 350 { lab=io_analog[7]}
+N 6660 530 6660 580 { lab=#net69}
+N 6660 480 6660 530 { lab=#net69}
+N 6700 530 6700 580 { lab=#net70}
+N 6700 480 6700 530 { lab=#net70}
+N 6720 530 6720 580 { lab=#net71}
+N 6720 480 6720 530 { lab=#net71}
+N 6740 530 6740 580 { lab=#net72}
+N 6740 480 6740 530 { lab=#net72}
+N 6760 530 6760 580 { lab=#net73}
+N 6760 480 6760 530 { lab=#net73}
+N 6800 530 6800 580 { lab=#net74}
+N 6800 480 6800 530 { lab=#net74}
+N 6820 530 6820 580 { lab=#net75}
+N 6820 480 6820 530 { lab=#net75}
+N 6840 530 6840 580 { lab=#net76}
+N 6840 480 6840 530 { lab=#net76}
+N 6860 530 6860 580 { lab=#net77}
+N 6860 480 6860 530 { lab=#net77}
+N 6880 530 6880 580 { lab=#net78}
+N 6880 480 6880 530 { lab=#net78}
+N 6900 530 6900 580 { lab=#net79}
+N 6900 480 6900 530 { lab=#net79}
+N 6940 530 6940 580 { lab=#net80}
+N 6940 480 6940 530 { lab=#net80}
+N 6960 530 6960 580 { lab=#net81}
+N 6960 480 6960 530 { lab=#net81}
+N 6980 530 6980 580 { lab=#net82}
+N 6980 480 6980 530 { lab=#net82}
+N 7000 530 7000 580 { lab=#net83}
+N 7000 480 7000 530 { lab=#net83}
+N 7020 530 7020 580 { lab=#net84}
+N 7020 480 7020 530 { lab=#net84}
+N 7040 530 7040 580 { lab=#net85}
+N 7040 480 7040 530 { lab=#net85}
+N 7060 530 7060 580 { lab=#net86}
+N 7060 480 7060 530 { lab=#net86}
+N 7300 350 7350 350 { lab=io_analog[7]}
+N 7250 350 7300 350 { lab=io_analog[7]}
N 6290 350 6360 350 { lab=io_analog[10]}
N 6420 150 6420 220 { lab=iref_cp0}
-N 6500 150 6500 220 { lab=gpio_noesd[7]}
+N 6480 150 6480 220 { lab=gpio_noesd[7]}
N 6250 350 6290 350 { lab=io_analog[10]}
N 3950 -330 3990 -330 { lab=iref_cp0}
N 4540 -360 4540 -300 { lab=vdda1}
@@ -234,27 +234,43 @@
N 5600 -240 5600 -180 { lab=vssa1}
N 5750 -360 5750 -300 { lab=vdda1}
N 5750 -240 5750 -180 { lab=vssa1}
-N 6680 -510 6680 -460 { lab=vdda1}
-N 6720 -230 6720 -180 { lab=vssa1}
-N 6850 -350 6960 -350 { lab=io_analog[0]}
-N 6850 -370 6960 -370 { lab=io_analog[1]}
-N 6450 -410 6560 -410 { lab=io_analog[4]}
-N 6450 -430 6560 -430 { lab=io_analog[6]}
-N 6450 -350 6560 -350 { lab=io_analog[2]}
-N 6450 -370 6560 -370 { lab=io_analog[3]}
-N 6450 -280 6560 -280 { lab=iref2}
-N 6450 -300 6560 -300 { lab=iref0}
-N 6450 -270 6560 -270 { lab=iref3}
-N 6450 -290 6560 -290 { lab=iref1}
-N 6450 -260 6560 -260 { lab=iref4}
-N 6610 -230 6610 -120 { lab=gpio_noesd[6]}
-N 6630 -230 6630 -120 { lab=gpio_noesd[2]}
-N 6600 -230 6600 -120 { lab=gpio_noesd[5]}
-N 6620 -230 6620 -120 { lab=gpio_noesd[3]}
-N 6590 -230 6590 -120 { lab=gpio_noesd[4]}
-N 6640 -230 6640 -120 { lab=gpio_noesd[1]}
+N 6460 -580 6460 -530 { lab=vdda1}
+N 6500 -300 6500 -250 { lab=vssa1}
+N 6630 -420 6740 -420 { lab=io_analog[0]}
+N 6630 -440 6740 -440 { lab=io_analog[1]}
+N 6230 -480 6340 -480 { lab=io_analog[4]}
+N 6230 -500 6340 -500 { lab=io_analog[6]}
+N 6230 -420 6340 -420 { lab=io_analog[2]}
+N 6230 -440 6340 -440 { lab=io_analog[3]}
+N 6230 -350 6340 -350 { lab=iref2}
+N 6230 -370 6340 -370 { lab=iref0}
+N 6230 -340 6340 -340 { lab=iref3}
+N 6230 -360 6340 -360 { lab=iref1}
+N 6230 -330 6340 -330 { lab=iref4}
+N 6390 -300 6390 -190 { lab=gpio_noesd[6]}
+N 6410 -300 6410 -190 { lab=gpio_noesd[2]}
+N 6380 -300 6380 -190 { lab=gpio_noesd[5]}
+N 6400 -300 6400 -190 { lab=gpio_noesd[3]}
+N 6370 -300 6370 -190 { lab=gpio_noesd[4]}
+N 6420 -300 6420 -190 { lab=gpio_noesd[1]}
N 5880 -360 5880 -300 { lab=vdda1}
N 5880 -240 5880 -180 { lab=vssa1}
+N 7080 530 7080 580 { lab=#net80}
+N 7080 480 7080 530 { lab=#net80}
+N 7100 530 7100 580 { lab=#net81}
+N 7100 480 7100 530 { lab=#net81}
+N 7120 530 7120 580 { lab=#net82}
+N 7120 480 7120 530 { lab=#net82}
+N 7140 530 7140 580 { lab=#net83}
+N 7140 480 7140 530 { lab=#net83}
+N 7160 530 7160 580 { lab=#net84}
+N 7160 480 7160 530 { lab=#net84}
+N 7200 530 7200 580 { lab=#net84}
+N 7200 480 7200 530 { lab=#net84}
+N 6520 150 6520 220 { lab=gpio_noesd[8]}
+N 6570 150 6570 220 { lab=gpio_noesd[8]}
+N 6600 150 6600 220 { lab=gpio_noesd[8]}
+N 6630 150 6630 220 { lab=gpio_noesd[8]}
C {iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
C {iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
C {iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
@@ -365,41 +381,40 @@
C {lab_pin.sym} 3990 -310 2 0 {name=l81 sig_type=std_logic lab=iref_cp1}
C {top_pll_v2.sym} 5490 350 0 0 {name=x3}
C {lab_pin.sym} 5340 150 3 1 {name=l47 sig_type=std_logic lab=gpio_noesd[8]}
-C {top_pll_v1.sym} 6710 350 0 0 {name=x4}
-C {lab_pin.sym} 6880 160 1 0 {name=l82 sig_type=std_logic lab=vdda1}
-C {lab_pin.sym} 6940 160 1 0 {name=l83 sig_type=std_logic lab=vssa1}
-C {noconn.sym} 6460 580 3 0 {name=l84}
-C {noconn.sym} 6440 580 3 0 {name=l85}
-C {noconn.sym} 6420 580 3 0 {name=l86}
-C {noconn.sym} 6530 580 3 0 {name=l87}
-C {noconn.sym} 6510 580 3 0 {name=l88}
-C {noconn.sym} 6490 580 3 0 {name=l89}
-C {noconn.sym} 6550 580 3 0 {name=l90}
+C {lab_pin.sym} 7080 160 1 0 {name=l82 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 7120 160 1 0 {name=l83 sig_type=std_logic lab=vssa1}
+C {noconn.sym} 6440 580 3 0 {name=l84}
+C {noconn.sym} 6420 580 3 0 {name=l85}
+C {noconn.sym} 6400 580 3 0 {name=l86}
+C {noconn.sym} 6520 580 3 0 {name=l87}
+C {noconn.sym} 6500 580 3 0 {name=l88}
+C {noconn.sym} 6480 580 3 0 {name=l89}
+C {noconn.sym} 6540 580 3 0 {name=l90}
C {noconn.sym} 6620 580 3 0 {name=l91}
C {noconn.sym} 6600 580 3 0 {name=l92}
C {noconn.sym} 6580 580 3 0 {name=l93}
-C {noconn.sym} 6650 580 3 0 {name=l94}
-C {noconn.sym} 6680 580 3 0 {name=l95}
-C {noconn.sym} 6700 580 3 0 {name=l96}
-C {noconn.sym} 6720 580 3 0 {name=l97}
-C {noconn.sym} 6740 580 3 0 {name=l98}
-C {noconn.sym} 6770 580 3 0 {name=l99}
-C {noconn.sym} 6790 580 3 0 {name=l100}
-C {noconn.sym} 6810 580 3 0 {name=l101}
-C {noconn.sym} 6830 580 3 0 {name=l102}
-C {noconn.sym} 6850 580 3 0 {name=l103}
-C {noconn.sym} 6870 580 3 0 {name=l104}
-C {noconn.sym} 6900 580 3 0 {name=l105}
-C {noconn.sym} 6920 580 3 0 {name=l106}
-C {noconn.sym} 6940 580 3 0 {name=l107}
-C {noconn.sym} 6960 580 3 0 {name=l108}
-C {noconn.sym} 6980 580 3 0 {name=l109}
-C {noconn.sym} 7000 580 3 0 {name=l110}
-C {noconn.sym} 7050 580 3 0 {name=l111}
+C {noconn.sym} 6660 580 3 0 {name=l94}
+C {noconn.sym} 6700 580 3 0 {name=l95}
+C {noconn.sym} 6720 580 3 0 {name=l96}
+C {noconn.sym} 6740 580 3 0 {name=l97}
+C {noconn.sym} 6760 580 3 0 {name=l98}
+C {noconn.sym} 6800 580 3 0 {name=l99}
+C {noconn.sym} 6820 580 3 0 {name=l100}
+C {noconn.sym} 6840 580 3 0 {name=l101}
+C {noconn.sym} 6860 580 3 0 {name=l102}
+C {noconn.sym} 6880 580 3 0 {name=l103}
+C {noconn.sym} 6900 580 3 0 {name=l104}
+C {noconn.sym} 6940 580 3 0 {name=l105}
+C {noconn.sym} 6960 580 3 0 {name=l106}
+C {noconn.sym} 6980 580 3 0 {name=l107}
+C {noconn.sym} 7000 580 3 0 {name=l108}
+C {noconn.sym} 7020 580 3 0 {name=l109}
+C {noconn.sym} 7040 580 3 0 {name=l110}
+C {noconn.sym} 7060 580 3 0 {name=l111}
C {lab_pin.sym} 6420 150 1 0 {name=l112 sig_type=std_logic lab=iref_cp0}
C {lab_pin.sym} 6250 350 0 0 {name=l113 sig_type=std_logic lab=io_analog[10]}
-C {lab_pin.sym} 7220 350 2 0 {name=l114 sig_type=std_logic lab=io_analog[7]}
-C {lab_pin.sym} 6500 150 3 1 {name=l115 sig_type=std_logic lab=gpio_noesd[7]}
+C {lab_pin.sym} 7350 350 2 0 {name=l114 sig_type=std_logic lab=io_analog[7]}
+C {lab_pin.sym} 6480 150 3 1 {name=l115 sig_type=std_logic lab=gpio_noesd[7]}
C {lab_pin.sym} 3990 -330 2 0 {name=l46 sig_type=std_logic lab=iref_cp0}
C {sky130_fd_pr/cap_mim_m3_2.sym} 4540 -270 0 0 {name=C1 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X}
C {lab_pin.sym} 4540 -360 1 0 {name=l116 sig_type=std_logic lab=vdda1}
@@ -428,31 +443,42 @@
C {sky130_fd_pr/cap_mim_m3_2.sym} 5750 -270 0 0 {name=C9 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
C {lab_pin.sym} 5750 -360 1 0 {name=l132 sig_type=std_logic lab=vdda1}
C {lab_pin.sym} 5750 -180 3 0 {name=l133 sig_type=std_logic lab=vssa1}
-C {lab_pin.sym} 6680 -490 2 0 {name=l134 sig_type=std_logic lab=vdda1}
-C {lab_pin.sym} 6720 -190 2 0 {name=l135 sig_type=std_logic lab=vssa1}
-C {res_amp_top.sym} 6730 -190 0 0 {name=x5}
-C {lab_pin.sym} 6960 -370 2 0 {name=l136 sig_type=std_logic lab=io_analog[1]}
-C {lab_pin.sym} 6960 -350 2 0 {name=l137 sig_type=std_logic lab=io_analog[0]}
-C {lab_pin.sym} 6450 -410 0 0 {name=l138 sig_type=std_logic lab=io_analog[4]}
-C {lab_pin.sym} 6450 -430 0 0 {name=l139 sig_type=std_logic lab=io_analog[6]}
-C {lab_pin.sym} 6450 -350 0 0 {name=l140 sig_type=std_logic lab=io_analog[2]}
-C {lab_pin.sym} 6450 -370 0 0 {name=l141 sig_type=std_logic lab=io_analog[3]}
+C {lab_pin.sym} 6460 -560 2 0 {name=l134 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 6500 -260 2 0 {name=l135 sig_type=std_logic lab=vssa1}
+C {res_amp_top.sym} 6510 -260 0 0 {name=x5}
+C {lab_pin.sym} 6740 -440 2 0 {name=l136 sig_type=std_logic lab=io_analog[1]}
+C {lab_pin.sym} 6740 -420 2 0 {name=l137 sig_type=std_logic lab=io_analog[0]}
+C {lab_pin.sym} 6230 -480 0 0 {name=l138 sig_type=std_logic lab=io_analog[4]}
+C {lab_pin.sym} 6230 -500 0 0 {name=l139 sig_type=std_logic lab=io_analog[6]}
+C {lab_pin.sym} 6230 -420 0 0 {name=l140 sig_type=std_logic lab=io_analog[2]}
+C {lab_pin.sym} 6230 -440 0 0 {name=l141 sig_type=std_logic lab=io_analog[3]}
C {lab_pin.sym} 4050 -150 2 0 {name=l50 sig_type=std_logic lab=iref0}
C {lab_pin.sym} 4050 -170 2 0 {name=l51 sig_type=std_logic lab=iref1}
C {lab_pin.sym} 4050 -190 2 0 {name=l52 sig_type=std_logic lab=iref3}
C {lab_pin.sym} 4050 -210 2 0 {name=l53 sig_type=std_logic lab=iref2}
C {lab_pin.sym} 4050 -230 2 0 {name=l54 sig_type=std_logic lab=iref4}
-C {lab_pin.sym} 6450 -280 0 0 {name=l142 sig_type=std_logic lab=iref2}
-C {lab_pin.sym} 6450 -300 0 0 {name=l143 sig_type=std_logic lab=iref0}
-C {lab_pin.sym} 6450 -270 0 0 {name=l144 sig_type=std_logic lab=iref3}
-C {lab_pin.sym} 6450 -290 0 0 {name=l145 sig_type=std_logic lab=iref1}
-C {lab_pin.sym} 6450 -260 0 0 {name=l146 sig_type=std_logic lab=iref4}
-C {lab_pin.sym} 6610 -120 3 0 {name=l147 sig_type=std_logic lab=gpio_noesd[6]}
-C {lab_pin.sym} 6600 -120 3 0 {name=l148 sig_type=std_logic lab=gpio_noesd[5]}
-C {lab_pin.sym} 6590 -120 3 0 {name=l149 sig_type=std_logic lab=gpio_noesd[4]}
-C {lab_pin.sym} 6640 -120 3 0 {name=l150 sig_type=std_logic lab=gpio_noesd[1]}
-C {lab_pin.sym} 6630 -120 3 0 {name=l151 sig_type=std_logic lab=gpio_noesd[2]}
-C {lab_pin.sym} 6620 -120 3 0 {name=l152 sig_type=std_logic lab=gpio_noesd[3]}
+C {lab_pin.sym} 6230 -350 0 0 {name=l142 sig_type=std_logic lab=iref2}
+C {lab_pin.sym} 6230 -370 0 0 {name=l143 sig_type=std_logic lab=iref0}
+C {lab_pin.sym} 6230 -340 0 0 {name=l144 sig_type=std_logic lab=iref3}
+C {lab_pin.sym} 6230 -360 0 0 {name=l145 sig_type=std_logic lab=iref1}
+C {lab_pin.sym} 6230 -330 0 0 {name=l146 sig_type=std_logic lab=iref4}
+C {lab_pin.sym} 6390 -190 3 0 {name=l147 sig_type=std_logic lab=gpio_noesd[6]}
+C {lab_pin.sym} 6380 -190 3 0 {name=l148 sig_type=std_logic lab=gpio_noesd[5]}
+C {lab_pin.sym} 6370 -190 3 0 {name=l149 sig_type=std_logic lab=gpio_noesd[4]}
+C {lab_pin.sym} 6420 -190 3 0 {name=l150 sig_type=std_logic lab=gpio_noesd[1]}
+C {lab_pin.sym} 6410 -190 3 0 {name=l151 sig_type=std_logic lab=gpio_noesd[2]}
+C {lab_pin.sym} 6400 -190 3 0 {name=l152 sig_type=std_logic lab=gpio_noesd[3]}
C {sky130_fd_pr/cap_mim_m3_2.sym} 5880 -270 0 0 {name=C10 model=cap_mim_m3_2 W=30 L=30 MF=10 spiceprefix=X}
C {lab_pin.sym} 5880 -360 1 0 {name=l153 sig_type=std_logic lab=vdda1}
C {lab_pin.sym} 5880 -180 3 0 {name=l154 sig_type=std_logic lab=vssa1}
+C {top_pll_v3.sym} 6760 350 0 0 {name=x4}
+C {noconn.sym} 7080 580 3 0 {name=l155}
+C {noconn.sym} 7100 580 3 0 {name=l156}
+C {noconn.sym} 7120 580 3 0 {name=l157}
+C {noconn.sym} 7140 580 3 0 {name=l158}
+C {noconn.sym} 7160 580 3 0 {name=l159}
+C {noconn.sym} 7200 580 3 0 {name=l160}
+C {lab_pin.sym} 6520 150 3 1 {name=l161 sig_type=std_logic lab=gpio_noesd[8]}
+C {lab_pin.sym} 6570 150 3 1 {name=l162 sig_type=std_logic lab=gpio_noesd[9]}
+C {lab_pin.sym} 6600 150 3 1 {name=l163 sig_type=std_logic lab=gpio_noesd[10]}
+C {lab_pin.sym} 6630 150 3 1 {name=l164 sig_type=std_logic lab=gpio_noesd[11]}
