commit: 7c3c72cc7ece13f0caece471149d1c9a6a6f8ef0
[log] [tgz]
author: Klas Nordmark <klas.nordmark.se@ieee.org>
Wed May 19 14:50:08 2021 +0200
committer: Klas Nordmark <klas.nordmark.se@ieee.org>
Wed May 19 14:50:55 2021 +0200
tree: 41da6ee4c7d2e9de8a6b4f0f13e5348fc57fc93f
parent: d3e050539b229d532a45c37a645482e081e344cc [diff]

Added files needed to build user_project_wrapper with subservient_wrapped

gds/subservient_wrapped.gds[Added - diff]
lef/subservient_wrapped.lef[Added - diff]
openlane/user_project_wrapper/config.tcl[diff]
verilog/gl/subservient_wrapped.v[Added - diff]
verilog/rtl/ff_ram.v[Added - diff]
verilog/rtl/serv_alu.v[Added - diff]
verilog/rtl/serv_bufreg.v[Added - diff]
verilog/rtl/serv_csr.v[Added - diff]
verilog/rtl/serv_ctrl.v[Added - diff]
verilog/rtl/serv_decode.v[Added - diff]
verilog/rtl/serv_immdec.v[Added - diff]
verilog/rtl/serv_mem_if.v[Added - diff]
verilog/rtl/serv_rf_if.v[Added - diff]
verilog/rtl/serv_rf_ram.v[Added - diff]
verilog/rtl/serv_rf_ram_if.v[Added - diff]
verilog/rtl/serv_rf_top.v[Added - diff]
verilog/rtl/serv_state.v[Added - diff]
verilog/rtl/serv_top.v[Added - diff]
verilog/rtl/serving.v[Added - diff]
verilog/rtl/serving_arbiter.v[Added - diff]
verilog/rtl/serving_mux.v[Added - diff]
verilog/rtl/serving_ram.v[Added - diff]
verilog/rtl/subservient.v[Added - diff]
verilog/rtl/subservient_core.v[Added - diff]
verilog/rtl/subservient_debug_switch.v[Added - diff]
verilog/rtl/subservient_gpio.v[Added - diff]
verilog/rtl/subservient_ram.v[Added - diff]
verilog/rtl/subservient_rf_ram_if.v[Added - diff]
verilog/rtl/subservient_top.v[Added - diff]
verilog/rtl/subservient_wrapped.v[Added - diff]
verilog/rtl/user_project_wrapper.v[diff]

31 files changed

tree: 41da6ee4c7d2e9de8a6b4f0f13e5348fc57fc93f

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.