Merge branch 'main' of https://github.com/efabless/caravel_user_project into makefile_fixes
diff --git a/README.md b/README.md
index 242bb9b..b25eab7 100644
--- a/README.md
+++ b/README.md
@@ -9,4 +9,4 @@
---
-Refer to [README](docs/source/README.md) for this sample project documentation.
+Refer to [README](docs/source/index.rst) for this sample project documentation.
diff --git a/caravel b/caravel
index 11aa3dd..e80f0ac 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit 11aa3dd76bedd31270dc4b00aea8d3ed20a7970c
+Subproject commit e80f0ac8b6f74eeed0c81668728e033adba4fa16
diff --git a/docs/source/index.rst b/docs/source/index.rst
index 83f8f0a..76f0c39 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -60,7 +60,9 @@
# By default, CARAVEL_ROOT is set to $(pwd)/caravel
# If you want to install caravel at a different location, run "export CARAVEL_ROOT=<caravel-path>"
# Disable submodule installation if needed by, run "export SUBMODULE=0"
-
+
+ clone https://github.com/efabless/caravel_user_project.git
+ cd caravel_user_project
make install
To update the installed caravel to the latest, run:
@@ -266,4 +268,4 @@
.. |User CI| image:: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg
:target: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml
.. |Caravel Build| image:: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg
- :target: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml
\ No newline at end of file
+ :target: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
index 94286b8..1a834f7 100644
--- a/verilog/dv/README.md
+++ b/verilog/dv/README.md
@@ -141,7 +141,7 @@
reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
```
-* Then, the firmware applies the pad configuration by enabling the serial transfer on the shift register responsible for configuring the pads and waits till the transfer is done.
+* Then, the firmware applies the pad configuration by enabling the serial transfer on the shift register responsible for configuring the pads and waits until the transfer is done.
```c
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
@@ -161,7 +161,7 @@
### Logic Analyzer Test 1
-* This test is meant to verify that we can use the logic analyzer to monitor and write signals in the user project from the management SoC. Firstly, the firmware configures the upper 16 pads as outputs from the managent SoC, applies the configuration by initiating the serial transfer on the shift register, and writes a value on the pads to indicate the end of pad configuration and the start of the test.
+* This test is meant to verify that we can use the logic analyzer to monitor and write signals in the user project from the management SoC. Firstly, the firmware configures the upper 16 of the first 32 GPIO pads as outputs from the managent SoC, applies the configuration by initiating the serial transfer on the shift register, and writes a value on the pads to indicate the end of pad configuration and the start of the test.
```c
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
@@ -176,29 +176,29 @@
reg_mprj_datal = 0xAB400000;
```
- This is done to flag the start/success/end of the simulation by writing a certain value to the I/Os which is then checked by the testbench to know whether the test started/ended/succeeded. For example, the testbench checks on the value of the upper 16 I/Os, if it is equal to `16'hAB40`, then we know that the test started.
+ This is done to flag the start/success/end of the simulation by writing a certain value to the I/Os which is then checked by the testbench to know whether the test started/ended/succeeded. For example, the testbench checks on the value of the upper 16 of 32 I/Os, if it is equal to `16'hAB40`, then we know that the test started.
```verilog
wait(checkbits == 16'hAB40);
$display("LA Test 1 started");
```
-* Then, the firmware configures the logic analyzer (LA) probes `[31:0]` as inputs to the management SoC to monitor the counter value, and configure the logic analyzer probes `[63:32]` as outputs from the management SoC (inputs to the user_proj_example) to set the counter initial value. This is done by writing to the LA probes enable registers.
+* Then, the firmware configures the logic analyzer (LA) probes `[31:0]` as inputs to the management SoC to monitor the counter value, and configure the logic analyzer probes `[63:32]` as outputs from the management SoC (inputs to the user_proj_example) to set the counter initial value. This is done by writing to the LA probes enable registers. Note that the output enable is active low, while the input enable is active high. Every channel can be configured for input, output, or both independently.
```c
- reg_la0_ena = 0xFFFFFFFF; // [31:0] inputs to mgmt_soc
- reg_la1_ena = 0x00000000; // [63:32] outputs from mgmt_soc
+ reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] inputs to mgmt_soc
+ reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32] outputs from mgmt_soc
```
* Then, the firmware writes an initial value to the counter through the LA1 data register. Afte writing the counter value, the LA probes are disabled to prevent the counter write signal from being always set to one.
```c
reg_la1_data = 0x00000000; // Write zero to count register
- reg_la1_ena = 0xFFFFFFFF; // Disable probes
+ reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // Disable probes
```
-* The firmware then waits till the count value exceeds 500 and flags the success of the test by writing `0xAB41` to the upper 16 pads. The firmware reads the count value through the logic analyzer probes `[31:0]`
+* The firmware then waits until the count value exceeds 500 and flags the success of the test by writing `0xAB41` to pads 16 to 31. The firmware reads the count value through the logic analyzer probes `[31:0]`
```c
if (reg_la0_data > 0x1F4) { // Read current count value through LA
@@ -212,7 +212,7 @@
* This test is meant to verify that we can drive the clock and reset signals for the user project example through the logic analyzer. In the [user_proj_example](verilog/rtl/user_proj_example.v) RTL, the clock can either be supplied from the `wb_clk_i` or from the logic analyzer through bit `[64]`. Similarly, the reset signal can be supplied from the `wb_rst_i` or through `LA[65]`. The firmware configures the clk and reset LA probes as outputs from the management SoC by writing to the LA2 enable register.
```c
- reg_la2_ena = 0xFFFFFFFC; // Configure LA[64] LA[65] as outputs from the cpu
+ reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC; // Configure LA[64] LA[65] as outputs from the cpu
```
* Then, the firmware supplies both clock reset signals through LA2 data register. First, both are set to one. Then, reset is driven to zero and the clock is toggled for 6 clock cycles.
diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c
index b77c8d5..220bdfe 100644
--- a/verilog/dv/la_test1/la_test1.c
+++ b/verilog/dv/la_test1/la_test1.c
@@ -97,10 +97,10 @@
// Configure LA probes [31:0], [127:64] as inputs to the cpu
// Configure LA probes [63:32] as outputs from the cpu
- reg_la0_ena = 0xFFFFFFFF; // [31:0]
- reg_la1_ena = 0x00000000; // [63:32]
- reg_la2_ena = 0xFFFFFFFF; // [95:64]
- reg_la3_ena = 0xFFFFFFFF; // [127:96]
+ reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
// Flag start of the test
reg_mprj_datal = 0xAB400000;
@@ -109,7 +109,7 @@
reg_la1_data = 0x00000000;
// Configure LA probes from [63:32] as inputs to disable counter write
- reg_la1_ena = 0xFFFFFFFF;
+ reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;
while (1) {
if (reg_la0_data > 0x1F4) {
diff --git a/verilog/dv/la_test2/la_test2.c b/verilog/dv/la_test2/la_test2.c
index 1b8a383..f9a293c 100644
--- a/verilog/dv/la_test2/la_test2.c
+++ b/verilog/dv/la_test2/la_test2.c
@@ -83,16 +83,16 @@
while (reg_mprj_xfer == 1);
// Configure All LA probes as inputs to the cpu
- reg_la0_ena = 0xFFFFFFFF; // [31:0]
- reg_la1_ena = 0xFFFFFFFF; // [63:32]
- reg_la2_ena = 0xFFFFFFFF; // [95:64]
- reg_la3_ena = 0xFFFFFFFF; // [127:96]
+ reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
// Flag start of the test
reg_mprj_datal = 0xAB600000;
// Configure LA[64] LA[65] as outputs from the cpu
- reg_la2_ena = 0xFFFFFFFC;
+ reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;
// Set clk & reset to one
reg_la2_data = 0x00000003;
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
index 2fae0f1..e4d0a2d 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus.c
@@ -97,10 +97,10 @@
// Configure LA probes [31:0], [127:64] as inputs to the cpu
// Configure LA probes [63:32] as outputs from the cpu
- reg_la0_ena = 0xFFFFFFFF; // [31:0]
- reg_la1_ena = 0x00000000; // [63:32]
- reg_la2_ena = 0xFFFFFFFF; // [95:64]
- reg_la3_ena = 0xFFFFFFFF; // [127:96]
+ reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
// Flag start of the test
reg_mprj_datal = 0xAB400000;
@@ -109,7 +109,7 @@
reg_la1_data = 0x00000000;
// Configure LA probes from [63:32] as inputs to disable counter write
- reg_la1_ena = 0xFFFFFFFF;
+ reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;
reg_mprj_datal = 0xAB410000;
reg_mprj_datah = 0x00000000;
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 46d7783..6c8129d 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -75,7 +75,7 @@
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
- reg_la2_ena = 0xFFFFFFFF; // [95:64]
+ reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
// Flag start of the test
reg_mprj_datal = 0xAB600000;
@@ -86,4 +86,4 @@
} else {
reg_mprj_datal = 0xAB600000;
}
-}
\ No newline at end of file
+}
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index b949583..b33e032 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -64,7 +64,7 @@
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
- input [127:0] la_oen,
+ input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
@@ -105,10 +105,10 @@
// LA
assign la_data_out = {{(127-BITS){1'b0}}, count};
// Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
+ assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
// Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
+ assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+ assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
counter #(
.BITS(BITS)
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 17c2511..2a3462b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -58,7 +58,7 @@
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
- input [127:0] la_oen,
+ input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
@@ -112,7 +112,7 @@
.la_data_in(la_data_in),
.la_data_out(la_data_out),
- .la_oen (la_oen),
+ .la_oenb (la_oenb),
// IO Pads
