|author||Jeff DiCorpo <email@example.com>||Tue Dec 28 01:19:20 2021 +0000|
|committer||Jeff DiCorpo <firstname.lastname@example.org>||Tue Dec 28 01:19:20 2021 +0000|
final gds & signoff results
This project constists of an ASIC-adapted version of the award-winning bit-serial RISC-V processor SERV. The macro was built from the subservient_wrapped repository linked later, which combines Subservient with 512 bytes of RAM (generated from RTL, as no satisfactory memory compiler was available in good time), used both as main memory and register file. For more information on subservient_wrapped, subservient and SERV, the original repositories can be accessed below. The repositories depend on each other through the Fusesoc packet management and tool abstraction system - this project was created to demonstrate Fusesoc in an ASIC context.
Subservient has access to the outside world through io_out. To access it from the Caravel management processor (which is how you would program Subservient), keep it in “debug” mode by holding la_data_in low. In this state, the 512 byte memory is accessible by the Caravel management processor over the Wishbone interface and Subservient does not run. The subservient_blinky full chip test included under verilog/dv gives an example of this, programming Subservient with a small ‘blink’ program toggling io_out.