commit	83e985d0950b6d2a5c2945f05e1bf44ee663e695	[log] [tgz]
author	jaquerinte <ivanrodriguezferrandez@gmail.com>	Mon Jun 07 17:02:36 2021 +0200
committer	jaquerinte <ivanrodriguezferrandez@gmail.com>	Mon Jun 07 17:02:36 2021 +0200
tree	594a05f3eaeae01ca3ecd8b34da3e3e880ed5484
parent	423cfa174066b34283f1608fb32bed2f85525e33 [diff]

version 2.0 of the chip

.gitignore[diff]
def/user_proj_example.def[diff]
def/user_project_wrapper.def[diff]
gds/user_proj_example.gds[diff]
gds/user_project_wrapper.gds[diff]
lef/user_proj_example.lef[diff]
lef/user_project_wrapper.lef[diff]
mag/user_proj_example.mag[diff]
mag/user_project_wrapper.mag[diff]
maglef/user_proj_example.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/user_proj_example/config.tcl[diff]
run_test.sh[diff]
signoff/user_proj_example/final_summary_report.csv[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spi/lvs/user_proj_example.spice[diff]
verilog/dv/Makefile[diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test1/la_test1.c[diff]
verilog/dv/la_test10/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/la_test10/la_test10.c[Added - diff]
verilog/dv/la_test10/la_test10_tb.v[Copied from verilog/dv/wb_port/wb_port_tb.v - diff]
verilog/dv/la_test11/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/la_test11/la_test11.c[Added - diff]
verilog/dv/la_test11/la_test11.gtkw[Added - diff]
verilog/dv/la_test11/la_test11_tb.v[Copied from verilog/dv/wb_port/wb_port_tb.v - diff]
verilog/dv/la_test2/la_test2.c[diff]
verilog/dv/la_test2/la_test2.gtkw[diff]
verilog/dv/la_test2/la_test2_tb.v[diff]
verilog/dv/la_test3/la_test3.c[diff]
verilog/dv/la_test4/la_test4.c[diff]
verilog/dv/la_test5/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/la_test5/la_test5.c[Added - diff]
verilog/dv/la_test5/la_test5.gtkw[Added - diff]
verilog/dv/la_test5/la_test5_tb.v[Copied from verilog/dv/wb_port/wb_port_tb.v - diff]
verilog/dv/la_test6/Makefile[Renamed from verilog/dv/wb_port/Makefile - diff]
verilog/dv/la_test6/la_test6.c[Added - diff]
verilog/dv/la_test6/la_test6.gtkw[Added - diff]
verilog/dv/la_test6/la_test6_tb.v[Added - diff]
verilog/dv/la_test7/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/la_test7/la_test7.c[Added - diff]
verilog/dv/la_test7/la_test7.gtkw[Added - diff]
verilog/dv/la_test7/la_test7_tb.v[Renamed from verilog/dv/wb_port/wb_port_tb.v - diff]
verilog/dv/la_test8/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/la_test8/la_test8.c[Added - diff]
verilog/dv/la_test8/la_test8.gtkw[Added - diff]
verilog/dv/la_test8/la_test8_tb.v[Copied from verilog/dv/wb_port/wb_port_tb.v - diff]
verilog/dv/la_test9/Makefile[Copied from verilog/dv/wb_port/Makefile - diff]
verilog/dv/la_test9/la_test9.c[Added - diff]
verilog/dv/la_test9/la_test9_tb.v[Added - diff]
verilog/dv/mprj_stimulus/Makefile[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_test1/wb_test1.c[diff]
verilog/dv/wb_test1/wb_test1_tb.v[diff]
verilog/dv/wb_test2/wb_test2.c[diff]
verilog/dv/wb_test3/wb_test3.c[diff]
verilog/gl/user_proj_example.v[diff]
verilog/rtl/ecc_registers/data_verificator.v[diff]
verilog/rtl/ecc_registers/parity_calculator.v[diff]
verilog/rtl/ecc_registers/register_data.v[diff]
verilog/rtl/ecc_registers/register_file.v[diff]
verilog/rtl/ecc_registers/state_counters.v[diff]
verilog/rtl/user_proj.v[diff]

67 files changed

tree: 594a05f3eaeae01ca3ecd8b34da3e3e880ed5484

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.