Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-027
/
5d7cfb44c302a8858b904040b6fdd0566bddcbf8
commit
5d7cfb44c302a8858b904040b6fdd0566bddcbf8
[
log
]
[
tgz
]
author
jaquerinte <ivanrodriguezferrandez@gmail.com>
Mon May 24 14:56:02 2021 +0200
committer
jaquerinte <ivanrodriguezferrandez@gmail.com>
Mon May 24 14:56:02 2021 +0200
tree
bcb5b2cb6be79000503279a455dba53d5c0b2478
parent
2e17032a427b49a9dbb1f79193314228c43de66e
[
diff
]
version 1.2 finish
def/user_proj_example.def
[
diff
]
def/user_project_wrapper.def
[
diff
]
gds/user_proj_example.gds
[
diff
]
gds/user_project_wrapper.gds
[
diff
]
lef/user_proj_example.lef
[
diff
]
lef/user_project_wrapper.lef
[
diff
]
mag/user_proj_example.mag
[
diff
]
mag/user_project_wrapper.mag
[
diff
]
maglef/user_proj_example.mag
[
diff
]
maglef/user_project_wrapper.mag
[
diff
]
openlane/user_proj_example/config.tcl
[
diff
]
signoff/user_proj_example/final_summary_report.csv
[
diff
]
signoff/user_project_wrapper/final_summary_report.csv
[
diff
]
spi/lvs/user_proj_example.spice
[
diff
]
verilog/gl/user_proj_example.v
[
diff
]
verilog/rtl/ecc_registers/decoder_output.v
[
diff
]
verilog/rtl/ecc_registers/register_data.v
[
diff
]
verilog/rtl/ecc_registers/register_file.v
[
diff
]
18 files changed
tree: bcb5b2cb6be79000503279a455dba53d5c0b2478
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
clean_run.sh
info.yaml
LICENSE
make_synthesis.sh
Makefile
README.md
run_test.sh
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.