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foss-eda-tools
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third_party
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shuttle
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sky130
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mpw-002
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slot-027
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05b24ae44e9b628adc3109e3d6d75b1506eab7d8
commit
05b24ae44e9b628adc3109e3d6d75b1506eab7d8
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author
jaquerinte <ivanrodriguezferrandez@gmail.com>
Thu Jun 17 11:50:48 2021 +0200
committer
jaquerinte <ivanrodriguezferrandez@gmail.com>
Thu Jun 17 11:50:48 2021 +0200
tree
e230ca5677b53549554d26bc1d26db84e5e334c5
parent
18d8a5bbf88c4530dec4d2a91944ad73b0566866
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final version ready for tape out
clean_run.sh
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def/user_proj_example.def.gz
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def/user_project_wrapper.def
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gds/user_proj_example.gds.gz
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gds/user_project_wrapper.gds.gz
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lef/user_proj_example.lef
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lef/user_project_wrapper.lef
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mag/user_proj_example.mag.gz
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mag/user_project_wrapper.mag
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maglef/user_proj_example.mag
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maglef/user_project_wrapper.mag
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openlane/user_proj_example/config.tcl
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openlane/user_project_wrapper/config.tcl
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signoff/user_proj_example/final_summary_report.csv
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signoff/user_project_wrapper/final_summary_report.csv
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spi/lvs/user_proj_example.spice
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spi/lvs/user_project_wrapper.spice
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verilog/dv/la_test1/Makefile
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verilog/gl/user_proj_example.v
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verilog/gl/user_project_wrapper.v
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verilog/rtl/uprj_netlists.v
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verilog/rtl/user_proj_example.v
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verilog/rtl/user_project_wrapper.v
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23 files changed
tree: e230ca5677b53549554d26bc1d26db84e5e334c5
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
clean_run.sh
info.yaml
LICENSE
make_synthesis.sh
Makefile
README.md
run_test.sh
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.
