| commit | 030d130d25dffd5ee11909efca9df1f4cffe6e52 | [log] [tgz] |
|---|---|---|
| author | jaquerinte <ivanrodriguezferrandez@gmail.com> | Tue May 18 20:53:48 2021 +0200 |
| committer | jaquerinte <ivanrodriguezferrandez@gmail.com> | Tue May 18 20:53:48 2021 +0200 |
| tree | 928a66d3a05f502c99946f3260fc836fea80fcf8 | |
| parent | 5eac7bd14d561de25cf850d20e853233ce5afed7 [diff] | |
| parent | 500ea5487451cb328f6cbd6d363ac28ce35dfaec [diff] |
Merge branch 'main' of https://github.com/jaquerinte/riscv_radiation_hard into main
The idea of this project is to design open source radiation harden techniques. For now the space industry is a very close source and restricted IP industry. But from ESA and his partners there is increasing interest in open source software and hardware for space use. So the main goal of the project is to implement some radiation harden features and test them under radiation to see how this techniques behave. Due to the nature of this project that is using a node that is close to the nodes use in this industry we will be easy to compare to current solutions.
One of the first things implemented is a 32 bit register file that has ECC implementation. In this case is implemented 1 bit correction and 2 bit detention.
For the of the code we use Hamming code for the implementation or the parity bits and correction. In this particularly case is implemented with 6 bits inside of the register (positions 1,2,4,8,16,32) and a extra bit at the last position of the 2 bit error detection.
The main code part is in the ecc_registers folder inside of the rtl folder. The user_proj.v contains only the connections to connect the project wrapper with the register file. The module works in a black box manner, the values are inserted to the module and you can ask for a value inside of the memory and the output is the value requested with a status signal that tells if the value is correct without modifications, the value has been corrected or if the value data is invalid. Is important to notice that if more that two bits are flip in the register value the system can not reliable determine if the value is incorrect.
The module is implemented with 32 bit word size and 8 registers. The counters are 32 bit counters.
clk_i: Clock signal for the module.
rst_i: Reset signal for the module, this signal clears all of the values for the internal register values and all of the counters.
data_to_register_i [31:0]: The 32 bit input value that will be store in the register file.
register_i [3:0]: Signal to select the register that the operation will be perform.
wregister_i: Signal to indicate that the operation that you want is to write the input data to a register.
rregister_i: Signal to indicate that the operation that you want is to read from the register file.
store_data_o [31:0]: The 32 bit value that was store in the register file
operation:result_o [1:0]. This is a two bit output that indicates the sate of the data.
Also some extra ports can be use in the case to add connection to a wishbone bus. For the current version the whisbone is only connected to the 32 bit counter that counts the number of 1 bit flip that have happened.
The ecc registers module is compose of a set of multiple sub-modules. The following image is a representation of the modules and how each one of them interconnect.
