commit	d12240ac9145e03ade410084c8a797f72f8a9ee5	[log] [tgz]
author	Baburaj <teche.raj2019@gmail.com>	Sun Jun 06 17:34:01 2021 +0530
committer	Baburaj <teche.raj2019@gmail.com>	Sun Jun 06 17:34:01 2021 +0530
tree	fed132700ad32bc1e6536aa847855b2bdbf7388a
parent	6c8c4032e0affe86a036024eaf1969ccac0ea8fb [diff]

 RTC Module from Opencores

verilog/rtl/rtc/hexmap.v[Added - diff]
verilog/rtl/rtc/rtcclock.v[Added - diff]
verilog/rtl/rtc/rtcdate.v[Added - diff]
verilog/rtl/rtc/rtcgps.v[Added - diff]
verilog/rtl/rtc/rtclight.v[Added - diff]

5 files changed

tree: fed132700ad32bc1e6536aa847855b2bdbf7388a

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.