commit	a3affbca0aeaceca9b1bc8d458f32f3acf70365a	[log] [tgz]
author	Baburaj <teche.raj2019@gmail.com>	Mon May 31 15:42:59 2021 +0530
committer	Baburaj <teche.raj2019@gmail.com>	Mon May 31 15:42:59 2021 +0530
tree	951ddf5c5f0a7772cd41dde7beb58b60b1e7cc13
parent	e12fd62d75f3dc1c5f881f2a00525d35b6fa4d7f [diff]

PWM RTL Code from opencores

verilog/rtl/pwm/PWM.v[Added - diff]
verilog/rtl/pwm/down_clocking_even.v[Added - diff]
verilog/rtl/pwm/down_clocking_odd.v[Added - diff]
verilog/rtl/pwm/minus_one.v[Added - diff]

4 files changed

tree: 951ddf5c5f0a7772cd41dde7beb58b60b1e7cc13

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.