Updated PID Module Verilog files
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 4ea25c6..caa7ec5 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -19,6 +19,10 @@
set ::env(VERILOG_FILES) "\
$script_dir/../../caravel/verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/pid/16x16bit_multiplier_pipelined.v \
+ $script_dir/../../verilog/rtl/pid/booth.v \
+ $script_dir/../../verilog/rtl/pid/CLA_fixed.v \
+ $script_dir/../../verilog/rtl/pid/PID.v \
$script_dir/../../verilog/rtl/user_proj_example.v"
set ::env(CLOCK_PORT) ""
