| commit | a9f0d7ddcdc63e811798fe8f84cc3c59054c05e1 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Tue Dec 28 01:36:05 2021 +0000 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Tue Dec 28 01:36:05 2021 +0000 |
| tree | 2dd1bdd9b947915132215f04bfdc8f4227e7908f | |
| parent | fb052d30e493765b11f64c2b9f11450e09379676 [diff] |
final gds & signoff results
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.
