commit	b9d3bd19efa397c5f1307727dc2b7589c7d1c817	[log] [tgz]
author	zeeshanrafique23 <zeeshanrafique23@gmail.com>	Fri Jun 25 21:29:09 2021 +0500
committer	zeeshanrafique23 <zeeshanrafique23@gmail.com>	Fri Jun 25 21:29:09 2021 +0500
tree	a4c16dace1273ffd63e7f0bbe7ab4ad654dcc615
parent	d3e050539b229d532a45c37a645482e081e344cc [diff]

updated files of mpw-two-tag form main

README.md[diff]
def/user_project_wrapper.def.gz[Added - diff]
gds/.magicrc[Added - diff]
gds/user_project_wrapper.gds.gz[diff]
images/gds.png[Added - diff]
info.yaml[diff]
lef/user_project_wrapper.lef[diff]
mag/user_project_wrapper.mag.gz[Added - diff]
maglef/user_project_wrapper.lef.mag[Added - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/interactive.tcl[Added - diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/gl/user_project_wrapper.v.gz[Added - diff]
verilog/rtl/DFFRAM.v[Added - diff]
verilog/rtl/azadi_soc_top_caravel.v[Added - diff]
verilog/rtl/azadi_soc_top_dffram.v[Added - diff]
verilog/rtl/azadi_soc_top_dffram_2kb.v[Added - diff]
verilog/rtl/azadi_soc_top_dffram_4kb.v[Added - diff]
verilog/rtl/azadi_soc_top_sram.v[Added - diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

22 files changed

tree: a4c16dace1273ffd63e7f0bbe7ab4ad654dcc615

README.md

Caravel User Project

Azadi RISC-V SoC

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.

Azadi SoC DFFRAM: Flattened with user_project_wrapper

azadi-gds