| commit | a64aa2d98d30ab8ff515da13873765581ac7baeb | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Wed Jul 21 09:37:10 2021 +0000 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Wed Jul 21 09:37:10 2021 +0000 |
| tree | c4b51e7892ecd3f79cc182a49b997599a5ec06cf | |
| parent | fc2aa4814fe1baf54e2ec0f33220f7ea8b1452a5 [diff] |
final gds & signoff results
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.
