commit 9645a180e3e730eaf6463cf9803950998cabd6bc
author Zeeshan Rafique <36025181+zeeshanrafique23@users.noreply.github.com> Sun Jul 11 00:17:58 2021 +0500
committer GitHub <noreply@github.com> Sun Jul 11 00:17:58 2021 +0500
tree 30f6317ef94b6e724467dccfcd17244bcfd854b2
parent 6debc45128189f12ff0c94a564152ab46eefb936
parent cb2bba5043ea3ffc243b006986cfa6eb6f9f89e8

Merge pull request #9 from zainrizwankhan/mpw-two

verilog/rtl/azadi_soc_top_caravel.v

diff --git a/verilog/rtl/azadi_soc_top_caravel.v b/verilog/rtl/azadi_soc_top_caravel.v
index f088012..ceab097 100644
--- a/verilog/rtl/azadi_soc_top_caravel.v
+++ b/verilog/rtl/azadi_soc_top_caravel.v
@@ -92,10 +92,11 @@
   assign io_out[4]     =  sclk_o;
   assign unused_02     =  io_in[4];
 
-  // UART 
-  assign io_oeb[5]     =  1'b1;
-  assign io_out[5]     =  1'b0;
+  // UART || GPIO 18
+  assign io_oeb[5]     =  ~gpio_oe[18];
+  assign io_out[5]     =  gpio_o[18];
   assign uart_rx       =  io_in[5];
+  assign gpio_i[18]    =  io_in[5];
 
   assign io_oeb[6]     =  1'b0;
   assign io_out[6]     =  uart_tx;
@@ -106,10 +107,10 @@
   assign io_out[7]     =  1'b0;
   assign prog          =  io_in[7];
 
-  // GPIO 0-18
-  assign io_oeb[25:8]  = ~gpio_oe[18:0];
-  assign gpio_i[18:0]  =  io_in  [25:8];
-  assign io_out[25:8]  =  gpio_o [18:0];
+  // GPIO 0-17
+  assign io_oeb[25:8]  = ~gpio_oe[17:0];
+  assign gpio_i[17:0]  =  io_in  [25:8];
+  assign io_out[25:8]  =  gpio_o [17:0];
 
   assign io_oeb[26]    = ~gpio_oe[31];
   assign gpio_i[31]    =  io_in  [26];