| commit | 872fa24f302cdba10bfdd0b426b9c7c07229d8e6 | [log] [tgz] |
|---|---|---|
| author | Zeeshan Rafique <36025181+zeeshanrafique23@users.noreply.github.com> | Sat Jun 26 09:04:49 2021 +0500 |
| committer | GitHub <noreply@github.com> | Sat Jun 26 09:04:49 2021 +0500 |
| tree | 750fe2e7fa452566525a7db4744665ea109c1d4b | |
| parent | 3b14e532fc2d53a127ade1d8f0973a4313d88187 [diff] | |
| parent | b3bf4d444a6900dc409da387def9a4be92a847bd [diff] |
Merge pull request #4 from zainrizwankhan/submission-mpw-two added initial DV setup for Azadi SoC
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.
