| commit | 3fc130efb026b85280e90e0a0a3007cb4efe9c89 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Tue Jul 27 19:49:32 2021 +0000 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Tue Jul 27 19:49:32 2021 +0000 |
| tree | 01f73434e4822e6ed71b0bf4371dc0e6c42f1560 | |
| parent | a64aa2d98d30ab8ff515da13873765581ac7baeb [diff] |
final gds & signoff results
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.
