| commit | 3cb0f7ada9cddf7b9de8c60028b92218a84f9b53 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Wed Dec 08 05:34:56 2021 +0000 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Wed Dec 08 05:34:56 2021 +0000 |
| tree | 042b52b0e74a8bdc4d7959034b17a3b3668b05be | |
| parent | 8af41f95bdafc9b13fd6ba4d2915270e4c2719f7 [diff] |
final gds & signoff results
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.
