| commit | 3b14e532fc2d53a127ade1d8f0973a4313d88187 | [log] [tgz] |
|---|---|---|
| author | Zeeshan Rafique <36025181+zeeshanrafique23@users.noreply.github.com> | Sat Jun 26 08:50:02 2021 +0500 |
| committer | GitHub <noreply@github.com> | Sat Jun 26 08:50:02 2021 +0500 |
| tree | 041ee2ae8037f07aed9b684f4cc45544299f67d2 | |
| parent | 445e0e659ee46287340d4fe2bee722a780ff6a21 [diff] | |
| parent | 99ca0fbf89e6231a1d5dce9bca45403a55dbc3fe [diff] |
Merge branch 'efabless:main' into submission-mpw-two
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.
