| commit | 31564e2ccd4fe376ae1ecaa193eebe1d98a49a78 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Mon Dec 06 04:02:21 2021 +0000 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Mon Dec 06 04:02:21 2021 +0000 |
| tree | 4d409947667b80fbf450b23ff52a956027e486cb | |
| parent | dcf4c4021ba05c09a1965ac5d5f38f6c3fbd6c16 [diff] |
final gds & signoff results
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.
